| 1 | /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
|---|---|
| 2 | |* *| |
| 3 | |* Machine Code Emitter *| |
| 4 | |* *| |
| 5 | |* Automatically generated file, do not edit! *| |
| 6 | |* *| |
| 7 | \*===----------------------------------------------------------------------===*/ |
| 8 | |
| 9 | uint64_t HexagonMCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI, |
| 10 | SmallVectorImpl<MCFixup> &Fixups, |
| 11 | const MCSubtargetInfo &STI) const { |
| 12 | static const uint64_t InstBits[] = { |
| 13 | UINT64_C(2357198976), // A2_abs |
| 14 | UINT64_C(2155872448), // A2_absp |
| 15 | UINT64_C(2357199008), // A2_abssat |
| 16 | UINT64_C(4076863488), // A2_add |
| 17 | UINT64_C(3577741408), // A2_addh_h16_hh |
| 18 | UINT64_C(3577741376), // A2_addh_h16_hl |
| 19 | UINT64_C(3577741344), // A2_addh_h16_lh |
| 20 | UINT64_C(3577741312), // A2_addh_h16_ll |
| 21 | UINT64_C(3577741536), // A2_addh_h16_sat_hh |
| 22 | UINT64_C(3577741504), // A2_addh_h16_sat_hl |
| 23 | UINT64_C(3577741472), // A2_addh_h16_sat_lh |
| 24 | UINT64_C(3577741440), // A2_addh_h16_sat_ll |
| 25 | UINT64_C(3573547072), // A2_addh_l16_hl |
| 26 | UINT64_C(3573547008), // A2_addh_l16_ll |
| 27 | UINT64_C(3573547200), // A2_addh_l16_sat_hl |
| 28 | UINT64_C(3573547136), // A2_addh_l16_sat_ll |
| 29 | UINT64_C(2952790016), // A2_addi |
| 30 | UINT64_C(3539992800), // A2_addp |
| 31 | UINT64_C(3546284192), // A2_addpsat |
| 32 | UINT64_C(4131389440), // A2_addsat |
| 33 | UINT64_C(3546284256), // A2_addsph |
| 34 | UINT64_C(3546284224), // A2_addspl |
| 35 | UINT64_C(4043309056), // A2_and |
| 36 | UINT64_C(1979711488), // A2_andir |
| 37 | UINT64_C(3554672640), // A2_andp |
| 38 | UINT64_C(1879048192), // A2_aslh |
| 39 | UINT64_C(1881145344), // A2_asrh |
| 40 | UINT64_C(4085252096), // A2_combine_hh |
| 41 | UINT64_C(4087349248), // A2_combine_hl |
| 42 | UINT64_C(4089446400), // A2_combine_lh |
| 43 | UINT64_C(4091543552), // A2_combine_ll |
| 44 | UINT64_C(2080374784), // A2_combineii |
| 45 | UINT64_C(4110417920), // A2_combinew |
| 46 | UINT64_C(3586129920), // A2_max |
| 47 | UINT64_C(3552575616), // A2_maxp |
| 48 | UINT64_C(3586130048), // A2_maxu |
| 49 | UINT64_C(3552575648), // A2_maxup |
| 50 | UINT64_C(3584032768), // A2_min |
| 51 | UINT64_C(3550478528), // A2_minp |
| 52 | UINT64_C(3584032896), // A2_minu |
| 53 | UINT64_C(3550478560), // A2_minup |
| 54 | UINT64_C(2155872416), // A2_negp |
| 55 | UINT64_C(2357199040), // A2_negsat |
| 56 | UINT64_C(2130706432), // A2_nop |
| 57 | UINT64_C(2155872384), // A2_notp |
| 58 | UINT64_C(4045406208), // A2_or |
| 59 | UINT64_C(1988100096), // A2_orir |
| 60 | UINT64_C(3554672704), // A2_orp |
| 61 | UINT64_C(4211081344), // A2_paddf |
| 62 | UINT64_C(4211089536), // A2_paddfnew |
| 63 | UINT64_C(1954545664), // A2_paddif |
| 64 | UINT64_C(1954553856), // A2_paddifnew |
| 65 | UINT64_C(1946157056), // A2_paddit |
| 66 | UINT64_C(1946165248), // A2_padditnew |
| 67 | UINT64_C(4211081216), // A2_paddt |
| 68 | UINT64_C(4211089408), // A2_paddtnew |
| 69 | UINT64_C(4177526912), // A2_pandf |
| 70 | UINT64_C(4177535104), // A2_pandfnew |
| 71 | UINT64_C(4177526784), // A2_pandt |
| 72 | UINT64_C(4177534976), // A2_pandtnew |
| 73 | UINT64_C(4179624064), // A2_porf |
| 74 | UINT64_C(4179632256), // A2_porfnew |
| 75 | UINT64_C(4179623936), // A2_port |
| 76 | UINT64_C(4179632128), // A2_portnew |
| 77 | UINT64_C(4213178496), // A2_psubf |
| 78 | UINT64_C(4213186688), // A2_psubfnew |
| 79 | UINT64_C(4213178368), // A2_psubt |
| 80 | UINT64_C(4213186560), // A2_psubtnew |
| 81 | UINT64_C(4183818368), // A2_pxorf |
| 82 | UINT64_C(4183826560), // A2_pxorfnew |
| 83 | UINT64_C(4183818240), // A2_pxort |
| 84 | UINT64_C(4183826432), // A2_pxortnew |
| 85 | UINT64_C(2294284320), // A2_roundsat |
| 86 | UINT64_C(2294284288), // A2_sat |
| 87 | UINT64_C(2361393376), // A2_satb |
| 88 | UINT64_C(2361393280), // A2_sath |
| 89 | UINT64_C(2361393344), // A2_satub |
| 90 | UINT64_C(2361393312), // A2_satuh |
| 91 | UINT64_C(4078960640), // A2_sub |
| 92 | UINT64_C(3579838560), // A2_subh_h16_hh |
| 93 | UINT64_C(3579838528), // A2_subh_h16_hl |
| 94 | UINT64_C(3579838496), // A2_subh_h16_lh |
| 95 | UINT64_C(3579838464), // A2_subh_h16_ll |
| 96 | UINT64_C(3579838688), // A2_subh_h16_sat_hh |
| 97 | UINT64_C(3579838656), // A2_subh_h16_sat_hl |
| 98 | UINT64_C(3579838624), // A2_subh_h16_sat_lh |
| 99 | UINT64_C(3579838592), // A2_subh_h16_sat_ll |
| 100 | UINT64_C(3575644224), // A2_subh_l16_hl |
| 101 | UINT64_C(3575644160), // A2_subh_l16_ll |
| 102 | UINT64_C(3575644352), // A2_subh_l16_sat_hl |
| 103 | UINT64_C(3575644288), // A2_subh_l16_sat_ll |
| 104 | UINT64_C(3542089952), // A2_subp |
| 105 | UINT64_C(1983905792), // A2_subri |
| 106 | UINT64_C(4139778048), // A2_subsat |
| 107 | UINT64_C(4127195136), // A2_svaddh |
| 108 | UINT64_C(4129292288), // A2_svaddhs |
| 109 | UINT64_C(4133486592), // A2_svadduhs |
| 110 | UINT64_C(4143972352), // A2_svavgh |
| 111 | UINT64_C(4146069504), // A2_svavghs |
| 112 | UINT64_C(4150263808), // A2_svnavgh |
| 113 | UINT64_C(4135583744), // A2_svsubh |
| 114 | UINT64_C(4137680896), // A2_svsubhs |
| 115 | UINT64_C(4141875200), // A2_svsubuhs |
| 116 | UINT64_C(2357199072), // A2_swiz |
| 117 | UINT64_C(1889533952), // A2_sxtb |
| 118 | UINT64_C(1893728256), // A2_sxth |
| 119 | UINT64_C(2218786816), // A2_sxtw |
| 120 | UINT64_C(1885339648), // A2_tfr |
| 121 | UINT64_C(1778384896), // A2_tfrcrr |
| 122 | UINT64_C(1914699776), // A2_tfrih |
| 123 | UINT64_C(1897922560), // A2_tfril |
| 124 | UINT64_C(1646264320), // A2_tfrrcr |
| 125 | UINT64_C(2013265920), // A2_tfrsi |
| 126 | UINT64_C(2151678080), // A2_vabsh |
| 127 | UINT64_C(2151678112), // A2_vabshsat |
| 128 | UINT64_C(2151678144), // A2_vabsw |
| 129 | UINT64_C(2151678176), // A2_vabswsat |
| 130 | UINT64_C(3539992640), // A2_vaddh |
| 131 | UINT64_C(3539992672), // A2_vaddhs |
| 132 | UINT64_C(3539992576), // A2_vaddub |
| 133 | UINT64_C(3539992608), // A2_vaddubs |
| 134 | UINT64_C(3539992704), // A2_vadduhs |
| 135 | UINT64_C(3539992736), // A2_vaddw |
| 136 | UINT64_C(3539992768), // A2_vaddws |
| 137 | UINT64_C(3544186944), // A2_vavgh |
| 138 | UINT64_C(3544187008), // A2_vavghcr |
| 139 | UINT64_C(3544186976), // A2_vavghr |
| 140 | UINT64_C(3544186880), // A2_vavgub |
| 141 | UINT64_C(3544186912), // A2_vavgubr |
| 142 | UINT64_C(3544187040), // A2_vavguh |
| 143 | UINT64_C(3544187072), // A2_vavguhr |
| 144 | UINT64_C(3546284128), // A2_vavguw |
| 145 | UINT64_C(3546284160), // A2_vavguwr |
| 146 | UINT64_C(3546284032), // A2_vavgw |
| 147 | UINT64_C(3546284096), // A2_vavgwcr |
| 148 | UINT64_C(3546284064), // A2_vavgwr |
| 149 | UINT64_C(3523215552), // A2_vcmpbeq |
| 150 | UINT64_C(3523215584), // A2_vcmpbgtu |
| 151 | UINT64_C(3523215456), // A2_vcmpheq |
| 152 | UINT64_C(3523215488), // A2_vcmphgt |
| 153 | UINT64_C(3523215520), // A2_vcmphgtu |
| 154 | UINT64_C(3523215360), // A2_vcmpweq |
| 155 | UINT64_C(3523215392), // A2_vcmpwgt |
| 156 | UINT64_C(3523215424), // A2_vcmpwgtu |
| 157 | UINT64_C(2155872480), // A2_vconj |
| 158 | UINT64_C(3552575680), // A2_vmaxb |
| 159 | UINT64_C(3552575520), // A2_vmaxh |
| 160 | UINT64_C(3552575488), // A2_vmaxub |
| 161 | UINT64_C(3552575552), // A2_vmaxuh |
| 162 | UINT64_C(3550478496), // A2_vmaxuw |
| 163 | UINT64_C(3552575584), // A2_vmaxw |
| 164 | UINT64_C(3552575712), // A2_vminb |
| 165 | UINT64_C(3550478368), // A2_vminh |
| 166 | UINT64_C(3550478336), // A2_vminub |
| 167 | UINT64_C(3550478400), // A2_vminuh |
| 168 | UINT64_C(3550478464), // A2_vminuw |
| 169 | UINT64_C(3550478432), // A2_vminw |
| 170 | UINT64_C(3548381184), // A2_vnavgh |
| 171 | UINT64_C(3548381248), // A2_vnavghcr |
| 172 | UINT64_C(3548381216), // A2_vnavghr |
| 173 | UINT64_C(3548381280), // A2_vnavgw |
| 174 | UINT64_C(3548381376), // A2_vnavgwcr |
| 175 | UINT64_C(3548381312), // A2_vnavgwr |
| 176 | UINT64_C(3896508448), // A2_vraddub |
| 177 | UINT64_C(3930062880), // A2_vraddub_acc |
| 178 | UINT64_C(3896508480), // A2_vrsadub |
| 179 | UINT64_C(3930062912), // A2_vrsadub_acc |
| 180 | UINT64_C(3542089792), // A2_vsubh |
| 181 | UINT64_C(3542089824), // A2_vsubhs |
| 182 | UINT64_C(3542089728), // A2_vsubub |
| 183 | UINT64_C(3542089760), // A2_vsububs |
| 184 | UINT64_C(3542089856), // A2_vsubuhs |
| 185 | UINT64_C(3542089888), // A2_vsubw |
| 186 | UINT64_C(3542089920), // A2_vsubws |
| 187 | UINT64_C(4049600512), // A2_xor |
| 188 | UINT64_C(3554672768), // A2_xorp |
| 189 | UINT64_C(1891631104), // A2_zxth |
| 190 | UINT64_C(3267362816), // A4_addp_c |
| 191 | UINT64_C(4051697664), // A4_andn |
| 192 | UINT64_C(3554672672), // A4_andnp |
| 193 | UINT64_C(3558866944), // A4_bitsplit |
| 194 | UINT64_C(2294284416), // A4_bitspliti |
| 195 | UINT64_C(3523223712), // A4_boundscheck_hi |
| 196 | UINT64_C(3523223680), // A4_boundscheck_lo |
| 197 | UINT64_C(3351249088), // A4_cmpbeq |
| 198 | UINT64_C(3707764736), // A4_cmpbeqi |
| 199 | UINT64_C(3351248960), // A4_cmpbgt |
| 200 | UINT64_C(3709861888), // A4_cmpbgti |
| 201 | UINT64_C(3351249120), // A4_cmpbgtu |
| 202 | UINT64_C(3711959040), // A4_cmpbgtui |
| 203 | UINT64_C(3351248992), // A4_cmpheq |
| 204 | UINT64_C(3707764744), // A4_cmpheqi |
| 205 | UINT64_C(3351249024), // A4_cmphgt |
| 206 | UINT64_C(3709861896), // A4_cmphgti |
| 207 | UINT64_C(3351249056), // A4_cmphgtu |
| 208 | UINT64_C(3711959048), // A4_cmphgtui |
| 209 | UINT64_C(2088763392), // A4_combineii |
| 210 | UINT64_C(1931485184), // A4_combineir |
| 211 | UINT64_C(1929388032), // A4_combineri |
| 212 | UINT64_C(2363490304), // A4_cround_ri |
| 213 | UINT64_C(3334471680), // A4_cround_rr |
| 214 | UINT64_C(0), // A4_ext |
| 215 | UINT64_C(3554672864), // A4_modwrapu |
| 216 | UINT64_C(4053794816), // A4_orn |
| 217 | UINT64_C(3554672736), // A4_ornp |
| 218 | UINT64_C(1879058432), // A4_paslhf |
| 219 | UINT64_C(1879059456), // A4_paslhfnew |
| 220 | UINT64_C(1879056384), // A4_paslht |
| 221 | UINT64_C(1879057408), // A4_paslhtnew |
| 222 | UINT64_C(1881155584), // A4_pasrhf |
| 223 | UINT64_C(1881156608), // A4_pasrhfnew |
| 224 | UINT64_C(1881153536), // A4_pasrht |
| 225 | UINT64_C(1881154560), // A4_pasrhtnew |
| 226 | UINT64_C(1889544192), // A4_psxtbf |
| 227 | UINT64_C(1889545216), // A4_psxtbfnew |
| 228 | UINT64_C(1889542144), // A4_psxtbt |
| 229 | UINT64_C(1889543168), // A4_psxtbtnew |
| 230 | UINT64_C(1893738496), // A4_psxthf |
| 231 | UINT64_C(1893739520), // A4_psxthfnew |
| 232 | UINT64_C(1893736448), // A4_psxtht |
| 233 | UINT64_C(1893737472), // A4_psxthtnew |
| 234 | UINT64_C(1887447040), // A4_pzxtbf |
| 235 | UINT64_C(1887448064), // A4_pzxtbfnew |
| 236 | UINT64_C(1887444992), // A4_pzxtbt |
| 237 | UINT64_C(1887446016), // A4_pzxtbtnew |
| 238 | UINT64_C(1891641344), // A4_pzxthf |
| 239 | UINT64_C(1891642368), // A4_pzxthfnew |
| 240 | UINT64_C(1891639296), // A4_pzxtht |
| 241 | UINT64_C(1891640320), // A4_pzxthtnew |
| 242 | UINT64_C(4081057792), // A4_rcmpeq |
| 243 | UINT64_C(1933582336), // A4_rcmpeqi |
| 244 | UINT64_C(4083154944), // A4_rcmpneq |
| 245 | UINT64_C(1935679488), // A4_rcmpneqi |
| 246 | UINT64_C(2363490432), // A4_round_ri |
| 247 | UINT64_C(2363490496), // A4_round_ri_sat |
| 248 | UINT64_C(3334471808), // A4_round_rr |
| 249 | UINT64_C(3334471872), // A4_round_rr_sat |
| 250 | UINT64_C(3269459968), // A4_subp_c |
| 251 | UINT64_C(1744830464), // A4_tfrcpp |
| 252 | UINT64_C(1663041536), // A4_tfrpcp |
| 253 | UINT64_C(3523223648), // A4_tlbmatch |
| 254 | UINT64_C(3523223552), // A4_vcmpbeq_any |
| 255 | UINT64_C(3690987520), // A4_vcmpbeqi |
| 256 | UINT64_C(3523223616), // A4_vcmpbgt |
| 257 | UINT64_C(3693084672), // A4_vcmpbgti |
| 258 | UINT64_C(3695181824), // A4_vcmpbgtui |
| 259 | UINT64_C(3690987528), // A4_vcmpheqi |
| 260 | UINT64_C(3693084680), // A4_vcmphgti |
| 261 | UINT64_C(3695181832), // A4_vcmphgtui |
| 262 | UINT64_C(3690987536), // A4_vcmpweqi |
| 263 | UINT64_C(3693084688), // A4_vcmpwgti |
| 264 | UINT64_C(3695181840), // A4_vcmpwgtui |
| 265 | UINT64_C(3407872032), // A4_vrmaxh |
| 266 | UINT64_C(3407880224), // A4_vrmaxuh |
| 267 | UINT64_C(3407880256), // A4_vrmaxuw |
| 268 | UINT64_C(3407872064), // A4_vrmaxw |
| 269 | UINT64_C(3407872160), // A4_vrminh |
| 270 | UINT64_C(3407880352), // A4_vrminuh |
| 271 | UINT64_C(3407880384), // A4_vrminuw |
| 272 | UINT64_C(3407872192), // A4_vrminw |
| 273 | UINT64_C(3936354304), // A5_ACS |
| 274 | UINT64_C(3242197024), // A5_vaddhubs |
| 275 | UINT64_C(3523223584), // A6_vcmpbeq_notany |
| 276 | UINT64_C(3940548608), // A6_vminub_RdP |
| 277 | UINT64_C(2294284448), // A7_clip |
| 278 | UINT64_C(2363490368), // A7_croundd_ri |
| 279 | UINT64_C(3334471744), // A7_croundd_rr |
| 280 | UINT64_C(2294284480), // A7_vclip |
| 281 | UINT64_C(1805647872), // C2_all8 |
| 282 | UINT64_C(1795162112), // C2_and |
| 283 | UINT64_C(1801453568), // C2_andn |
| 284 | UINT64_C(1803550720), // C2_any8 |
| 285 | UINT64_C(3347054592), // C2_bitsclr |
| 286 | UINT64_C(2239758336), // C2_bitsclri |
| 287 | UINT64_C(3342860288), // C2_bitsset |
| 288 | UINT64_C(4244635776), // C2_ccombinewf |
| 289 | UINT64_C(4244643968), // C2_ccombinewnewf |
| 290 | UINT64_C(4244643840), // C2_ccombinewnewt |
| 291 | UINT64_C(4244635648), // C2_ccombinewt |
| 292 | UINT64_C(2122317824), // C2_cmoveif |
| 293 | UINT64_C(2113929216), // C2_cmoveit |
| 294 | UINT64_C(2122326016), // C2_cmovenewif |
| 295 | UINT64_C(2113937408), // C2_cmovenewit |
| 296 | UINT64_C(4060086272), // C2_cmpeq |
| 297 | UINT64_C(1962934272), // C2_cmpeqi |
| 298 | UINT64_C(3531603968), // C2_cmpeqp |
| 299 | UINT64_C(4064280576), // C2_cmpgt |
| 300 | UINT64_C(1967128576), // C2_cmpgti |
| 301 | UINT64_C(3531604032), // C2_cmpgtp |
| 302 | UINT64_C(4066377728), // C2_cmpgtu |
| 303 | UINT64_C(1971322880), // C2_cmpgtui |
| 304 | UINT64_C(3531604096), // C2_cmpgtup |
| 305 | UINT64_C(2248146944), // C2_mask |
| 306 | UINT64_C(4093640704), // C2_mux |
| 307 | UINT64_C(2046820352), // C2_muxii |
| 308 | UINT64_C(1929379840), // C2_muxir |
| 309 | UINT64_C(1937768448), // C2_muxri |
| 310 | UINT64_C(1807745024), // C2_not |
| 311 | UINT64_C(1797259264), // C2_or |
| 312 | UINT64_C(1809842176), // C2_orn |
| 313 | UINT64_C(2302672896), // C2_tfrpr |
| 314 | UINT64_C(2235564032), // C2_tfrrp |
| 315 | UINT64_C(2298478592), // C2_vitpack |
| 316 | UINT64_C(3506438144), // C2_vmux |
| 317 | UINT64_C(1799356416), // C2_xor |
| 318 | UINT64_C(1783169024), // C4_addipc |
| 319 | UINT64_C(1796210688), // C4_and_and |
| 320 | UINT64_C(1804599296), // C4_and_andn |
| 321 | UINT64_C(1798307840), // C4_and_or |
| 322 | UINT64_C(1806696448), // C4_and_orn |
| 323 | UINT64_C(4064280592), // C4_cmplte |
| 324 | UINT64_C(1967128592), // C4_cmpltei |
| 325 | UINT64_C(4066377744), // C4_cmplteu |
| 326 | UINT64_C(1971322896), // C4_cmplteui |
| 327 | UINT64_C(4060086288), // C4_cmpneq |
| 328 | UINT64_C(1962934288), // C4_cmpneqi |
| 329 | UINT64_C(1795170448), // C4_fastcorner9 |
| 330 | UINT64_C(1796219024), // C4_fastcorner9_not |
| 331 | UINT64_C(3349151744), // C4_nbitsclr |
| 332 | UINT64_C(2241855488), // C4_nbitsclri |
| 333 | UINT64_C(3344957440), // C4_nbitsset |
| 334 | UINT64_C(1800404992), // C4_or_and |
| 335 | UINT64_C(1808793600), // C4_or_andn |
| 336 | UINT64_C(1802502144), // C4_or_or |
| 337 | UINT64_C(1810890752), // C4_or_orn |
| 338 | UINT64_C(1509949440), // CALLProfile |
| 339 | UINT64_C(0), // CONST32 |
| 340 | UINT64_C(0), // CONST64 |
| 341 | UINT64_C(0), // DuplexIClass0 |
| 342 | UINT64_C(8192), // DuplexIClass1 |
| 343 | UINT64_C(536870912), // DuplexIClass2 |
| 344 | UINT64_C(536879104), // DuplexIClass3 |
| 345 | UINT64_C(1073741824), // DuplexIClass4 |
| 346 | UINT64_C(1073750016), // DuplexIClass5 |
| 347 | UINT64_C(1610612736), // DuplexIClass6 |
| 348 | UINT64_C(1610620928), // DuplexIClass7 |
| 349 | UINT64_C(2147483648), // DuplexIClass8 |
| 350 | UINT64_C(2147491840), // DuplexIClass9 |
| 351 | UINT64_C(2684354560), // DuplexIClassA |
| 352 | UINT64_C(2684362752), // DuplexIClassB |
| 353 | UINT64_C(3221225472), // DuplexIClassC |
| 354 | UINT64_C(3221233664), // DuplexIClassD |
| 355 | UINT64_C(3758096384), // DuplexIClassE |
| 356 | UINT64_C(3758104576), // DuplexIClassF |
| 357 | UINT64_C(1384120320), // EH_RETURN_JMPR |
| 358 | UINT64_C(2162163808), // F2_conv_d2df |
| 359 | UINT64_C(2285895712), // F2_conv_d2sf |
| 360 | UINT64_C(2162163712), // F2_conv_df2d |
| 361 | UINT64_C(2162163904), // F2_conv_df2d_chop |
| 362 | UINT64_C(2281701408), // F2_conv_df2sf |
| 363 | UINT64_C(2162163744), // F2_conv_df2ud |
| 364 | UINT64_C(2162163936), // F2_conv_df2ud_chop |
| 365 | UINT64_C(2287992864), // F2_conv_df2uw |
| 366 | UINT64_C(2292187168), // F2_conv_df2uw_chop |
| 367 | UINT64_C(2290090016), // F2_conv_df2w |
| 368 | UINT64_C(2296381472), // F2_conv_df2w_chop |
| 369 | UINT64_C(2222981248), // F2_conv_sf2d |
| 370 | UINT64_C(2222981312), // F2_conv_sf2d_chop |
| 371 | UINT64_C(2222981120), // F2_conv_sf2df |
| 372 | UINT64_C(2222981216), // F2_conv_sf2ud |
| 373 | UINT64_C(2222981280), // F2_conv_sf2ud_chop |
| 374 | UINT64_C(2338324480), // F2_conv_sf2uw |
| 375 | UINT64_C(2338324512), // F2_conv_sf2uw_chop |
| 376 | UINT64_C(2340421632), // F2_conv_sf2w |
| 377 | UINT64_C(2340421664), // F2_conv_sf2w_chop |
| 378 | UINT64_C(2162163776), // F2_conv_ud2df |
| 379 | UINT64_C(2283798560), // F2_conv_ud2sf |
| 380 | UINT64_C(2222981152), // F2_conv_uw2df |
| 381 | UINT64_C(2334130176), // F2_conv_uw2sf |
| 382 | UINT64_C(2222981184), // F2_conv_w2df |
| 383 | UINT64_C(2336227328), // F2_conv_w2sf |
| 384 | UINT64_C(3892314208), // F2_dfadd |
| 385 | UINT64_C(3699376144), // F2_dfclass |
| 386 | UINT64_C(3537895424), // F2_dfcmpeq |
| 387 | UINT64_C(3537895488), // F2_dfcmpge |
| 388 | UINT64_C(3537895456), // F2_dfcmpgt |
| 389 | UINT64_C(3537895520), // F2_dfcmpuo |
| 390 | UINT64_C(3644850176), // F2_dfimm_n |
| 391 | UINT64_C(3640655872), // F2_dfimm_p |
| 392 | UINT64_C(3894411360), // F2_dfmax |
| 393 | UINT64_C(3904897120), // F2_dfmin |
| 394 | UINT64_C(3896508512), // F2_dfmpyfix |
| 395 | UINT64_C(3934257248), // F2_dfmpyhh |
| 396 | UINT64_C(3925868640), // F2_dfmpylh |
| 397 | UINT64_C(3902799968), // F2_dfmpyll |
| 398 | UINT64_C(3900702816), // F2_dfsub |
| 399 | UINT64_C(3942645760), // F2_sfadd |
| 400 | UINT64_C(2246049792), // F2_sfclass |
| 401 | UINT64_C(3353346144), // F2_sfcmpeq |
| 402 | UINT64_C(3353346048), // F2_sfcmpge |
| 403 | UINT64_C(3353346176), // F2_sfcmpgt |
| 404 | UINT64_C(3353346080), // F2_sfcmpuo |
| 405 | UINT64_C(3955228704), // F2_sffixupd |
| 406 | UINT64_C(3955228672), // F2_sffixupn |
| 407 | UINT64_C(2342518784), // F2_sffixupr |
| 408 | UINT64_C(4009754752), // F2_sffma |
| 409 | UINT64_C(4009754816), // F2_sffma_lib |
| 410 | UINT64_C(4016046208), // F2_sffma_sc |
| 411 | UINT64_C(4009754784), // F2_sffms |
| 412 | UINT64_C(4009754848), // F2_sffms_lib |
| 413 | UINT64_C(3594518528), // F2_sfimm_n |
| 414 | UINT64_C(3590324224), // F2_sfimm_p |
| 415 | UINT64_C(2346713088), // F2_sfinvsqrta |
| 416 | UINT64_C(3951034368), // F2_sfmax |
| 417 | UINT64_C(3951034400), // F2_sfmin |
| 418 | UINT64_C(3946840064), // F2_sfmpy |
| 419 | UINT64_C(3957325952), // F2_sfrecipa |
| 420 | UINT64_C(3942645792), // F2_sfsub |
| 421 | UINT64_C(1746927616), // G4_tfrgcpp |
| 422 | UINT64_C(1780482048), // G4_tfrgcrr |
| 423 | UINT64_C(1660944384), // G4_tfrgpcp |
| 424 | UINT64_C(1644167168), // G4_tfrgrcr |
| 425 | UINT64_C(35651584), // HI |
| 426 | UINT64_C(1509949440), // J2_call |
| 427 | UINT64_C(1562378240), // J2_callf |
| 428 | UINT64_C(1352663040), // J2_callr |
| 429 | UINT64_C(1361051648), // J2_callrf |
| 430 | UINT64_C(1354760192), // J2_callrh |
| 431 | UINT64_C(1358954496), // J2_callrt |
| 432 | UINT64_C(1560281088), // J2_callt |
| 433 | UINT64_C(1476395008), // J2_jump |
| 434 | UINT64_C(1545601024), // J2_jumpf |
| 435 | UINT64_C(1545603072), // J2_jumpfnew |
| 436 | UINT64_C(1545607168), // J2_jumpfnewpt |
| 437 | UINT64_C(1545605120), // J2_jumpfpt |
| 438 | UINT64_C(1384120320), // J2_jumpr |
| 439 | UINT64_C(1398800384), // J2_jumprf |
| 440 | UINT64_C(1398802432), // J2_jumprfnew |
| 441 | UINT64_C(1398806528), // J2_jumprfnewpt |
| 442 | UINT64_C(1398804480), // J2_jumprfpt |
| 443 | UINT64_C(1631584256), // J2_jumprgtez |
| 444 | UINT64_C(1631588352), // J2_jumprgtezpt |
| 445 | UINT64_C(1388314624), // J2_jumprh |
| 446 | UINT64_C(1639972864), // J2_jumprltez |
| 447 | UINT64_C(1639976960), // J2_jumprltezpt |
| 448 | UINT64_C(1635778560), // J2_jumprnz |
| 449 | UINT64_C(1635782656), // J2_jumprnzpt |
| 450 | UINT64_C(1396703232), // J2_jumprt |
| 451 | UINT64_C(1396705280), // J2_jumprtnew |
| 452 | UINT64_C(1396709376), // J2_jumprtnewpt |
| 453 | UINT64_C(1396707328), // J2_jumprtpt |
| 454 | UINT64_C(1627389952), // J2_jumprz |
| 455 | UINT64_C(1627394048), // J2_jumprzpt |
| 456 | UINT64_C(1543503872), // J2_jumpt |
| 457 | UINT64_C(1543505920), // J2_jumptnew |
| 458 | UINT64_C(1543510016), // J2_jumptnewpt |
| 459 | UINT64_C(1543507968), // J2_jumptpt |
| 460 | UINT64_C(1761607680), // J2_loop0i |
| 461 | UINT64_C(1761607680), // J2_loop0iext |
| 462 | UINT64_C(1610612736), // J2_loop0r |
| 463 | UINT64_C(1610612736), // J2_loop0rext |
| 464 | UINT64_C(1763704832), // J2_loop1i |
| 465 | UINT64_C(1763704832), // J2_loop1iext |
| 466 | UINT64_C(1612709888), // J2_loop1r |
| 467 | UINT64_C(1612709888), // J2_loop1rext |
| 468 | UINT64_C(1413480448), // J2_pause |
| 469 | UINT64_C(1772093440), // J2_ploop1si |
| 470 | UINT64_C(1621098496), // J2_ploop1sr |
| 471 | UINT64_C(1774190592), // J2_ploop2si |
| 472 | UINT64_C(1623195648), // J2_ploop2sr |
| 473 | UINT64_C(1776287744), // J2_ploop3si |
| 474 | UINT64_C(1625292800), // J2_ploop3sr |
| 475 | UINT64_C(1474297856), // J2_rte |
| 476 | UINT64_C(1409286144), // J2_trap0 |
| 477 | UINT64_C(1417674752), // J2_trap1 |
| 478 | UINT64_C(1474301952), // J2_unpause |
| 479 | UINT64_C(541065216), // J4_cmpeq_f_jumpnv_nt |
| 480 | UINT64_C(541073408), // J4_cmpeq_f_jumpnv_t |
| 481 | UINT64_C(339738624), // J4_cmpeq_fp0_jump_nt |
| 482 | UINT64_C(339746816), // J4_cmpeq_fp0_jump_t |
| 483 | UINT64_C(339742720), // J4_cmpeq_fp1_jump_nt |
| 484 | UINT64_C(339750912), // J4_cmpeq_fp1_jump_t |
| 485 | UINT64_C(536870912), // J4_cmpeq_t_jumpnv_nt |
| 486 | UINT64_C(536879104), // J4_cmpeq_t_jumpnv_t |
| 487 | UINT64_C(335544320), // J4_cmpeq_tp0_jump_nt |
| 488 | UINT64_C(335552512), // J4_cmpeq_tp0_jump_t |
| 489 | UINT64_C(335548416), // J4_cmpeq_tp1_jump_nt |
| 490 | UINT64_C(335556608), // J4_cmpeq_tp1_jump_t |
| 491 | UINT64_C(608174080), // J4_cmpeqi_f_jumpnv_nt |
| 492 | UINT64_C(608182272), // J4_cmpeqi_f_jumpnv_t |
| 493 | UINT64_C(272629760), // J4_cmpeqi_fp0_jump_nt |
| 494 | UINT64_C(272637952), // J4_cmpeqi_fp0_jump_t |
| 495 | UINT64_C(306184192), // J4_cmpeqi_fp1_jump_nt |
| 496 | UINT64_C(306192384), // J4_cmpeqi_fp1_jump_t |
| 497 | UINT64_C(603979776), // J4_cmpeqi_t_jumpnv_nt |
| 498 | UINT64_C(603987968), // J4_cmpeqi_t_jumpnv_t |
| 499 | UINT64_C(268435456), // J4_cmpeqi_tp0_jump_nt |
| 500 | UINT64_C(268443648), // J4_cmpeqi_tp0_jump_t |
| 501 | UINT64_C(301989888), // J4_cmpeqi_tp1_jump_nt |
| 502 | UINT64_C(301998080), // J4_cmpeqi_tp1_jump_t |
| 503 | UINT64_C(641728512), // J4_cmpeqn1_f_jumpnv_nt |
| 504 | UINT64_C(641736704), // J4_cmpeqn1_f_jumpnv_t |
| 505 | UINT64_C(297795584), // J4_cmpeqn1_fp0_jump_nt |
| 506 | UINT64_C(297803776), // J4_cmpeqn1_fp0_jump_t |
| 507 | UINT64_C(331350016), // J4_cmpeqn1_fp1_jump_nt |
| 508 | UINT64_C(331358208), // J4_cmpeqn1_fp1_jump_t |
| 509 | UINT64_C(637534208), // J4_cmpeqn1_t_jumpnv_nt |
| 510 | UINT64_C(637542400), // J4_cmpeqn1_t_jumpnv_t |
| 511 | UINT64_C(293601280), // J4_cmpeqn1_tp0_jump_nt |
| 512 | UINT64_C(293609472), // J4_cmpeqn1_tp0_jump_t |
| 513 | UINT64_C(327155712), // J4_cmpeqn1_tp1_jump_nt |
| 514 | UINT64_C(327163904), // J4_cmpeqn1_tp1_jump_t |
| 515 | UINT64_C(549453824), // J4_cmpgt_f_jumpnv_nt |
| 516 | UINT64_C(549462016), // J4_cmpgt_f_jumpnv_t |
| 517 | UINT64_C(348127232), // J4_cmpgt_fp0_jump_nt |
| 518 | UINT64_C(348135424), // J4_cmpgt_fp0_jump_t |
| 519 | UINT64_C(348131328), // J4_cmpgt_fp1_jump_nt |
| 520 | UINT64_C(348139520), // J4_cmpgt_fp1_jump_t |
| 521 | UINT64_C(545259520), // J4_cmpgt_t_jumpnv_nt |
| 522 | UINT64_C(545267712), // J4_cmpgt_t_jumpnv_t |
| 523 | UINT64_C(343932928), // J4_cmpgt_tp0_jump_nt |
| 524 | UINT64_C(343941120), // J4_cmpgt_tp0_jump_t |
| 525 | UINT64_C(343937024), // J4_cmpgt_tp1_jump_nt |
| 526 | UINT64_C(343945216), // J4_cmpgt_tp1_jump_t |
| 527 | UINT64_C(616562688), // J4_cmpgti_f_jumpnv_nt |
| 528 | UINT64_C(616570880), // J4_cmpgti_f_jumpnv_t |
| 529 | UINT64_C(281018368), // J4_cmpgti_fp0_jump_nt |
| 530 | UINT64_C(281026560), // J4_cmpgti_fp0_jump_t |
| 531 | UINT64_C(314572800), // J4_cmpgti_fp1_jump_nt |
| 532 | UINT64_C(314580992), // J4_cmpgti_fp1_jump_t |
| 533 | UINT64_C(612368384), // J4_cmpgti_t_jumpnv_nt |
| 534 | UINT64_C(612376576), // J4_cmpgti_t_jumpnv_t |
| 535 | UINT64_C(276824064), // J4_cmpgti_tp0_jump_nt |
| 536 | UINT64_C(276832256), // J4_cmpgti_tp0_jump_t |
| 537 | UINT64_C(310378496), // J4_cmpgti_tp1_jump_nt |
| 538 | UINT64_C(310386688), // J4_cmpgti_tp1_jump_t |
| 539 | UINT64_C(650117120), // J4_cmpgtn1_f_jumpnv_nt |
| 540 | UINT64_C(650125312), // J4_cmpgtn1_f_jumpnv_t |
| 541 | UINT64_C(297795840), // J4_cmpgtn1_fp0_jump_nt |
| 542 | UINT64_C(297804032), // J4_cmpgtn1_fp0_jump_t |
| 543 | UINT64_C(331350272), // J4_cmpgtn1_fp1_jump_nt |
| 544 | UINT64_C(331358464), // J4_cmpgtn1_fp1_jump_t |
| 545 | UINT64_C(645922816), // J4_cmpgtn1_t_jumpnv_nt |
| 546 | UINT64_C(645931008), // J4_cmpgtn1_t_jumpnv_t |
| 547 | UINT64_C(293601536), // J4_cmpgtn1_tp0_jump_nt |
| 548 | UINT64_C(293609728), // J4_cmpgtn1_tp0_jump_t |
| 549 | UINT64_C(327155968), // J4_cmpgtn1_tp1_jump_nt |
| 550 | UINT64_C(327164160), // J4_cmpgtn1_tp1_jump_t |
| 551 | UINT64_C(557842432), // J4_cmpgtu_f_jumpnv_nt |
| 552 | UINT64_C(557850624), // J4_cmpgtu_f_jumpnv_t |
| 553 | UINT64_C(356515840), // J4_cmpgtu_fp0_jump_nt |
| 554 | UINT64_C(356524032), // J4_cmpgtu_fp0_jump_t |
| 555 | UINT64_C(356519936), // J4_cmpgtu_fp1_jump_nt |
| 556 | UINT64_C(356528128), // J4_cmpgtu_fp1_jump_t |
| 557 | UINT64_C(553648128), // J4_cmpgtu_t_jumpnv_nt |
| 558 | UINT64_C(553656320), // J4_cmpgtu_t_jumpnv_t |
| 559 | UINT64_C(352321536), // J4_cmpgtu_tp0_jump_nt |
| 560 | UINT64_C(352329728), // J4_cmpgtu_tp0_jump_t |
| 561 | UINT64_C(352325632), // J4_cmpgtu_tp1_jump_nt |
| 562 | UINT64_C(352333824), // J4_cmpgtu_tp1_jump_t |
| 563 | UINT64_C(624951296), // J4_cmpgtui_f_jumpnv_nt |
| 564 | UINT64_C(624959488), // J4_cmpgtui_f_jumpnv_t |
| 565 | UINT64_C(289406976), // J4_cmpgtui_fp0_jump_nt |
| 566 | UINT64_C(289415168), // J4_cmpgtui_fp0_jump_t |
| 567 | UINT64_C(322961408), // J4_cmpgtui_fp1_jump_nt |
| 568 | UINT64_C(322969600), // J4_cmpgtui_fp1_jump_t |
| 569 | UINT64_C(620756992), // J4_cmpgtui_t_jumpnv_nt |
| 570 | UINT64_C(620765184), // J4_cmpgtui_t_jumpnv_t |
| 571 | UINT64_C(285212672), // J4_cmpgtui_tp0_jump_nt |
| 572 | UINT64_C(285220864), // J4_cmpgtui_tp0_jump_t |
| 573 | UINT64_C(318767104), // J4_cmpgtui_tp1_jump_nt |
| 574 | UINT64_C(318775296), // J4_cmpgtui_tp1_jump_t |
| 575 | UINT64_C(566231040), // J4_cmplt_f_jumpnv_nt |
| 576 | UINT64_C(566239232), // J4_cmplt_f_jumpnv_t |
| 577 | UINT64_C(562036736), // J4_cmplt_t_jumpnv_nt |
| 578 | UINT64_C(562044928), // J4_cmplt_t_jumpnv_t |
| 579 | UINT64_C(574619648), // J4_cmpltu_f_jumpnv_nt |
| 580 | UINT64_C(574627840), // J4_cmpltu_f_jumpnv_t |
| 581 | UINT64_C(570425344), // J4_cmpltu_t_jumpnv_nt |
| 582 | UINT64_C(570433536), // J4_cmpltu_t_jumpnv_t |
| 583 | UINT64_C(1386217472), // J4_hintjumpr |
| 584 | UINT64_C(369098752), // J4_jumpseti |
| 585 | UINT64_C(385875968), // J4_jumpsetr |
| 586 | UINT64_C(633339904), // J4_tstbit0_f_jumpnv_nt |
| 587 | UINT64_C(633348096), // J4_tstbit0_f_jumpnv_t |
| 588 | UINT64_C(297796352), // J4_tstbit0_fp0_jump_nt |
| 589 | UINT64_C(297804544), // J4_tstbit0_fp0_jump_t |
| 590 | UINT64_C(331350784), // J4_tstbit0_fp1_jump_nt |
| 591 | UINT64_C(331358976), // J4_tstbit0_fp1_jump_t |
| 592 | UINT64_C(629145600), // J4_tstbit0_t_jumpnv_nt |
| 593 | UINT64_C(629153792), // J4_tstbit0_t_jumpnv_t |
| 594 | UINT64_C(293602048), // J4_tstbit0_tp0_jump_nt |
| 595 | UINT64_C(293610240), // J4_tstbit0_tp0_jump_t |
| 596 | UINT64_C(327156480), // J4_tstbit0_tp1_jump_nt |
| 597 | UINT64_C(327164672), // J4_tstbit0_tp1_jump_t |
| 598 | UINT64_C(2415919104), // L2_deallocframe |
| 599 | UINT64_C(2424307712), // L2_loadalignb_io |
| 600 | UINT64_C(2659188736), // L2_loadalignb_pbr |
| 601 | UINT64_C(2558525440), // L2_loadalignb_pci |
| 602 | UINT64_C(2558525952), // L2_loadalignb_pcr |
| 603 | UINT64_C(2592079872), // L2_loadalignb_pi |
| 604 | UINT64_C(2625634304), // L2_loadalignb_pr |
| 605 | UINT64_C(2420113408), // L2_loadalignh_io |
| 606 | UINT64_C(2654994432), // L2_loadalignh_pbr |
| 607 | UINT64_C(2554331136), // L2_loadalignh_pci |
| 608 | UINT64_C(2554331648), // L2_loadalignh_pcr |
| 609 | UINT64_C(2587885568), // L2_loadalignh_pi |
| 610 | UINT64_C(2621440000), // L2_loadalignh_pr |
| 611 | UINT64_C(2418016256), // L2_loadbsw2_io |
| 612 | UINT64_C(2652897280), // L2_loadbsw2_pbr |
| 613 | UINT64_C(2552233984), // L2_loadbsw2_pci |
| 614 | UINT64_C(2552234496), // L2_loadbsw2_pcr |
| 615 | UINT64_C(2585788416), // L2_loadbsw2_pi |
| 616 | UINT64_C(2619342848), // L2_loadbsw2_pr |
| 617 | UINT64_C(2430599168), // L2_loadbsw4_io |
| 618 | UINT64_C(2665480192), // L2_loadbsw4_pbr |
| 619 | UINT64_C(2564816896), // L2_loadbsw4_pci |
| 620 | UINT64_C(2564817408), // L2_loadbsw4_pcr |
| 621 | UINT64_C(2598371328), // L2_loadbsw4_pi |
| 622 | UINT64_C(2631925760), // L2_loadbsw4_pr |
| 623 | UINT64_C(2422210560), // L2_loadbzw2_io |
| 624 | UINT64_C(2657091584), // L2_loadbzw2_pbr |
| 625 | UINT64_C(2556428288), // L2_loadbzw2_pci |
| 626 | UINT64_C(2556428800), // L2_loadbzw2_pcr |
| 627 | UINT64_C(2589982720), // L2_loadbzw2_pi |
| 628 | UINT64_C(2623537152), // L2_loadbzw2_pr |
| 629 | UINT64_C(2426404864), // L2_loadbzw4_io |
| 630 | UINT64_C(2661285888), // L2_loadbzw4_pbr |
| 631 | UINT64_C(2560622592), // L2_loadbzw4_pci |
| 632 | UINT64_C(2560623104), // L2_loadbzw4_pcr |
| 633 | UINT64_C(2594177024), // L2_loadbzw4_pi |
| 634 | UINT64_C(2627731456), // L2_loadbzw4_pr |
| 635 | UINT64_C(2432696320), // L2_loadrb_io |
| 636 | UINT64_C(2667577344), // L2_loadrb_pbr |
| 637 | UINT64_C(2566914048), // L2_loadrb_pci |
| 638 | UINT64_C(2566914560), // L2_loadrb_pcr |
| 639 | UINT64_C(2600468480), // L2_loadrb_pi |
| 640 | UINT64_C(2634022912), // L2_loadrb_pr |
| 641 | UINT64_C(1224736768), // L2_loadrbgp |
| 642 | UINT64_C(2445279232), // L2_loadrd_io |
| 643 | UINT64_C(2680160256), // L2_loadrd_pbr |
| 644 | UINT64_C(2579496960), // L2_loadrd_pci |
| 645 | UINT64_C(2579497472), // L2_loadrd_pcr |
| 646 | UINT64_C(2613051392), // L2_loadrd_pi |
| 647 | UINT64_C(2646605824), // L2_loadrd_pr |
| 648 | UINT64_C(1237319680), // L2_loadrdgp |
| 649 | UINT64_C(2436890624), // L2_loadrh_io |
| 650 | UINT64_C(2671771648), // L2_loadrh_pbr |
| 651 | UINT64_C(2571108352), // L2_loadrh_pci |
| 652 | UINT64_C(2571108864), // L2_loadrh_pcr |
| 653 | UINT64_C(2604662784), // L2_loadrh_pi |
| 654 | UINT64_C(2638217216), // L2_loadrh_pr |
| 655 | UINT64_C(1228931072), // L2_loadrhgp |
| 656 | UINT64_C(2441084928), // L2_loadri_io |
| 657 | UINT64_C(2675965952), // L2_loadri_pbr |
| 658 | UINT64_C(2575302656), // L2_loadri_pci |
| 659 | UINT64_C(2575303168), // L2_loadri_pcr |
| 660 | UINT64_C(2608857088), // L2_loadri_pi |
| 661 | UINT64_C(2642411520), // L2_loadri_pr |
| 662 | UINT64_C(1233125376), // L2_loadrigp |
| 663 | UINT64_C(2434793472), // L2_loadrub_io |
| 664 | UINT64_C(2669674496), // L2_loadrub_pbr |
| 665 | UINT64_C(2569011200), // L2_loadrub_pci |
| 666 | UINT64_C(2569011712), // L2_loadrub_pcr |
| 667 | UINT64_C(2602565632), // L2_loadrub_pi |
| 668 | UINT64_C(2636120064), // L2_loadrub_pr |
| 669 | UINT64_C(1226833920), // L2_loadrubgp |
| 670 | UINT64_C(2438987776), // L2_loadruh_io |
| 671 | UINT64_C(2673868800), // L2_loadruh_pbr |
| 672 | UINT64_C(2573205504), // L2_loadruh_pci |
| 673 | UINT64_C(2573206016), // L2_loadruh_pcr |
| 674 | UINT64_C(2606759936), // L2_loadruh_pi |
| 675 | UINT64_C(2640314368), // L2_loadruh_pr |
| 676 | UINT64_C(1231028224), // L2_loadruhgp |
| 677 | UINT64_C(2449475584), // L2_loadw_aq |
| 678 | UINT64_C(2449473536), // L2_loadw_locked |
| 679 | UINT64_C(1157627904), // L2_ploadrbf_io |
| 680 | UINT64_C(2600478720), // L2_ploadrbf_pi |
| 681 | UINT64_C(1191182336), // L2_ploadrbfnew_io |
| 682 | UINT64_C(2600482816), // L2_ploadrbfnew_pi |
| 683 | UINT64_C(1090519040), // L2_ploadrbt_io |
| 684 | UINT64_C(2600476672), // L2_ploadrbt_pi |
| 685 | UINT64_C(1124073472), // L2_ploadrbtnew_io |
| 686 | UINT64_C(2600480768), // L2_ploadrbtnew_pi |
| 687 | UINT64_C(1170210816), // L2_ploadrdf_io |
| 688 | UINT64_C(2613061632), // L2_ploadrdf_pi |
| 689 | UINT64_C(1203765248), // L2_ploadrdfnew_io |
| 690 | UINT64_C(2613065728), // L2_ploadrdfnew_pi |
| 691 | UINT64_C(1103101952), // L2_ploadrdt_io |
| 692 | UINT64_C(2613059584), // L2_ploadrdt_pi |
| 693 | UINT64_C(1136656384), // L2_ploadrdtnew_io |
| 694 | UINT64_C(2613063680), // L2_ploadrdtnew_pi |
| 695 | UINT64_C(1161822208), // L2_ploadrhf_io |
| 696 | UINT64_C(2604673024), // L2_ploadrhf_pi |
| 697 | UINT64_C(1195376640), // L2_ploadrhfnew_io |
| 698 | UINT64_C(2604677120), // L2_ploadrhfnew_pi |
| 699 | UINT64_C(1094713344), // L2_ploadrht_io |
| 700 | UINT64_C(2604670976), // L2_ploadrht_pi |
| 701 | UINT64_C(1128267776), // L2_ploadrhtnew_io |
| 702 | UINT64_C(2604675072), // L2_ploadrhtnew_pi |
| 703 | UINT64_C(1166016512), // L2_ploadrif_io |
| 704 | UINT64_C(2608867328), // L2_ploadrif_pi |
| 705 | UINT64_C(1199570944), // L2_ploadrifnew_io |
| 706 | UINT64_C(2608871424), // L2_ploadrifnew_pi |
| 707 | UINT64_C(1098907648), // L2_ploadrit_io |
| 708 | UINT64_C(2608865280), // L2_ploadrit_pi |
| 709 | UINT64_C(1132462080), // L2_ploadritnew_io |
| 710 | UINT64_C(2608869376), // L2_ploadritnew_pi |
| 711 | UINT64_C(1159725056), // L2_ploadrubf_io |
| 712 | UINT64_C(2602575872), // L2_ploadrubf_pi |
| 713 | UINT64_C(1193279488), // L2_ploadrubfnew_io |
| 714 | UINT64_C(2602579968), // L2_ploadrubfnew_pi |
| 715 | UINT64_C(1092616192), // L2_ploadrubt_io |
| 716 | UINT64_C(2602573824), // L2_ploadrubt_pi |
| 717 | UINT64_C(1126170624), // L2_ploadrubtnew_io |
| 718 | UINT64_C(2602577920), // L2_ploadrubtnew_pi |
| 719 | UINT64_C(1163919360), // L2_ploadruhf_io |
| 720 | UINT64_C(2606770176), // L2_ploadruhf_pi |
| 721 | UINT64_C(1197473792), // L2_ploadruhfnew_io |
| 722 | UINT64_C(2606774272), // L2_ploadruhfnew_pi |
| 723 | UINT64_C(1096810496), // L2_ploadruht_io |
| 724 | UINT64_C(2606768128), // L2_ploadruht_pi |
| 725 | UINT64_C(1130364928), // L2_ploadruhtnew_io |
| 726 | UINT64_C(2606772224), // L2_ploadruhtnew_pi |
| 727 | UINT64_C(1040187392), // L4_add_memopb_io |
| 728 | UINT64_C(1042284544), // L4_add_memoph_io |
| 729 | UINT64_C(1044381696), // L4_add_memopw_io |
| 730 | UINT64_C(1040187456), // L4_and_memopb_io |
| 731 | UINT64_C(1042284608), // L4_and_memoph_io |
| 732 | UINT64_C(1044381760), // L4_and_memopw_io |
| 733 | UINT64_C(1056964608), // L4_iadd_memopb_io |
| 734 | UINT64_C(1059061760), // L4_iadd_memoph_io |
| 735 | UINT64_C(1061158912), // L4_iadd_memopw_io |
| 736 | UINT64_C(1056964672), // L4_iand_memopb_io |
| 737 | UINT64_C(1059061824), // L4_iand_memoph_io |
| 738 | UINT64_C(1061158976), // L4_iand_memopw_io |
| 739 | UINT64_C(1056964704), // L4_ior_memopb_io |
| 740 | UINT64_C(1059061856), // L4_ior_memoph_io |
| 741 | UINT64_C(1061159008), // L4_ior_memopw_io |
| 742 | UINT64_C(1056964640), // L4_isub_memopb_io |
| 743 | UINT64_C(1059061792), // L4_isub_memoph_io |
| 744 | UINT64_C(1061158944), // L4_isub_memopw_io |
| 745 | UINT64_C(2592083968), // L4_loadalignb_ap |
| 746 | UINT64_C(2625638400), // L4_loadalignb_ur |
| 747 | UINT64_C(2587889664), // L4_loadalignh_ap |
| 748 | UINT64_C(2621444096), // L4_loadalignh_ur |
| 749 | UINT64_C(2585792512), // L4_loadbsw2_ap |
| 750 | UINT64_C(2619346944), // L4_loadbsw2_ur |
| 751 | UINT64_C(2598375424), // L4_loadbsw4_ap |
| 752 | UINT64_C(2631929856), // L4_loadbsw4_ur |
| 753 | UINT64_C(2589986816), // L4_loadbzw2_ap |
| 754 | UINT64_C(2623541248), // L4_loadbzw2_ur |
| 755 | UINT64_C(2594181120), // L4_loadbzw4_ap |
| 756 | UINT64_C(2627735552), // L4_loadbzw4_ur |
| 757 | UINT64_C(2449479680), // L4_loadd_aq |
| 758 | UINT64_C(2449477632), // L4_loadd_locked |
| 759 | UINT64_C(2600472576), // L4_loadrb_ap |
| 760 | UINT64_C(973078528), // L4_loadrb_rr |
| 761 | UINT64_C(2634027008), // L4_loadrb_ur |
| 762 | UINT64_C(2613055488), // L4_loadrd_ap |
| 763 | UINT64_C(985661440), // L4_loadrd_rr |
| 764 | UINT64_C(2646609920), // L4_loadrd_ur |
| 765 | UINT64_C(2604666880), // L4_loadrh_ap |
| 766 | UINT64_C(977272832), // L4_loadrh_rr |
| 767 | UINT64_C(2638221312), // L4_loadrh_ur |
| 768 | UINT64_C(2608861184), // L4_loadri_ap |
| 769 | UINT64_C(981467136), // L4_loadri_rr |
| 770 | UINT64_C(2642415616), // L4_loadri_ur |
| 771 | UINT64_C(2602569728), // L4_loadrub_ap |
| 772 | UINT64_C(975175680), // L4_loadrub_rr |
| 773 | UINT64_C(2636124160), // L4_loadrub_ur |
| 774 | UINT64_C(2606764032), // L4_loadruh_ap |
| 775 | UINT64_C(979369984), // L4_loadruh_rr |
| 776 | UINT64_C(2640318464), // L4_loadruh_ur |
| 777 | UINT64_C(2449481728), // L4_loadw_phys |
| 778 | UINT64_C(1040187488), // L4_or_memopb_io |
| 779 | UINT64_C(1042284640), // L4_or_memoph_io |
| 780 | UINT64_C(1044381792), // L4_or_memopw_io |
| 781 | UINT64_C(2667587712), // L4_ploadrbf_abs |
| 782 | UINT64_C(822083584), // L4_ploadrbf_rr |
| 783 | UINT64_C(2667591808), // L4_ploadrbfnew_abs |
| 784 | UINT64_C(855638016), // L4_ploadrbfnew_rr |
| 785 | UINT64_C(2667585664), // L4_ploadrbt_abs |
| 786 | UINT64_C(805306368), // L4_ploadrbt_rr |
| 787 | UINT64_C(2667589760), // L4_ploadrbtnew_abs |
| 788 | UINT64_C(838860800), // L4_ploadrbtnew_rr |
| 789 | UINT64_C(2680170624), // L4_ploadrdf_abs |
| 790 | UINT64_C(834666496), // L4_ploadrdf_rr |
| 791 | UINT64_C(2680174720), // L4_ploadrdfnew_abs |
| 792 | UINT64_C(868220928), // L4_ploadrdfnew_rr |
| 793 | UINT64_C(2680168576), // L4_ploadrdt_abs |
| 794 | UINT64_C(817889280), // L4_ploadrdt_rr |
| 795 | UINT64_C(2680172672), // L4_ploadrdtnew_abs |
| 796 | UINT64_C(851443712), // L4_ploadrdtnew_rr |
| 797 | UINT64_C(2671782016), // L4_ploadrhf_abs |
| 798 | UINT64_C(826277888), // L4_ploadrhf_rr |
| 799 | UINT64_C(2671786112), // L4_ploadrhfnew_abs |
| 800 | UINT64_C(859832320), // L4_ploadrhfnew_rr |
| 801 | UINT64_C(2671779968), // L4_ploadrht_abs |
| 802 | UINT64_C(809500672), // L4_ploadrht_rr |
| 803 | UINT64_C(2671784064), // L4_ploadrhtnew_abs |
| 804 | UINT64_C(843055104), // L4_ploadrhtnew_rr |
| 805 | UINT64_C(2675976320), // L4_ploadrif_abs |
| 806 | UINT64_C(830472192), // L4_ploadrif_rr |
| 807 | UINT64_C(2675980416), // L4_ploadrifnew_abs |
| 808 | UINT64_C(864026624), // L4_ploadrifnew_rr |
| 809 | UINT64_C(2675974272), // L4_ploadrit_abs |
| 810 | UINT64_C(813694976), // L4_ploadrit_rr |
| 811 | UINT64_C(2675978368), // L4_ploadritnew_abs |
| 812 | UINT64_C(847249408), // L4_ploadritnew_rr |
| 813 | UINT64_C(2669684864), // L4_ploadrubf_abs |
| 814 | UINT64_C(824180736), // L4_ploadrubf_rr |
| 815 | UINT64_C(2669688960), // L4_ploadrubfnew_abs |
| 816 | UINT64_C(857735168), // L4_ploadrubfnew_rr |
| 817 | UINT64_C(2669682816), // L4_ploadrubt_abs |
| 818 | UINT64_C(807403520), // L4_ploadrubt_rr |
| 819 | UINT64_C(2669686912), // L4_ploadrubtnew_abs |
| 820 | UINT64_C(840957952), // L4_ploadrubtnew_rr |
| 821 | UINT64_C(2673879168), // L4_ploadruhf_abs |
| 822 | UINT64_C(828375040), // L4_ploadruhf_rr |
| 823 | UINT64_C(2673883264), // L4_ploadruhfnew_abs |
| 824 | UINT64_C(861929472), // L4_ploadruhfnew_rr |
| 825 | UINT64_C(2673877120), // L4_ploadruht_abs |
| 826 | UINT64_C(811597824), // L4_ploadruht_rr |
| 827 | UINT64_C(2673881216), // L4_ploadruhtnew_abs |
| 828 | UINT64_C(845152256), // L4_ploadruhtnew_rr |
| 829 | UINT64_C(2516582400), // L4_return |
| 830 | UINT64_C(2516594688), // L4_return_f |
| 831 | UINT64_C(2516592640), // L4_return_fnew_pnt |
| 832 | UINT64_C(2516596736), // L4_return_fnew_pt |
| 833 | UINT64_C(2516586496), // L4_return_t |
| 834 | UINT64_C(2516584448), // L4_return_tnew_pnt |
| 835 | UINT64_C(2516588544), // L4_return_tnew_pt |
| 836 | UINT64_C(1040187424), // L4_sub_memopb_io |
| 837 | UINT64_C(1042284576), // L4_sub_memoph_io |
| 838 | UINT64_C(1044381728), // L4_sub_memopw_io |
| 839 | UINT64_C(2449473600), // L6_memcpy |
| 840 | UINT64_C(18874368), // LO |
| 841 | UINT64_C(4009754656), // M2_acci |
| 842 | UINT64_C(3791650816), // M2_accii |
| 843 | UINT64_C(3875536928), // M2_cmaci_s0 |
| 844 | UINT64_C(3875536960), // M2_cmacr_s0 |
| 845 | UINT64_C(3875537088), // M2_cmacs_s0 |
| 846 | UINT64_C(3883925696), // M2_cmacs_s1 |
| 847 | UINT64_C(3879731392), // M2_cmacsc_s0 |
| 848 | UINT64_C(3888120000), // M2_cmacsc_s1 |
| 849 | UINT64_C(3841982496), // M2_cmpyi_s0 |
| 850 | UINT64_C(3841982528), // M2_cmpyr_s0 |
| 851 | UINT64_C(3978297536), // M2_cmpyrs_s0 |
| 852 | UINT64_C(3986686144), // M2_cmpyrs_s1 |
| 853 | UINT64_C(3982491840), // M2_cmpyrsc_s0 |
| 854 | UINT64_C(3990880448), // M2_cmpyrsc_s1 |
| 855 | UINT64_C(3841982656), // M2_cmpys_s0 |
| 856 | UINT64_C(3850371264), // M2_cmpys_s1 |
| 857 | UINT64_C(3846176960), // M2_cmpysc_s0 |
| 858 | UINT64_C(3854565568), // M2_cmpysc_s1 |
| 859 | UINT64_C(3875537120), // M2_cnacs_s0 |
| 860 | UINT64_C(3883925728), // M2_cnacs_s1 |
| 861 | UINT64_C(3879731424), // M2_cnacsc_s0 |
| 862 | UINT64_C(3888120032), // M2_cnacsc_s1 |
| 863 | UINT64_C(3875536896), // M2_dpmpyss_acc_s0 |
| 864 | UINT64_C(3877634048), // M2_dpmpyss_nac_s0 |
| 865 | UINT64_C(3978297376), // M2_dpmpyss_rnd_s0 |
| 866 | UINT64_C(3841982464), // M2_dpmpyss_s0 |
| 867 | UINT64_C(3879731200), // M2_dpmpyuu_acc_s0 |
| 868 | UINT64_C(3881828352), // M2_dpmpyuu_nac_s0 |
| 869 | UINT64_C(3846176768), // M2_dpmpyuu_s0 |
| 870 | UINT64_C(3986686080), // M2_hmmpyh_rs1 |
| 871 | UINT64_C(3986685952), // M2_hmmpyh_s1 |
| 872 | UINT64_C(3990880384), // M2_hmmpyl_rs1 |
| 873 | UINT64_C(3986685984), // M2_hmmpyl_s1 |
| 874 | UINT64_C(4009754624), // M2_maci |
| 875 | UINT64_C(3783262208), // M2_macsin |
| 876 | UINT64_C(3774873600), // M2_macsip |
| 877 | UINT64_C(3927965920), // M2_mmachs_rs0 |
| 878 | UINT64_C(3936354528), // M2_mmachs_rs1 |
| 879 | UINT64_C(3925868768), // M2_mmachs_s0 |
| 880 | UINT64_C(3934257376), // M2_mmachs_s1 |
| 881 | UINT64_C(3927965856), // M2_mmacls_rs0 |
| 882 | UINT64_C(3936354464), // M2_mmacls_rs1 |
| 883 | UINT64_C(3925868704), // M2_mmacls_s0 |
| 884 | UINT64_C(3934257312), // M2_mmacls_s1 |
| 885 | UINT64_C(3932160224), // M2_mmacuhs_rs0 |
| 886 | UINT64_C(3940548832), // M2_mmacuhs_rs1 |
| 887 | UINT64_C(3930063072), // M2_mmacuhs_s0 |
| 888 | UINT64_C(3938451680), // M2_mmacuhs_s1 |
| 889 | UINT64_C(3932160160), // M2_mmaculs_rs0 |
| 890 | UINT64_C(3940548768), // M2_mmaculs_rs1 |
| 891 | UINT64_C(3930063008), // M2_mmaculs_s0 |
| 892 | UINT64_C(3938451616), // M2_mmaculs_s1 |
| 893 | UINT64_C(3894411488), // M2_mmpyh_rs0 |
| 894 | UINT64_C(3902800096), // M2_mmpyh_rs1 |
| 895 | UINT64_C(3892314336), // M2_mmpyh_s0 |
| 896 | UINT64_C(3900702944), // M2_mmpyh_s1 |
| 897 | UINT64_C(3894411424), // M2_mmpyl_rs0 |
| 898 | UINT64_C(3902800032), // M2_mmpyl_rs1 |
| 899 | UINT64_C(3892314272), // M2_mmpyl_s0 |
| 900 | UINT64_C(3900702880), // M2_mmpyl_s1 |
| 901 | UINT64_C(3898605792), // M2_mmpyuh_rs0 |
| 902 | UINT64_C(3906994400), // M2_mmpyuh_rs1 |
| 903 | UINT64_C(3896508640), // M2_mmpyuh_s0 |
| 904 | UINT64_C(3904897248), // M2_mmpyuh_s1 |
| 905 | UINT64_C(3898605728), // M2_mmpyul_rs0 |
| 906 | UINT64_C(3906994336), // M2_mmpyul_rs1 |
| 907 | UINT64_C(3896508576), // M2_mmpyul_s0 |
| 908 | UINT64_C(3904897184), // M2_mmpyul_s1 |
| 909 | UINT64_C(4018143232), // M2_mnaci |
| 910 | UINT64_C(3992977504), // M2_mpy_acc_hh_s0 |
| 911 | UINT64_C(4001366112), // M2_mpy_acc_hh_s1 |
| 912 | UINT64_C(3992977472), // M2_mpy_acc_hl_s0 |
| 913 | UINT64_C(4001366080), // M2_mpy_acc_hl_s1 |
| 914 | UINT64_C(3992977440), // M2_mpy_acc_lh_s0 |
| 915 | UINT64_C(4001366048), // M2_mpy_acc_lh_s1 |
| 916 | UINT64_C(3992977408), // M2_mpy_acc_ll_s0 |
| 917 | UINT64_C(4001366016), // M2_mpy_acc_ll_s1 |
| 918 | UINT64_C(3992977632), // M2_mpy_acc_sat_hh_s0 |
| 919 | UINT64_C(4001366240), // M2_mpy_acc_sat_hh_s1 |
| 920 | UINT64_C(3992977600), // M2_mpy_acc_sat_hl_s0 |
| 921 | UINT64_C(4001366208), // M2_mpy_acc_sat_hl_s1 |
| 922 | UINT64_C(3992977568), // M2_mpy_acc_sat_lh_s0 |
| 923 | UINT64_C(4001366176), // M2_mpy_acc_sat_lh_s1 |
| 924 | UINT64_C(3992977536), // M2_mpy_acc_sat_ll_s0 |
| 925 | UINT64_C(4001366144), // M2_mpy_acc_sat_ll_s1 |
| 926 | UINT64_C(3959423072), // M2_mpy_hh_s0 |
| 927 | UINT64_C(3967811680), // M2_mpy_hh_s1 |
| 928 | UINT64_C(3959423040), // M2_mpy_hl_s0 |
| 929 | UINT64_C(3967811648), // M2_mpy_hl_s1 |
| 930 | UINT64_C(3959423008), // M2_mpy_lh_s0 |
| 931 | UINT64_C(3967811616), // M2_mpy_lh_s1 |
| 932 | UINT64_C(3959422976), // M2_mpy_ll_s0 |
| 933 | UINT64_C(3967811584), // M2_mpy_ll_s1 |
| 934 | UINT64_C(3995074656), // M2_mpy_nac_hh_s0 |
| 935 | UINT64_C(4003463264), // M2_mpy_nac_hh_s1 |
| 936 | UINT64_C(3995074624), // M2_mpy_nac_hl_s0 |
| 937 | UINT64_C(4003463232), // M2_mpy_nac_hl_s1 |
| 938 | UINT64_C(3995074592), // M2_mpy_nac_lh_s0 |
| 939 | UINT64_C(4003463200), // M2_mpy_nac_lh_s1 |
| 940 | UINT64_C(3995074560), // M2_mpy_nac_ll_s0 |
| 941 | UINT64_C(4003463168), // M2_mpy_nac_ll_s1 |
| 942 | UINT64_C(3995074784), // M2_mpy_nac_sat_hh_s0 |
| 943 | UINT64_C(4003463392), // M2_mpy_nac_sat_hh_s1 |
| 944 | UINT64_C(3995074752), // M2_mpy_nac_sat_hl_s0 |
| 945 | UINT64_C(4003463360), // M2_mpy_nac_sat_hl_s1 |
| 946 | UINT64_C(3995074720), // M2_mpy_nac_sat_lh_s0 |
| 947 | UINT64_C(4003463328), // M2_mpy_nac_sat_lh_s1 |
| 948 | UINT64_C(3995074688), // M2_mpy_nac_sat_ll_s0 |
| 949 | UINT64_C(4003463296), // M2_mpy_nac_sat_ll_s1 |
| 950 | UINT64_C(3961520224), // M2_mpy_rnd_hh_s0 |
| 951 | UINT64_C(3969908832), // M2_mpy_rnd_hh_s1 |
| 952 | UINT64_C(3961520192), // M2_mpy_rnd_hl_s0 |
| 953 | UINT64_C(3969908800), // M2_mpy_rnd_hl_s1 |
| 954 | UINT64_C(3961520160), // M2_mpy_rnd_lh_s0 |
| 955 | UINT64_C(3969908768), // M2_mpy_rnd_lh_s1 |
| 956 | UINT64_C(3961520128), // M2_mpy_rnd_ll_s0 |
| 957 | UINT64_C(3969908736), // M2_mpy_rnd_ll_s1 |
| 958 | UINT64_C(3959423200), // M2_mpy_sat_hh_s0 |
| 959 | UINT64_C(3967811808), // M2_mpy_sat_hh_s1 |
| 960 | UINT64_C(3959423168), // M2_mpy_sat_hl_s0 |
| 961 | UINT64_C(3967811776), // M2_mpy_sat_hl_s1 |
| 962 | UINT64_C(3959423136), // M2_mpy_sat_lh_s0 |
| 963 | UINT64_C(3967811744), // M2_mpy_sat_lh_s1 |
| 964 | UINT64_C(3959423104), // M2_mpy_sat_ll_s0 |
| 965 | UINT64_C(3967811712), // M2_mpy_sat_ll_s1 |
| 966 | UINT64_C(3961520352), // M2_mpy_sat_rnd_hh_s0 |
| 967 | UINT64_C(3969908960), // M2_mpy_sat_rnd_hh_s1 |
| 968 | UINT64_C(3961520320), // M2_mpy_sat_rnd_hl_s0 |
| 969 | UINT64_C(3969908928), // M2_mpy_sat_rnd_hl_s1 |
| 970 | UINT64_C(3961520288), // M2_mpy_sat_rnd_lh_s0 |
| 971 | UINT64_C(3969908896), // M2_mpy_sat_rnd_lh_s1 |
| 972 | UINT64_C(3961520256), // M2_mpy_sat_rnd_ll_s0 |
| 973 | UINT64_C(3969908864), // M2_mpy_sat_rnd_ll_s1 |
| 974 | UINT64_C(3976200224), // M2_mpy_up |
| 975 | UINT64_C(3986686016), // M2_mpy_up_s1 |
| 976 | UINT64_C(3990880256), // M2_mpy_up_s1_sat |
| 977 | UINT64_C(3858759776), // M2_mpyd_acc_hh_s0 |
| 978 | UINT64_C(3867148384), // M2_mpyd_acc_hh_s1 |
| 979 | UINT64_C(3858759744), // M2_mpyd_acc_hl_s0 |
| 980 | UINT64_C(3867148352), // M2_mpyd_acc_hl_s1 |
| 981 | UINT64_C(3858759712), // M2_mpyd_acc_lh_s0 |
| 982 | UINT64_C(3867148320), // M2_mpyd_acc_lh_s1 |
| 983 | UINT64_C(3858759680), // M2_mpyd_acc_ll_s0 |
| 984 | UINT64_C(3867148288), // M2_mpyd_acc_ll_s1 |
| 985 | UINT64_C(3825205344), // M2_mpyd_hh_s0 |
| 986 | UINT64_C(3833593952), // M2_mpyd_hh_s1 |
| 987 | UINT64_C(3825205312), // M2_mpyd_hl_s0 |
| 988 | UINT64_C(3833593920), // M2_mpyd_hl_s1 |
| 989 | UINT64_C(3825205280), // M2_mpyd_lh_s0 |
| 990 | UINT64_C(3833593888), // M2_mpyd_lh_s1 |
| 991 | UINT64_C(3825205248), // M2_mpyd_ll_s0 |
| 992 | UINT64_C(3833593856), // M2_mpyd_ll_s1 |
| 993 | UINT64_C(3860856928), // M2_mpyd_nac_hh_s0 |
| 994 | UINT64_C(3869245536), // M2_mpyd_nac_hh_s1 |
| 995 | UINT64_C(3860856896), // M2_mpyd_nac_hl_s0 |
| 996 | UINT64_C(3869245504), // M2_mpyd_nac_hl_s1 |
| 997 | UINT64_C(3860856864), // M2_mpyd_nac_lh_s0 |
| 998 | UINT64_C(3869245472), // M2_mpyd_nac_lh_s1 |
| 999 | UINT64_C(3860856832), // M2_mpyd_nac_ll_s0 |
| 1000 | UINT64_C(3869245440), // M2_mpyd_nac_ll_s1 |
| 1001 | UINT64_C(3827302496), // M2_mpyd_rnd_hh_s0 |
| 1002 | UINT64_C(3835691104), // M2_mpyd_rnd_hh_s1 |
| 1003 | UINT64_C(3827302464), // M2_mpyd_rnd_hl_s0 |
| 1004 | UINT64_C(3835691072), // M2_mpyd_rnd_hl_s1 |
| 1005 | UINT64_C(3827302432), // M2_mpyd_rnd_lh_s0 |
| 1006 | UINT64_C(3835691040), // M2_mpyd_rnd_lh_s1 |
| 1007 | UINT64_C(3827302400), // M2_mpyd_rnd_ll_s0 |
| 1008 | UINT64_C(3835691008), // M2_mpyd_rnd_ll_s1 |
| 1009 | UINT64_C(3976200192), // M2_mpyi |
| 1010 | UINT64_C(3766484992), // M2_mpysin |
| 1011 | UINT64_C(3758096384), // M2_mpysip |
| 1012 | UINT64_C(3982491680), // M2_mpysu_up |
| 1013 | UINT64_C(3997171808), // M2_mpyu_acc_hh_s0 |
| 1014 | UINT64_C(4005560416), // M2_mpyu_acc_hh_s1 |
| 1015 | UINT64_C(3997171776), // M2_mpyu_acc_hl_s0 |
| 1016 | UINT64_C(4005560384), // M2_mpyu_acc_hl_s1 |
| 1017 | UINT64_C(3997171744), // M2_mpyu_acc_lh_s0 |
| 1018 | UINT64_C(4005560352), // M2_mpyu_acc_lh_s1 |
| 1019 | UINT64_C(3997171712), // M2_mpyu_acc_ll_s0 |
| 1020 | UINT64_C(4005560320), // M2_mpyu_acc_ll_s1 |
| 1021 | UINT64_C(3963617376), // M2_mpyu_hh_s0 |
| 1022 | UINT64_C(3972005984), // M2_mpyu_hh_s1 |
| 1023 | UINT64_C(3963617344), // M2_mpyu_hl_s0 |
| 1024 | UINT64_C(3972005952), // M2_mpyu_hl_s1 |
| 1025 | UINT64_C(3963617312), // M2_mpyu_lh_s0 |
| 1026 | UINT64_C(3972005920), // M2_mpyu_lh_s1 |
| 1027 | UINT64_C(3963617280), // M2_mpyu_ll_s0 |
| 1028 | UINT64_C(3972005888), // M2_mpyu_ll_s1 |
| 1029 | UINT64_C(3999268960), // M2_mpyu_nac_hh_s0 |
| 1030 | UINT64_C(4007657568), // M2_mpyu_nac_hh_s1 |
| 1031 | UINT64_C(3999268928), // M2_mpyu_nac_hl_s0 |
| 1032 | UINT64_C(4007657536), // M2_mpyu_nac_hl_s1 |
| 1033 | UINT64_C(3999268896), // M2_mpyu_nac_lh_s0 |
| 1034 | UINT64_C(4007657504), // M2_mpyu_nac_lh_s1 |
| 1035 | UINT64_C(3999268864), // M2_mpyu_nac_ll_s0 |
| 1036 | UINT64_C(4007657472), // M2_mpyu_nac_ll_s1 |
| 1037 | UINT64_C(3980394528), // M2_mpyu_up |
| 1038 | UINT64_C(3862954080), // M2_mpyud_acc_hh_s0 |
| 1039 | UINT64_C(3871342688), // M2_mpyud_acc_hh_s1 |
| 1040 | UINT64_C(3862954048), // M2_mpyud_acc_hl_s0 |
| 1041 | UINT64_C(3871342656), // M2_mpyud_acc_hl_s1 |
| 1042 | UINT64_C(3862954016), // M2_mpyud_acc_lh_s0 |
| 1043 | UINT64_C(3871342624), // M2_mpyud_acc_lh_s1 |
| 1044 | UINT64_C(3862953984), // M2_mpyud_acc_ll_s0 |
| 1045 | UINT64_C(3871342592), // M2_mpyud_acc_ll_s1 |
| 1046 | UINT64_C(3829399648), // M2_mpyud_hh_s0 |
| 1047 | UINT64_C(3837788256), // M2_mpyud_hh_s1 |
| 1048 | UINT64_C(3829399616), // M2_mpyud_hl_s0 |
| 1049 | UINT64_C(3837788224), // M2_mpyud_hl_s1 |
| 1050 | UINT64_C(3829399584), // M2_mpyud_lh_s0 |
| 1051 | UINT64_C(3837788192), // M2_mpyud_lh_s1 |
| 1052 | UINT64_C(3829399552), // M2_mpyud_ll_s0 |
| 1053 | UINT64_C(3837788160), // M2_mpyud_ll_s1 |
| 1054 | UINT64_C(3865051232), // M2_mpyud_nac_hh_s0 |
| 1055 | UINT64_C(3873439840), // M2_mpyud_nac_hh_s1 |
| 1056 | UINT64_C(3865051200), // M2_mpyud_nac_hl_s0 |
| 1057 | UINT64_C(3873439808), // M2_mpyud_nac_hl_s1 |
| 1058 | UINT64_C(3865051168), // M2_mpyud_nac_lh_s0 |
| 1059 | UINT64_C(3873439776), // M2_mpyud_nac_lh_s1 |
| 1060 | UINT64_C(3865051136), // M2_mpyud_nac_ll_s0 |
| 1061 | UINT64_C(3873439744), // M2_mpyud_nac_ll_s1 |
| 1062 | UINT64_C(4018143264), // M2_nacci |
| 1063 | UINT64_C(3800039424), // M2_naccii |
| 1064 | UINT64_C(4009754720), // M2_subacc |
| 1065 | UINT64_C(3898605568), // M2_vabsdiffh |
| 1066 | UINT64_C(3894411264), // M2_vabsdiffw |
| 1067 | UINT64_C(3930062976), // M2_vcmac_s0_sat_i |
| 1068 | UINT64_C(3927965824), // M2_vcmac_s0_sat_r |
| 1069 | UINT64_C(3896508608), // M2_vcmpy_s0_sat_i |
| 1070 | UINT64_C(3894411456), // M2_vcmpy_s0_sat_r |
| 1071 | UINT64_C(3904897216), // M2_vcmpy_s1_sat_i |
| 1072 | UINT64_C(3902800064), // M2_vcmpy_s1_sat_r |
| 1073 | UINT64_C(3925868672), // M2_vdmacs_s0 |
| 1074 | UINT64_C(3934257280), // M2_vdmacs_s1 |
| 1075 | UINT64_C(3909091328), // M2_vdmpyrs_s0 |
| 1076 | UINT64_C(3917479936), // M2_vdmpyrs_s1 |
| 1077 | UINT64_C(3892314240), // M2_vdmpys_s0 |
| 1078 | UINT64_C(3900702848), // M2_vdmpys_s1 |
| 1079 | UINT64_C(3877634080), // M2_vmac2 |
| 1080 | UINT64_C(3927965760), // M2_vmac2es |
| 1081 | UINT64_C(3925868736), // M2_vmac2es_s0 |
| 1082 | UINT64_C(3934257344), // M2_vmac2es_s1 |
| 1083 | UINT64_C(3875537056), // M2_vmac2s_s0 |
| 1084 | UINT64_C(3883925664), // M2_vmac2s_s1 |
| 1085 | UINT64_C(3881828512), // M2_vmac2su_s0 |
| 1086 | UINT64_C(3890217120), // M2_vmac2su_s1 |
| 1087 | UINT64_C(3892314304), // M2_vmpy2es_s0 |
| 1088 | UINT64_C(3900702912), // M2_vmpy2es_s1 |
| 1089 | UINT64_C(3841982624), // M2_vmpy2s_s0 |
| 1090 | UINT64_C(3978297568), // M2_vmpy2s_s0pack |
| 1091 | UINT64_C(3850371232), // M2_vmpy2s_s1 |
| 1092 | UINT64_C(3986686176), // M2_vmpy2s_s1pack |
| 1093 | UINT64_C(3841982688), // M2_vmpy2su_s0 |
| 1094 | UINT64_C(3850371296), // M2_vmpy2su_s1 |
| 1095 | UINT64_C(3911188704), // M2_vraddh |
| 1096 | UINT64_C(3909091360), // M2_vradduh |
| 1097 | UINT64_C(3925868544), // M2_vrcmaci_s0 |
| 1098 | UINT64_C(3930062848), // M2_vrcmaci_s0c |
| 1099 | UINT64_C(3925868576), // M2_vrcmacr_s0 |
| 1100 | UINT64_C(3932160032), // M2_vrcmacr_s0c |
| 1101 | UINT64_C(3892314112), // M2_vrcmpyi_s0 |
| 1102 | UINT64_C(3896508416), // M2_vrcmpyi_s0c |
| 1103 | UINT64_C(3892314144), // M2_vrcmpyr_s0 |
| 1104 | UINT64_C(3898605600), // M2_vrcmpyr_s0c |
| 1105 | UINT64_C(3936354432), // M2_vrcmpys_acc_s1_h |
| 1106 | UINT64_C(3940548736), // M2_vrcmpys_acc_s1_l |
| 1107 | UINT64_C(3902800000), // M2_vrcmpys_s1_h |
| 1108 | UINT64_C(3906994304), // M2_vrcmpys_s1_l |
| 1109 | UINT64_C(3919577280), // M2_vrcmpys_s1rp_h |
| 1110 | UINT64_C(3919577312), // M2_vrcmpys_s1rp_l |
| 1111 | UINT64_C(3925868608), // M2_vrmac_s0 |
| 1112 | UINT64_C(3892314176), // M2_vrmpy_s0 |
| 1113 | UINT64_C(4018143328), // M2_xor_xacc |
| 1114 | UINT64_C(4013948928), // M4_and_and |
| 1115 | UINT64_C(4011851808), // M4_and_andn |
| 1116 | UINT64_C(4013948960), // M4_and_or |
| 1117 | UINT64_C(4013948992), // M4_and_xor |
| 1118 | UINT64_C(3305111680), // M4_cmpyi_wh |
| 1119 | UINT64_C(3305111712), // M4_cmpyi_whc |
| 1120 | UINT64_C(3305111744), // M4_cmpyr_wh |
| 1121 | UINT64_C(3305111776), // M4_cmpyr_whc |
| 1122 | UINT64_C(4016046080), // M4_mac_up_s1_sat |
| 1123 | UINT64_C(3623878656), // M4_mpyri_addi |
| 1124 | UINT64_C(3749707776), // M4_mpyri_addr |
| 1125 | UINT64_C(3741319168), // M4_mpyri_addr_u2 |
| 1126 | UINT64_C(3607101440), // M4_mpyrr_addi |
| 1127 | UINT64_C(3808428032), // M4_mpyrr_addr |
| 1128 | UINT64_C(4016046112), // M4_nac_up_s1_sat |
| 1129 | UINT64_C(4013949024), // M4_or_and |
| 1130 | UINT64_C(4011851776), // M4_or_andn |
| 1131 | UINT64_C(4022337536), // M4_or_or |
| 1132 | UINT64_C(4022337568), // M4_or_xor |
| 1133 | UINT64_C(3846176992), // M4_pmpyw |
| 1134 | UINT64_C(3877634272), // M4_pmpyw_acc |
| 1135 | UINT64_C(3854565600), // M4_vpmpyh |
| 1136 | UINT64_C(3886022880), // M4_vpmpyh_acc |
| 1137 | UINT64_C(3927965888), // M4_vrmpyeh_acc_s0 |
| 1138 | UINT64_C(3936354496), // M4_vrmpyeh_acc_s1 |
| 1139 | UINT64_C(3896508544), // M4_vrmpyeh_s0 |
| 1140 | UINT64_C(3904897152), // M4_vrmpyeh_s1 |
| 1141 | UINT64_C(3932160192), // M4_vrmpyoh_acc_s0 |
| 1142 | UINT64_C(3940548800), // M4_vrmpyoh_acc_s1 |
| 1143 | UINT64_C(3894411328), // M4_vrmpyoh_s0 |
| 1144 | UINT64_C(3902799936), // M4_vrmpyoh_s1 |
| 1145 | UINT64_C(4022337600), // M4_xor_and |
| 1146 | UINT64_C(4011851840), // M4_xor_andn |
| 1147 | UINT64_C(4022337632), // M4_xor_or |
| 1148 | UINT64_C(3397386240), // M4_xor_xacc |
| 1149 | UINT64_C(3927965728), // M5_vdmacbsu |
| 1150 | UINT64_C(3902799904), // M5_vdmpybsu |
| 1151 | UINT64_C(3888119840), // M5_vmacbsu |
| 1152 | UINT64_C(3883925536), // M5_vmacbuu |
| 1153 | UINT64_C(3846176800), // M5_vmpybsu |
| 1154 | UINT64_C(3850371104), // M5_vmpybuu |
| 1155 | UINT64_C(3938451488), // M5_vrmacbsu |
| 1156 | UINT64_C(3934257184), // M5_vrmacbuu |
| 1157 | UINT64_C(3904897056), // M5_vrmpybsu |
| 1158 | UINT64_C(3900702752), // M5_vrmpybuu |
| 1159 | UINT64_C(3906994176), // M6_vabsdiffb |
| 1160 | UINT64_C(3902799872), // M6_vabsdiffub |
| 1161 | UINT64_C(3898605632), // M7_dcmpyiw |
| 1162 | UINT64_C(3932160064), // M7_dcmpyiw_acc |
| 1163 | UINT64_C(3906994240), // M7_dcmpyiwc |
| 1164 | UINT64_C(3930063040), // M7_dcmpyiwc_acc |
| 1165 | UINT64_C(3900702784), // M7_dcmpyrw |
| 1166 | UINT64_C(3934257216), // M7_dcmpyrw_acc |
| 1167 | UINT64_C(3904897088), // M7_dcmpyrwc |
| 1168 | UINT64_C(3938451520), // M7_dcmpyrwc_acc |
| 1169 | UINT64_C(3911188480), // M7_wcmpyiw |
| 1170 | UINT64_C(3919577088), // M7_wcmpyiw_rnd |
| 1171 | UINT64_C(3909091456), // M7_wcmpyiwc |
| 1172 | UINT64_C(3917480064), // M7_wcmpyiwc_rnd |
| 1173 | UINT64_C(3913285632), // M7_wcmpyrw |
| 1174 | UINT64_C(3921674240), // M7_wcmpyrw_rnd |
| 1175 | UINT64_C(3915382784), // M7_wcmpyrwc |
| 1176 | UINT64_C(3923771392), // M7_wcmpyrwc_rnd |
| 1177 | UINT64_C(1509949440), // PS_call_stk |
| 1178 | UINT64_C(1352663040), // PS_callr_nr |
| 1179 | UINT64_C(1384120320), // PS_jmpret |
| 1180 | UINT64_C(1398800384), // PS_jmpretf |
| 1181 | UINT64_C(1398802432), // PS_jmpretfnew |
| 1182 | UINT64_C(1398806528), // PS_jmpretfnewpt |
| 1183 | UINT64_C(1396703232), // PS_jmprett |
| 1184 | UINT64_C(1396705280), // PS_jmprettnew |
| 1185 | UINT64_C(1396709376), // PS_jmprettnewpt |
| 1186 | UINT64_C(1224736768), // PS_loadrbabs |
| 1187 | UINT64_C(1237319680), // PS_loadrdabs |
| 1188 | UINT64_C(1228931072), // PS_loadrhabs |
| 1189 | UINT64_C(1233125376), // PS_loadriabs |
| 1190 | UINT64_C(1226833920), // PS_loadrubabs |
| 1191 | UINT64_C(1231028224), // PS_loadruhabs |
| 1192 | UINT64_C(1207959552), // PS_storerbabs |
| 1193 | UINT64_C(1218445312), // PS_storerbnewabs |
| 1194 | UINT64_C(1220542464), // PS_storerdabs |
| 1195 | UINT64_C(1214251008), // PS_storerfabs |
| 1196 | UINT64_C(1212153856), // PS_storerhabs |
| 1197 | UINT64_C(1218447360), // PS_storerhnewabs |
| 1198 | UINT64_C(1216348160), // PS_storeriabs |
| 1199 | UINT64_C(1218449408), // PS_storerinewabs |
| 1200 | UINT64_C(1417674752), // PS_trap1 |
| 1201 | UINT64_C(2699034636), // R6_release_at_vi |
| 1202 | UINT64_C(2699034668), // R6_release_st_vi |
| 1203 | UINT64_C(1509949440), // RESTORE_DEALLOC_BEFORE_TAILCALL_V4 |
| 1204 | UINT64_C(1509949440), // RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT |
| 1205 | UINT64_C(1509949440), // RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT_PIC |
| 1206 | UINT64_C(1509949440), // RESTORE_DEALLOC_BEFORE_TAILCALL_V4_PIC |
| 1207 | UINT64_C(1476395008), // RESTORE_DEALLOC_RET_JMP_V4 |
| 1208 | UINT64_C(1476395008), // RESTORE_DEALLOC_RET_JMP_V4_EXT |
| 1209 | UINT64_C(1476395008), // RESTORE_DEALLOC_RET_JMP_V4_EXT_PIC |
| 1210 | UINT64_C(1476395008), // RESTORE_DEALLOC_RET_JMP_V4_PIC |
| 1211 | UINT64_C(3288334336), // S2_addasl_rrri |
| 1212 | UINT64_C(2692743168), // S2_allocframe |
| 1213 | UINT64_C(2147483712), // S2_asl_i_p |
| 1214 | UINT64_C(2181038272), // S2_asl_i_p_acc |
| 1215 | UINT64_C(2185232448), // S2_asl_i_p_and |
| 1216 | UINT64_C(2181038144), // S2_asl_i_p_nac |
| 1217 | UINT64_C(2185232576), // S2_asl_i_p_or |
| 1218 | UINT64_C(2189426752), // S2_asl_i_p_xacc |
| 1219 | UINT64_C(2348810304), // S2_asl_i_r |
| 1220 | UINT64_C(2382364864), // S2_asl_i_r_acc |
| 1221 | UINT64_C(2386559040), // S2_asl_i_r_and |
| 1222 | UINT64_C(2382364736), // S2_asl_i_r_nac |
| 1223 | UINT64_C(2386559168), // S2_asl_i_r_or |
| 1224 | UINT64_C(2353004608), // S2_asl_i_r_sat |
| 1225 | UINT64_C(2390753344), // S2_asl_i_r_xacc |
| 1226 | UINT64_C(2155872320), // S2_asl_i_vh |
| 1227 | UINT64_C(2151678016), // S2_asl_i_vw |
| 1228 | UINT64_C(3279945856), // S2_asl_r_p |
| 1229 | UINT64_C(3418357888), // S2_asl_r_p_acc |
| 1230 | UINT64_C(3409969280), // S2_asl_r_p_and |
| 1231 | UINT64_C(3414163584), // S2_asl_r_p_nac |
| 1232 | UINT64_C(3405774976), // S2_asl_r_p_or |
| 1233 | UINT64_C(3412066432), // S2_asl_r_p_xor |
| 1234 | UINT64_C(3326083200), // S2_asl_r_r |
| 1235 | UINT64_C(3435135104), // S2_asl_r_r_acc |
| 1236 | UINT64_C(3426746496), // S2_asl_r_r_and |
| 1237 | UINT64_C(3430940800), // S2_asl_r_r_nac |
| 1238 | UINT64_C(3422552192), // S2_asl_r_r_or |
| 1239 | UINT64_C(3321888896), // S2_asl_r_r_sat |
| 1240 | UINT64_C(3275751552), // S2_asl_r_vh |
| 1241 | UINT64_C(3271557248), // S2_asl_r_vw |
| 1242 | UINT64_C(2147483648), // S2_asr_i_p |
| 1243 | UINT64_C(2181038208), // S2_asr_i_p_acc |
| 1244 | UINT64_C(2185232384), // S2_asr_i_p_and |
| 1245 | UINT64_C(2181038080), // S2_asr_i_p_nac |
| 1246 | UINT64_C(2185232512), // S2_asr_i_p_or |
| 1247 | UINT64_C(2160066784), // S2_asr_i_p_rnd |
| 1248 | UINT64_C(2348810240), // S2_asr_i_r |
| 1249 | UINT64_C(2382364800), // S2_asr_i_r_acc |
| 1250 | UINT64_C(2386558976), // S2_asr_i_r_and |
| 1251 | UINT64_C(2382364672), // S2_asr_i_r_nac |
| 1252 | UINT64_C(2386559104), // S2_asr_i_r_or |
| 1253 | UINT64_C(2353004544), // S2_asr_i_r_rnd |
| 1254 | UINT64_C(2294284352), // S2_asr_i_svw_trun |
| 1255 | UINT64_C(2155872256), // S2_asr_i_vh |
| 1256 | UINT64_C(2151677952), // S2_asr_i_vw |
| 1257 | UINT64_C(3279945728), // S2_asr_r_p |
| 1258 | UINT64_C(3418357760), // S2_asr_r_p_acc |
| 1259 | UINT64_C(3409969152), // S2_asr_r_p_and |
| 1260 | UINT64_C(3414163456), // S2_asr_r_p_nac |
| 1261 | UINT64_C(3405774848), // S2_asr_r_p_or |
| 1262 | UINT64_C(3412066304), // S2_asr_r_p_xor |
| 1263 | UINT64_C(3326083072), // S2_asr_r_r |
| 1264 | UINT64_C(3435134976), // S2_asr_r_r_acc |
| 1265 | UINT64_C(3426746368), // S2_asr_r_r_and |
| 1266 | UINT64_C(3430940672), // S2_asr_r_r_nac |
| 1267 | UINT64_C(3422552064), // S2_asr_r_r_or |
| 1268 | UINT64_C(3321888768), // S2_asr_r_r_sat |
| 1269 | UINT64_C(3305111616), // S2_asr_r_svw_trun |
| 1270 | UINT64_C(3275751424), // S2_asr_r_vh |
| 1271 | UINT64_C(3271557120), // S2_asr_r_vw |
| 1272 | UINT64_C(2353004736), // S2_brev |
| 1273 | UINT64_C(2160066752), // S2_brevp |
| 1274 | UINT64_C(3250585792), // S2_cabacdecbin |
| 1275 | UINT64_C(2348810400), // S2_cl0 |
| 1276 | UINT64_C(2285895744), // S2_cl0p |
| 1277 | UINT64_C(2348810432), // S2_cl1 |
| 1278 | UINT64_C(2285895808), // S2_cl1p |
| 1279 | UINT64_C(2348810368), // S2_clb |
| 1280 | UINT64_C(2348810464), // S2_clbnorm |
| 1281 | UINT64_C(2285895680), // S2_clbp |
| 1282 | UINT64_C(2361393184), // S2_clrbit_i |
| 1283 | UINT64_C(3330277440), // S2_clrbit_r |
| 1284 | UINT64_C(2353004672), // S2_ct0 |
| 1285 | UINT64_C(2296381504), // S2_ct0p |
| 1286 | UINT64_C(2353004704), // S2_ct1 |
| 1287 | UINT64_C(2296381568), // S2_ct1p |
| 1288 | UINT64_C(2160066688), // S2_deinterleave |
| 1289 | UINT64_C(2365587456), // S2_extractu |
| 1290 | UINT64_C(3372220416), // S2_extractu_rp |
| 1291 | UINT64_C(2164260864), // S2_extractup |
| 1292 | UINT64_C(3238002688), // S2_extractup_rp |
| 1293 | UINT64_C(2399141888), // S2_insert |
| 1294 | UINT64_C(3355443200), // S2_insert_rp |
| 1295 | UINT64_C(2197815296), // S2_insertp |
| 1296 | UINT64_C(3388997632), // S2_insertp_rp |
| 1297 | UINT64_C(2160066720), // S2_interleave |
| 1298 | UINT64_C(3246391488), // S2_lfsp |
| 1299 | UINT64_C(3279945920), // S2_lsl_r_p |
| 1300 | UINT64_C(3418357952), // S2_lsl_r_p_acc |
| 1301 | UINT64_C(3409969344), // S2_lsl_r_p_and |
| 1302 | UINT64_C(3414163648), // S2_lsl_r_p_nac |
| 1303 | UINT64_C(3405775040), // S2_lsl_r_p_or |
| 1304 | UINT64_C(3412066496), // S2_lsl_r_p_xor |
| 1305 | UINT64_C(3326083264), // S2_lsl_r_r |
| 1306 | UINT64_C(3435135168), // S2_lsl_r_r_acc |
| 1307 | UINT64_C(3426746560), // S2_lsl_r_r_and |
| 1308 | UINT64_C(3430940864), // S2_lsl_r_r_nac |
| 1309 | UINT64_C(3422552256), // S2_lsl_r_r_or |
| 1310 | UINT64_C(3275751616), // S2_lsl_r_vh |
| 1311 | UINT64_C(3271557312), // S2_lsl_r_vw |
| 1312 | UINT64_C(2147483680), // S2_lsr_i_p |
| 1313 | UINT64_C(2181038240), // S2_lsr_i_p_acc |
| 1314 | UINT64_C(2185232416), // S2_lsr_i_p_and |
| 1315 | UINT64_C(2181038112), // S2_lsr_i_p_nac |
| 1316 | UINT64_C(2185232544), // S2_lsr_i_p_or |
| 1317 | UINT64_C(2189426720), // S2_lsr_i_p_xacc |
| 1318 | UINT64_C(2348810272), // S2_lsr_i_r |
| 1319 | UINT64_C(2382364832), // S2_lsr_i_r_acc |
| 1320 | UINT64_C(2386559008), // S2_lsr_i_r_and |
| 1321 | UINT64_C(2382364704), // S2_lsr_i_r_nac |
| 1322 | UINT64_C(2386559136), // S2_lsr_i_r_or |
| 1323 | UINT64_C(2390753312), // S2_lsr_i_r_xacc |
| 1324 | UINT64_C(2155872288), // S2_lsr_i_vh |
| 1325 | UINT64_C(2151677984), // S2_lsr_i_vw |
| 1326 | UINT64_C(3279945792), // S2_lsr_r_p |
| 1327 | UINT64_C(3418357824), // S2_lsr_r_p_acc |
| 1328 | UINT64_C(3409969216), // S2_lsr_r_p_and |
| 1329 | UINT64_C(3414163520), // S2_lsr_r_p_nac |
| 1330 | UINT64_C(3405774912), // S2_lsr_r_p_or |
| 1331 | UINT64_C(3412066368), // S2_lsr_r_p_xor |
| 1332 | UINT64_C(3326083136), // S2_lsr_r_r |
| 1333 | UINT64_C(3435135040), // S2_lsr_r_r_acc |
| 1334 | UINT64_C(3426746432), // S2_lsr_r_r_and |
| 1335 | UINT64_C(3430940736), // S2_lsr_r_r_nac |
| 1336 | UINT64_C(3422552128), // S2_lsr_r_r_or |
| 1337 | UINT64_C(3275751488), // S2_lsr_r_vh |
| 1338 | UINT64_C(3271557184), // S2_lsr_r_vw |
| 1339 | UINT64_C(2365595648), // S2_mask |
| 1340 | UINT64_C(4118806528), // S2_packhl |
| 1341 | UINT64_C(3489660928), // S2_parityp |
| 1342 | UINT64_C(1140850688), // S2_pstorerbf_io |
| 1343 | UINT64_C(2868912132), // S2_pstorerbf_pi |
| 1344 | UINT64_C(2868912260), // S2_pstorerbfnew_pi |
| 1345 | UINT64_C(1151336448), // S2_pstorerbnewf_io |
| 1346 | UINT64_C(2879397892), // S2_pstorerbnewf_pi |
| 1347 | UINT64_C(2879398020), // S2_pstorerbnewfnew_pi |
| 1348 | UINT64_C(1084227584), // S2_pstorerbnewt_io |
| 1349 | UINT64_C(2879397888), // S2_pstorerbnewt_pi |
| 1350 | UINT64_C(2879398016), // S2_pstorerbnewtnew_pi |
| 1351 | UINT64_C(1073741824), // S2_pstorerbt_io |
| 1352 | UINT64_C(2868912128), // S2_pstorerbt_pi |
| 1353 | UINT64_C(2868912256), // S2_pstorerbtnew_pi |
| 1354 | UINT64_C(1153433600), // S2_pstorerdf_io |
| 1355 | UINT64_C(2881495044), // S2_pstorerdf_pi |
| 1356 | UINT64_C(2881495172), // S2_pstorerdfnew_pi |
| 1357 | UINT64_C(1086324736), // S2_pstorerdt_io |
| 1358 | UINT64_C(2881495040), // S2_pstorerdt_pi |
| 1359 | UINT64_C(2881495168), // S2_pstorerdtnew_pi |
| 1360 | UINT64_C(1147142144), // S2_pstorerff_io |
| 1361 | UINT64_C(2875203588), // S2_pstorerff_pi |
| 1362 | UINT64_C(2875203716), // S2_pstorerffnew_pi |
| 1363 | UINT64_C(1080033280), // S2_pstorerft_io |
| 1364 | UINT64_C(2875203584), // S2_pstorerft_pi |
| 1365 | UINT64_C(2875203712), // S2_pstorerftnew_pi |
| 1366 | UINT64_C(1145044992), // S2_pstorerhf_io |
| 1367 | UINT64_C(2873106436), // S2_pstorerhf_pi |
| 1368 | UINT64_C(2873106564), // S2_pstorerhfnew_pi |
| 1369 | UINT64_C(1151338496), // S2_pstorerhnewf_io |
| 1370 | UINT64_C(2879399940), // S2_pstorerhnewf_pi |
| 1371 | UINT64_C(2879400068), // S2_pstorerhnewfnew_pi |
| 1372 | UINT64_C(1084229632), // S2_pstorerhnewt_io |
| 1373 | UINT64_C(2879399936), // S2_pstorerhnewt_pi |
| 1374 | UINT64_C(2879400064), // S2_pstorerhnewtnew_pi |
| 1375 | UINT64_C(1077936128), // S2_pstorerht_io |
| 1376 | UINT64_C(2873106432), // S2_pstorerht_pi |
| 1377 | UINT64_C(2873106560), // S2_pstorerhtnew_pi |
| 1378 | UINT64_C(1149239296), // S2_pstorerif_io |
| 1379 | UINT64_C(2877300740), // S2_pstorerif_pi |
| 1380 | UINT64_C(2877300868), // S2_pstorerifnew_pi |
| 1381 | UINT64_C(1151340544), // S2_pstorerinewf_io |
| 1382 | UINT64_C(2879401988), // S2_pstorerinewf_pi |
| 1383 | UINT64_C(2879402116), // S2_pstorerinewfnew_pi |
| 1384 | UINT64_C(1084231680), // S2_pstorerinewt_io |
| 1385 | UINT64_C(2879401984), // S2_pstorerinewt_pi |
| 1386 | UINT64_C(2879402112), // S2_pstorerinewtnew_pi |
| 1387 | UINT64_C(1082130432), // S2_pstorerit_io |
| 1388 | UINT64_C(2877300736), // S2_pstorerit_pi |
| 1389 | UINT64_C(2877300864), // S2_pstoreritnew_pi |
| 1390 | UINT64_C(2361393152), // S2_setbit_i |
| 1391 | UINT64_C(3330277376), // S2_setbit_r |
| 1392 | UINT64_C(3238002752), // S2_shuffeb |
| 1393 | UINT64_C(3238002880), // S2_shuffeh |
| 1394 | UINT64_C(3238002816), // S2_shuffob |
| 1395 | UINT64_C(3246391296), // S2_shuffoh |
| 1396 | UINT64_C(2701131776), // S2_storerb_io |
| 1397 | UINT64_C(2936012800), // S2_storerb_pbr |
| 1398 | UINT64_C(2835349504), // S2_storerb_pci |
| 1399 | UINT64_C(2835349506), // S2_storerb_pcr |
| 1400 | UINT64_C(2868903936), // S2_storerb_pi |
| 1401 | UINT64_C(2902458368), // S2_storerb_pr |
| 1402 | UINT64_C(1207959552), // S2_storerbgp |
| 1403 | UINT64_C(2711617536), // S2_storerbnew_io |
| 1404 | UINT64_C(2946498560), // S2_storerbnew_pbr |
| 1405 | UINT64_C(2845835264), // S2_storerbnew_pci |
| 1406 | UINT64_C(2845835266), // S2_storerbnew_pcr |
| 1407 | UINT64_C(2879389696), // S2_storerbnew_pi |
| 1408 | UINT64_C(2912944128), // S2_storerbnew_pr |
| 1409 | UINT64_C(1218445312), // S2_storerbnewgp |
| 1410 | UINT64_C(2713714688), // S2_storerd_io |
| 1411 | UINT64_C(2948595712), // S2_storerd_pbr |
| 1412 | UINT64_C(2847932416), // S2_storerd_pci |
| 1413 | UINT64_C(2847932418), // S2_storerd_pcr |
| 1414 | UINT64_C(2881486848), // S2_storerd_pi |
| 1415 | UINT64_C(2915041280), // S2_storerd_pr |
| 1416 | UINT64_C(1220542464), // S2_storerdgp |
| 1417 | UINT64_C(2707423232), // S2_storerf_io |
| 1418 | UINT64_C(2942304256), // S2_storerf_pbr |
| 1419 | UINT64_C(2841640960), // S2_storerf_pci |
| 1420 | UINT64_C(2841640962), // S2_storerf_pcr |
| 1421 | UINT64_C(2875195392), // S2_storerf_pi |
| 1422 | UINT64_C(2908749824), // S2_storerf_pr |
| 1423 | UINT64_C(1214251008), // S2_storerfgp |
| 1424 | UINT64_C(2705326080), // S2_storerh_io |
| 1425 | UINT64_C(2940207104), // S2_storerh_pbr |
| 1426 | UINT64_C(2839543808), // S2_storerh_pci |
| 1427 | UINT64_C(2839543810), // S2_storerh_pcr |
| 1428 | UINT64_C(2873098240), // S2_storerh_pi |
| 1429 | UINT64_C(2906652672), // S2_storerh_pr |
| 1430 | UINT64_C(1212153856), // S2_storerhgp |
| 1431 | UINT64_C(2711619584), // S2_storerhnew_io |
| 1432 | UINT64_C(2946500608), // S2_storerhnew_pbr |
| 1433 | UINT64_C(2845837312), // S2_storerhnew_pci |
| 1434 | UINT64_C(2845837314), // S2_storerhnew_pcr |
| 1435 | UINT64_C(2879391744), // S2_storerhnew_pi |
| 1436 | UINT64_C(2912946176), // S2_storerhnew_pr |
| 1437 | UINT64_C(1218447360), // S2_storerhnewgp |
| 1438 | UINT64_C(2709520384), // S2_storeri_io |
| 1439 | UINT64_C(2944401408), // S2_storeri_pbr |
| 1440 | UINT64_C(2843738112), // S2_storeri_pci |
| 1441 | UINT64_C(2843738114), // S2_storeri_pcr |
| 1442 | UINT64_C(2877292544), // S2_storeri_pi |
| 1443 | UINT64_C(2910846976), // S2_storeri_pr |
| 1444 | UINT64_C(1216348160), // S2_storerigp |
| 1445 | UINT64_C(2711621632), // S2_storerinew_io |
| 1446 | UINT64_C(2946502656), // S2_storerinew_pbr |
| 1447 | UINT64_C(2845839360), // S2_storerinew_pci |
| 1448 | UINT64_C(2845839362), // S2_storerinew_pcr |
| 1449 | UINT64_C(2879393792), // S2_storerinew_pi |
| 1450 | UINT64_C(2912948224), // S2_storerinew_pr |
| 1451 | UINT64_C(1218449408), // S2_storerinewgp |
| 1452 | UINT64_C(2694840320), // S2_storew_locked |
| 1453 | UINT64_C(2694840328), // S2_storew_rl_at_vi |
| 1454 | UINT64_C(2694840360), // S2_storew_rl_st_vi |
| 1455 | UINT64_C(2357198848), // S2_svsathb |
| 1456 | UINT64_C(2357198912), // S2_svsathub |
| 1457 | UINT64_C(2264924160), // S2_tableidxb |
| 1458 | UINT64_C(2277507072), // S2_tableidxd |
| 1459 | UINT64_C(2269118464), // S2_tableidxh |
| 1460 | UINT64_C(2273312768), // S2_tableidxw |
| 1461 | UINT64_C(2361393216), // S2_togglebit_i |
| 1462 | UINT64_C(3330277504), // S2_togglebit_r |
| 1463 | UINT64_C(2231369728), // S2_tstbit_i |
| 1464 | UINT64_C(3338665984), // S2_tstbit_r |
| 1465 | UINT64_C(3221225472), // S2_valignib |
| 1466 | UINT64_C(3254779904), // S2_valignrb |
| 1467 | UINT64_C(3284140096), // S2_vcnegh |
| 1468 | UINT64_C(3284140032), // S2_vcrotate |
| 1469 | UINT64_C(3407880416), // S2_vrcnegh |
| 1470 | UINT64_C(2290090112), // S2_vrndpackwh |
| 1471 | UINT64_C(2290090176), // S2_vrndpackwhs |
| 1472 | UINT64_C(2281701568), // S2_vsathb |
| 1473 | UINT64_C(2147483872), // S2_vsathb_nopack |
| 1474 | UINT64_C(2281701376), // S2_vsathub |
| 1475 | UINT64_C(2147483776), // S2_vsathub_nopack |
| 1476 | UINT64_C(2281701440), // S2_vsatwh |
| 1477 | UINT64_C(2147483840), // S2_vsatwh_nopack |
| 1478 | UINT64_C(2281701504), // S2_vsatwuh |
| 1479 | UINT64_C(2147483808), // S2_vsatwuh_nopack |
| 1480 | UINT64_C(2353004768), // S2_vsplatrb |
| 1481 | UINT64_C(2218786880), // S2_vsplatrh |
| 1482 | UINT64_C(3229614080), // S2_vspliceib |
| 1483 | UINT64_C(3263168512), // S2_vsplicerb |
| 1484 | UINT64_C(2214592512), // S2_vsxtbh |
| 1485 | UINT64_C(2214592640), // S2_vsxthw |
| 1486 | UINT64_C(2290090048), // S2_vtrunehb |
| 1487 | UINT64_C(3246391360), // S2_vtrunewh |
| 1488 | UINT64_C(2290089984), // S2_vtrunohb |
| 1489 | UINT64_C(3246391424), // S2_vtrunowh |
| 1490 | UINT64_C(2214592576), // S2_vzxtbh |
| 1491 | UINT64_C(2214592704), // S2_vzxthw |
| 1492 | UINT64_C(3674210304), // S4_addaddi |
| 1493 | UINT64_C(3724541956), // S4_addi_asl_ri |
| 1494 | UINT64_C(3724541972), // S4_addi_lsr_ri |
| 1495 | UINT64_C(3724541952), // S4_andi_asl_ri |
| 1496 | UINT64_C(3724541968), // S4_andi_lsr_ri |
| 1497 | UINT64_C(2350907392), // S4_clbaddi |
| 1498 | UINT64_C(2287992896), // S4_clbpaddi |
| 1499 | UINT64_C(2287992832), // S4_clbpnorm |
| 1500 | UINT64_C(2373976064), // S4_extract |
| 1501 | UINT64_C(3372220480), // S4_extract_rp |
| 1502 | UINT64_C(2315255808), // S4_extractp |
| 1503 | UINT64_C(3250585728), // S4_extractp_rp |
| 1504 | UINT64_C(3330277568), // S4_lsli |
| 1505 | UINT64_C(2233466880), // S4_ntstbit_i |
| 1506 | UINT64_C(3340763136), // S4_ntstbit_r |
| 1507 | UINT64_C(3657433088), // S4_or_andi |
| 1508 | UINT64_C(3661627392), // S4_or_andix |
| 1509 | UINT64_C(3665821696), // S4_or_ori |
| 1510 | UINT64_C(3724541954), // S4_ori_asl_ri |
| 1511 | UINT64_C(3724541970), // S4_ori_lsr_ri |
| 1512 | UINT64_C(3588227072), // S4_parity |
| 1513 | UINT64_C(2936012932), // S4_pstorerbf_abs |
| 1514 | UINT64_C(889192448), // S4_pstorerbf_rr |
| 1515 | UINT64_C(2936021124), // S4_pstorerbfnew_abs |
| 1516 | UINT64_C(1174405120), // S4_pstorerbfnew_io |
| 1517 | UINT64_C(922746880), // S4_pstorerbfnew_rr |
| 1518 | UINT64_C(2946498692), // S4_pstorerbnewf_abs |
| 1519 | UINT64_C(899678208), // S4_pstorerbnewf_rr |
| 1520 | UINT64_C(2946506884), // S4_pstorerbnewfnew_abs |
| 1521 | UINT64_C(1184890880), // S4_pstorerbnewfnew_io |
| 1522 | UINT64_C(933232640), // S4_pstorerbnewfnew_rr |
| 1523 | UINT64_C(2946498688), // S4_pstorerbnewt_abs |
| 1524 | UINT64_C(882900992), // S4_pstorerbnewt_rr |
| 1525 | UINT64_C(2946506880), // S4_pstorerbnewtnew_abs |
| 1526 | UINT64_C(1117782016), // S4_pstorerbnewtnew_io |
| 1527 | UINT64_C(916455424), // S4_pstorerbnewtnew_rr |
| 1528 | UINT64_C(2936012928), // S4_pstorerbt_abs |
| 1529 | UINT64_C(872415232), // S4_pstorerbt_rr |
| 1530 | UINT64_C(2936021120), // S4_pstorerbtnew_abs |
| 1531 | UINT64_C(1107296256), // S4_pstorerbtnew_io |
| 1532 | UINT64_C(905969664), // S4_pstorerbtnew_rr |
| 1533 | UINT64_C(2948595844), // S4_pstorerdf_abs |
| 1534 | UINT64_C(901775360), // S4_pstorerdf_rr |
| 1535 | UINT64_C(2948604036), // S4_pstorerdfnew_abs |
| 1536 | UINT64_C(1186988032), // S4_pstorerdfnew_io |
| 1537 | UINT64_C(935329792), // S4_pstorerdfnew_rr |
| 1538 | UINT64_C(2948595840), // S4_pstorerdt_abs |
| 1539 | UINT64_C(884998144), // S4_pstorerdt_rr |
| 1540 | UINT64_C(2948604032), // S4_pstorerdtnew_abs |
| 1541 | UINT64_C(1119879168), // S4_pstorerdtnew_io |
| 1542 | UINT64_C(918552576), // S4_pstorerdtnew_rr |
| 1543 | UINT64_C(2942304388), // S4_pstorerff_abs |
| 1544 | UINT64_C(895483904), // S4_pstorerff_rr |
| 1545 | UINT64_C(2942312580), // S4_pstorerffnew_abs |
| 1546 | UINT64_C(1180696576), // S4_pstorerffnew_io |
| 1547 | UINT64_C(929038336), // S4_pstorerffnew_rr |
| 1548 | UINT64_C(2942304384), // S4_pstorerft_abs |
| 1549 | UINT64_C(878706688), // S4_pstorerft_rr |
| 1550 | UINT64_C(2942312576), // S4_pstorerftnew_abs |
| 1551 | UINT64_C(1113587712), // S4_pstorerftnew_io |
| 1552 | UINT64_C(912261120), // S4_pstorerftnew_rr |
| 1553 | UINT64_C(2940207236), // S4_pstorerhf_abs |
| 1554 | UINT64_C(893386752), // S4_pstorerhf_rr |
| 1555 | UINT64_C(2940215428), // S4_pstorerhfnew_abs |
| 1556 | UINT64_C(1178599424), // S4_pstorerhfnew_io |
| 1557 | UINT64_C(926941184), // S4_pstorerhfnew_rr |
| 1558 | UINT64_C(2946500740), // S4_pstorerhnewf_abs |
| 1559 | UINT64_C(899678216), // S4_pstorerhnewf_rr |
| 1560 | UINT64_C(2946508932), // S4_pstorerhnewfnew_abs |
| 1561 | UINT64_C(1184892928), // S4_pstorerhnewfnew_io |
| 1562 | UINT64_C(933232648), // S4_pstorerhnewfnew_rr |
| 1563 | UINT64_C(2946500736), // S4_pstorerhnewt_abs |
| 1564 | UINT64_C(882901000), // S4_pstorerhnewt_rr |
| 1565 | UINT64_C(2946508928), // S4_pstorerhnewtnew_abs |
| 1566 | UINT64_C(1117784064), // S4_pstorerhnewtnew_io |
| 1567 | UINT64_C(916455432), // S4_pstorerhnewtnew_rr |
| 1568 | UINT64_C(2940207232), // S4_pstorerht_abs |
| 1569 | UINT64_C(876609536), // S4_pstorerht_rr |
| 1570 | UINT64_C(2940215424), // S4_pstorerhtnew_abs |
| 1571 | UINT64_C(1111490560), // S4_pstorerhtnew_io |
| 1572 | UINT64_C(910163968), // S4_pstorerhtnew_rr |
| 1573 | UINT64_C(2944401540), // S4_pstorerif_abs |
| 1574 | UINT64_C(897581056), // S4_pstorerif_rr |
| 1575 | UINT64_C(2944409732), // S4_pstorerifnew_abs |
| 1576 | UINT64_C(1182793728), // S4_pstorerifnew_io |
| 1577 | UINT64_C(931135488), // S4_pstorerifnew_rr |
| 1578 | UINT64_C(2946502788), // S4_pstorerinewf_abs |
| 1579 | UINT64_C(899678224), // S4_pstorerinewf_rr |
| 1580 | UINT64_C(2946510980), // S4_pstorerinewfnew_abs |
| 1581 | UINT64_C(1184894976), // S4_pstorerinewfnew_io |
| 1582 | UINT64_C(933232656), // S4_pstorerinewfnew_rr |
| 1583 | UINT64_C(2946502784), // S4_pstorerinewt_abs |
| 1584 | UINT64_C(882901008), // S4_pstorerinewt_rr |
| 1585 | UINT64_C(2946510976), // S4_pstorerinewtnew_abs |
| 1586 | UINT64_C(1117786112), // S4_pstorerinewtnew_io |
| 1587 | UINT64_C(916455440), // S4_pstorerinewtnew_rr |
| 1588 | UINT64_C(2944401536), // S4_pstorerit_abs |
| 1589 | UINT64_C(880803840), // S4_pstorerit_rr |
| 1590 | UINT64_C(2944409728), // S4_pstoreritnew_abs |
| 1591 | UINT64_C(1115684864), // S4_pstoreritnew_io |
| 1592 | UINT64_C(914358272), // S4_pstoreritnew_rr |
| 1593 | UINT64_C(2699034624), // S4_stored_locked |
| 1594 | UINT64_C(2699034632), // S4_stored_rl_at_vi |
| 1595 | UINT64_C(2699034664), // S4_stored_rl_st_vi |
| 1596 | UINT64_C(1006632960), // S4_storeirb_io |
| 1597 | UINT64_C(947912704), // S4_storeirbf_io |
| 1598 | UINT64_C(964689920), // S4_storeirbfnew_io |
| 1599 | UINT64_C(939524096), // S4_storeirbt_io |
| 1600 | UINT64_C(956301312), // S4_storeirbtnew_io |
| 1601 | UINT64_C(1008730112), // S4_storeirh_io |
| 1602 | UINT64_C(950009856), // S4_storeirhf_io |
| 1603 | UINT64_C(966787072), // S4_storeirhfnew_io |
| 1604 | UINT64_C(941621248), // S4_storeirht_io |
| 1605 | UINT64_C(958398464), // S4_storeirhtnew_io |
| 1606 | UINT64_C(1010827264), // S4_storeiri_io |
| 1607 | UINT64_C(952107008), // S4_storeirif_io |
| 1608 | UINT64_C(968884224), // S4_storeirifnew_io |
| 1609 | UINT64_C(943718400), // S4_storeirit_io |
| 1610 | UINT64_C(960495616), // S4_storeiritnew_io |
| 1611 | UINT64_C(2868904064), // S4_storerb_ap |
| 1612 | UINT64_C(989855744), // S4_storerb_rr |
| 1613 | UINT64_C(2902458496), // S4_storerb_ur |
| 1614 | UINT64_C(2879389824), // S4_storerbnew_ap |
| 1615 | UINT64_C(1000341504), // S4_storerbnew_rr |
| 1616 | UINT64_C(2912944256), // S4_storerbnew_ur |
| 1617 | UINT64_C(2881486976), // S4_storerd_ap |
| 1618 | UINT64_C(1002438656), // S4_storerd_rr |
| 1619 | UINT64_C(2915041408), // S4_storerd_ur |
| 1620 | UINT64_C(2875195520), // S4_storerf_ap |
| 1621 | UINT64_C(996147200), // S4_storerf_rr |
| 1622 | UINT64_C(2908749952), // S4_storerf_ur |
| 1623 | UINT64_C(2873098368), // S4_storerh_ap |
| 1624 | UINT64_C(994050048), // S4_storerh_rr |
| 1625 | UINT64_C(2906652800), // S4_storerh_ur |
| 1626 | UINT64_C(2879391872), // S4_storerhnew_ap |
| 1627 | UINT64_C(1000341512), // S4_storerhnew_rr |
| 1628 | UINT64_C(2912946304), // S4_storerhnew_ur |
| 1629 | UINT64_C(2877292672), // S4_storeri_ap |
| 1630 | UINT64_C(998244352), // S4_storeri_rr |
| 1631 | UINT64_C(2910847104), // S4_storeri_ur |
| 1632 | UINT64_C(2879393920), // S4_storerinew_ap |
| 1633 | UINT64_C(1000341520), // S4_storerinew_rr |
| 1634 | UINT64_C(2912948352), // S4_storerinew_ur |
| 1635 | UINT64_C(3682598912), // S4_subaddi |
| 1636 | UINT64_C(3724541958), // S4_subi_asl_ri |
| 1637 | UINT64_C(3724541974), // S4_subi_lsr_ri |
| 1638 | UINT64_C(3284140224), // S4_vrcrotate |
| 1639 | UINT64_C(3416260608), // S4_vrcrotate_acc |
| 1640 | UINT64_C(3242197120), // S4_vxaddsubh |
| 1641 | UINT64_C(3250585600), // S4_vxaddsubhr |
| 1642 | UINT64_C(3242196992), // S4_vxaddsubw |
| 1643 | UINT64_C(3242197184), // S4_vxsubaddh |
| 1644 | UINT64_C(3250585664), // S4_vxsubaddhr |
| 1645 | UINT64_C(3242197056), // S4_vxsubaddw |
| 1646 | UINT64_C(2287992960), // S5_asrhub_rnd_sat |
| 1647 | UINT64_C(2287992992), // S5_asrhub_sat |
| 1648 | UINT64_C(2287992928), // S5_popcountp |
| 1649 | UINT64_C(2149580800), // S5_vasrhrnd |
| 1650 | UINT64_C(2147483744), // S6_rol_i_p |
| 1651 | UINT64_C(2181038304), // S6_rol_i_p_acc |
| 1652 | UINT64_C(2185232480), // S6_rol_i_p_and |
| 1653 | UINT64_C(2181038176), // S6_rol_i_p_nac |
| 1654 | UINT64_C(2185232608), // S6_rol_i_p_or |
| 1655 | UINT64_C(2189426784), // S6_rol_i_p_xacc |
| 1656 | UINT64_C(2348810336), // S6_rol_i_r |
| 1657 | UINT64_C(2382364896), // S6_rol_i_r_acc |
| 1658 | UINT64_C(2386559072), // S6_rol_i_r_and |
| 1659 | UINT64_C(2382364768), // S6_rol_i_r_nac |
| 1660 | UINT64_C(2386559200), // S6_rol_i_r_or |
| 1661 | UINT64_C(2390753376), // S6_rol_i_r_xacc |
| 1662 | UINT64_C(2218786944), // S6_vsplatrbp |
| 1663 | UINT64_C(3246391392), // S6_vtrunehb_ppp |
| 1664 | UINT64_C(3246391456), // S6_vtrunohb_ppp |
| 1665 | UINT64_C(0), // SA1_addi |
| 1666 | UINT64_C(6144), // SA1_addrx |
| 1667 | UINT64_C(3072), // SA1_addsp |
| 1668 | UINT64_C(4608), // SA1_and1 |
| 1669 | UINT64_C(6768), // SA1_clrf |
| 1670 | UINT64_C(6736), // SA1_clrfnew |
| 1671 | UINT64_C(6752), // SA1_clrt |
| 1672 | UINT64_C(6720), // SA1_clrtnew |
| 1673 | UINT64_C(6400), // SA1_cmpeqi |
| 1674 | UINT64_C(7168), // SA1_combine0i |
| 1675 | UINT64_C(7176), // SA1_combine1i |
| 1676 | UINT64_C(7184), // SA1_combine2i |
| 1677 | UINT64_C(7192), // SA1_combine3i |
| 1678 | UINT64_C(7432), // SA1_combinerz |
| 1679 | UINT64_C(7424), // SA1_combinezr |
| 1680 | UINT64_C(4864), // SA1_dec |
| 1681 | UINT64_C(4352), // SA1_inc |
| 1682 | UINT64_C(2048), // SA1_seti |
| 1683 | UINT64_C(6656), // SA1_setin1 |
| 1684 | UINT64_C(5376), // SA1_sxtb |
| 1685 | UINT64_C(5120), // SA1_sxth |
| 1686 | UINT64_C(4096), // SA1_tfr |
| 1687 | UINT64_C(5888), // SA1_zxtb |
| 1688 | UINT64_C(5632), // SA1_zxth |
| 1689 | UINT64_C(1509949440), // SAVE_REGISTERS_CALL_V4 |
| 1690 | UINT64_C(1509949440), // SAVE_REGISTERS_CALL_V4STK |
| 1691 | UINT64_C(1509949440), // SAVE_REGISTERS_CALL_V4STK_EXT |
| 1692 | UINT64_C(1509949440), // SAVE_REGISTERS_CALL_V4STK_EXT_PIC |
| 1693 | UINT64_C(1509949440), // SAVE_REGISTERS_CALL_V4STK_PIC |
| 1694 | UINT64_C(1509949440), // SAVE_REGISTERS_CALL_V4_EXT |
| 1695 | UINT64_C(1509949440), // SAVE_REGISTERS_CALL_V4_EXT_PIC |
| 1696 | UINT64_C(1509949440), // SAVE_REGISTERS_CALL_V4_PIC |
| 1697 | UINT64_C(0), // SL1_loadri_io |
| 1698 | UINT64_C(4096), // SL1_loadrub_io |
| 1699 | UINT64_C(7936), // SL2_deallocframe |
| 1700 | UINT64_C(8128), // SL2_jumpr31 |
| 1701 | UINT64_C(8133), // SL2_jumpr31_f |
| 1702 | UINT64_C(8135), // SL2_jumpr31_fnew |
| 1703 | UINT64_C(8132), // SL2_jumpr31_t |
| 1704 | UINT64_C(8134), // SL2_jumpr31_tnew |
| 1705 | UINT64_C(4096), // SL2_loadrb_io |
| 1706 | UINT64_C(7680), // SL2_loadrd_sp |
| 1707 | UINT64_C(0), // SL2_loadrh_io |
| 1708 | UINT64_C(7168), // SL2_loadri_sp |
| 1709 | UINT64_C(2048), // SL2_loadruh_io |
| 1710 | UINT64_C(8000), // SL2_return |
| 1711 | UINT64_C(8005), // SL2_return_f |
| 1712 | UINT64_C(8007), // SL2_return_fnew |
| 1713 | UINT64_C(8004), // SL2_return_t |
| 1714 | UINT64_C(8006), // SL2_return_tnew |
| 1715 | UINT64_C(4096), // SS1_storeb_io |
| 1716 | UINT64_C(0), // SS1_storew_io |
| 1717 | UINT64_C(7168), // SS2_allocframe |
| 1718 | UINT64_C(4608), // SS2_storebi0 |
| 1719 | UINT64_C(4864), // SS2_storebi1 |
| 1720 | UINT64_C(2560), // SS2_stored_sp |
| 1721 | UINT64_C(0), // SS2_storeh_io |
| 1722 | UINT64_C(2048), // SS2_storew_sp |
| 1723 | UINT64_C(4096), // SS2_storewi0 |
| 1724 | UINT64_C(4352), // SS2_storewi1 |
| 1725 | UINT64_C(0), // TFRI64_V2_ext |
| 1726 | UINT64_C(0), // TFRI64_V4 |
| 1727 | UINT64_C(2449473568), // V6_extractw |
| 1728 | UINT64_C(432013536), // V6_get_qfext |
| 1729 | UINT64_C(432013504), // V6_get_qfext_oracc |
| 1730 | UINT64_C(432013376), // V6_lvsplatb |
| 1731 | UINT64_C(432013344), // V6_lvsplath |
| 1732 | UINT64_C(429916192), // V6_lvsplatw |
| 1733 | UINT64_C(503513088), // V6_pred_and |
| 1734 | UINT64_C(503513108), // V6_pred_and_n |
| 1735 | UINT64_C(503513096), // V6_pred_not |
| 1736 | UINT64_C(503513092), // V6_pred_or |
| 1737 | UINT64_C(503513104), // V6_pred_or_n |
| 1738 | UINT64_C(429916228), // V6_pred_scalar2 |
| 1739 | UINT64_C(429916236), // V6_pred_scalar2v2 |
| 1740 | UINT64_C(503513100), // V6_pred_xor |
| 1741 | UINT64_C(432013408), // V6_set_qfext |
| 1742 | UINT64_C(503513112), // V6_shuffeqh |
| 1743 | UINT64_C(503513116), // V6_shuffeqw |
| 1744 | UINT64_C(524296320), // V6_v6mpyhubs10 |
| 1745 | UINT64_C(522199168), // V6_v6mpyhubs10_vxx |
| 1746 | UINT64_C(524296192), // V6_v6mpyvubs10 |
| 1747 | UINT64_C(522199040), // V6_v6mpyvubs10_vxx |
| 1748 | UINT64_C(671088864), // V6_vL32Ub_ai |
| 1749 | UINT64_C(687866080), // V6_vL32Ub_pi |
| 1750 | UINT64_C(721420512), // V6_vL32Ub_ppu |
| 1751 | UINT64_C(671088640), // V6_vL32b_ai |
| 1752 | UINT64_C(671088672), // V6_vL32b_cur_ai |
| 1753 | UINT64_C(679477408), // V6_vL32b_cur_npred_ai |
| 1754 | UINT64_C(696254624), // V6_vL32b_cur_npred_pi |
| 1755 | UINT64_C(729809056), // V6_vL32b_cur_npred_ppu |
| 1756 | UINT64_C(687865888), // V6_vL32b_cur_pi |
| 1757 | UINT64_C(721420320), // V6_vL32b_cur_ppu |
| 1758 | UINT64_C(679477376), // V6_vL32b_cur_pred_ai |
| 1759 | UINT64_C(696254592), // V6_vL32b_cur_pred_pi |
| 1760 | UINT64_C(729809024), // V6_vL32b_cur_pred_ppu |
| 1761 | UINT64_C(679477344), // V6_vL32b_npred_ai |
| 1762 | UINT64_C(696254560), // V6_vL32b_npred_pi |
| 1763 | UINT64_C(729808992), // V6_vL32b_npred_ppu |
| 1764 | UINT64_C(675282944), // V6_vL32b_nt_ai |
| 1765 | UINT64_C(675282976), // V6_vL32b_nt_cur_ai |
| 1766 | UINT64_C(683671712), // V6_vL32b_nt_cur_npred_ai |
| 1767 | UINT64_C(700448928), // V6_vL32b_nt_cur_npred_pi |
| 1768 | UINT64_C(734003360), // V6_vL32b_nt_cur_npred_ppu |
| 1769 | UINT64_C(692060192), // V6_vL32b_nt_cur_pi |
| 1770 | UINT64_C(725614624), // V6_vL32b_nt_cur_ppu |
| 1771 | UINT64_C(683671680), // V6_vL32b_nt_cur_pred_ai |
| 1772 | UINT64_C(700448896), // V6_vL32b_nt_cur_pred_pi |
| 1773 | UINT64_C(734003328), // V6_vL32b_nt_cur_pred_ppu |
| 1774 | UINT64_C(683671648), // V6_vL32b_nt_npred_ai |
| 1775 | UINT64_C(700448864), // V6_vL32b_nt_npred_pi |
| 1776 | UINT64_C(734003296), // V6_vL32b_nt_npred_ppu |
| 1777 | UINT64_C(692060160), // V6_vL32b_nt_pi |
| 1778 | UINT64_C(725614592), // V6_vL32b_nt_ppu |
| 1779 | UINT64_C(683671616), // V6_vL32b_nt_pred_ai |
| 1780 | UINT64_C(700448832), // V6_vL32b_nt_pred_pi |
| 1781 | UINT64_C(734003264), // V6_vL32b_nt_pred_ppu |
| 1782 | UINT64_C(675283008), // V6_vL32b_nt_tmp_ai |
| 1783 | UINT64_C(683671776), // V6_vL32b_nt_tmp_npred_ai |
| 1784 | UINT64_C(700448992), // V6_vL32b_nt_tmp_npred_pi |
| 1785 | UINT64_C(734003424), // V6_vL32b_nt_tmp_npred_ppu |
| 1786 | UINT64_C(692060224), // V6_vL32b_nt_tmp_pi |
| 1787 | UINT64_C(725614656), // V6_vL32b_nt_tmp_ppu |
| 1788 | UINT64_C(683671744), // V6_vL32b_nt_tmp_pred_ai |
| 1789 | UINT64_C(700448960), // V6_vL32b_nt_tmp_pred_pi |
| 1790 | UINT64_C(734003392), // V6_vL32b_nt_tmp_pred_ppu |
| 1791 | UINT64_C(687865856), // V6_vL32b_pi |
| 1792 | UINT64_C(721420288), // V6_vL32b_ppu |
| 1793 | UINT64_C(679477312), // V6_vL32b_pred_ai |
| 1794 | UINT64_C(696254528), // V6_vL32b_pred_pi |
| 1795 | UINT64_C(729808960), // V6_vL32b_pred_ppu |
| 1796 | UINT64_C(671088704), // V6_vL32b_tmp_ai |
| 1797 | UINT64_C(679477472), // V6_vL32b_tmp_npred_ai |
| 1798 | UINT64_C(696254688), // V6_vL32b_tmp_npred_pi |
| 1799 | UINT64_C(729809120), // V6_vL32b_tmp_npred_ppu |
| 1800 | UINT64_C(687865920), // V6_vL32b_tmp_pi |
| 1801 | UINT64_C(721420352), // V6_vL32b_tmp_ppu |
| 1802 | UINT64_C(679477440), // V6_vL32b_tmp_pred_ai |
| 1803 | UINT64_C(696254656), // V6_vL32b_tmp_pred_pi |
| 1804 | UINT64_C(729809088), // V6_vL32b_tmp_pred_ppu |
| 1805 | UINT64_C(673186016), // V6_vS32Ub_ai |
| 1806 | UINT64_C(681574624), // V6_vS32Ub_npred_ai |
| 1807 | UINT64_C(698351840), // V6_vS32Ub_npred_pi |
| 1808 | UINT64_C(731906272), // V6_vS32Ub_npred_ppu |
| 1809 | UINT64_C(689963232), // V6_vS32Ub_pi |
| 1810 | UINT64_C(723517664), // V6_vS32Ub_ppu |
| 1811 | UINT64_C(681574592), // V6_vS32Ub_pred_ai |
| 1812 | UINT64_C(698351808), // V6_vS32Ub_pred_pi |
| 1813 | UINT64_C(731906240), // V6_vS32Ub_pred_ppu |
| 1814 | UINT64_C(673185792), // V6_vS32b_ai |
| 1815 | UINT64_C(673185824), // V6_vS32b_new_ai |
| 1816 | UINT64_C(681574504), // V6_vS32b_new_npred_ai |
| 1817 | UINT64_C(698351720), // V6_vS32b_new_npred_pi |
| 1818 | UINT64_C(731906152), // V6_vS32b_new_npred_ppu |
| 1819 | UINT64_C(689963040), // V6_vS32b_new_pi |
| 1820 | UINT64_C(723517472), // V6_vS32b_new_ppu |
| 1821 | UINT64_C(681574464), // V6_vS32b_new_pred_ai |
| 1822 | UINT64_C(698351680), // V6_vS32b_new_pred_pi |
| 1823 | UINT64_C(731906112), // V6_vS32b_new_pred_ppu |
| 1824 | UINT64_C(681574432), // V6_vS32b_npred_ai |
| 1825 | UINT64_C(698351648), // V6_vS32b_npred_pi |
| 1826 | UINT64_C(731906080), // V6_vS32b_npred_ppu |
| 1827 | UINT64_C(679477280), // V6_vS32b_nqpred_ai |
| 1828 | UINT64_C(696254496), // V6_vS32b_nqpred_pi |
| 1829 | UINT64_C(729808928), // V6_vS32b_nqpred_ppu |
| 1830 | UINT64_C(677380096), // V6_vS32b_nt_ai |
| 1831 | UINT64_C(677380128), // V6_vS32b_nt_new_ai |
| 1832 | UINT64_C(685768824), // V6_vS32b_nt_new_npred_ai |
| 1833 | UINT64_C(702546040), // V6_vS32b_nt_new_npred_pi |
| 1834 | UINT64_C(736100472), // V6_vS32b_nt_new_npred_ppu |
| 1835 | UINT64_C(694157344), // V6_vS32b_nt_new_pi |
| 1836 | UINT64_C(727711776), // V6_vS32b_nt_new_ppu |
| 1837 | UINT64_C(685768784), // V6_vS32b_nt_new_pred_ai |
| 1838 | UINT64_C(702546000), // V6_vS32b_nt_new_pred_pi |
| 1839 | UINT64_C(736100432), // V6_vS32b_nt_new_pred_ppu |
| 1840 | UINT64_C(685768736), // V6_vS32b_nt_npred_ai |
| 1841 | UINT64_C(702545952), // V6_vS32b_nt_npred_pi |
| 1842 | UINT64_C(736100384), // V6_vS32b_nt_npred_ppu |
| 1843 | UINT64_C(683671584), // V6_vS32b_nt_nqpred_ai |
| 1844 | UINT64_C(700448800), // V6_vS32b_nt_nqpred_pi |
| 1845 | UINT64_C(734003232), // V6_vS32b_nt_nqpred_ppu |
| 1846 | UINT64_C(694157312), // V6_vS32b_nt_pi |
| 1847 | UINT64_C(727711744), // V6_vS32b_nt_ppu |
| 1848 | UINT64_C(685768704), // V6_vS32b_nt_pred_ai |
| 1849 | UINT64_C(702545920), // V6_vS32b_nt_pred_pi |
| 1850 | UINT64_C(736100352), // V6_vS32b_nt_pred_ppu |
| 1851 | UINT64_C(683671552), // V6_vS32b_nt_qpred_ai |
| 1852 | UINT64_C(700448768), // V6_vS32b_nt_qpred_pi |
| 1853 | UINT64_C(734003200), // V6_vS32b_nt_qpred_ppu |
| 1854 | UINT64_C(689963008), // V6_vS32b_pi |
| 1855 | UINT64_C(723517440), // V6_vS32b_ppu |
| 1856 | UINT64_C(681574400), // V6_vS32b_pred_ai |
| 1857 | UINT64_C(698351616), // V6_vS32b_pred_pi |
| 1858 | UINT64_C(731906048), // V6_vS32b_pred_ppu |
| 1859 | UINT64_C(679477248), // V6_vS32b_qpred_ai |
| 1860 | UINT64_C(696254464), // V6_vS32b_qpred_pi |
| 1861 | UINT64_C(729808896), // V6_vS32b_qpred_ppu |
| 1862 | UINT64_C(673185832), // V6_vS32b_srls_ai |
| 1863 | UINT64_C(689963048), // V6_vS32b_srls_pi |
| 1864 | UINT64_C(723517480), // V6_vS32b_srls_ppu |
| 1865 | UINT64_C(476455104), // V6_vabs_f8 |
| 1866 | UINT64_C(503718016), // V6_vabs_hf |
| 1867 | UINT64_C(504242368), // V6_vabs_qf16_hf |
| 1868 | UINT64_C(504242400), // V6_vabs_qf16_qf16 |
| 1869 | UINT64_C(504242336), // V6_vabs_qf32_qf32 |
| 1870 | UINT64_C(504242304), // V6_vabs_qf32_sf |
| 1871 | UINT64_C(503718048), // V6_vabs_sf |
| 1872 | UINT64_C(503382144), // V6_vabsb |
| 1873 | UINT64_C(503382176), // V6_vabsb_sat |
| 1874 | UINT64_C(482344992), // V6_vabsdiffh |
| 1875 | UINT64_C(482344960), // V6_vabsdiffub |
| 1876 | UINT64_C(482345024), // V6_vabsdiffuh |
| 1877 | UINT64_C(482345056), // V6_vabsdiffw |
| 1878 | UINT64_C(503316480), // V6_vabsh |
| 1879 | UINT64_C(503316512), // V6_vabsh_sat |
| 1880 | UINT64_C(503316544), // V6_vabsw |
| 1881 | UINT64_C(503316576), // V6_vabsw_sat |
| 1882 | UINT64_C(526393440), // V6_vadd_hf |
| 1883 | UINT64_C(528482432), // V6_vadd_hf_f8 |
| 1884 | UINT64_C(530587872), // V6_vadd_hf_hf |
| 1885 | UINT64_C(526393408), // V6_vadd_qf16 |
| 1886 | UINT64_C(526393472), // V6_vadd_qf16_mix |
| 1887 | UINT64_C(530587648), // V6_vadd_qf32 |
| 1888 | UINT64_C(530587712), // V6_vadd_qf32_mix |
| 1889 | UINT64_C(530587680), // V6_vadd_sf |
| 1890 | UINT64_C(490741952), // V6_vadd_sf_bf |
| 1891 | UINT64_C(528490624), // V6_vadd_sf_hf |
| 1892 | UINT64_C(528490688), // V6_vadd_sf_sf |
| 1893 | UINT64_C(530579648), // V6_vaddb |
| 1894 | UINT64_C(476053632), // V6_vaddb_dv |
| 1895 | UINT64_C(503390304), // V6_vaddbnq |
| 1896 | UINT64_C(503390208), // V6_vaddbq |
| 1897 | UINT64_C(520093696), // V6_vaddbsat |
| 1898 | UINT64_C(513802240), // V6_vaddbsat_dv |
| 1899 | UINT64_C(480256000), // V6_vaddcarry |
| 1900 | UINT64_C(497033216), // V6_vaddcarryo |
| 1901 | UINT64_C(494936064), // V6_vaddcarrysat |
| 1902 | UINT64_C(520101888), // V6_vaddclbh |
| 1903 | UINT64_C(520101920), // V6_vaddclbw |
| 1904 | UINT64_C(530579680), // V6_vaddh |
| 1905 | UINT64_C(476053664), // V6_vaddh_dv |
| 1906 | UINT64_C(503390336), // V6_vaddhnq |
| 1907 | UINT64_C(503390240), // V6_vaddhq |
| 1908 | UINT64_C(473956448), // V6_vaddhsat |
| 1909 | UINT64_C(478150688), // V6_vaddhsat_dv |
| 1910 | UINT64_C(480247936), // V6_vaddhw |
| 1911 | UINT64_C(471867456), // V6_vaddhw_acc |
| 1912 | UINT64_C(480247872), // V6_vaddubh |
| 1913 | UINT64_C(473964704), // V6_vaddubh_acc |
| 1914 | UINT64_C(473956384), // V6_vaddubsat |
| 1915 | UINT64_C(476053728), // V6_vaddubsat_dv |
| 1916 | UINT64_C(513802368), // V6_vaddububb_sat |
| 1917 | UINT64_C(473956416), // V6_vadduhsat |
| 1918 | UINT64_C(478150656), // V6_vadduhsat_dv |
| 1919 | UINT64_C(480247904), // V6_vadduhw |
| 1920 | UINT64_C(473964672), // V6_vadduhw_acc |
| 1921 | UINT64_C(526385184), // V6_vadduwsat |
| 1922 | UINT64_C(513802304), // V6_vadduwsat_dv |
| 1923 | UINT64_C(473956352), // V6_vaddw |
| 1924 | UINT64_C(476053696), // V6_vaddw_dv |
| 1925 | UINT64_C(503390368), // V6_vaddwnq |
| 1926 | UINT64_C(503390272), // V6_vaddwq |
| 1927 | UINT64_C(473956480), // V6_vaddwsat |
| 1928 | UINT64_C(478150720), // V6_vaddwsat_dv |
| 1929 | UINT64_C(402653344), // V6_valign4 |
| 1930 | UINT64_C(452984832), // V6_valignb |
| 1931 | UINT64_C(505421824), // V6_valignbi |
| 1932 | UINT64_C(471859360), // V6_vand |
| 1933 | UINT64_C(429917344), // V6_vandnqrt |
| 1934 | UINT64_C(425731168), // V6_vandnqrt_acc |
| 1935 | UINT64_C(429916320), // V6_vandqrt |
| 1936 | UINT64_C(425730144), // V6_vandqrt_acc |
| 1937 | UINT64_C(503521312), // V6_vandvnqv |
| 1938 | UINT64_C(503521280), // V6_vandvqv |
| 1939 | UINT64_C(429916232), // V6_vandvrt |
| 1940 | UINT64_C(425730176), // V6_vandvrt_acc |
| 1941 | UINT64_C(427819008), // V6_vaslh |
| 1942 | UINT64_C(429924512), // V6_vaslh_acc |
| 1943 | UINT64_C(530579616), // V6_vaslhv |
| 1944 | UINT64_C(425722080), // V6_vaslw |
| 1945 | UINT64_C(425730112), // V6_vaslw_acc |
| 1946 | UINT64_C(530579584), // V6_vaslwv |
| 1947 | UINT64_C(446701792), // V6_vasr_into |
| 1948 | UINT64_C(425722048), // V6_vasrh |
| 1949 | UINT64_C(427827424), // V6_vasrh_acc |
| 1950 | UINT64_C(452993024), // V6_vasrhbrndsat |
| 1951 | UINT64_C(402653184), // V6_vasrhbsat |
| 1952 | UINT64_C(452985056), // V6_vasrhubrndsat |
| 1953 | UINT64_C(452985024), // V6_vasrhubsat |
| 1954 | UINT64_C(530579552), // V6_vasrhv |
| 1955 | UINT64_C(402653408), // V6_vasruhubrndsat |
| 1956 | UINT64_C(402661536), // V6_vasruhubsat |
| 1957 | UINT64_C(402653216), // V6_vasruwuhrndsat |
| 1958 | UINT64_C(402661504), // V6_vasruwuhsat |
| 1959 | UINT64_C(486539360), // V6_vasrvuhubrndsat |
| 1960 | UINT64_C(486539328), // V6_vasrvuhubsat |
| 1961 | UINT64_C(486539296), // V6_vasrvwuhrndsat |
| 1962 | UINT64_C(486539264), // V6_vasrvwuhsat |
| 1963 | UINT64_C(425722016), // V6_vasrw |
| 1964 | UINT64_C(425730208), // V6_vasrw_acc |
| 1965 | UINT64_C(452984896), // V6_vasrwh |
| 1966 | UINT64_C(452984960), // V6_vasrwhrndsat |
| 1967 | UINT64_C(452984928), // V6_vasrwhsat |
| 1968 | UINT64_C(402653248), // V6_vasrwuhrndsat |
| 1969 | UINT64_C(452984992), // V6_vasrwuhsat |
| 1970 | UINT64_C(530579456), // V6_vasrwv |
| 1971 | UINT64_C(503521504), // V6_vassign |
| 1972 | UINT64_C(503717920), // V6_vassign_fp |
| 1973 | UINT64_C(503382208), // V6_vassign_tmp |
| 1974 | UINT64_C(520102016), // V6_vavgb |
| 1975 | UINT64_C(520102048), // V6_vavgbrnd |
| 1976 | UINT64_C(482345152), // V6_vavgh |
| 1977 | UINT64_C(484442272), // V6_vavghrnd |
| 1978 | UINT64_C(482345088), // V6_vavgub |
| 1979 | UINT64_C(484442208), // V6_vavgubrnd |
| 1980 | UINT64_C(482345120), // V6_vavguh |
| 1981 | UINT64_C(484442240), // V6_vavguhrnd |
| 1982 | UINT64_C(520101952), // V6_vavguw |
| 1983 | UINT64_C(520101984), // V6_vavguwrnd |
| 1984 | UINT64_C(482345184), // V6_vavgw |
| 1985 | UINT64_C(484442304), // V6_vavgwrnd |
| 1986 | UINT64_C(442499072), // V6_vccombine |
| 1987 | UINT64_C(503447776), // V6_vcl0h |
| 1988 | UINT64_C(503447712), // V6_vcl0w |
| 1989 | UINT64_C(436207616), // V6_vcmov |
| 1990 | UINT64_C(524288224), // V6_vcombine |
| 1991 | UINT64_C(513802464), // V6_vcombine_tmp |
| 1992 | UINT64_C(503718112), // V6_vconv_bf_qf32 |
| 1993 | UINT64_C(504111328), // V6_vconv_f8_qf16 |
| 1994 | UINT64_C(503652416), // V6_vconv_h_hf |
| 1995 | UINT64_C(503718080), // V6_vconv_h_hf_rnd |
| 1996 | UINT64_C(503652480), // V6_vconv_hf_h |
| 1997 | UINT64_C(503586912), // V6_vconv_hf_qf16 |
| 1998 | UINT64_C(503587008), // V6_vconv_hf_qf32 |
| 1999 | UINT64_C(504111264), // V6_vconv_qf16_f8 |
| 2000 | UINT64_C(504111232), // V6_vconv_qf16_hf |
| 2001 | UINT64_C(504111296), // V6_vconv_qf16_qf16 |
| 2002 | UINT64_C(504176864), // V6_vconv_qf32_qf32 |
| 2003 | UINT64_C(504176832), // V6_vconv_qf32_sf |
| 2004 | UINT64_C(503586816), // V6_vconv_sf_qf32 |
| 2005 | UINT64_C(503652448), // V6_vconv_sf_w |
| 2006 | UINT64_C(503652384), // V6_vconv_w_sf |
| 2007 | UINT64_C(448798912), // V6_vcvt2_b_hf |
| 2008 | UINT64_C(517284032), // V6_vcvt2_hf_b |
| 2009 | UINT64_C(517284064), // V6_vcvt2_hf_ub |
| 2010 | UINT64_C(448798944), // V6_vcvt2_ub_hf |
| 2011 | UINT64_C(532684992), // V6_vcvt_b_hf |
| 2012 | UINT64_C(490741856), // V6_vcvt_bf_sf |
| 2013 | UINT64_C(534782016), // V6_vcvt_f8_hf |
| 2014 | UINT64_C(503717888), // V6_vcvt_h_hf |
| 2015 | UINT64_C(503586880), // V6_vcvt_hf_b |
| 2016 | UINT64_C(503652512), // V6_vcvt_hf_f8 |
| 2017 | UINT64_C(503587040), // V6_vcvt_hf_h |
| 2018 | UINT64_C(526393376), // V6_vcvt_hf_sf |
| 2019 | UINT64_C(503586848), // V6_vcvt_hf_ub |
| 2020 | UINT64_C(503586976), // V6_vcvt_hf_uh |
| 2021 | UINT64_C(503586944), // V6_vcvt_sf_hf |
| 2022 | UINT64_C(532684960), // V6_vcvt_ub_hf |
| 2023 | UINT64_C(503652352), // V6_vcvt_uh_hf |
| 2024 | UINT64_C(434118720), // V6_vdeal |
| 2025 | UINT64_C(503316704), // V6_vdealb |
| 2026 | UINT64_C(522191072), // V6_vdealb4w |
| 2027 | UINT64_C(503316672), // V6_vdealh |
| 2028 | UINT64_C(452993152), // V6_vdealvdd |
| 2029 | UINT64_C(522190880), // V6_vdelta |
| 2030 | UINT64_C(530587840), // V6_vdmpy_sf_hf |
| 2031 | UINT64_C(473964640), // V6_vdmpy_sf_hf_acc |
| 2032 | UINT64_C(419430592), // V6_vdmpybus |
| 2033 | UINT64_C(419438784), // V6_vdmpybus_acc |
| 2034 | UINT64_C(419430624), // V6_vdmpybus_dv |
| 2035 | UINT64_C(419438816), // V6_vdmpybus_dv_acc |
| 2036 | UINT64_C(419430464), // V6_vdmpyhb |
| 2037 | UINT64_C(419438688), // V6_vdmpyhb_acc |
| 2038 | UINT64_C(421527680), // V6_vdmpyhb_dv |
| 2039 | UINT64_C(421535872), // V6_vdmpyhb_dv_acc |
| 2040 | UINT64_C(421527648), // V6_vdmpyhisat |
| 2041 | UINT64_C(421535808), // V6_vdmpyhisat_acc |
| 2042 | UINT64_C(421527616), // V6_vdmpyhsat |
| 2043 | UINT64_C(421535840), // V6_vdmpyhsat_acc |
| 2044 | UINT64_C(421527584), // V6_vdmpyhsuisat |
| 2045 | UINT64_C(421535776), // V6_vdmpyhsuisat_acc |
| 2046 | UINT64_C(421527552), // V6_vdmpyhsusat |
| 2047 | UINT64_C(421535744), // V6_vdmpyhsusat_acc |
| 2048 | UINT64_C(469762144), // V6_vdmpyhvsat |
| 2049 | UINT64_C(469770336), // V6_vdmpyhvsat_acc |
| 2050 | UINT64_C(419430560), // V6_vdsaduh |
| 2051 | UINT64_C(425730048), // V6_vdsaduh_acc |
| 2052 | UINT64_C(528482304), // V6_veqb |
| 2053 | UINT64_C(478158848), // V6_veqb_and |
| 2054 | UINT64_C(478158912), // V6_veqb_or |
| 2055 | UINT64_C(478158976), // V6_veqb_xor |
| 2056 | UINT64_C(528482308), // V6_veqh |
| 2057 | UINT64_C(478158852), // V6_veqh_and |
| 2058 | UINT64_C(478158916), // V6_veqh_or |
| 2059 | UINT64_C(478158980), // V6_veqh_xor |
| 2060 | UINT64_C(528482332), // V6_veqhf |
| 2061 | UINT64_C(478158876), // V6_veqhf_and |
| 2062 | UINT64_C(478158940), // V6_veqhf_or |
| 2063 | UINT64_C(478159004), // V6_veqhf_xor |
| 2064 | UINT64_C(528482316), // V6_veqsf |
| 2065 | UINT64_C(478158860), // V6_veqsf_and |
| 2066 | UINT64_C(478158924), // V6_veqsf_or |
| 2067 | UINT64_C(478158988), // V6_veqsf_xor |
| 2068 | UINT64_C(528482312), // V6_veqw |
| 2069 | UINT64_C(478158856), // V6_veqw_and |
| 2070 | UINT64_C(478158920), // V6_veqw_or |
| 2071 | UINT64_C(478158984), // V6_veqw_xor |
| 2072 | UINT64_C(476061856), // V6_vfmax_f8 |
| 2073 | UINT64_C(476061760), // V6_vfmax_hf |
| 2074 | UINT64_C(476061792), // V6_vfmax_sf |
| 2075 | UINT64_C(476061824), // V6_vfmin_f8 |
| 2076 | UINT64_C(476061696), // V6_vfmin_hf |
| 2077 | UINT64_C(476061728), // V6_vfmin_sf |
| 2078 | UINT64_C(476455136), // V6_vfneg_f8 |
| 2079 | UINT64_C(503717952), // V6_vfneg_hf |
| 2080 | UINT64_C(503717984), // V6_vfneg_sf |
| 2081 | UINT64_C(788529408), // V6_vgathermh |
| 2082 | UINT64_C(788530432), // V6_vgathermhq |
| 2083 | UINT64_C(788529664), // V6_vgathermhw |
| 2084 | UINT64_C(788530688), // V6_vgathermhwq |
| 2085 | UINT64_C(788529152), // V6_vgathermw |
| 2086 | UINT64_C(788530176), // V6_vgathermwq |
| 2087 | UINT64_C(528482320), // V6_vgtb |
| 2088 | UINT64_C(478158864), // V6_vgtb_and |
| 2089 | UINT64_C(478158928), // V6_vgtb_or |
| 2090 | UINT64_C(478158992), // V6_vgtb_xor |
| 2091 | UINT64_C(478158968), // V6_vgtbf |
| 2092 | UINT64_C(478159056), // V6_vgtbf_and |
| 2093 | UINT64_C(478158904), // V6_vgtbf_or |
| 2094 | UINT64_C(478159088), // V6_vgtbf_xor |
| 2095 | UINT64_C(528482324), // V6_vgth |
| 2096 | UINT64_C(478158868), // V6_vgth_and |
| 2097 | UINT64_C(478158932), // V6_vgth_or |
| 2098 | UINT64_C(478158996), // V6_vgth_xor |
| 2099 | UINT64_C(478158964), // V6_vgthf |
| 2100 | UINT64_C(478159052), // V6_vgthf_and |
| 2101 | UINT64_C(478158900), // V6_vgthf_or |
| 2102 | UINT64_C(478159084), // V6_vgthf_xor |
| 2103 | UINT64_C(478158960), // V6_vgtsf |
| 2104 | UINT64_C(478159048), // V6_vgtsf_and |
| 2105 | UINT64_C(478158896), // V6_vgtsf_or |
| 2106 | UINT64_C(478159080), // V6_vgtsf_xor |
| 2107 | UINT64_C(528482336), // V6_vgtub |
| 2108 | UINT64_C(478158880), // V6_vgtub_and |
| 2109 | UINT64_C(478158944), // V6_vgtub_or |
| 2110 | UINT64_C(478159008), // V6_vgtub_xor |
| 2111 | UINT64_C(528482340), // V6_vgtuh |
| 2112 | UINT64_C(478158884), // V6_vgtuh_and |
| 2113 | UINT64_C(478158948), // V6_vgtuh_or |
| 2114 | UINT64_C(478159012), // V6_vgtuh_xor |
| 2115 | UINT64_C(528482344), // V6_vgtuw |
| 2116 | UINT64_C(478158888), // V6_vgtuw_and |
| 2117 | UINT64_C(478158952), // V6_vgtuw_or |
| 2118 | UINT64_C(478159016), // V6_vgtuw_xor |
| 2119 | UINT64_C(528482328), // V6_vgtw |
| 2120 | UINT64_C(478158872), // V6_vgtw_and |
| 2121 | UINT64_C(478158936), // V6_vgtw_or |
| 2122 | UINT64_C(478159000), // V6_vgtw_xor |
| 2123 | UINT64_C(503324800), // V6_vhist |
| 2124 | UINT64_C(503455872), // V6_vhistq |
| 2125 | UINT64_C(504111200), // V6_vilog2_hf |
| 2126 | UINT64_C(504111136), // V6_vilog2_qf16 |
| 2127 | UINT64_C(504111104), // V6_vilog2_qf32 |
| 2128 | UINT64_C(504111168), // V6_vilog2_sf |
| 2129 | UINT64_C(429924384), // V6_vinsertwr |
| 2130 | UINT64_C(452984864), // V6_vlalignb |
| 2131 | UINT64_C(509616128), // V6_vlalignbi |
| 2132 | UINT64_C(427819104), // V6_vlsrb |
| 2133 | UINT64_C(427819072), // V6_vlsrh |
| 2134 | UINT64_C(530579520), // V6_vlsrhv |
| 2135 | UINT64_C(427819040), // V6_vlsrw |
| 2136 | UINT64_C(530579488), // V6_vlsrwv |
| 2137 | UINT64_C(425721984), // V6_vlut4 |
| 2138 | UINT64_C(452993056), // V6_vlutvvb |
| 2139 | UINT64_C(402653280), // V6_vlutvvb_nm |
| 2140 | UINT64_C(452993184), // V6_vlutvvb_oracc |
| 2141 | UINT64_C(482353152), // V6_vlutvvb_oracci |
| 2142 | UINT64_C(505413632), // V6_vlutvvbi |
| 2143 | UINT64_C(452993216), // V6_vlutvwh |
| 2144 | UINT64_C(402653312), // V6_vlutvwh_nm |
| 2145 | UINT64_C(452993248), // V6_vlutvwh_oracc |
| 2146 | UINT64_C(484450304), // V6_vlutvwh_oracci |
| 2147 | UINT64_C(509607936), // V6_vlutvwhi |
| 2148 | UINT64_C(490741984), // V6_vmax_bf |
| 2149 | UINT64_C(532684896), // V6_vmax_hf |
| 2150 | UINT64_C(532684832), // V6_vmax_sf |
| 2151 | UINT64_C(522191008), // V6_vmaxb |
| 2152 | UINT64_C(520093920), // V6_vmaxh |
| 2153 | UINT64_C(520093856), // V6_vmaxub |
| 2154 | UINT64_C(520093888), // V6_vmaxuh |
| 2155 | UINT64_C(522190848), // V6_vmaxw |
| 2156 | UINT64_C(520102112), // V6_vmerge_qf |
| 2157 | UINT64_C(490741760), // V6_vmin_bf |
| 2158 | UINT64_C(532684928), // V6_vmin_hf |
| 2159 | UINT64_C(532684864), // V6_vmin_sf |
| 2160 | UINT64_C(522190976), // V6_vminb |
| 2161 | UINT64_C(520093792), // V6_vminh |
| 2162 | UINT64_C(520093728), // V6_vminub |
| 2163 | UINT64_C(520093760), // V6_vminuh |
| 2164 | UINT64_C(520093824), // V6_vminw |
| 2165 | UINT64_C(421527744), // V6_vmpabus |
| 2166 | UINT64_C(421535936), // V6_vmpabus_acc |
| 2167 | UINT64_C(471859296), // V6_vmpabusv |
| 2168 | UINT64_C(425721952), // V6_vmpabuu |
| 2169 | UINT64_C(429924480), // V6_vmpabuu_acc |
| 2170 | UINT64_C(484442336), // V6_vmpabuuv |
| 2171 | UINT64_C(421527776), // V6_vmpahb |
| 2172 | UINT64_C(421535968), // V6_vmpahb_acc |
| 2173 | UINT64_C(427827328), // V6_vmpahhsat |
| 2174 | UINT64_C(427819168), // V6_vmpauhb |
| 2175 | UINT64_C(427827264), // V6_vmpauhb_acc |
| 2176 | UINT64_C(427827360), // V6_vmpauhuhsat |
| 2177 | UINT64_C(427827392), // V6_vmpsuhuhsat |
| 2178 | UINT64_C(528482496), // V6_vmpy_hf_f8 |
| 2179 | UINT64_C(528482528), // V6_vmpy_hf_f8_acc |
| 2180 | UINT64_C(528490592), // V6_vmpy_hf_hf |
| 2181 | UINT64_C(473964608), // V6_vmpy_hf_hf_acc |
| 2182 | UINT64_C(534782048), // V6_vmpy_qf16 |
| 2183 | UINT64_C(534782080), // V6_vmpy_qf16_hf |
| 2184 | UINT64_C(534782112), // V6_vmpy_qf16_mix_hf |
| 2185 | UINT64_C(534781952), // V6_vmpy_qf32 |
| 2186 | UINT64_C(534782176), // V6_vmpy_qf32_hf |
| 2187 | UINT64_C(528490496), // V6_vmpy_qf32_mix_hf |
| 2188 | UINT64_C(534782144), // V6_vmpy_qf32_qf16 |
| 2189 | UINT64_C(534781984), // V6_vmpy_qf32_sf |
| 2190 | UINT64_C(436215904), // V6_vmpy_rt_hf |
| 2191 | UINT64_C(436215872), // V6_vmpy_rt_qf16 |
| 2192 | UINT64_C(436215840), // V6_vmpy_rt_sf |
| 2193 | UINT64_C(490741888), // V6_vmpy_sf_bf |
| 2194 | UINT64_C(486547456), // V6_vmpy_sf_bf_acc |
| 2195 | UINT64_C(528490560), // V6_vmpy_sf_hf |
| 2196 | UINT64_C(473964576), // V6_vmpy_sf_hf_acc |
| 2197 | UINT64_C(528490528), // V6_vmpy_sf_sf |
| 2198 | UINT64_C(421527712), // V6_vmpybus |
| 2199 | UINT64_C(421535904), // V6_vmpybus_acc |
| 2200 | UINT64_C(469762240), // V6_vmpybusv |
| 2201 | UINT64_C(469770432), // V6_vmpybusv_acc |
| 2202 | UINT64_C(469762176), // V6_vmpybv |
| 2203 | UINT64_C(469770368), // V6_vmpybv_acc |
| 2204 | UINT64_C(534773920), // V6_vmpyewuh |
| 2205 | UINT64_C(513802432), // V6_vmpyewuh_64 |
| 2206 | UINT64_C(423624704), // V6_vmpyh |
| 2207 | UINT64_C(429924544), // V6_vmpyh_acc |
| 2208 | UINT64_C(423632896), // V6_vmpyhsat_acc |
| 2209 | UINT64_C(423624768), // V6_vmpyhsrs |
| 2210 | UINT64_C(423624736), // V6_vmpyhss |
| 2211 | UINT64_C(471859264), // V6_vmpyhus |
| 2212 | UINT64_C(471867424), // V6_vmpyhus_acc |
| 2213 | UINT64_C(469762272), // V6_vmpyhv |
| 2214 | UINT64_C(469770464), // V6_vmpyhv_acc |
| 2215 | UINT64_C(471859232), // V6_vmpyhvsrs |
| 2216 | UINT64_C(526385152), // V6_vmpyieoh |
| 2217 | UINT64_C(473964544), // V6_vmpyiewh_acc |
| 2218 | UINT64_C(532676608), // V6_vmpyiewuh |
| 2219 | UINT64_C(471867552), // V6_vmpyiewuh_acc |
| 2220 | UINT64_C(471859328), // V6_vmpyih |
| 2221 | UINT64_C(471867520), // V6_vmpyih_acc |
| 2222 | UINT64_C(425721856), // V6_vmpyihb |
| 2223 | UINT64_C(425730080), // V6_vmpyihb_acc |
| 2224 | UINT64_C(532676640), // V6_vmpyiowh |
| 2225 | UINT64_C(429916160), // V6_vmpyiwb |
| 2226 | UINT64_C(423632960), // V6_vmpyiwb_acc |
| 2227 | UINT64_C(427819232), // V6_vmpyiwh |
| 2228 | UINT64_C(423632992), // V6_vmpyiwh_acc |
| 2229 | UINT64_C(427819200), // V6_vmpyiwub |
| 2230 | UINT64_C(427827232), // V6_vmpyiwub_acc |
| 2231 | UINT64_C(534773984), // V6_vmpyowh |
| 2232 | UINT64_C(471867488), // V6_vmpyowh_64_acc |
| 2233 | UINT64_C(524288000), // V6_vmpyowh_rnd |
| 2234 | UINT64_C(471867616), // V6_vmpyowh_rnd_sacc |
| 2235 | UINT64_C(471867584), // V6_vmpyowh_sacc |
| 2236 | UINT64_C(432013312), // V6_vmpyub |
| 2237 | UINT64_C(427827200), // V6_vmpyub_acc |
| 2238 | UINT64_C(469762208), // V6_vmpyubv |
| 2239 | UINT64_C(469770400), // V6_vmpyubv_acc |
| 2240 | UINT64_C(423624800), // V6_vmpyuh |
| 2241 | UINT64_C(423632928), // V6_vmpyuh_acc |
| 2242 | UINT64_C(425721920), // V6_vmpyuhe |
| 2243 | UINT64_C(427827296), // V6_vmpyuhe_acc |
| 2244 | UINT64_C(471859200), // V6_vmpyuhv |
| 2245 | UINT64_C(471867392), // V6_vmpyuhv_acc |
| 2246 | UINT64_C(532685024), // V6_vmpyuhvs |
| 2247 | UINT64_C(518004736), // V6_vmux |
| 2248 | UINT64_C(520102080), // V6_vnavgb |
| 2249 | UINT64_C(484442144), // V6_vnavgh |
| 2250 | UINT64_C(484442112), // V6_vnavgub |
| 2251 | UINT64_C(484442176), // V6_vnavgw |
| 2252 | UINT64_C(440401920), // V6_vnccombine |
| 2253 | UINT64_C(438304768), // V6_vncmov |
| 2254 | UINT64_C(504242240), // V6_vneg_qf16_hf |
| 2255 | UINT64_C(504242272), // V6_vneg_qf16_qf16 |
| 2256 | UINT64_C(504242208), // V6_vneg_qf32_qf32 |
| 2257 | UINT64_C(504242176), // V6_vneg_qf32_sf |
| 2258 | UINT64_C(503513248), // V6_vnormamth |
| 2259 | UINT64_C(503513216), // V6_vnormamtw |
| 2260 | UINT64_C(503316608), // V6_vnot |
| 2261 | UINT64_C(471859392), // V6_vor |
| 2262 | UINT64_C(532676672), // V6_vpackeb |
| 2263 | UINT64_C(532676704), // V6_vpackeh |
| 2264 | UINT64_C(532676800), // V6_vpackhb_sat |
| 2265 | UINT64_C(532676768), // V6_vpackhub_sat |
| 2266 | UINT64_C(534773792), // V6_vpackob |
| 2267 | UINT64_C(534773824), // V6_vpackoh |
| 2268 | UINT64_C(534773760), // V6_vpackwh_sat |
| 2269 | UINT64_C(532676832), // V6_vpackwuh_sat |
| 2270 | UINT64_C(503447744), // V6_vpopcounth |
| 2271 | UINT64_C(503521344), // V6_vprefixqb |
| 2272 | UINT64_C(503521600), // V6_vprefixqh |
| 2273 | UINT64_C(503521856), // V6_vprefixqw |
| 2274 | UINT64_C(522190944), // V6_vrdelta |
| 2275 | UINT64_C(432013472), // V6_vrmpybub_rtt |
| 2276 | UINT64_C(429924352), // V6_vrmpybub_rtt_acc |
| 2277 | UINT64_C(419430528), // V6_vrmpybus |
| 2278 | UINT64_C(419438752), // V6_vrmpybus_acc |
| 2279 | UINT64_C(423624832), // V6_vrmpybusi |
| 2280 | UINT64_C(423633024), // V6_vrmpybusi_acc |
| 2281 | UINT64_C(469762112), // V6_vrmpybusv |
| 2282 | UINT64_C(469770304), // V6_vrmpybusv_acc |
| 2283 | UINT64_C(469762080), // V6_vrmpybv |
| 2284 | UINT64_C(469770272), // V6_vrmpybv_acc |
| 2285 | UINT64_C(419430496), // V6_vrmpyub |
| 2286 | UINT64_C(419438720), // V6_vrmpyub_acc |
| 2287 | UINT64_C(432013440), // V6_vrmpyub_rtt |
| 2288 | UINT64_C(429924576), // V6_vrmpyub_rtt_acc |
| 2289 | UINT64_C(429916352), // V6_vrmpyubi |
| 2290 | UINT64_C(425730240), // V6_vrmpyubi_acc |
| 2291 | UINT64_C(469762048), // V6_vrmpyubv |
| 2292 | UINT64_C(469770240), // V6_vrmpyubv_acc |
| 2293 | UINT64_C(434634752), // V6_vrmpyzbb_rt |
| 2294 | UINT64_C(432021568), // V6_vrmpyzbb_rt_acc |
| 2295 | UINT64_C(434110464), // V6_vrmpyzbb_rx |
| 2296 | UINT64_C(432545856), // V6_vrmpyzbb_rx_acc |
| 2297 | UINT64_C(435683392), // V6_vrmpyzbub_rt |
| 2298 | UINT64_C(433070112), // V6_vrmpyzbub_rt_acc |
| 2299 | UINT64_C(435159104), // V6_vrmpyzbub_rx |
| 2300 | UINT64_C(433594400), // V6_vrmpyzbub_rx_acc |
| 2301 | UINT64_C(434634784), // V6_vrmpyzcb_rt |
| 2302 | UINT64_C(432021600), // V6_vrmpyzcb_rt_acc |
| 2303 | UINT64_C(434110496), // V6_vrmpyzcb_rx |
| 2304 | UINT64_C(432545888), // V6_vrmpyzcb_rx_acc |
| 2305 | UINT64_C(434634816), // V6_vrmpyzcbs_rt |
| 2306 | UINT64_C(432021536), // V6_vrmpyzcbs_rt_acc |
| 2307 | UINT64_C(434110528), // V6_vrmpyzcbs_rx |
| 2308 | UINT64_C(432545824), // V6_vrmpyzcbs_rx_acc |
| 2309 | UINT64_C(435683328), // V6_vrmpyznb_rt |
| 2310 | UINT64_C(433070144), // V6_vrmpyznb_rt_acc |
| 2311 | UINT64_C(435159040), // V6_vrmpyznb_rx |
| 2312 | UINT64_C(433594432), // V6_vrmpyznb_rx_acc |
| 2313 | UINT64_C(425721888), // V6_vror |
| 2314 | UINT64_C(444604640), // V6_vrotr |
| 2315 | UINT64_C(526385344), // V6_vroundhb |
| 2316 | UINT64_C(526385376), // V6_vroundhub |
| 2317 | UINT64_C(534773856), // V6_vrounduhub |
| 2318 | UINT64_C(534773888), // V6_vrounduwuh |
| 2319 | UINT64_C(526385280), // V6_vroundwh |
| 2320 | UINT64_C(526385312), // V6_vroundwuh |
| 2321 | UINT64_C(423624896), // V6_vrsadubi |
| 2322 | UINT64_C(423633088), // V6_vrsadubi_acc |
| 2323 | UINT64_C(494936288), // V6_vsatdw |
| 2324 | UINT64_C(526385216), // V6_vsathub |
| 2325 | UINT64_C(522191040), // V6_vsatuwuh |
| 2326 | UINT64_C(526385248), // V6_vsatwh |
| 2327 | UINT64_C(503447648), // V6_vsb |
| 2328 | UINT64_C(790626336), // V6_vscattermh |
| 2329 | UINT64_C(790626464), // V6_vscattermh_add |
| 2330 | UINT64_C(796917888), // V6_vscattermhq |
| 2331 | UINT64_C(790626368), // V6_vscattermhw |
| 2332 | UINT64_C(790626496), // V6_vscattermhw_add |
| 2333 | UINT64_C(799014912), // V6_vscattermhwq |
| 2334 | UINT64_C(790626304), // V6_vscattermw |
| 2335 | UINT64_C(790626432), // V6_vscattermw_add |
| 2336 | UINT64_C(796917760), // V6_vscattermwq |
| 2337 | UINT64_C(503447680), // V6_vsh |
| 2338 | UINT64_C(524288096), // V6_vshufeh |
| 2339 | UINT64_C(434118688), // V6_vshuff |
| 2340 | UINT64_C(503447552), // V6_vshuffb |
| 2341 | UINT64_C(524288032), // V6_vshuffeb |
| 2342 | UINT64_C(503382240), // V6_vshuffh |
| 2343 | UINT64_C(524288064), // V6_vshuffob |
| 2344 | UINT64_C(452993120), // V6_vshuffvdd |
| 2345 | UINT64_C(524288192), // V6_vshufoeb |
| 2346 | UINT64_C(524288160), // V6_vshufoeh |
| 2347 | UINT64_C(524288128), // V6_vshufoh |
| 2348 | UINT64_C(526393536), // V6_vsub_hf |
| 2349 | UINT64_C(528482464), // V6_vsub_hf_f8 |
| 2350 | UINT64_C(526393344), // V6_vsub_hf_hf |
| 2351 | UINT64_C(436215936), // V6_vsub_hf_mix |
| 2352 | UINT64_C(526393504), // V6_vsub_qf16 |
| 2353 | UINT64_C(526393568), // V6_vsub_qf16_mix |
| 2354 | UINT64_C(530587744), // V6_vsub_qf32 |
| 2355 | UINT64_C(530587808), // V6_vsub_qf32_mix |
| 2356 | UINT64_C(530587776), // V6_vsub_sf |
| 2357 | UINT64_C(490741920), // V6_vsub_sf_bf |
| 2358 | UINT64_C(528490656), // V6_vsub_sf_hf |
| 2359 | UINT64_C(436215808), // V6_vsub_sf_mix |
| 2360 | UINT64_C(528490720), // V6_vsub_sf_sf |
| 2361 | UINT64_C(473956512), // V6_vsubb |
| 2362 | UINT64_C(478150752), // V6_vsubb_dv |
| 2363 | UINT64_C(503455776), // V6_vsubbnq |
| 2364 | UINT64_C(503390400), // V6_vsubbq |
| 2365 | UINT64_C(522190912), // V6_vsubbsat |
| 2366 | UINT64_C(513802272), // V6_vsubbsat_dv |
| 2367 | UINT64_C(480256128), // V6_vsubcarry |
| 2368 | UINT64_C(497033344), // V6_vsubcarryo |
| 2369 | UINT64_C(473956544), // V6_vsubh |
| 2370 | UINT64_C(478150784), // V6_vsubh_dv |
| 2371 | UINT64_C(503455808), // V6_vsubhnq |
| 2372 | UINT64_C(503390432), // V6_vsubhq |
| 2373 | UINT64_C(476053568), // V6_vsubhsat |
| 2374 | UINT64_C(480247808), // V6_vsubhsat_dv |
| 2375 | UINT64_C(480248032), // V6_vsubhw |
| 2376 | UINT64_C(480247968), // V6_vsububh |
| 2377 | UINT64_C(476053504), // V6_vsububsat |
| 2378 | UINT64_C(478150848), // V6_vsububsat_dv |
| 2379 | UINT64_C(513802400), // V6_vsubububb_sat |
| 2380 | UINT64_C(476053536), // V6_vsubuhsat |
| 2381 | UINT64_C(478150880), // V6_vsubuhsat_dv |
| 2382 | UINT64_C(480248000), // V6_vsubuhw |
| 2383 | UINT64_C(532676736), // V6_vsubuwsat |
| 2384 | UINT64_C(513802336), // V6_vsubuwsat_dv |
| 2385 | UINT64_C(473956576), // V6_vsubw |
| 2386 | UINT64_C(478150816), // V6_vsubw_dv |
| 2387 | UINT64_C(503455840), // V6_vsubwnq |
| 2388 | UINT64_C(503455744), // V6_vsubwq |
| 2389 | UINT64_C(476053600), // V6_vsubwsat |
| 2390 | UINT64_C(480247840), // V6_vsubwsat_dv |
| 2391 | UINT64_C(513810432), // V6_vswap |
| 2392 | UINT64_C(419430400), // V6_vtmpyb |
| 2393 | UINT64_C(419438592), // V6_vtmpyb_acc |
| 2394 | UINT64_C(419430432), // V6_vtmpybus |
| 2395 | UINT64_C(419438624), // V6_vtmpybus_acc |
| 2396 | UINT64_C(429916288), // V6_vtmpyhb |
| 2397 | UINT64_C(419438656), // V6_vtmpyhb_acc |
| 2398 | UINT64_C(503382080), // V6_vunpackb |
| 2399 | UINT64_C(503382112), // V6_vunpackh |
| 2400 | UINT64_C(503324672), // V6_vunpackob |
| 2401 | UINT64_C(503324704), // V6_vunpackoh |
| 2402 | UINT64_C(503382016), // V6_vunpackub |
| 2403 | UINT64_C(503382048), // V6_vunpackuh |
| 2404 | UINT64_C(503325824), // V6_vwhist128 |
| 2405 | UINT64_C(503326336), // V6_vwhist128m |
| 2406 | UINT64_C(503456896), // V6_vwhist128q |
| 2407 | UINT64_C(503457408), // V6_vwhist128qm |
| 2408 | UINT64_C(503325312), // V6_vwhist256 |
| 2409 | UINT64_C(503325568), // V6_vwhist256_sat |
| 2410 | UINT64_C(503456384), // V6_vwhist256q |
| 2411 | UINT64_C(503456640), // V6_vwhist256q_sat |
| 2412 | UINT64_C(471859424), // V6_vxor |
| 2413 | UINT64_C(503447584), // V6_vzb |
| 2414 | UINT64_C(503447616), // V6_vzh |
| 2415 | UINT64_C(738197504), // V6_zLd_ai |
| 2416 | UINT64_C(754974720), // V6_zLd_pi |
| 2417 | UINT64_C(754974721), // V6_zLd_ppu |
| 2418 | UINT64_C(746586112), // V6_zLd_pred_ai |
| 2419 | UINT64_C(763363328), // V6_zLd_pred_pi |
| 2420 | UINT64_C(763363329), // V6_zLd_pred_ppu |
| 2421 | UINT64_C(429916448), // V6_zextract |
| 2422 | UINT64_C(2818572288), // Y2_barrier |
| 2423 | UINT64_C(1814036480), // Y2_break |
| 2424 | UINT64_C(1677721696), // Y2_ciad |
| 2425 | UINT64_C(1694498816), // Y2_crswap0 |
| 2426 | UINT64_C(1677721632), // Y2_cswi |
| 2427 | UINT64_C(2684354560), // Y2_dccleana |
| 2428 | UINT64_C(2720006144), // Y2_dccleanidx |
| 2429 | UINT64_C(2688548864), // Y2_dccleaninva |
| 2430 | UINT64_C(2724200448), // Y2_dccleaninvidx |
| 2431 | UINT64_C(2483027968), // Y2_dcfetchbo |
| 2432 | UINT64_C(2686451712), // Y2_dcinva |
| 2433 | UINT64_C(2722103296), // Y2_dcinvidx |
| 2434 | UINT64_C(2717908992), // Y2_dckill |
| 2435 | UINT64_C(2753560576), // Y2_dctagr |
| 2436 | UINT64_C(2751463424), // Y2_dctagw |
| 2437 | UINT64_C(2696937472), // Y2_dczeroa |
| 2438 | UINT64_C(1711276032), // Y2_getimask |
| 2439 | UINT64_C(1717567488), // Y2_iassignr |
| 2440 | UINT64_C(1677721664), // Y2_iassignw |
| 2441 | UINT64_C(1436549120), // Y2_icdatar |
| 2442 | UINT64_C(1438654464), // Y2_icdataw |
| 2443 | UINT64_C(1455423488), // Y2_icinva |
| 2444 | UINT64_C(1455425536), // Y2_icinvidx |
| 2445 | UINT64_C(1455427584), // Y2_ickill |
| 2446 | UINT64_C(1440743424), // Y2_ictagr |
| 2447 | UINT64_C(1438646272), // Y2_ictagw |
| 2448 | UINT64_C(1472200706), // Y2_isync |
| 2449 | UINT64_C(1814036576), // Y2_k0lock |
| 2450 | UINT64_C(1814036608), // Y2_k0unlock |
| 2451 | UINT64_C(2824863744), // Y2_l2cleaninvidx |
| 2452 | UINT64_C(2820669440), // Y2_l2kill |
| 2453 | UINT64_C(1681915936), // Y2_resume |
| 2454 | UINT64_C(1686110208), // Y2_setimask |
| 2455 | UINT64_C(1686110240), // Y2_setprio |
| 2456 | UINT64_C(1684013088), // Y2_start |
| 2457 | UINT64_C(1684013056), // Y2_stop |
| 2458 | UINT64_C(1677721600), // Y2_swi |
| 2459 | UINT64_C(2822766592), // Y2_syncht |
| 2460 | UINT64_C(1853882368), // Y2_tfrscrr |
| 2461 | UINT64_C(1728053248), // Y2_tfrsrcr |
| 2462 | UINT64_C(1814036512), // Y2_tlblock |
| 2463 | UINT64_C(1820327936), // Y2_tlbp |
| 2464 | UINT64_C(1818230784), // Y2_tlbpp |
| 2465 | UINT64_C(1816133632), // Y2_tlbr |
| 2466 | UINT64_C(1814036544), // Y2_tlbunlock |
| 2467 | UINT64_C(1811939328), // Y2_tlbw |
| 2468 | UINT64_C(1681915904), // Y2_wait |
| 2469 | UINT64_C(1696595968), // Y4_crswap1 |
| 2470 | UINT64_C(1837105152), // Y4_crswap10 |
| 2471 | UINT64_C(2785017856), // Y4_l2fetch |
| 2472 | UINT64_C(2757754880), // Y4_l2tagr |
| 2473 | UINT64_C(2755657728), // Y4_l2tagw |
| 2474 | UINT64_C(1684013120), // Y4_nmi |
| 2475 | UINT64_C(1686110304), // Y4_siad |
| 2476 | UINT64_C(1862270976), // Y4_tfrscpp |
| 2477 | UINT64_C(1828716544), // Y4_tfrspcp |
| 2478 | UINT64_C(1648361472), // Y4_trace |
| 2479 | UINT64_C(1824522240), // Y5_ctlbw |
| 2480 | UINT64_C(2787115008), // Y5_l2cleanidx |
| 2481 | UINT64_C(2793406464), // Y5_l2fetch |
| 2482 | UINT64_C(2820673536), // Y5_l2gclean |
| 2483 | UINT64_C(2820675584), // Y5_l2gcleaninv |
| 2484 | UINT64_C(2820671488), // Y5_l2gunlock |
| 2485 | UINT64_C(2789212160), // Y5_l2invidx |
| 2486 | UINT64_C(2699042816), // Y5_l2locka |
| 2487 | UINT64_C(2791309312), // Y5_l2unlocka |
| 2488 | UINT64_C(1822425088), // Y5_tlbasidi |
| 2489 | UINT64_C(1826619392), // Y5_tlboc |
| 2490 | UINT64_C(1648361504), // Y6_diag |
| 2491 | UINT64_C(1648361536), // Y6_diag0 |
| 2492 | UINT64_C(1648361568), // Y6_diag1 |
| 2493 | UINT64_C(2785017920), // Y6_dmlink |
| 2494 | UINT64_C(2818572384), // Y6_dmpause |
| 2495 | UINT64_C(2818572352), // Y6_dmpoll |
| 2496 | UINT64_C(2785017984), // Y6_dmresume |
| 2497 | UINT64_C(2785017888), // Y6_dmstart |
| 2498 | UINT64_C(2818572320), // Y6_dmwait |
| 2499 | UINT64_C(2797600768), // Y6_l2gcleaninvpa |
| 2500 | UINT64_C(2795503616), // Y6_l2gcleanpa |
| 2501 | UINT64_C(3581935616), // dep_A2_addsat |
| 2502 | UINT64_C(3581935744), // dep_A2_subsat |
| 2503 | UINT64_C(3556769792), // dep_S2_packhl |
| 2504 | UINT64_C(0), // invalid_decode |
| 2505 | }; |
| 2506 | constexpr unsigned FirstSupportedOpcode = 931; |
| 2507 | |
| 2508 | const unsigned opcode = MI.getOpcode(); |
| 2509 | if (opcode < FirstSupportedOpcode) |
| 2510 | reportUnsupportedInst(Inst: MI); |
| 2511 | unsigned TableIndex = opcode - FirstSupportedOpcode; |
| 2512 | uint64_t Value = InstBits[TableIndex]; |
| 2513 | uint64_t op = 0; |
| 2514 | (void)op; // suppress warning |
| 2515 | switch (opcode) { |
| 2516 | case Hexagon::A2_nop: |
| 2517 | case Hexagon::CONST32: |
| 2518 | case Hexagon::CONST64: |
| 2519 | case Hexagon::DuplexIClass0: |
| 2520 | case Hexagon::DuplexIClass1: |
| 2521 | case Hexagon::DuplexIClass2: |
| 2522 | case Hexagon::DuplexIClass3: |
| 2523 | case Hexagon::DuplexIClass4: |
| 2524 | case Hexagon::DuplexIClass5: |
| 2525 | case Hexagon::DuplexIClass6: |
| 2526 | case Hexagon::DuplexIClass7: |
| 2527 | case Hexagon::DuplexIClass8: |
| 2528 | case Hexagon::DuplexIClass9: |
| 2529 | case Hexagon::DuplexIClassA: |
| 2530 | case Hexagon::DuplexIClassB: |
| 2531 | case Hexagon::DuplexIClassC: |
| 2532 | case Hexagon::DuplexIClassD: |
| 2533 | case Hexagon::DuplexIClassE: |
| 2534 | case Hexagon::DuplexIClassF: |
| 2535 | case Hexagon::J2_rte: |
| 2536 | case Hexagon::J2_unpause: |
| 2537 | case Hexagon::SL2_deallocframe: |
| 2538 | case Hexagon::SL2_jumpr31: |
| 2539 | case Hexagon::SL2_jumpr31_f: |
| 2540 | case Hexagon::SL2_jumpr31_fnew: |
| 2541 | case Hexagon::SL2_jumpr31_t: |
| 2542 | case Hexagon::SL2_jumpr31_tnew: |
| 2543 | case Hexagon::SL2_return: |
| 2544 | case Hexagon::SL2_return_f: |
| 2545 | case Hexagon::SL2_return_fnew: |
| 2546 | case Hexagon::SL2_return_t: |
| 2547 | case Hexagon::SL2_return_tnew: |
| 2548 | case Hexagon::TFRI64_V2_ext: |
| 2549 | case Hexagon::TFRI64_V4: |
| 2550 | case Hexagon::V6_vhist: |
| 2551 | case Hexagon::V6_vwhist128: |
| 2552 | case Hexagon::V6_vwhist256: |
| 2553 | case Hexagon::V6_vwhist256_sat: |
| 2554 | case Hexagon::Y2_barrier: |
| 2555 | case Hexagon::Y2_break: |
| 2556 | case Hexagon::Y2_dckill: |
| 2557 | case Hexagon::Y2_ickill: |
| 2558 | case Hexagon::Y2_isync: |
| 2559 | case Hexagon::Y2_k0lock: |
| 2560 | case Hexagon::Y2_k0unlock: |
| 2561 | case Hexagon::Y2_l2kill: |
| 2562 | case Hexagon::Y2_syncht: |
| 2563 | case Hexagon::Y2_tlblock: |
| 2564 | case Hexagon::Y2_tlbunlock: |
| 2565 | case Hexagon::Y5_l2gclean: |
| 2566 | case Hexagon::Y5_l2gcleaninv: |
| 2567 | case Hexagon::Y5_l2gunlock: |
| 2568 | case Hexagon::invalid_decode: { |
| 2569 | break; |
| 2570 | } |
| 2571 | case Hexagon::A2_tfrcrr: { |
| 2572 | // op: Cs32 |
| 2573 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 2574 | Value |= (op & 0x1f) << 16; |
| 2575 | // op: Rd32 |
| 2576 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 2577 | Value |= (op & 0x1f); |
| 2578 | break; |
| 2579 | } |
| 2580 | case Hexagon::A4_tfrcpp: { |
| 2581 | // op: Css32 |
| 2582 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 2583 | Value |= (op & 0x1f) << 16; |
| 2584 | // op: Rdd32 |
| 2585 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 2586 | Value |= (op & 0x1f); |
| 2587 | break; |
| 2588 | } |
| 2589 | case Hexagon::G4_tfrgcrr: { |
| 2590 | // op: Gs32 |
| 2591 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 2592 | Value |= (op & 0x1f) << 16; |
| 2593 | // op: Rd32 |
| 2594 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 2595 | Value |= (op & 0x1f); |
| 2596 | break; |
| 2597 | } |
| 2598 | case Hexagon::G4_tfrgcpp: { |
| 2599 | // op: Gss32 |
| 2600 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 2601 | Value |= (op & 0x1f) << 16; |
| 2602 | // op: Rdd32 |
| 2603 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 2604 | Value |= (op & 0x1f); |
| 2605 | break; |
| 2606 | } |
| 2607 | case Hexagon::J4_cmpeqi_f_jumpnv_nt: |
| 2608 | case Hexagon::J4_cmpeqi_f_jumpnv_t: |
| 2609 | case Hexagon::J4_cmpeqi_t_jumpnv_nt: |
| 2610 | case Hexagon::J4_cmpeqi_t_jumpnv_t: |
| 2611 | case Hexagon::J4_cmpgti_f_jumpnv_nt: |
| 2612 | case Hexagon::J4_cmpgti_f_jumpnv_t: |
| 2613 | case Hexagon::J4_cmpgti_t_jumpnv_nt: |
| 2614 | case Hexagon::J4_cmpgti_t_jumpnv_t: |
| 2615 | case Hexagon::J4_cmpgtui_f_jumpnv_nt: |
| 2616 | case Hexagon::J4_cmpgtui_f_jumpnv_t: |
| 2617 | case Hexagon::J4_cmpgtui_t_jumpnv_nt: |
| 2618 | case Hexagon::J4_cmpgtui_t_jumpnv_t: { |
| 2619 | // op: II |
| 2620 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 2621 | Value |= (op & 0x1f) << 8; |
| 2622 | // op: Ii |
| 2623 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 2624 | Value |= (op & 0x600) << 11; |
| 2625 | Value |= (op & 0x1fc) >> 1; |
| 2626 | // op: Ns8 |
| 2627 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 2628 | Value |= (op & 0x7) << 16; |
| 2629 | break; |
| 2630 | } |
| 2631 | case Hexagon::J4_cmpeqi_fp0_jump_nt: |
| 2632 | case Hexagon::J4_cmpeqi_fp0_jump_t: |
| 2633 | case Hexagon::J4_cmpeqi_fp1_jump_nt: |
| 2634 | case Hexagon::J4_cmpeqi_fp1_jump_t: |
| 2635 | case Hexagon::J4_cmpeqi_tp0_jump_nt: |
| 2636 | case Hexagon::J4_cmpeqi_tp0_jump_t: |
| 2637 | case Hexagon::J4_cmpeqi_tp1_jump_nt: |
| 2638 | case Hexagon::J4_cmpeqi_tp1_jump_t: |
| 2639 | case Hexagon::J4_cmpgti_fp0_jump_nt: |
| 2640 | case Hexagon::J4_cmpgti_fp0_jump_t: |
| 2641 | case Hexagon::J4_cmpgti_fp1_jump_nt: |
| 2642 | case Hexagon::J4_cmpgti_fp1_jump_t: |
| 2643 | case Hexagon::J4_cmpgti_tp0_jump_nt: |
| 2644 | case Hexagon::J4_cmpgti_tp0_jump_t: |
| 2645 | case Hexagon::J4_cmpgti_tp1_jump_nt: |
| 2646 | case Hexagon::J4_cmpgti_tp1_jump_t: |
| 2647 | case Hexagon::J4_cmpgtui_fp0_jump_nt: |
| 2648 | case Hexagon::J4_cmpgtui_fp0_jump_t: |
| 2649 | case Hexagon::J4_cmpgtui_fp1_jump_nt: |
| 2650 | case Hexagon::J4_cmpgtui_fp1_jump_t: |
| 2651 | case Hexagon::J4_cmpgtui_tp0_jump_nt: |
| 2652 | case Hexagon::J4_cmpgtui_tp0_jump_t: |
| 2653 | case Hexagon::J4_cmpgtui_tp1_jump_nt: |
| 2654 | case Hexagon::J4_cmpgtui_tp1_jump_t: { |
| 2655 | // op: II |
| 2656 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 2657 | Value |= (op & 0x1f) << 8; |
| 2658 | // op: Ii |
| 2659 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 2660 | Value |= (op & 0x600) << 11; |
| 2661 | Value |= (op & 0x1fc) >> 1; |
| 2662 | // op: Rs16 |
| 2663 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 2664 | Value |= (op & 0xf) << 16; |
| 2665 | break; |
| 2666 | } |
| 2667 | case Hexagon::J4_jumpseti: { |
| 2668 | // op: II |
| 2669 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 2670 | Value |= (op & 0x3f) << 8; |
| 2671 | // op: Ii |
| 2672 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 2673 | Value |= (op & 0x600) << 11; |
| 2674 | Value |= (op & 0x1fc) >> 1; |
| 2675 | // op: Rd16 |
| 2676 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 2677 | Value |= (op & 0xf) << 16; |
| 2678 | break; |
| 2679 | } |
| 2680 | case Hexagon::S4_storerbnew_ap: |
| 2681 | case Hexagon::S4_storerhnew_ap: |
| 2682 | case Hexagon::S4_storerinew_ap: { |
| 2683 | // op: II |
| 2684 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 2685 | Value |= (op & 0x3f); |
| 2686 | // op: Nt8 |
| 2687 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 2688 | Value |= (op & 0x7) << 8; |
| 2689 | // op: Re32 |
| 2690 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 2691 | Value |= (op & 0x1f) << 16; |
| 2692 | break; |
| 2693 | } |
| 2694 | case Hexagon::S4_storerb_ap: |
| 2695 | case Hexagon::S4_storerf_ap: |
| 2696 | case Hexagon::S4_storerh_ap: |
| 2697 | case Hexagon::S4_storeri_ap: { |
| 2698 | // op: II |
| 2699 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 2700 | Value |= (op & 0x3f); |
| 2701 | // op: Rt32 |
| 2702 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 2703 | Value |= (op & 0x1f) << 8; |
| 2704 | // op: Re32 |
| 2705 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 2706 | Value |= (op & 0x1f) << 16; |
| 2707 | break; |
| 2708 | } |
| 2709 | case Hexagon::S4_storerd_ap: { |
| 2710 | // op: II |
| 2711 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 2712 | Value |= (op & 0x3f); |
| 2713 | // op: Rtt32 |
| 2714 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 2715 | Value |= (op & 0x1f) << 8; |
| 2716 | // op: Re32 |
| 2717 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 2718 | Value |= (op & 0x1f) << 16; |
| 2719 | break; |
| 2720 | } |
| 2721 | case Hexagon::L4_loadbsw2_ap: |
| 2722 | case Hexagon::L4_loadbzw2_ap: |
| 2723 | case Hexagon::L4_loadrb_ap: |
| 2724 | case Hexagon::L4_loadrh_ap: |
| 2725 | case Hexagon::L4_loadri_ap: |
| 2726 | case Hexagon::L4_loadrub_ap: |
| 2727 | case Hexagon::L4_loadruh_ap: { |
| 2728 | // op: II |
| 2729 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 2730 | Value |= (op & 0x3c) << 6; |
| 2731 | Value |= (op & 0x3) << 5; |
| 2732 | // op: Rd32 |
| 2733 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 2734 | Value |= (op & 0x1f); |
| 2735 | // op: Re32 |
| 2736 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 2737 | Value |= (op & 0x1f) << 16; |
| 2738 | break; |
| 2739 | } |
| 2740 | case Hexagon::L4_loadbsw4_ap: |
| 2741 | case Hexagon::L4_loadbzw4_ap: |
| 2742 | case Hexagon::L4_loadrd_ap: { |
| 2743 | // op: II |
| 2744 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 2745 | Value |= (op & 0x3c) << 6; |
| 2746 | Value |= (op & 0x3) << 5; |
| 2747 | // op: Rdd32 |
| 2748 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 2749 | Value |= (op & 0x1f); |
| 2750 | // op: Re32 |
| 2751 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 2752 | Value |= (op & 0x1f) << 16; |
| 2753 | break; |
| 2754 | } |
| 2755 | case Hexagon::L4_loadalignb_ap: |
| 2756 | case Hexagon::L4_loadalignh_ap: { |
| 2757 | // op: II |
| 2758 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 2759 | Value |= (op & 0x3c) << 6; |
| 2760 | Value |= (op & 0x3) << 5; |
| 2761 | // op: Ryy32 |
| 2762 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 2763 | Value |= (op & 0x1f); |
| 2764 | // op: Re32 |
| 2765 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 2766 | Value |= (op & 0x1f) << 16; |
| 2767 | break; |
| 2768 | } |
| 2769 | case Hexagon::V6_vwhist128m: { |
| 2770 | // op: Ii |
| 2771 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 2772 | Value |= (op & 0x1) << 8; |
| 2773 | break; |
| 2774 | } |
| 2775 | case Hexagon::PS_storerhnewabs: |
| 2776 | case Hexagon::S2_storerhnewgp: { |
| 2777 | // op: Ii |
| 2778 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 2779 | Value |= (op & 0x18000) << 10; |
| 2780 | Value |= (op & 0x7c00) << 6; |
| 2781 | Value |= (op & 0x200) << 4; |
| 2782 | Value |= (op & 0x1fe) >> 1; |
| 2783 | // op: Nt8 |
| 2784 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 2785 | Value |= (op & 0x7) << 8; |
| 2786 | break; |
| 2787 | } |
| 2788 | case Hexagon::PS_storerfabs: |
| 2789 | case Hexagon::PS_storerhabs: |
| 2790 | case Hexagon::S2_storerfgp: |
| 2791 | case Hexagon::S2_storerhgp: { |
| 2792 | // op: Ii |
| 2793 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 2794 | Value |= (op & 0x18000) << 10; |
| 2795 | Value |= (op & 0x7c00) << 6; |
| 2796 | Value |= (op & 0x200) << 4; |
| 2797 | Value |= (op & 0x1fe) >> 1; |
| 2798 | // op: Rt32 |
| 2799 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 2800 | Value |= (op & 0x1f) << 8; |
| 2801 | break; |
| 2802 | } |
| 2803 | case Hexagon::J2_loop0i: |
| 2804 | case Hexagon::J2_loop1i: |
| 2805 | case Hexagon::J2_ploop1si: |
| 2806 | case Hexagon::J2_ploop2si: |
| 2807 | case Hexagon::J2_ploop3si: { |
| 2808 | // op: Ii |
| 2809 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 2810 | Value |= (op & 0x1f0) << 4; |
| 2811 | Value |= (op & 0xc) << 1; |
| 2812 | // op: II |
| 2813 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 2814 | Value |= (op & 0x3e0) << 11; |
| 2815 | Value |= (op & 0x1c) << 3; |
| 2816 | Value |= (op & 0x3); |
| 2817 | break; |
| 2818 | } |
| 2819 | case Hexagon::J2_loop0r: |
| 2820 | case Hexagon::J2_loop1r: |
| 2821 | case Hexagon::J2_ploop1sr: |
| 2822 | case Hexagon::J2_ploop2sr: |
| 2823 | case Hexagon::J2_ploop3sr: { |
| 2824 | // op: Ii |
| 2825 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 2826 | Value |= (op & 0x1f0) << 4; |
| 2827 | Value |= (op & 0xc) << 1; |
| 2828 | // op: Rs32 |
| 2829 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 2830 | Value |= (op & 0x1f) << 16; |
| 2831 | break; |
| 2832 | } |
| 2833 | case Hexagon::SS2_stored_sp: { |
| 2834 | // op: Ii |
| 2835 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 2836 | Value |= (op & 0x1f8); |
| 2837 | // op: Rtt8 |
| 2838 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 2839 | Value |= (op & 0x7); |
| 2840 | break; |
| 2841 | } |
| 2842 | case Hexagon::J2_pause: { |
| 2843 | // op: Ii |
| 2844 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 2845 | Value |= (op & 0x300) << 8; |
| 2846 | Value |= (op & 0xf8) << 5; |
| 2847 | Value |= (op & 0x7) << 2; |
| 2848 | break; |
| 2849 | } |
| 2850 | case Hexagon::PS_storerinewabs: |
| 2851 | case Hexagon::S2_storerinewgp: { |
| 2852 | // op: Ii |
| 2853 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 2854 | Value |= (op & 0x30000) << 9; |
| 2855 | Value |= (op & 0xf800) << 5; |
| 2856 | Value |= (op & 0x400) << 3; |
| 2857 | Value |= (op & 0x3fc) >> 2; |
| 2858 | // op: Nt8 |
| 2859 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 2860 | Value |= (op & 0x7) << 8; |
| 2861 | break; |
| 2862 | } |
| 2863 | case Hexagon::PS_storeriabs: |
| 2864 | case Hexagon::S2_storerigp: { |
| 2865 | // op: Ii |
| 2866 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 2867 | Value |= (op & 0x30000) << 9; |
| 2868 | Value |= (op & 0xf800) << 5; |
| 2869 | Value |= (op & 0x400) << 3; |
| 2870 | Value |= (op & 0x3fc) >> 2; |
| 2871 | // op: Rt32 |
| 2872 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 2873 | Value |= (op & 0x1f) << 8; |
| 2874 | break; |
| 2875 | } |
| 2876 | case Hexagon::PS_storerdabs: |
| 2877 | case Hexagon::S2_storerdgp: { |
| 2878 | // op: Ii |
| 2879 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 2880 | Value |= (op & 0x60000) << 8; |
| 2881 | Value |= (op & 0x1f000) << 4; |
| 2882 | Value |= (op & 0x800) << 2; |
| 2883 | Value |= (op & 0x7f8) >> 3; |
| 2884 | // op: Rtt32 |
| 2885 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 2886 | Value |= (op & 0x1f) << 8; |
| 2887 | break; |
| 2888 | } |
| 2889 | case Hexagon::SS2_storew_sp: { |
| 2890 | // op: Ii |
| 2891 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 2892 | Value |= (op & 0x7c) << 2; |
| 2893 | // op: Rt16 |
| 2894 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 2895 | Value |= (op & 0xf); |
| 2896 | break; |
| 2897 | } |
| 2898 | case Hexagon::PS_storerbnewabs: |
| 2899 | case Hexagon::S2_storerbnewgp: { |
| 2900 | // op: Ii |
| 2901 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 2902 | Value |= (op & 0xc000) << 11; |
| 2903 | Value |= (op & 0x3e00) << 7; |
| 2904 | Value |= (op & 0x100) << 5; |
| 2905 | Value |= (op & 0xff); |
| 2906 | // op: Nt8 |
| 2907 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 2908 | Value |= (op & 0x7) << 8; |
| 2909 | break; |
| 2910 | } |
| 2911 | case Hexagon::PS_storerbabs: |
| 2912 | case Hexagon::S2_storerbgp: { |
| 2913 | // op: Ii |
| 2914 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 2915 | Value |= (op & 0xc000) << 11; |
| 2916 | Value |= (op & 0x3e00) << 7; |
| 2917 | Value |= (op & 0x100) << 5; |
| 2918 | Value |= (op & 0xff); |
| 2919 | // op: Rt32 |
| 2920 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 2921 | Value |= (op & 0x1f) << 8; |
| 2922 | break; |
| 2923 | } |
| 2924 | case Hexagon::SS2_allocframe: { |
| 2925 | // op: Ii |
| 2926 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 2927 | Value |= (op & 0xf8) << 1; |
| 2928 | break; |
| 2929 | } |
| 2930 | case Hexagon::J2_trap0: |
| 2931 | case Hexagon::PS_trap1: { |
| 2932 | // op: Ii |
| 2933 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 2934 | Value |= (op & 0xf8) << 5; |
| 2935 | Value |= (op & 0x7) << 2; |
| 2936 | break; |
| 2937 | } |
| 2938 | case Hexagon::J2_call: |
| 2939 | case Hexagon::J2_jump: { |
| 2940 | // op: Ii |
| 2941 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 2942 | Value |= (op & 0xff8000) << 1; |
| 2943 | Value |= (op & 0x7ffc) >> 1; |
| 2944 | break; |
| 2945 | } |
| 2946 | case Hexagon::A4_ext: { |
| 2947 | // op: Ii |
| 2948 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 2949 | Value |= (op & 0xfff00000) >> 4; |
| 2950 | Value |= (op & 0xfffc0) >> 6; |
| 2951 | break; |
| 2952 | } |
| 2953 | case Hexagon::V6_vwhist128qm: { |
| 2954 | // op: Ii |
| 2955 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 2956 | Value |= (op & 0x1) << 8; |
| 2957 | // op: Qv4 |
| 2958 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 2959 | Value |= (op & 0x3) << 22; |
| 2960 | break; |
| 2961 | } |
| 2962 | case Hexagon::S2_storerinew_io: { |
| 2963 | // op: Ii |
| 2964 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 2965 | Value |= (op & 0x1800) << 14; |
| 2966 | Value |= (op & 0x400) << 3; |
| 2967 | Value |= (op & 0x3fc) >> 2; |
| 2968 | // op: Rs32 |
| 2969 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 2970 | Value |= (op & 0x1f) << 16; |
| 2971 | // op: Nt8 |
| 2972 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 2973 | Value |= (op & 0x7) << 8; |
| 2974 | break; |
| 2975 | } |
| 2976 | case Hexagon::S2_storeri_io: { |
| 2977 | // op: Ii |
| 2978 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 2979 | Value |= (op & 0x1800) << 14; |
| 2980 | Value |= (op & 0x400) << 3; |
| 2981 | Value |= (op & 0x3fc) >> 2; |
| 2982 | // op: Rs32 |
| 2983 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 2984 | Value |= (op & 0x1f) << 16; |
| 2985 | // op: Rt32 |
| 2986 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 2987 | Value |= (op & 0x1f) << 8; |
| 2988 | break; |
| 2989 | } |
| 2990 | case Hexagon::L2_loadrhgp: |
| 2991 | case Hexagon::L2_loadruhgp: |
| 2992 | case Hexagon::PS_loadrhabs: |
| 2993 | case Hexagon::PS_loadruhabs: { |
| 2994 | // op: Ii |
| 2995 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 2996 | Value |= (op & 0x18000) << 10; |
| 2997 | Value |= (op & 0x7c00) << 6; |
| 2998 | Value |= (op & 0x3fe) << 4; |
| 2999 | // op: Rd32 |
| 3000 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3001 | Value |= (op & 0x1f); |
| 3002 | break; |
| 3003 | } |
| 3004 | case Hexagon::J2_callf: |
| 3005 | case Hexagon::J2_callt: |
| 3006 | case Hexagon::J2_jumpf: |
| 3007 | case Hexagon::J2_jumpfnew: |
| 3008 | case Hexagon::J2_jumpfnewpt: |
| 3009 | case Hexagon::J2_jumpfpt: |
| 3010 | case Hexagon::J2_jumpt: |
| 3011 | case Hexagon::J2_jumptnew: |
| 3012 | case Hexagon::J2_jumptnewpt: |
| 3013 | case Hexagon::J2_jumptpt: { |
| 3014 | // op: Ii |
| 3015 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3016 | Value |= (op & 0x18000) << 7; |
| 3017 | Value |= (op & 0x7c00) << 6; |
| 3018 | Value |= (op & 0x200) << 4; |
| 3019 | Value |= (op & 0x1fc) >> 1; |
| 3020 | // op: Pu4 |
| 3021 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3022 | Value |= (op & 0x3) << 8; |
| 3023 | break; |
| 3024 | } |
| 3025 | case Hexagon::S2_mask: { |
| 3026 | // op: Ii |
| 3027 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3028 | Value |= (op & 0x1f) << 8; |
| 3029 | // op: II |
| 3030 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3031 | Value |= (op & 0x18) << 18; |
| 3032 | Value |= (op & 0x7) << 5; |
| 3033 | // op: Rd32 |
| 3034 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3035 | Value |= (op & 0x1f); |
| 3036 | break; |
| 3037 | } |
| 3038 | case Hexagon::S4_storerbnew_ur: |
| 3039 | case Hexagon::S4_storerhnew_ur: |
| 3040 | case Hexagon::S4_storerinew_ur: { |
| 3041 | // op: Ii |
| 3042 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3043 | Value |= (op & 0x2) << 12; |
| 3044 | Value |= (op & 0x1) << 6; |
| 3045 | // op: II |
| 3046 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3047 | Value |= (op & 0x3f); |
| 3048 | // op: Ru32 |
| 3049 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3050 | Value |= (op & 0x1f) << 16; |
| 3051 | // op: Nt8 |
| 3052 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 3053 | Value |= (op & 0x7) << 8; |
| 3054 | break; |
| 3055 | } |
| 3056 | case Hexagon::S4_storerb_ur: |
| 3057 | case Hexagon::S4_storerf_ur: |
| 3058 | case Hexagon::S4_storerh_ur: |
| 3059 | case Hexagon::S4_storeri_ur: { |
| 3060 | // op: Ii |
| 3061 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3062 | Value |= (op & 0x2) << 12; |
| 3063 | Value |= (op & 0x1) << 6; |
| 3064 | // op: II |
| 3065 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3066 | Value |= (op & 0x3f); |
| 3067 | // op: Ru32 |
| 3068 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3069 | Value |= (op & 0x1f) << 16; |
| 3070 | // op: Rt32 |
| 3071 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 3072 | Value |= (op & 0x1f) << 8; |
| 3073 | break; |
| 3074 | } |
| 3075 | case Hexagon::S4_storerd_ur: { |
| 3076 | // op: Ii |
| 3077 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3078 | Value |= (op & 0x2) << 12; |
| 3079 | Value |= (op & 0x1) << 6; |
| 3080 | // op: II |
| 3081 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3082 | Value |= (op & 0x3f); |
| 3083 | // op: Ru32 |
| 3084 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3085 | Value |= (op & 0x1f) << 16; |
| 3086 | // op: Rtt32 |
| 3087 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 3088 | Value |= (op & 0x1f) << 8; |
| 3089 | break; |
| 3090 | } |
| 3091 | case Hexagon::F2_sfimm_n: |
| 3092 | case Hexagon::F2_sfimm_p: { |
| 3093 | // op: Ii |
| 3094 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3095 | Value |= (op & 0x200) << 12; |
| 3096 | Value |= (op & 0x1ff) << 5; |
| 3097 | // op: Rd32 |
| 3098 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3099 | Value |= (op & 0x1f); |
| 3100 | break; |
| 3101 | } |
| 3102 | case Hexagon::F2_dfimm_n: |
| 3103 | case Hexagon::F2_dfimm_p: { |
| 3104 | // op: Ii |
| 3105 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3106 | Value |= (op & 0x200) << 12; |
| 3107 | Value |= (op & 0x1ff) << 5; |
| 3108 | // op: Rdd32 |
| 3109 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3110 | Value |= (op & 0x1f); |
| 3111 | break; |
| 3112 | } |
| 3113 | case Hexagon::A2_subri: { |
| 3114 | // op: Ii |
| 3115 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3116 | Value |= (op & 0x200) << 12; |
| 3117 | Value |= (op & 0x1ff) << 5; |
| 3118 | // op: Rs32 |
| 3119 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3120 | Value |= (op & 0x1f) << 16; |
| 3121 | // op: Rd32 |
| 3122 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3123 | Value |= (op & 0x1f); |
| 3124 | break; |
| 3125 | } |
| 3126 | case Hexagon::SA1_combine0i: |
| 3127 | case Hexagon::SA1_combine1i: |
| 3128 | case Hexagon::SA1_combine2i: |
| 3129 | case Hexagon::SA1_combine3i: { |
| 3130 | // op: Ii |
| 3131 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3132 | Value |= (op & 0x3) << 5; |
| 3133 | // op: Rdd8 |
| 3134 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3135 | Value |= (op & 0x7); |
| 3136 | break; |
| 3137 | } |
| 3138 | case Hexagon::SA1_cmpeqi: { |
| 3139 | // op: Ii |
| 3140 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3141 | Value |= (op & 0x3); |
| 3142 | // op: Rs16 |
| 3143 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3144 | Value |= (op & 0xf) << 4; |
| 3145 | break; |
| 3146 | } |
| 3147 | case Hexagon::S4_pstorerbnewf_abs: |
| 3148 | case Hexagon::S4_pstorerbnewfnew_abs: |
| 3149 | case Hexagon::S4_pstorerbnewt_abs: |
| 3150 | case Hexagon::S4_pstorerbnewtnew_abs: |
| 3151 | case Hexagon::S4_pstorerhnewf_abs: |
| 3152 | case Hexagon::S4_pstorerhnewfnew_abs: |
| 3153 | case Hexagon::S4_pstorerhnewt_abs: |
| 3154 | case Hexagon::S4_pstorerhnewtnew_abs: |
| 3155 | case Hexagon::S4_pstorerinewf_abs: |
| 3156 | case Hexagon::S4_pstorerinewfnew_abs: |
| 3157 | case Hexagon::S4_pstorerinewt_abs: |
| 3158 | case Hexagon::S4_pstorerinewtnew_abs: { |
| 3159 | // op: Ii |
| 3160 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3161 | Value |= (op & 0x30) << 12; |
| 3162 | Value |= (op & 0xf) << 3; |
| 3163 | // op: Pv4 |
| 3164 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3165 | Value |= (op & 0x3); |
| 3166 | // op: Nt8 |
| 3167 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3168 | Value |= (op & 0x7) << 8; |
| 3169 | break; |
| 3170 | } |
| 3171 | case Hexagon::S4_pstorerbf_abs: |
| 3172 | case Hexagon::S4_pstorerbfnew_abs: |
| 3173 | case Hexagon::S4_pstorerbt_abs: |
| 3174 | case Hexagon::S4_pstorerbtnew_abs: |
| 3175 | case Hexagon::S4_pstorerff_abs: |
| 3176 | case Hexagon::S4_pstorerffnew_abs: |
| 3177 | case Hexagon::S4_pstorerft_abs: |
| 3178 | case Hexagon::S4_pstorerftnew_abs: |
| 3179 | case Hexagon::S4_pstorerhf_abs: |
| 3180 | case Hexagon::S4_pstorerhfnew_abs: |
| 3181 | case Hexagon::S4_pstorerht_abs: |
| 3182 | case Hexagon::S4_pstorerhtnew_abs: |
| 3183 | case Hexagon::S4_pstorerif_abs: |
| 3184 | case Hexagon::S4_pstorerifnew_abs: |
| 3185 | case Hexagon::S4_pstorerit_abs: |
| 3186 | case Hexagon::S4_pstoreritnew_abs: { |
| 3187 | // op: Ii |
| 3188 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3189 | Value |= (op & 0x30) << 12; |
| 3190 | Value |= (op & 0xf) << 3; |
| 3191 | // op: Pv4 |
| 3192 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3193 | Value |= (op & 0x3); |
| 3194 | // op: Rt32 |
| 3195 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3196 | Value |= (op & 0x1f) << 8; |
| 3197 | break; |
| 3198 | } |
| 3199 | case Hexagon::S4_pstorerdf_abs: |
| 3200 | case Hexagon::S4_pstorerdfnew_abs: |
| 3201 | case Hexagon::S4_pstorerdt_abs: |
| 3202 | case Hexagon::S4_pstorerdtnew_abs: { |
| 3203 | // op: Ii |
| 3204 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3205 | Value |= (op & 0x30) << 12; |
| 3206 | Value |= (op & 0xf) << 3; |
| 3207 | // op: Pv4 |
| 3208 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3209 | Value |= (op & 0x3); |
| 3210 | // op: Rtt32 |
| 3211 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3212 | Value |= (op & 0x1f) << 8; |
| 3213 | break; |
| 3214 | } |
| 3215 | case Hexagon::M4_mpyri_addi: { |
| 3216 | // op: Ii |
| 3217 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3218 | Value |= (op & 0x30) << 17; |
| 3219 | Value |= (op & 0x8) << 10; |
| 3220 | Value |= (op & 0x7) << 5; |
| 3221 | // op: II |
| 3222 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 3223 | Value |= (op & 0x20) << 18; |
| 3224 | Value |= (op & 0x1f); |
| 3225 | // op: Rs32 |
| 3226 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3227 | Value |= (op & 0x1f) << 16; |
| 3228 | // op: Rd32 |
| 3229 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3230 | Value |= (op & 0x1f) << 8; |
| 3231 | break; |
| 3232 | } |
| 3233 | case Hexagon::M4_mpyrr_addi: { |
| 3234 | // op: Ii |
| 3235 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3236 | Value |= (op & 0x30) << 17; |
| 3237 | Value |= (op & 0x8) << 10; |
| 3238 | Value |= (op & 0x7) << 5; |
| 3239 | // op: Rs32 |
| 3240 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3241 | Value |= (op & 0x1f) << 16; |
| 3242 | // op: Rt32 |
| 3243 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 3244 | Value |= (op & 0x1f) << 8; |
| 3245 | // op: Rd32 |
| 3246 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3247 | Value |= (op & 0x1f); |
| 3248 | break; |
| 3249 | } |
| 3250 | case Hexagon::S2_storerd_io: { |
| 3251 | // op: Ii |
| 3252 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3253 | Value |= (op & 0x3000) << 13; |
| 3254 | Value |= (op & 0x800) << 2; |
| 3255 | Value |= (op & 0x7f8) >> 3; |
| 3256 | // op: Rs32 |
| 3257 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3258 | Value |= (op & 0x1f) << 16; |
| 3259 | // op: Rtt32 |
| 3260 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3261 | Value |= (op & 0x1f) << 8; |
| 3262 | break; |
| 3263 | } |
| 3264 | case Hexagon::L2_loadrigp: |
| 3265 | case Hexagon::PS_loadriabs: { |
| 3266 | // op: Ii |
| 3267 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3268 | Value |= (op & 0x30000) << 9; |
| 3269 | Value |= (op & 0xf800) << 5; |
| 3270 | Value |= (op & 0x7fc) << 3; |
| 3271 | // op: Rd32 |
| 3272 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3273 | Value |= (op & 0x1f); |
| 3274 | break; |
| 3275 | } |
| 3276 | case Hexagon::SS1_storew_io: { |
| 3277 | // op: Ii |
| 3278 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3279 | Value |= (op & 0x3c) << 6; |
| 3280 | // op: Rs16 |
| 3281 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3282 | Value |= (op & 0xf) << 4; |
| 3283 | // op: Rt16 |
| 3284 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3285 | Value |= (op & 0xf); |
| 3286 | break; |
| 3287 | } |
| 3288 | case Hexagon::SS2_storewi0: |
| 3289 | case Hexagon::SS2_storewi1: { |
| 3290 | // op: Ii |
| 3291 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3292 | Value |= (op & 0x3c) >> 2; |
| 3293 | // op: Rs16 |
| 3294 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3295 | Value |= (op & 0xf) << 4; |
| 3296 | break; |
| 3297 | } |
| 3298 | case Hexagon::S4_lsli: { |
| 3299 | // op: Ii |
| 3300 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3301 | Value |= (op & 0x3e) << 15; |
| 3302 | Value |= (op & 0x1) << 5; |
| 3303 | // op: Rt32 |
| 3304 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3305 | Value |= (op & 0x1f) << 8; |
| 3306 | // op: Rd32 |
| 3307 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3308 | Value |= (op & 0x1f); |
| 3309 | break; |
| 3310 | } |
| 3311 | case Hexagon::SA1_seti: { |
| 3312 | // op: Ii |
| 3313 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3314 | Value |= (op & 0x3f) << 4; |
| 3315 | // op: Rd16 |
| 3316 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3317 | Value |= (op & 0xf); |
| 3318 | break; |
| 3319 | } |
| 3320 | case Hexagon::L4_iadd_memopb_io: |
| 3321 | case Hexagon::L4_iand_memopb_io: |
| 3322 | case Hexagon::L4_ior_memopb_io: |
| 3323 | case Hexagon::L4_isub_memopb_io: { |
| 3324 | // op: Ii |
| 3325 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3326 | Value |= (op & 0x3f) << 7; |
| 3327 | // op: II |
| 3328 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3329 | Value |= (op & 0x1f); |
| 3330 | // op: Rs32 |
| 3331 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3332 | Value |= (op & 0x1f) << 16; |
| 3333 | break; |
| 3334 | } |
| 3335 | case Hexagon::S4_storeirb_io: { |
| 3336 | // op: Ii |
| 3337 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3338 | Value |= (op & 0x3f) << 7; |
| 3339 | // op: II |
| 3340 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3341 | Value |= (op & 0x80) << 6; |
| 3342 | Value |= (op & 0x7f); |
| 3343 | // op: Rs32 |
| 3344 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3345 | Value |= (op & 0x1f) << 16; |
| 3346 | break; |
| 3347 | } |
| 3348 | case Hexagon::C4_addipc: { |
| 3349 | // op: Ii |
| 3350 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3351 | Value |= (op & 0x3f) << 7; |
| 3352 | // op: Rd32 |
| 3353 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3354 | Value |= (op & 0x1f); |
| 3355 | break; |
| 3356 | } |
| 3357 | case Hexagon::L4_add_memopb_io: |
| 3358 | case Hexagon::L4_and_memopb_io: |
| 3359 | case Hexagon::L4_or_memopb_io: |
| 3360 | case Hexagon::L4_sub_memopb_io: { |
| 3361 | // op: Ii |
| 3362 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3363 | Value |= (op & 0x3f) << 7; |
| 3364 | // op: Rs32 |
| 3365 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3366 | Value |= (op & 0x1f) << 16; |
| 3367 | // op: Rt32 |
| 3368 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3369 | Value |= (op & 0x1f); |
| 3370 | break; |
| 3371 | } |
| 3372 | case Hexagon::Y2_dcfetchbo: { |
| 3373 | // op: Ii |
| 3374 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3375 | Value |= (op & 0x3ff8) >> 3; |
| 3376 | // op: Rs32 |
| 3377 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3378 | Value |= (op & 0x1f) << 16; |
| 3379 | break; |
| 3380 | } |
| 3381 | case Hexagon::J2_jumprgtez: |
| 3382 | case Hexagon::J2_jumprgtezpt: |
| 3383 | case Hexagon::J2_jumprltez: |
| 3384 | case Hexagon::J2_jumprltezpt: |
| 3385 | case Hexagon::J2_jumprnz: |
| 3386 | case Hexagon::J2_jumprnzpt: |
| 3387 | case Hexagon::J2_jumprz: |
| 3388 | case Hexagon::J2_jumprzpt: { |
| 3389 | // op: Ii |
| 3390 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3391 | Value |= (op & 0x4000) << 7; |
| 3392 | Value |= (op & 0x2000); |
| 3393 | Value |= (op & 0x1ffc) >> 1; |
| 3394 | // op: Rs32 |
| 3395 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3396 | Value |= (op & 0x1f) << 16; |
| 3397 | break; |
| 3398 | } |
| 3399 | case Hexagon::J4_tstbit0_f_jumpnv_nt: |
| 3400 | case Hexagon::J4_tstbit0_f_jumpnv_t: |
| 3401 | case Hexagon::J4_tstbit0_t_jumpnv_nt: |
| 3402 | case Hexagon::J4_tstbit0_t_jumpnv_t: { |
| 3403 | // op: Ii |
| 3404 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3405 | Value |= (op & 0x600) << 11; |
| 3406 | Value |= (op & 0x1fc) >> 1; |
| 3407 | // op: Ns8 |
| 3408 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3409 | Value |= (op & 0x7) << 16; |
| 3410 | break; |
| 3411 | } |
| 3412 | case Hexagon::J4_tstbit0_fp0_jump_nt: |
| 3413 | case Hexagon::J4_tstbit0_fp0_jump_t: |
| 3414 | case Hexagon::J4_tstbit0_fp1_jump_nt: |
| 3415 | case Hexagon::J4_tstbit0_fp1_jump_t: |
| 3416 | case Hexagon::J4_tstbit0_tp0_jump_nt: |
| 3417 | case Hexagon::J4_tstbit0_tp0_jump_t: |
| 3418 | case Hexagon::J4_tstbit0_tp1_jump_nt: |
| 3419 | case Hexagon::J4_tstbit0_tp1_jump_t: { |
| 3420 | // op: Ii |
| 3421 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3422 | Value |= (op & 0x600) << 11; |
| 3423 | Value |= (op & 0x1fc) >> 1; |
| 3424 | // op: Rs16 |
| 3425 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3426 | Value |= (op & 0xf) << 16; |
| 3427 | break; |
| 3428 | } |
| 3429 | case Hexagon::S2_storerbnew_io: { |
| 3430 | // op: Ii |
| 3431 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3432 | Value |= (op & 0x600) << 16; |
| 3433 | Value |= (op & 0x100) << 5; |
| 3434 | Value |= (op & 0xff); |
| 3435 | // op: Rs32 |
| 3436 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3437 | Value |= (op & 0x1f) << 16; |
| 3438 | // op: Nt8 |
| 3439 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3440 | Value |= (op & 0x7) << 8; |
| 3441 | break; |
| 3442 | } |
| 3443 | case Hexagon::S2_storerb_io: { |
| 3444 | // op: Ii |
| 3445 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3446 | Value |= (op & 0x600) << 16; |
| 3447 | Value |= (op & 0x100) << 5; |
| 3448 | Value |= (op & 0xff); |
| 3449 | // op: Rs32 |
| 3450 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3451 | Value |= (op & 0x1f) << 16; |
| 3452 | // op: Rt32 |
| 3453 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3454 | Value |= (op & 0x1f) << 8; |
| 3455 | break; |
| 3456 | } |
| 3457 | case Hexagon::L2_loadrdgp: |
| 3458 | case Hexagon::PS_loadrdabs: { |
| 3459 | // op: Ii |
| 3460 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3461 | Value |= (op & 0x60000) << 8; |
| 3462 | Value |= (op & 0x1f000) << 4; |
| 3463 | Value |= (op & 0xff8) << 2; |
| 3464 | // op: Rdd32 |
| 3465 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3466 | Value |= (op & 0x1f); |
| 3467 | break; |
| 3468 | } |
| 3469 | case Hexagon::SL2_loadri_sp: { |
| 3470 | // op: Ii |
| 3471 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3472 | Value |= (op & 0x7c) << 2; |
| 3473 | // op: Rd16 |
| 3474 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3475 | Value |= (op & 0xf); |
| 3476 | break; |
| 3477 | } |
| 3478 | case Hexagon::L4_iadd_memoph_io: |
| 3479 | case Hexagon::L4_iand_memoph_io: |
| 3480 | case Hexagon::L4_ior_memoph_io: |
| 3481 | case Hexagon::L4_isub_memoph_io: { |
| 3482 | // op: Ii |
| 3483 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3484 | Value |= (op & 0x7e) << 6; |
| 3485 | // op: II |
| 3486 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3487 | Value |= (op & 0x1f); |
| 3488 | // op: Rs32 |
| 3489 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3490 | Value |= (op & 0x1f) << 16; |
| 3491 | break; |
| 3492 | } |
| 3493 | case Hexagon::S4_storeirh_io: { |
| 3494 | // op: Ii |
| 3495 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3496 | Value |= (op & 0x7e) << 6; |
| 3497 | // op: II |
| 3498 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3499 | Value |= (op & 0x80) << 6; |
| 3500 | Value |= (op & 0x7f); |
| 3501 | // op: Rs32 |
| 3502 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3503 | Value |= (op & 0x1f) << 16; |
| 3504 | break; |
| 3505 | } |
| 3506 | case Hexagon::L4_add_memoph_io: |
| 3507 | case Hexagon::L4_and_memoph_io: |
| 3508 | case Hexagon::L4_or_memoph_io: |
| 3509 | case Hexagon::L4_sub_memoph_io: { |
| 3510 | // op: Ii |
| 3511 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3512 | Value |= (op & 0x7e) << 6; |
| 3513 | // op: Rs32 |
| 3514 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3515 | Value |= (op & 0x1f) << 16; |
| 3516 | // op: Rt32 |
| 3517 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3518 | Value |= (op & 0x1f); |
| 3519 | break; |
| 3520 | } |
| 3521 | case Hexagon::V6_vS32b_srls_ai: |
| 3522 | case Hexagon::V6_zLd_ai: { |
| 3523 | // op: Ii |
| 3524 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3525 | Value |= (op & 0x8) << 10; |
| 3526 | Value |= (op & 0x7) << 8; |
| 3527 | // op: Rt32 |
| 3528 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3529 | Value |= (op & 0x1f) << 16; |
| 3530 | break; |
| 3531 | } |
| 3532 | case Hexagon::V6_vS32b_new_ai: |
| 3533 | case Hexagon::V6_vS32b_nt_new_ai: { |
| 3534 | // op: Ii |
| 3535 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3536 | Value |= (op & 0x8) << 10; |
| 3537 | Value |= (op & 0x7) << 8; |
| 3538 | // op: Rt32 |
| 3539 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3540 | Value |= (op & 0x1f) << 16; |
| 3541 | // op: Os8 |
| 3542 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3543 | Value |= (op & 0x7); |
| 3544 | break; |
| 3545 | } |
| 3546 | case Hexagon::V6_vS32Ub_ai: |
| 3547 | case Hexagon::V6_vS32b_ai: |
| 3548 | case Hexagon::V6_vS32b_nt_ai: { |
| 3549 | // op: Ii |
| 3550 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3551 | Value |= (op & 0x8) << 10; |
| 3552 | Value |= (op & 0x7) << 8; |
| 3553 | // op: Rt32 |
| 3554 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3555 | Value |= (op & 0x1f) << 16; |
| 3556 | // op: Vs32 |
| 3557 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3558 | Value |= (op & 0x1f); |
| 3559 | break; |
| 3560 | } |
| 3561 | case Hexagon::S2_storerhnew_io: { |
| 3562 | // op: Ii |
| 3563 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3564 | Value |= (op & 0xc00) << 15; |
| 3565 | Value |= (op & 0x200) << 4; |
| 3566 | Value |= (op & 0x1fe) >> 1; |
| 3567 | // op: Rs32 |
| 3568 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3569 | Value |= (op & 0x1f) << 16; |
| 3570 | // op: Nt8 |
| 3571 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3572 | Value |= (op & 0x7) << 8; |
| 3573 | break; |
| 3574 | } |
| 3575 | case Hexagon::S2_storerf_io: |
| 3576 | case Hexagon::S2_storerh_io: { |
| 3577 | // op: Ii |
| 3578 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3579 | Value |= (op & 0xc00) << 15; |
| 3580 | Value |= (op & 0x200) << 4; |
| 3581 | Value |= (op & 0x1fe) >> 1; |
| 3582 | // op: Rs32 |
| 3583 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3584 | Value |= (op & 0x1f) << 16; |
| 3585 | // op: Rt32 |
| 3586 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3587 | Value |= (op & 0x1f) << 8; |
| 3588 | break; |
| 3589 | } |
| 3590 | case Hexagon::L2_loadrbgp: |
| 3591 | case Hexagon::L2_loadrubgp: |
| 3592 | case Hexagon::PS_loadrbabs: |
| 3593 | case Hexagon::PS_loadrubabs: { |
| 3594 | // op: Ii |
| 3595 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3596 | Value |= (op & 0xc000) << 11; |
| 3597 | Value |= (op & 0x3e00) << 7; |
| 3598 | Value |= (op & 0x1ff) << 5; |
| 3599 | // op: Rd32 |
| 3600 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3601 | Value |= (op & 0x1f); |
| 3602 | break; |
| 3603 | } |
| 3604 | case Hexagon::A2_tfrsi: { |
| 3605 | // op: Ii |
| 3606 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3607 | Value |= (op & 0xc000) << 8; |
| 3608 | Value |= (op & 0x3e00) << 7; |
| 3609 | Value |= (op & 0x1ff) << 5; |
| 3610 | // op: Rd32 |
| 3611 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3612 | Value |= (op & 0x1f); |
| 3613 | break; |
| 3614 | } |
| 3615 | case Hexagon::SS2_storeh_io: { |
| 3616 | // op: Ii |
| 3617 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3618 | Value |= (op & 0xe) << 7; |
| 3619 | // op: Rs16 |
| 3620 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3621 | Value |= (op & 0xf) << 4; |
| 3622 | // op: Rt16 |
| 3623 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3624 | Value |= (op & 0xf); |
| 3625 | break; |
| 3626 | } |
| 3627 | case Hexagon::S4_addi_asl_ri: |
| 3628 | case Hexagon::S4_addi_lsr_ri: |
| 3629 | case Hexagon::S4_andi_asl_ri: |
| 3630 | case Hexagon::S4_andi_lsr_ri: |
| 3631 | case Hexagon::S4_ori_asl_ri: |
| 3632 | case Hexagon::S4_ori_lsr_ri: |
| 3633 | case Hexagon::S4_subi_asl_ri: |
| 3634 | case Hexagon::S4_subi_lsr_ri: { |
| 3635 | // op: Ii |
| 3636 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3637 | Value |= (op & 0xe0) << 16; |
| 3638 | Value |= (op & 0x10) << 9; |
| 3639 | Value |= (op & 0xe) << 4; |
| 3640 | Value |= (op & 0x1) << 3; |
| 3641 | // op: II |
| 3642 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 3643 | Value |= (op & 0x1f) << 8; |
| 3644 | // op: Rx32 |
| 3645 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3646 | Value |= (op & 0x1f) << 16; |
| 3647 | break; |
| 3648 | } |
| 3649 | case Hexagon::SS1_storeb_io: { |
| 3650 | // op: Ii |
| 3651 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3652 | Value |= (op & 0xf) << 8; |
| 3653 | // op: Rs16 |
| 3654 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3655 | Value |= (op & 0xf) << 4; |
| 3656 | // op: Rt16 |
| 3657 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3658 | Value |= (op & 0xf); |
| 3659 | break; |
| 3660 | } |
| 3661 | case Hexagon::SS2_storebi0: |
| 3662 | case Hexagon::SS2_storebi1: { |
| 3663 | // op: Ii |
| 3664 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3665 | Value |= (op & 0xf); |
| 3666 | // op: Rs16 |
| 3667 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3668 | Value |= (op & 0xf) << 4; |
| 3669 | break; |
| 3670 | } |
| 3671 | case Hexagon::SL2_loadrd_sp: { |
| 3672 | // op: Ii |
| 3673 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3674 | Value |= (op & 0xf8); |
| 3675 | // op: Rdd8 |
| 3676 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3677 | Value |= (op & 0x7); |
| 3678 | break; |
| 3679 | } |
| 3680 | case Hexagon::SA1_addsp: { |
| 3681 | // op: Ii |
| 3682 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3683 | Value |= (op & 0xfc) << 2; |
| 3684 | // op: Rd16 |
| 3685 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3686 | Value |= (op & 0xf); |
| 3687 | break; |
| 3688 | } |
| 3689 | case Hexagon::L4_iadd_memopw_io: |
| 3690 | case Hexagon::L4_iand_memopw_io: |
| 3691 | case Hexagon::L4_ior_memopw_io: |
| 3692 | case Hexagon::L4_isub_memopw_io: { |
| 3693 | // op: Ii |
| 3694 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3695 | Value |= (op & 0xfc) << 5; |
| 3696 | // op: II |
| 3697 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3698 | Value |= (op & 0x1f); |
| 3699 | // op: Rs32 |
| 3700 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3701 | Value |= (op & 0x1f) << 16; |
| 3702 | break; |
| 3703 | } |
| 3704 | case Hexagon::S4_storeiri_io: { |
| 3705 | // op: Ii |
| 3706 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3707 | Value |= (op & 0xfc) << 5; |
| 3708 | // op: II |
| 3709 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3710 | Value |= (op & 0x80) << 6; |
| 3711 | Value |= (op & 0x7f); |
| 3712 | // op: Rs32 |
| 3713 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3714 | Value |= (op & 0x1f) << 16; |
| 3715 | break; |
| 3716 | } |
| 3717 | case Hexagon::L4_add_memopw_io: |
| 3718 | case Hexagon::L4_and_memopw_io: |
| 3719 | case Hexagon::L4_or_memopw_io: |
| 3720 | case Hexagon::L4_sub_memopw_io: { |
| 3721 | // op: Ii |
| 3722 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3723 | Value |= (op & 0xfc) << 5; |
| 3724 | // op: Rs32 |
| 3725 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3726 | Value |= (op & 0x1f) << 16; |
| 3727 | // op: Rt32 |
| 3728 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3729 | Value |= (op & 0x1f); |
| 3730 | break; |
| 3731 | } |
| 3732 | case Hexagon::A4_combineii: { |
| 3733 | // op: Ii |
| 3734 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3735 | Value |= (op & 0xff) << 5; |
| 3736 | // op: II |
| 3737 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3738 | Value |= (op & 0x3e) << 15; |
| 3739 | Value |= (op & 0x1) << 13; |
| 3740 | // op: Rdd32 |
| 3741 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3742 | Value |= (op & 0x1f); |
| 3743 | break; |
| 3744 | } |
| 3745 | case Hexagon::A2_combineii: { |
| 3746 | // op: Ii |
| 3747 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3748 | Value |= (op & 0xff) << 5; |
| 3749 | // op: II |
| 3750 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3751 | Value |= (op & 0xfe) << 15; |
| 3752 | Value |= (op & 0x1) << 13; |
| 3753 | // op: Rdd32 |
| 3754 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3755 | Value |= (op & 0x1f); |
| 3756 | break; |
| 3757 | } |
| 3758 | case Hexagon::A4_combineir: { |
| 3759 | // op: Ii |
| 3760 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3761 | Value |= (op & 0xff) << 5; |
| 3762 | // op: Rs32 |
| 3763 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3764 | Value |= (op & 0x1f) << 16; |
| 3765 | // op: Rdd32 |
| 3766 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3767 | Value |= (op & 0x1f); |
| 3768 | break; |
| 3769 | } |
| 3770 | case Hexagon::S2_pstorerdf_io: |
| 3771 | case Hexagon::S2_pstorerdt_io: |
| 3772 | case Hexagon::S4_pstorerdfnew_io: |
| 3773 | case Hexagon::S4_pstorerdtnew_io: { |
| 3774 | // op: Ii |
| 3775 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3776 | Value |= (op & 0x100) << 5; |
| 3777 | Value |= (op & 0xf8); |
| 3778 | // op: Pv4 |
| 3779 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3780 | Value |= (op & 0x3); |
| 3781 | // op: Rs32 |
| 3782 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3783 | Value |= (op & 0x1f) << 16; |
| 3784 | // op: Rtt32 |
| 3785 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 3786 | Value |= (op & 0x1f) << 8; |
| 3787 | break; |
| 3788 | } |
| 3789 | case Hexagon::L2_loadri_io: { |
| 3790 | // op: Ii |
| 3791 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3792 | Value |= (op & 0x1800) << 14; |
| 3793 | Value |= (op & 0x7fc) << 3; |
| 3794 | // op: Rs32 |
| 3795 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3796 | Value |= (op & 0x1f) << 16; |
| 3797 | // op: Rd32 |
| 3798 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3799 | Value |= (op & 0x1f); |
| 3800 | break; |
| 3801 | } |
| 3802 | case Hexagon::L2_loadbsw4_io: |
| 3803 | case Hexagon::L2_loadbzw4_io: { |
| 3804 | // op: Ii |
| 3805 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3806 | Value |= (op & 0x1800) << 14; |
| 3807 | Value |= (op & 0x7fc) << 3; |
| 3808 | // op: Rs32 |
| 3809 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3810 | Value |= (op & 0x1f) << 16; |
| 3811 | // op: Rdd32 |
| 3812 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3813 | Value |= (op & 0x1f); |
| 3814 | break; |
| 3815 | } |
| 3816 | case Hexagon::S2_storerhnew_pci: { |
| 3817 | // op: Ii |
| 3818 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3819 | Value |= (op & 0x1e) << 2; |
| 3820 | // op: Mu2 |
| 3821 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 3822 | Value |= (op & 0x1) << 13; |
| 3823 | // op: Nt8 |
| 3824 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 3825 | Value |= (op & 0x7) << 8; |
| 3826 | // op: Rx32 |
| 3827 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3828 | Value |= (op & 0x1f) << 16; |
| 3829 | break; |
| 3830 | } |
| 3831 | case Hexagon::S2_storerf_pci: |
| 3832 | case Hexagon::S2_storerh_pci: { |
| 3833 | // op: Ii |
| 3834 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3835 | Value |= (op & 0x1e) << 2; |
| 3836 | // op: Mu2 |
| 3837 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 3838 | Value |= (op & 0x1) << 13; |
| 3839 | // op: Rt32 |
| 3840 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 3841 | Value |= (op & 0x1f) << 8; |
| 3842 | // op: Rx32 |
| 3843 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3844 | Value |= (op & 0x1f) << 16; |
| 3845 | break; |
| 3846 | } |
| 3847 | case Hexagon::S2_storerhnew_pi: { |
| 3848 | // op: Ii |
| 3849 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3850 | Value |= (op & 0x1e) << 2; |
| 3851 | // op: Nt8 |
| 3852 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 3853 | Value |= (op & 0x7) << 8; |
| 3854 | // op: Rx32 |
| 3855 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3856 | Value |= (op & 0x1f) << 16; |
| 3857 | break; |
| 3858 | } |
| 3859 | case Hexagon::S2_storerf_pi: |
| 3860 | case Hexagon::S2_storerh_pi: { |
| 3861 | // op: Ii |
| 3862 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3863 | Value |= (op & 0x1e) << 2; |
| 3864 | // op: Rt32 |
| 3865 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 3866 | Value |= (op & 0x1f) << 8; |
| 3867 | // op: Rx32 |
| 3868 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3869 | Value |= (op & 0x1f) << 16; |
| 3870 | break; |
| 3871 | } |
| 3872 | case Hexagon::F2_dfclass: { |
| 3873 | // op: Ii |
| 3874 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3875 | Value |= (op & 0x1f) << 5; |
| 3876 | // op: Rss32 |
| 3877 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3878 | Value |= (op & 0x1f) << 16; |
| 3879 | // op: Pd4 |
| 3880 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3881 | Value |= (op & 0x3); |
| 3882 | break; |
| 3883 | } |
| 3884 | case Hexagon::S2_extractu: |
| 3885 | case Hexagon::S4_extract: { |
| 3886 | // op: Ii |
| 3887 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3888 | Value |= (op & 0x1f) << 8; |
| 3889 | // op: II |
| 3890 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 3891 | Value |= (op & 0x18) << 18; |
| 3892 | Value |= (op & 0x7) << 5; |
| 3893 | // op: Rs32 |
| 3894 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3895 | Value |= (op & 0x1f) << 16; |
| 3896 | // op: Rd32 |
| 3897 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3898 | Value |= (op & 0x1f); |
| 3899 | break; |
| 3900 | } |
| 3901 | case Hexagon::F2_sfclass: |
| 3902 | case Hexagon::S2_tstbit_i: |
| 3903 | case Hexagon::S4_ntstbit_i: { |
| 3904 | // op: Ii |
| 3905 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3906 | Value |= (op & 0x1f) << 8; |
| 3907 | // op: Rs32 |
| 3908 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3909 | Value |= (op & 0x1f) << 16; |
| 3910 | // op: Pd4 |
| 3911 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3912 | Value |= (op & 0x3); |
| 3913 | break; |
| 3914 | } |
| 3915 | case Hexagon::A4_cround_ri: |
| 3916 | case Hexagon::A4_round_ri: |
| 3917 | case Hexagon::A4_round_ri_sat: |
| 3918 | case Hexagon::A7_clip: |
| 3919 | case Hexagon::S2_asl_i_r: |
| 3920 | case Hexagon::S2_asl_i_r_sat: |
| 3921 | case Hexagon::S2_asr_i_r: |
| 3922 | case Hexagon::S2_asr_i_r_rnd: |
| 3923 | case Hexagon::S2_clrbit_i: |
| 3924 | case Hexagon::S2_lsr_i_r: |
| 3925 | case Hexagon::S2_setbit_i: |
| 3926 | case Hexagon::S2_togglebit_i: |
| 3927 | case Hexagon::S6_rol_i_r: { |
| 3928 | // op: Ii |
| 3929 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3930 | Value |= (op & 0x1f) << 8; |
| 3931 | // op: Rs32 |
| 3932 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3933 | Value |= (op & 0x1f) << 16; |
| 3934 | // op: Rd32 |
| 3935 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3936 | Value |= (op & 0x1f); |
| 3937 | break; |
| 3938 | } |
| 3939 | case Hexagon::A4_bitspliti: { |
| 3940 | // op: Ii |
| 3941 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3942 | Value |= (op & 0x1f) << 8; |
| 3943 | // op: Rs32 |
| 3944 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3945 | Value |= (op & 0x1f) << 16; |
| 3946 | // op: Rdd32 |
| 3947 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3948 | Value |= (op & 0x1f); |
| 3949 | break; |
| 3950 | } |
| 3951 | case Hexagon::S2_asr_i_svw_trun: { |
| 3952 | // op: Ii |
| 3953 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3954 | Value |= (op & 0x1f) << 8; |
| 3955 | // op: Rss32 |
| 3956 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3957 | Value |= (op & 0x1f) << 16; |
| 3958 | // op: Rd32 |
| 3959 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3960 | Value |= (op & 0x1f); |
| 3961 | break; |
| 3962 | } |
| 3963 | case Hexagon::A7_vclip: |
| 3964 | case Hexagon::S2_asl_i_vw: |
| 3965 | case Hexagon::S2_asr_i_vw: |
| 3966 | case Hexagon::S2_lsr_i_vw: { |
| 3967 | // op: Ii |
| 3968 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3969 | Value |= (op & 0x1f) << 8; |
| 3970 | // op: Rss32 |
| 3971 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3972 | Value |= (op & 0x1f) << 16; |
| 3973 | // op: Rdd32 |
| 3974 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3975 | Value |= (op & 0x1f); |
| 3976 | break; |
| 3977 | } |
| 3978 | case Hexagon::C2_cmpgtui: |
| 3979 | case Hexagon::C4_cmplteui: { |
| 3980 | // op: Ii |
| 3981 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 3982 | Value |= (op & 0x1ff) << 5; |
| 3983 | // op: Rs32 |
| 3984 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 3985 | Value |= (op & 0x1f) << 16; |
| 3986 | // op: Pd4 |
| 3987 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 3988 | Value |= (op & 0x3); |
| 3989 | break; |
| 3990 | } |
| 3991 | case Hexagon::L4_loadbsw2_ur: |
| 3992 | case Hexagon::L4_loadbzw2_ur: |
| 3993 | case Hexagon::L4_loadrb_ur: |
| 3994 | case Hexagon::L4_loadrh_ur: |
| 3995 | case Hexagon::L4_loadri_ur: |
| 3996 | case Hexagon::L4_loadrub_ur: |
| 3997 | case Hexagon::L4_loadruh_ur: { |
| 3998 | // op: Ii |
| 3999 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4000 | Value |= (op & 0x2) << 12; |
| 4001 | Value |= (op & 0x1) << 7; |
| 4002 | // op: II |
| 4003 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 4004 | Value |= (op & 0x3c) << 6; |
| 4005 | Value |= (op & 0x3) << 5; |
| 4006 | // op: Rt32 |
| 4007 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4008 | Value |= (op & 0x1f) << 16; |
| 4009 | // op: Rd32 |
| 4010 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4011 | Value |= (op & 0x1f); |
| 4012 | break; |
| 4013 | } |
| 4014 | case Hexagon::L4_loadbsw4_ur: |
| 4015 | case Hexagon::L4_loadbzw4_ur: |
| 4016 | case Hexagon::L4_loadrd_ur: { |
| 4017 | // op: Ii |
| 4018 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4019 | Value |= (op & 0x2) << 12; |
| 4020 | Value |= (op & 0x1) << 7; |
| 4021 | // op: II |
| 4022 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 4023 | Value |= (op & 0x3c) << 6; |
| 4024 | Value |= (op & 0x3) << 5; |
| 4025 | // op: Rt32 |
| 4026 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4027 | Value |= (op & 0x1f) << 16; |
| 4028 | // op: Rdd32 |
| 4029 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4030 | Value |= (op & 0x1f); |
| 4031 | break; |
| 4032 | } |
| 4033 | case Hexagon::S4_storerbnew_rr: |
| 4034 | case Hexagon::S4_storerhnew_rr: |
| 4035 | case Hexagon::S4_storerinew_rr: { |
| 4036 | // op: Ii |
| 4037 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4038 | Value |= (op & 0x2) << 12; |
| 4039 | Value |= (op & 0x1) << 7; |
| 4040 | // op: Rs32 |
| 4041 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4042 | Value |= (op & 0x1f) << 16; |
| 4043 | // op: Ru32 |
| 4044 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4045 | Value |= (op & 0x1f) << 8; |
| 4046 | // op: Nt8 |
| 4047 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 4048 | Value |= (op & 0x7); |
| 4049 | break; |
| 4050 | } |
| 4051 | case Hexagon::S4_storerb_rr: |
| 4052 | case Hexagon::S4_storerf_rr: |
| 4053 | case Hexagon::S4_storerh_rr: |
| 4054 | case Hexagon::S4_storeri_rr: { |
| 4055 | // op: Ii |
| 4056 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4057 | Value |= (op & 0x2) << 12; |
| 4058 | Value |= (op & 0x1) << 7; |
| 4059 | // op: Rs32 |
| 4060 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4061 | Value |= (op & 0x1f) << 16; |
| 4062 | // op: Ru32 |
| 4063 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4064 | Value |= (op & 0x1f) << 8; |
| 4065 | // op: Rt32 |
| 4066 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 4067 | Value |= (op & 0x1f); |
| 4068 | break; |
| 4069 | } |
| 4070 | case Hexagon::S4_storerd_rr: { |
| 4071 | // op: Ii |
| 4072 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4073 | Value |= (op & 0x2) << 12; |
| 4074 | Value |= (op & 0x1) << 7; |
| 4075 | // op: Rs32 |
| 4076 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4077 | Value |= (op & 0x1f) << 16; |
| 4078 | // op: Ru32 |
| 4079 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4080 | Value |= (op & 0x1f) << 8; |
| 4081 | // op: Rtt32 |
| 4082 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 4083 | Value |= (op & 0x1f); |
| 4084 | break; |
| 4085 | } |
| 4086 | case Hexagon::S2_pstorerbnewf_io: |
| 4087 | case Hexagon::S2_pstorerbnewt_io: |
| 4088 | case Hexagon::S4_pstorerbnewfnew_io: |
| 4089 | case Hexagon::S4_pstorerbnewtnew_io: { |
| 4090 | // op: Ii |
| 4091 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4092 | Value |= (op & 0x20) << 8; |
| 4093 | Value |= (op & 0x1f) << 3; |
| 4094 | // op: Pv4 |
| 4095 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4096 | Value |= (op & 0x3); |
| 4097 | // op: Rs32 |
| 4098 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4099 | Value |= (op & 0x1f) << 16; |
| 4100 | // op: Nt8 |
| 4101 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 4102 | Value |= (op & 0x7) << 8; |
| 4103 | break; |
| 4104 | } |
| 4105 | case Hexagon::S2_pstorerbf_io: |
| 4106 | case Hexagon::S2_pstorerbt_io: |
| 4107 | case Hexagon::S4_pstorerbfnew_io: |
| 4108 | case Hexagon::S4_pstorerbtnew_io: { |
| 4109 | // op: Ii |
| 4110 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4111 | Value |= (op & 0x20) << 8; |
| 4112 | Value |= (op & 0x1f) << 3; |
| 4113 | // op: Pv4 |
| 4114 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4115 | Value |= (op & 0x3); |
| 4116 | // op: Rs32 |
| 4117 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4118 | Value |= (op & 0x1f) << 16; |
| 4119 | // op: Rt32 |
| 4120 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 4121 | Value |= (op & 0x1f) << 8; |
| 4122 | break; |
| 4123 | } |
| 4124 | case Hexagon::C2_cmpeqi: |
| 4125 | case Hexagon::C2_cmpgti: |
| 4126 | case Hexagon::C4_cmpltei: |
| 4127 | case Hexagon::C4_cmpneqi: { |
| 4128 | // op: Ii |
| 4129 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4130 | Value |= (op & 0x200) << 12; |
| 4131 | Value |= (op & 0x1ff) << 5; |
| 4132 | // op: Rs32 |
| 4133 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4134 | Value |= (op & 0x1f) << 16; |
| 4135 | // op: Pd4 |
| 4136 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4137 | Value |= (op & 0x3); |
| 4138 | break; |
| 4139 | } |
| 4140 | case Hexagon::A2_andir: |
| 4141 | case Hexagon::A2_orir: { |
| 4142 | // op: Ii |
| 4143 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4144 | Value |= (op & 0x200) << 12; |
| 4145 | Value |= (op & 0x1ff) << 5; |
| 4146 | // op: Rs32 |
| 4147 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4148 | Value |= (op & 0x1f) << 16; |
| 4149 | // op: Rd32 |
| 4150 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4151 | Value |= (op & 0x1f); |
| 4152 | break; |
| 4153 | } |
| 4154 | case Hexagon::S4_subaddi: { |
| 4155 | // op: Ii |
| 4156 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4157 | Value |= (op & 0x30) << 17; |
| 4158 | Value |= (op & 0x8) << 10; |
| 4159 | Value |= (op & 0x7) << 5; |
| 4160 | // op: Rs32 |
| 4161 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4162 | Value |= (op & 0x1f) << 16; |
| 4163 | // op: Ru32 |
| 4164 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 4165 | Value |= (op & 0x1f); |
| 4166 | // op: Rd32 |
| 4167 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4168 | Value |= (op & 0x1f) << 8; |
| 4169 | break; |
| 4170 | } |
| 4171 | case Hexagon::L2_loadrd_io: { |
| 4172 | // op: Ii |
| 4173 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4174 | Value |= (op & 0x3000) << 13; |
| 4175 | Value |= (op & 0xff8) << 2; |
| 4176 | // op: Rs32 |
| 4177 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4178 | Value |= (op & 0x1f) << 16; |
| 4179 | // op: Rdd32 |
| 4180 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4181 | Value |= (op & 0x1f); |
| 4182 | break; |
| 4183 | } |
| 4184 | case Hexagon::S2_storerinew_pci: { |
| 4185 | // op: Ii |
| 4186 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4187 | Value |= (op & 0x3c) << 1; |
| 4188 | // op: Mu2 |
| 4189 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 4190 | Value |= (op & 0x1) << 13; |
| 4191 | // op: Nt8 |
| 4192 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 4193 | Value |= (op & 0x7) << 8; |
| 4194 | // op: Rx32 |
| 4195 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4196 | Value |= (op & 0x1f) << 16; |
| 4197 | break; |
| 4198 | } |
| 4199 | case Hexagon::S2_storeri_pci: { |
| 4200 | // op: Ii |
| 4201 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4202 | Value |= (op & 0x3c) << 1; |
| 4203 | // op: Mu2 |
| 4204 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 4205 | Value |= (op & 0x1) << 13; |
| 4206 | // op: Rt32 |
| 4207 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 4208 | Value |= (op & 0x1f) << 8; |
| 4209 | // op: Rx32 |
| 4210 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4211 | Value |= (op & 0x1f) << 16; |
| 4212 | break; |
| 4213 | } |
| 4214 | case Hexagon::S2_storerinew_pi: { |
| 4215 | // op: Ii |
| 4216 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4217 | Value |= (op & 0x3c) << 1; |
| 4218 | // op: Nt8 |
| 4219 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 4220 | Value |= (op & 0x7) << 8; |
| 4221 | // op: Rx32 |
| 4222 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4223 | Value |= (op & 0x1f) << 16; |
| 4224 | break; |
| 4225 | } |
| 4226 | case Hexagon::S2_storeri_pi: { |
| 4227 | // op: Ii |
| 4228 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4229 | Value |= (op & 0x3c) << 1; |
| 4230 | // op: Rt32 |
| 4231 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 4232 | Value |= (op & 0x1f) << 8; |
| 4233 | // op: Rx32 |
| 4234 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4235 | Value |= (op & 0x1f) << 16; |
| 4236 | break; |
| 4237 | } |
| 4238 | case Hexagon::SL1_loadri_io: { |
| 4239 | // op: Ii |
| 4240 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4241 | Value |= (op & 0x3c) << 6; |
| 4242 | // op: Rs16 |
| 4243 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4244 | Value |= (op & 0xf) << 4; |
| 4245 | // op: Rd16 |
| 4246 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4247 | Value |= (op & 0xf); |
| 4248 | break; |
| 4249 | } |
| 4250 | case Hexagon::L4_ploadrbf_abs: |
| 4251 | case Hexagon::L4_ploadrbfnew_abs: |
| 4252 | case Hexagon::L4_ploadrbt_abs: |
| 4253 | case Hexagon::L4_ploadrbtnew_abs: |
| 4254 | case Hexagon::L4_ploadrhf_abs: |
| 4255 | case Hexagon::L4_ploadrhfnew_abs: |
| 4256 | case Hexagon::L4_ploadrht_abs: |
| 4257 | case Hexagon::L4_ploadrhtnew_abs: |
| 4258 | case Hexagon::L4_ploadrif_abs: |
| 4259 | case Hexagon::L4_ploadrifnew_abs: |
| 4260 | case Hexagon::L4_ploadrit_abs: |
| 4261 | case Hexagon::L4_ploadritnew_abs: |
| 4262 | case Hexagon::L4_ploadrubf_abs: |
| 4263 | case Hexagon::L4_ploadrubfnew_abs: |
| 4264 | case Hexagon::L4_ploadrubt_abs: |
| 4265 | case Hexagon::L4_ploadrubtnew_abs: |
| 4266 | case Hexagon::L4_ploadruhf_abs: |
| 4267 | case Hexagon::L4_ploadruhfnew_abs: |
| 4268 | case Hexagon::L4_ploadruht_abs: |
| 4269 | case Hexagon::L4_ploadruhtnew_abs: { |
| 4270 | // op: Ii |
| 4271 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4272 | Value |= (op & 0x3e) << 15; |
| 4273 | Value |= (op & 0x1) << 8; |
| 4274 | // op: Pt4 |
| 4275 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4276 | Value |= (op & 0x3) << 9; |
| 4277 | // op: Rd32 |
| 4278 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4279 | Value |= (op & 0x1f); |
| 4280 | break; |
| 4281 | } |
| 4282 | case Hexagon::L4_ploadrdf_abs: |
| 4283 | case Hexagon::L4_ploadrdfnew_abs: |
| 4284 | case Hexagon::L4_ploadrdt_abs: |
| 4285 | case Hexagon::L4_ploadrdtnew_abs: { |
| 4286 | // op: Ii |
| 4287 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4288 | Value |= (op & 0x3e) << 15; |
| 4289 | Value |= (op & 0x1) << 8; |
| 4290 | // op: Pt4 |
| 4291 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4292 | Value |= (op & 0x3) << 9; |
| 4293 | // op: Rdd32 |
| 4294 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4295 | Value |= (op & 0x1f); |
| 4296 | break; |
| 4297 | } |
| 4298 | case Hexagon::S4_storeirbf_io: |
| 4299 | case Hexagon::S4_storeirbfnew_io: |
| 4300 | case Hexagon::S4_storeirbt_io: |
| 4301 | case Hexagon::S4_storeirbtnew_io: { |
| 4302 | // op: Ii |
| 4303 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4304 | Value |= (op & 0x3f) << 7; |
| 4305 | // op: II |
| 4306 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 4307 | Value |= (op & 0x20) << 8; |
| 4308 | Value |= (op & 0x1f); |
| 4309 | // op: Pv4 |
| 4310 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4311 | Value |= (op & 0x3) << 5; |
| 4312 | // op: Rs32 |
| 4313 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4314 | Value |= (op & 0x1f) << 16; |
| 4315 | break; |
| 4316 | } |
| 4317 | case Hexagon::S2_extractup: |
| 4318 | case Hexagon::S4_extractp: { |
| 4319 | // op: Ii |
| 4320 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4321 | Value |= (op & 0x3f) << 8; |
| 4322 | // op: II |
| 4323 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 4324 | Value |= (op & 0x38) << 18; |
| 4325 | Value |= (op & 0x7) << 5; |
| 4326 | // op: Rss32 |
| 4327 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4328 | Value |= (op & 0x1f) << 16; |
| 4329 | // op: Rdd32 |
| 4330 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4331 | Value |= (op & 0x1f); |
| 4332 | break; |
| 4333 | } |
| 4334 | case Hexagon::C2_bitsclri: |
| 4335 | case Hexagon::C4_nbitsclri: { |
| 4336 | // op: Ii |
| 4337 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4338 | Value |= (op & 0x3f) << 8; |
| 4339 | // op: Rs32 |
| 4340 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4341 | Value |= (op & 0x1f) << 16; |
| 4342 | // op: Pd4 |
| 4343 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4344 | Value |= (op & 0x3); |
| 4345 | break; |
| 4346 | } |
| 4347 | case Hexagon::S4_clbaddi: { |
| 4348 | // op: Ii |
| 4349 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4350 | Value |= (op & 0x3f) << 8; |
| 4351 | // op: Rs32 |
| 4352 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4353 | Value |= (op & 0x1f) << 16; |
| 4354 | // op: Rd32 |
| 4355 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4356 | Value |= (op & 0x1f); |
| 4357 | break; |
| 4358 | } |
| 4359 | case Hexagon::S4_clbpaddi: { |
| 4360 | // op: Ii |
| 4361 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4362 | Value |= (op & 0x3f) << 8; |
| 4363 | // op: Rss32 |
| 4364 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4365 | Value |= (op & 0x1f) << 16; |
| 4366 | // op: Rd32 |
| 4367 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4368 | Value |= (op & 0x1f); |
| 4369 | break; |
| 4370 | } |
| 4371 | case Hexagon::A7_croundd_ri: |
| 4372 | case Hexagon::S2_asl_i_p: |
| 4373 | case Hexagon::S2_asr_i_p: |
| 4374 | case Hexagon::S2_asr_i_p_rnd: |
| 4375 | case Hexagon::S2_lsr_i_p: |
| 4376 | case Hexagon::S6_rol_i_p: { |
| 4377 | // op: Ii |
| 4378 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4379 | Value |= (op & 0x3f) << 8; |
| 4380 | // op: Rss32 |
| 4381 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4382 | Value |= (op & 0x1f) << 16; |
| 4383 | // op: Rdd32 |
| 4384 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4385 | Value |= (op & 0x1f); |
| 4386 | break; |
| 4387 | } |
| 4388 | case Hexagon::S2_allocframe: { |
| 4389 | // op: Ii |
| 4390 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4391 | Value |= (op & 0x3ff8) >> 3; |
| 4392 | // op: Rx32 |
| 4393 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4394 | Value |= (op & 0x1f) << 16; |
| 4395 | break; |
| 4396 | } |
| 4397 | case Hexagon::S2_pstorerhnewf_io: |
| 4398 | case Hexagon::S2_pstorerhnewt_io: |
| 4399 | case Hexagon::S4_pstorerhnewfnew_io: |
| 4400 | case Hexagon::S4_pstorerhnewtnew_io: { |
| 4401 | // op: Ii |
| 4402 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4403 | Value |= (op & 0x40) << 7; |
| 4404 | Value |= (op & 0x3e) << 2; |
| 4405 | // op: Pv4 |
| 4406 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4407 | Value |= (op & 0x3); |
| 4408 | // op: Rs32 |
| 4409 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4410 | Value |= (op & 0x1f) << 16; |
| 4411 | // op: Nt8 |
| 4412 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 4413 | Value |= (op & 0x7) << 8; |
| 4414 | break; |
| 4415 | } |
| 4416 | case Hexagon::S2_pstorerff_io: |
| 4417 | case Hexagon::S2_pstorerft_io: |
| 4418 | case Hexagon::S2_pstorerhf_io: |
| 4419 | case Hexagon::S2_pstorerht_io: |
| 4420 | case Hexagon::S4_pstorerffnew_io: |
| 4421 | case Hexagon::S4_pstorerftnew_io: |
| 4422 | case Hexagon::S4_pstorerhfnew_io: |
| 4423 | case Hexagon::S4_pstorerhtnew_io: { |
| 4424 | // op: Ii |
| 4425 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4426 | Value |= (op & 0x40) << 7; |
| 4427 | Value |= (op & 0x3e) << 2; |
| 4428 | // op: Pv4 |
| 4429 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4430 | Value |= (op & 0x3); |
| 4431 | // op: Rs32 |
| 4432 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4433 | Value |= (op & 0x1f) << 16; |
| 4434 | // op: Rt32 |
| 4435 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 4436 | Value |= (op & 0x1f) << 8; |
| 4437 | break; |
| 4438 | } |
| 4439 | case Hexagon::J4_cmpeqn1_f_jumpnv_nt: |
| 4440 | case Hexagon::J4_cmpeqn1_f_jumpnv_t: |
| 4441 | case Hexagon::J4_cmpeqn1_t_jumpnv_nt: |
| 4442 | case Hexagon::J4_cmpeqn1_t_jumpnv_t: |
| 4443 | case Hexagon::J4_cmpgtn1_f_jumpnv_nt: |
| 4444 | case Hexagon::J4_cmpgtn1_f_jumpnv_t: |
| 4445 | case Hexagon::J4_cmpgtn1_t_jumpnv_nt: |
| 4446 | case Hexagon::J4_cmpgtn1_t_jumpnv_t: { |
| 4447 | // op: Ii |
| 4448 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4449 | Value |= (op & 0x600) << 11; |
| 4450 | Value |= (op & 0x1fc) >> 1; |
| 4451 | // op: Ns8 |
| 4452 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4453 | Value |= (op & 0x7) << 16; |
| 4454 | break; |
| 4455 | } |
| 4456 | case Hexagon::J4_cmpeq_f_jumpnv_nt: |
| 4457 | case Hexagon::J4_cmpeq_f_jumpnv_t: |
| 4458 | case Hexagon::J4_cmpeq_t_jumpnv_nt: |
| 4459 | case Hexagon::J4_cmpeq_t_jumpnv_t: |
| 4460 | case Hexagon::J4_cmpgt_f_jumpnv_nt: |
| 4461 | case Hexagon::J4_cmpgt_f_jumpnv_t: |
| 4462 | case Hexagon::J4_cmpgt_t_jumpnv_nt: |
| 4463 | case Hexagon::J4_cmpgt_t_jumpnv_t: |
| 4464 | case Hexagon::J4_cmpgtu_f_jumpnv_nt: |
| 4465 | case Hexagon::J4_cmpgtu_f_jumpnv_t: |
| 4466 | case Hexagon::J4_cmpgtu_t_jumpnv_nt: |
| 4467 | case Hexagon::J4_cmpgtu_t_jumpnv_t: { |
| 4468 | // op: Ii |
| 4469 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4470 | Value |= (op & 0x600) << 11; |
| 4471 | Value |= (op & 0x1fc) >> 1; |
| 4472 | // op: Ns8 |
| 4473 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4474 | Value |= (op & 0x7) << 16; |
| 4475 | // op: Rt32 |
| 4476 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4477 | Value |= (op & 0x1f) << 8; |
| 4478 | break; |
| 4479 | } |
| 4480 | case Hexagon::J4_cmpeqn1_fp0_jump_nt: |
| 4481 | case Hexagon::J4_cmpeqn1_fp0_jump_t: |
| 4482 | case Hexagon::J4_cmpeqn1_fp1_jump_nt: |
| 4483 | case Hexagon::J4_cmpeqn1_fp1_jump_t: |
| 4484 | case Hexagon::J4_cmpeqn1_tp0_jump_nt: |
| 4485 | case Hexagon::J4_cmpeqn1_tp0_jump_t: |
| 4486 | case Hexagon::J4_cmpeqn1_tp1_jump_nt: |
| 4487 | case Hexagon::J4_cmpeqn1_tp1_jump_t: |
| 4488 | case Hexagon::J4_cmpgtn1_fp0_jump_nt: |
| 4489 | case Hexagon::J4_cmpgtn1_fp0_jump_t: |
| 4490 | case Hexagon::J4_cmpgtn1_fp1_jump_nt: |
| 4491 | case Hexagon::J4_cmpgtn1_fp1_jump_t: |
| 4492 | case Hexagon::J4_cmpgtn1_tp0_jump_nt: |
| 4493 | case Hexagon::J4_cmpgtn1_tp0_jump_t: |
| 4494 | case Hexagon::J4_cmpgtn1_tp1_jump_nt: |
| 4495 | case Hexagon::J4_cmpgtn1_tp1_jump_t: { |
| 4496 | // op: Ii |
| 4497 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4498 | Value |= (op & 0x600) << 11; |
| 4499 | Value |= (op & 0x1fc) >> 1; |
| 4500 | // op: Rs16 |
| 4501 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4502 | Value |= (op & 0xf) << 16; |
| 4503 | break; |
| 4504 | } |
| 4505 | case Hexagon::J4_cmpeq_fp0_jump_nt: |
| 4506 | case Hexagon::J4_cmpeq_fp0_jump_t: |
| 4507 | case Hexagon::J4_cmpeq_fp1_jump_nt: |
| 4508 | case Hexagon::J4_cmpeq_fp1_jump_t: |
| 4509 | case Hexagon::J4_cmpeq_tp0_jump_nt: |
| 4510 | case Hexagon::J4_cmpeq_tp0_jump_t: |
| 4511 | case Hexagon::J4_cmpeq_tp1_jump_nt: |
| 4512 | case Hexagon::J4_cmpeq_tp1_jump_t: |
| 4513 | case Hexagon::J4_cmpgt_fp0_jump_nt: |
| 4514 | case Hexagon::J4_cmpgt_fp0_jump_t: |
| 4515 | case Hexagon::J4_cmpgt_fp1_jump_nt: |
| 4516 | case Hexagon::J4_cmpgt_fp1_jump_t: |
| 4517 | case Hexagon::J4_cmpgt_tp0_jump_nt: |
| 4518 | case Hexagon::J4_cmpgt_tp0_jump_t: |
| 4519 | case Hexagon::J4_cmpgt_tp1_jump_nt: |
| 4520 | case Hexagon::J4_cmpgt_tp1_jump_t: |
| 4521 | case Hexagon::J4_cmpgtu_fp0_jump_nt: |
| 4522 | case Hexagon::J4_cmpgtu_fp0_jump_t: |
| 4523 | case Hexagon::J4_cmpgtu_fp1_jump_nt: |
| 4524 | case Hexagon::J4_cmpgtu_fp1_jump_t: |
| 4525 | case Hexagon::J4_cmpgtu_tp0_jump_nt: |
| 4526 | case Hexagon::J4_cmpgtu_tp0_jump_t: |
| 4527 | case Hexagon::J4_cmpgtu_tp1_jump_nt: |
| 4528 | case Hexagon::J4_cmpgtu_tp1_jump_t: { |
| 4529 | // op: Ii |
| 4530 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4531 | Value |= (op & 0x600) << 11; |
| 4532 | Value |= (op & 0x1fc) >> 1; |
| 4533 | // op: Rs16 |
| 4534 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4535 | Value |= (op & 0xf) << 16; |
| 4536 | // op: Rt16 |
| 4537 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4538 | Value |= (op & 0xf) << 8; |
| 4539 | break; |
| 4540 | } |
| 4541 | case Hexagon::J4_jumpsetr: { |
| 4542 | // op: Ii |
| 4543 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4544 | Value |= (op & 0x600) << 11; |
| 4545 | Value |= (op & 0x1fc) >> 1; |
| 4546 | // op: Rs16 |
| 4547 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4548 | Value |= (op & 0xf) << 16; |
| 4549 | // op: Rd16 |
| 4550 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4551 | Value |= (op & 0xf) << 8; |
| 4552 | break; |
| 4553 | } |
| 4554 | case Hexagon::J4_cmplt_f_jumpnv_nt: |
| 4555 | case Hexagon::J4_cmplt_f_jumpnv_t: |
| 4556 | case Hexagon::J4_cmplt_t_jumpnv_nt: |
| 4557 | case Hexagon::J4_cmplt_t_jumpnv_t: |
| 4558 | case Hexagon::J4_cmpltu_f_jumpnv_nt: |
| 4559 | case Hexagon::J4_cmpltu_f_jumpnv_t: |
| 4560 | case Hexagon::J4_cmpltu_t_jumpnv_nt: |
| 4561 | case Hexagon::J4_cmpltu_t_jumpnv_t: { |
| 4562 | // op: Ii |
| 4563 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4564 | Value |= (op & 0x600) << 11; |
| 4565 | Value |= (op & 0x1fc) >> 1; |
| 4566 | // op: Rt32 |
| 4567 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4568 | Value |= (op & 0x1f) << 8; |
| 4569 | // op: Ns8 |
| 4570 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4571 | Value |= (op & 0x7) << 16; |
| 4572 | break; |
| 4573 | } |
| 4574 | case Hexagon::L2_loadrb_io: |
| 4575 | case Hexagon::L2_loadrub_io: { |
| 4576 | // op: Ii |
| 4577 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4578 | Value |= (op & 0x600) << 16; |
| 4579 | Value |= (op & 0x1ff) << 5; |
| 4580 | // op: Rs32 |
| 4581 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4582 | Value |= (op & 0x1f) << 16; |
| 4583 | // op: Rd32 |
| 4584 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4585 | Value |= (op & 0x1f); |
| 4586 | break; |
| 4587 | } |
| 4588 | case Hexagon::V6_vS32b_new_pi: |
| 4589 | case Hexagon::V6_vS32b_nt_new_pi: { |
| 4590 | // op: Ii |
| 4591 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4592 | Value |= (op & 0x7) << 8; |
| 4593 | // op: Os8 |
| 4594 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 4595 | Value |= (op & 0x7); |
| 4596 | // op: Rx32 |
| 4597 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4598 | Value |= (op & 0x1f) << 16; |
| 4599 | break; |
| 4600 | } |
| 4601 | case Hexagon::SL2_loadrb_io: { |
| 4602 | // op: Ii |
| 4603 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4604 | Value |= (op & 0x7) << 8; |
| 4605 | // op: Rs16 |
| 4606 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4607 | Value |= (op & 0xf) << 4; |
| 4608 | // op: Rd16 |
| 4609 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4610 | Value |= (op & 0xf); |
| 4611 | break; |
| 4612 | } |
| 4613 | case Hexagon::V6_vS32b_srls_pi: |
| 4614 | case Hexagon::V6_zLd_pi: { |
| 4615 | // op: Ii |
| 4616 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4617 | Value |= (op & 0x7) << 8; |
| 4618 | // op: Rx32 |
| 4619 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4620 | Value |= (op & 0x1f) << 16; |
| 4621 | break; |
| 4622 | } |
| 4623 | case Hexagon::V6_vS32Ub_pi: |
| 4624 | case Hexagon::V6_vS32b_nt_pi: |
| 4625 | case Hexagon::V6_vS32b_pi: { |
| 4626 | // op: Ii |
| 4627 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4628 | Value |= (op & 0x7) << 8; |
| 4629 | // op: Vs32 |
| 4630 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 4631 | Value |= (op & 0x1f); |
| 4632 | // op: Rx32 |
| 4633 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4634 | Value |= (op & 0x1f) << 16; |
| 4635 | break; |
| 4636 | } |
| 4637 | case Hexagon::S2_storerd_pci: { |
| 4638 | // op: Ii |
| 4639 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4640 | Value |= (op & 0x78); |
| 4641 | // op: Mu2 |
| 4642 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 4643 | Value |= (op & 0x1) << 13; |
| 4644 | // op: Rtt32 |
| 4645 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 4646 | Value |= (op & 0x1f) << 8; |
| 4647 | // op: Rx32 |
| 4648 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4649 | Value |= (op & 0x1f) << 16; |
| 4650 | break; |
| 4651 | } |
| 4652 | case Hexagon::S2_storerd_pi: { |
| 4653 | // op: Ii |
| 4654 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4655 | Value |= (op & 0x78); |
| 4656 | // op: Rtt32 |
| 4657 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 4658 | Value |= (op & 0x1f) << 8; |
| 4659 | // op: Rx32 |
| 4660 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4661 | Value |= (op & 0x1f) << 16; |
| 4662 | break; |
| 4663 | } |
| 4664 | case Hexagon::S4_storeirhf_io: |
| 4665 | case Hexagon::S4_storeirhfnew_io: |
| 4666 | case Hexagon::S4_storeirht_io: |
| 4667 | case Hexagon::S4_storeirhtnew_io: { |
| 4668 | // op: Ii |
| 4669 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4670 | Value |= (op & 0x7e) << 6; |
| 4671 | // op: II |
| 4672 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 4673 | Value |= (op & 0x20) << 8; |
| 4674 | Value |= (op & 0x1f); |
| 4675 | // op: Pv4 |
| 4676 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4677 | Value |= (op & 0x3) << 5; |
| 4678 | // op: Rs32 |
| 4679 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4680 | Value |= (op & 0x1f) << 16; |
| 4681 | break; |
| 4682 | } |
| 4683 | case Hexagon::SA1_addi: { |
| 4684 | // op: Ii |
| 4685 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4686 | Value |= (op & 0x7f) << 4; |
| 4687 | // op: Rx16 |
| 4688 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4689 | Value |= (op & 0xf); |
| 4690 | break; |
| 4691 | } |
| 4692 | case Hexagon::A4_cmpbgtui: |
| 4693 | case Hexagon::A4_cmphgtui: { |
| 4694 | // op: Ii |
| 4695 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4696 | Value |= (op & 0x7f) << 5; |
| 4697 | // op: Rs32 |
| 4698 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4699 | Value |= (op & 0x1f) << 16; |
| 4700 | // op: Pd4 |
| 4701 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4702 | Value |= (op & 0x3); |
| 4703 | break; |
| 4704 | } |
| 4705 | case Hexagon::A4_vcmpbgtui: |
| 4706 | case Hexagon::A4_vcmphgtui: |
| 4707 | case Hexagon::A4_vcmpwgtui: { |
| 4708 | // op: Ii |
| 4709 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4710 | Value |= (op & 0x7f) << 5; |
| 4711 | // op: Rss32 |
| 4712 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4713 | Value |= (op & 0x1f) << 16; |
| 4714 | // op: Pd4 |
| 4715 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4716 | Value |= (op & 0x3); |
| 4717 | break; |
| 4718 | } |
| 4719 | case Hexagon::V6_zLd_pred_ai: { |
| 4720 | // op: Ii |
| 4721 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4722 | Value |= (op & 0x8) << 10; |
| 4723 | Value |= (op & 0x7) << 8; |
| 4724 | // op: Pv4 |
| 4725 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4726 | Value |= (op & 0x3) << 11; |
| 4727 | // op: Rt32 |
| 4728 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4729 | Value |= (op & 0x1f) << 16; |
| 4730 | break; |
| 4731 | } |
| 4732 | case Hexagon::V6_vS32b_new_npred_ai: |
| 4733 | case Hexagon::V6_vS32b_new_pred_ai: |
| 4734 | case Hexagon::V6_vS32b_nt_new_npred_ai: |
| 4735 | case Hexagon::V6_vS32b_nt_new_pred_ai: { |
| 4736 | // op: Ii |
| 4737 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4738 | Value |= (op & 0x8) << 10; |
| 4739 | Value |= (op & 0x7) << 8; |
| 4740 | // op: Pv4 |
| 4741 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4742 | Value |= (op & 0x3) << 11; |
| 4743 | // op: Rt32 |
| 4744 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4745 | Value |= (op & 0x1f) << 16; |
| 4746 | // op: Os8 |
| 4747 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 4748 | Value |= (op & 0x7); |
| 4749 | break; |
| 4750 | } |
| 4751 | case Hexagon::V6_vS32Ub_npred_ai: |
| 4752 | case Hexagon::V6_vS32Ub_pred_ai: |
| 4753 | case Hexagon::V6_vS32b_npred_ai: |
| 4754 | case Hexagon::V6_vS32b_nt_npred_ai: |
| 4755 | case Hexagon::V6_vS32b_nt_pred_ai: |
| 4756 | case Hexagon::V6_vS32b_pred_ai: { |
| 4757 | // op: Ii |
| 4758 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4759 | Value |= (op & 0x8) << 10; |
| 4760 | Value |= (op & 0x7) << 8; |
| 4761 | // op: Pv4 |
| 4762 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4763 | Value |= (op & 0x3) << 11; |
| 4764 | // op: Rt32 |
| 4765 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4766 | Value |= (op & 0x1f) << 16; |
| 4767 | // op: Vs32 |
| 4768 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 4769 | Value |= (op & 0x1f); |
| 4770 | break; |
| 4771 | } |
| 4772 | case Hexagon::V6_vS32b_nqpred_ai: |
| 4773 | case Hexagon::V6_vS32b_nt_nqpred_ai: |
| 4774 | case Hexagon::V6_vS32b_nt_qpred_ai: |
| 4775 | case Hexagon::V6_vS32b_qpred_ai: { |
| 4776 | // op: Ii |
| 4777 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4778 | Value |= (op & 0x8) << 10; |
| 4779 | Value |= (op & 0x7) << 8; |
| 4780 | // op: Qv4 |
| 4781 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4782 | Value |= (op & 0x3) << 11; |
| 4783 | // op: Rt32 |
| 4784 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4785 | Value |= (op & 0x1f) << 16; |
| 4786 | // op: Vs32 |
| 4787 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 4788 | Value |= (op & 0x1f); |
| 4789 | break; |
| 4790 | } |
| 4791 | case Hexagon::V6_vL32Ub_ai: |
| 4792 | case Hexagon::V6_vL32b_ai: |
| 4793 | case Hexagon::V6_vL32b_cur_ai: |
| 4794 | case Hexagon::V6_vL32b_nt_ai: |
| 4795 | case Hexagon::V6_vL32b_nt_cur_ai: |
| 4796 | case Hexagon::V6_vL32b_nt_tmp_ai: |
| 4797 | case Hexagon::V6_vL32b_tmp_ai: { |
| 4798 | // op: Ii |
| 4799 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4800 | Value |= (op & 0x8) << 10; |
| 4801 | Value |= (op & 0x7) << 8; |
| 4802 | // op: Rt32 |
| 4803 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4804 | Value |= (op & 0x1f) << 16; |
| 4805 | // op: Vd32 |
| 4806 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4807 | Value |= (op & 0x1f); |
| 4808 | break; |
| 4809 | } |
| 4810 | case Hexagon::S2_pstorerinewf_io: |
| 4811 | case Hexagon::S2_pstorerinewt_io: |
| 4812 | case Hexagon::S4_pstorerinewfnew_io: |
| 4813 | case Hexagon::S4_pstorerinewtnew_io: { |
| 4814 | // op: Ii |
| 4815 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4816 | Value |= (op & 0x80) << 6; |
| 4817 | Value |= (op & 0x7c) << 1; |
| 4818 | // op: Pv4 |
| 4819 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4820 | Value |= (op & 0x3); |
| 4821 | // op: Rs32 |
| 4822 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4823 | Value |= (op & 0x1f) << 16; |
| 4824 | // op: Nt8 |
| 4825 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 4826 | Value |= (op & 0x7) << 8; |
| 4827 | break; |
| 4828 | } |
| 4829 | case Hexagon::S2_pstorerif_io: |
| 4830 | case Hexagon::S2_pstorerit_io: |
| 4831 | case Hexagon::S4_pstorerifnew_io: |
| 4832 | case Hexagon::S4_pstoreritnew_io: { |
| 4833 | // op: Ii |
| 4834 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4835 | Value |= (op & 0x80) << 6; |
| 4836 | Value |= (op & 0x7c) << 1; |
| 4837 | // op: Pv4 |
| 4838 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4839 | Value |= (op & 0x3); |
| 4840 | // op: Rs32 |
| 4841 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4842 | Value |= (op & 0x1f) << 16; |
| 4843 | // op: Rt32 |
| 4844 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 4845 | Value |= (op & 0x1f) << 8; |
| 4846 | break; |
| 4847 | } |
| 4848 | case Hexagon::M4_mpyri_addr_u2: { |
| 4849 | // op: Ii |
| 4850 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4851 | Value |= (op & 0xc0) << 15; |
| 4852 | Value |= (op & 0x20) << 8; |
| 4853 | Value |= (op & 0x1c) << 3; |
| 4854 | // op: Ru32 |
| 4855 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4856 | Value |= (op & 0x1f); |
| 4857 | // op: Rs32 |
| 4858 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 4859 | Value |= (op & 0x1f) << 16; |
| 4860 | // op: Rd32 |
| 4861 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4862 | Value |= (op & 0x1f) << 8; |
| 4863 | break; |
| 4864 | } |
| 4865 | case Hexagon::L2_loadbsw2_io: |
| 4866 | case Hexagon::L2_loadbzw2_io: |
| 4867 | case Hexagon::L2_loadrh_io: |
| 4868 | case Hexagon::L2_loadruh_io: { |
| 4869 | // op: Ii |
| 4870 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4871 | Value |= (op & 0xc00) << 15; |
| 4872 | Value |= (op & 0x3fe) << 4; |
| 4873 | // op: Rs32 |
| 4874 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4875 | Value |= (op & 0x1f) << 16; |
| 4876 | // op: Rd32 |
| 4877 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4878 | Value |= (op & 0x1f); |
| 4879 | break; |
| 4880 | } |
| 4881 | case Hexagon::A2_tfrih: |
| 4882 | case Hexagon::A2_tfril: { |
| 4883 | // op: Ii |
| 4884 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4885 | Value |= (op & 0xc000) << 8; |
| 4886 | Value |= (op & 0x3fff); |
| 4887 | // op: Rx32 |
| 4888 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4889 | Value |= (op & 0x1f) << 16; |
| 4890 | break; |
| 4891 | } |
| 4892 | case Hexagon::SL2_loadrh_io: |
| 4893 | case Hexagon::SL2_loadruh_io: { |
| 4894 | // op: Ii |
| 4895 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4896 | Value |= (op & 0xe) << 7; |
| 4897 | // op: Rs16 |
| 4898 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4899 | Value |= (op & 0xf) << 4; |
| 4900 | // op: Rd16 |
| 4901 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4902 | Value |= (op & 0xf); |
| 4903 | break; |
| 4904 | } |
| 4905 | case Hexagon::S2_storerbnew_pci: { |
| 4906 | // op: Ii |
| 4907 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4908 | Value |= (op & 0xf) << 3; |
| 4909 | // op: Mu2 |
| 4910 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 4911 | Value |= (op & 0x1) << 13; |
| 4912 | // op: Nt8 |
| 4913 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 4914 | Value |= (op & 0x7) << 8; |
| 4915 | // op: Rx32 |
| 4916 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4917 | Value |= (op & 0x1f) << 16; |
| 4918 | break; |
| 4919 | } |
| 4920 | case Hexagon::S2_storerb_pci: { |
| 4921 | // op: Ii |
| 4922 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4923 | Value |= (op & 0xf) << 3; |
| 4924 | // op: Mu2 |
| 4925 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 4926 | Value |= (op & 0x1) << 13; |
| 4927 | // op: Rt32 |
| 4928 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 4929 | Value |= (op & 0x1f) << 8; |
| 4930 | // op: Rx32 |
| 4931 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4932 | Value |= (op & 0x1f) << 16; |
| 4933 | break; |
| 4934 | } |
| 4935 | case Hexagon::S2_storerbnew_pi: { |
| 4936 | // op: Ii |
| 4937 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4938 | Value |= (op & 0xf) << 3; |
| 4939 | // op: Nt8 |
| 4940 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 4941 | Value |= (op & 0x7) << 8; |
| 4942 | // op: Rx32 |
| 4943 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4944 | Value |= (op & 0x1f) << 16; |
| 4945 | break; |
| 4946 | } |
| 4947 | case Hexagon::S2_storerb_pi: { |
| 4948 | // op: Ii |
| 4949 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4950 | Value |= (op & 0xf) << 3; |
| 4951 | // op: Rt32 |
| 4952 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 4953 | Value |= (op & 0x1f) << 8; |
| 4954 | // op: Rx32 |
| 4955 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4956 | Value |= (op & 0x1f) << 16; |
| 4957 | break; |
| 4958 | } |
| 4959 | case Hexagon::SL1_loadrub_io: { |
| 4960 | // op: Ii |
| 4961 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4962 | Value |= (op & 0xf) << 8; |
| 4963 | // op: Rs16 |
| 4964 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4965 | Value |= (op & 0xf) << 4; |
| 4966 | // op: Rd16 |
| 4967 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4968 | Value |= (op & 0xf); |
| 4969 | break; |
| 4970 | } |
| 4971 | case Hexagon::S5_asrhub_rnd_sat: |
| 4972 | case Hexagon::S5_asrhub_sat: { |
| 4973 | // op: Ii |
| 4974 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4975 | Value |= (op & 0xf) << 8; |
| 4976 | // op: Rss32 |
| 4977 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4978 | Value |= (op & 0x1f) << 16; |
| 4979 | // op: Rd32 |
| 4980 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4981 | Value |= (op & 0x1f); |
| 4982 | break; |
| 4983 | } |
| 4984 | case Hexagon::S2_asl_i_vh: |
| 4985 | case Hexagon::S2_asr_i_vh: |
| 4986 | case Hexagon::S2_lsr_i_vh: |
| 4987 | case Hexagon::S5_vasrhrnd: { |
| 4988 | // op: Ii |
| 4989 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 4990 | Value |= (op & 0xf) << 8; |
| 4991 | // op: Rss32 |
| 4992 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 4993 | Value |= (op & 0x1f) << 16; |
| 4994 | // op: Rdd32 |
| 4995 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 4996 | Value |= (op & 0x1f); |
| 4997 | break; |
| 4998 | } |
| 4999 | case Hexagon::C2_cmoveif: |
| 5000 | case Hexagon::C2_cmoveit: |
| 5001 | case Hexagon::C2_cmovenewif: |
| 5002 | case Hexagon::C2_cmovenewit: { |
| 5003 | // op: Ii |
| 5004 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 5005 | Value |= (op & 0xf00) << 8; |
| 5006 | Value |= (op & 0xff) << 5; |
| 5007 | // op: Pu4 |
| 5008 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5009 | Value |= (op & 0x3) << 21; |
| 5010 | // op: Rd32 |
| 5011 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5012 | Value |= (op & 0x1f); |
| 5013 | break; |
| 5014 | } |
| 5015 | case Hexagon::J2_trap1: { |
| 5016 | // op: Ii |
| 5017 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 5018 | Value |= (op & 0xf8) << 5; |
| 5019 | Value |= (op & 0x7) << 2; |
| 5020 | // op: Rx32 |
| 5021 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5022 | Value |= (op & 0x1f) << 16; |
| 5023 | break; |
| 5024 | } |
| 5025 | case Hexagon::S4_storeirif_io: |
| 5026 | case Hexagon::S4_storeirifnew_io: |
| 5027 | case Hexagon::S4_storeirit_io: |
| 5028 | case Hexagon::S4_storeiritnew_io: { |
| 5029 | // op: Ii |
| 5030 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 5031 | Value |= (op & 0xfc) << 5; |
| 5032 | // op: II |
| 5033 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 5034 | Value |= (op & 0x20) << 8; |
| 5035 | Value |= (op & 0x1f); |
| 5036 | // op: Pv4 |
| 5037 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5038 | Value |= (op & 0x3) << 5; |
| 5039 | // op: Rs32 |
| 5040 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5041 | Value |= (op & 0x1f) << 16; |
| 5042 | break; |
| 5043 | } |
| 5044 | case Hexagon::A2_addi: { |
| 5045 | // op: Ii |
| 5046 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 5047 | Value |= (op & 0xfe00) << 12; |
| 5048 | Value |= (op & 0x1ff) << 5; |
| 5049 | // op: Rs32 |
| 5050 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5051 | Value |= (op & 0x1f) << 16; |
| 5052 | // op: Rd32 |
| 5053 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5054 | Value |= (op & 0x1f); |
| 5055 | break; |
| 5056 | } |
| 5057 | case Hexagon::C2_muxii: { |
| 5058 | // op: Ii |
| 5059 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 5060 | Value |= (op & 0xff) << 5; |
| 5061 | // op: II |
| 5062 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 5063 | Value |= (op & 0xfe) << 15; |
| 5064 | Value |= (op & 0x1) << 13; |
| 5065 | // op: Pu4 |
| 5066 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5067 | Value |= (op & 0x3) << 23; |
| 5068 | // op: Rd32 |
| 5069 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5070 | Value |= (op & 0x1f); |
| 5071 | break; |
| 5072 | } |
| 5073 | case Hexagon::C2_muxri: { |
| 5074 | // op: Ii |
| 5075 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 5076 | Value |= (op & 0xff) << 5; |
| 5077 | // op: Pu4 |
| 5078 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5079 | Value |= (op & 0x3) << 21; |
| 5080 | // op: Rs32 |
| 5081 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 5082 | Value |= (op & 0x1f) << 16; |
| 5083 | // op: Rd32 |
| 5084 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5085 | Value |= (op & 0x1f); |
| 5086 | break; |
| 5087 | } |
| 5088 | case Hexagon::A4_cmpbeqi: |
| 5089 | case Hexagon::A4_cmpbgti: |
| 5090 | case Hexagon::A4_cmpheqi: |
| 5091 | case Hexagon::A4_cmphgti: { |
| 5092 | // op: Ii |
| 5093 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 5094 | Value |= (op & 0xff) << 5; |
| 5095 | // op: Rs32 |
| 5096 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5097 | Value |= (op & 0x1f) << 16; |
| 5098 | // op: Pd4 |
| 5099 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5100 | Value |= (op & 0x3); |
| 5101 | break; |
| 5102 | } |
| 5103 | case Hexagon::A4_rcmpeqi: |
| 5104 | case Hexagon::A4_rcmpneqi: |
| 5105 | case Hexagon::M2_mpysin: |
| 5106 | case Hexagon::M2_mpysip: { |
| 5107 | // op: Ii |
| 5108 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 5109 | Value |= (op & 0xff) << 5; |
| 5110 | // op: Rs32 |
| 5111 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5112 | Value |= (op & 0x1f) << 16; |
| 5113 | // op: Rd32 |
| 5114 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5115 | Value |= (op & 0x1f); |
| 5116 | break; |
| 5117 | } |
| 5118 | case Hexagon::A4_combineri: { |
| 5119 | // op: Ii |
| 5120 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 5121 | Value |= (op & 0xff) << 5; |
| 5122 | // op: Rs32 |
| 5123 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5124 | Value |= (op & 0x1f) << 16; |
| 5125 | // op: Rdd32 |
| 5126 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5127 | Value |= (op & 0x1f); |
| 5128 | break; |
| 5129 | } |
| 5130 | case Hexagon::A4_vcmpbeqi: |
| 5131 | case Hexagon::A4_vcmpbgti: |
| 5132 | case Hexagon::A4_vcmpheqi: |
| 5133 | case Hexagon::A4_vcmphgti: |
| 5134 | case Hexagon::A4_vcmpweqi: |
| 5135 | case Hexagon::A4_vcmpwgti: { |
| 5136 | // op: Ii |
| 5137 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 5138 | Value |= (op & 0xff) << 5; |
| 5139 | // op: Rss32 |
| 5140 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5141 | Value |= (op & 0x1f) << 16; |
| 5142 | // op: Pd4 |
| 5143 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5144 | Value |= (op & 0x3); |
| 5145 | break; |
| 5146 | } |
| 5147 | case Hexagon::V6_vrmpybusi: |
| 5148 | case Hexagon::V6_vrmpyubi: |
| 5149 | case Hexagon::V6_vrsadubi: { |
| 5150 | // op: Ii |
| 5151 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 5152 | Value |= (op & 0x1) << 5; |
| 5153 | // op: Vuu32 |
| 5154 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5155 | Value |= (op & 0x1f) << 8; |
| 5156 | // op: Rt32 |
| 5157 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 5158 | Value |= (op & 0x1f) << 16; |
| 5159 | // op: Vdd32 |
| 5160 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5161 | Value |= (op & 0x1f); |
| 5162 | break; |
| 5163 | } |
| 5164 | case Hexagon::S2_pstorerhnewf_pi: |
| 5165 | case Hexagon::S2_pstorerhnewfnew_pi: |
| 5166 | case Hexagon::S2_pstorerhnewt_pi: |
| 5167 | case Hexagon::S2_pstorerhnewtnew_pi: { |
| 5168 | // op: Ii |
| 5169 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 5170 | Value |= (op & 0x1e) << 2; |
| 5171 | // op: Pv4 |
| 5172 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5173 | Value |= (op & 0x3); |
| 5174 | // op: Nt8 |
| 5175 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 5176 | Value |= (op & 0x7) << 8; |
| 5177 | // op: Rx32 |
| 5178 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5179 | Value |= (op & 0x1f) << 16; |
| 5180 | break; |
| 5181 | } |
| 5182 | case Hexagon::S2_pstorerff_pi: |
| 5183 | case Hexagon::S2_pstorerffnew_pi: |
| 5184 | case Hexagon::S2_pstorerft_pi: |
| 5185 | case Hexagon::S2_pstorerftnew_pi: |
| 5186 | case Hexagon::S2_pstorerhf_pi: |
| 5187 | case Hexagon::S2_pstorerhfnew_pi: |
| 5188 | case Hexagon::S2_pstorerht_pi: |
| 5189 | case Hexagon::S2_pstorerhtnew_pi: { |
| 5190 | // op: Ii |
| 5191 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 5192 | Value |= (op & 0x1e) << 2; |
| 5193 | // op: Pv4 |
| 5194 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5195 | Value |= (op & 0x3); |
| 5196 | // op: Rt32 |
| 5197 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 5198 | Value |= (op & 0x1f) << 8; |
| 5199 | // op: Rx32 |
| 5200 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5201 | Value |= (op & 0x1f) << 16; |
| 5202 | break; |
| 5203 | } |
| 5204 | case Hexagon::L2_loadbsw2_pci: |
| 5205 | case Hexagon::L2_loadbzw2_pci: |
| 5206 | case Hexagon::L2_loadrh_pci: |
| 5207 | case Hexagon::L2_loadruh_pci: { |
| 5208 | // op: Ii |
| 5209 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 5210 | Value |= (op & 0x1e) << 4; |
| 5211 | // op: Mu2 |
| 5212 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 5213 | Value |= (op & 0x1) << 13; |
| 5214 | // op: Rd32 |
| 5215 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5216 | Value |= (op & 0x1f); |
| 5217 | // op: Rx32 |
| 5218 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5219 | Value |= (op & 0x1f) << 16; |
| 5220 | break; |
| 5221 | } |
| 5222 | case Hexagon::L2_loadbsw2_pi: |
| 5223 | case Hexagon::L2_loadbzw2_pi: |
| 5224 | case Hexagon::L2_loadrh_pi: |
| 5225 | case Hexagon::L2_loadruh_pi: { |
| 5226 | // op: Ii |
| 5227 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 5228 | Value |= (op & 0x1e) << 4; |
| 5229 | // op: Rd32 |
| 5230 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5231 | Value |= (op & 0x1f); |
| 5232 | // op: Rx32 |
| 5233 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5234 | Value |= (op & 0x1f) << 16; |
| 5235 | break; |
| 5236 | } |
| 5237 | case Hexagon::S2_insert: { |
| 5238 | // op: Ii |
| 5239 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 5240 | Value |= (op & 0x1f) << 8; |
| 5241 | // op: II |
| 5242 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 5243 | Value |= (op & 0x18) << 18; |
| 5244 | Value |= (op & 0x7) << 5; |
| 5245 | // op: Rs32 |
| 5246 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 5247 | Value |= (op & 0x1f) << 16; |
| 5248 | // op: Rx32 |
| 5249 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5250 | Value |= (op & 0x1f); |
| 5251 | break; |
| 5252 | } |
| 5253 | case Hexagon::S2_asl_i_r_acc: |
| 5254 | case Hexagon::S2_asl_i_r_and: |
| 5255 | case Hexagon::S2_asl_i_r_nac: |
| 5256 | case Hexagon::S2_asl_i_r_or: |
| 5257 | case Hexagon::S2_asl_i_r_xacc: |
| 5258 | case Hexagon::S2_asr_i_r_acc: |
| 5259 | case Hexagon::S2_asr_i_r_and: |
| 5260 | case Hexagon::S2_asr_i_r_nac: |
| 5261 | case Hexagon::S2_asr_i_r_or: |
| 5262 | case Hexagon::S2_lsr_i_r_acc: |
| 5263 | case Hexagon::S2_lsr_i_r_and: |
| 5264 | case Hexagon::S2_lsr_i_r_nac: |
| 5265 | case Hexagon::S2_lsr_i_r_or: |
| 5266 | case Hexagon::S2_lsr_i_r_xacc: |
| 5267 | case Hexagon::S6_rol_i_r_acc: |
| 5268 | case Hexagon::S6_rol_i_r_and: |
| 5269 | case Hexagon::S6_rol_i_r_nac: |
| 5270 | case Hexagon::S6_rol_i_r_or: |
| 5271 | case Hexagon::S6_rol_i_r_xacc: { |
| 5272 | // op: Ii |
| 5273 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 5274 | Value |= (op & 0x1f) << 8; |
| 5275 | // op: Rs32 |
| 5276 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 5277 | Value |= (op & 0x1f) << 16; |
| 5278 | // op: Rx32 |
| 5279 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5280 | Value |= (op & 0x1f); |
| 5281 | break; |
| 5282 | } |
| 5283 | case Hexagon::L2_ploadrdf_io: |
| 5284 | case Hexagon::L2_ploadrdfnew_io: |
| 5285 | case Hexagon::L2_ploadrdt_io: |
| 5286 | case Hexagon::L2_ploadrdtnew_io: { |
| 5287 | // op: Ii |
| 5288 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 5289 | Value |= (op & 0x1f8) << 2; |
| 5290 | // op: Pt4 |
| 5291 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5292 | Value |= (op & 0x3) << 11; |
| 5293 | // op: Rs32 |
| 5294 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 5295 | Value |= (op & 0x1f) << 16; |
| 5296 | // op: Rdd32 |
| 5297 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5298 | Value |= (op & 0x1f); |
| 5299 | break; |
| 5300 | } |
| 5301 | case Hexagon::S4_vrcrotate: { |
| 5302 | // op: Ii |
| 5303 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 5304 | Value |= (op & 0x2) << 12; |
| 5305 | Value |= (op & 0x1) << 5; |
| 5306 | // op: Rss32 |
| 5307 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5308 | Value |= (op & 0x1f) << 16; |
| 5309 | // op: Rt32 |
| 5310 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 5311 | Value |= (op & 0x1f) << 8; |
| 5312 | // op: Rdd32 |
| 5313 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5314 | Value |= (op & 0x1f); |
| 5315 | break; |
| 5316 | } |
| 5317 | case Hexagon::L4_loadalignb_ur: |
| 5318 | case Hexagon::L4_loadalignh_ur: { |
| 5319 | // op: Ii |
| 5320 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 5321 | Value |= (op & 0x2) << 12; |
| 5322 | Value |= (op & 0x1) << 7; |
| 5323 | // op: II |
| 5324 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 5325 | Value |= (op & 0x3c) << 6; |
| 5326 | Value |= (op & 0x3) << 5; |
| 5327 | // op: Rt32 |
| 5328 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 5329 | Value |= (op & 0x1f) << 16; |
| 5330 | // op: Ryy32 |
| 5331 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5332 | Value |= (op & 0x1f); |
| 5333 | break; |
| 5334 | } |
| 5335 | case Hexagon::S4_pstorerbnewf_rr: |
| 5336 | case Hexagon::S4_pstorerbnewfnew_rr: |
| 5337 | case Hexagon::S4_pstorerbnewt_rr: |
| 5338 | case Hexagon::S4_pstorerbnewtnew_rr: |
| 5339 | case Hexagon::S4_pstorerhnewf_rr: |
| 5340 | case Hexagon::S4_pstorerhnewfnew_rr: |
| 5341 | case Hexagon::S4_pstorerhnewt_rr: |
| 5342 | case Hexagon::S4_pstorerhnewtnew_rr: |
| 5343 | case Hexagon::S4_pstorerinewf_rr: |
| 5344 | case Hexagon::S4_pstorerinewfnew_rr: |
| 5345 | case Hexagon::S4_pstorerinewt_rr: |
| 5346 | case Hexagon::S4_pstorerinewtnew_rr: { |
| 5347 | // op: Ii |
| 5348 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 5349 | Value |= (op & 0x2) << 12; |
| 5350 | Value |= (op & 0x1) << 7; |
| 5351 | // op: Pv4 |
| 5352 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5353 | Value |= (op & 0x3) << 5; |
| 5354 | // op: Rs32 |
| 5355 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5356 | Value |= (op & 0x1f) << 16; |
| 5357 | // op: Ru32 |
| 5358 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 5359 | Value |= (op & 0x1f) << 8; |
| 5360 | // op: Nt8 |
| 5361 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 5362 | Value |= (op & 0x7); |
| 5363 | break; |
| 5364 | } |
| 5365 | case Hexagon::S4_pstorerbf_rr: |
| 5366 | case Hexagon::S4_pstorerbfnew_rr: |
| 5367 | case Hexagon::S4_pstorerbt_rr: |
| 5368 | case Hexagon::S4_pstorerbtnew_rr: |
| 5369 | case Hexagon::S4_pstorerff_rr: |
| 5370 | case Hexagon::S4_pstorerffnew_rr: |
| 5371 | case Hexagon::S4_pstorerft_rr: |
| 5372 | case Hexagon::S4_pstorerftnew_rr: |
| 5373 | case Hexagon::S4_pstorerhf_rr: |
| 5374 | case Hexagon::S4_pstorerhfnew_rr: |
| 5375 | case Hexagon::S4_pstorerht_rr: |
| 5376 | case Hexagon::S4_pstorerhtnew_rr: |
| 5377 | case Hexagon::S4_pstorerif_rr: |
| 5378 | case Hexagon::S4_pstorerifnew_rr: |
| 5379 | case Hexagon::S4_pstorerit_rr: |
| 5380 | case Hexagon::S4_pstoreritnew_rr: { |
| 5381 | // op: Ii |
| 5382 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 5383 | Value |= (op & 0x2) << 12; |
| 5384 | Value |= (op & 0x1) << 7; |
| 5385 | // op: Pv4 |
| 5386 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5387 | Value |= (op & 0x3) << 5; |
| 5388 | // op: Rs32 |
| 5389 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5390 | Value |= (op & 0x1f) << 16; |
| 5391 | // op: Ru32 |
| 5392 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 5393 | Value |= (op & 0x1f) << 8; |
| 5394 | // op: Rt32 |
| 5395 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 5396 | Value |= (op & 0x1f); |
| 5397 | break; |
| 5398 | } |
| 5399 | case Hexagon::S4_pstorerdf_rr: |
| 5400 | case Hexagon::S4_pstorerdfnew_rr: |
| 5401 | case Hexagon::S4_pstorerdt_rr: |
| 5402 | case Hexagon::S4_pstorerdtnew_rr: { |
| 5403 | // op: Ii |
| 5404 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 5405 | Value |= (op & 0x2) << 12; |
| 5406 | Value |= (op & 0x1) << 7; |
| 5407 | // op: Pv4 |
| 5408 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5409 | Value |= (op & 0x3) << 5; |
| 5410 | // op: Rs32 |
| 5411 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5412 | Value |= (op & 0x1f) << 16; |
| 5413 | // op: Ru32 |
| 5414 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 5415 | Value |= (op & 0x1f) << 8; |
| 5416 | // op: Rtt32 |
| 5417 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 5418 | Value |= (op & 0x1f); |
| 5419 | break; |
| 5420 | } |
| 5421 | case Hexagon::L4_loadrb_rr: |
| 5422 | case Hexagon::L4_loadrh_rr: |
| 5423 | case Hexagon::L4_loadri_rr: |
| 5424 | case Hexagon::L4_loadrub_rr: |
| 5425 | case Hexagon::L4_loadruh_rr: { |
| 5426 | // op: Ii |
| 5427 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 5428 | Value |= (op & 0x2) << 12; |
| 5429 | Value |= (op & 0x1) << 7; |
| 5430 | // op: Rs32 |
| 5431 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5432 | Value |= (op & 0x1f) << 16; |
| 5433 | // op: Rt32 |
| 5434 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 5435 | Value |= (op & 0x1f) << 8; |
| 5436 | // op: Rd32 |
| 5437 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5438 | Value |= (op & 0x1f); |
| 5439 | break; |
| 5440 | } |
| 5441 | case Hexagon::L4_loadrd_rr: { |
| 5442 | // op: Ii |
| 5443 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 5444 | Value |= (op & 0x2) << 12; |
| 5445 | Value |= (op & 0x1) << 7; |
| 5446 | // op: Rs32 |
| 5447 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5448 | Value |= (op & 0x1f) << 16; |
| 5449 | // op: Rt32 |
| 5450 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 5451 | Value |= (op & 0x1f) << 8; |
| 5452 | // op: Rdd32 |
| 5453 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5454 | Value |= (op & 0x1f); |
| 5455 | break; |
| 5456 | } |
| 5457 | case Hexagon::S4_or_andi: |
| 5458 | case Hexagon::S4_or_ori: { |
| 5459 | // op: Ii |
| 5460 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 5461 | Value |= (op & 0x200) << 12; |
| 5462 | Value |= (op & 0x1ff) << 5; |
| 5463 | // op: Rs32 |
| 5464 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 5465 | Value |= (op & 0x1f) << 16; |
| 5466 | // op: Rx32 |
| 5467 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5468 | Value |= (op & 0x1f); |
| 5469 | break; |
| 5470 | } |
| 5471 | case Hexagon::S4_or_andix: { |
| 5472 | // op: Ii |
| 5473 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 5474 | Value |= (op & 0x200) << 12; |
| 5475 | Value |= (op & 0x1ff) << 5; |
| 5476 | // op: Ru32 |
| 5477 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5478 | Value |= (op & 0x1f); |
| 5479 | // op: Rx32 |
| 5480 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5481 | Value |= (op & 0x1f) << 16; |
| 5482 | break; |
| 5483 | } |
| 5484 | case Hexagon::V6_v6mpyhubs10: |
| 5485 | case Hexagon::V6_v6mpyvubs10: { |
| 5486 | // op: Ii |
| 5487 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 5488 | Value |= (op & 0x3) << 5; |
| 5489 | // op: Vuu32 |
| 5490 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5491 | Value |= (op & 0x1f) << 8; |
| 5492 | // op: Vvv32 |
| 5493 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 5494 | Value |= (op & 0x1f) << 16; |
| 5495 | // op: Vdd32 |
| 5496 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5497 | Value |= (op & 0x1f); |
| 5498 | break; |
| 5499 | } |
| 5500 | case Hexagon::S4_addaddi: { |
| 5501 | // op: Ii |
| 5502 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 5503 | Value |= (op & 0x30) << 17; |
| 5504 | Value |= (op & 0x8) << 10; |
| 5505 | Value |= (op & 0x7) << 5; |
| 5506 | // op: Rs32 |
| 5507 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5508 | Value |= (op & 0x1f) << 16; |
| 5509 | // op: Ru32 |
| 5510 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 5511 | Value |= (op & 0x1f); |
| 5512 | // op: Rd32 |
| 5513 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5514 | Value |= (op & 0x1f) << 8; |
| 5515 | break; |
| 5516 | } |
| 5517 | case Hexagon::M4_mpyri_addr: { |
| 5518 | // op: Ii |
| 5519 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 5520 | Value |= (op & 0x30) << 17; |
| 5521 | Value |= (op & 0x8) << 10; |
| 5522 | Value |= (op & 0x7) << 5; |
| 5523 | // op: Ru32 |
| 5524 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5525 | Value |= (op & 0x1f); |
| 5526 | // op: Rs32 |
| 5527 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 5528 | Value |= (op & 0x1f) << 16; |
| 5529 | // op: Rd32 |
| 5530 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5531 | Value |= (op & 0x1f) << 8; |
| 5532 | break; |
| 5533 | } |
| 5534 | case Hexagon::S2_pstorerinewf_pi: |
| 5535 | case Hexagon::S2_pstorerinewfnew_pi: |
| 5536 | case Hexagon::S2_pstorerinewt_pi: |
| 5537 | case Hexagon::S2_pstorerinewtnew_pi: { |
| 5538 | // op: Ii |
| 5539 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 5540 | Value |= (op & 0x3c) << 1; |
| 5541 | // op: Pv4 |
| 5542 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5543 | Value |= (op & 0x3); |
| 5544 | // op: Nt8 |
| 5545 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 5546 | Value |= (op & 0x7) << 8; |
| 5547 | // op: Rx32 |
| 5548 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5549 | Value |= (op & 0x1f) << 16; |
| 5550 | break; |
| 5551 | } |
| 5552 | case Hexagon::S2_pstorerif_pi: |
| 5553 | case Hexagon::S2_pstorerifnew_pi: |
| 5554 | case Hexagon::S2_pstorerit_pi: |
| 5555 | case Hexagon::S2_pstoreritnew_pi: { |
| 5556 | // op: Ii |
| 5557 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 5558 | Value |= (op & 0x3c) << 1; |
| 5559 | // op: Pv4 |
| 5560 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5561 | Value |= (op & 0x3); |
| 5562 | // op: Rt32 |
| 5563 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 5564 | Value |= (op & 0x1f) << 8; |
| 5565 | // op: Rx32 |
| 5566 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5567 | Value |= (op & 0x1f) << 16; |
| 5568 | break; |
| 5569 | } |
| 5570 | case Hexagon::L2_loadri_pci: { |
| 5571 | // op: Ii |
| 5572 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 5573 | Value |= (op & 0x3c) << 3; |
| 5574 | // op: Mu2 |
| 5575 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 5576 | Value |= (op & 0x1) << 13; |
| 5577 | // op: Rd32 |
| 5578 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5579 | Value |= (op & 0x1f); |
| 5580 | // op: Rx32 |
| 5581 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5582 | Value |= (op & 0x1f) << 16; |
| 5583 | break; |
| 5584 | } |
| 5585 | case Hexagon::L2_loadbsw4_pci: |
| 5586 | case Hexagon::L2_loadbzw4_pci: { |
| 5587 | // op: Ii |
| 5588 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 5589 | Value |= (op & 0x3c) << 3; |
| 5590 | // op: Mu2 |
| 5591 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 5592 | Value |= (op & 0x1) << 13; |
| 5593 | // op: Rdd32 |
| 5594 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5595 | Value |= (op & 0x1f); |
| 5596 | // op: Rx32 |
| 5597 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5598 | Value |= (op & 0x1f) << 16; |
| 5599 | break; |
| 5600 | } |
| 5601 | case Hexagon::L2_loadri_pi: { |
| 5602 | // op: Ii |
| 5603 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 5604 | Value |= (op & 0x3c) << 3; |
| 5605 | // op: Rd32 |
| 5606 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5607 | Value |= (op & 0x1f); |
| 5608 | // op: Rx32 |
| 5609 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5610 | Value |= (op & 0x1f) << 16; |
| 5611 | break; |
| 5612 | } |
| 5613 | case Hexagon::L2_loadbsw4_pi: |
| 5614 | case Hexagon::L2_loadbzw4_pi: { |
| 5615 | // op: Ii |
| 5616 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 5617 | Value |= (op & 0x3c) << 3; |
| 5618 | // op: Rdd32 |
| 5619 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5620 | Value |= (op & 0x1f); |
| 5621 | // op: Rx32 |
| 5622 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5623 | Value |= (op & 0x1f) << 16; |
| 5624 | break; |
| 5625 | } |
| 5626 | case Hexagon::L2_ploadrbf_io: |
| 5627 | case Hexagon::L2_ploadrbfnew_io: |
| 5628 | case Hexagon::L2_ploadrbt_io: |
| 5629 | case Hexagon::L2_ploadrbtnew_io: |
| 5630 | case Hexagon::L2_ploadrubf_io: |
| 5631 | case Hexagon::L2_ploadrubfnew_io: |
| 5632 | case Hexagon::L2_ploadrubt_io: |
| 5633 | case Hexagon::L2_ploadrubtnew_io: { |
| 5634 | // op: Ii |
| 5635 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 5636 | Value |= (op & 0x3f) << 5; |
| 5637 | // op: Pt4 |
| 5638 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5639 | Value |= (op & 0x3) << 11; |
| 5640 | // op: Rs32 |
| 5641 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 5642 | Value |= (op & 0x1f) << 16; |
| 5643 | // op: Rd32 |
| 5644 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5645 | Value |= (op & 0x1f); |
| 5646 | break; |
| 5647 | } |
| 5648 | case Hexagon::S2_insertp: { |
| 5649 | // op: Ii |
| 5650 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 5651 | Value |= (op & 0x3f) << 8; |
| 5652 | // op: II |
| 5653 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 5654 | Value |= (op & 0x38) << 18; |
| 5655 | Value |= (op & 0x7) << 5; |
| 5656 | // op: Rss32 |
| 5657 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 5658 | Value |= (op & 0x1f) << 16; |
| 5659 | // op: Rxx32 |
| 5660 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5661 | Value |= (op & 0x1f); |
| 5662 | break; |
| 5663 | } |
| 5664 | case Hexagon::S2_asl_i_p_acc: |
| 5665 | case Hexagon::S2_asl_i_p_and: |
| 5666 | case Hexagon::S2_asl_i_p_nac: |
| 5667 | case Hexagon::S2_asl_i_p_or: |
| 5668 | case Hexagon::S2_asl_i_p_xacc: |
| 5669 | case Hexagon::S2_asr_i_p_acc: |
| 5670 | case Hexagon::S2_asr_i_p_and: |
| 5671 | case Hexagon::S2_asr_i_p_nac: |
| 5672 | case Hexagon::S2_asr_i_p_or: |
| 5673 | case Hexagon::S2_lsr_i_p_acc: |
| 5674 | case Hexagon::S2_lsr_i_p_and: |
| 5675 | case Hexagon::S2_lsr_i_p_nac: |
| 5676 | case Hexagon::S2_lsr_i_p_or: |
| 5677 | case Hexagon::S2_lsr_i_p_xacc: |
| 5678 | case Hexagon::S6_rol_i_p_acc: |
| 5679 | case Hexagon::S6_rol_i_p_and: |
| 5680 | case Hexagon::S6_rol_i_p_nac: |
| 5681 | case Hexagon::S6_rol_i_p_or: |
| 5682 | case Hexagon::S6_rol_i_p_xacc: { |
| 5683 | // op: Ii |
| 5684 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 5685 | Value |= (op & 0x3f) << 8; |
| 5686 | // op: Rss32 |
| 5687 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 5688 | Value |= (op & 0x1f) << 16; |
| 5689 | // op: Rxx32 |
| 5690 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5691 | Value |= (op & 0x1f); |
| 5692 | break; |
| 5693 | } |
| 5694 | case Hexagon::L2_loadalignb_io: { |
| 5695 | // op: Ii |
| 5696 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 5697 | Value |= (op & 0x600) << 16; |
| 5698 | Value |= (op & 0x1ff) << 5; |
| 5699 | // op: Rs32 |
| 5700 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 5701 | Value |= (op & 0x1f) << 16; |
| 5702 | // op: Ryy32 |
| 5703 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5704 | Value |= (op & 0x1f); |
| 5705 | break; |
| 5706 | } |
| 5707 | case Hexagon::S2_vspliceib: { |
| 5708 | // op: Ii |
| 5709 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 5710 | Value |= (op & 0x7) << 5; |
| 5711 | // op: Rss32 |
| 5712 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5713 | Value |= (op & 0x1f) << 16; |
| 5714 | // op: Rtt32 |
| 5715 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 5716 | Value |= (op & 0x1f) << 8; |
| 5717 | // op: Rdd32 |
| 5718 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5719 | Value |= (op & 0x1f); |
| 5720 | break; |
| 5721 | } |
| 5722 | case Hexagon::S2_addasl_rrri: { |
| 5723 | // op: Ii |
| 5724 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 5725 | Value |= (op & 0x7) << 5; |
| 5726 | // op: Rt32 |
| 5727 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5728 | Value |= (op & 0x1f) << 8; |
| 5729 | // op: Rs32 |
| 5730 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 5731 | Value |= (op & 0x1f) << 16; |
| 5732 | // op: Rd32 |
| 5733 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5734 | Value |= (op & 0x1f); |
| 5735 | break; |
| 5736 | } |
| 5737 | case Hexagon::S2_valignib: { |
| 5738 | // op: Ii |
| 5739 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 5740 | Value |= (op & 0x7) << 5; |
| 5741 | // op: Rtt32 |
| 5742 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5743 | Value |= (op & 0x1f) << 8; |
| 5744 | // op: Rss32 |
| 5745 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 5746 | Value |= (op & 0x1f) << 16; |
| 5747 | // op: Rdd32 |
| 5748 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5749 | Value |= (op & 0x1f); |
| 5750 | break; |
| 5751 | } |
| 5752 | case Hexagon::V6_valignbi: |
| 5753 | case Hexagon::V6_vlalignbi: |
| 5754 | case Hexagon::V6_vlutvvbi: { |
| 5755 | // op: Ii |
| 5756 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 5757 | Value |= (op & 0x7) << 5; |
| 5758 | // op: Vu32 |
| 5759 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5760 | Value |= (op & 0x1f) << 8; |
| 5761 | // op: Vv32 |
| 5762 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 5763 | Value |= (op & 0x1f) << 16; |
| 5764 | // op: Vd32 |
| 5765 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5766 | Value |= (op & 0x1f); |
| 5767 | break; |
| 5768 | } |
| 5769 | case Hexagon::V6_vlutvwhi: { |
| 5770 | // op: Ii |
| 5771 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 5772 | Value |= (op & 0x7) << 5; |
| 5773 | // op: Vu32 |
| 5774 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5775 | Value |= (op & 0x1f) << 8; |
| 5776 | // op: Vv32 |
| 5777 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 5778 | Value |= (op & 0x1f) << 16; |
| 5779 | // op: Vdd32 |
| 5780 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5781 | Value |= (op & 0x1f); |
| 5782 | break; |
| 5783 | } |
| 5784 | case Hexagon::V6_vS32b_new_npred_pi: |
| 5785 | case Hexagon::V6_vS32b_new_pred_pi: |
| 5786 | case Hexagon::V6_vS32b_nt_new_npred_pi: |
| 5787 | case Hexagon::V6_vS32b_nt_new_pred_pi: { |
| 5788 | // op: Ii |
| 5789 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 5790 | Value |= (op & 0x7) << 8; |
| 5791 | // op: Pv4 |
| 5792 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5793 | Value |= (op & 0x3) << 11; |
| 5794 | // op: Os8 |
| 5795 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 5796 | Value |= (op & 0x7); |
| 5797 | // op: Rx32 |
| 5798 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5799 | Value |= (op & 0x1f) << 16; |
| 5800 | break; |
| 5801 | } |
| 5802 | case Hexagon::V6_zLd_pred_pi: { |
| 5803 | // op: Ii |
| 5804 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 5805 | Value |= (op & 0x7) << 8; |
| 5806 | // op: Pv4 |
| 5807 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5808 | Value |= (op & 0x3) << 11; |
| 5809 | // op: Rx32 |
| 5810 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5811 | Value |= (op & 0x1f) << 16; |
| 5812 | break; |
| 5813 | } |
| 5814 | case Hexagon::V6_vS32Ub_npred_pi: |
| 5815 | case Hexagon::V6_vS32Ub_pred_pi: |
| 5816 | case Hexagon::V6_vS32b_npred_pi: |
| 5817 | case Hexagon::V6_vS32b_nt_npred_pi: |
| 5818 | case Hexagon::V6_vS32b_nt_pred_pi: |
| 5819 | case Hexagon::V6_vS32b_pred_pi: { |
| 5820 | // op: Ii |
| 5821 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 5822 | Value |= (op & 0x7) << 8; |
| 5823 | // op: Pv4 |
| 5824 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5825 | Value |= (op & 0x3) << 11; |
| 5826 | // op: Vs32 |
| 5827 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 5828 | Value |= (op & 0x1f); |
| 5829 | // op: Rx32 |
| 5830 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5831 | Value |= (op & 0x1f) << 16; |
| 5832 | break; |
| 5833 | } |
| 5834 | case Hexagon::V6_vS32b_nqpred_pi: |
| 5835 | case Hexagon::V6_vS32b_nt_nqpred_pi: |
| 5836 | case Hexagon::V6_vS32b_nt_qpred_pi: |
| 5837 | case Hexagon::V6_vS32b_qpred_pi: { |
| 5838 | // op: Ii |
| 5839 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 5840 | Value |= (op & 0x7) << 8; |
| 5841 | // op: Qv4 |
| 5842 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5843 | Value |= (op & 0x3) << 11; |
| 5844 | // op: Vs32 |
| 5845 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 5846 | Value |= (op & 0x1f); |
| 5847 | // op: Rx32 |
| 5848 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5849 | Value |= (op & 0x1f) << 16; |
| 5850 | break; |
| 5851 | } |
| 5852 | case Hexagon::V6_vL32Ub_pi: |
| 5853 | case Hexagon::V6_vL32b_cur_pi: |
| 5854 | case Hexagon::V6_vL32b_nt_cur_pi: |
| 5855 | case Hexagon::V6_vL32b_nt_pi: |
| 5856 | case Hexagon::V6_vL32b_nt_tmp_pi: |
| 5857 | case Hexagon::V6_vL32b_pi: |
| 5858 | case Hexagon::V6_vL32b_tmp_pi: { |
| 5859 | // op: Ii |
| 5860 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 5861 | Value |= (op & 0x7) << 8; |
| 5862 | // op: Vd32 |
| 5863 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5864 | Value |= (op & 0x1f); |
| 5865 | // op: Rx32 |
| 5866 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5867 | Value |= (op & 0x1f) << 16; |
| 5868 | break; |
| 5869 | } |
| 5870 | case Hexagon::L2_loadrd_pci: { |
| 5871 | // op: Ii |
| 5872 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 5873 | Value |= (op & 0x78) << 2; |
| 5874 | // op: Mu2 |
| 5875 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 5876 | Value |= (op & 0x1) << 13; |
| 5877 | // op: Rdd32 |
| 5878 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5879 | Value |= (op & 0x1f); |
| 5880 | // op: Rx32 |
| 5881 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5882 | Value |= (op & 0x1f) << 16; |
| 5883 | break; |
| 5884 | } |
| 5885 | case Hexagon::L2_loadrd_pi: { |
| 5886 | // op: Ii |
| 5887 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 5888 | Value |= (op & 0x78) << 2; |
| 5889 | // op: Rdd32 |
| 5890 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5891 | Value |= (op & 0x1f); |
| 5892 | // op: Rx32 |
| 5893 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5894 | Value |= (op & 0x1f) << 16; |
| 5895 | break; |
| 5896 | } |
| 5897 | case Hexagon::S2_pstorerdf_pi: |
| 5898 | case Hexagon::S2_pstorerdfnew_pi: |
| 5899 | case Hexagon::S2_pstorerdt_pi: |
| 5900 | case Hexagon::S2_pstorerdtnew_pi: { |
| 5901 | // op: Ii |
| 5902 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 5903 | Value |= (op & 0x78); |
| 5904 | // op: Pv4 |
| 5905 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5906 | Value |= (op & 0x3); |
| 5907 | // op: Rtt32 |
| 5908 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 5909 | Value |= (op & 0x1f) << 8; |
| 5910 | // op: Rx32 |
| 5911 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5912 | Value |= (op & 0x1f) << 16; |
| 5913 | break; |
| 5914 | } |
| 5915 | case Hexagon::L2_ploadrhf_io: |
| 5916 | case Hexagon::L2_ploadrhfnew_io: |
| 5917 | case Hexagon::L2_ploadrht_io: |
| 5918 | case Hexagon::L2_ploadrhtnew_io: |
| 5919 | case Hexagon::L2_ploadruhf_io: |
| 5920 | case Hexagon::L2_ploadruhfnew_io: |
| 5921 | case Hexagon::L2_ploadruht_io: |
| 5922 | case Hexagon::L2_ploadruhtnew_io: { |
| 5923 | // op: Ii |
| 5924 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 5925 | Value |= (op & 0x7e) << 4; |
| 5926 | // op: Pt4 |
| 5927 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5928 | Value |= (op & 0x3) << 11; |
| 5929 | // op: Rs32 |
| 5930 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 5931 | Value |= (op & 0x1f) << 16; |
| 5932 | // op: Rd32 |
| 5933 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5934 | Value |= (op & 0x1f); |
| 5935 | break; |
| 5936 | } |
| 5937 | case Hexagon::V6_vL32b_cur_npred_ai: |
| 5938 | case Hexagon::V6_vL32b_cur_pred_ai: |
| 5939 | case Hexagon::V6_vL32b_npred_ai: |
| 5940 | case Hexagon::V6_vL32b_nt_cur_npred_ai: |
| 5941 | case Hexagon::V6_vL32b_nt_cur_pred_ai: |
| 5942 | case Hexagon::V6_vL32b_nt_npred_ai: |
| 5943 | case Hexagon::V6_vL32b_nt_pred_ai: |
| 5944 | case Hexagon::V6_vL32b_nt_tmp_npred_ai: |
| 5945 | case Hexagon::V6_vL32b_nt_tmp_pred_ai: |
| 5946 | case Hexagon::V6_vL32b_pred_ai: |
| 5947 | case Hexagon::V6_vL32b_tmp_npred_ai: |
| 5948 | case Hexagon::V6_vL32b_tmp_pred_ai: { |
| 5949 | // op: Ii |
| 5950 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 5951 | Value |= (op & 0x8) << 10; |
| 5952 | Value |= (op & 0x7) << 8; |
| 5953 | // op: Pv4 |
| 5954 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 5955 | Value |= (op & 0x3) << 11; |
| 5956 | // op: Rt32 |
| 5957 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 5958 | Value |= (op & 0x1f) << 16; |
| 5959 | // op: Vd32 |
| 5960 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5961 | Value |= (op & 0x1f); |
| 5962 | break; |
| 5963 | } |
| 5964 | case Hexagon::S2_tableidxb: |
| 5965 | case Hexagon::S2_tableidxd: |
| 5966 | case Hexagon::S2_tableidxh: |
| 5967 | case Hexagon::S2_tableidxw: { |
| 5968 | // op: Ii |
| 5969 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 5970 | Value |= (op & 0x8) << 18; |
| 5971 | Value |= (op & 0x7) << 5; |
| 5972 | // op: II |
| 5973 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 5974 | Value |= (op & 0x3f) << 8; |
| 5975 | // op: Rs32 |
| 5976 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 5977 | Value |= (op & 0x1f) << 16; |
| 5978 | // op: Rx32 |
| 5979 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5980 | Value |= (op & 0x1f); |
| 5981 | break; |
| 5982 | } |
| 5983 | case Hexagon::L2_loadalignh_io: { |
| 5984 | // op: Ii |
| 5985 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 5986 | Value |= (op & 0xc00) << 15; |
| 5987 | Value |= (op & 0x3fe) << 4; |
| 5988 | // op: Rs32 |
| 5989 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 5990 | Value |= (op & 0x1f) << 16; |
| 5991 | // op: Ryy32 |
| 5992 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 5993 | Value |= (op & 0x1f); |
| 5994 | break; |
| 5995 | } |
| 5996 | case Hexagon::S2_pstorerbnewf_pi: |
| 5997 | case Hexagon::S2_pstorerbnewfnew_pi: |
| 5998 | case Hexagon::S2_pstorerbnewt_pi: |
| 5999 | case Hexagon::S2_pstorerbnewtnew_pi: { |
| 6000 | // op: Ii |
| 6001 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 6002 | Value |= (op & 0xf) << 3; |
| 6003 | // op: Pv4 |
| 6004 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6005 | Value |= (op & 0x3); |
| 6006 | // op: Nt8 |
| 6007 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 6008 | Value |= (op & 0x7) << 8; |
| 6009 | // op: Rx32 |
| 6010 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6011 | Value |= (op & 0x1f) << 16; |
| 6012 | break; |
| 6013 | } |
| 6014 | case Hexagon::S2_pstorerbf_pi: |
| 6015 | case Hexagon::S2_pstorerbfnew_pi: |
| 6016 | case Hexagon::S2_pstorerbt_pi: |
| 6017 | case Hexagon::S2_pstorerbtnew_pi: { |
| 6018 | // op: Ii |
| 6019 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 6020 | Value |= (op & 0xf) << 3; |
| 6021 | // op: Pv4 |
| 6022 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6023 | Value |= (op & 0x3); |
| 6024 | // op: Rt32 |
| 6025 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 6026 | Value |= (op & 0x1f) << 8; |
| 6027 | // op: Rx32 |
| 6028 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6029 | Value |= (op & 0x1f) << 16; |
| 6030 | break; |
| 6031 | } |
| 6032 | case Hexagon::L2_loadrb_pci: |
| 6033 | case Hexagon::L2_loadrub_pci: { |
| 6034 | // op: Ii |
| 6035 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 6036 | Value |= (op & 0xf) << 5; |
| 6037 | // op: Mu2 |
| 6038 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 6039 | Value |= (op & 0x1) << 13; |
| 6040 | // op: Rd32 |
| 6041 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6042 | Value |= (op & 0x1f); |
| 6043 | // op: Rx32 |
| 6044 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6045 | Value |= (op & 0x1f) << 16; |
| 6046 | break; |
| 6047 | } |
| 6048 | case Hexagon::L2_loadrb_pi: |
| 6049 | case Hexagon::L2_loadrub_pi: { |
| 6050 | // op: Ii |
| 6051 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 6052 | Value |= (op & 0xf) << 5; |
| 6053 | // op: Rd32 |
| 6054 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6055 | Value |= (op & 0x1f); |
| 6056 | // op: Rx32 |
| 6057 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6058 | Value |= (op & 0x1f) << 16; |
| 6059 | break; |
| 6060 | } |
| 6061 | case Hexagon::L2_ploadrif_io: |
| 6062 | case Hexagon::L2_ploadrifnew_io: |
| 6063 | case Hexagon::L2_ploadrit_io: |
| 6064 | case Hexagon::L2_ploadritnew_io: { |
| 6065 | // op: Ii |
| 6066 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 6067 | Value |= (op & 0xfc) << 3; |
| 6068 | // op: Pt4 |
| 6069 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6070 | Value |= (op & 0x3) << 11; |
| 6071 | // op: Rs32 |
| 6072 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6073 | Value |= (op & 0x1f) << 16; |
| 6074 | // op: Rd32 |
| 6075 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6076 | Value |= (op & 0x1f); |
| 6077 | break; |
| 6078 | } |
| 6079 | case Hexagon::A2_paddif: |
| 6080 | case Hexagon::A2_paddifnew: |
| 6081 | case Hexagon::A2_paddit: |
| 6082 | case Hexagon::A2_padditnew: |
| 6083 | case Hexagon::C2_muxir: { |
| 6084 | // op: Ii |
| 6085 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 6086 | Value |= (op & 0xff) << 5; |
| 6087 | // op: Pu4 |
| 6088 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6089 | Value |= (op & 0x3) << 21; |
| 6090 | // op: Rs32 |
| 6091 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6092 | Value |= (op & 0x1f) << 16; |
| 6093 | // op: Rd32 |
| 6094 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6095 | Value |= (op & 0x1f); |
| 6096 | break; |
| 6097 | } |
| 6098 | case Hexagon::M2_accii: |
| 6099 | case Hexagon::M2_macsin: |
| 6100 | case Hexagon::M2_macsip: |
| 6101 | case Hexagon::M2_naccii: { |
| 6102 | // op: Ii |
| 6103 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 6104 | Value |= (op & 0xff) << 5; |
| 6105 | // op: Rs32 |
| 6106 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6107 | Value |= (op & 0x1f) << 16; |
| 6108 | // op: Rx32 |
| 6109 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6110 | Value |= (op & 0x1f); |
| 6111 | break; |
| 6112 | } |
| 6113 | case Hexagon::V6_vrmpybusi_acc: |
| 6114 | case Hexagon::V6_vrmpyubi_acc: |
| 6115 | case Hexagon::V6_vrsadubi_acc: { |
| 6116 | // op: Ii |
| 6117 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 6118 | Value |= (op & 0x1) << 5; |
| 6119 | // op: Vuu32 |
| 6120 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6121 | Value |= (op & 0x1f) << 8; |
| 6122 | // op: Rt32 |
| 6123 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 6124 | Value |= (op & 0x1f) << 16; |
| 6125 | // op: Vxx32 |
| 6126 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6127 | Value |= (op & 0x1f); |
| 6128 | break; |
| 6129 | } |
| 6130 | case Hexagon::L2_loadalignh_pci: { |
| 6131 | // op: Ii |
| 6132 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 6133 | Value |= (op & 0x1e) << 4; |
| 6134 | // op: Mu2 |
| 6135 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI); |
| 6136 | Value |= (op & 0x1) << 13; |
| 6137 | // op: Ryy32 |
| 6138 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6139 | Value |= (op & 0x1f); |
| 6140 | // op: Rx32 |
| 6141 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6142 | Value |= (op & 0x1f) << 16; |
| 6143 | break; |
| 6144 | } |
| 6145 | case Hexagon::L2_ploadrhf_pi: |
| 6146 | case Hexagon::L2_ploadrhfnew_pi: |
| 6147 | case Hexagon::L2_ploadrht_pi: |
| 6148 | case Hexagon::L2_ploadrhtnew_pi: |
| 6149 | case Hexagon::L2_ploadruhf_pi: |
| 6150 | case Hexagon::L2_ploadruhfnew_pi: |
| 6151 | case Hexagon::L2_ploadruht_pi: |
| 6152 | case Hexagon::L2_ploadruhtnew_pi: { |
| 6153 | // op: Ii |
| 6154 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 6155 | Value |= (op & 0x1e) << 4; |
| 6156 | // op: Pt4 |
| 6157 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6158 | Value |= (op & 0x3) << 9; |
| 6159 | // op: Rd32 |
| 6160 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6161 | Value |= (op & 0x1f); |
| 6162 | // op: Rx32 |
| 6163 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6164 | Value |= (op & 0x1f) << 16; |
| 6165 | break; |
| 6166 | } |
| 6167 | case Hexagon::L2_loadalignh_pi: { |
| 6168 | // op: Ii |
| 6169 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 6170 | Value |= (op & 0x1e) << 4; |
| 6171 | // op: Ryy32 |
| 6172 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6173 | Value |= (op & 0x1f); |
| 6174 | // op: Rx32 |
| 6175 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6176 | Value |= (op & 0x1f) << 16; |
| 6177 | break; |
| 6178 | } |
| 6179 | case Hexagon::S4_vrcrotate_acc: { |
| 6180 | // op: Ii |
| 6181 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 6182 | Value |= (op & 0x2) << 12; |
| 6183 | Value |= (op & 0x1) << 5; |
| 6184 | // op: Rss32 |
| 6185 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6186 | Value |= (op & 0x1f) << 16; |
| 6187 | // op: Rt32 |
| 6188 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 6189 | Value |= (op & 0x1f) << 8; |
| 6190 | // op: Rxx32 |
| 6191 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6192 | Value |= (op & 0x1f); |
| 6193 | break; |
| 6194 | } |
| 6195 | case Hexagon::L4_ploadrbf_rr: |
| 6196 | case Hexagon::L4_ploadrbfnew_rr: |
| 6197 | case Hexagon::L4_ploadrbt_rr: |
| 6198 | case Hexagon::L4_ploadrbtnew_rr: |
| 6199 | case Hexagon::L4_ploadrhf_rr: |
| 6200 | case Hexagon::L4_ploadrhfnew_rr: |
| 6201 | case Hexagon::L4_ploadrht_rr: |
| 6202 | case Hexagon::L4_ploadrhtnew_rr: |
| 6203 | case Hexagon::L4_ploadrif_rr: |
| 6204 | case Hexagon::L4_ploadrifnew_rr: |
| 6205 | case Hexagon::L4_ploadrit_rr: |
| 6206 | case Hexagon::L4_ploadritnew_rr: |
| 6207 | case Hexagon::L4_ploadrubf_rr: |
| 6208 | case Hexagon::L4_ploadrubfnew_rr: |
| 6209 | case Hexagon::L4_ploadrubt_rr: |
| 6210 | case Hexagon::L4_ploadrubtnew_rr: |
| 6211 | case Hexagon::L4_ploadruhf_rr: |
| 6212 | case Hexagon::L4_ploadruhfnew_rr: |
| 6213 | case Hexagon::L4_ploadruht_rr: |
| 6214 | case Hexagon::L4_ploadruhtnew_rr: { |
| 6215 | // op: Ii |
| 6216 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 6217 | Value |= (op & 0x2) << 12; |
| 6218 | Value |= (op & 0x1) << 7; |
| 6219 | // op: Pv4 |
| 6220 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6221 | Value |= (op & 0x3) << 5; |
| 6222 | // op: Rs32 |
| 6223 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6224 | Value |= (op & 0x1f) << 16; |
| 6225 | // op: Rt32 |
| 6226 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 6227 | Value |= (op & 0x1f) << 8; |
| 6228 | // op: Rd32 |
| 6229 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6230 | Value |= (op & 0x1f); |
| 6231 | break; |
| 6232 | } |
| 6233 | case Hexagon::L4_ploadrdf_rr: |
| 6234 | case Hexagon::L4_ploadrdfnew_rr: |
| 6235 | case Hexagon::L4_ploadrdt_rr: |
| 6236 | case Hexagon::L4_ploadrdtnew_rr: { |
| 6237 | // op: Ii |
| 6238 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 6239 | Value |= (op & 0x2) << 12; |
| 6240 | Value |= (op & 0x1) << 7; |
| 6241 | // op: Pv4 |
| 6242 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6243 | Value |= (op & 0x3) << 5; |
| 6244 | // op: Rs32 |
| 6245 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6246 | Value |= (op & 0x1f) << 16; |
| 6247 | // op: Rt32 |
| 6248 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 6249 | Value |= (op & 0x1f) << 8; |
| 6250 | // op: Rdd32 |
| 6251 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6252 | Value |= (op & 0x1f); |
| 6253 | break; |
| 6254 | } |
| 6255 | case Hexagon::V6_v6mpyhubs10_vxx: |
| 6256 | case Hexagon::V6_v6mpyvubs10_vxx: { |
| 6257 | // op: Ii |
| 6258 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 6259 | Value |= (op & 0x3) << 5; |
| 6260 | // op: Vuu32 |
| 6261 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6262 | Value |= (op & 0x1f) << 8; |
| 6263 | // op: Vvv32 |
| 6264 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 6265 | Value |= (op & 0x1f) << 16; |
| 6266 | // op: Vxx32 |
| 6267 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6268 | Value |= (op & 0x1f); |
| 6269 | break; |
| 6270 | } |
| 6271 | case Hexagon::L2_ploadrif_pi: |
| 6272 | case Hexagon::L2_ploadrifnew_pi: |
| 6273 | case Hexagon::L2_ploadrit_pi: |
| 6274 | case Hexagon::L2_ploadritnew_pi: { |
| 6275 | // op: Ii |
| 6276 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 6277 | Value |= (op & 0x3c) << 3; |
| 6278 | // op: Pt4 |
| 6279 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6280 | Value |= (op & 0x3) << 9; |
| 6281 | // op: Rd32 |
| 6282 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6283 | Value |= (op & 0x1f); |
| 6284 | // op: Rx32 |
| 6285 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6286 | Value |= (op & 0x1f) << 16; |
| 6287 | break; |
| 6288 | } |
| 6289 | case Hexagon::V6_vlutvvb_oracci: { |
| 6290 | // op: Ii |
| 6291 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 6292 | Value |= (op & 0x7) << 5; |
| 6293 | // op: Vu32 |
| 6294 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6295 | Value |= (op & 0x1f) << 8; |
| 6296 | // op: Vv32 |
| 6297 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 6298 | Value |= (op & 0x1f) << 16; |
| 6299 | // op: Vx32 |
| 6300 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6301 | Value |= (op & 0x1f); |
| 6302 | break; |
| 6303 | } |
| 6304 | case Hexagon::V6_vlutvwh_oracci: { |
| 6305 | // op: Ii |
| 6306 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 6307 | Value |= (op & 0x7) << 5; |
| 6308 | // op: Vu32 |
| 6309 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6310 | Value |= (op & 0x1f) << 8; |
| 6311 | // op: Vv32 |
| 6312 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 6313 | Value |= (op & 0x1f) << 16; |
| 6314 | // op: Vxx32 |
| 6315 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6316 | Value |= (op & 0x1f); |
| 6317 | break; |
| 6318 | } |
| 6319 | case Hexagon::V6_vL32b_cur_npred_pi: |
| 6320 | case Hexagon::V6_vL32b_cur_pred_pi: |
| 6321 | case Hexagon::V6_vL32b_npred_pi: |
| 6322 | case Hexagon::V6_vL32b_nt_cur_npred_pi: |
| 6323 | case Hexagon::V6_vL32b_nt_cur_pred_pi: |
| 6324 | case Hexagon::V6_vL32b_nt_npred_pi: |
| 6325 | case Hexagon::V6_vL32b_nt_pred_pi: |
| 6326 | case Hexagon::V6_vL32b_nt_tmp_npred_pi: |
| 6327 | case Hexagon::V6_vL32b_nt_tmp_pred_pi: |
| 6328 | case Hexagon::V6_vL32b_pred_pi: |
| 6329 | case Hexagon::V6_vL32b_tmp_npred_pi: |
| 6330 | case Hexagon::V6_vL32b_tmp_pred_pi: { |
| 6331 | // op: Ii |
| 6332 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 6333 | Value |= (op & 0x7) << 8; |
| 6334 | // op: Pv4 |
| 6335 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6336 | Value |= (op & 0x3) << 11; |
| 6337 | // op: Vd32 |
| 6338 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6339 | Value |= (op & 0x1f); |
| 6340 | // op: Rx32 |
| 6341 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6342 | Value |= (op & 0x1f) << 16; |
| 6343 | break; |
| 6344 | } |
| 6345 | case Hexagon::L2_ploadrdf_pi: |
| 6346 | case Hexagon::L2_ploadrdfnew_pi: |
| 6347 | case Hexagon::L2_ploadrdt_pi: |
| 6348 | case Hexagon::L2_ploadrdtnew_pi: { |
| 6349 | // op: Ii |
| 6350 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 6351 | Value |= (op & 0x78) << 2; |
| 6352 | // op: Pt4 |
| 6353 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6354 | Value |= (op & 0x3) << 9; |
| 6355 | // op: Rdd32 |
| 6356 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6357 | Value |= (op & 0x1f); |
| 6358 | // op: Rx32 |
| 6359 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6360 | Value |= (op & 0x1f) << 16; |
| 6361 | break; |
| 6362 | } |
| 6363 | case Hexagon::L2_loadalignb_pci: { |
| 6364 | // op: Ii |
| 6365 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 6366 | Value |= (op & 0xf) << 5; |
| 6367 | // op: Mu2 |
| 6368 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI); |
| 6369 | Value |= (op & 0x1) << 13; |
| 6370 | // op: Ryy32 |
| 6371 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6372 | Value |= (op & 0x1f); |
| 6373 | // op: Rx32 |
| 6374 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6375 | Value |= (op & 0x1f) << 16; |
| 6376 | break; |
| 6377 | } |
| 6378 | case Hexagon::L2_ploadrbf_pi: |
| 6379 | case Hexagon::L2_ploadrbfnew_pi: |
| 6380 | case Hexagon::L2_ploadrbt_pi: |
| 6381 | case Hexagon::L2_ploadrbtnew_pi: |
| 6382 | case Hexagon::L2_ploadrubf_pi: |
| 6383 | case Hexagon::L2_ploadrubfnew_pi: |
| 6384 | case Hexagon::L2_ploadrubt_pi: |
| 6385 | case Hexagon::L2_ploadrubtnew_pi: { |
| 6386 | // op: Ii |
| 6387 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 6388 | Value |= (op & 0xf) << 5; |
| 6389 | // op: Pt4 |
| 6390 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6391 | Value |= (op & 0x3) << 9; |
| 6392 | // op: Rd32 |
| 6393 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6394 | Value |= (op & 0x1f); |
| 6395 | // op: Rx32 |
| 6396 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6397 | Value |= (op & 0x1f) << 16; |
| 6398 | break; |
| 6399 | } |
| 6400 | case Hexagon::L2_loadalignb_pi: { |
| 6401 | // op: Ii |
| 6402 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 6403 | Value |= (op & 0xf) << 5; |
| 6404 | // op: Ryy32 |
| 6405 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6406 | Value |= (op & 0x1f); |
| 6407 | // op: Rx32 |
| 6408 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6409 | Value |= (op & 0x1f) << 16; |
| 6410 | break; |
| 6411 | } |
| 6412 | case Hexagon::S2_storerbnew_pbr: |
| 6413 | case Hexagon::S2_storerbnew_pcr: |
| 6414 | case Hexagon::S2_storerbnew_pr: |
| 6415 | case Hexagon::S2_storerhnew_pbr: |
| 6416 | case Hexagon::S2_storerhnew_pcr: |
| 6417 | case Hexagon::S2_storerhnew_pr: |
| 6418 | case Hexagon::S2_storerinew_pbr: |
| 6419 | case Hexagon::S2_storerinew_pcr: |
| 6420 | case Hexagon::S2_storerinew_pr: { |
| 6421 | // op: Mu2 |
| 6422 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6423 | Value |= (op & 0x1) << 13; |
| 6424 | // op: Nt8 |
| 6425 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 6426 | Value |= (op & 0x7) << 8; |
| 6427 | // op: Rx32 |
| 6428 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6429 | Value |= (op & 0x1f) << 16; |
| 6430 | break; |
| 6431 | } |
| 6432 | case Hexagon::V6_vS32b_new_ppu: |
| 6433 | case Hexagon::V6_vS32b_nt_new_ppu: { |
| 6434 | // op: Mu2 |
| 6435 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6436 | Value |= (op & 0x1) << 13; |
| 6437 | // op: Os8 |
| 6438 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 6439 | Value |= (op & 0x7); |
| 6440 | // op: Rx32 |
| 6441 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6442 | Value |= (op & 0x1f) << 16; |
| 6443 | break; |
| 6444 | } |
| 6445 | case Hexagon::S2_storerb_pbr: |
| 6446 | case Hexagon::S2_storerb_pcr: |
| 6447 | case Hexagon::S2_storerb_pr: |
| 6448 | case Hexagon::S2_storerf_pbr: |
| 6449 | case Hexagon::S2_storerf_pcr: |
| 6450 | case Hexagon::S2_storerf_pr: |
| 6451 | case Hexagon::S2_storerh_pbr: |
| 6452 | case Hexagon::S2_storerh_pcr: |
| 6453 | case Hexagon::S2_storerh_pr: |
| 6454 | case Hexagon::S2_storeri_pbr: |
| 6455 | case Hexagon::S2_storeri_pcr: |
| 6456 | case Hexagon::S2_storeri_pr: { |
| 6457 | // op: Mu2 |
| 6458 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6459 | Value |= (op & 0x1) << 13; |
| 6460 | // op: Rt32 |
| 6461 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 6462 | Value |= (op & 0x1f) << 8; |
| 6463 | // op: Rx32 |
| 6464 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6465 | Value |= (op & 0x1f) << 16; |
| 6466 | break; |
| 6467 | } |
| 6468 | case Hexagon::S2_storerd_pbr: |
| 6469 | case Hexagon::S2_storerd_pcr: |
| 6470 | case Hexagon::S2_storerd_pr: { |
| 6471 | // op: Mu2 |
| 6472 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6473 | Value |= (op & 0x1) << 13; |
| 6474 | // op: Rtt32 |
| 6475 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 6476 | Value |= (op & 0x1f) << 8; |
| 6477 | // op: Rx32 |
| 6478 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6479 | Value |= (op & 0x1f) << 16; |
| 6480 | break; |
| 6481 | } |
| 6482 | case Hexagon::V6_vS32b_srls_ppu: |
| 6483 | case Hexagon::V6_zLd_ppu: { |
| 6484 | // op: Mu2 |
| 6485 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6486 | Value |= (op & 0x1) << 13; |
| 6487 | // op: Rx32 |
| 6488 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6489 | Value |= (op & 0x1f) << 16; |
| 6490 | break; |
| 6491 | } |
| 6492 | case Hexagon::V6_vS32Ub_ppu: |
| 6493 | case Hexagon::V6_vS32b_nt_ppu: |
| 6494 | case Hexagon::V6_vS32b_ppu: { |
| 6495 | // op: Mu2 |
| 6496 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6497 | Value |= (op & 0x1) << 13; |
| 6498 | // op: Vs32 |
| 6499 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 6500 | Value |= (op & 0x1f); |
| 6501 | // op: Rx32 |
| 6502 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6503 | Value |= (op & 0x1f) << 16; |
| 6504 | break; |
| 6505 | } |
| 6506 | case Hexagon::L2_loadbsw2_pbr: |
| 6507 | case Hexagon::L2_loadbsw2_pcr: |
| 6508 | case Hexagon::L2_loadbsw2_pr: |
| 6509 | case Hexagon::L2_loadbzw2_pbr: |
| 6510 | case Hexagon::L2_loadbzw2_pcr: |
| 6511 | case Hexagon::L2_loadbzw2_pr: |
| 6512 | case Hexagon::L2_loadrb_pbr: |
| 6513 | case Hexagon::L2_loadrb_pcr: |
| 6514 | case Hexagon::L2_loadrb_pr: |
| 6515 | case Hexagon::L2_loadrh_pbr: |
| 6516 | case Hexagon::L2_loadrh_pcr: |
| 6517 | case Hexagon::L2_loadrh_pr: |
| 6518 | case Hexagon::L2_loadri_pbr: |
| 6519 | case Hexagon::L2_loadri_pcr: |
| 6520 | case Hexagon::L2_loadri_pr: |
| 6521 | case Hexagon::L2_loadrub_pbr: |
| 6522 | case Hexagon::L2_loadrub_pcr: |
| 6523 | case Hexagon::L2_loadrub_pr: |
| 6524 | case Hexagon::L2_loadruh_pbr: |
| 6525 | case Hexagon::L2_loadruh_pcr: |
| 6526 | case Hexagon::L2_loadruh_pr: { |
| 6527 | // op: Mu2 |
| 6528 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 6529 | Value |= (op & 0x1) << 13; |
| 6530 | // op: Rd32 |
| 6531 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6532 | Value |= (op & 0x1f); |
| 6533 | // op: Rx32 |
| 6534 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6535 | Value |= (op & 0x1f) << 16; |
| 6536 | break; |
| 6537 | } |
| 6538 | case Hexagon::L2_loadbsw4_pbr: |
| 6539 | case Hexagon::L2_loadbsw4_pcr: |
| 6540 | case Hexagon::L2_loadbsw4_pr: |
| 6541 | case Hexagon::L2_loadbzw4_pbr: |
| 6542 | case Hexagon::L2_loadbzw4_pcr: |
| 6543 | case Hexagon::L2_loadbzw4_pr: |
| 6544 | case Hexagon::L2_loadrd_pbr: |
| 6545 | case Hexagon::L2_loadrd_pcr: |
| 6546 | case Hexagon::L2_loadrd_pr: { |
| 6547 | // op: Mu2 |
| 6548 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 6549 | Value |= (op & 0x1) << 13; |
| 6550 | // op: Rdd32 |
| 6551 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6552 | Value |= (op & 0x1f); |
| 6553 | // op: Rx32 |
| 6554 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6555 | Value |= (op & 0x1f) << 16; |
| 6556 | break; |
| 6557 | } |
| 6558 | case Hexagon::V6_vL32Ub_ppu: |
| 6559 | case Hexagon::V6_vL32b_cur_ppu: |
| 6560 | case Hexagon::V6_vL32b_nt_cur_ppu: |
| 6561 | case Hexagon::V6_vL32b_nt_ppu: |
| 6562 | case Hexagon::V6_vL32b_nt_tmp_ppu: |
| 6563 | case Hexagon::V6_vL32b_ppu: |
| 6564 | case Hexagon::V6_vL32b_tmp_ppu: { |
| 6565 | // op: Mu2 |
| 6566 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 6567 | Value |= (op & 0x1) << 13; |
| 6568 | // op: Vd32 |
| 6569 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6570 | Value |= (op & 0x1f); |
| 6571 | // op: Rx32 |
| 6572 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6573 | Value |= (op & 0x1f) << 16; |
| 6574 | break; |
| 6575 | } |
| 6576 | case Hexagon::L2_loadalignb_pbr: |
| 6577 | case Hexagon::L2_loadalignb_pcr: |
| 6578 | case Hexagon::L2_loadalignb_pr: |
| 6579 | case Hexagon::L2_loadalignh_pbr: |
| 6580 | case Hexagon::L2_loadalignh_pcr: |
| 6581 | case Hexagon::L2_loadalignh_pr: { |
| 6582 | // op: Mu2 |
| 6583 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 6584 | Value |= (op & 0x1) << 13; |
| 6585 | // op: Ryy32 |
| 6586 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6587 | Value |= (op & 0x1f); |
| 6588 | // op: Rx32 |
| 6589 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6590 | Value |= (op & 0x1f) << 16; |
| 6591 | break; |
| 6592 | } |
| 6593 | case Hexagon::C2_all8: |
| 6594 | case Hexagon::C2_any8: |
| 6595 | case Hexagon::C2_not: { |
| 6596 | // op: Ps4 |
| 6597 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6598 | Value |= (op & 0x3) << 16; |
| 6599 | // op: Pd4 |
| 6600 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6601 | Value |= (op & 0x3); |
| 6602 | break; |
| 6603 | } |
| 6604 | case Hexagon::C2_xor: |
| 6605 | case Hexagon::C4_fastcorner9: |
| 6606 | case Hexagon::C4_fastcorner9_not: { |
| 6607 | // op: Ps4 |
| 6608 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6609 | Value |= (op & 0x3) << 16; |
| 6610 | // op: Pt4 |
| 6611 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6612 | Value |= (op & 0x3) << 8; |
| 6613 | // op: Pd4 |
| 6614 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6615 | Value |= (op & 0x3); |
| 6616 | break; |
| 6617 | } |
| 6618 | case Hexagon::C4_and_and: |
| 6619 | case Hexagon::C4_and_andn: |
| 6620 | case Hexagon::C4_and_or: |
| 6621 | case Hexagon::C4_and_orn: |
| 6622 | case Hexagon::C4_or_and: |
| 6623 | case Hexagon::C4_or_andn: |
| 6624 | case Hexagon::C4_or_or: |
| 6625 | case Hexagon::C4_or_orn: { |
| 6626 | // op: Ps4 |
| 6627 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6628 | Value |= (op & 0x3) << 16; |
| 6629 | // op: Pt4 |
| 6630 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6631 | Value |= (op & 0x3) << 8; |
| 6632 | // op: Pu4 |
| 6633 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 6634 | Value |= (op & 0x3) << 6; |
| 6635 | // op: Pd4 |
| 6636 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6637 | Value |= (op & 0x3); |
| 6638 | break; |
| 6639 | } |
| 6640 | case Hexagon::C2_vitpack: { |
| 6641 | // op: Ps4 |
| 6642 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6643 | Value |= (op & 0x3) << 16; |
| 6644 | // op: Pt4 |
| 6645 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6646 | Value |= (op & 0x3) << 8; |
| 6647 | // op: Rd32 |
| 6648 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6649 | Value |= (op & 0x1f); |
| 6650 | break; |
| 6651 | } |
| 6652 | case Hexagon::C2_tfrpr: { |
| 6653 | // op: Ps4 |
| 6654 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6655 | Value |= (op & 0x3) << 16; |
| 6656 | // op: Rd32 |
| 6657 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6658 | Value |= (op & 0x1f); |
| 6659 | break; |
| 6660 | } |
| 6661 | case Hexagon::V6_vcmov: |
| 6662 | case Hexagon::V6_vncmov: { |
| 6663 | // op: Ps4 |
| 6664 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6665 | Value |= (op & 0x3) << 5; |
| 6666 | // op: Vu32 |
| 6667 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6668 | Value |= (op & 0x1f) << 8; |
| 6669 | // op: Vd32 |
| 6670 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6671 | Value |= (op & 0x1f); |
| 6672 | break; |
| 6673 | } |
| 6674 | case Hexagon::V6_vccombine: |
| 6675 | case Hexagon::V6_vnccombine: { |
| 6676 | // op: Ps4 |
| 6677 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6678 | Value |= (op & 0x3) << 5; |
| 6679 | // op: Vu32 |
| 6680 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6681 | Value |= (op & 0x1f) << 8; |
| 6682 | // op: Vv32 |
| 6683 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 6684 | Value |= (op & 0x1f) << 16; |
| 6685 | // op: Vdd32 |
| 6686 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6687 | Value |= (op & 0x1f); |
| 6688 | break; |
| 6689 | } |
| 6690 | case Hexagon::Y2_setimask: |
| 6691 | case Hexagon::Y2_setprio: { |
| 6692 | // op: Pt4 |
| 6693 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6694 | Value |= (op & 0x3) << 8; |
| 6695 | // op: Rs32 |
| 6696 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6697 | Value |= (op & 0x1f) << 16; |
| 6698 | break; |
| 6699 | } |
| 6700 | case Hexagon::C2_and: |
| 6701 | case Hexagon::C2_andn: |
| 6702 | case Hexagon::C2_or: |
| 6703 | case Hexagon::C2_orn: { |
| 6704 | // op: Pt4 |
| 6705 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6706 | Value |= (op & 0x3) << 8; |
| 6707 | // op: Ps4 |
| 6708 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6709 | Value |= (op & 0x3) << 16; |
| 6710 | // op: Pd4 |
| 6711 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6712 | Value |= (op & 0x3); |
| 6713 | break; |
| 6714 | } |
| 6715 | case Hexagon::C2_mask: { |
| 6716 | // op: Pt4 |
| 6717 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6718 | Value |= (op & 0x3) << 8; |
| 6719 | // op: Rdd32 |
| 6720 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6721 | Value |= (op & 0x1f); |
| 6722 | break; |
| 6723 | } |
| 6724 | case Hexagon::J2_callrf: |
| 6725 | case Hexagon::J2_callrt: |
| 6726 | case Hexagon::J2_jumprf: |
| 6727 | case Hexagon::J2_jumprfnew: |
| 6728 | case Hexagon::J2_jumprfnewpt: |
| 6729 | case Hexagon::J2_jumprfpt: |
| 6730 | case Hexagon::J2_jumprt: |
| 6731 | case Hexagon::J2_jumprtnew: |
| 6732 | case Hexagon::J2_jumprtnewpt: |
| 6733 | case Hexagon::J2_jumprtpt: { |
| 6734 | // op: Pu4 |
| 6735 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6736 | Value |= (op & 0x3) << 8; |
| 6737 | // op: Rs32 |
| 6738 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6739 | Value |= (op & 0x1f) << 16; |
| 6740 | break; |
| 6741 | } |
| 6742 | case Hexagon::A2_paddf: |
| 6743 | case Hexagon::A2_paddfnew: |
| 6744 | case Hexagon::A2_paddt: |
| 6745 | case Hexagon::A2_paddtnew: |
| 6746 | case Hexagon::A2_pandf: |
| 6747 | case Hexagon::A2_pandfnew: |
| 6748 | case Hexagon::A2_pandt: |
| 6749 | case Hexagon::A2_pandtnew: |
| 6750 | case Hexagon::A2_porf: |
| 6751 | case Hexagon::A2_porfnew: |
| 6752 | case Hexagon::A2_port: |
| 6753 | case Hexagon::A2_portnew: |
| 6754 | case Hexagon::A2_pxorf: |
| 6755 | case Hexagon::A2_pxorfnew: |
| 6756 | case Hexagon::A2_pxort: |
| 6757 | case Hexagon::A2_pxortnew: |
| 6758 | case Hexagon::C2_mux: { |
| 6759 | // op: Pu4 |
| 6760 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6761 | Value |= (op & 0x3) << 5; |
| 6762 | // op: Rs32 |
| 6763 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6764 | Value |= (op & 0x1f) << 16; |
| 6765 | // op: Rt32 |
| 6766 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 6767 | Value |= (op & 0x1f) << 8; |
| 6768 | // op: Rd32 |
| 6769 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6770 | Value |= (op & 0x1f); |
| 6771 | break; |
| 6772 | } |
| 6773 | case Hexagon::C2_ccombinewf: |
| 6774 | case Hexagon::C2_ccombinewnewf: |
| 6775 | case Hexagon::C2_ccombinewnewt: |
| 6776 | case Hexagon::C2_ccombinewt: { |
| 6777 | // op: Pu4 |
| 6778 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6779 | Value |= (op & 0x3) << 5; |
| 6780 | // op: Rs32 |
| 6781 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6782 | Value |= (op & 0x1f) << 16; |
| 6783 | // op: Rt32 |
| 6784 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 6785 | Value |= (op & 0x1f) << 8; |
| 6786 | // op: Rdd32 |
| 6787 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6788 | Value |= (op & 0x1f); |
| 6789 | break; |
| 6790 | } |
| 6791 | case Hexagon::C2_vmux: { |
| 6792 | // op: Pu4 |
| 6793 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6794 | Value |= (op & 0x3) << 5; |
| 6795 | // op: Rss32 |
| 6796 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6797 | Value |= (op & 0x1f) << 16; |
| 6798 | // op: Rtt32 |
| 6799 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 6800 | Value |= (op & 0x1f) << 8; |
| 6801 | // op: Rdd32 |
| 6802 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6803 | Value |= (op & 0x1f); |
| 6804 | break; |
| 6805 | } |
| 6806 | case Hexagon::A2_psubf: |
| 6807 | case Hexagon::A2_psubfnew: |
| 6808 | case Hexagon::A2_psubt: |
| 6809 | case Hexagon::A2_psubtnew: { |
| 6810 | // op: Pu4 |
| 6811 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6812 | Value |= (op & 0x3) << 5; |
| 6813 | // op: Rt32 |
| 6814 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6815 | Value |= (op & 0x1f) << 8; |
| 6816 | // op: Rs32 |
| 6817 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 6818 | Value |= (op & 0x1f) << 16; |
| 6819 | // op: Rd32 |
| 6820 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6821 | Value |= (op & 0x1f); |
| 6822 | break; |
| 6823 | } |
| 6824 | case Hexagon::A4_paslhf: |
| 6825 | case Hexagon::A4_paslhfnew: |
| 6826 | case Hexagon::A4_paslht: |
| 6827 | case Hexagon::A4_paslhtnew: |
| 6828 | case Hexagon::A4_pasrhf: |
| 6829 | case Hexagon::A4_pasrhfnew: |
| 6830 | case Hexagon::A4_pasrht: |
| 6831 | case Hexagon::A4_pasrhtnew: |
| 6832 | case Hexagon::A4_psxtbf: |
| 6833 | case Hexagon::A4_psxtbfnew: |
| 6834 | case Hexagon::A4_psxtbt: |
| 6835 | case Hexagon::A4_psxtbtnew: |
| 6836 | case Hexagon::A4_psxthf: |
| 6837 | case Hexagon::A4_psxthfnew: |
| 6838 | case Hexagon::A4_psxtht: |
| 6839 | case Hexagon::A4_psxthtnew: |
| 6840 | case Hexagon::A4_pzxtbf: |
| 6841 | case Hexagon::A4_pzxtbfnew: |
| 6842 | case Hexagon::A4_pzxtbt: |
| 6843 | case Hexagon::A4_pzxtbtnew: |
| 6844 | case Hexagon::A4_pzxthf: |
| 6845 | case Hexagon::A4_pzxthfnew: |
| 6846 | case Hexagon::A4_pzxtht: |
| 6847 | case Hexagon::A4_pzxthtnew: { |
| 6848 | // op: Pu4 |
| 6849 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6850 | Value |= (op & 0x3) << 8; |
| 6851 | // op: Rs32 |
| 6852 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6853 | Value |= (op & 0x1f) << 16; |
| 6854 | // op: Rd32 |
| 6855 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6856 | Value |= (op & 0x1f); |
| 6857 | break; |
| 6858 | } |
| 6859 | case Hexagon::V6_vS32b_new_npred_ppu: |
| 6860 | case Hexagon::V6_vS32b_new_pred_ppu: |
| 6861 | case Hexagon::V6_vS32b_nt_new_npred_ppu: |
| 6862 | case Hexagon::V6_vS32b_nt_new_pred_ppu: { |
| 6863 | // op: Pv4 |
| 6864 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6865 | Value |= (op & 0x3) << 11; |
| 6866 | // op: Mu2 |
| 6867 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 6868 | Value |= (op & 0x1) << 13; |
| 6869 | // op: Os8 |
| 6870 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 6871 | Value |= (op & 0x7); |
| 6872 | // op: Rx32 |
| 6873 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6874 | Value |= (op & 0x1f) << 16; |
| 6875 | break; |
| 6876 | } |
| 6877 | case Hexagon::V6_zLd_pred_ppu: { |
| 6878 | // op: Pv4 |
| 6879 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6880 | Value |= (op & 0x3) << 11; |
| 6881 | // op: Mu2 |
| 6882 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 6883 | Value |= (op & 0x1) << 13; |
| 6884 | // op: Rx32 |
| 6885 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6886 | Value |= (op & 0x1f) << 16; |
| 6887 | break; |
| 6888 | } |
| 6889 | case Hexagon::V6_vS32Ub_npred_ppu: |
| 6890 | case Hexagon::V6_vS32Ub_pred_ppu: |
| 6891 | case Hexagon::V6_vS32b_npred_ppu: |
| 6892 | case Hexagon::V6_vS32b_nt_npred_ppu: |
| 6893 | case Hexagon::V6_vS32b_nt_pred_ppu: |
| 6894 | case Hexagon::V6_vS32b_pred_ppu: { |
| 6895 | // op: Pv4 |
| 6896 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6897 | Value |= (op & 0x3) << 11; |
| 6898 | // op: Mu2 |
| 6899 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 6900 | Value |= (op & 0x1) << 13; |
| 6901 | // op: Vs32 |
| 6902 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 6903 | Value |= (op & 0x1f); |
| 6904 | // op: Rx32 |
| 6905 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6906 | Value |= (op & 0x1f) << 16; |
| 6907 | break; |
| 6908 | } |
| 6909 | case Hexagon::L4_return_f: |
| 6910 | case Hexagon::L4_return_fnew_pnt: |
| 6911 | case Hexagon::L4_return_fnew_pt: |
| 6912 | case Hexagon::L4_return_t: |
| 6913 | case Hexagon::L4_return_tnew_pnt: |
| 6914 | case Hexagon::L4_return_tnew_pt: { |
| 6915 | // op: Pv4 |
| 6916 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6917 | Value |= (op & 0x3) << 8; |
| 6918 | // op: Rs32 |
| 6919 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6920 | Value |= (op & 0x1f) << 16; |
| 6921 | // op: Rdd32 |
| 6922 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6923 | Value |= (op & 0x1f); |
| 6924 | break; |
| 6925 | } |
| 6926 | case Hexagon::V6_vL32b_cur_npred_ppu: |
| 6927 | case Hexagon::V6_vL32b_cur_pred_ppu: |
| 6928 | case Hexagon::V6_vL32b_npred_ppu: |
| 6929 | case Hexagon::V6_vL32b_nt_cur_npred_ppu: |
| 6930 | case Hexagon::V6_vL32b_nt_cur_pred_ppu: |
| 6931 | case Hexagon::V6_vL32b_nt_npred_ppu: |
| 6932 | case Hexagon::V6_vL32b_nt_pred_ppu: |
| 6933 | case Hexagon::V6_vL32b_nt_tmp_npred_ppu: |
| 6934 | case Hexagon::V6_vL32b_nt_tmp_pred_ppu: |
| 6935 | case Hexagon::V6_vL32b_pred_ppu: |
| 6936 | case Hexagon::V6_vL32b_tmp_npred_ppu: |
| 6937 | case Hexagon::V6_vL32b_tmp_pred_ppu: { |
| 6938 | // op: Pv4 |
| 6939 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6940 | Value |= (op & 0x3) << 11; |
| 6941 | // op: Mu2 |
| 6942 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 6943 | Value |= (op & 0x1) << 13; |
| 6944 | // op: Vd32 |
| 6945 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6946 | Value |= (op & 0x1f); |
| 6947 | // op: Rx32 |
| 6948 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6949 | Value |= (op & 0x1f) << 16; |
| 6950 | break; |
| 6951 | } |
| 6952 | case Hexagon::V6_vscattermhq: |
| 6953 | case Hexagon::V6_vscattermwq: { |
| 6954 | // op: Qs4 |
| 6955 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6956 | Value |= (op & 0x3) << 5; |
| 6957 | // op: Rt32 |
| 6958 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6959 | Value |= (op & 0x1f) << 16; |
| 6960 | // op: Mu2 |
| 6961 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6962 | Value |= (op & 0x1) << 13; |
| 6963 | // op: Vv32 |
| 6964 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 6965 | Value |= (op & 0x1f) << 8; |
| 6966 | // op: Vw32 |
| 6967 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 6968 | Value |= (op & 0x1f); |
| 6969 | break; |
| 6970 | } |
| 6971 | case Hexagon::V6_vgathermhq: |
| 6972 | case Hexagon::V6_vgathermwq: { |
| 6973 | // op: Qs4 |
| 6974 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6975 | Value |= (op & 0x3) << 5; |
| 6976 | // op: Rt32 |
| 6977 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6978 | Value |= (op & 0x1f) << 16; |
| 6979 | // op: Mu2 |
| 6980 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6981 | Value |= (op & 0x1) << 13; |
| 6982 | // op: Vv32 |
| 6983 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 6984 | Value |= (op & 0x1f); |
| 6985 | break; |
| 6986 | } |
| 6987 | case Hexagon::V6_vscattermhwq: { |
| 6988 | // op: Qs4 |
| 6989 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 6990 | Value |= (op & 0x3) << 5; |
| 6991 | // op: Rt32 |
| 6992 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 6993 | Value |= (op & 0x1f) << 16; |
| 6994 | // op: Mu2 |
| 6995 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 6996 | Value |= (op & 0x1) << 13; |
| 6997 | // op: Vvv32 |
| 6998 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 6999 | Value |= (op & 0x1f) << 8; |
| 7000 | // op: Vw32 |
| 7001 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 7002 | Value |= (op & 0x1f); |
| 7003 | break; |
| 7004 | } |
| 7005 | case Hexagon::V6_vgathermhwq: { |
| 7006 | // op: Qs4 |
| 7007 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7008 | Value |= (op & 0x3) << 5; |
| 7009 | // op: Rt32 |
| 7010 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 7011 | Value |= (op & 0x1f) << 16; |
| 7012 | // op: Mu2 |
| 7013 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 7014 | Value |= (op & 0x1) << 13; |
| 7015 | // op: Vvv32 |
| 7016 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 7017 | Value |= (op & 0x1f); |
| 7018 | break; |
| 7019 | } |
| 7020 | case Hexagon::V6_pred_not: { |
| 7021 | // op: Qs4 |
| 7022 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 7023 | Value |= (op & 0x3) << 8; |
| 7024 | // op: Qd4 |
| 7025 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7026 | Value |= (op & 0x3); |
| 7027 | break; |
| 7028 | } |
| 7029 | case Hexagon::V6_pred_and: |
| 7030 | case Hexagon::V6_pred_and_n: |
| 7031 | case Hexagon::V6_pred_or: |
| 7032 | case Hexagon::V6_pred_or_n: |
| 7033 | case Hexagon::V6_pred_xor: |
| 7034 | case Hexagon::V6_shuffeqh: |
| 7035 | case Hexagon::V6_shuffeqw: { |
| 7036 | // op: Qs4 |
| 7037 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 7038 | Value |= (op & 0x3) << 8; |
| 7039 | // op: Qt4 |
| 7040 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 7041 | Value |= (op & 0x3) << 22; |
| 7042 | // op: Qd4 |
| 7043 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7044 | Value |= (op & 0x3); |
| 7045 | break; |
| 7046 | } |
| 7047 | case Hexagon::V6_vmux: { |
| 7048 | // op: Qt4 |
| 7049 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 7050 | Value |= (op & 0x3) << 5; |
| 7051 | // op: Vu32 |
| 7052 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 7053 | Value |= (op & 0x1f) << 8; |
| 7054 | // op: Vv32 |
| 7055 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 7056 | Value |= (op & 0x1f) << 16; |
| 7057 | // op: Vd32 |
| 7058 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7059 | Value |= (op & 0x1f); |
| 7060 | break; |
| 7061 | } |
| 7062 | case Hexagon::V6_vswap: { |
| 7063 | // op: Qt4 |
| 7064 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 7065 | Value |= (op & 0x3) << 5; |
| 7066 | // op: Vu32 |
| 7067 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 7068 | Value |= (op & 0x1f) << 8; |
| 7069 | // op: Vv32 |
| 7070 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 7071 | Value |= (op & 0x1f) << 16; |
| 7072 | // op: Vdd32 |
| 7073 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7074 | Value |= (op & 0x1f); |
| 7075 | break; |
| 7076 | } |
| 7077 | case Hexagon::V6_vandnqrt: |
| 7078 | case Hexagon::V6_vandqrt: { |
| 7079 | // op: Qu4 |
| 7080 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 7081 | Value |= (op & 0x3) << 8; |
| 7082 | // op: Rt32 |
| 7083 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 7084 | Value |= (op & 0x1f) << 16; |
| 7085 | // op: Vd32 |
| 7086 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7087 | Value |= (op & 0x1f); |
| 7088 | break; |
| 7089 | } |
| 7090 | case Hexagon::V6_vandnqrt_acc: |
| 7091 | case Hexagon::V6_vandqrt_acc: { |
| 7092 | // op: Qu4 |
| 7093 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 7094 | Value |= (op & 0x3) << 8; |
| 7095 | // op: Rt32 |
| 7096 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 7097 | Value |= (op & 0x1f) << 16; |
| 7098 | // op: Vx32 |
| 7099 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7100 | Value |= (op & 0x1f); |
| 7101 | break; |
| 7102 | } |
| 7103 | case Hexagon::V6_vhistq: |
| 7104 | case Hexagon::V6_vwhist128q: |
| 7105 | case Hexagon::V6_vwhist256q: |
| 7106 | case Hexagon::V6_vwhist256q_sat: { |
| 7107 | // op: Qv4 |
| 7108 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7109 | Value |= (op & 0x3) << 22; |
| 7110 | break; |
| 7111 | } |
| 7112 | case Hexagon::V6_vS32b_nqpred_ppu: |
| 7113 | case Hexagon::V6_vS32b_nt_nqpred_ppu: |
| 7114 | case Hexagon::V6_vS32b_nt_qpred_ppu: |
| 7115 | case Hexagon::V6_vS32b_qpred_ppu: { |
| 7116 | // op: Qv4 |
| 7117 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 7118 | Value |= (op & 0x3) << 11; |
| 7119 | // op: Mu2 |
| 7120 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 7121 | Value |= (op & 0x1) << 13; |
| 7122 | // op: Vs32 |
| 7123 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 7124 | Value |= (op & 0x1f); |
| 7125 | // op: Rx32 |
| 7126 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7127 | Value |= (op & 0x1f) << 16; |
| 7128 | break; |
| 7129 | } |
| 7130 | case Hexagon::V6_vprefixqb: |
| 7131 | case Hexagon::V6_vprefixqh: |
| 7132 | case Hexagon::V6_vprefixqw: { |
| 7133 | // op: Qv4 |
| 7134 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 7135 | Value |= (op & 0x3) << 22; |
| 7136 | // op: Vd32 |
| 7137 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7138 | Value |= (op & 0x1f); |
| 7139 | break; |
| 7140 | } |
| 7141 | case Hexagon::V6_vandvnqv: |
| 7142 | case Hexagon::V6_vandvqv: { |
| 7143 | // op: Qv4 |
| 7144 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 7145 | Value |= (op & 0x3) << 22; |
| 7146 | // op: Vu32 |
| 7147 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 7148 | Value |= (op & 0x1f) << 8; |
| 7149 | // op: Vd32 |
| 7150 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7151 | Value |= (op & 0x1f); |
| 7152 | break; |
| 7153 | } |
| 7154 | case Hexagon::V6_vaddbnq: |
| 7155 | case Hexagon::V6_vaddbq: |
| 7156 | case Hexagon::V6_vaddhnq: |
| 7157 | case Hexagon::V6_vaddhq: |
| 7158 | case Hexagon::V6_vaddwnq: |
| 7159 | case Hexagon::V6_vaddwq: |
| 7160 | case Hexagon::V6_vsubbnq: |
| 7161 | case Hexagon::V6_vsubbq: |
| 7162 | case Hexagon::V6_vsubhnq: |
| 7163 | case Hexagon::V6_vsubhq: |
| 7164 | case Hexagon::V6_vsubwnq: |
| 7165 | case Hexagon::V6_vsubwq: { |
| 7166 | // op: Qv4 |
| 7167 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 7168 | Value |= (op & 0x3) << 22; |
| 7169 | // op: Vu32 |
| 7170 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 7171 | Value |= (op & 0x1f) << 8; |
| 7172 | // op: Vx32 |
| 7173 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7174 | Value |= (op & 0x1f); |
| 7175 | break; |
| 7176 | } |
| 7177 | case Hexagon::SA1_clrf: |
| 7178 | case Hexagon::SA1_clrfnew: |
| 7179 | case Hexagon::SA1_clrt: |
| 7180 | case Hexagon::SA1_clrtnew: |
| 7181 | case Hexagon::SA1_setin1: { |
| 7182 | // op: Rd16 |
| 7183 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7184 | Value |= (op & 0xf); |
| 7185 | break; |
| 7186 | } |
| 7187 | case Hexagon::Y6_dmpause: |
| 7188 | case Hexagon::Y6_dmpoll: |
| 7189 | case Hexagon::Y6_dmwait: { |
| 7190 | // op: Rd32 |
| 7191 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7192 | Value |= (op & 0x1f); |
| 7193 | break; |
| 7194 | } |
| 7195 | case Hexagon::PS_callr_nr: { |
| 7196 | // op: Rs |
| 7197 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7198 | Value |= (op & 0x1f) << 16; |
| 7199 | break; |
| 7200 | } |
| 7201 | case Hexagon::SA1_and1: |
| 7202 | case Hexagon::SA1_dec: |
| 7203 | case Hexagon::SA1_inc: |
| 7204 | case Hexagon::SA1_sxtb: |
| 7205 | case Hexagon::SA1_sxth: |
| 7206 | case Hexagon::SA1_tfr: |
| 7207 | case Hexagon::SA1_zxtb: |
| 7208 | case Hexagon::SA1_zxth: { |
| 7209 | // op: Rs16 |
| 7210 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 7211 | Value |= (op & 0xf) << 4; |
| 7212 | // op: Rd16 |
| 7213 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7214 | Value |= (op & 0xf); |
| 7215 | break; |
| 7216 | } |
| 7217 | case Hexagon::SA1_combinerz: |
| 7218 | case Hexagon::SA1_combinezr: { |
| 7219 | // op: Rs16 |
| 7220 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 7221 | Value |= (op & 0xf) << 4; |
| 7222 | // op: Rdd8 |
| 7223 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7224 | Value |= (op & 0x7); |
| 7225 | break; |
| 7226 | } |
| 7227 | case Hexagon::SA1_addrx: { |
| 7228 | // op: Rs16 |
| 7229 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 7230 | Value |= (op & 0xf) << 4; |
| 7231 | // op: Rx16 |
| 7232 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7233 | Value |= (op & 0xf); |
| 7234 | break; |
| 7235 | } |
| 7236 | case Hexagon::J2_callr: |
| 7237 | case Hexagon::J2_callrh: |
| 7238 | case Hexagon::J2_jumpr: |
| 7239 | case Hexagon::J2_jumprh: |
| 7240 | case Hexagon::J4_hintjumpr: |
| 7241 | case Hexagon::R6_release_at_vi: |
| 7242 | case Hexagon::R6_release_st_vi: |
| 7243 | case Hexagon::Y2_ciad: |
| 7244 | case Hexagon::Y2_cswi: |
| 7245 | case Hexagon::Y2_dccleana: |
| 7246 | case Hexagon::Y2_dccleanidx: |
| 7247 | case Hexagon::Y2_dccleaninva: |
| 7248 | case Hexagon::Y2_dccleaninvidx: |
| 7249 | case Hexagon::Y2_dcinva: |
| 7250 | case Hexagon::Y2_dcinvidx: |
| 7251 | case Hexagon::Y2_dczeroa: |
| 7252 | case Hexagon::Y2_iassignw: |
| 7253 | case Hexagon::Y2_icinva: |
| 7254 | case Hexagon::Y2_icinvidx: |
| 7255 | case Hexagon::Y2_l2cleaninvidx: |
| 7256 | case Hexagon::Y2_resume: |
| 7257 | case Hexagon::Y2_start: |
| 7258 | case Hexagon::Y2_stop: |
| 7259 | case Hexagon::Y2_swi: |
| 7260 | case Hexagon::Y2_wait: |
| 7261 | case Hexagon::Y4_nmi: |
| 7262 | case Hexagon::Y4_siad: |
| 7263 | case Hexagon::Y4_trace: |
| 7264 | case Hexagon::Y5_l2cleanidx: |
| 7265 | case Hexagon::Y5_l2invidx: |
| 7266 | case Hexagon::Y5_l2unlocka: |
| 7267 | case Hexagon::Y5_tlbasidi: |
| 7268 | case Hexagon::Y6_diag: |
| 7269 | case Hexagon::Y6_dmresume: |
| 7270 | case Hexagon::Y6_dmstart: { |
| 7271 | // op: Rs32 |
| 7272 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7273 | Value |= (op & 0x1f) << 16; |
| 7274 | break; |
| 7275 | } |
| 7276 | case Hexagon::S2_storew_rl_at_vi: |
| 7277 | case Hexagon::S2_storew_rl_st_vi: |
| 7278 | case Hexagon::Y2_dctagw: |
| 7279 | case Hexagon::Y2_icdataw: |
| 7280 | case Hexagon::Y2_ictagw: |
| 7281 | case Hexagon::Y4_l2fetch: |
| 7282 | case Hexagon::Y4_l2tagw: |
| 7283 | case Hexagon::Y6_dmlink: { |
| 7284 | // op: Rs32 |
| 7285 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7286 | Value |= (op & 0x1f) << 16; |
| 7287 | // op: Rt32 |
| 7288 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 7289 | Value |= (op & 0x1f) << 8; |
| 7290 | break; |
| 7291 | } |
| 7292 | case Hexagon::L6_memcpy: { |
| 7293 | // op: Rs32 |
| 7294 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7295 | Value |= (op & 0x1f) << 16; |
| 7296 | // op: Rt32 |
| 7297 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 7298 | Value |= (op & 0x1f) << 8; |
| 7299 | // op: Mu2 |
| 7300 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 7301 | Value |= (op & 0x1) << 13; |
| 7302 | break; |
| 7303 | } |
| 7304 | case Hexagon::S4_stored_rl_at_vi: |
| 7305 | case Hexagon::S4_stored_rl_st_vi: |
| 7306 | case Hexagon::Y5_l2fetch: { |
| 7307 | // op: Rs32 |
| 7308 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7309 | Value |= (op & 0x1f) << 16; |
| 7310 | // op: Rtt32 |
| 7311 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 7312 | Value |= (op & 0x1f) << 8; |
| 7313 | break; |
| 7314 | } |
| 7315 | case Hexagon::A2_tfrrcr: { |
| 7316 | // op: Rs32 |
| 7317 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 7318 | Value |= (op & 0x1f) << 16; |
| 7319 | // op: Cd32 |
| 7320 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7321 | Value |= (op & 0x1f); |
| 7322 | break; |
| 7323 | } |
| 7324 | case Hexagon::G4_tfrgrcr: { |
| 7325 | // op: Rs32 |
| 7326 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 7327 | Value |= (op & 0x1f) << 16; |
| 7328 | // op: Gd32 |
| 7329 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7330 | Value |= (op & 0x1f); |
| 7331 | break; |
| 7332 | } |
| 7333 | case Hexagon::C2_tfrrp: |
| 7334 | case Hexagon::Y5_l2locka: { |
| 7335 | // op: Rs32 |
| 7336 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 7337 | Value |= (op & 0x1f) << 16; |
| 7338 | // op: Pd4 |
| 7339 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7340 | Value |= (op & 0x3); |
| 7341 | break; |
| 7342 | } |
| 7343 | case Hexagon::A2_abs: |
| 7344 | case Hexagon::A2_abssat: |
| 7345 | case Hexagon::A2_aslh: |
| 7346 | case Hexagon::A2_asrh: |
| 7347 | case Hexagon::A2_negsat: |
| 7348 | case Hexagon::A2_satb: |
| 7349 | case Hexagon::A2_sath: |
| 7350 | case Hexagon::A2_satub: |
| 7351 | case Hexagon::A2_satuh: |
| 7352 | case Hexagon::A2_swiz: |
| 7353 | case Hexagon::A2_sxtb: |
| 7354 | case Hexagon::A2_sxth: |
| 7355 | case Hexagon::A2_tfr: |
| 7356 | case Hexagon::A2_zxth: |
| 7357 | case Hexagon::F2_conv_sf2uw: |
| 7358 | case Hexagon::F2_conv_sf2uw_chop: |
| 7359 | case Hexagon::F2_conv_sf2w: |
| 7360 | case Hexagon::F2_conv_sf2w_chop: |
| 7361 | case Hexagon::F2_conv_uw2sf: |
| 7362 | case Hexagon::F2_conv_w2sf: |
| 7363 | case Hexagon::F2_sffixupr: |
| 7364 | case Hexagon::L2_loadw_aq: |
| 7365 | case Hexagon::L2_loadw_locked: |
| 7366 | case Hexagon::S2_brev: |
| 7367 | case Hexagon::S2_cl0: |
| 7368 | case Hexagon::S2_cl1: |
| 7369 | case Hexagon::S2_clb: |
| 7370 | case Hexagon::S2_clbnorm: |
| 7371 | case Hexagon::S2_ct0: |
| 7372 | case Hexagon::S2_ct1: |
| 7373 | case Hexagon::S2_svsathb: |
| 7374 | case Hexagon::S2_svsathub: |
| 7375 | case Hexagon::S2_vsplatrb: |
| 7376 | case Hexagon::Y2_dctagr: |
| 7377 | case Hexagon::Y2_getimask: |
| 7378 | case Hexagon::Y2_iassignr: |
| 7379 | case Hexagon::Y2_icdatar: |
| 7380 | case Hexagon::Y2_ictagr: |
| 7381 | case Hexagon::Y2_tlbp: |
| 7382 | case Hexagon::Y4_l2tagr: { |
| 7383 | // op: Rs32 |
| 7384 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 7385 | Value |= (op & 0x1f) << 16; |
| 7386 | // op: Rd32 |
| 7387 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7388 | Value |= (op & 0x1f); |
| 7389 | break; |
| 7390 | } |
| 7391 | case Hexagon::A2_sxtw: |
| 7392 | case Hexagon::F2_conv_sf2d: |
| 7393 | case Hexagon::F2_conv_sf2d_chop: |
| 7394 | case Hexagon::F2_conv_sf2df: |
| 7395 | case Hexagon::F2_conv_sf2ud: |
| 7396 | case Hexagon::F2_conv_sf2ud_chop: |
| 7397 | case Hexagon::F2_conv_uw2df: |
| 7398 | case Hexagon::F2_conv_w2df: |
| 7399 | case Hexagon::L2_deallocframe: |
| 7400 | case Hexagon::L4_loadd_aq: |
| 7401 | case Hexagon::L4_loadd_locked: |
| 7402 | case Hexagon::L4_return: |
| 7403 | case Hexagon::S2_vsplatrh: |
| 7404 | case Hexagon::S2_vsxtbh: |
| 7405 | case Hexagon::S2_vsxthw: |
| 7406 | case Hexagon::S2_vzxtbh: |
| 7407 | case Hexagon::S2_vzxthw: |
| 7408 | case Hexagon::S6_vsplatrbp: |
| 7409 | case Hexagon::Y2_tlbr: { |
| 7410 | // op: Rs32 |
| 7411 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 7412 | Value |= (op & 0x1f) << 16; |
| 7413 | // op: Rdd32 |
| 7414 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7415 | Value |= (op & 0x1f); |
| 7416 | break; |
| 7417 | } |
| 7418 | case Hexagon::A4_cmpbeq: |
| 7419 | case Hexagon::A4_cmpbgt: |
| 7420 | case Hexagon::A4_cmpbgtu: |
| 7421 | case Hexagon::A4_cmpheq: |
| 7422 | case Hexagon::A4_cmphgt: |
| 7423 | case Hexagon::A4_cmphgtu: |
| 7424 | case Hexagon::C2_bitsclr: |
| 7425 | case Hexagon::C2_bitsset: |
| 7426 | case Hexagon::C2_cmpeq: |
| 7427 | case Hexagon::C2_cmpgt: |
| 7428 | case Hexagon::C2_cmpgtu: |
| 7429 | case Hexagon::C4_cmplte: |
| 7430 | case Hexagon::C4_cmplteu: |
| 7431 | case Hexagon::C4_cmpneq: |
| 7432 | case Hexagon::C4_nbitsclr: |
| 7433 | case Hexagon::C4_nbitsset: |
| 7434 | case Hexagon::F2_sfcmpeq: |
| 7435 | case Hexagon::F2_sfcmpge: |
| 7436 | case Hexagon::F2_sfcmpgt: |
| 7437 | case Hexagon::F2_sfcmpuo: |
| 7438 | case Hexagon::S2_storew_locked: |
| 7439 | case Hexagon::S2_tstbit_r: |
| 7440 | case Hexagon::S4_ntstbit_r: { |
| 7441 | // op: Rs32 |
| 7442 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 7443 | Value |= (op & 0x1f) << 16; |
| 7444 | // op: Rt32 |
| 7445 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 7446 | Value |= (op & 0x1f) << 8; |
| 7447 | // op: Pd4 |
| 7448 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7449 | Value |= (op & 0x3); |
| 7450 | break; |
| 7451 | } |
| 7452 | case Hexagon::A2_add: |
| 7453 | case Hexagon::A2_addsat: |
| 7454 | case Hexagon::A2_and: |
| 7455 | case Hexagon::A2_max: |
| 7456 | case Hexagon::A2_maxu: |
| 7457 | case Hexagon::A2_or: |
| 7458 | case Hexagon::A2_svaddh: |
| 7459 | case Hexagon::A2_svaddhs: |
| 7460 | case Hexagon::A2_svadduhs: |
| 7461 | case Hexagon::A2_svavgh: |
| 7462 | case Hexagon::A2_svavghs: |
| 7463 | case Hexagon::A2_xor: |
| 7464 | case Hexagon::A4_cround_rr: |
| 7465 | case Hexagon::A4_modwrapu: |
| 7466 | case Hexagon::A4_rcmpeq: |
| 7467 | case Hexagon::A4_rcmpneq: |
| 7468 | case Hexagon::A4_round_rr: |
| 7469 | case Hexagon::A4_round_rr_sat: |
| 7470 | case Hexagon::F2_sfadd: |
| 7471 | case Hexagon::F2_sffixupd: |
| 7472 | case Hexagon::F2_sffixupn: |
| 7473 | case Hexagon::F2_sfmax: |
| 7474 | case Hexagon::F2_sfmin: |
| 7475 | case Hexagon::F2_sfmpy: |
| 7476 | case Hexagon::F2_sfsub: |
| 7477 | case Hexagon::L4_loadw_phys: |
| 7478 | case Hexagon::M2_cmpyrs_s0: |
| 7479 | case Hexagon::M2_cmpyrs_s1: |
| 7480 | case Hexagon::M2_cmpyrsc_s0: |
| 7481 | case Hexagon::M2_cmpyrsc_s1: |
| 7482 | case Hexagon::M2_dpmpyss_rnd_s0: |
| 7483 | case Hexagon::M2_hmmpyh_rs1: |
| 7484 | case Hexagon::M2_hmmpyh_s1: |
| 7485 | case Hexagon::M2_hmmpyl_rs1: |
| 7486 | case Hexagon::M2_hmmpyl_s1: |
| 7487 | case Hexagon::M2_mpy_hh_s0: |
| 7488 | case Hexagon::M2_mpy_hh_s1: |
| 7489 | case Hexagon::M2_mpy_hl_s0: |
| 7490 | case Hexagon::M2_mpy_hl_s1: |
| 7491 | case Hexagon::M2_mpy_lh_s0: |
| 7492 | case Hexagon::M2_mpy_lh_s1: |
| 7493 | case Hexagon::M2_mpy_ll_s0: |
| 7494 | case Hexagon::M2_mpy_ll_s1: |
| 7495 | case Hexagon::M2_mpy_rnd_hh_s0: |
| 7496 | case Hexagon::M2_mpy_rnd_hh_s1: |
| 7497 | case Hexagon::M2_mpy_rnd_hl_s0: |
| 7498 | case Hexagon::M2_mpy_rnd_hl_s1: |
| 7499 | case Hexagon::M2_mpy_rnd_lh_s0: |
| 7500 | case Hexagon::M2_mpy_rnd_lh_s1: |
| 7501 | case Hexagon::M2_mpy_rnd_ll_s0: |
| 7502 | case Hexagon::M2_mpy_rnd_ll_s1: |
| 7503 | case Hexagon::M2_mpy_sat_hh_s0: |
| 7504 | case Hexagon::M2_mpy_sat_hh_s1: |
| 7505 | case Hexagon::M2_mpy_sat_hl_s0: |
| 7506 | case Hexagon::M2_mpy_sat_hl_s1: |
| 7507 | case Hexagon::M2_mpy_sat_lh_s0: |
| 7508 | case Hexagon::M2_mpy_sat_lh_s1: |
| 7509 | case Hexagon::M2_mpy_sat_ll_s0: |
| 7510 | case Hexagon::M2_mpy_sat_ll_s1: |
| 7511 | case Hexagon::M2_mpy_sat_rnd_hh_s0: |
| 7512 | case Hexagon::M2_mpy_sat_rnd_hh_s1: |
| 7513 | case Hexagon::M2_mpy_sat_rnd_hl_s0: |
| 7514 | case Hexagon::M2_mpy_sat_rnd_hl_s1: |
| 7515 | case Hexagon::M2_mpy_sat_rnd_lh_s0: |
| 7516 | case Hexagon::M2_mpy_sat_rnd_lh_s1: |
| 7517 | case Hexagon::M2_mpy_sat_rnd_ll_s0: |
| 7518 | case Hexagon::M2_mpy_sat_rnd_ll_s1: |
| 7519 | case Hexagon::M2_mpy_up: |
| 7520 | case Hexagon::M2_mpy_up_s1: |
| 7521 | case Hexagon::M2_mpy_up_s1_sat: |
| 7522 | case Hexagon::M2_mpyi: |
| 7523 | case Hexagon::M2_mpysu_up: |
| 7524 | case Hexagon::M2_mpyu_hh_s0: |
| 7525 | case Hexagon::M2_mpyu_hh_s1: |
| 7526 | case Hexagon::M2_mpyu_hl_s0: |
| 7527 | case Hexagon::M2_mpyu_hl_s1: |
| 7528 | case Hexagon::M2_mpyu_lh_s0: |
| 7529 | case Hexagon::M2_mpyu_lh_s1: |
| 7530 | case Hexagon::M2_mpyu_ll_s0: |
| 7531 | case Hexagon::M2_mpyu_ll_s1: |
| 7532 | case Hexagon::M2_mpyu_up: |
| 7533 | case Hexagon::M2_vmpy2s_s0pack: |
| 7534 | case Hexagon::M2_vmpy2s_s1pack: |
| 7535 | case Hexagon::S2_asl_r_r: |
| 7536 | case Hexagon::S2_asl_r_r_sat: |
| 7537 | case Hexagon::S2_asr_r_r: |
| 7538 | case Hexagon::S2_asr_r_r_sat: |
| 7539 | case Hexagon::S2_clrbit_r: |
| 7540 | case Hexagon::S2_lsl_r_r: |
| 7541 | case Hexagon::S2_lsr_r_r: |
| 7542 | case Hexagon::S2_setbit_r: |
| 7543 | case Hexagon::S2_togglebit_r: |
| 7544 | case Hexagon::S4_parity: |
| 7545 | case Hexagon::dep_A2_addsat: { |
| 7546 | // op: Rs32 |
| 7547 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 7548 | Value |= (op & 0x1f) << 16; |
| 7549 | // op: Rt32 |
| 7550 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 7551 | Value |= (op & 0x1f) << 8; |
| 7552 | // op: Rd32 |
| 7553 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7554 | Value |= (op & 0x1f); |
| 7555 | break; |
| 7556 | } |
| 7557 | case Hexagon::A2_combinew: |
| 7558 | case Hexagon::A4_bitsplit: |
| 7559 | case Hexagon::M2_cmpyi_s0: |
| 7560 | case Hexagon::M2_cmpyr_s0: |
| 7561 | case Hexagon::M2_cmpys_s0: |
| 7562 | case Hexagon::M2_cmpys_s1: |
| 7563 | case Hexagon::M2_cmpysc_s0: |
| 7564 | case Hexagon::M2_cmpysc_s1: |
| 7565 | case Hexagon::M2_dpmpyss_s0: |
| 7566 | case Hexagon::M2_dpmpyuu_s0: |
| 7567 | case Hexagon::M2_mpyd_hh_s0: |
| 7568 | case Hexagon::M2_mpyd_hh_s1: |
| 7569 | case Hexagon::M2_mpyd_hl_s0: |
| 7570 | case Hexagon::M2_mpyd_hl_s1: |
| 7571 | case Hexagon::M2_mpyd_lh_s0: |
| 7572 | case Hexagon::M2_mpyd_lh_s1: |
| 7573 | case Hexagon::M2_mpyd_ll_s0: |
| 7574 | case Hexagon::M2_mpyd_ll_s1: |
| 7575 | case Hexagon::M2_mpyd_rnd_hh_s0: |
| 7576 | case Hexagon::M2_mpyd_rnd_hh_s1: |
| 7577 | case Hexagon::M2_mpyd_rnd_hl_s0: |
| 7578 | case Hexagon::M2_mpyd_rnd_hl_s1: |
| 7579 | case Hexagon::M2_mpyd_rnd_lh_s0: |
| 7580 | case Hexagon::M2_mpyd_rnd_lh_s1: |
| 7581 | case Hexagon::M2_mpyd_rnd_ll_s0: |
| 7582 | case Hexagon::M2_mpyd_rnd_ll_s1: |
| 7583 | case Hexagon::M2_mpyud_hh_s0: |
| 7584 | case Hexagon::M2_mpyud_hh_s1: |
| 7585 | case Hexagon::M2_mpyud_hl_s0: |
| 7586 | case Hexagon::M2_mpyud_hl_s1: |
| 7587 | case Hexagon::M2_mpyud_lh_s0: |
| 7588 | case Hexagon::M2_mpyud_lh_s1: |
| 7589 | case Hexagon::M2_mpyud_ll_s0: |
| 7590 | case Hexagon::M2_mpyud_ll_s1: |
| 7591 | case Hexagon::M2_vmpy2s_s0: |
| 7592 | case Hexagon::M2_vmpy2s_s1: |
| 7593 | case Hexagon::M2_vmpy2su_s0: |
| 7594 | case Hexagon::M2_vmpy2su_s1: |
| 7595 | case Hexagon::M4_pmpyw: |
| 7596 | case Hexagon::M4_vpmpyh: |
| 7597 | case Hexagon::M5_vmpybsu: |
| 7598 | case Hexagon::M5_vmpybuu: |
| 7599 | case Hexagon::S2_packhl: |
| 7600 | case Hexagon::dep_S2_packhl: { |
| 7601 | // op: Rs32 |
| 7602 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 7603 | Value |= (op & 0x1f) << 16; |
| 7604 | // op: Rt32 |
| 7605 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 7606 | Value |= (op & 0x1f) << 8; |
| 7607 | // op: Rdd32 |
| 7608 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7609 | Value |= (op & 0x1f); |
| 7610 | break; |
| 7611 | } |
| 7612 | case Hexagon::S4_stored_locked: { |
| 7613 | // op: Rs32 |
| 7614 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 7615 | Value |= (op & 0x1f) << 16; |
| 7616 | // op: Rtt32 |
| 7617 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 7618 | Value |= (op & 0x1f) << 8; |
| 7619 | // op: Pd4 |
| 7620 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7621 | Value |= (op & 0x3); |
| 7622 | break; |
| 7623 | } |
| 7624 | case Hexagon::S2_extractu_rp: |
| 7625 | case Hexagon::S4_extract_rp: { |
| 7626 | // op: Rs32 |
| 7627 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 7628 | Value |= (op & 0x1f) << 16; |
| 7629 | // op: Rtt32 |
| 7630 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 7631 | Value |= (op & 0x1f) << 8; |
| 7632 | // op: Rd32 |
| 7633 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7634 | Value |= (op & 0x1f); |
| 7635 | break; |
| 7636 | } |
| 7637 | case Hexagon::Y2_tfrsrcr: { |
| 7638 | // op: Rs32 |
| 7639 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 7640 | Value |= (op & 0x1f) << 16; |
| 7641 | // op: Sd128 |
| 7642 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7643 | Value |= (op & 0x7f); |
| 7644 | break; |
| 7645 | } |
| 7646 | case Hexagon::F2_sfinvsqrta: { |
| 7647 | // op: Rs32 |
| 7648 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 7649 | Value |= (op & 0x1f) << 16; |
| 7650 | // op: Rd32 |
| 7651 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7652 | Value |= (op & 0x1f); |
| 7653 | // op: Pe4 |
| 7654 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 7655 | Value |= (op & 0x3) << 5; |
| 7656 | break; |
| 7657 | } |
| 7658 | case Hexagon::F2_sffma_sc: { |
| 7659 | // op: Rs32 |
| 7660 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 7661 | Value |= (op & 0x1f) << 16; |
| 7662 | // op: Rt32 |
| 7663 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 7664 | Value |= (op & 0x1f) << 8; |
| 7665 | // op: Pu4 |
| 7666 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 7667 | Value |= (op & 0x3) << 5; |
| 7668 | // op: Rx32 |
| 7669 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7670 | Value |= (op & 0x1f); |
| 7671 | break; |
| 7672 | } |
| 7673 | case Hexagon::F2_sfrecipa: { |
| 7674 | // op: Rs32 |
| 7675 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 7676 | Value |= (op & 0x1f) << 16; |
| 7677 | // op: Rt32 |
| 7678 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 7679 | Value |= (op & 0x1f) << 8; |
| 7680 | // op: Rd32 |
| 7681 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7682 | Value |= (op & 0x1f); |
| 7683 | // op: Pe4 |
| 7684 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 7685 | Value |= (op & 0x3) << 5; |
| 7686 | break; |
| 7687 | } |
| 7688 | case Hexagon::F2_sffma: |
| 7689 | case Hexagon::F2_sffma_lib: |
| 7690 | case Hexagon::F2_sffms: |
| 7691 | case Hexagon::F2_sffms_lib: |
| 7692 | case Hexagon::M2_acci: |
| 7693 | case Hexagon::M2_maci: |
| 7694 | case Hexagon::M2_mnaci: |
| 7695 | case Hexagon::M2_mpy_acc_hh_s0: |
| 7696 | case Hexagon::M2_mpy_acc_hh_s1: |
| 7697 | case Hexagon::M2_mpy_acc_hl_s0: |
| 7698 | case Hexagon::M2_mpy_acc_hl_s1: |
| 7699 | case Hexagon::M2_mpy_acc_lh_s0: |
| 7700 | case Hexagon::M2_mpy_acc_lh_s1: |
| 7701 | case Hexagon::M2_mpy_acc_ll_s0: |
| 7702 | case Hexagon::M2_mpy_acc_ll_s1: |
| 7703 | case Hexagon::M2_mpy_acc_sat_hh_s0: |
| 7704 | case Hexagon::M2_mpy_acc_sat_hh_s1: |
| 7705 | case Hexagon::M2_mpy_acc_sat_hl_s0: |
| 7706 | case Hexagon::M2_mpy_acc_sat_hl_s1: |
| 7707 | case Hexagon::M2_mpy_acc_sat_lh_s0: |
| 7708 | case Hexagon::M2_mpy_acc_sat_lh_s1: |
| 7709 | case Hexagon::M2_mpy_acc_sat_ll_s0: |
| 7710 | case Hexagon::M2_mpy_acc_sat_ll_s1: |
| 7711 | case Hexagon::M2_mpy_nac_hh_s0: |
| 7712 | case Hexagon::M2_mpy_nac_hh_s1: |
| 7713 | case Hexagon::M2_mpy_nac_hl_s0: |
| 7714 | case Hexagon::M2_mpy_nac_hl_s1: |
| 7715 | case Hexagon::M2_mpy_nac_lh_s0: |
| 7716 | case Hexagon::M2_mpy_nac_lh_s1: |
| 7717 | case Hexagon::M2_mpy_nac_ll_s0: |
| 7718 | case Hexagon::M2_mpy_nac_ll_s1: |
| 7719 | case Hexagon::M2_mpy_nac_sat_hh_s0: |
| 7720 | case Hexagon::M2_mpy_nac_sat_hh_s1: |
| 7721 | case Hexagon::M2_mpy_nac_sat_hl_s0: |
| 7722 | case Hexagon::M2_mpy_nac_sat_hl_s1: |
| 7723 | case Hexagon::M2_mpy_nac_sat_lh_s0: |
| 7724 | case Hexagon::M2_mpy_nac_sat_lh_s1: |
| 7725 | case Hexagon::M2_mpy_nac_sat_ll_s0: |
| 7726 | case Hexagon::M2_mpy_nac_sat_ll_s1: |
| 7727 | case Hexagon::M2_mpyu_acc_hh_s0: |
| 7728 | case Hexagon::M2_mpyu_acc_hh_s1: |
| 7729 | case Hexagon::M2_mpyu_acc_hl_s0: |
| 7730 | case Hexagon::M2_mpyu_acc_hl_s1: |
| 7731 | case Hexagon::M2_mpyu_acc_lh_s0: |
| 7732 | case Hexagon::M2_mpyu_acc_lh_s1: |
| 7733 | case Hexagon::M2_mpyu_acc_ll_s0: |
| 7734 | case Hexagon::M2_mpyu_acc_ll_s1: |
| 7735 | case Hexagon::M2_mpyu_nac_hh_s0: |
| 7736 | case Hexagon::M2_mpyu_nac_hh_s1: |
| 7737 | case Hexagon::M2_mpyu_nac_hl_s0: |
| 7738 | case Hexagon::M2_mpyu_nac_hl_s1: |
| 7739 | case Hexagon::M2_mpyu_nac_lh_s0: |
| 7740 | case Hexagon::M2_mpyu_nac_lh_s1: |
| 7741 | case Hexagon::M2_mpyu_nac_ll_s0: |
| 7742 | case Hexagon::M2_mpyu_nac_ll_s1: |
| 7743 | case Hexagon::M2_nacci: |
| 7744 | case Hexagon::M2_xor_xacc: |
| 7745 | case Hexagon::M4_and_and: |
| 7746 | case Hexagon::M4_and_andn: |
| 7747 | case Hexagon::M4_and_or: |
| 7748 | case Hexagon::M4_and_xor: |
| 7749 | case Hexagon::M4_mac_up_s1_sat: |
| 7750 | case Hexagon::M4_nac_up_s1_sat: |
| 7751 | case Hexagon::M4_or_and: |
| 7752 | case Hexagon::M4_or_andn: |
| 7753 | case Hexagon::M4_or_or: |
| 7754 | case Hexagon::M4_or_xor: |
| 7755 | case Hexagon::M4_xor_and: |
| 7756 | case Hexagon::M4_xor_andn: |
| 7757 | case Hexagon::M4_xor_or: |
| 7758 | case Hexagon::S2_asl_r_r_acc: |
| 7759 | case Hexagon::S2_asl_r_r_and: |
| 7760 | case Hexagon::S2_asl_r_r_nac: |
| 7761 | case Hexagon::S2_asl_r_r_or: |
| 7762 | case Hexagon::S2_asr_r_r_acc: |
| 7763 | case Hexagon::S2_asr_r_r_and: |
| 7764 | case Hexagon::S2_asr_r_r_nac: |
| 7765 | case Hexagon::S2_asr_r_r_or: |
| 7766 | case Hexagon::S2_lsl_r_r_acc: |
| 7767 | case Hexagon::S2_lsl_r_r_and: |
| 7768 | case Hexagon::S2_lsl_r_r_nac: |
| 7769 | case Hexagon::S2_lsl_r_r_or: |
| 7770 | case Hexagon::S2_lsr_r_r_acc: |
| 7771 | case Hexagon::S2_lsr_r_r_and: |
| 7772 | case Hexagon::S2_lsr_r_r_nac: |
| 7773 | case Hexagon::S2_lsr_r_r_or: { |
| 7774 | // op: Rs32 |
| 7775 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 7776 | Value |= (op & 0x1f) << 16; |
| 7777 | // op: Rt32 |
| 7778 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 7779 | Value |= (op & 0x1f) << 8; |
| 7780 | // op: Rx32 |
| 7781 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7782 | Value |= (op & 0x1f); |
| 7783 | break; |
| 7784 | } |
| 7785 | case Hexagon::M2_cmaci_s0: |
| 7786 | case Hexagon::M2_cmacr_s0: |
| 7787 | case Hexagon::M2_cmacs_s0: |
| 7788 | case Hexagon::M2_cmacs_s1: |
| 7789 | case Hexagon::M2_cmacsc_s0: |
| 7790 | case Hexagon::M2_cmacsc_s1: |
| 7791 | case Hexagon::M2_cnacs_s0: |
| 7792 | case Hexagon::M2_cnacs_s1: |
| 7793 | case Hexagon::M2_cnacsc_s0: |
| 7794 | case Hexagon::M2_cnacsc_s1: |
| 7795 | case Hexagon::M2_dpmpyss_acc_s0: |
| 7796 | case Hexagon::M2_dpmpyss_nac_s0: |
| 7797 | case Hexagon::M2_dpmpyuu_acc_s0: |
| 7798 | case Hexagon::M2_dpmpyuu_nac_s0: |
| 7799 | case Hexagon::M2_mpyd_acc_hh_s0: |
| 7800 | case Hexagon::M2_mpyd_acc_hh_s1: |
| 7801 | case Hexagon::M2_mpyd_acc_hl_s0: |
| 7802 | case Hexagon::M2_mpyd_acc_hl_s1: |
| 7803 | case Hexagon::M2_mpyd_acc_lh_s0: |
| 7804 | case Hexagon::M2_mpyd_acc_lh_s1: |
| 7805 | case Hexagon::M2_mpyd_acc_ll_s0: |
| 7806 | case Hexagon::M2_mpyd_acc_ll_s1: |
| 7807 | case Hexagon::M2_mpyd_nac_hh_s0: |
| 7808 | case Hexagon::M2_mpyd_nac_hh_s1: |
| 7809 | case Hexagon::M2_mpyd_nac_hl_s0: |
| 7810 | case Hexagon::M2_mpyd_nac_hl_s1: |
| 7811 | case Hexagon::M2_mpyd_nac_lh_s0: |
| 7812 | case Hexagon::M2_mpyd_nac_lh_s1: |
| 7813 | case Hexagon::M2_mpyd_nac_ll_s0: |
| 7814 | case Hexagon::M2_mpyd_nac_ll_s1: |
| 7815 | case Hexagon::M2_mpyud_acc_hh_s0: |
| 7816 | case Hexagon::M2_mpyud_acc_hh_s1: |
| 7817 | case Hexagon::M2_mpyud_acc_hl_s0: |
| 7818 | case Hexagon::M2_mpyud_acc_hl_s1: |
| 7819 | case Hexagon::M2_mpyud_acc_lh_s0: |
| 7820 | case Hexagon::M2_mpyud_acc_lh_s1: |
| 7821 | case Hexagon::M2_mpyud_acc_ll_s0: |
| 7822 | case Hexagon::M2_mpyud_acc_ll_s1: |
| 7823 | case Hexagon::M2_mpyud_nac_hh_s0: |
| 7824 | case Hexagon::M2_mpyud_nac_hh_s1: |
| 7825 | case Hexagon::M2_mpyud_nac_hl_s0: |
| 7826 | case Hexagon::M2_mpyud_nac_hl_s1: |
| 7827 | case Hexagon::M2_mpyud_nac_lh_s0: |
| 7828 | case Hexagon::M2_mpyud_nac_lh_s1: |
| 7829 | case Hexagon::M2_mpyud_nac_ll_s0: |
| 7830 | case Hexagon::M2_mpyud_nac_ll_s1: |
| 7831 | case Hexagon::M2_vmac2: |
| 7832 | case Hexagon::M2_vmac2s_s0: |
| 7833 | case Hexagon::M2_vmac2s_s1: |
| 7834 | case Hexagon::M2_vmac2su_s0: |
| 7835 | case Hexagon::M2_vmac2su_s1: |
| 7836 | case Hexagon::M4_pmpyw_acc: |
| 7837 | case Hexagon::M4_vpmpyh_acc: |
| 7838 | case Hexagon::M5_vmacbsu: |
| 7839 | case Hexagon::M5_vmacbuu: { |
| 7840 | // op: Rs32 |
| 7841 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 7842 | Value |= (op & 0x1f) << 16; |
| 7843 | // op: Rt32 |
| 7844 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 7845 | Value |= (op & 0x1f) << 8; |
| 7846 | // op: Rxx32 |
| 7847 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7848 | Value |= (op & 0x1f); |
| 7849 | break; |
| 7850 | } |
| 7851 | case Hexagon::S2_insert_rp: { |
| 7852 | // op: Rs32 |
| 7853 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 7854 | Value |= (op & 0x1f) << 16; |
| 7855 | // op: Rtt32 |
| 7856 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 7857 | Value |= (op & 0x1f) << 8; |
| 7858 | // op: Rx32 |
| 7859 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7860 | Value |= (op & 0x1f); |
| 7861 | break; |
| 7862 | } |
| 7863 | case Hexagon::Y2_tlbw: { |
| 7864 | // op: Rss32 |
| 7865 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7866 | Value |= (op & 0x1f) << 16; |
| 7867 | // op: Rt32 |
| 7868 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 7869 | Value |= (op & 0x1f) << 8; |
| 7870 | break; |
| 7871 | } |
| 7872 | case Hexagon::Y6_diag0: |
| 7873 | case Hexagon::Y6_diag1: { |
| 7874 | // op: Rss32 |
| 7875 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7876 | Value |= (op & 0x1f) << 16; |
| 7877 | // op: Rtt32 |
| 7878 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 7879 | Value |= (op & 0x1f) << 8; |
| 7880 | break; |
| 7881 | } |
| 7882 | case Hexagon::A4_tfrpcp: { |
| 7883 | // op: Rss32 |
| 7884 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 7885 | Value |= (op & 0x1f) << 16; |
| 7886 | // op: Cdd32 |
| 7887 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7888 | Value |= (op & 0x1f); |
| 7889 | break; |
| 7890 | } |
| 7891 | case Hexagon::G4_tfrgpcp: { |
| 7892 | // op: Rss32 |
| 7893 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 7894 | Value |= (op & 0x1f) << 16; |
| 7895 | // op: Gdd32 |
| 7896 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7897 | Value |= (op & 0x1f); |
| 7898 | break; |
| 7899 | } |
| 7900 | case Hexagon::A2_roundsat: |
| 7901 | case Hexagon::A2_sat: |
| 7902 | case Hexagon::F2_conv_d2sf: |
| 7903 | case Hexagon::F2_conv_df2sf: |
| 7904 | case Hexagon::F2_conv_df2uw: |
| 7905 | case Hexagon::F2_conv_df2uw_chop: |
| 7906 | case Hexagon::F2_conv_df2w: |
| 7907 | case Hexagon::F2_conv_df2w_chop: |
| 7908 | case Hexagon::F2_conv_ud2sf: |
| 7909 | case Hexagon::S2_cl0p: |
| 7910 | case Hexagon::S2_cl1p: |
| 7911 | case Hexagon::S2_clbp: |
| 7912 | case Hexagon::S2_ct0p: |
| 7913 | case Hexagon::S2_ct1p: |
| 7914 | case Hexagon::S2_vrndpackwh: |
| 7915 | case Hexagon::S2_vrndpackwhs: |
| 7916 | case Hexagon::S2_vsathb: |
| 7917 | case Hexagon::S2_vsathub: |
| 7918 | case Hexagon::S2_vsatwh: |
| 7919 | case Hexagon::S2_vsatwuh: |
| 7920 | case Hexagon::S2_vtrunehb: |
| 7921 | case Hexagon::S2_vtrunohb: |
| 7922 | case Hexagon::S4_clbpnorm: |
| 7923 | case Hexagon::S5_popcountp: |
| 7924 | case Hexagon::Y2_tlbpp: |
| 7925 | case Hexagon::Y5_tlboc: { |
| 7926 | // op: Rss32 |
| 7927 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 7928 | Value |= (op & 0x1f) << 16; |
| 7929 | // op: Rd32 |
| 7930 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7931 | Value |= (op & 0x1f); |
| 7932 | break; |
| 7933 | } |
| 7934 | case Hexagon::A2_absp: |
| 7935 | case Hexagon::A2_negp: |
| 7936 | case Hexagon::A2_notp: |
| 7937 | case Hexagon::A2_vabsh: |
| 7938 | case Hexagon::A2_vabshsat: |
| 7939 | case Hexagon::A2_vabsw: |
| 7940 | case Hexagon::A2_vabswsat: |
| 7941 | case Hexagon::A2_vconj: |
| 7942 | case Hexagon::F2_conv_d2df: |
| 7943 | case Hexagon::F2_conv_df2d: |
| 7944 | case Hexagon::F2_conv_df2d_chop: |
| 7945 | case Hexagon::F2_conv_df2ud: |
| 7946 | case Hexagon::F2_conv_df2ud_chop: |
| 7947 | case Hexagon::F2_conv_ud2df: |
| 7948 | case Hexagon::S2_brevp: |
| 7949 | case Hexagon::S2_deinterleave: |
| 7950 | case Hexagon::S2_interleave: |
| 7951 | case Hexagon::S2_vsathb_nopack: |
| 7952 | case Hexagon::S2_vsathub_nopack: |
| 7953 | case Hexagon::S2_vsatwh_nopack: |
| 7954 | case Hexagon::S2_vsatwuh_nopack: { |
| 7955 | // op: Rss32 |
| 7956 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 7957 | Value |= (op & 0x1f) << 16; |
| 7958 | // op: Rdd32 |
| 7959 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7960 | Value |= (op & 0x1f); |
| 7961 | break; |
| 7962 | } |
| 7963 | case Hexagon::A4_tlbmatch: { |
| 7964 | // op: Rss32 |
| 7965 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 7966 | Value |= (op & 0x1f) << 16; |
| 7967 | // op: Rt32 |
| 7968 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 7969 | Value |= (op & 0x1f) << 8; |
| 7970 | // op: Pd4 |
| 7971 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7972 | Value |= (op & 0x3); |
| 7973 | break; |
| 7974 | } |
| 7975 | case Hexagon::M4_cmpyi_wh: |
| 7976 | case Hexagon::M4_cmpyi_whc: |
| 7977 | case Hexagon::M4_cmpyr_wh: |
| 7978 | case Hexagon::M4_cmpyr_whc: |
| 7979 | case Hexagon::S2_asr_r_svw_trun: |
| 7980 | case Hexagon::Y5_ctlbw: { |
| 7981 | // op: Rss32 |
| 7982 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 7983 | Value |= (op & 0x1f) << 16; |
| 7984 | // op: Rt32 |
| 7985 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 7986 | Value |= (op & 0x1f) << 8; |
| 7987 | // op: Rd32 |
| 7988 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7989 | Value |= (op & 0x1f); |
| 7990 | break; |
| 7991 | } |
| 7992 | case Hexagon::A7_croundd_rr: |
| 7993 | case Hexagon::S2_asl_r_p: |
| 7994 | case Hexagon::S2_asl_r_vh: |
| 7995 | case Hexagon::S2_asl_r_vw: |
| 7996 | case Hexagon::S2_asr_r_p: |
| 7997 | case Hexagon::S2_asr_r_vh: |
| 7998 | case Hexagon::S2_asr_r_vw: |
| 7999 | case Hexagon::S2_lsl_r_p: |
| 8000 | case Hexagon::S2_lsl_r_vh: |
| 8001 | case Hexagon::S2_lsl_r_vw: |
| 8002 | case Hexagon::S2_lsr_r_p: |
| 8003 | case Hexagon::S2_lsr_r_vh: |
| 8004 | case Hexagon::S2_lsr_r_vw: |
| 8005 | case Hexagon::S2_vcnegh: |
| 8006 | case Hexagon::S2_vcrotate: { |
| 8007 | // op: Rss32 |
| 8008 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8009 | Value |= (op & 0x1f) << 16; |
| 8010 | // op: Rt32 |
| 8011 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8012 | Value |= (op & 0x1f) << 8; |
| 8013 | // op: Rdd32 |
| 8014 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8015 | Value |= (op & 0x1f); |
| 8016 | break; |
| 8017 | } |
| 8018 | case Hexagon::A2_vcmpbeq: |
| 8019 | case Hexagon::A2_vcmpbgtu: |
| 8020 | case Hexagon::A2_vcmpheq: |
| 8021 | case Hexagon::A2_vcmphgt: |
| 8022 | case Hexagon::A2_vcmphgtu: |
| 8023 | case Hexagon::A2_vcmpweq: |
| 8024 | case Hexagon::A2_vcmpwgt: |
| 8025 | case Hexagon::A2_vcmpwgtu: |
| 8026 | case Hexagon::A4_boundscheck_hi: |
| 8027 | case Hexagon::A4_boundscheck_lo: |
| 8028 | case Hexagon::A4_vcmpbeq_any: |
| 8029 | case Hexagon::A4_vcmpbgt: |
| 8030 | case Hexagon::A6_vcmpbeq_notany: |
| 8031 | case Hexagon::C2_cmpeqp: |
| 8032 | case Hexagon::C2_cmpgtp: |
| 8033 | case Hexagon::C2_cmpgtup: |
| 8034 | case Hexagon::F2_dfcmpeq: |
| 8035 | case Hexagon::F2_dfcmpge: |
| 8036 | case Hexagon::F2_dfcmpgt: |
| 8037 | case Hexagon::F2_dfcmpuo: { |
| 8038 | // op: Rss32 |
| 8039 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8040 | Value |= (op & 0x1f) << 16; |
| 8041 | // op: Rtt32 |
| 8042 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8043 | Value |= (op & 0x1f) << 8; |
| 8044 | // op: Pd4 |
| 8045 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8046 | Value |= (op & 0x3); |
| 8047 | break; |
| 8048 | } |
| 8049 | case Hexagon::S2_vsplicerb: { |
| 8050 | // op: Rss32 |
| 8051 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8052 | Value |= (op & 0x1f) << 16; |
| 8053 | // op: Rtt32 |
| 8054 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8055 | Value |= (op & 0x1f) << 8; |
| 8056 | // op: Pu4 |
| 8057 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 8058 | Value |= (op & 0x3) << 5; |
| 8059 | // op: Rdd32 |
| 8060 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8061 | Value |= (op & 0x1f); |
| 8062 | break; |
| 8063 | } |
| 8064 | case Hexagon::A5_vaddhubs: |
| 8065 | case Hexagon::M2_vdmpyrs_s0: |
| 8066 | case Hexagon::M2_vdmpyrs_s1: |
| 8067 | case Hexagon::M2_vraddh: |
| 8068 | case Hexagon::M2_vradduh: |
| 8069 | case Hexagon::M2_vrcmpys_s1rp_h: |
| 8070 | case Hexagon::M2_vrcmpys_s1rp_l: |
| 8071 | case Hexagon::M7_wcmpyiw: |
| 8072 | case Hexagon::M7_wcmpyiw_rnd: |
| 8073 | case Hexagon::M7_wcmpyiwc: |
| 8074 | case Hexagon::M7_wcmpyiwc_rnd: |
| 8075 | case Hexagon::M7_wcmpyrw: |
| 8076 | case Hexagon::M7_wcmpyrw_rnd: |
| 8077 | case Hexagon::M7_wcmpyrwc: |
| 8078 | case Hexagon::M7_wcmpyrwc_rnd: |
| 8079 | case Hexagon::S2_parityp: { |
| 8080 | // op: Rss32 |
| 8081 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8082 | Value |= (op & 0x1f) << 16; |
| 8083 | // op: Rtt32 |
| 8084 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8085 | Value |= (op & 0x1f) << 8; |
| 8086 | // op: Rd32 |
| 8087 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8088 | Value |= (op & 0x1f); |
| 8089 | break; |
| 8090 | } |
| 8091 | case Hexagon::A2_addp: |
| 8092 | case Hexagon::A2_addpsat: |
| 8093 | case Hexagon::A2_addsph: |
| 8094 | case Hexagon::A2_addspl: |
| 8095 | case Hexagon::A2_andp: |
| 8096 | case Hexagon::A2_maxp: |
| 8097 | case Hexagon::A2_maxup: |
| 8098 | case Hexagon::A2_orp: |
| 8099 | case Hexagon::A2_vaddh: |
| 8100 | case Hexagon::A2_vaddhs: |
| 8101 | case Hexagon::A2_vaddub: |
| 8102 | case Hexagon::A2_vaddubs: |
| 8103 | case Hexagon::A2_vadduhs: |
| 8104 | case Hexagon::A2_vaddw: |
| 8105 | case Hexagon::A2_vaddws: |
| 8106 | case Hexagon::A2_vavgh: |
| 8107 | case Hexagon::A2_vavghcr: |
| 8108 | case Hexagon::A2_vavghr: |
| 8109 | case Hexagon::A2_vavgub: |
| 8110 | case Hexagon::A2_vavgubr: |
| 8111 | case Hexagon::A2_vavguh: |
| 8112 | case Hexagon::A2_vavguhr: |
| 8113 | case Hexagon::A2_vavguw: |
| 8114 | case Hexagon::A2_vavguwr: |
| 8115 | case Hexagon::A2_vavgw: |
| 8116 | case Hexagon::A2_vavgwcr: |
| 8117 | case Hexagon::A2_vavgwr: |
| 8118 | case Hexagon::A2_vraddub: |
| 8119 | case Hexagon::A2_vrsadub: |
| 8120 | case Hexagon::A2_xorp: |
| 8121 | case Hexagon::F2_dfadd: |
| 8122 | case Hexagon::F2_dfmax: |
| 8123 | case Hexagon::F2_dfmin: |
| 8124 | case Hexagon::F2_dfmpyfix: |
| 8125 | case Hexagon::F2_dfmpyll: |
| 8126 | case Hexagon::F2_dfsub: |
| 8127 | case Hexagon::M2_mmpyh_rs0: |
| 8128 | case Hexagon::M2_mmpyh_rs1: |
| 8129 | case Hexagon::M2_mmpyh_s0: |
| 8130 | case Hexagon::M2_mmpyh_s1: |
| 8131 | case Hexagon::M2_mmpyl_rs0: |
| 8132 | case Hexagon::M2_mmpyl_rs1: |
| 8133 | case Hexagon::M2_mmpyl_s0: |
| 8134 | case Hexagon::M2_mmpyl_s1: |
| 8135 | case Hexagon::M2_mmpyuh_rs0: |
| 8136 | case Hexagon::M2_mmpyuh_rs1: |
| 8137 | case Hexagon::M2_mmpyuh_s0: |
| 8138 | case Hexagon::M2_mmpyuh_s1: |
| 8139 | case Hexagon::M2_mmpyul_rs0: |
| 8140 | case Hexagon::M2_mmpyul_rs1: |
| 8141 | case Hexagon::M2_mmpyul_s0: |
| 8142 | case Hexagon::M2_mmpyul_s1: |
| 8143 | case Hexagon::M2_vcmpy_s0_sat_i: |
| 8144 | case Hexagon::M2_vcmpy_s0_sat_r: |
| 8145 | case Hexagon::M2_vcmpy_s1_sat_i: |
| 8146 | case Hexagon::M2_vcmpy_s1_sat_r: |
| 8147 | case Hexagon::M2_vdmpys_s0: |
| 8148 | case Hexagon::M2_vdmpys_s1: |
| 8149 | case Hexagon::M2_vmpy2es_s0: |
| 8150 | case Hexagon::M2_vmpy2es_s1: |
| 8151 | case Hexagon::M2_vrcmpyi_s0: |
| 8152 | case Hexagon::M2_vrcmpyi_s0c: |
| 8153 | case Hexagon::M2_vrcmpyr_s0: |
| 8154 | case Hexagon::M2_vrcmpyr_s0c: |
| 8155 | case Hexagon::M2_vrcmpys_s1_h: |
| 8156 | case Hexagon::M2_vrcmpys_s1_l: |
| 8157 | case Hexagon::M2_vrmpy_s0: |
| 8158 | case Hexagon::M4_vrmpyeh_s0: |
| 8159 | case Hexagon::M4_vrmpyeh_s1: |
| 8160 | case Hexagon::M4_vrmpyoh_s0: |
| 8161 | case Hexagon::M4_vrmpyoh_s1: |
| 8162 | case Hexagon::M5_vdmpybsu: |
| 8163 | case Hexagon::M5_vrmpybsu: |
| 8164 | case Hexagon::M5_vrmpybuu: |
| 8165 | case Hexagon::M7_dcmpyiw: |
| 8166 | case Hexagon::M7_dcmpyiwc: |
| 8167 | case Hexagon::M7_dcmpyrw: |
| 8168 | case Hexagon::M7_dcmpyrwc: |
| 8169 | case Hexagon::S2_cabacdecbin: |
| 8170 | case Hexagon::S2_extractup_rp: |
| 8171 | case Hexagon::S2_lfsp: |
| 8172 | case Hexagon::S2_shuffeb: |
| 8173 | case Hexagon::S2_shuffeh: |
| 8174 | case Hexagon::S2_vtrunewh: |
| 8175 | case Hexagon::S2_vtrunowh: |
| 8176 | case Hexagon::S4_extractp_rp: |
| 8177 | case Hexagon::S4_vxaddsubh: |
| 8178 | case Hexagon::S4_vxaddsubhr: |
| 8179 | case Hexagon::S4_vxaddsubw: |
| 8180 | case Hexagon::S4_vxsubaddh: |
| 8181 | case Hexagon::S4_vxsubaddhr: |
| 8182 | case Hexagon::S4_vxsubaddw: |
| 8183 | case Hexagon::S6_vtrunehb_ppp: |
| 8184 | case Hexagon::S6_vtrunohb_ppp: { |
| 8185 | // op: Rss32 |
| 8186 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8187 | Value |= (op & 0x1f) << 16; |
| 8188 | // op: Rtt32 |
| 8189 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8190 | Value |= (op & 0x1f) << 8; |
| 8191 | // op: Rdd32 |
| 8192 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8193 | Value |= (op & 0x1f); |
| 8194 | break; |
| 8195 | } |
| 8196 | case Hexagon::Y4_tfrspcp: { |
| 8197 | // op: Rss32 |
| 8198 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8199 | Value |= (op & 0x1f) << 16; |
| 8200 | // op: Sdd128 |
| 8201 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8202 | Value |= (op & 0x7f); |
| 8203 | break; |
| 8204 | } |
| 8205 | case Hexagon::S2_asl_r_p_acc: |
| 8206 | case Hexagon::S2_asl_r_p_and: |
| 8207 | case Hexagon::S2_asl_r_p_nac: |
| 8208 | case Hexagon::S2_asl_r_p_or: |
| 8209 | case Hexagon::S2_asl_r_p_xor: |
| 8210 | case Hexagon::S2_asr_r_p_acc: |
| 8211 | case Hexagon::S2_asr_r_p_and: |
| 8212 | case Hexagon::S2_asr_r_p_nac: |
| 8213 | case Hexagon::S2_asr_r_p_or: |
| 8214 | case Hexagon::S2_asr_r_p_xor: |
| 8215 | case Hexagon::S2_lsl_r_p_acc: |
| 8216 | case Hexagon::S2_lsl_r_p_and: |
| 8217 | case Hexagon::S2_lsl_r_p_nac: |
| 8218 | case Hexagon::S2_lsl_r_p_or: |
| 8219 | case Hexagon::S2_lsl_r_p_xor: |
| 8220 | case Hexagon::S2_lsr_r_p_acc: |
| 8221 | case Hexagon::S2_lsr_r_p_and: |
| 8222 | case Hexagon::S2_lsr_r_p_nac: |
| 8223 | case Hexagon::S2_lsr_r_p_or: |
| 8224 | case Hexagon::S2_lsr_r_p_xor: |
| 8225 | case Hexagon::S2_vrcnegh: { |
| 8226 | // op: Rss32 |
| 8227 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8228 | Value |= (op & 0x1f) << 16; |
| 8229 | // op: Rt32 |
| 8230 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 8231 | Value |= (op & 0x1f) << 8; |
| 8232 | // op: Rxx32 |
| 8233 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8234 | Value |= (op & 0x1f); |
| 8235 | break; |
| 8236 | } |
| 8237 | case Hexagon::A4_addp_c: |
| 8238 | case Hexagon::A4_subp_c: { |
| 8239 | // op: Rss32 |
| 8240 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8241 | Value |= (op & 0x1f) << 16; |
| 8242 | // op: Rtt32 |
| 8243 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 8244 | Value |= (op & 0x1f) << 8; |
| 8245 | // op: Rdd32 |
| 8246 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8247 | Value |= (op & 0x1f); |
| 8248 | // op: Px4 |
| 8249 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8250 | Value |= (op & 0x3) << 5; |
| 8251 | break; |
| 8252 | } |
| 8253 | case Hexagon::A2_vraddub_acc: |
| 8254 | case Hexagon::A2_vrsadub_acc: |
| 8255 | case Hexagon::F2_dfmpyhh: |
| 8256 | case Hexagon::F2_dfmpylh: |
| 8257 | case Hexagon::M2_mmachs_rs0: |
| 8258 | case Hexagon::M2_mmachs_rs1: |
| 8259 | case Hexagon::M2_mmachs_s0: |
| 8260 | case Hexagon::M2_mmachs_s1: |
| 8261 | case Hexagon::M2_mmacls_rs0: |
| 8262 | case Hexagon::M2_mmacls_rs1: |
| 8263 | case Hexagon::M2_mmacls_s0: |
| 8264 | case Hexagon::M2_mmacls_s1: |
| 8265 | case Hexagon::M2_mmacuhs_rs0: |
| 8266 | case Hexagon::M2_mmacuhs_rs1: |
| 8267 | case Hexagon::M2_mmacuhs_s0: |
| 8268 | case Hexagon::M2_mmacuhs_s1: |
| 8269 | case Hexagon::M2_mmaculs_rs0: |
| 8270 | case Hexagon::M2_mmaculs_rs1: |
| 8271 | case Hexagon::M2_mmaculs_s0: |
| 8272 | case Hexagon::M2_mmaculs_s1: |
| 8273 | case Hexagon::M2_vcmac_s0_sat_i: |
| 8274 | case Hexagon::M2_vcmac_s0_sat_r: |
| 8275 | case Hexagon::M2_vdmacs_s0: |
| 8276 | case Hexagon::M2_vdmacs_s1: |
| 8277 | case Hexagon::M2_vmac2es: |
| 8278 | case Hexagon::M2_vmac2es_s0: |
| 8279 | case Hexagon::M2_vmac2es_s1: |
| 8280 | case Hexagon::M2_vrcmaci_s0: |
| 8281 | case Hexagon::M2_vrcmaci_s0c: |
| 8282 | case Hexagon::M2_vrcmacr_s0: |
| 8283 | case Hexagon::M2_vrcmacr_s0c: |
| 8284 | case Hexagon::M2_vrcmpys_acc_s1_h: |
| 8285 | case Hexagon::M2_vrcmpys_acc_s1_l: |
| 8286 | case Hexagon::M2_vrmac_s0: |
| 8287 | case Hexagon::M4_vrmpyeh_acc_s0: |
| 8288 | case Hexagon::M4_vrmpyeh_acc_s1: |
| 8289 | case Hexagon::M4_vrmpyoh_acc_s0: |
| 8290 | case Hexagon::M4_vrmpyoh_acc_s1: |
| 8291 | case Hexagon::M4_xor_xacc: |
| 8292 | case Hexagon::M5_vdmacbsu: |
| 8293 | case Hexagon::M5_vrmacbsu: |
| 8294 | case Hexagon::M5_vrmacbuu: |
| 8295 | case Hexagon::M7_dcmpyiw_acc: |
| 8296 | case Hexagon::M7_dcmpyiwc_acc: |
| 8297 | case Hexagon::M7_dcmpyrw_acc: |
| 8298 | case Hexagon::M7_dcmpyrwc_acc: |
| 8299 | case Hexagon::S2_insertp_rp: { |
| 8300 | // op: Rss32 |
| 8301 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8302 | Value |= (op & 0x1f) << 16; |
| 8303 | // op: Rtt32 |
| 8304 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 8305 | Value |= (op & 0x1f) << 8; |
| 8306 | // op: Rxx32 |
| 8307 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8308 | Value |= (op & 0x1f); |
| 8309 | break; |
| 8310 | } |
| 8311 | case Hexagon::A4_vrmaxh: |
| 8312 | case Hexagon::A4_vrmaxuh: |
| 8313 | case Hexagon::A4_vrmaxuw: |
| 8314 | case Hexagon::A4_vrmaxw: |
| 8315 | case Hexagon::A4_vrminh: |
| 8316 | case Hexagon::A4_vrminuh: |
| 8317 | case Hexagon::A4_vrminuw: |
| 8318 | case Hexagon::A4_vrminw: { |
| 8319 | // op: Rss32 |
| 8320 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8321 | Value |= (op & 0x1f) << 16; |
| 8322 | // op: Ru32 |
| 8323 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 8324 | Value |= (op & 0x1f); |
| 8325 | // op: Rxx32 |
| 8326 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8327 | Value |= (op & 0x1f) << 8; |
| 8328 | break; |
| 8329 | } |
| 8330 | case Hexagon::A5_ACS: { |
| 8331 | // op: Rss32 |
| 8332 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 8333 | Value |= (op & 0x1f) << 16; |
| 8334 | // op: Rtt32 |
| 8335 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 8336 | Value |= (op & 0x1f) << 8; |
| 8337 | // op: Rxx32 |
| 8338 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8339 | Value |= (op & 0x1f); |
| 8340 | // op: Pe4 |
| 8341 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8342 | Value |= (op & 0x3) << 5; |
| 8343 | break; |
| 8344 | } |
| 8345 | case Hexagon::V6_vscattermh: |
| 8346 | case Hexagon::V6_vscattermh_add: |
| 8347 | case Hexagon::V6_vscattermw: |
| 8348 | case Hexagon::V6_vscattermw_add: { |
| 8349 | // op: Rt32 |
| 8350 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8351 | Value |= (op & 0x1f) << 16; |
| 8352 | // op: Mu2 |
| 8353 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8354 | Value |= (op & 0x1) << 13; |
| 8355 | // op: Vv32 |
| 8356 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8357 | Value |= (op & 0x1f) << 8; |
| 8358 | // op: Vw32 |
| 8359 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 8360 | Value |= (op & 0x1f); |
| 8361 | break; |
| 8362 | } |
| 8363 | case Hexagon::V6_vgathermh: |
| 8364 | case Hexagon::V6_vgathermw: { |
| 8365 | // op: Rt32 |
| 8366 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8367 | Value |= (op & 0x1f) << 16; |
| 8368 | // op: Mu2 |
| 8369 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8370 | Value |= (op & 0x1) << 13; |
| 8371 | // op: Vv32 |
| 8372 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8373 | Value |= (op & 0x1f); |
| 8374 | break; |
| 8375 | } |
| 8376 | case Hexagon::V6_vscattermhw: |
| 8377 | case Hexagon::V6_vscattermhw_add: { |
| 8378 | // op: Rt32 |
| 8379 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8380 | Value |= (op & 0x1f) << 16; |
| 8381 | // op: Mu2 |
| 8382 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8383 | Value |= (op & 0x1) << 13; |
| 8384 | // op: Vvv32 |
| 8385 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8386 | Value |= (op & 0x1f) << 8; |
| 8387 | // op: Vw32 |
| 8388 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 8389 | Value |= (op & 0x1f); |
| 8390 | break; |
| 8391 | } |
| 8392 | case Hexagon::V6_vgathermhw: { |
| 8393 | // op: Rt32 |
| 8394 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8395 | Value |= (op & 0x1f) << 16; |
| 8396 | // op: Mu2 |
| 8397 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8398 | Value |= (op & 0x1) << 13; |
| 8399 | // op: Vvv32 |
| 8400 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8401 | Value |= (op & 0x1f); |
| 8402 | break; |
| 8403 | } |
| 8404 | case Hexagon::V6_pred_scalar2: |
| 8405 | case Hexagon::V6_pred_scalar2v2: { |
| 8406 | // op: Rt32 |
| 8407 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8408 | Value |= (op & 0x1f) << 16; |
| 8409 | // op: Qd4 |
| 8410 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8411 | Value |= (op & 0x3); |
| 8412 | break; |
| 8413 | } |
| 8414 | case Hexagon::V6_lvsplatb: |
| 8415 | case Hexagon::V6_lvsplath: |
| 8416 | case Hexagon::V6_lvsplatw: |
| 8417 | case Hexagon::V6_zextract: { |
| 8418 | // op: Rt32 |
| 8419 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8420 | Value |= (op & 0x1f) << 16; |
| 8421 | // op: Vd32 |
| 8422 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8423 | Value |= (op & 0x1f); |
| 8424 | break; |
| 8425 | } |
| 8426 | case Hexagon::A2_addh_h16_hh: |
| 8427 | case Hexagon::A2_addh_h16_hl: |
| 8428 | case Hexagon::A2_addh_h16_lh: |
| 8429 | case Hexagon::A2_addh_h16_ll: |
| 8430 | case Hexagon::A2_addh_h16_sat_hh: |
| 8431 | case Hexagon::A2_addh_h16_sat_hl: |
| 8432 | case Hexagon::A2_addh_h16_sat_lh: |
| 8433 | case Hexagon::A2_addh_h16_sat_ll: |
| 8434 | case Hexagon::A2_addh_l16_hl: |
| 8435 | case Hexagon::A2_addh_l16_ll: |
| 8436 | case Hexagon::A2_addh_l16_sat_hl: |
| 8437 | case Hexagon::A2_addh_l16_sat_ll: |
| 8438 | case Hexagon::A2_combine_hh: |
| 8439 | case Hexagon::A2_combine_hl: |
| 8440 | case Hexagon::A2_combine_lh: |
| 8441 | case Hexagon::A2_combine_ll: |
| 8442 | case Hexagon::A2_min: |
| 8443 | case Hexagon::A2_minu: |
| 8444 | case Hexagon::A2_sub: |
| 8445 | case Hexagon::A2_subh_h16_hh: |
| 8446 | case Hexagon::A2_subh_h16_hl: |
| 8447 | case Hexagon::A2_subh_h16_lh: |
| 8448 | case Hexagon::A2_subh_h16_ll: |
| 8449 | case Hexagon::A2_subh_h16_sat_hh: |
| 8450 | case Hexagon::A2_subh_h16_sat_hl: |
| 8451 | case Hexagon::A2_subh_h16_sat_lh: |
| 8452 | case Hexagon::A2_subh_h16_sat_ll: |
| 8453 | case Hexagon::A2_subh_l16_hl: |
| 8454 | case Hexagon::A2_subh_l16_ll: |
| 8455 | case Hexagon::A2_subh_l16_sat_hl: |
| 8456 | case Hexagon::A2_subh_l16_sat_ll: |
| 8457 | case Hexagon::A2_subsat: |
| 8458 | case Hexagon::A2_svnavgh: |
| 8459 | case Hexagon::A2_svsubh: |
| 8460 | case Hexagon::A2_svsubhs: |
| 8461 | case Hexagon::A2_svsubuhs: |
| 8462 | case Hexagon::A4_andn: |
| 8463 | case Hexagon::A4_orn: |
| 8464 | case Hexagon::dep_A2_subsat: { |
| 8465 | // op: Rt32 |
| 8466 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8467 | Value |= (op & 0x1f) << 8; |
| 8468 | // op: Rs32 |
| 8469 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8470 | Value |= (op & 0x1f) << 16; |
| 8471 | // op: Rd32 |
| 8472 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8473 | Value |= (op & 0x1f); |
| 8474 | break; |
| 8475 | } |
| 8476 | case Hexagon::V6_vinsertwr: { |
| 8477 | // op: Rt32 |
| 8478 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8479 | Value |= (op & 0x1f) << 16; |
| 8480 | // op: Vx32 |
| 8481 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8482 | Value |= (op & 0x1f); |
| 8483 | break; |
| 8484 | } |
| 8485 | case Hexagon::M2_subacc: { |
| 8486 | // op: Rt32 |
| 8487 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8488 | Value |= (op & 0x1f) << 8; |
| 8489 | // op: Rs32 |
| 8490 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 8491 | Value |= (op & 0x1f) << 16; |
| 8492 | // op: Rx32 |
| 8493 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8494 | Value |= (op & 0x1f); |
| 8495 | break; |
| 8496 | } |
| 8497 | case Hexagon::V6_vdeal: |
| 8498 | case Hexagon::V6_vshuff: { |
| 8499 | // op: Rt32 |
| 8500 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 8501 | Value |= (op & 0x1f) << 16; |
| 8502 | // op: Vy32 |
| 8503 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8504 | Value |= (op & 0x1f) << 8; |
| 8505 | // op: Vx32 |
| 8506 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8507 | Value |= (op & 0x1f); |
| 8508 | break; |
| 8509 | } |
| 8510 | case Hexagon::Y6_l2gcleaninvpa: |
| 8511 | case Hexagon::Y6_l2gcleanpa: { |
| 8512 | // op: Rtt32 |
| 8513 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8514 | Value |= (op & 0x1f) << 8; |
| 8515 | break; |
| 8516 | } |
| 8517 | case Hexagon::S2_valignrb: { |
| 8518 | // op: Rtt32 |
| 8519 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8520 | Value |= (op & 0x1f) << 8; |
| 8521 | // op: Rss32 |
| 8522 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8523 | Value |= (op & 0x1f) << 16; |
| 8524 | // op: Pu4 |
| 8525 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 8526 | Value |= (op & 0x3) << 5; |
| 8527 | // op: Rdd32 |
| 8528 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8529 | Value |= (op & 0x1f); |
| 8530 | break; |
| 8531 | } |
| 8532 | case Hexagon::A2_minp: |
| 8533 | case Hexagon::A2_minup: |
| 8534 | case Hexagon::A2_subp: |
| 8535 | case Hexagon::A2_vmaxb: |
| 8536 | case Hexagon::A2_vmaxh: |
| 8537 | case Hexagon::A2_vmaxub: |
| 8538 | case Hexagon::A2_vmaxuh: |
| 8539 | case Hexagon::A2_vmaxuw: |
| 8540 | case Hexagon::A2_vmaxw: |
| 8541 | case Hexagon::A2_vminb: |
| 8542 | case Hexagon::A2_vminh: |
| 8543 | case Hexagon::A2_vminub: |
| 8544 | case Hexagon::A2_vminuh: |
| 8545 | case Hexagon::A2_vminuw: |
| 8546 | case Hexagon::A2_vminw: |
| 8547 | case Hexagon::A2_vnavgh: |
| 8548 | case Hexagon::A2_vnavghcr: |
| 8549 | case Hexagon::A2_vnavghr: |
| 8550 | case Hexagon::A2_vnavgw: |
| 8551 | case Hexagon::A2_vnavgwcr: |
| 8552 | case Hexagon::A2_vnavgwr: |
| 8553 | case Hexagon::A2_vsubh: |
| 8554 | case Hexagon::A2_vsubhs: |
| 8555 | case Hexagon::A2_vsubub: |
| 8556 | case Hexagon::A2_vsububs: |
| 8557 | case Hexagon::A2_vsubuhs: |
| 8558 | case Hexagon::A2_vsubw: |
| 8559 | case Hexagon::A2_vsubws: |
| 8560 | case Hexagon::A4_andnp: |
| 8561 | case Hexagon::A4_ornp: |
| 8562 | case Hexagon::M2_vabsdiffh: |
| 8563 | case Hexagon::M2_vabsdiffw: |
| 8564 | case Hexagon::M6_vabsdiffb: |
| 8565 | case Hexagon::M6_vabsdiffub: |
| 8566 | case Hexagon::S2_shuffob: |
| 8567 | case Hexagon::S2_shuffoh: { |
| 8568 | // op: Rtt32 |
| 8569 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8570 | Value |= (op & 0x1f) << 8; |
| 8571 | // op: Rss32 |
| 8572 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8573 | Value |= (op & 0x1f) << 16; |
| 8574 | // op: Rdd32 |
| 8575 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8576 | Value |= (op & 0x1f); |
| 8577 | break; |
| 8578 | } |
| 8579 | case Hexagon::A6_vminub_RdP: { |
| 8580 | // op: Rtt32 |
| 8581 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8582 | Value |= (op & 0x1f) << 8; |
| 8583 | // op: Rss32 |
| 8584 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 8585 | Value |= (op & 0x1f) << 16; |
| 8586 | // op: Rdd32 |
| 8587 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8588 | Value |= (op & 0x1f); |
| 8589 | // op: Pe4 |
| 8590 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8591 | Value |= (op & 0x3) << 5; |
| 8592 | break; |
| 8593 | } |
| 8594 | case Hexagon::M4_mpyrr_addr: { |
| 8595 | // op: Ru32 |
| 8596 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8597 | Value |= (op & 0x1f); |
| 8598 | // op: Rs32 |
| 8599 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 8600 | Value |= (op & 0x1f) << 16; |
| 8601 | // op: Ry32 |
| 8602 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8603 | Value |= (op & 0x1f) << 8; |
| 8604 | break; |
| 8605 | } |
| 8606 | case Hexagon::Y2_crswap0: |
| 8607 | case Hexagon::Y4_crswap1: { |
| 8608 | // op: Rx32 |
| 8609 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8610 | Value |= (op & 0x1f) << 16; |
| 8611 | break; |
| 8612 | } |
| 8613 | case Hexagon::Y4_crswap10: { |
| 8614 | // op: Rxx32 |
| 8615 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8616 | Value |= (op & 0x1f) << 16; |
| 8617 | break; |
| 8618 | } |
| 8619 | case Hexagon::Y2_tfrscrr: { |
| 8620 | // op: Ss128 |
| 8621 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8622 | Value |= (op & 0x7f) << 16; |
| 8623 | // op: Rd32 |
| 8624 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8625 | Value |= (op & 0x1f); |
| 8626 | break; |
| 8627 | } |
| 8628 | case Hexagon::Y4_tfrscpp: { |
| 8629 | // op: Sss128 |
| 8630 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8631 | Value |= (op & 0x7f) << 16; |
| 8632 | // op: Rdd32 |
| 8633 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8634 | Value |= (op & 0x1f); |
| 8635 | break; |
| 8636 | } |
| 8637 | case Hexagon::V6_extractw: { |
| 8638 | // op: Vu32 |
| 8639 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8640 | Value |= (op & 0x1f) << 8; |
| 8641 | // op: Rs32 |
| 8642 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8643 | Value |= (op & 0x1f) << 16; |
| 8644 | // op: Rd32 |
| 8645 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8646 | Value |= (op & 0x1f); |
| 8647 | break; |
| 8648 | } |
| 8649 | case Hexagon::V6_vandvrt: { |
| 8650 | // op: Vu32 |
| 8651 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8652 | Value |= (op & 0x1f) << 8; |
| 8653 | // op: Rt32 |
| 8654 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8655 | Value |= (op & 0x1f) << 16; |
| 8656 | // op: Qd4 |
| 8657 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8658 | Value |= (op & 0x3); |
| 8659 | break; |
| 8660 | } |
| 8661 | case Hexagon::V6_get_qfext: |
| 8662 | case Hexagon::V6_set_qfext: |
| 8663 | case Hexagon::V6_vaslh: |
| 8664 | case Hexagon::V6_vaslw: |
| 8665 | case Hexagon::V6_vasrh: |
| 8666 | case Hexagon::V6_vasrw: |
| 8667 | case Hexagon::V6_vdmpybus: |
| 8668 | case Hexagon::V6_vdmpyhb: |
| 8669 | case Hexagon::V6_vdmpyhsat: |
| 8670 | case Hexagon::V6_vdmpyhsusat: |
| 8671 | case Hexagon::V6_vlsrb: |
| 8672 | case Hexagon::V6_vlsrh: |
| 8673 | case Hexagon::V6_vlsrw: |
| 8674 | case Hexagon::V6_vmpy_rt_hf: |
| 8675 | case Hexagon::V6_vmpy_rt_qf16: |
| 8676 | case Hexagon::V6_vmpy_rt_sf: |
| 8677 | case Hexagon::V6_vmpyhsrs: |
| 8678 | case Hexagon::V6_vmpyhss: |
| 8679 | case Hexagon::V6_vmpyihb: |
| 8680 | case Hexagon::V6_vmpyiwb: |
| 8681 | case Hexagon::V6_vmpyiwh: |
| 8682 | case Hexagon::V6_vmpyiwub: |
| 8683 | case Hexagon::V6_vmpyuhe: |
| 8684 | case Hexagon::V6_vrmpybus: |
| 8685 | case Hexagon::V6_vrmpyub: |
| 8686 | case Hexagon::V6_vror: { |
| 8687 | // op: Vu32 |
| 8688 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8689 | Value |= (op & 0x1f) << 8; |
| 8690 | // op: Rt32 |
| 8691 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8692 | Value |= (op & 0x1f) << 16; |
| 8693 | // op: Vd32 |
| 8694 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8695 | Value |= (op & 0x1f); |
| 8696 | break; |
| 8697 | } |
| 8698 | case Hexagon::V6_vmpybus: |
| 8699 | case Hexagon::V6_vmpyh: |
| 8700 | case Hexagon::V6_vmpyub: |
| 8701 | case Hexagon::V6_vmpyuh: { |
| 8702 | // op: Vu32 |
| 8703 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8704 | Value |= (op & 0x1f) << 8; |
| 8705 | // op: Rt32 |
| 8706 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8707 | Value |= (op & 0x1f) << 16; |
| 8708 | // op: Vdd32 |
| 8709 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8710 | Value |= (op & 0x1f); |
| 8711 | break; |
| 8712 | } |
| 8713 | case Hexagon::V6_vrmpyzbb_rt: |
| 8714 | case Hexagon::V6_vrmpyzbub_rt: |
| 8715 | case Hexagon::V6_vrmpyzcb_rt: |
| 8716 | case Hexagon::V6_vrmpyzcbs_rt: |
| 8717 | case Hexagon::V6_vrmpyznb_rt: { |
| 8718 | // op: Vu32 |
| 8719 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8720 | Value |= (op & 0x1f) << 8; |
| 8721 | // op: Rt8 |
| 8722 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8723 | Value |= (op & 0x7) << 16; |
| 8724 | // op: Vdddd32 |
| 8725 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8726 | Value |= (op & 0x1f); |
| 8727 | break; |
| 8728 | } |
| 8729 | case Hexagon::V6_vlut4: { |
| 8730 | // op: Vu32 |
| 8731 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8732 | Value |= (op & 0x1f) << 8; |
| 8733 | // op: Rtt32 |
| 8734 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8735 | Value |= (op & 0x1f) << 16; |
| 8736 | // op: Vd32 |
| 8737 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8738 | Value |= (op & 0x1f); |
| 8739 | break; |
| 8740 | } |
| 8741 | case Hexagon::V6_vrmpybub_rtt: |
| 8742 | case Hexagon::V6_vrmpyub_rtt: { |
| 8743 | // op: Vu32 |
| 8744 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8745 | Value |= (op & 0x1f) << 8; |
| 8746 | // op: Rtt32 |
| 8747 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8748 | Value |= (op & 0x1f) << 16; |
| 8749 | // op: Vdd32 |
| 8750 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8751 | Value |= (op & 0x1f); |
| 8752 | break; |
| 8753 | } |
| 8754 | case Hexagon::V6_vabs_f8: |
| 8755 | case Hexagon::V6_vabs_hf: |
| 8756 | case Hexagon::V6_vabs_qf16_hf: |
| 8757 | case Hexagon::V6_vabs_qf16_qf16: |
| 8758 | case Hexagon::V6_vabs_qf32_qf32: |
| 8759 | case Hexagon::V6_vabs_qf32_sf: |
| 8760 | case Hexagon::V6_vabs_sf: |
| 8761 | case Hexagon::V6_vabsb: |
| 8762 | case Hexagon::V6_vabsb_sat: |
| 8763 | case Hexagon::V6_vabsh: |
| 8764 | case Hexagon::V6_vabsh_sat: |
| 8765 | case Hexagon::V6_vabsw: |
| 8766 | case Hexagon::V6_vabsw_sat: |
| 8767 | case Hexagon::V6_vassign: |
| 8768 | case Hexagon::V6_vassign_fp: |
| 8769 | case Hexagon::V6_vassign_tmp: |
| 8770 | case Hexagon::V6_vcl0h: |
| 8771 | case Hexagon::V6_vcl0w: |
| 8772 | case Hexagon::V6_vconv_f8_qf16: |
| 8773 | case Hexagon::V6_vconv_h_hf: |
| 8774 | case Hexagon::V6_vconv_h_hf_rnd: |
| 8775 | case Hexagon::V6_vconv_hf_h: |
| 8776 | case Hexagon::V6_vconv_hf_qf16: |
| 8777 | case Hexagon::V6_vconv_qf16_hf: |
| 8778 | case Hexagon::V6_vconv_qf16_qf16: |
| 8779 | case Hexagon::V6_vconv_qf32_qf32: |
| 8780 | case Hexagon::V6_vconv_qf32_sf: |
| 8781 | case Hexagon::V6_vconv_sf_qf32: |
| 8782 | case Hexagon::V6_vconv_sf_w: |
| 8783 | case Hexagon::V6_vconv_w_sf: |
| 8784 | case Hexagon::V6_vcvt_h_hf: |
| 8785 | case Hexagon::V6_vcvt_hf_h: |
| 8786 | case Hexagon::V6_vcvt_hf_uh: |
| 8787 | case Hexagon::V6_vcvt_uh_hf: |
| 8788 | case Hexagon::V6_vdealb: |
| 8789 | case Hexagon::V6_vdealh: |
| 8790 | case Hexagon::V6_vfneg_f8: |
| 8791 | case Hexagon::V6_vfneg_hf: |
| 8792 | case Hexagon::V6_vfneg_sf: |
| 8793 | case Hexagon::V6_vilog2_hf: |
| 8794 | case Hexagon::V6_vilog2_qf16: |
| 8795 | case Hexagon::V6_vilog2_qf32: |
| 8796 | case Hexagon::V6_vilog2_sf: |
| 8797 | case Hexagon::V6_vneg_qf16_hf: |
| 8798 | case Hexagon::V6_vneg_qf16_qf16: |
| 8799 | case Hexagon::V6_vneg_qf32_qf32: |
| 8800 | case Hexagon::V6_vneg_qf32_sf: |
| 8801 | case Hexagon::V6_vnormamth: |
| 8802 | case Hexagon::V6_vnormamtw: |
| 8803 | case Hexagon::V6_vnot: |
| 8804 | case Hexagon::V6_vpopcounth: |
| 8805 | case Hexagon::V6_vshuffb: |
| 8806 | case Hexagon::V6_vshuffh: { |
| 8807 | // op: Vu32 |
| 8808 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8809 | Value |= (op & 0x1f) << 8; |
| 8810 | // op: Vd32 |
| 8811 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8812 | Value |= (op & 0x1f); |
| 8813 | break; |
| 8814 | } |
| 8815 | case Hexagon::V6_vconv_qf16_f8: |
| 8816 | case Hexagon::V6_vcvt2_hf_b: |
| 8817 | case Hexagon::V6_vcvt2_hf_ub: |
| 8818 | case Hexagon::V6_vcvt_hf_b: |
| 8819 | case Hexagon::V6_vcvt_hf_f8: |
| 8820 | case Hexagon::V6_vcvt_hf_ub: |
| 8821 | case Hexagon::V6_vcvt_sf_hf: |
| 8822 | case Hexagon::V6_vsb: |
| 8823 | case Hexagon::V6_vsh: |
| 8824 | case Hexagon::V6_vunpackb: |
| 8825 | case Hexagon::V6_vunpackh: |
| 8826 | case Hexagon::V6_vunpackub: |
| 8827 | case Hexagon::V6_vunpackuh: |
| 8828 | case Hexagon::V6_vzb: |
| 8829 | case Hexagon::V6_vzh: { |
| 8830 | // op: Vu32 |
| 8831 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8832 | Value |= (op & 0x1f) << 8; |
| 8833 | // op: Vdd32 |
| 8834 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8835 | Value |= (op & 0x1f); |
| 8836 | break; |
| 8837 | } |
| 8838 | case Hexagon::V6_veqb: |
| 8839 | case Hexagon::V6_veqh: |
| 8840 | case Hexagon::V6_veqhf: |
| 8841 | case Hexagon::V6_veqsf: |
| 8842 | case Hexagon::V6_veqw: |
| 8843 | case Hexagon::V6_vgtb: |
| 8844 | case Hexagon::V6_vgtbf: |
| 8845 | case Hexagon::V6_vgth: |
| 8846 | case Hexagon::V6_vgthf: |
| 8847 | case Hexagon::V6_vgtsf: |
| 8848 | case Hexagon::V6_vgtub: |
| 8849 | case Hexagon::V6_vgtuh: |
| 8850 | case Hexagon::V6_vgtuw: |
| 8851 | case Hexagon::V6_vgtw: { |
| 8852 | // op: Vu32 |
| 8853 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8854 | Value |= (op & 0x1f) << 8; |
| 8855 | // op: Vv32 |
| 8856 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8857 | Value |= (op & 0x1f) << 16; |
| 8858 | // op: Qd4 |
| 8859 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8860 | Value |= (op & 0x3); |
| 8861 | break; |
| 8862 | } |
| 8863 | case Hexagon::V6_vaddcarrysat: { |
| 8864 | // op: Vu32 |
| 8865 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8866 | Value |= (op & 0x1f) << 8; |
| 8867 | // op: Vv32 |
| 8868 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8869 | Value |= (op & 0x1f) << 16; |
| 8870 | // op: Qs4 |
| 8871 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 8872 | Value |= (op & 0x3) << 5; |
| 8873 | // op: Vd32 |
| 8874 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8875 | Value |= (op & 0x1f); |
| 8876 | break; |
| 8877 | } |
| 8878 | case Hexagon::V6_vabsdiffh: |
| 8879 | case Hexagon::V6_vabsdiffub: |
| 8880 | case Hexagon::V6_vabsdiffuh: |
| 8881 | case Hexagon::V6_vabsdiffw: |
| 8882 | case Hexagon::V6_vadd_hf: |
| 8883 | case Hexagon::V6_vadd_hf_hf: |
| 8884 | case Hexagon::V6_vadd_qf16: |
| 8885 | case Hexagon::V6_vadd_qf16_mix: |
| 8886 | case Hexagon::V6_vadd_qf32: |
| 8887 | case Hexagon::V6_vadd_qf32_mix: |
| 8888 | case Hexagon::V6_vadd_sf: |
| 8889 | case Hexagon::V6_vadd_sf_sf: |
| 8890 | case Hexagon::V6_vaddb: |
| 8891 | case Hexagon::V6_vaddbsat: |
| 8892 | case Hexagon::V6_vaddclbh: |
| 8893 | case Hexagon::V6_vaddclbw: |
| 8894 | case Hexagon::V6_vaddh: |
| 8895 | case Hexagon::V6_vaddhsat: |
| 8896 | case Hexagon::V6_vaddubsat: |
| 8897 | case Hexagon::V6_vaddububb_sat: |
| 8898 | case Hexagon::V6_vadduhsat: |
| 8899 | case Hexagon::V6_vadduwsat: |
| 8900 | case Hexagon::V6_vaddw: |
| 8901 | case Hexagon::V6_vaddwsat: |
| 8902 | case Hexagon::V6_vand: |
| 8903 | case Hexagon::V6_vaslhv: |
| 8904 | case Hexagon::V6_vaslwv: |
| 8905 | case Hexagon::V6_vasrhv: |
| 8906 | case Hexagon::V6_vasrwv: |
| 8907 | case Hexagon::V6_vavgb: |
| 8908 | case Hexagon::V6_vavgbrnd: |
| 8909 | case Hexagon::V6_vavgh: |
| 8910 | case Hexagon::V6_vavghrnd: |
| 8911 | case Hexagon::V6_vavgub: |
| 8912 | case Hexagon::V6_vavgubrnd: |
| 8913 | case Hexagon::V6_vavguh: |
| 8914 | case Hexagon::V6_vavguhrnd: |
| 8915 | case Hexagon::V6_vavguw: |
| 8916 | case Hexagon::V6_vavguwrnd: |
| 8917 | case Hexagon::V6_vavgw: |
| 8918 | case Hexagon::V6_vavgwrnd: |
| 8919 | case Hexagon::V6_vcvt2_b_hf: |
| 8920 | case Hexagon::V6_vcvt2_ub_hf: |
| 8921 | case Hexagon::V6_vcvt_b_hf: |
| 8922 | case Hexagon::V6_vcvt_bf_sf: |
| 8923 | case Hexagon::V6_vcvt_f8_hf: |
| 8924 | case Hexagon::V6_vcvt_hf_sf: |
| 8925 | case Hexagon::V6_vcvt_ub_hf: |
| 8926 | case Hexagon::V6_vdealb4w: |
| 8927 | case Hexagon::V6_vdelta: |
| 8928 | case Hexagon::V6_vdmpy_sf_hf: |
| 8929 | case Hexagon::V6_vdmpyhvsat: |
| 8930 | case Hexagon::V6_vfmax_f8: |
| 8931 | case Hexagon::V6_vfmax_hf: |
| 8932 | case Hexagon::V6_vfmax_sf: |
| 8933 | case Hexagon::V6_vfmin_f8: |
| 8934 | case Hexagon::V6_vfmin_hf: |
| 8935 | case Hexagon::V6_vfmin_sf: |
| 8936 | case Hexagon::V6_vlsrhv: |
| 8937 | case Hexagon::V6_vlsrwv: |
| 8938 | case Hexagon::V6_vmax_bf: |
| 8939 | case Hexagon::V6_vmax_hf: |
| 8940 | case Hexagon::V6_vmax_sf: |
| 8941 | case Hexagon::V6_vmaxb: |
| 8942 | case Hexagon::V6_vmaxh: |
| 8943 | case Hexagon::V6_vmaxub: |
| 8944 | case Hexagon::V6_vmaxuh: |
| 8945 | case Hexagon::V6_vmaxw: |
| 8946 | case Hexagon::V6_vmerge_qf: |
| 8947 | case Hexagon::V6_vmin_bf: |
| 8948 | case Hexagon::V6_vmin_hf: |
| 8949 | case Hexagon::V6_vmin_sf: |
| 8950 | case Hexagon::V6_vminb: |
| 8951 | case Hexagon::V6_vminh: |
| 8952 | case Hexagon::V6_vminub: |
| 8953 | case Hexagon::V6_vminuh: |
| 8954 | case Hexagon::V6_vminw: |
| 8955 | case Hexagon::V6_vmpy_hf_hf: |
| 8956 | case Hexagon::V6_vmpy_qf16: |
| 8957 | case Hexagon::V6_vmpy_qf16_hf: |
| 8958 | case Hexagon::V6_vmpy_qf16_mix_hf: |
| 8959 | case Hexagon::V6_vmpy_qf32: |
| 8960 | case Hexagon::V6_vmpy_qf32_sf: |
| 8961 | case Hexagon::V6_vmpy_sf_sf: |
| 8962 | case Hexagon::V6_vmpyewuh: |
| 8963 | case Hexagon::V6_vmpyhvsrs: |
| 8964 | case Hexagon::V6_vmpyieoh: |
| 8965 | case Hexagon::V6_vmpyiewuh: |
| 8966 | case Hexagon::V6_vmpyih: |
| 8967 | case Hexagon::V6_vmpyiowh: |
| 8968 | case Hexagon::V6_vmpyowh: |
| 8969 | case Hexagon::V6_vmpyowh_rnd: |
| 8970 | case Hexagon::V6_vmpyuhvs: |
| 8971 | case Hexagon::V6_vnavgb: |
| 8972 | case Hexagon::V6_vnavgh: |
| 8973 | case Hexagon::V6_vnavgub: |
| 8974 | case Hexagon::V6_vnavgw: |
| 8975 | case Hexagon::V6_vor: |
| 8976 | case Hexagon::V6_vpackeb: |
| 8977 | case Hexagon::V6_vpackeh: |
| 8978 | case Hexagon::V6_vpackhb_sat: |
| 8979 | case Hexagon::V6_vpackhub_sat: |
| 8980 | case Hexagon::V6_vpackob: |
| 8981 | case Hexagon::V6_vpackoh: |
| 8982 | case Hexagon::V6_vpackwh_sat: |
| 8983 | case Hexagon::V6_vpackwuh_sat: |
| 8984 | case Hexagon::V6_vrdelta: |
| 8985 | case Hexagon::V6_vrmpybusv: |
| 8986 | case Hexagon::V6_vrmpybv: |
| 8987 | case Hexagon::V6_vrmpyubv: |
| 8988 | case Hexagon::V6_vrotr: |
| 8989 | case Hexagon::V6_vroundhb: |
| 8990 | case Hexagon::V6_vroundhub: |
| 8991 | case Hexagon::V6_vrounduhub: |
| 8992 | case Hexagon::V6_vrounduwuh: |
| 8993 | case Hexagon::V6_vroundwh: |
| 8994 | case Hexagon::V6_vroundwuh: |
| 8995 | case Hexagon::V6_vsatdw: |
| 8996 | case Hexagon::V6_vsathub: |
| 8997 | case Hexagon::V6_vsatuwuh: |
| 8998 | case Hexagon::V6_vsatwh: |
| 8999 | case Hexagon::V6_vshufeh: |
| 9000 | case Hexagon::V6_vshuffeb: |
| 9001 | case Hexagon::V6_vshuffob: |
| 9002 | case Hexagon::V6_vshufoh: |
| 9003 | case Hexagon::V6_vsub_hf: |
| 9004 | case Hexagon::V6_vsub_hf_hf: |
| 9005 | case Hexagon::V6_vsub_hf_mix: |
| 9006 | case Hexagon::V6_vsub_qf16: |
| 9007 | case Hexagon::V6_vsub_qf16_mix: |
| 9008 | case Hexagon::V6_vsub_qf32: |
| 9009 | case Hexagon::V6_vsub_qf32_mix: |
| 9010 | case Hexagon::V6_vsub_sf: |
| 9011 | case Hexagon::V6_vsub_sf_mix: |
| 9012 | case Hexagon::V6_vsub_sf_sf: |
| 9013 | case Hexagon::V6_vsubb: |
| 9014 | case Hexagon::V6_vsubbsat: |
| 9015 | case Hexagon::V6_vsubh: |
| 9016 | case Hexagon::V6_vsubhsat: |
| 9017 | case Hexagon::V6_vsububsat: |
| 9018 | case Hexagon::V6_vsubububb_sat: |
| 9019 | case Hexagon::V6_vsubuhsat: |
| 9020 | case Hexagon::V6_vsubuwsat: |
| 9021 | case Hexagon::V6_vsubw: |
| 9022 | case Hexagon::V6_vsubwsat: |
| 9023 | case Hexagon::V6_vxor: { |
| 9024 | // op: Vu32 |
| 9025 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 9026 | Value |= (op & 0x1f) << 8; |
| 9027 | // op: Vv32 |
| 9028 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 9029 | Value |= (op & 0x1f) << 16; |
| 9030 | // op: Vd32 |
| 9031 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 9032 | Value |= (op & 0x1f); |
| 9033 | break; |
| 9034 | } |
| 9035 | case Hexagon::V6_vadd_hf_f8: |
| 9036 | case Hexagon::V6_vadd_sf_bf: |
| 9037 | case Hexagon::V6_vadd_sf_hf: |
| 9038 | case Hexagon::V6_vaddhw: |
| 9039 | case Hexagon::V6_vaddubh: |
| 9040 | case Hexagon::V6_vadduhw: |
| 9041 | case Hexagon::V6_vcombine: |
| 9042 | case Hexagon::V6_vcombine_tmp: |
| 9043 | case Hexagon::V6_vmpy_hf_f8: |
| 9044 | case Hexagon::V6_vmpy_qf32_hf: |
| 9045 | case Hexagon::V6_vmpy_qf32_mix_hf: |
| 9046 | case Hexagon::V6_vmpy_qf32_qf16: |
| 9047 | case Hexagon::V6_vmpy_sf_bf: |
| 9048 | case Hexagon::V6_vmpy_sf_hf: |
| 9049 | case Hexagon::V6_vmpybusv: |
| 9050 | case Hexagon::V6_vmpybv: |
| 9051 | case Hexagon::V6_vmpyewuh_64: |
| 9052 | case Hexagon::V6_vmpyhus: |
| 9053 | case Hexagon::V6_vmpyhv: |
| 9054 | case Hexagon::V6_vmpyubv: |
| 9055 | case Hexagon::V6_vmpyuhv: |
| 9056 | case Hexagon::V6_vshufoeb: |
| 9057 | case Hexagon::V6_vshufoeh: |
| 9058 | case Hexagon::V6_vsub_hf_f8: |
| 9059 | case Hexagon::V6_vsub_sf_bf: |
| 9060 | case Hexagon::V6_vsub_sf_hf: |
| 9061 | case Hexagon::V6_vsubhw: |
| 9062 | case Hexagon::V6_vsububh: |
| 9063 | case Hexagon::V6_vsubuhw: { |
| 9064 | // op: Vu32 |
| 9065 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 9066 | Value |= (op & 0x1f) << 8; |
| 9067 | // op: Vv32 |
| 9068 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 9069 | Value |= (op & 0x1f) << 16; |
| 9070 | // op: Vdd32 |
| 9071 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 9072 | Value |= (op & 0x1f); |
| 9073 | break; |
| 9074 | } |
| 9075 | case Hexagon::V6_valign4: |
| 9076 | case Hexagon::V6_valignb: |
| 9077 | case Hexagon::V6_vasrhbrndsat: |
| 9078 | case Hexagon::V6_vasrhbsat: |
| 9079 | case Hexagon::V6_vasrhubrndsat: |
| 9080 | case Hexagon::V6_vasrhubsat: |
| 9081 | case Hexagon::V6_vasruhubrndsat: |
| 9082 | case Hexagon::V6_vasruhubsat: |
| 9083 | case Hexagon::V6_vasruwuhrndsat: |
| 9084 | case Hexagon::V6_vasruwuhsat: |
| 9085 | case Hexagon::V6_vasrwh: |
| 9086 | case Hexagon::V6_vasrwhrndsat: |
| 9087 | case Hexagon::V6_vasrwhsat: |
| 9088 | case Hexagon::V6_vasrwuhrndsat: |
| 9089 | case Hexagon::V6_vasrwuhsat: |
| 9090 | case Hexagon::V6_vlalignb: |
| 9091 | case Hexagon::V6_vlutvvb: |
| 9092 | case Hexagon::V6_vlutvvb_nm: { |
| 9093 | // op: Vu32 |
| 9094 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 9095 | Value |= (op & 0x1f) << 8; |
| 9096 | // op: Vv32 |
| 9097 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 9098 | Value |= (op & 0x1f) << 19; |
| 9099 | // op: Rt8 |
| 9100 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 9101 | Value |= (op & 0x7) << 16; |
| 9102 | // op: Vd32 |
| 9103 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 9104 | Value |= (op & 0x1f); |
| 9105 | break; |
| 9106 | } |
| 9107 | case Hexagon::V6_vdealvdd: |
| 9108 | case Hexagon::V6_vlutvwh: |
| 9109 | case Hexagon::V6_vlutvwh_nm: |
| 9110 | case Hexagon::V6_vshuffvdd: { |
| 9111 | // op: Vu32 |
| 9112 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 9113 | Value |= (op & 0x1f) << 8; |
| 9114 | // op: Vv32 |
| 9115 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 9116 | Value |= (op & 0x1f) << 19; |
| 9117 | // op: Rt8 |
| 9118 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 9119 | Value |= (op & 0x7) << 16; |
| 9120 | // op: Vdd32 |
| 9121 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 9122 | Value |= (op & 0x1f); |
| 9123 | break; |
| 9124 | } |
| 9125 | case Hexagon::V6_vandvrt_acc: { |
| 9126 | // op: Vu32 |
| 9127 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 9128 | Value |= (op & 0x1f) << 8; |
| 9129 | // op: Rt32 |
| 9130 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 9131 | Value |= (op & 0x1f) << 16; |
| 9132 | // op: Qx4 |
| 9133 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 9134 | Value |= (op & 0x3); |
| 9135 | break; |
| 9136 | } |
| 9137 | case Hexagon::V6_get_qfext_oracc: |
| 9138 | case Hexagon::V6_vaslh_acc: |
| 9139 | case Hexagon::V6_vaslw_acc: |
| 9140 | case Hexagon::V6_vasrh_acc: |
| 9141 | case Hexagon::V6_vasrw_acc: |
| 9142 | case Hexagon::V6_vdmpybus_acc: |
| 9143 | case Hexagon::V6_vdmpyhb_acc: |
| 9144 | case Hexagon::V6_vdmpyhsat_acc: |
| 9145 | case Hexagon::V6_vdmpyhsusat_acc: |
| 9146 | case Hexagon::V6_vmpyihb_acc: |
| 9147 | case Hexagon::V6_vmpyiwb_acc: |
| 9148 | case Hexagon::V6_vmpyiwh_acc: |
| 9149 | case Hexagon::V6_vmpyiwub_acc: |
| 9150 | case Hexagon::V6_vmpyuhe_acc: |
| 9151 | case Hexagon::V6_vrmpybus_acc: |
| 9152 | case Hexagon::V6_vrmpyub_acc: { |
| 9153 | // op: Vu32 |
| 9154 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 9155 | Value |= (op & 0x1f) << 8; |
| 9156 | // op: Rt32 |
| 9157 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 9158 | Value |= (op & 0x1f) << 16; |
| 9159 | // op: Vx32 |
| 9160 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 9161 | Value |= (op & 0x1f); |
| 9162 | break; |
| 9163 | } |
| 9164 | case Hexagon::V6_vmpybus_acc: |
| 9165 | case Hexagon::V6_vmpyh_acc: |
| 9166 | case Hexagon::V6_vmpyhsat_acc: |
| 9167 | case Hexagon::V6_vmpyub_acc: |
| 9168 | case Hexagon::V6_vmpyuh_acc: { |
| 9169 | // op: Vu32 |
| 9170 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 9171 | Value |= (op & 0x1f) << 8; |
| 9172 | // op: Rt32 |
| 9173 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 9174 | Value |= (op & 0x1f) << 16; |
| 9175 | // op: Vxx32 |
| 9176 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 9177 | Value |= (op & 0x1f); |
| 9178 | break; |
| 9179 | } |
| 9180 | case Hexagon::V6_vrmpyzbb_rt_acc: |
| 9181 | case Hexagon::V6_vrmpyzbub_rt_acc: |
| 9182 | case Hexagon::V6_vrmpyzcb_rt_acc: |
| 9183 | case Hexagon::V6_vrmpyzcbs_rt_acc: |
| 9184 | case Hexagon::V6_vrmpyznb_rt_acc: { |
| 9185 | // op: Vu32 |
| 9186 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 9187 | Value |= (op & 0x1f) << 8; |
| 9188 | // op: Rt8 |
| 9189 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 9190 | Value |= (op & 0x7) << 16; |
| 9191 | // op: Vyyyy32 |
| 9192 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 9193 | Value |= (op & 0x1f); |
| 9194 | break; |
| 9195 | } |
| 9196 | case Hexagon::V6_vmpahhsat: |
| 9197 | case Hexagon::V6_vmpauhuhsat: |
| 9198 | case Hexagon::V6_vmpsuhuhsat: { |
| 9199 | // op: Vu32 |
| 9200 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 9201 | Value |= (op & 0x1f) << 8; |
| 9202 | // op: Rtt32 |
| 9203 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 9204 | Value |= (op & 0x1f) << 16; |
| 9205 | // op: Vx32 |
| 9206 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 9207 | Value |= (op & 0x1f); |
| 9208 | break; |
| 9209 | } |
| 9210 | case Hexagon::V6_vrmpybub_rtt_acc: |
| 9211 | case Hexagon::V6_vrmpyub_rtt_acc: { |
| 9212 | // op: Vu32 |
| 9213 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 9214 | Value |= (op & 0x1f) << 8; |
| 9215 | // op: Rtt32 |
| 9216 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 9217 | Value |= (op & 0x1f) << 16; |
| 9218 | // op: Vxx32 |
| 9219 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 9220 | Value |= (op & 0x1f); |
| 9221 | break; |
| 9222 | } |
| 9223 | case Hexagon::V6_vrmpyzbb_rx: |
| 9224 | case Hexagon::V6_vrmpyzbub_rx: |
| 9225 | case Hexagon::V6_vrmpyzcb_rx: |
| 9226 | case Hexagon::V6_vrmpyzcbs_rx: |
| 9227 | case Hexagon::V6_vrmpyznb_rx: { |
| 9228 | // op: Vu32 |
| 9229 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 9230 | Value |= (op & 0x1f) << 8; |
| 9231 | // op: Vdddd32 |
| 9232 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 9233 | Value |= (op & 0x1f); |
| 9234 | // op: Rx8 |
| 9235 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 9236 | Value |= (op & 0x7) << 16; |
| 9237 | break; |
| 9238 | } |
| 9239 | case Hexagon::V6_veqb_and: |
| 9240 | case Hexagon::V6_veqb_or: |
| 9241 | case Hexagon::V6_veqb_xor: |
| 9242 | case Hexagon::V6_veqh_and: |
| 9243 | case Hexagon::V6_veqh_or: |
| 9244 | case Hexagon::V6_veqh_xor: |
| 9245 | case Hexagon::V6_veqhf_and: |
| 9246 | case Hexagon::V6_veqhf_or: |
| 9247 | case Hexagon::V6_veqhf_xor: |
| 9248 | case Hexagon::V6_veqsf_and: |
| 9249 | case Hexagon::V6_veqsf_or: |
| 9250 | case Hexagon::V6_veqsf_xor: |
| 9251 | case Hexagon::V6_veqw_and: |
| 9252 | case Hexagon::V6_veqw_or: |
| 9253 | case Hexagon::V6_veqw_xor: |
| 9254 | case Hexagon::V6_vgtb_and: |
| 9255 | case Hexagon::V6_vgtb_or: |
| 9256 | case Hexagon::V6_vgtb_xor: |
| 9257 | case Hexagon::V6_vgtbf_and: |
| 9258 | case Hexagon::V6_vgtbf_or: |
| 9259 | case Hexagon::V6_vgtbf_xor: |
| 9260 | case Hexagon::V6_vgth_and: |
| 9261 | case Hexagon::V6_vgth_or: |
| 9262 | case Hexagon::V6_vgth_xor: |
| 9263 | case Hexagon::V6_vgthf_and: |
| 9264 | case Hexagon::V6_vgthf_or: |
| 9265 | case Hexagon::V6_vgthf_xor: |
| 9266 | case Hexagon::V6_vgtsf_and: |
| 9267 | case Hexagon::V6_vgtsf_or: |
| 9268 | case Hexagon::V6_vgtsf_xor: |
| 9269 | case Hexagon::V6_vgtub_and: |
| 9270 | case Hexagon::V6_vgtub_or: |
| 9271 | case Hexagon::V6_vgtub_xor: |
| 9272 | case Hexagon::V6_vgtuh_and: |
| 9273 | case Hexagon::V6_vgtuh_or: |
| 9274 | case Hexagon::V6_vgtuh_xor: |
| 9275 | case Hexagon::V6_vgtuw_and: |
| 9276 | case Hexagon::V6_vgtuw_or: |
| 9277 | case Hexagon::V6_vgtuw_xor: |
| 9278 | case Hexagon::V6_vgtw_and: |
| 9279 | case Hexagon::V6_vgtw_or: |
| 9280 | case Hexagon::V6_vgtw_xor: { |
| 9281 | // op: Vu32 |
| 9282 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 9283 | Value |= (op & 0x1f) << 8; |
| 9284 | // op: Vv32 |
| 9285 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 9286 | Value |= (op & 0x1f) << 16; |
| 9287 | // op: Qx4 |
| 9288 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 9289 | Value |= (op & 0x3); |
| 9290 | break; |
| 9291 | } |
| 9292 | case Hexagon::V6_vaddcarryo: |
| 9293 | case Hexagon::V6_vsubcarryo: { |
| 9294 | // op: Vu32 |
| 9295 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 9296 | Value |= (op & 0x1f) << 8; |
| 9297 | // op: Vv32 |
| 9298 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 9299 | Value |= (op & 0x1f) << 16; |
| 9300 | // op: Vd32 |
| 9301 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 9302 | Value |= (op & 0x1f); |
| 9303 | // op: Qe4 |
| 9304 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 9305 | Value |= (op & 0x3) << 5; |
| 9306 | break; |
| 9307 | } |
| 9308 | case Hexagon::V6_vaddcarry: |
| 9309 | case Hexagon::V6_vsubcarry: { |
| 9310 | // op: Vu32 |
| 9311 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 9312 | Value |= (op & 0x1f) << 8; |
| 9313 | // op: Vv32 |
| 9314 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 9315 | Value |= (op & 0x1f) << 16; |
| 9316 | // op: Vd32 |
| 9317 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 9318 | Value |= (op & 0x1f); |
| 9319 | // op: Qx4 |
| 9320 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 9321 | Value |= (op & 0x3) << 5; |
| 9322 | break; |
| 9323 | } |
| 9324 | case Hexagon::V6_vdmpy_sf_hf_acc: |
| 9325 | case Hexagon::V6_vdmpyhvsat_acc: |
| 9326 | case Hexagon::V6_vmpy_hf_hf_acc: |
| 9327 | case Hexagon::V6_vmpyiewh_acc: |
| 9328 | case Hexagon::V6_vmpyiewuh_acc: |
| 9329 | case Hexagon::V6_vmpyih_acc: |
| 9330 | case Hexagon::V6_vmpyowh_rnd_sacc: |
| 9331 | case Hexagon::V6_vmpyowh_sacc: |
| 9332 | case Hexagon::V6_vrmpybusv_acc: |
| 9333 | case Hexagon::V6_vrmpybv_acc: |
| 9334 | case Hexagon::V6_vrmpyubv_acc: { |
| 9335 | // op: Vu32 |
| 9336 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 9337 | Value |= (op & 0x1f) << 8; |
| 9338 | // op: Vv32 |
| 9339 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 9340 | Value |= (op & 0x1f) << 16; |
| 9341 | // op: Vx32 |
| 9342 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 9343 | Value |= (op & 0x1f); |
| 9344 | break; |
| 9345 | } |
| 9346 | case Hexagon::V6_vaddhw_acc: |
| 9347 | case Hexagon::V6_vaddubh_acc: |
| 9348 | case Hexagon::V6_vadduhw_acc: |
| 9349 | case Hexagon::V6_vasr_into: |
| 9350 | case Hexagon::V6_vmpy_hf_f8_acc: |
| 9351 | case Hexagon::V6_vmpy_sf_bf_acc: |
| 9352 | case Hexagon::V6_vmpy_sf_hf_acc: |
| 9353 | case Hexagon::V6_vmpybusv_acc: |
| 9354 | case Hexagon::V6_vmpybv_acc: |
| 9355 | case Hexagon::V6_vmpyhus_acc: |
| 9356 | case Hexagon::V6_vmpyhv_acc: |
| 9357 | case Hexagon::V6_vmpyowh_64_acc: |
| 9358 | case Hexagon::V6_vmpyubv_acc: |
| 9359 | case Hexagon::V6_vmpyuhv_acc: { |
| 9360 | // op: Vu32 |
| 9361 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 9362 | Value |= (op & 0x1f) << 8; |
| 9363 | // op: Vv32 |
| 9364 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 9365 | Value |= (op & 0x1f) << 16; |
| 9366 | // op: Vxx32 |
| 9367 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 9368 | Value |= (op & 0x1f); |
| 9369 | break; |
| 9370 | } |
| 9371 | case Hexagon::V6_vlutvvb_oracc: { |
| 9372 | // op: Vu32 |
| 9373 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 9374 | Value |= (op & 0x1f) << 8; |
| 9375 | // op: Vv32 |
| 9376 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 9377 | Value |= (op & 0x1f) << 19; |
| 9378 | // op: Rt8 |
| 9379 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 9380 | Value |= (op & 0x7) << 16; |
| 9381 | // op: Vx32 |
| 9382 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 9383 | Value |= (op & 0x1f); |
| 9384 | break; |
| 9385 | } |
| 9386 | case Hexagon::V6_vlutvwh_oracc: { |
| 9387 | // op: Vu32 |
| 9388 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 9389 | Value |= (op & 0x1f) << 8; |
| 9390 | // op: Vv32 |
| 9391 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 9392 | Value |= (op & 0x1f) << 19; |
| 9393 | // op: Rt8 |
| 9394 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 9395 | Value |= (op & 0x7) << 16; |
| 9396 | // op: Vxx32 |
| 9397 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 9398 | Value |= (op & 0x1f); |
| 9399 | break; |
| 9400 | } |
| 9401 | case Hexagon::V6_vunpackob: |
| 9402 | case Hexagon::V6_vunpackoh: { |
| 9403 | // op: Vu32 |
| 9404 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 9405 | Value |= (op & 0x1f) << 8; |
| 9406 | // op: Vxx32 |
| 9407 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 9408 | Value |= (op & 0x1f); |
| 9409 | break; |
| 9410 | } |
| 9411 | case Hexagon::V6_vrmpyzbb_rx_acc: |
| 9412 | case Hexagon::V6_vrmpyzbub_rx_acc: |
| 9413 | case Hexagon::V6_vrmpyzcb_rx_acc: |
| 9414 | case Hexagon::V6_vrmpyzcbs_rx_acc: |
| 9415 | case Hexagon::V6_vrmpyznb_rx_acc: { |
| 9416 | // op: Vu32 |
| 9417 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 9418 | Value |= (op & 0x1f) << 8; |
| 9419 | // op: Vyyyy32 |
| 9420 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 9421 | Value |= (op & 0x1f); |
| 9422 | // op: Rx8 |
| 9423 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 9424 | Value |= (op & 0x7) << 16; |
| 9425 | break; |
| 9426 | } |
| 9427 | case Hexagon::V6_vdmpyhisat: |
| 9428 | case Hexagon::V6_vdmpyhsuisat: { |
| 9429 | // op: Vuu32 |
| 9430 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 9431 | Value |= (op & 0x1f) << 8; |
| 9432 | // op: Rt32 |
| 9433 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 9434 | Value |= (op & 0x1f) << 16; |
| 9435 | // op: Vd32 |
| 9436 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 9437 | Value |= (op & 0x1f); |
| 9438 | break; |
| 9439 | } |
| 9440 | case Hexagon::V6_vdmpybus_dv: |
| 9441 | case Hexagon::V6_vdmpyhb_dv: |
| 9442 | case Hexagon::V6_vdsaduh: |
| 9443 | case Hexagon::V6_vmpabus: |
| 9444 | case Hexagon::V6_vmpabuu: |
| 9445 | case Hexagon::V6_vmpahb: |
| 9446 | case Hexagon::V6_vmpauhb: |
| 9447 | case Hexagon::V6_vtmpyb: |
| 9448 | case Hexagon::V6_vtmpybus: |
| 9449 | case Hexagon::V6_vtmpyhb: { |
| 9450 | // op: Vuu32 |
| 9451 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 9452 | Value |= (op & 0x1f) << 8; |
| 9453 | // op: Rt32 |
| 9454 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 9455 | Value |= (op & 0x1f) << 16; |
| 9456 | // op: Vdd32 |
| 9457 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 9458 | Value |= (op & 0x1f); |
| 9459 | break; |
| 9460 | } |
| 9461 | case Hexagon::V6_vconv_bf_qf32: |
| 9462 | case Hexagon::V6_vconv_hf_qf32: { |
| 9463 | // op: Vuu32 |
| 9464 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 9465 | Value |= (op & 0x1f) << 8; |
| 9466 | // op: Vd32 |
| 9467 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 9468 | Value |= (op & 0x1f); |
| 9469 | break; |
| 9470 | } |
| 9471 | case Hexagon::V6_vasrvuhubrndsat: |
| 9472 | case Hexagon::V6_vasrvuhubsat: |
| 9473 | case Hexagon::V6_vasrvwuhrndsat: |
| 9474 | case Hexagon::V6_vasrvwuhsat: { |
| 9475 | // op: Vuu32 |
| 9476 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 9477 | Value |= (op & 0x1f) << 8; |
| 9478 | // op: Vv32 |
| 9479 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 9480 | Value |= (op & 0x1f) << 16; |
| 9481 | // op: Vd32 |
| 9482 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 9483 | Value |= (op & 0x1f); |
| 9484 | break; |
| 9485 | } |
| 9486 | case Hexagon::V6_vaddb_dv: |
| 9487 | case Hexagon::V6_vaddbsat_dv: |
| 9488 | case Hexagon::V6_vaddh_dv: |
| 9489 | case Hexagon::V6_vaddhsat_dv: |
| 9490 | case Hexagon::V6_vaddubsat_dv: |
| 9491 | case Hexagon::V6_vadduhsat_dv: |
| 9492 | case Hexagon::V6_vadduwsat_dv: |
| 9493 | case Hexagon::V6_vaddw_dv: |
| 9494 | case Hexagon::V6_vaddwsat_dv: |
| 9495 | case Hexagon::V6_vmpabusv: |
| 9496 | case Hexagon::V6_vmpabuuv: |
| 9497 | case Hexagon::V6_vsubb_dv: |
| 9498 | case Hexagon::V6_vsubbsat_dv: |
| 9499 | case Hexagon::V6_vsubh_dv: |
| 9500 | case Hexagon::V6_vsubhsat_dv: |
| 9501 | case Hexagon::V6_vsububsat_dv: |
| 9502 | case Hexagon::V6_vsubuhsat_dv: |
| 9503 | case Hexagon::V6_vsubuwsat_dv: |
| 9504 | case Hexagon::V6_vsubw_dv: |
| 9505 | case Hexagon::V6_vsubwsat_dv: { |
| 9506 | // op: Vuu32 |
| 9507 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 9508 | Value |= (op & 0x1f) << 8; |
| 9509 | // op: Vvv32 |
| 9510 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 9511 | Value |= (op & 0x1f) << 16; |
| 9512 | // op: Vdd32 |
| 9513 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 9514 | Value |= (op & 0x1f); |
| 9515 | break; |
| 9516 | } |
| 9517 | case Hexagon::V6_vdmpyhisat_acc: |
| 9518 | case Hexagon::V6_vdmpyhsuisat_acc: { |
| 9519 | // op: Vuu32 |
| 9520 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 9521 | Value |= (op & 0x1f) << 8; |
| 9522 | // op: Rt32 |
| 9523 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 9524 | Value |= (op & 0x1f) << 16; |
| 9525 | // op: Vx32 |
| 9526 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 9527 | Value |= (op & 0x1f); |
| 9528 | break; |
| 9529 | } |
| 9530 | case Hexagon::V6_vdmpybus_dv_acc: |
| 9531 | case Hexagon::V6_vdmpyhb_dv_acc: |
| 9532 | case Hexagon::V6_vdsaduh_acc: |
| 9533 | case Hexagon::V6_vmpabus_acc: |
| 9534 | case Hexagon::V6_vmpabuu_acc: |
| 9535 | case Hexagon::V6_vmpahb_acc: |
| 9536 | case Hexagon::V6_vmpauhb_acc: |
| 9537 | case Hexagon::V6_vtmpyb_acc: |
| 9538 | case Hexagon::V6_vtmpybus_acc: |
| 9539 | case Hexagon::V6_vtmpyhb_acc: { |
| 9540 | // op: Vuu32 |
| 9541 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 9542 | Value |= (op & 0x1f) << 8; |
| 9543 | // op: Rt32 |
| 9544 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 9545 | Value |= (op & 0x1f) << 16; |
| 9546 | // op: Vxx32 |
| 9547 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 9548 | Value |= (op & 0x1f); |
| 9549 | break; |
| 9550 | } |
| 9551 | case Hexagon::EH_RETURN_JMPR: |
| 9552 | case Hexagon::PS_jmpret: { |
| 9553 | // op: dst |
| 9554 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 9555 | Value |= (op & 0x1f) << 16; |
| 9556 | break; |
| 9557 | } |
| 9558 | case Hexagon::HI: |
| 9559 | case Hexagon::LO: { |
| 9560 | // op: dst |
| 9561 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 9562 | Value |= (op & 0x1f) << 16; |
| 9563 | // op: imm_value |
| 9564 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 9565 | Value |= (op & 0xc000) << 8; |
| 9566 | Value |= (op & 0x3fff); |
| 9567 | break; |
| 9568 | } |
| 9569 | case Hexagon::CALLProfile: |
| 9570 | case Hexagon::PS_call_stk: |
| 9571 | case Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4: |
| 9572 | case Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT: |
| 9573 | case Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT_PIC: |
| 9574 | case Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_PIC: |
| 9575 | case Hexagon::RESTORE_DEALLOC_RET_JMP_V4: |
| 9576 | case Hexagon::RESTORE_DEALLOC_RET_JMP_V4_EXT: |
| 9577 | case Hexagon::RESTORE_DEALLOC_RET_JMP_V4_EXT_PIC: |
| 9578 | case Hexagon::RESTORE_DEALLOC_RET_JMP_V4_PIC: |
| 9579 | case Hexagon::SAVE_REGISTERS_CALL_V4: |
| 9580 | case Hexagon::SAVE_REGISTERS_CALL_V4STK: |
| 9581 | case Hexagon::SAVE_REGISTERS_CALL_V4STK_EXT: |
| 9582 | case Hexagon::SAVE_REGISTERS_CALL_V4STK_EXT_PIC: |
| 9583 | case Hexagon::SAVE_REGISTERS_CALL_V4STK_PIC: |
| 9584 | case Hexagon::SAVE_REGISTERS_CALL_V4_EXT: |
| 9585 | case Hexagon::SAVE_REGISTERS_CALL_V4_EXT_PIC: |
| 9586 | case Hexagon::SAVE_REGISTERS_CALL_V4_PIC: { |
| 9587 | // op: dst |
| 9588 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 9589 | Value |= (op & 0xff8000) << 1; |
| 9590 | Value |= (op & 0x7ffc) >> 1; |
| 9591 | break; |
| 9592 | } |
| 9593 | case Hexagon::J2_loop0rext: |
| 9594 | case Hexagon::J2_loop1rext: { |
| 9595 | // op: offset |
| 9596 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 9597 | Value |= (op & 0x1f0) << 4; |
| 9598 | Value |= (op & 0xc) << 1; |
| 9599 | // op: src2 |
| 9600 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 9601 | Value |= (op & 0x1f) << 16; |
| 9602 | break; |
| 9603 | } |
| 9604 | case Hexagon::J2_loop0iext: |
| 9605 | case Hexagon::J2_loop1iext: { |
| 9606 | // op: offset |
| 9607 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 9608 | Value |= (op & 0x1f0) << 4; |
| 9609 | Value |= (op & 0xc) << 1; |
| 9610 | // op: src2 |
| 9611 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 9612 | Value |= (op & 0x3e0) << 11; |
| 9613 | Value |= (op & 0x1c) << 3; |
| 9614 | Value |= (op & 0x3); |
| 9615 | break; |
| 9616 | } |
| 9617 | case Hexagon::PS_jmpretf: |
| 9618 | case Hexagon::PS_jmpretfnew: |
| 9619 | case Hexagon::PS_jmpretfnewpt: |
| 9620 | case Hexagon::PS_jmprett: |
| 9621 | case Hexagon::PS_jmprettnew: |
| 9622 | case Hexagon::PS_jmprettnewpt: { |
| 9623 | // op: src |
| 9624 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 9625 | Value |= (op & 0x3) << 8; |
| 9626 | // op: dst |
| 9627 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 9628 | Value |= (op & 0x1f) << 16; |
| 9629 | break; |
| 9630 | } |
| 9631 | default: |
| 9632 | reportUnsupportedInst(Inst: MI); |
| 9633 | } |
| 9634 | return Value; |
| 9635 | } |
| 9636 | |
| 9637 | #ifdef GET_OPERAND_BIT_OFFSET |
| 9638 | #undef GET_OPERAND_BIT_OFFSET |
| 9639 | |
| 9640 | uint32_t HexagonMCCodeEmitter::getOperandBitOffset(const MCInst &MI, |
| 9641 | unsigned OpNum, |
| 9642 | const MCSubtargetInfo &STI) const { |
| 9643 | switch (MI.getOpcode()) { |
| 9644 | case Hexagon::A2_nop: |
| 9645 | case Hexagon::CONST32: |
| 9646 | case Hexagon::CONST64: |
| 9647 | case Hexagon::DuplexIClass0: |
| 9648 | case Hexagon::DuplexIClass1: |
| 9649 | case Hexagon::DuplexIClass2: |
| 9650 | case Hexagon::DuplexIClass3: |
| 9651 | case Hexagon::DuplexIClass4: |
| 9652 | case Hexagon::DuplexIClass5: |
| 9653 | case Hexagon::DuplexIClass6: |
| 9654 | case Hexagon::DuplexIClass7: |
| 9655 | case Hexagon::DuplexIClass8: |
| 9656 | case Hexagon::DuplexIClass9: |
| 9657 | case Hexagon::DuplexIClassA: |
| 9658 | case Hexagon::DuplexIClassB: |
| 9659 | case Hexagon::DuplexIClassC: |
| 9660 | case Hexagon::DuplexIClassD: |
| 9661 | case Hexagon::DuplexIClassE: |
| 9662 | case Hexagon::DuplexIClassF: |
| 9663 | case Hexagon::J2_rte: |
| 9664 | case Hexagon::J2_unpause: |
| 9665 | case Hexagon::SL2_deallocframe: |
| 9666 | case Hexagon::SL2_jumpr31: |
| 9667 | case Hexagon::SL2_jumpr31_f: |
| 9668 | case Hexagon::SL2_jumpr31_fnew: |
| 9669 | case Hexagon::SL2_jumpr31_t: |
| 9670 | case Hexagon::SL2_jumpr31_tnew: |
| 9671 | case Hexagon::SL2_return: |
| 9672 | case Hexagon::SL2_return_f: |
| 9673 | case Hexagon::SL2_return_fnew: |
| 9674 | case Hexagon::SL2_return_t: |
| 9675 | case Hexagon::SL2_return_tnew: |
| 9676 | case Hexagon::TFRI64_V2_ext: |
| 9677 | case Hexagon::TFRI64_V4: |
| 9678 | case Hexagon::V6_vhist: |
| 9679 | case Hexagon::V6_vwhist128: |
| 9680 | case Hexagon::V6_vwhist256: |
| 9681 | case Hexagon::V6_vwhist256_sat: |
| 9682 | case Hexagon::Y2_barrier: |
| 9683 | case Hexagon::Y2_break: |
| 9684 | case Hexagon::Y2_dckill: |
| 9685 | case Hexagon::Y2_ickill: |
| 9686 | case Hexagon::Y2_isync: |
| 9687 | case Hexagon::Y2_k0lock: |
| 9688 | case Hexagon::Y2_k0unlock: |
| 9689 | case Hexagon::Y2_l2kill: |
| 9690 | case Hexagon::Y2_syncht: |
| 9691 | case Hexagon::Y2_tlblock: |
| 9692 | case Hexagon::Y2_tlbunlock: |
| 9693 | case Hexagon::Y5_l2gclean: |
| 9694 | case Hexagon::Y5_l2gcleaninv: |
| 9695 | case Hexagon::Y5_l2gunlock: |
| 9696 | case Hexagon::invalid_decode: { |
| 9697 | break; |
| 9698 | } |
| 9699 | case Hexagon::PS_storerbnewabs: |
| 9700 | case Hexagon::PS_storerhnewabs: |
| 9701 | case Hexagon::PS_storerinewabs: |
| 9702 | case Hexagon::S2_storerbnewgp: |
| 9703 | case Hexagon::S2_storerhnewgp: |
| 9704 | case Hexagon::S2_storerinewgp: { |
| 9705 | switch (OpNum) { |
| 9706 | case 0: |
| 9707 | // op: Ii |
| 9708 | return 0; |
| 9709 | case 1: |
| 9710 | // op: Nt8 |
| 9711 | return 8; |
| 9712 | } |
| 9713 | break; |
| 9714 | } |
| 9715 | case Hexagon::PS_storerbabs: |
| 9716 | case Hexagon::PS_storerfabs: |
| 9717 | case Hexagon::PS_storerhabs: |
| 9718 | case Hexagon::PS_storeriabs: |
| 9719 | case Hexagon::S2_storerbgp: |
| 9720 | case Hexagon::S2_storerfgp: |
| 9721 | case Hexagon::S2_storerhgp: |
| 9722 | case Hexagon::S2_storerigp: { |
| 9723 | switch (OpNum) { |
| 9724 | case 0: |
| 9725 | // op: Ii |
| 9726 | return 0; |
| 9727 | case 1: |
| 9728 | // op: Rt32 |
| 9729 | return 8; |
| 9730 | } |
| 9731 | break; |
| 9732 | } |
| 9733 | case Hexagon::PS_storerdabs: |
| 9734 | case Hexagon::S2_storerdgp: { |
| 9735 | switch (OpNum) { |
| 9736 | case 0: |
| 9737 | // op: Ii |
| 9738 | return 0; |
| 9739 | case 1: |
| 9740 | // op: Rtt32 |
| 9741 | return 8; |
| 9742 | } |
| 9743 | break; |
| 9744 | } |
| 9745 | case Hexagon::A4_ext: { |
| 9746 | switch (OpNum) { |
| 9747 | case 0: |
| 9748 | // op: Ii |
| 9749 | return 0; |
| 9750 | } |
| 9751 | break; |
| 9752 | } |
| 9753 | case Hexagon::J2_call: |
| 9754 | case Hexagon::J2_jump: { |
| 9755 | switch (OpNum) { |
| 9756 | case 0: |
| 9757 | // op: Ii |
| 9758 | return 1; |
| 9759 | } |
| 9760 | break; |
| 9761 | } |
| 9762 | case Hexagon::J2_pause: |
| 9763 | case Hexagon::J2_trap0: |
| 9764 | case Hexagon::PS_trap1: { |
| 9765 | switch (OpNum) { |
| 9766 | case 0: |
| 9767 | // op: Ii |
| 9768 | return 2; |
| 9769 | } |
| 9770 | break; |
| 9771 | } |
| 9772 | case Hexagon::J2_loop0i: |
| 9773 | case Hexagon::J2_loop1i: |
| 9774 | case Hexagon::J2_ploop1si: |
| 9775 | case Hexagon::J2_ploop2si: |
| 9776 | case Hexagon::J2_ploop3si: { |
| 9777 | switch (OpNum) { |
| 9778 | case 0: |
| 9779 | // op: Ii |
| 9780 | return 3; |
| 9781 | case 1: |
| 9782 | // op: II |
| 9783 | return 0; |
| 9784 | } |
| 9785 | break; |
| 9786 | } |
| 9787 | case Hexagon::J2_loop0r: |
| 9788 | case Hexagon::J2_loop1r: |
| 9789 | case Hexagon::J2_ploop1sr: |
| 9790 | case Hexagon::J2_ploop2sr: |
| 9791 | case Hexagon::J2_ploop3sr: { |
| 9792 | switch (OpNum) { |
| 9793 | case 0: |
| 9794 | // op: Ii |
| 9795 | return 3; |
| 9796 | case 1: |
| 9797 | // op: Rs32 |
| 9798 | return 16; |
| 9799 | } |
| 9800 | break; |
| 9801 | } |
| 9802 | case Hexagon::SS2_stored_sp: { |
| 9803 | switch (OpNum) { |
| 9804 | case 0: |
| 9805 | // op: Ii |
| 9806 | return 3; |
| 9807 | case 1: |
| 9808 | // op: Rtt8 |
| 9809 | return 0; |
| 9810 | } |
| 9811 | break; |
| 9812 | } |
| 9813 | case Hexagon::SS2_storew_sp: { |
| 9814 | switch (OpNum) { |
| 9815 | case 0: |
| 9816 | // op: Ii |
| 9817 | return 4; |
| 9818 | case 1: |
| 9819 | // op: Rt16 |
| 9820 | return 0; |
| 9821 | } |
| 9822 | break; |
| 9823 | } |
| 9824 | case Hexagon::SS2_allocframe: { |
| 9825 | switch (OpNum) { |
| 9826 | case 0: |
| 9827 | // op: Ii |
| 9828 | return 4; |
| 9829 | } |
| 9830 | break; |
| 9831 | } |
| 9832 | case Hexagon::V6_vwhist128m: { |
| 9833 | switch (OpNum) { |
| 9834 | case 0: |
| 9835 | // op: Ii |
| 9836 | return 8; |
| 9837 | } |
| 9838 | break; |
| 9839 | } |
| 9840 | case Hexagon::Y2_setimask: |
| 9841 | case Hexagon::Y2_setprio: { |
| 9842 | switch (OpNum) { |
| 9843 | case 0: |
| 9844 | // op: Pt4 |
| 9845 | return 8; |
| 9846 | case 1: |
| 9847 | // op: Rs32 |
| 9848 | return 16; |
| 9849 | } |
| 9850 | break; |
| 9851 | } |
| 9852 | case Hexagon::J2_callrf: |
| 9853 | case Hexagon::J2_callrt: |
| 9854 | case Hexagon::J2_jumprf: |
| 9855 | case Hexagon::J2_jumprfnew: |
| 9856 | case Hexagon::J2_jumprfnewpt: |
| 9857 | case Hexagon::J2_jumprfpt: |
| 9858 | case Hexagon::J2_jumprt: |
| 9859 | case Hexagon::J2_jumprtnew: |
| 9860 | case Hexagon::J2_jumprtnewpt: |
| 9861 | case Hexagon::J2_jumprtpt: { |
| 9862 | switch (OpNum) { |
| 9863 | case 0: |
| 9864 | // op: Pu4 |
| 9865 | return 8; |
| 9866 | case 1: |
| 9867 | // op: Rs32 |
| 9868 | return 16; |
| 9869 | } |
| 9870 | break; |
| 9871 | } |
| 9872 | case Hexagon::V6_vgathermhq: |
| 9873 | case Hexagon::V6_vgathermwq: { |
| 9874 | switch (OpNum) { |
| 9875 | case 0: |
| 9876 | // op: Qs4 |
| 9877 | return 5; |
| 9878 | case 1: |
| 9879 | // op: Rt32 |
| 9880 | return 16; |
| 9881 | case 2: |
| 9882 | // op: Mu2 |
| 9883 | return 13; |
| 9884 | case 3: |
| 9885 | // op: Vv32 |
| 9886 | return 0; |
| 9887 | } |
| 9888 | break; |
| 9889 | } |
| 9890 | case Hexagon::V6_vscattermhq: |
| 9891 | case Hexagon::V6_vscattermwq: { |
| 9892 | switch (OpNum) { |
| 9893 | case 0: |
| 9894 | // op: Qs4 |
| 9895 | return 5; |
| 9896 | case 1: |
| 9897 | // op: Rt32 |
| 9898 | return 16; |
| 9899 | case 2: |
| 9900 | // op: Mu2 |
| 9901 | return 13; |
| 9902 | case 3: |
| 9903 | // op: Vv32 |
| 9904 | return 8; |
| 9905 | case 4: |
| 9906 | // op: Vw32 |
| 9907 | return 0; |
| 9908 | } |
| 9909 | break; |
| 9910 | } |
| 9911 | case Hexagon::V6_vgathermhwq: { |
| 9912 | switch (OpNum) { |
| 9913 | case 0: |
| 9914 | // op: Qs4 |
| 9915 | return 5; |
| 9916 | case 1: |
| 9917 | // op: Rt32 |
| 9918 | return 16; |
| 9919 | case 2: |
| 9920 | // op: Mu2 |
| 9921 | return 13; |
| 9922 | case 3: |
| 9923 | // op: Vvv32 |
| 9924 | return 0; |
| 9925 | } |
| 9926 | break; |
| 9927 | } |
| 9928 | case Hexagon::V6_vscattermhwq: { |
| 9929 | switch (OpNum) { |
| 9930 | case 0: |
| 9931 | // op: Qs4 |
| 9932 | return 5; |
| 9933 | case 1: |
| 9934 | // op: Rt32 |
| 9935 | return 16; |
| 9936 | case 2: |
| 9937 | // op: Mu2 |
| 9938 | return 13; |
| 9939 | case 3: |
| 9940 | // op: Vvv32 |
| 9941 | return 8; |
| 9942 | case 4: |
| 9943 | // op: Vw32 |
| 9944 | return 0; |
| 9945 | } |
| 9946 | break; |
| 9947 | } |
| 9948 | case Hexagon::V6_vhistq: |
| 9949 | case Hexagon::V6_vwhist128q: |
| 9950 | case Hexagon::V6_vwhist256q: |
| 9951 | case Hexagon::V6_vwhist256q_sat: { |
| 9952 | switch (OpNum) { |
| 9953 | case 0: |
| 9954 | // op: Qv4 |
| 9955 | return 22; |
| 9956 | } |
| 9957 | break; |
| 9958 | } |
| 9959 | case Hexagon::SA1_clrf: |
| 9960 | case Hexagon::SA1_clrfnew: |
| 9961 | case Hexagon::SA1_clrt: |
| 9962 | case Hexagon::SA1_clrtnew: |
| 9963 | case Hexagon::SA1_setin1: { |
| 9964 | switch (OpNum) { |
| 9965 | case 0: |
| 9966 | // op: Rd16 |
| 9967 | return 0; |
| 9968 | } |
| 9969 | break; |
| 9970 | } |
| 9971 | case Hexagon::Y6_dmpause: |
| 9972 | case Hexagon::Y6_dmpoll: |
| 9973 | case Hexagon::Y6_dmwait: { |
| 9974 | switch (OpNum) { |
| 9975 | case 0: |
| 9976 | // op: Rd32 |
| 9977 | return 0; |
| 9978 | } |
| 9979 | break; |
| 9980 | } |
| 9981 | case Hexagon::PS_callr_nr: { |
| 9982 | switch (OpNum) { |
| 9983 | case 0: |
| 9984 | // op: Rs |
| 9985 | return 16; |
| 9986 | } |
| 9987 | break; |
| 9988 | } |
| 9989 | case Hexagon::L6_memcpy: { |
| 9990 | switch (OpNum) { |
| 9991 | case 0: |
| 9992 | // op: Rs32 |
| 9993 | return 16; |
| 9994 | case 1: |
| 9995 | // op: Rt32 |
| 9996 | return 8; |
| 9997 | case 2: |
| 9998 | // op: Mu2 |
| 9999 | return 13; |
| 10000 | } |
| 10001 | break; |
| 10002 | } |
| 10003 | case Hexagon::S2_storew_rl_at_vi: |
| 10004 | case Hexagon::S2_storew_rl_st_vi: |
| 10005 | case Hexagon::Y2_dctagw: |
| 10006 | case Hexagon::Y2_icdataw: |
| 10007 | case Hexagon::Y2_ictagw: |
| 10008 | case Hexagon::Y4_l2fetch: |
| 10009 | case Hexagon::Y4_l2tagw: |
| 10010 | case Hexagon::Y6_dmlink: { |
| 10011 | switch (OpNum) { |
| 10012 | case 0: |
| 10013 | // op: Rs32 |
| 10014 | return 16; |
| 10015 | case 1: |
| 10016 | // op: Rt32 |
| 10017 | return 8; |
| 10018 | } |
| 10019 | break; |
| 10020 | } |
| 10021 | case Hexagon::S4_stored_rl_at_vi: |
| 10022 | case Hexagon::S4_stored_rl_st_vi: |
| 10023 | case Hexagon::Y5_l2fetch: { |
| 10024 | switch (OpNum) { |
| 10025 | case 0: |
| 10026 | // op: Rs32 |
| 10027 | return 16; |
| 10028 | case 1: |
| 10029 | // op: Rtt32 |
| 10030 | return 8; |
| 10031 | } |
| 10032 | break; |
| 10033 | } |
| 10034 | case Hexagon::J2_callr: |
| 10035 | case Hexagon::J2_callrh: |
| 10036 | case Hexagon::J2_jumpr: |
| 10037 | case Hexagon::J2_jumprh: |
| 10038 | case Hexagon::J4_hintjumpr: |
| 10039 | case Hexagon::R6_release_at_vi: |
| 10040 | case Hexagon::R6_release_st_vi: |
| 10041 | case Hexagon::Y2_ciad: |
| 10042 | case Hexagon::Y2_cswi: |
| 10043 | case Hexagon::Y2_dccleana: |
| 10044 | case Hexagon::Y2_dccleanidx: |
| 10045 | case Hexagon::Y2_dccleaninva: |
| 10046 | case Hexagon::Y2_dccleaninvidx: |
| 10047 | case Hexagon::Y2_dcinva: |
| 10048 | case Hexagon::Y2_dcinvidx: |
| 10049 | case Hexagon::Y2_dczeroa: |
| 10050 | case Hexagon::Y2_iassignw: |
| 10051 | case Hexagon::Y2_icinva: |
| 10052 | case Hexagon::Y2_icinvidx: |
| 10053 | case Hexagon::Y2_l2cleaninvidx: |
| 10054 | case Hexagon::Y2_resume: |
| 10055 | case Hexagon::Y2_start: |
| 10056 | case Hexagon::Y2_stop: |
| 10057 | case Hexagon::Y2_swi: |
| 10058 | case Hexagon::Y2_wait: |
| 10059 | case Hexagon::Y4_nmi: |
| 10060 | case Hexagon::Y4_siad: |
| 10061 | case Hexagon::Y4_trace: |
| 10062 | case Hexagon::Y5_l2cleanidx: |
| 10063 | case Hexagon::Y5_l2invidx: |
| 10064 | case Hexagon::Y5_l2unlocka: |
| 10065 | case Hexagon::Y5_tlbasidi: |
| 10066 | case Hexagon::Y6_diag: |
| 10067 | case Hexagon::Y6_dmresume: |
| 10068 | case Hexagon::Y6_dmstart: { |
| 10069 | switch (OpNum) { |
| 10070 | case 0: |
| 10071 | // op: Rs32 |
| 10072 | return 16; |
| 10073 | } |
| 10074 | break; |
| 10075 | } |
| 10076 | case Hexagon::Y2_tlbw: { |
| 10077 | switch (OpNum) { |
| 10078 | case 0: |
| 10079 | // op: Rss32 |
| 10080 | return 16; |
| 10081 | case 1: |
| 10082 | // op: Rt32 |
| 10083 | return 8; |
| 10084 | } |
| 10085 | break; |
| 10086 | } |
| 10087 | case Hexagon::Y6_diag0: |
| 10088 | case Hexagon::Y6_diag1: { |
| 10089 | switch (OpNum) { |
| 10090 | case 0: |
| 10091 | // op: Rss32 |
| 10092 | return 16; |
| 10093 | case 1: |
| 10094 | // op: Rtt32 |
| 10095 | return 8; |
| 10096 | } |
| 10097 | break; |
| 10098 | } |
| 10099 | case Hexagon::V6_vgathermh: |
| 10100 | case Hexagon::V6_vgathermw: { |
| 10101 | switch (OpNum) { |
| 10102 | case 0: |
| 10103 | // op: Rt32 |
| 10104 | return 16; |
| 10105 | case 1: |
| 10106 | // op: Mu2 |
| 10107 | return 13; |
| 10108 | case 2: |
| 10109 | // op: Vv32 |
| 10110 | return 0; |
| 10111 | } |
| 10112 | break; |
| 10113 | } |
| 10114 | case Hexagon::V6_vscattermh: |
| 10115 | case Hexagon::V6_vscattermh_add: |
| 10116 | case Hexagon::V6_vscattermw: |
| 10117 | case Hexagon::V6_vscattermw_add: { |
| 10118 | switch (OpNum) { |
| 10119 | case 0: |
| 10120 | // op: Rt32 |
| 10121 | return 16; |
| 10122 | case 1: |
| 10123 | // op: Mu2 |
| 10124 | return 13; |
| 10125 | case 2: |
| 10126 | // op: Vv32 |
| 10127 | return 8; |
| 10128 | case 3: |
| 10129 | // op: Vw32 |
| 10130 | return 0; |
| 10131 | } |
| 10132 | break; |
| 10133 | } |
| 10134 | case Hexagon::V6_vgathermhw: { |
| 10135 | switch (OpNum) { |
| 10136 | case 0: |
| 10137 | // op: Rt32 |
| 10138 | return 16; |
| 10139 | case 1: |
| 10140 | // op: Mu2 |
| 10141 | return 13; |
| 10142 | case 2: |
| 10143 | // op: Vvv32 |
| 10144 | return 0; |
| 10145 | } |
| 10146 | break; |
| 10147 | } |
| 10148 | case Hexagon::V6_vscattermhw: |
| 10149 | case Hexagon::V6_vscattermhw_add: { |
| 10150 | switch (OpNum) { |
| 10151 | case 0: |
| 10152 | // op: Rt32 |
| 10153 | return 16; |
| 10154 | case 1: |
| 10155 | // op: Mu2 |
| 10156 | return 13; |
| 10157 | case 2: |
| 10158 | // op: Vvv32 |
| 10159 | return 8; |
| 10160 | case 3: |
| 10161 | // op: Vw32 |
| 10162 | return 0; |
| 10163 | } |
| 10164 | break; |
| 10165 | } |
| 10166 | case Hexagon::Y6_l2gcleaninvpa: |
| 10167 | case Hexagon::Y6_l2gcleanpa: { |
| 10168 | switch (OpNum) { |
| 10169 | case 0: |
| 10170 | // op: Rtt32 |
| 10171 | return 8; |
| 10172 | } |
| 10173 | break; |
| 10174 | } |
| 10175 | case Hexagon::Y2_crswap0: |
| 10176 | case Hexagon::Y4_crswap1: { |
| 10177 | switch (OpNum) { |
| 10178 | case 0: |
| 10179 | // op: Rx32 |
| 10180 | return 16; |
| 10181 | } |
| 10182 | break; |
| 10183 | } |
| 10184 | case Hexagon::Y4_crswap10: { |
| 10185 | switch (OpNum) { |
| 10186 | case 0: |
| 10187 | // op: Rxx32 |
| 10188 | return 16; |
| 10189 | } |
| 10190 | break; |
| 10191 | } |
| 10192 | case Hexagon::HI: |
| 10193 | case Hexagon::LO: { |
| 10194 | switch (OpNum) { |
| 10195 | case 0: |
| 10196 | // op: dst |
| 10197 | return 16; |
| 10198 | case 1: |
| 10199 | // op: imm_value |
| 10200 | return 0; |
| 10201 | } |
| 10202 | break; |
| 10203 | } |
| 10204 | case Hexagon::EH_RETURN_JMPR: |
| 10205 | case Hexagon::PS_jmpret: { |
| 10206 | switch (OpNum) { |
| 10207 | case 0: |
| 10208 | // op: dst |
| 10209 | return 16; |
| 10210 | } |
| 10211 | break; |
| 10212 | } |
| 10213 | case Hexagon::CALLProfile: |
| 10214 | case Hexagon::PS_call_stk: |
| 10215 | case Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4: |
| 10216 | case Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT: |
| 10217 | case Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT_PIC: |
| 10218 | case Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_PIC: |
| 10219 | case Hexagon::RESTORE_DEALLOC_RET_JMP_V4: |
| 10220 | case Hexagon::RESTORE_DEALLOC_RET_JMP_V4_EXT: |
| 10221 | case Hexagon::RESTORE_DEALLOC_RET_JMP_V4_EXT_PIC: |
| 10222 | case Hexagon::RESTORE_DEALLOC_RET_JMP_V4_PIC: |
| 10223 | case Hexagon::SAVE_REGISTERS_CALL_V4: |
| 10224 | case Hexagon::SAVE_REGISTERS_CALL_V4STK: |
| 10225 | case Hexagon::SAVE_REGISTERS_CALL_V4STK_EXT: |
| 10226 | case Hexagon::SAVE_REGISTERS_CALL_V4STK_EXT_PIC: |
| 10227 | case Hexagon::SAVE_REGISTERS_CALL_V4STK_PIC: |
| 10228 | case Hexagon::SAVE_REGISTERS_CALL_V4_EXT: |
| 10229 | case Hexagon::SAVE_REGISTERS_CALL_V4_EXT_PIC: |
| 10230 | case Hexagon::SAVE_REGISTERS_CALL_V4_PIC: { |
| 10231 | switch (OpNum) { |
| 10232 | case 0: |
| 10233 | // op: dst |
| 10234 | return 1; |
| 10235 | } |
| 10236 | break; |
| 10237 | } |
| 10238 | case Hexagon::J2_loop0iext: |
| 10239 | case Hexagon::J2_loop1iext: { |
| 10240 | switch (OpNum) { |
| 10241 | case 0: |
| 10242 | // op: offset |
| 10243 | return 3; |
| 10244 | case 1: |
| 10245 | // op: src2 |
| 10246 | return 0; |
| 10247 | } |
| 10248 | break; |
| 10249 | } |
| 10250 | case Hexagon::J2_loop0rext: |
| 10251 | case Hexagon::J2_loop1rext: { |
| 10252 | switch (OpNum) { |
| 10253 | case 0: |
| 10254 | // op: offset |
| 10255 | return 3; |
| 10256 | case 1: |
| 10257 | // op: src2 |
| 10258 | return 16; |
| 10259 | } |
| 10260 | break; |
| 10261 | } |
| 10262 | case Hexagon::PS_jmpretf: |
| 10263 | case Hexagon::PS_jmpretfnew: |
| 10264 | case Hexagon::PS_jmpretfnewpt: |
| 10265 | case Hexagon::PS_jmprett: |
| 10266 | case Hexagon::PS_jmprettnew: |
| 10267 | case Hexagon::PS_jmprettnewpt: { |
| 10268 | switch (OpNum) { |
| 10269 | case 0: |
| 10270 | // op: src |
| 10271 | return 8; |
| 10272 | case 1: |
| 10273 | // op: dst |
| 10274 | return 16; |
| 10275 | } |
| 10276 | break; |
| 10277 | } |
| 10278 | case Hexagon::A2_tfrcrr: { |
| 10279 | switch (OpNum) { |
| 10280 | case 1: |
| 10281 | // op: Cs32 |
| 10282 | return 16; |
| 10283 | case 0: |
| 10284 | // op: Rd32 |
| 10285 | return 0; |
| 10286 | } |
| 10287 | break; |
| 10288 | } |
| 10289 | case Hexagon::A4_tfrcpp: { |
| 10290 | switch (OpNum) { |
| 10291 | case 1: |
| 10292 | // op: Css32 |
| 10293 | return 16; |
| 10294 | case 0: |
| 10295 | // op: Rdd32 |
| 10296 | return 0; |
| 10297 | } |
| 10298 | break; |
| 10299 | } |
| 10300 | case Hexagon::G4_tfrgcrr: { |
| 10301 | switch (OpNum) { |
| 10302 | case 1: |
| 10303 | // op: Gs32 |
| 10304 | return 16; |
| 10305 | case 0: |
| 10306 | // op: Rd32 |
| 10307 | return 0; |
| 10308 | } |
| 10309 | break; |
| 10310 | } |
| 10311 | case Hexagon::G4_tfrgcpp: { |
| 10312 | switch (OpNum) { |
| 10313 | case 1: |
| 10314 | // op: Gss32 |
| 10315 | return 16; |
| 10316 | case 0: |
| 10317 | // op: Rdd32 |
| 10318 | return 0; |
| 10319 | } |
| 10320 | break; |
| 10321 | } |
| 10322 | case Hexagon::S4_storerbnew_ap: |
| 10323 | case Hexagon::S4_storerhnew_ap: |
| 10324 | case Hexagon::S4_storerinew_ap: { |
| 10325 | switch (OpNum) { |
| 10326 | case 1: |
| 10327 | // op: II |
| 10328 | return 0; |
| 10329 | case 2: |
| 10330 | // op: Nt8 |
| 10331 | return 8; |
| 10332 | case 0: |
| 10333 | // op: Re32 |
| 10334 | return 16; |
| 10335 | } |
| 10336 | break; |
| 10337 | } |
| 10338 | case Hexagon::S4_storerb_ap: |
| 10339 | case Hexagon::S4_storerf_ap: |
| 10340 | case Hexagon::S4_storerh_ap: |
| 10341 | case Hexagon::S4_storeri_ap: { |
| 10342 | switch (OpNum) { |
| 10343 | case 1: |
| 10344 | // op: II |
| 10345 | return 0; |
| 10346 | case 2: |
| 10347 | // op: Rt32 |
| 10348 | return 8; |
| 10349 | case 0: |
| 10350 | // op: Re32 |
| 10351 | return 16; |
| 10352 | } |
| 10353 | break; |
| 10354 | } |
| 10355 | case Hexagon::S4_storerd_ap: { |
| 10356 | switch (OpNum) { |
| 10357 | case 1: |
| 10358 | // op: II |
| 10359 | return 0; |
| 10360 | case 2: |
| 10361 | // op: Rtt32 |
| 10362 | return 8; |
| 10363 | case 0: |
| 10364 | // op: Re32 |
| 10365 | return 16; |
| 10366 | } |
| 10367 | break; |
| 10368 | } |
| 10369 | case Hexagon::J4_cmpeqi_f_jumpnv_nt: |
| 10370 | case Hexagon::J4_cmpeqi_f_jumpnv_t: |
| 10371 | case Hexagon::J4_cmpeqi_t_jumpnv_nt: |
| 10372 | case Hexagon::J4_cmpeqi_t_jumpnv_t: |
| 10373 | case Hexagon::J4_cmpgti_f_jumpnv_nt: |
| 10374 | case Hexagon::J4_cmpgti_f_jumpnv_t: |
| 10375 | case Hexagon::J4_cmpgti_t_jumpnv_nt: |
| 10376 | case Hexagon::J4_cmpgti_t_jumpnv_t: |
| 10377 | case Hexagon::J4_cmpgtui_f_jumpnv_nt: |
| 10378 | case Hexagon::J4_cmpgtui_f_jumpnv_t: |
| 10379 | case Hexagon::J4_cmpgtui_t_jumpnv_nt: |
| 10380 | case Hexagon::J4_cmpgtui_t_jumpnv_t: { |
| 10381 | switch (OpNum) { |
| 10382 | case 1: |
| 10383 | // op: II |
| 10384 | return 8; |
| 10385 | case 2: |
| 10386 | // op: Ii |
| 10387 | return 1; |
| 10388 | case 0: |
| 10389 | // op: Ns8 |
| 10390 | return 16; |
| 10391 | } |
| 10392 | break; |
| 10393 | } |
| 10394 | case Hexagon::J4_jumpseti: { |
| 10395 | switch (OpNum) { |
| 10396 | case 1: |
| 10397 | // op: II |
| 10398 | return 8; |
| 10399 | case 2: |
| 10400 | // op: Ii |
| 10401 | return 1; |
| 10402 | case 0: |
| 10403 | // op: Rd16 |
| 10404 | return 16; |
| 10405 | } |
| 10406 | break; |
| 10407 | } |
| 10408 | case Hexagon::J4_cmpeqi_fp0_jump_nt: |
| 10409 | case Hexagon::J4_cmpeqi_fp0_jump_t: |
| 10410 | case Hexagon::J4_cmpeqi_fp1_jump_nt: |
| 10411 | case Hexagon::J4_cmpeqi_fp1_jump_t: |
| 10412 | case Hexagon::J4_cmpeqi_tp0_jump_nt: |
| 10413 | case Hexagon::J4_cmpeqi_tp0_jump_t: |
| 10414 | case Hexagon::J4_cmpeqi_tp1_jump_nt: |
| 10415 | case Hexagon::J4_cmpeqi_tp1_jump_t: |
| 10416 | case Hexagon::J4_cmpgti_fp0_jump_nt: |
| 10417 | case Hexagon::J4_cmpgti_fp0_jump_t: |
| 10418 | case Hexagon::J4_cmpgti_fp1_jump_nt: |
| 10419 | case Hexagon::J4_cmpgti_fp1_jump_t: |
| 10420 | case Hexagon::J4_cmpgti_tp0_jump_nt: |
| 10421 | case Hexagon::J4_cmpgti_tp0_jump_t: |
| 10422 | case Hexagon::J4_cmpgti_tp1_jump_nt: |
| 10423 | case Hexagon::J4_cmpgti_tp1_jump_t: |
| 10424 | case Hexagon::J4_cmpgtui_fp0_jump_nt: |
| 10425 | case Hexagon::J4_cmpgtui_fp0_jump_t: |
| 10426 | case Hexagon::J4_cmpgtui_fp1_jump_nt: |
| 10427 | case Hexagon::J4_cmpgtui_fp1_jump_t: |
| 10428 | case Hexagon::J4_cmpgtui_tp0_jump_nt: |
| 10429 | case Hexagon::J4_cmpgtui_tp0_jump_t: |
| 10430 | case Hexagon::J4_cmpgtui_tp1_jump_nt: |
| 10431 | case Hexagon::J4_cmpgtui_tp1_jump_t: { |
| 10432 | switch (OpNum) { |
| 10433 | case 1: |
| 10434 | // op: II |
| 10435 | return 8; |
| 10436 | case 2: |
| 10437 | // op: Ii |
| 10438 | return 1; |
| 10439 | case 0: |
| 10440 | // op: Rs16 |
| 10441 | return 16; |
| 10442 | } |
| 10443 | break; |
| 10444 | } |
| 10445 | case Hexagon::SA1_cmpeqi: |
| 10446 | case Hexagon::SS2_storebi0: |
| 10447 | case Hexagon::SS2_storebi1: |
| 10448 | case Hexagon::SS2_storewi0: |
| 10449 | case Hexagon::SS2_storewi1: { |
| 10450 | switch (OpNum) { |
| 10451 | case 1: |
| 10452 | // op: Ii |
| 10453 | return 0; |
| 10454 | case 0: |
| 10455 | // op: Rs16 |
| 10456 | return 4; |
| 10457 | } |
| 10458 | break; |
| 10459 | } |
| 10460 | case Hexagon::S2_storerbnew_io: |
| 10461 | case Hexagon::S2_storerhnew_io: |
| 10462 | case Hexagon::S2_storerinew_io: { |
| 10463 | switch (OpNum) { |
| 10464 | case 1: |
| 10465 | // op: Ii |
| 10466 | return 0; |
| 10467 | case 0: |
| 10468 | // op: Rs32 |
| 10469 | return 16; |
| 10470 | case 2: |
| 10471 | // op: Nt8 |
| 10472 | return 8; |
| 10473 | } |
| 10474 | break; |
| 10475 | } |
| 10476 | case Hexagon::S2_storerb_io: |
| 10477 | case Hexagon::S2_storerf_io: |
| 10478 | case Hexagon::S2_storerh_io: |
| 10479 | case Hexagon::S2_storeri_io: { |
| 10480 | switch (OpNum) { |
| 10481 | case 1: |
| 10482 | // op: Ii |
| 10483 | return 0; |
| 10484 | case 0: |
| 10485 | // op: Rs32 |
| 10486 | return 16; |
| 10487 | case 2: |
| 10488 | // op: Rt32 |
| 10489 | return 8; |
| 10490 | } |
| 10491 | break; |
| 10492 | } |
| 10493 | case Hexagon::S2_storerd_io: { |
| 10494 | switch (OpNum) { |
| 10495 | case 1: |
| 10496 | // op: Ii |
| 10497 | return 0; |
| 10498 | case 0: |
| 10499 | // op: Rs32 |
| 10500 | return 16; |
| 10501 | case 2: |
| 10502 | // op: Rtt32 |
| 10503 | return 8; |
| 10504 | } |
| 10505 | break; |
| 10506 | } |
| 10507 | case Hexagon::Y2_dcfetchbo: { |
| 10508 | switch (OpNum) { |
| 10509 | case 1: |
| 10510 | // op: Ii |
| 10511 | return 0; |
| 10512 | case 0: |
| 10513 | // op: Rs32 |
| 10514 | return 16; |
| 10515 | } |
| 10516 | break; |
| 10517 | } |
| 10518 | case Hexagon::J4_tstbit0_f_jumpnv_nt: |
| 10519 | case Hexagon::J4_tstbit0_f_jumpnv_t: |
| 10520 | case Hexagon::J4_tstbit0_t_jumpnv_nt: |
| 10521 | case Hexagon::J4_tstbit0_t_jumpnv_t: { |
| 10522 | switch (OpNum) { |
| 10523 | case 1: |
| 10524 | // op: Ii |
| 10525 | return 1; |
| 10526 | case 0: |
| 10527 | // op: Ns8 |
| 10528 | return 16; |
| 10529 | } |
| 10530 | break; |
| 10531 | } |
| 10532 | case Hexagon::J2_callf: |
| 10533 | case Hexagon::J2_callt: |
| 10534 | case Hexagon::J2_jumpf: |
| 10535 | case Hexagon::J2_jumpfnew: |
| 10536 | case Hexagon::J2_jumpfnewpt: |
| 10537 | case Hexagon::J2_jumpfpt: |
| 10538 | case Hexagon::J2_jumpt: |
| 10539 | case Hexagon::J2_jumptnew: |
| 10540 | case Hexagon::J2_jumptnewpt: |
| 10541 | case Hexagon::J2_jumptpt: { |
| 10542 | switch (OpNum) { |
| 10543 | case 1: |
| 10544 | // op: Ii |
| 10545 | return 1; |
| 10546 | case 0: |
| 10547 | // op: Pu4 |
| 10548 | return 8; |
| 10549 | } |
| 10550 | break; |
| 10551 | } |
| 10552 | case Hexagon::J4_tstbit0_fp0_jump_nt: |
| 10553 | case Hexagon::J4_tstbit0_fp0_jump_t: |
| 10554 | case Hexagon::J4_tstbit0_fp1_jump_nt: |
| 10555 | case Hexagon::J4_tstbit0_fp1_jump_t: |
| 10556 | case Hexagon::J4_tstbit0_tp0_jump_nt: |
| 10557 | case Hexagon::J4_tstbit0_tp0_jump_t: |
| 10558 | case Hexagon::J4_tstbit0_tp1_jump_nt: |
| 10559 | case Hexagon::J4_tstbit0_tp1_jump_t: { |
| 10560 | switch (OpNum) { |
| 10561 | case 1: |
| 10562 | // op: Ii |
| 10563 | return 1; |
| 10564 | case 0: |
| 10565 | // op: Rs16 |
| 10566 | return 16; |
| 10567 | } |
| 10568 | break; |
| 10569 | } |
| 10570 | case Hexagon::J2_jumprgtez: |
| 10571 | case Hexagon::J2_jumprgtezpt: |
| 10572 | case Hexagon::J2_jumprltez: |
| 10573 | case Hexagon::J2_jumprltezpt: |
| 10574 | case Hexagon::J2_jumprnz: |
| 10575 | case Hexagon::J2_jumprnzpt: |
| 10576 | case Hexagon::J2_jumprz: |
| 10577 | case Hexagon::J2_jumprzpt: { |
| 10578 | switch (OpNum) { |
| 10579 | case 1: |
| 10580 | // op: Ii |
| 10581 | return 1; |
| 10582 | case 0: |
| 10583 | // op: Rs32 |
| 10584 | return 16; |
| 10585 | } |
| 10586 | break; |
| 10587 | } |
| 10588 | case Hexagon::S4_pstorerbnewf_abs: |
| 10589 | case Hexagon::S4_pstorerbnewfnew_abs: |
| 10590 | case Hexagon::S4_pstorerbnewt_abs: |
| 10591 | case Hexagon::S4_pstorerbnewtnew_abs: |
| 10592 | case Hexagon::S4_pstorerhnewf_abs: |
| 10593 | case Hexagon::S4_pstorerhnewfnew_abs: |
| 10594 | case Hexagon::S4_pstorerhnewt_abs: |
| 10595 | case Hexagon::S4_pstorerhnewtnew_abs: |
| 10596 | case Hexagon::S4_pstorerinewf_abs: |
| 10597 | case Hexagon::S4_pstorerinewfnew_abs: |
| 10598 | case Hexagon::S4_pstorerinewt_abs: |
| 10599 | case Hexagon::S4_pstorerinewtnew_abs: { |
| 10600 | switch (OpNum) { |
| 10601 | case 1: |
| 10602 | // op: Ii |
| 10603 | return 3; |
| 10604 | case 0: |
| 10605 | // op: Pv4 |
| 10606 | return 0; |
| 10607 | case 2: |
| 10608 | // op: Nt8 |
| 10609 | return 8; |
| 10610 | } |
| 10611 | break; |
| 10612 | } |
| 10613 | case Hexagon::S4_pstorerbf_abs: |
| 10614 | case Hexagon::S4_pstorerbfnew_abs: |
| 10615 | case Hexagon::S4_pstorerbt_abs: |
| 10616 | case Hexagon::S4_pstorerbtnew_abs: |
| 10617 | case Hexagon::S4_pstorerff_abs: |
| 10618 | case Hexagon::S4_pstorerffnew_abs: |
| 10619 | case Hexagon::S4_pstorerft_abs: |
| 10620 | case Hexagon::S4_pstorerftnew_abs: |
| 10621 | case Hexagon::S4_pstorerhf_abs: |
| 10622 | case Hexagon::S4_pstorerhfnew_abs: |
| 10623 | case Hexagon::S4_pstorerht_abs: |
| 10624 | case Hexagon::S4_pstorerhtnew_abs: |
| 10625 | case Hexagon::S4_pstorerif_abs: |
| 10626 | case Hexagon::S4_pstorerifnew_abs: |
| 10627 | case Hexagon::S4_pstorerit_abs: |
| 10628 | case Hexagon::S4_pstoreritnew_abs: { |
| 10629 | switch (OpNum) { |
| 10630 | case 1: |
| 10631 | // op: Ii |
| 10632 | return 3; |
| 10633 | case 0: |
| 10634 | // op: Pv4 |
| 10635 | return 0; |
| 10636 | case 2: |
| 10637 | // op: Rt32 |
| 10638 | return 8; |
| 10639 | } |
| 10640 | break; |
| 10641 | } |
| 10642 | case Hexagon::S4_pstorerdf_abs: |
| 10643 | case Hexagon::S4_pstorerdfnew_abs: |
| 10644 | case Hexagon::S4_pstorerdt_abs: |
| 10645 | case Hexagon::S4_pstorerdtnew_abs: { |
| 10646 | switch (OpNum) { |
| 10647 | case 1: |
| 10648 | // op: Ii |
| 10649 | return 3; |
| 10650 | case 0: |
| 10651 | // op: Pv4 |
| 10652 | return 0; |
| 10653 | case 2: |
| 10654 | // op: Rtt32 |
| 10655 | return 8; |
| 10656 | } |
| 10657 | break; |
| 10658 | } |
| 10659 | case Hexagon::SL2_loadrd_sp: { |
| 10660 | switch (OpNum) { |
| 10661 | case 1: |
| 10662 | // op: Ii |
| 10663 | return 3; |
| 10664 | case 0: |
| 10665 | // op: Rdd8 |
| 10666 | return 0; |
| 10667 | } |
| 10668 | break; |
| 10669 | } |
| 10670 | case Hexagon::S4_addi_asl_ri: |
| 10671 | case Hexagon::S4_addi_lsr_ri: |
| 10672 | case Hexagon::S4_andi_asl_ri: |
| 10673 | case Hexagon::S4_andi_lsr_ri: |
| 10674 | case Hexagon::S4_ori_asl_ri: |
| 10675 | case Hexagon::S4_ori_lsr_ri: |
| 10676 | case Hexagon::S4_subi_asl_ri: |
| 10677 | case Hexagon::S4_subi_lsr_ri: { |
| 10678 | switch (OpNum) { |
| 10679 | case 1: |
| 10680 | // op: Ii |
| 10681 | return 3; |
| 10682 | case 3: |
| 10683 | // op: II |
| 10684 | return 8; |
| 10685 | case 0: |
| 10686 | // op: Rx32 |
| 10687 | return 16; |
| 10688 | } |
| 10689 | break; |
| 10690 | } |
| 10691 | case Hexagon::SA1_addsp: |
| 10692 | case Hexagon::SA1_seti: |
| 10693 | case Hexagon::SL2_loadri_sp: { |
| 10694 | switch (OpNum) { |
| 10695 | case 1: |
| 10696 | // op: Ii |
| 10697 | return 4; |
| 10698 | case 0: |
| 10699 | // op: Rd16 |
| 10700 | return 0; |
| 10701 | } |
| 10702 | break; |
| 10703 | } |
| 10704 | case Hexagon::A2_tfrsi: |
| 10705 | case Hexagon::F2_sfimm_n: |
| 10706 | case Hexagon::F2_sfimm_p: |
| 10707 | case Hexagon::L2_loadrbgp: |
| 10708 | case Hexagon::L2_loadrhgp: |
| 10709 | case Hexagon::L2_loadrigp: |
| 10710 | case Hexagon::L2_loadrubgp: |
| 10711 | case Hexagon::L2_loadruhgp: |
| 10712 | case Hexagon::PS_loadrbabs: |
| 10713 | case Hexagon::PS_loadrhabs: |
| 10714 | case Hexagon::PS_loadriabs: |
| 10715 | case Hexagon::PS_loadrubabs: |
| 10716 | case Hexagon::PS_loadruhabs: { |
| 10717 | switch (OpNum) { |
| 10718 | case 1: |
| 10719 | // op: Ii |
| 10720 | return 5; |
| 10721 | case 0: |
| 10722 | // op: Rd32 |
| 10723 | return 0; |
| 10724 | } |
| 10725 | break; |
| 10726 | } |
| 10727 | case Hexagon::F2_dfimm_n: |
| 10728 | case Hexagon::F2_dfimm_p: |
| 10729 | case Hexagon::L2_loadrdgp: |
| 10730 | case Hexagon::PS_loadrdabs: { |
| 10731 | switch (OpNum) { |
| 10732 | case 1: |
| 10733 | // op: Ii |
| 10734 | return 5; |
| 10735 | case 0: |
| 10736 | // op: Rdd32 |
| 10737 | return 0; |
| 10738 | } |
| 10739 | break; |
| 10740 | } |
| 10741 | case Hexagon::SA1_combine0i: |
| 10742 | case Hexagon::SA1_combine1i: |
| 10743 | case Hexagon::SA1_combine2i: |
| 10744 | case Hexagon::SA1_combine3i: { |
| 10745 | switch (OpNum) { |
| 10746 | case 1: |
| 10747 | // op: Ii |
| 10748 | return 5; |
| 10749 | case 0: |
| 10750 | // op: Rdd8 |
| 10751 | return 0; |
| 10752 | } |
| 10753 | break; |
| 10754 | } |
| 10755 | case Hexagon::A2_combineii: |
| 10756 | case Hexagon::A4_combineii: { |
| 10757 | switch (OpNum) { |
| 10758 | case 1: |
| 10759 | // op: Ii |
| 10760 | return 5; |
| 10761 | case 2: |
| 10762 | // op: II |
| 10763 | return 13; |
| 10764 | case 0: |
| 10765 | // op: Rdd32 |
| 10766 | return 0; |
| 10767 | } |
| 10768 | break; |
| 10769 | } |
| 10770 | case Hexagon::A2_subri: { |
| 10771 | switch (OpNum) { |
| 10772 | case 1: |
| 10773 | // op: Ii |
| 10774 | return 5; |
| 10775 | case 2: |
| 10776 | // op: Rs32 |
| 10777 | return 16; |
| 10778 | case 0: |
| 10779 | // op: Rd32 |
| 10780 | return 0; |
| 10781 | } |
| 10782 | break; |
| 10783 | } |
| 10784 | case Hexagon::A4_combineir: { |
| 10785 | switch (OpNum) { |
| 10786 | case 1: |
| 10787 | // op: Ii |
| 10788 | return 5; |
| 10789 | case 2: |
| 10790 | // op: Rs32 |
| 10791 | return 16; |
| 10792 | case 0: |
| 10793 | // op: Rdd32 |
| 10794 | return 0; |
| 10795 | } |
| 10796 | break; |
| 10797 | } |
| 10798 | case Hexagon::M4_mpyrr_addi: { |
| 10799 | switch (OpNum) { |
| 10800 | case 1: |
| 10801 | // op: Ii |
| 10802 | return 5; |
| 10803 | case 2: |
| 10804 | // op: Rs32 |
| 10805 | return 16; |
| 10806 | case 3: |
| 10807 | // op: Rt32 |
| 10808 | return 8; |
| 10809 | case 0: |
| 10810 | // op: Rd32 |
| 10811 | return 0; |
| 10812 | } |
| 10813 | break; |
| 10814 | } |
| 10815 | case Hexagon::S4_lsli: { |
| 10816 | switch (OpNum) { |
| 10817 | case 1: |
| 10818 | // op: Ii |
| 10819 | return 5; |
| 10820 | case 2: |
| 10821 | // op: Rt32 |
| 10822 | return 8; |
| 10823 | case 0: |
| 10824 | // op: Rd32 |
| 10825 | return 0; |
| 10826 | } |
| 10827 | break; |
| 10828 | } |
| 10829 | case Hexagon::M4_mpyri_addi: { |
| 10830 | switch (OpNum) { |
| 10831 | case 1: |
| 10832 | // op: Ii |
| 10833 | return 5; |
| 10834 | case 3: |
| 10835 | // op: II |
| 10836 | return 0; |
| 10837 | case 2: |
| 10838 | // op: Rs32 |
| 10839 | return 16; |
| 10840 | case 0: |
| 10841 | // op: Rd32 |
| 10842 | return 8; |
| 10843 | } |
| 10844 | break; |
| 10845 | } |
| 10846 | case Hexagon::S4_storerbnew_ur: |
| 10847 | case Hexagon::S4_storerhnew_ur: |
| 10848 | case Hexagon::S4_storerinew_ur: { |
| 10849 | switch (OpNum) { |
| 10850 | case 1: |
| 10851 | // op: Ii |
| 10852 | return 6; |
| 10853 | case 2: |
| 10854 | // op: II |
| 10855 | return 0; |
| 10856 | case 0: |
| 10857 | // op: Ru32 |
| 10858 | return 16; |
| 10859 | case 3: |
| 10860 | // op: Nt8 |
| 10861 | return 8; |
| 10862 | } |
| 10863 | break; |
| 10864 | } |
| 10865 | case Hexagon::S4_storerb_ur: |
| 10866 | case Hexagon::S4_storerf_ur: |
| 10867 | case Hexagon::S4_storerh_ur: |
| 10868 | case Hexagon::S4_storeri_ur: { |
| 10869 | switch (OpNum) { |
| 10870 | case 1: |
| 10871 | // op: Ii |
| 10872 | return 6; |
| 10873 | case 2: |
| 10874 | // op: II |
| 10875 | return 0; |
| 10876 | case 0: |
| 10877 | // op: Ru32 |
| 10878 | return 16; |
| 10879 | case 3: |
| 10880 | // op: Rt32 |
| 10881 | return 8; |
| 10882 | } |
| 10883 | break; |
| 10884 | } |
| 10885 | case Hexagon::S4_storerd_ur: { |
| 10886 | switch (OpNum) { |
| 10887 | case 1: |
| 10888 | // op: Ii |
| 10889 | return 6; |
| 10890 | case 2: |
| 10891 | // op: II |
| 10892 | return 0; |
| 10893 | case 0: |
| 10894 | // op: Ru32 |
| 10895 | return 16; |
| 10896 | case 3: |
| 10897 | // op: Rtt32 |
| 10898 | return 8; |
| 10899 | } |
| 10900 | break; |
| 10901 | } |
| 10902 | case Hexagon::C4_addipc: { |
| 10903 | switch (OpNum) { |
| 10904 | case 1: |
| 10905 | // op: Ii |
| 10906 | return 7; |
| 10907 | case 0: |
| 10908 | // op: Rd32 |
| 10909 | return 0; |
| 10910 | } |
| 10911 | break; |
| 10912 | } |
| 10913 | case Hexagon::L4_add_memopb_io: |
| 10914 | case Hexagon::L4_add_memoph_io: |
| 10915 | case Hexagon::L4_add_memopw_io: |
| 10916 | case Hexagon::L4_and_memopb_io: |
| 10917 | case Hexagon::L4_and_memoph_io: |
| 10918 | case Hexagon::L4_and_memopw_io: |
| 10919 | case Hexagon::L4_or_memopb_io: |
| 10920 | case Hexagon::L4_or_memoph_io: |
| 10921 | case Hexagon::L4_or_memopw_io: |
| 10922 | case Hexagon::L4_sub_memopb_io: |
| 10923 | case Hexagon::L4_sub_memoph_io: |
| 10924 | case Hexagon::L4_sub_memopw_io: { |
| 10925 | switch (OpNum) { |
| 10926 | case 1: |
| 10927 | // op: Ii |
| 10928 | return 7; |
| 10929 | case 0: |
| 10930 | // op: Rs32 |
| 10931 | return 16; |
| 10932 | case 2: |
| 10933 | // op: Rt32 |
| 10934 | return 0; |
| 10935 | } |
| 10936 | break; |
| 10937 | } |
| 10938 | case Hexagon::L4_iadd_memopb_io: |
| 10939 | case Hexagon::L4_iadd_memoph_io: |
| 10940 | case Hexagon::L4_iadd_memopw_io: |
| 10941 | case Hexagon::L4_iand_memopb_io: |
| 10942 | case Hexagon::L4_iand_memoph_io: |
| 10943 | case Hexagon::L4_iand_memopw_io: |
| 10944 | case Hexagon::L4_ior_memopb_io: |
| 10945 | case Hexagon::L4_ior_memoph_io: |
| 10946 | case Hexagon::L4_ior_memopw_io: |
| 10947 | case Hexagon::L4_isub_memopb_io: |
| 10948 | case Hexagon::L4_isub_memoph_io: |
| 10949 | case Hexagon::L4_isub_memopw_io: |
| 10950 | case Hexagon::S4_storeirb_io: |
| 10951 | case Hexagon::S4_storeirh_io: |
| 10952 | case Hexagon::S4_storeiri_io: { |
| 10953 | switch (OpNum) { |
| 10954 | case 1: |
| 10955 | // op: Ii |
| 10956 | return 7; |
| 10957 | case 2: |
| 10958 | // op: II |
| 10959 | return 0; |
| 10960 | case 0: |
| 10961 | // op: Rs32 |
| 10962 | return 16; |
| 10963 | } |
| 10964 | break; |
| 10965 | } |
| 10966 | case Hexagon::V6_vwhist128qm: { |
| 10967 | switch (OpNum) { |
| 10968 | case 1: |
| 10969 | // op: Ii |
| 10970 | return 8; |
| 10971 | case 0: |
| 10972 | // op: Qv4 |
| 10973 | return 22; |
| 10974 | } |
| 10975 | break; |
| 10976 | } |
| 10977 | case Hexagon::SS1_storeb_io: |
| 10978 | case Hexagon::SS1_storew_io: |
| 10979 | case Hexagon::SS2_storeh_io: { |
| 10980 | switch (OpNum) { |
| 10981 | case 1: |
| 10982 | // op: Ii |
| 10983 | return 8; |
| 10984 | case 0: |
| 10985 | // op: Rs16 |
| 10986 | return 4; |
| 10987 | case 2: |
| 10988 | // op: Rt16 |
| 10989 | return 0; |
| 10990 | } |
| 10991 | break; |
| 10992 | } |
| 10993 | case Hexagon::V6_vS32b_new_ai: |
| 10994 | case Hexagon::V6_vS32b_nt_new_ai: { |
| 10995 | switch (OpNum) { |
| 10996 | case 1: |
| 10997 | // op: Ii |
| 10998 | return 8; |
| 10999 | case 0: |
| 11000 | // op: Rt32 |
| 11001 | return 16; |
| 11002 | case 2: |
| 11003 | // op: Os8 |
| 11004 | return 0; |
| 11005 | } |
| 11006 | break; |
| 11007 | } |
| 11008 | case Hexagon::V6_vS32Ub_ai: |
| 11009 | case Hexagon::V6_vS32b_ai: |
| 11010 | case Hexagon::V6_vS32b_nt_ai: { |
| 11011 | switch (OpNum) { |
| 11012 | case 1: |
| 11013 | // op: Ii |
| 11014 | return 8; |
| 11015 | case 0: |
| 11016 | // op: Rt32 |
| 11017 | return 16; |
| 11018 | case 2: |
| 11019 | // op: Vs32 |
| 11020 | return 0; |
| 11021 | } |
| 11022 | break; |
| 11023 | } |
| 11024 | case Hexagon::V6_vS32b_srls_ai: |
| 11025 | case Hexagon::V6_zLd_ai: { |
| 11026 | switch (OpNum) { |
| 11027 | case 1: |
| 11028 | // op: Ii |
| 11029 | return 8; |
| 11030 | case 0: |
| 11031 | // op: Rt32 |
| 11032 | return 16; |
| 11033 | } |
| 11034 | break; |
| 11035 | } |
| 11036 | case Hexagon::S2_mask: { |
| 11037 | switch (OpNum) { |
| 11038 | case 1: |
| 11039 | // op: Ii |
| 11040 | return 8; |
| 11041 | case 2: |
| 11042 | // op: II |
| 11043 | return 5; |
| 11044 | case 0: |
| 11045 | // op: Rd32 |
| 11046 | return 0; |
| 11047 | } |
| 11048 | break; |
| 11049 | } |
| 11050 | case Hexagon::C2_all8: |
| 11051 | case Hexagon::C2_any8: |
| 11052 | case Hexagon::C2_not: { |
| 11053 | switch (OpNum) { |
| 11054 | case 1: |
| 11055 | // op: Ps4 |
| 11056 | return 16; |
| 11057 | case 0: |
| 11058 | // op: Pd4 |
| 11059 | return 0; |
| 11060 | } |
| 11061 | break; |
| 11062 | } |
| 11063 | case Hexagon::C2_tfrpr: { |
| 11064 | switch (OpNum) { |
| 11065 | case 1: |
| 11066 | // op: Ps4 |
| 11067 | return 16; |
| 11068 | case 0: |
| 11069 | // op: Rd32 |
| 11070 | return 0; |
| 11071 | } |
| 11072 | break; |
| 11073 | } |
| 11074 | case Hexagon::C2_xor: |
| 11075 | case Hexagon::C4_fastcorner9: |
| 11076 | case Hexagon::C4_fastcorner9_not: { |
| 11077 | switch (OpNum) { |
| 11078 | case 1: |
| 11079 | // op: Ps4 |
| 11080 | return 16; |
| 11081 | case 2: |
| 11082 | // op: Pt4 |
| 11083 | return 8; |
| 11084 | case 0: |
| 11085 | // op: Pd4 |
| 11086 | return 0; |
| 11087 | } |
| 11088 | break; |
| 11089 | } |
| 11090 | case Hexagon::C2_vitpack: { |
| 11091 | switch (OpNum) { |
| 11092 | case 1: |
| 11093 | // op: Ps4 |
| 11094 | return 16; |
| 11095 | case 2: |
| 11096 | // op: Pt4 |
| 11097 | return 8; |
| 11098 | case 0: |
| 11099 | // op: Rd32 |
| 11100 | return 0; |
| 11101 | } |
| 11102 | break; |
| 11103 | } |
| 11104 | case Hexagon::C4_and_and: |
| 11105 | case Hexagon::C4_and_andn: |
| 11106 | case Hexagon::C4_and_or: |
| 11107 | case Hexagon::C4_and_orn: |
| 11108 | case Hexagon::C4_or_and: |
| 11109 | case Hexagon::C4_or_andn: |
| 11110 | case Hexagon::C4_or_or: |
| 11111 | case Hexagon::C4_or_orn: { |
| 11112 | switch (OpNum) { |
| 11113 | case 1: |
| 11114 | // op: Ps4 |
| 11115 | return 16; |
| 11116 | case 2: |
| 11117 | // op: Pt4 |
| 11118 | return 8; |
| 11119 | case 3: |
| 11120 | // op: Pu4 |
| 11121 | return 6; |
| 11122 | case 0: |
| 11123 | // op: Pd4 |
| 11124 | return 0; |
| 11125 | } |
| 11126 | break; |
| 11127 | } |
| 11128 | case Hexagon::V6_vcmov: |
| 11129 | case Hexagon::V6_vncmov: { |
| 11130 | switch (OpNum) { |
| 11131 | case 1: |
| 11132 | // op: Ps4 |
| 11133 | return 5; |
| 11134 | case 2: |
| 11135 | // op: Vu32 |
| 11136 | return 8; |
| 11137 | case 0: |
| 11138 | // op: Vd32 |
| 11139 | return 0; |
| 11140 | } |
| 11141 | break; |
| 11142 | } |
| 11143 | case Hexagon::V6_vccombine: |
| 11144 | case Hexagon::V6_vnccombine: { |
| 11145 | switch (OpNum) { |
| 11146 | case 1: |
| 11147 | // op: Ps4 |
| 11148 | return 5; |
| 11149 | case 2: |
| 11150 | // op: Vu32 |
| 11151 | return 8; |
| 11152 | case 3: |
| 11153 | // op: Vv32 |
| 11154 | return 16; |
| 11155 | case 0: |
| 11156 | // op: Vdd32 |
| 11157 | return 0; |
| 11158 | } |
| 11159 | break; |
| 11160 | } |
| 11161 | case Hexagon::C2_mask: { |
| 11162 | switch (OpNum) { |
| 11163 | case 1: |
| 11164 | // op: Pt4 |
| 11165 | return 8; |
| 11166 | case 0: |
| 11167 | // op: Rdd32 |
| 11168 | return 0; |
| 11169 | } |
| 11170 | break; |
| 11171 | } |
| 11172 | case Hexagon::C2_and: |
| 11173 | case Hexagon::C2_andn: |
| 11174 | case Hexagon::C2_or: |
| 11175 | case Hexagon::C2_orn: { |
| 11176 | switch (OpNum) { |
| 11177 | case 1: |
| 11178 | // op: Pt4 |
| 11179 | return 8; |
| 11180 | case 2: |
| 11181 | // op: Ps4 |
| 11182 | return 16; |
| 11183 | case 0: |
| 11184 | // op: Pd4 |
| 11185 | return 0; |
| 11186 | } |
| 11187 | break; |
| 11188 | } |
| 11189 | case Hexagon::A2_paddf: |
| 11190 | case Hexagon::A2_paddfnew: |
| 11191 | case Hexagon::A2_paddt: |
| 11192 | case Hexagon::A2_paddtnew: |
| 11193 | case Hexagon::A2_pandf: |
| 11194 | case Hexagon::A2_pandfnew: |
| 11195 | case Hexagon::A2_pandt: |
| 11196 | case Hexagon::A2_pandtnew: |
| 11197 | case Hexagon::A2_porf: |
| 11198 | case Hexagon::A2_porfnew: |
| 11199 | case Hexagon::A2_port: |
| 11200 | case Hexagon::A2_portnew: |
| 11201 | case Hexagon::A2_pxorf: |
| 11202 | case Hexagon::A2_pxorfnew: |
| 11203 | case Hexagon::A2_pxort: |
| 11204 | case Hexagon::A2_pxortnew: |
| 11205 | case Hexagon::C2_mux: { |
| 11206 | switch (OpNum) { |
| 11207 | case 1: |
| 11208 | // op: Pu4 |
| 11209 | return 5; |
| 11210 | case 2: |
| 11211 | // op: Rs32 |
| 11212 | return 16; |
| 11213 | case 3: |
| 11214 | // op: Rt32 |
| 11215 | return 8; |
| 11216 | case 0: |
| 11217 | // op: Rd32 |
| 11218 | return 0; |
| 11219 | } |
| 11220 | break; |
| 11221 | } |
| 11222 | case Hexagon::C2_ccombinewf: |
| 11223 | case Hexagon::C2_ccombinewnewf: |
| 11224 | case Hexagon::C2_ccombinewnewt: |
| 11225 | case Hexagon::C2_ccombinewt: { |
| 11226 | switch (OpNum) { |
| 11227 | case 1: |
| 11228 | // op: Pu4 |
| 11229 | return 5; |
| 11230 | case 2: |
| 11231 | // op: Rs32 |
| 11232 | return 16; |
| 11233 | case 3: |
| 11234 | // op: Rt32 |
| 11235 | return 8; |
| 11236 | case 0: |
| 11237 | // op: Rdd32 |
| 11238 | return 0; |
| 11239 | } |
| 11240 | break; |
| 11241 | } |
| 11242 | case Hexagon::C2_vmux: { |
| 11243 | switch (OpNum) { |
| 11244 | case 1: |
| 11245 | // op: Pu4 |
| 11246 | return 5; |
| 11247 | case 2: |
| 11248 | // op: Rss32 |
| 11249 | return 16; |
| 11250 | case 3: |
| 11251 | // op: Rtt32 |
| 11252 | return 8; |
| 11253 | case 0: |
| 11254 | // op: Rdd32 |
| 11255 | return 0; |
| 11256 | } |
| 11257 | break; |
| 11258 | } |
| 11259 | case Hexagon::A2_psubf: |
| 11260 | case Hexagon::A2_psubfnew: |
| 11261 | case Hexagon::A2_psubt: |
| 11262 | case Hexagon::A2_psubtnew: { |
| 11263 | switch (OpNum) { |
| 11264 | case 1: |
| 11265 | // op: Pu4 |
| 11266 | return 5; |
| 11267 | case 2: |
| 11268 | // op: Rt32 |
| 11269 | return 8; |
| 11270 | case 3: |
| 11271 | // op: Rs32 |
| 11272 | return 16; |
| 11273 | case 0: |
| 11274 | // op: Rd32 |
| 11275 | return 0; |
| 11276 | } |
| 11277 | break; |
| 11278 | } |
| 11279 | case Hexagon::A4_paslhf: |
| 11280 | case Hexagon::A4_paslhfnew: |
| 11281 | case Hexagon::A4_paslht: |
| 11282 | case Hexagon::A4_paslhtnew: |
| 11283 | case Hexagon::A4_pasrhf: |
| 11284 | case Hexagon::A4_pasrhfnew: |
| 11285 | case Hexagon::A4_pasrht: |
| 11286 | case Hexagon::A4_pasrhtnew: |
| 11287 | case Hexagon::A4_psxtbf: |
| 11288 | case Hexagon::A4_psxtbfnew: |
| 11289 | case Hexagon::A4_psxtbt: |
| 11290 | case Hexagon::A4_psxtbtnew: |
| 11291 | case Hexagon::A4_psxthf: |
| 11292 | case Hexagon::A4_psxthfnew: |
| 11293 | case Hexagon::A4_psxtht: |
| 11294 | case Hexagon::A4_psxthtnew: |
| 11295 | case Hexagon::A4_pzxtbf: |
| 11296 | case Hexagon::A4_pzxtbfnew: |
| 11297 | case Hexagon::A4_pzxtbt: |
| 11298 | case Hexagon::A4_pzxtbtnew: |
| 11299 | case Hexagon::A4_pzxthf: |
| 11300 | case Hexagon::A4_pzxthfnew: |
| 11301 | case Hexagon::A4_pzxtht: |
| 11302 | case Hexagon::A4_pzxthtnew: { |
| 11303 | switch (OpNum) { |
| 11304 | case 1: |
| 11305 | // op: Pu4 |
| 11306 | return 8; |
| 11307 | case 2: |
| 11308 | // op: Rs32 |
| 11309 | return 16; |
| 11310 | case 0: |
| 11311 | // op: Rd32 |
| 11312 | return 0; |
| 11313 | } |
| 11314 | break; |
| 11315 | } |
| 11316 | case Hexagon::V6_zLd_pred_ppu: { |
| 11317 | switch (OpNum) { |
| 11318 | case 1: |
| 11319 | // op: Pv4 |
| 11320 | return 11; |
| 11321 | case 3: |
| 11322 | // op: Mu2 |
| 11323 | return 13; |
| 11324 | case 0: |
| 11325 | // op: Rx32 |
| 11326 | return 16; |
| 11327 | } |
| 11328 | break; |
| 11329 | } |
| 11330 | case Hexagon::V6_vS32b_new_npred_ppu: |
| 11331 | case Hexagon::V6_vS32b_new_pred_ppu: |
| 11332 | case Hexagon::V6_vS32b_nt_new_npred_ppu: |
| 11333 | case Hexagon::V6_vS32b_nt_new_pred_ppu: { |
| 11334 | switch (OpNum) { |
| 11335 | case 1: |
| 11336 | // op: Pv4 |
| 11337 | return 11; |
| 11338 | case 3: |
| 11339 | // op: Mu2 |
| 11340 | return 13; |
| 11341 | case 4: |
| 11342 | // op: Os8 |
| 11343 | return 0; |
| 11344 | case 0: |
| 11345 | // op: Rx32 |
| 11346 | return 16; |
| 11347 | } |
| 11348 | break; |
| 11349 | } |
| 11350 | case Hexagon::V6_vS32Ub_npred_ppu: |
| 11351 | case Hexagon::V6_vS32Ub_pred_ppu: |
| 11352 | case Hexagon::V6_vS32b_npred_ppu: |
| 11353 | case Hexagon::V6_vS32b_nt_npred_ppu: |
| 11354 | case Hexagon::V6_vS32b_nt_pred_ppu: |
| 11355 | case Hexagon::V6_vS32b_pred_ppu: { |
| 11356 | switch (OpNum) { |
| 11357 | case 1: |
| 11358 | // op: Pv4 |
| 11359 | return 11; |
| 11360 | case 3: |
| 11361 | // op: Mu2 |
| 11362 | return 13; |
| 11363 | case 4: |
| 11364 | // op: Vs32 |
| 11365 | return 0; |
| 11366 | case 0: |
| 11367 | // op: Rx32 |
| 11368 | return 16; |
| 11369 | } |
| 11370 | break; |
| 11371 | } |
| 11372 | case Hexagon::L4_return_f: |
| 11373 | case Hexagon::L4_return_fnew_pnt: |
| 11374 | case Hexagon::L4_return_fnew_pt: |
| 11375 | case Hexagon::L4_return_t: |
| 11376 | case Hexagon::L4_return_tnew_pnt: |
| 11377 | case Hexagon::L4_return_tnew_pt: { |
| 11378 | switch (OpNum) { |
| 11379 | case 1: |
| 11380 | // op: Pv4 |
| 11381 | return 8; |
| 11382 | case 2: |
| 11383 | // op: Rs32 |
| 11384 | return 16; |
| 11385 | case 0: |
| 11386 | // op: Rdd32 |
| 11387 | return 0; |
| 11388 | } |
| 11389 | break; |
| 11390 | } |
| 11391 | case Hexagon::V6_pred_not: { |
| 11392 | switch (OpNum) { |
| 11393 | case 1: |
| 11394 | // op: Qs4 |
| 11395 | return 8; |
| 11396 | case 0: |
| 11397 | // op: Qd4 |
| 11398 | return 0; |
| 11399 | } |
| 11400 | break; |
| 11401 | } |
| 11402 | case Hexagon::V6_pred_and: |
| 11403 | case Hexagon::V6_pred_and_n: |
| 11404 | case Hexagon::V6_pred_or: |
| 11405 | case Hexagon::V6_pred_or_n: |
| 11406 | case Hexagon::V6_pred_xor: |
| 11407 | case Hexagon::V6_shuffeqh: |
| 11408 | case Hexagon::V6_shuffeqw: { |
| 11409 | switch (OpNum) { |
| 11410 | case 1: |
| 11411 | // op: Qs4 |
| 11412 | return 8; |
| 11413 | case 2: |
| 11414 | // op: Qt4 |
| 11415 | return 22; |
| 11416 | case 0: |
| 11417 | // op: Qd4 |
| 11418 | return 0; |
| 11419 | } |
| 11420 | break; |
| 11421 | } |
| 11422 | case Hexagon::V6_vmux: { |
| 11423 | switch (OpNum) { |
| 11424 | case 1: |
| 11425 | // op: Qt4 |
| 11426 | return 5; |
| 11427 | case 2: |
| 11428 | // op: Vu32 |
| 11429 | return 8; |
| 11430 | case 3: |
| 11431 | // op: Vv32 |
| 11432 | return 16; |
| 11433 | case 0: |
| 11434 | // op: Vd32 |
| 11435 | return 0; |
| 11436 | } |
| 11437 | break; |
| 11438 | } |
| 11439 | case Hexagon::V6_vswap: { |
| 11440 | switch (OpNum) { |
| 11441 | case 1: |
| 11442 | // op: Qt4 |
| 11443 | return 5; |
| 11444 | case 2: |
| 11445 | // op: Vu32 |
| 11446 | return 8; |
| 11447 | case 3: |
| 11448 | // op: Vv32 |
| 11449 | return 16; |
| 11450 | case 0: |
| 11451 | // op: Vdd32 |
| 11452 | return 0; |
| 11453 | } |
| 11454 | break; |
| 11455 | } |
| 11456 | case Hexagon::V6_vandnqrt: |
| 11457 | case Hexagon::V6_vandqrt: { |
| 11458 | switch (OpNum) { |
| 11459 | case 1: |
| 11460 | // op: Qu4 |
| 11461 | return 8; |
| 11462 | case 2: |
| 11463 | // op: Rt32 |
| 11464 | return 16; |
| 11465 | case 0: |
| 11466 | // op: Vd32 |
| 11467 | return 0; |
| 11468 | } |
| 11469 | break; |
| 11470 | } |
| 11471 | case Hexagon::V6_vS32b_nqpred_ppu: |
| 11472 | case Hexagon::V6_vS32b_nt_nqpred_ppu: |
| 11473 | case Hexagon::V6_vS32b_nt_qpred_ppu: |
| 11474 | case Hexagon::V6_vS32b_qpred_ppu: { |
| 11475 | switch (OpNum) { |
| 11476 | case 1: |
| 11477 | // op: Qv4 |
| 11478 | return 11; |
| 11479 | case 3: |
| 11480 | // op: Mu2 |
| 11481 | return 13; |
| 11482 | case 4: |
| 11483 | // op: Vs32 |
| 11484 | return 0; |
| 11485 | case 0: |
| 11486 | // op: Rx32 |
| 11487 | return 16; |
| 11488 | } |
| 11489 | break; |
| 11490 | } |
| 11491 | case Hexagon::V6_vprefixqb: |
| 11492 | case Hexagon::V6_vprefixqh: |
| 11493 | case Hexagon::V6_vprefixqw: { |
| 11494 | switch (OpNum) { |
| 11495 | case 1: |
| 11496 | // op: Qv4 |
| 11497 | return 22; |
| 11498 | case 0: |
| 11499 | // op: Vd32 |
| 11500 | return 0; |
| 11501 | } |
| 11502 | break; |
| 11503 | } |
| 11504 | case Hexagon::V6_vandvnqv: |
| 11505 | case Hexagon::V6_vandvqv: { |
| 11506 | switch (OpNum) { |
| 11507 | case 1: |
| 11508 | // op: Qv4 |
| 11509 | return 22; |
| 11510 | case 2: |
| 11511 | // op: Vu32 |
| 11512 | return 8; |
| 11513 | case 0: |
| 11514 | // op: Vd32 |
| 11515 | return 0; |
| 11516 | } |
| 11517 | break; |
| 11518 | } |
| 11519 | case Hexagon::V6_vaddbnq: |
| 11520 | case Hexagon::V6_vaddbq: |
| 11521 | case Hexagon::V6_vaddhnq: |
| 11522 | case Hexagon::V6_vaddhq: |
| 11523 | case Hexagon::V6_vaddwnq: |
| 11524 | case Hexagon::V6_vaddwq: |
| 11525 | case Hexagon::V6_vsubbnq: |
| 11526 | case Hexagon::V6_vsubbq: |
| 11527 | case Hexagon::V6_vsubhnq: |
| 11528 | case Hexagon::V6_vsubhq: |
| 11529 | case Hexagon::V6_vsubwnq: |
| 11530 | case Hexagon::V6_vsubwq: { |
| 11531 | switch (OpNum) { |
| 11532 | case 1: |
| 11533 | // op: Qv4 |
| 11534 | return 22; |
| 11535 | case 3: |
| 11536 | // op: Vu32 |
| 11537 | return 8; |
| 11538 | case 0: |
| 11539 | // op: Vx32 |
| 11540 | return 0; |
| 11541 | } |
| 11542 | break; |
| 11543 | } |
| 11544 | case Hexagon::SA1_and1: |
| 11545 | case Hexagon::SA1_dec: |
| 11546 | case Hexagon::SA1_inc: |
| 11547 | case Hexagon::SA1_sxtb: |
| 11548 | case Hexagon::SA1_sxth: |
| 11549 | case Hexagon::SA1_tfr: |
| 11550 | case Hexagon::SA1_zxtb: |
| 11551 | case Hexagon::SA1_zxth: { |
| 11552 | switch (OpNum) { |
| 11553 | case 1: |
| 11554 | // op: Rs16 |
| 11555 | return 4; |
| 11556 | case 0: |
| 11557 | // op: Rd16 |
| 11558 | return 0; |
| 11559 | } |
| 11560 | break; |
| 11561 | } |
| 11562 | case Hexagon::SA1_combinerz: |
| 11563 | case Hexagon::SA1_combinezr: { |
| 11564 | switch (OpNum) { |
| 11565 | case 1: |
| 11566 | // op: Rs16 |
| 11567 | return 4; |
| 11568 | case 0: |
| 11569 | // op: Rdd8 |
| 11570 | return 0; |
| 11571 | } |
| 11572 | break; |
| 11573 | } |
| 11574 | case Hexagon::A2_tfrrcr: { |
| 11575 | switch (OpNum) { |
| 11576 | case 1: |
| 11577 | // op: Rs32 |
| 11578 | return 16; |
| 11579 | case 0: |
| 11580 | // op: Cd32 |
| 11581 | return 0; |
| 11582 | } |
| 11583 | break; |
| 11584 | } |
| 11585 | case Hexagon::G4_tfrgrcr: { |
| 11586 | switch (OpNum) { |
| 11587 | case 1: |
| 11588 | // op: Rs32 |
| 11589 | return 16; |
| 11590 | case 0: |
| 11591 | // op: Gd32 |
| 11592 | return 0; |
| 11593 | } |
| 11594 | break; |
| 11595 | } |
| 11596 | case Hexagon::C2_tfrrp: |
| 11597 | case Hexagon::Y5_l2locka: { |
| 11598 | switch (OpNum) { |
| 11599 | case 1: |
| 11600 | // op: Rs32 |
| 11601 | return 16; |
| 11602 | case 0: |
| 11603 | // op: Pd4 |
| 11604 | return 0; |
| 11605 | } |
| 11606 | break; |
| 11607 | } |
| 11608 | case Hexagon::A2_abs: |
| 11609 | case Hexagon::A2_abssat: |
| 11610 | case Hexagon::A2_aslh: |
| 11611 | case Hexagon::A2_asrh: |
| 11612 | case Hexagon::A2_negsat: |
| 11613 | case Hexagon::A2_satb: |
| 11614 | case Hexagon::A2_sath: |
| 11615 | case Hexagon::A2_satub: |
| 11616 | case Hexagon::A2_satuh: |
| 11617 | case Hexagon::A2_swiz: |
| 11618 | case Hexagon::A2_sxtb: |
| 11619 | case Hexagon::A2_sxth: |
| 11620 | case Hexagon::A2_tfr: |
| 11621 | case Hexagon::A2_zxth: |
| 11622 | case Hexagon::F2_conv_sf2uw: |
| 11623 | case Hexagon::F2_conv_sf2uw_chop: |
| 11624 | case Hexagon::F2_conv_sf2w: |
| 11625 | case Hexagon::F2_conv_sf2w_chop: |
| 11626 | case Hexagon::F2_conv_uw2sf: |
| 11627 | case Hexagon::F2_conv_w2sf: |
| 11628 | case Hexagon::F2_sffixupr: |
| 11629 | case Hexagon::L2_loadw_aq: |
| 11630 | case Hexagon::L2_loadw_locked: |
| 11631 | case Hexagon::S2_brev: |
| 11632 | case Hexagon::S2_cl0: |
| 11633 | case Hexagon::S2_cl1: |
| 11634 | case Hexagon::S2_clb: |
| 11635 | case Hexagon::S2_clbnorm: |
| 11636 | case Hexagon::S2_ct0: |
| 11637 | case Hexagon::S2_ct1: |
| 11638 | case Hexagon::S2_svsathb: |
| 11639 | case Hexagon::S2_svsathub: |
| 11640 | case Hexagon::S2_vsplatrb: |
| 11641 | case Hexagon::Y2_dctagr: |
| 11642 | case Hexagon::Y2_getimask: |
| 11643 | case Hexagon::Y2_iassignr: |
| 11644 | case Hexagon::Y2_icdatar: |
| 11645 | case Hexagon::Y2_ictagr: |
| 11646 | case Hexagon::Y2_tlbp: |
| 11647 | case Hexagon::Y4_l2tagr: { |
| 11648 | switch (OpNum) { |
| 11649 | case 1: |
| 11650 | // op: Rs32 |
| 11651 | return 16; |
| 11652 | case 0: |
| 11653 | // op: Rd32 |
| 11654 | return 0; |
| 11655 | } |
| 11656 | break; |
| 11657 | } |
| 11658 | case Hexagon::A2_sxtw: |
| 11659 | case Hexagon::F2_conv_sf2d: |
| 11660 | case Hexagon::F2_conv_sf2d_chop: |
| 11661 | case Hexagon::F2_conv_sf2df: |
| 11662 | case Hexagon::F2_conv_sf2ud: |
| 11663 | case Hexagon::F2_conv_sf2ud_chop: |
| 11664 | case Hexagon::F2_conv_uw2df: |
| 11665 | case Hexagon::F2_conv_w2df: |
| 11666 | case Hexagon::L2_deallocframe: |
| 11667 | case Hexagon::L4_loadd_aq: |
| 11668 | case Hexagon::L4_loadd_locked: |
| 11669 | case Hexagon::L4_return: |
| 11670 | case Hexagon::S2_vsplatrh: |
| 11671 | case Hexagon::S2_vsxtbh: |
| 11672 | case Hexagon::S2_vsxthw: |
| 11673 | case Hexagon::S2_vzxtbh: |
| 11674 | case Hexagon::S2_vzxthw: |
| 11675 | case Hexagon::S6_vsplatrbp: |
| 11676 | case Hexagon::Y2_tlbr: { |
| 11677 | switch (OpNum) { |
| 11678 | case 1: |
| 11679 | // op: Rs32 |
| 11680 | return 16; |
| 11681 | case 0: |
| 11682 | // op: Rdd32 |
| 11683 | return 0; |
| 11684 | } |
| 11685 | break; |
| 11686 | } |
| 11687 | case Hexagon::Y2_tfrsrcr: { |
| 11688 | switch (OpNum) { |
| 11689 | case 1: |
| 11690 | // op: Rs32 |
| 11691 | return 16; |
| 11692 | case 0: |
| 11693 | // op: Sd128 |
| 11694 | return 0; |
| 11695 | } |
| 11696 | break; |
| 11697 | } |
| 11698 | case Hexagon::A4_cmpbeq: |
| 11699 | case Hexagon::A4_cmpbgt: |
| 11700 | case Hexagon::A4_cmpbgtu: |
| 11701 | case Hexagon::A4_cmpheq: |
| 11702 | case Hexagon::A4_cmphgt: |
| 11703 | case Hexagon::A4_cmphgtu: |
| 11704 | case Hexagon::C2_bitsclr: |
| 11705 | case Hexagon::C2_bitsset: |
| 11706 | case Hexagon::C2_cmpeq: |
| 11707 | case Hexagon::C2_cmpgt: |
| 11708 | case Hexagon::C2_cmpgtu: |
| 11709 | case Hexagon::C4_cmplte: |
| 11710 | case Hexagon::C4_cmplteu: |
| 11711 | case Hexagon::C4_cmpneq: |
| 11712 | case Hexagon::C4_nbitsclr: |
| 11713 | case Hexagon::C4_nbitsset: |
| 11714 | case Hexagon::F2_sfcmpeq: |
| 11715 | case Hexagon::F2_sfcmpge: |
| 11716 | case Hexagon::F2_sfcmpgt: |
| 11717 | case Hexagon::F2_sfcmpuo: |
| 11718 | case Hexagon::S2_storew_locked: |
| 11719 | case Hexagon::S2_tstbit_r: |
| 11720 | case Hexagon::S4_ntstbit_r: { |
| 11721 | switch (OpNum) { |
| 11722 | case 1: |
| 11723 | // op: Rs32 |
| 11724 | return 16; |
| 11725 | case 2: |
| 11726 | // op: Rt32 |
| 11727 | return 8; |
| 11728 | case 0: |
| 11729 | // op: Pd4 |
| 11730 | return 0; |
| 11731 | } |
| 11732 | break; |
| 11733 | } |
| 11734 | case Hexagon::A2_add: |
| 11735 | case Hexagon::A2_addsat: |
| 11736 | case Hexagon::A2_and: |
| 11737 | case Hexagon::A2_max: |
| 11738 | case Hexagon::A2_maxu: |
| 11739 | case Hexagon::A2_or: |
| 11740 | case Hexagon::A2_svaddh: |
| 11741 | case Hexagon::A2_svaddhs: |
| 11742 | case Hexagon::A2_svadduhs: |
| 11743 | case Hexagon::A2_svavgh: |
| 11744 | case Hexagon::A2_svavghs: |
| 11745 | case Hexagon::A2_xor: |
| 11746 | case Hexagon::A4_cround_rr: |
| 11747 | case Hexagon::A4_modwrapu: |
| 11748 | case Hexagon::A4_rcmpeq: |
| 11749 | case Hexagon::A4_rcmpneq: |
| 11750 | case Hexagon::A4_round_rr: |
| 11751 | case Hexagon::A4_round_rr_sat: |
| 11752 | case Hexagon::F2_sfadd: |
| 11753 | case Hexagon::F2_sffixupd: |
| 11754 | case Hexagon::F2_sffixupn: |
| 11755 | case Hexagon::F2_sfmax: |
| 11756 | case Hexagon::F2_sfmin: |
| 11757 | case Hexagon::F2_sfmpy: |
| 11758 | case Hexagon::F2_sfsub: |
| 11759 | case Hexagon::L4_loadw_phys: |
| 11760 | case Hexagon::M2_cmpyrs_s0: |
| 11761 | case Hexagon::M2_cmpyrs_s1: |
| 11762 | case Hexagon::M2_cmpyrsc_s0: |
| 11763 | case Hexagon::M2_cmpyrsc_s1: |
| 11764 | case Hexagon::M2_dpmpyss_rnd_s0: |
| 11765 | case Hexagon::M2_hmmpyh_rs1: |
| 11766 | case Hexagon::M2_hmmpyh_s1: |
| 11767 | case Hexagon::M2_hmmpyl_rs1: |
| 11768 | case Hexagon::M2_hmmpyl_s1: |
| 11769 | case Hexagon::M2_mpy_hh_s0: |
| 11770 | case Hexagon::M2_mpy_hh_s1: |
| 11771 | case Hexagon::M2_mpy_hl_s0: |
| 11772 | case Hexagon::M2_mpy_hl_s1: |
| 11773 | case Hexagon::M2_mpy_lh_s0: |
| 11774 | case Hexagon::M2_mpy_lh_s1: |
| 11775 | case Hexagon::M2_mpy_ll_s0: |
| 11776 | case Hexagon::M2_mpy_ll_s1: |
| 11777 | case Hexagon::M2_mpy_rnd_hh_s0: |
| 11778 | case Hexagon::M2_mpy_rnd_hh_s1: |
| 11779 | case Hexagon::M2_mpy_rnd_hl_s0: |
| 11780 | case Hexagon::M2_mpy_rnd_hl_s1: |
| 11781 | case Hexagon::M2_mpy_rnd_lh_s0: |
| 11782 | case Hexagon::M2_mpy_rnd_lh_s1: |
| 11783 | case Hexagon::M2_mpy_rnd_ll_s0: |
| 11784 | case Hexagon::M2_mpy_rnd_ll_s1: |
| 11785 | case Hexagon::M2_mpy_sat_hh_s0: |
| 11786 | case Hexagon::M2_mpy_sat_hh_s1: |
| 11787 | case Hexagon::M2_mpy_sat_hl_s0: |
| 11788 | case Hexagon::M2_mpy_sat_hl_s1: |
| 11789 | case Hexagon::M2_mpy_sat_lh_s0: |
| 11790 | case Hexagon::M2_mpy_sat_lh_s1: |
| 11791 | case Hexagon::M2_mpy_sat_ll_s0: |
| 11792 | case Hexagon::M2_mpy_sat_ll_s1: |
| 11793 | case Hexagon::M2_mpy_sat_rnd_hh_s0: |
| 11794 | case Hexagon::M2_mpy_sat_rnd_hh_s1: |
| 11795 | case Hexagon::M2_mpy_sat_rnd_hl_s0: |
| 11796 | case Hexagon::M2_mpy_sat_rnd_hl_s1: |
| 11797 | case Hexagon::M2_mpy_sat_rnd_lh_s0: |
| 11798 | case Hexagon::M2_mpy_sat_rnd_lh_s1: |
| 11799 | case Hexagon::M2_mpy_sat_rnd_ll_s0: |
| 11800 | case Hexagon::M2_mpy_sat_rnd_ll_s1: |
| 11801 | case Hexagon::M2_mpy_up: |
| 11802 | case Hexagon::M2_mpy_up_s1: |
| 11803 | case Hexagon::M2_mpy_up_s1_sat: |
| 11804 | case Hexagon::M2_mpyi: |
| 11805 | case Hexagon::M2_mpysu_up: |
| 11806 | case Hexagon::M2_mpyu_hh_s0: |
| 11807 | case Hexagon::M2_mpyu_hh_s1: |
| 11808 | case Hexagon::M2_mpyu_hl_s0: |
| 11809 | case Hexagon::M2_mpyu_hl_s1: |
| 11810 | case Hexagon::M2_mpyu_lh_s0: |
| 11811 | case Hexagon::M2_mpyu_lh_s1: |
| 11812 | case Hexagon::M2_mpyu_ll_s0: |
| 11813 | case Hexagon::M2_mpyu_ll_s1: |
| 11814 | case Hexagon::M2_mpyu_up: |
| 11815 | case Hexagon::M2_vmpy2s_s0pack: |
| 11816 | case Hexagon::M2_vmpy2s_s1pack: |
| 11817 | case Hexagon::S2_asl_r_r: |
| 11818 | case Hexagon::S2_asl_r_r_sat: |
| 11819 | case Hexagon::S2_asr_r_r: |
| 11820 | case Hexagon::S2_asr_r_r_sat: |
| 11821 | case Hexagon::S2_clrbit_r: |
| 11822 | case Hexagon::S2_lsl_r_r: |
| 11823 | case Hexagon::S2_lsr_r_r: |
| 11824 | case Hexagon::S2_setbit_r: |
| 11825 | case Hexagon::S2_togglebit_r: |
| 11826 | case Hexagon::S4_parity: |
| 11827 | case Hexagon::dep_A2_addsat: { |
| 11828 | switch (OpNum) { |
| 11829 | case 1: |
| 11830 | // op: Rs32 |
| 11831 | return 16; |
| 11832 | case 2: |
| 11833 | // op: Rt32 |
| 11834 | return 8; |
| 11835 | case 0: |
| 11836 | // op: Rd32 |
| 11837 | return 0; |
| 11838 | } |
| 11839 | break; |
| 11840 | } |
| 11841 | case Hexagon::A2_combinew: |
| 11842 | case Hexagon::A4_bitsplit: |
| 11843 | case Hexagon::M2_cmpyi_s0: |
| 11844 | case Hexagon::M2_cmpyr_s0: |
| 11845 | case Hexagon::M2_cmpys_s0: |
| 11846 | case Hexagon::M2_cmpys_s1: |
| 11847 | case Hexagon::M2_cmpysc_s0: |
| 11848 | case Hexagon::M2_cmpysc_s1: |
| 11849 | case Hexagon::M2_dpmpyss_s0: |
| 11850 | case Hexagon::M2_dpmpyuu_s0: |
| 11851 | case Hexagon::M2_mpyd_hh_s0: |
| 11852 | case Hexagon::M2_mpyd_hh_s1: |
| 11853 | case Hexagon::M2_mpyd_hl_s0: |
| 11854 | case Hexagon::M2_mpyd_hl_s1: |
| 11855 | case Hexagon::M2_mpyd_lh_s0: |
| 11856 | case Hexagon::M2_mpyd_lh_s1: |
| 11857 | case Hexagon::M2_mpyd_ll_s0: |
| 11858 | case Hexagon::M2_mpyd_ll_s1: |
| 11859 | case Hexagon::M2_mpyd_rnd_hh_s0: |
| 11860 | case Hexagon::M2_mpyd_rnd_hh_s1: |
| 11861 | case Hexagon::M2_mpyd_rnd_hl_s0: |
| 11862 | case Hexagon::M2_mpyd_rnd_hl_s1: |
| 11863 | case Hexagon::M2_mpyd_rnd_lh_s0: |
| 11864 | case Hexagon::M2_mpyd_rnd_lh_s1: |
| 11865 | case Hexagon::M2_mpyd_rnd_ll_s0: |
| 11866 | case Hexagon::M2_mpyd_rnd_ll_s1: |
| 11867 | case Hexagon::M2_mpyud_hh_s0: |
| 11868 | case Hexagon::M2_mpyud_hh_s1: |
| 11869 | case Hexagon::M2_mpyud_hl_s0: |
| 11870 | case Hexagon::M2_mpyud_hl_s1: |
| 11871 | case Hexagon::M2_mpyud_lh_s0: |
| 11872 | case Hexagon::M2_mpyud_lh_s1: |
| 11873 | case Hexagon::M2_mpyud_ll_s0: |
| 11874 | case Hexagon::M2_mpyud_ll_s1: |
| 11875 | case Hexagon::M2_vmpy2s_s0: |
| 11876 | case Hexagon::M2_vmpy2s_s1: |
| 11877 | case Hexagon::M2_vmpy2su_s0: |
| 11878 | case Hexagon::M2_vmpy2su_s1: |
| 11879 | case Hexagon::M4_pmpyw: |
| 11880 | case Hexagon::M4_vpmpyh: |
| 11881 | case Hexagon::M5_vmpybsu: |
| 11882 | case Hexagon::M5_vmpybuu: |
| 11883 | case Hexagon::S2_packhl: |
| 11884 | case Hexagon::dep_S2_packhl: { |
| 11885 | switch (OpNum) { |
| 11886 | case 1: |
| 11887 | // op: Rs32 |
| 11888 | return 16; |
| 11889 | case 2: |
| 11890 | // op: Rt32 |
| 11891 | return 8; |
| 11892 | case 0: |
| 11893 | // op: Rdd32 |
| 11894 | return 0; |
| 11895 | } |
| 11896 | break; |
| 11897 | } |
| 11898 | case Hexagon::S4_stored_locked: { |
| 11899 | switch (OpNum) { |
| 11900 | case 1: |
| 11901 | // op: Rs32 |
| 11902 | return 16; |
| 11903 | case 2: |
| 11904 | // op: Rtt32 |
| 11905 | return 8; |
| 11906 | case 0: |
| 11907 | // op: Pd4 |
| 11908 | return 0; |
| 11909 | } |
| 11910 | break; |
| 11911 | } |
| 11912 | case Hexagon::S2_extractu_rp: |
| 11913 | case Hexagon::S4_extract_rp: { |
| 11914 | switch (OpNum) { |
| 11915 | case 1: |
| 11916 | // op: Rs32 |
| 11917 | return 16; |
| 11918 | case 2: |
| 11919 | // op: Rtt32 |
| 11920 | return 8; |
| 11921 | case 0: |
| 11922 | // op: Rd32 |
| 11923 | return 0; |
| 11924 | } |
| 11925 | break; |
| 11926 | } |
| 11927 | case Hexagon::A4_tfrpcp: { |
| 11928 | switch (OpNum) { |
| 11929 | case 1: |
| 11930 | // op: Rss32 |
| 11931 | return 16; |
| 11932 | case 0: |
| 11933 | // op: Cdd32 |
| 11934 | return 0; |
| 11935 | } |
| 11936 | break; |
| 11937 | } |
| 11938 | case Hexagon::G4_tfrgpcp: { |
| 11939 | switch (OpNum) { |
| 11940 | case 1: |
| 11941 | // op: Rss32 |
| 11942 | return 16; |
| 11943 | case 0: |
| 11944 | // op: Gdd32 |
| 11945 | return 0; |
| 11946 | } |
| 11947 | break; |
| 11948 | } |
| 11949 | case Hexagon::A2_roundsat: |
| 11950 | case Hexagon::A2_sat: |
| 11951 | case Hexagon::F2_conv_d2sf: |
| 11952 | case Hexagon::F2_conv_df2sf: |
| 11953 | case Hexagon::F2_conv_df2uw: |
| 11954 | case Hexagon::F2_conv_df2uw_chop: |
| 11955 | case Hexagon::F2_conv_df2w: |
| 11956 | case Hexagon::F2_conv_df2w_chop: |
| 11957 | case Hexagon::F2_conv_ud2sf: |
| 11958 | case Hexagon::S2_cl0p: |
| 11959 | case Hexagon::S2_cl1p: |
| 11960 | case Hexagon::S2_clbp: |
| 11961 | case Hexagon::S2_ct0p: |
| 11962 | case Hexagon::S2_ct1p: |
| 11963 | case Hexagon::S2_vrndpackwh: |
| 11964 | case Hexagon::S2_vrndpackwhs: |
| 11965 | case Hexagon::S2_vsathb: |
| 11966 | case Hexagon::S2_vsathub: |
| 11967 | case Hexagon::S2_vsatwh: |
| 11968 | case Hexagon::S2_vsatwuh: |
| 11969 | case Hexagon::S2_vtrunehb: |
| 11970 | case Hexagon::S2_vtrunohb: |
| 11971 | case Hexagon::S4_clbpnorm: |
| 11972 | case Hexagon::S5_popcountp: |
| 11973 | case Hexagon::Y2_tlbpp: |
| 11974 | case Hexagon::Y5_tlboc: { |
| 11975 | switch (OpNum) { |
| 11976 | case 1: |
| 11977 | // op: Rss32 |
| 11978 | return 16; |
| 11979 | case 0: |
| 11980 | // op: Rd32 |
| 11981 | return 0; |
| 11982 | } |
| 11983 | break; |
| 11984 | } |
| 11985 | case Hexagon::A2_absp: |
| 11986 | case Hexagon::A2_negp: |
| 11987 | case Hexagon::A2_notp: |
| 11988 | case Hexagon::A2_vabsh: |
| 11989 | case Hexagon::A2_vabshsat: |
| 11990 | case Hexagon::A2_vabsw: |
| 11991 | case Hexagon::A2_vabswsat: |
| 11992 | case Hexagon::A2_vconj: |
| 11993 | case Hexagon::F2_conv_d2df: |
| 11994 | case Hexagon::F2_conv_df2d: |
| 11995 | case Hexagon::F2_conv_df2d_chop: |
| 11996 | case Hexagon::F2_conv_df2ud: |
| 11997 | case Hexagon::F2_conv_df2ud_chop: |
| 11998 | case Hexagon::F2_conv_ud2df: |
| 11999 | case Hexagon::S2_brevp: |
| 12000 | case Hexagon::S2_deinterleave: |
| 12001 | case Hexagon::S2_interleave: |
| 12002 | case Hexagon::S2_vsathb_nopack: |
| 12003 | case Hexagon::S2_vsathub_nopack: |
| 12004 | case Hexagon::S2_vsatwh_nopack: |
| 12005 | case Hexagon::S2_vsatwuh_nopack: { |
| 12006 | switch (OpNum) { |
| 12007 | case 1: |
| 12008 | // op: Rss32 |
| 12009 | return 16; |
| 12010 | case 0: |
| 12011 | // op: Rdd32 |
| 12012 | return 0; |
| 12013 | } |
| 12014 | break; |
| 12015 | } |
| 12016 | case Hexagon::Y4_tfrspcp: { |
| 12017 | switch (OpNum) { |
| 12018 | case 1: |
| 12019 | // op: Rss32 |
| 12020 | return 16; |
| 12021 | case 0: |
| 12022 | // op: Sdd128 |
| 12023 | return 0; |
| 12024 | } |
| 12025 | break; |
| 12026 | } |
| 12027 | case Hexagon::A4_tlbmatch: { |
| 12028 | switch (OpNum) { |
| 12029 | case 1: |
| 12030 | // op: Rss32 |
| 12031 | return 16; |
| 12032 | case 2: |
| 12033 | // op: Rt32 |
| 12034 | return 8; |
| 12035 | case 0: |
| 12036 | // op: Pd4 |
| 12037 | return 0; |
| 12038 | } |
| 12039 | break; |
| 12040 | } |
| 12041 | case Hexagon::M4_cmpyi_wh: |
| 12042 | case Hexagon::M4_cmpyi_whc: |
| 12043 | case Hexagon::M4_cmpyr_wh: |
| 12044 | case Hexagon::M4_cmpyr_whc: |
| 12045 | case Hexagon::S2_asr_r_svw_trun: |
| 12046 | case Hexagon::Y5_ctlbw: { |
| 12047 | switch (OpNum) { |
| 12048 | case 1: |
| 12049 | // op: Rss32 |
| 12050 | return 16; |
| 12051 | case 2: |
| 12052 | // op: Rt32 |
| 12053 | return 8; |
| 12054 | case 0: |
| 12055 | // op: Rd32 |
| 12056 | return 0; |
| 12057 | } |
| 12058 | break; |
| 12059 | } |
| 12060 | case Hexagon::A7_croundd_rr: |
| 12061 | case Hexagon::S2_asl_r_p: |
| 12062 | case Hexagon::S2_asl_r_vh: |
| 12063 | case Hexagon::S2_asl_r_vw: |
| 12064 | case Hexagon::S2_asr_r_p: |
| 12065 | case Hexagon::S2_asr_r_vh: |
| 12066 | case Hexagon::S2_asr_r_vw: |
| 12067 | case Hexagon::S2_lsl_r_p: |
| 12068 | case Hexagon::S2_lsl_r_vh: |
| 12069 | case Hexagon::S2_lsl_r_vw: |
| 12070 | case Hexagon::S2_lsr_r_p: |
| 12071 | case Hexagon::S2_lsr_r_vh: |
| 12072 | case Hexagon::S2_lsr_r_vw: |
| 12073 | case Hexagon::S2_vcnegh: |
| 12074 | case Hexagon::S2_vcrotate: { |
| 12075 | switch (OpNum) { |
| 12076 | case 1: |
| 12077 | // op: Rss32 |
| 12078 | return 16; |
| 12079 | case 2: |
| 12080 | // op: Rt32 |
| 12081 | return 8; |
| 12082 | case 0: |
| 12083 | // op: Rdd32 |
| 12084 | return 0; |
| 12085 | } |
| 12086 | break; |
| 12087 | } |
| 12088 | case Hexagon::A2_vcmpbeq: |
| 12089 | case Hexagon::A2_vcmpbgtu: |
| 12090 | case Hexagon::A2_vcmpheq: |
| 12091 | case Hexagon::A2_vcmphgt: |
| 12092 | case Hexagon::A2_vcmphgtu: |
| 12093 | case Hexagon::A2_vcmpweq: |
| 12094 | case Hexagon::A2_vcmpwgt: |
| 12095 | case Hexagon::A2_vcmpwgtu: |
| 12096 | case Hexagon::A4_boundscheck_hi: |
| 12097 | case Hexagon::A4_boundscheck_lo: |
| 12098 | case Hexagon::A4_vcmpbeq_any: |
| 12099 | case Hexagon::A4_vcmpbgt: |
| 12100 | case Hexagon::A6_vcmpbeq_notany: |
| 12101 | case Hexagon::C2_cmpeqp: |
| 12102 | case Hexagon::C2_cmpgtp: |
| 12103 | case Hexagon::C2_cmpgtup: |
| 12104 | case Hexagon::F2_dfcmpeq: |
| 12105 | case Hexagon::F2_dfcmpge: |
| 12106 | case Hexagon::F2_dfcmpgt: |
| 12107 | case Hexagon::F2_dfcmpuo: { |
| 12108 | switch (OpNum) { |
| 12109 | case 1: |
| 12110 | // op: Rss32 |
| 12111 | return 16; |
| 12112 | case 2: |
| 12113 | // op: Rtt32 |
| 12114 | return 8; |
| 12115 | case 0: |
| 12116 | // op: Pd4 |
| 12117 | return 0; |
| 12118 | } |
| 12119 | break; |
| 12120 | } |
| 12121 | case Hexagon::A5_vaddhubs: |
| 12122 | case Hexagon::M2_vdmpyrs_s0: |
| 12123 | case Hexagon::M2_vdmpyrs_s1: |
| 12124 | case Hexagon::M2_vraddh: |
| 12125 | case Hexagon::M2_vradduh: |
| 12126 | case Hexagon::M2_vrcmpys_s1rp_h: |
| 12127 | case Hexagon::M2_vrcmpys_s1rp_l: |
| 12128 | case Hexagon::M7_wcmpyiw: |
| 12129 | case Hexagon::M7_wcmpyiw_rnd: |
| 12130 | case Hexagon::M7_wcmpyiwc: |
| 12131 | case Hexagon::M7_wcmpyiwc_rnd: |
| 12132 | case Hexagon::M7_wcmpyrw: |
| 12133 | case Hexagon::M7_wcmpyrw_rnd: |
| 12134 | case Hexagon::M7_wcmpyrwc: |
| 12135 | case Hexagon::M7_wcmpyrwc_rnd: |
| 12136 | case Hexagon::S2_parityp: { |
| 12137 | switch (OpNum) { |
| 12138 | case 1: |
| 12139 | // op: Rss32 |
| 12140 | return 16; |
| 12141 | case 2: |
| 12142 | // op: Rtt32 |
| 12143 | return 8; |
| 12144 | case 0: |
| 12145 | // op: Rd32 |
| 12146 | return 0; |
| 12147 | } |
| 12148 | break; |
| 12149 | } |
| 12150 | case Hexagon::A2_addp: |
| 12151 | case Hexagon::A2_addpsat: |
| 12152 | case Hexagon::A2_addsph: |
| 12153 | case Hexagon::A2_addspl: |
| 12154 | case Hexagon::A2_andp: |
| 12155 | case Hexagon::A2_maxp: |
| 12156 | case Hexagon::A2_maxup: |
| 12157 | case Hexagon::A2_orp: |
| 12158 | case Hexagon::A2_vaddh: |
| 12159 | case Hexagon::A2_vaddhs: |
| 12160 | case Hexagon::A2_vaddub: |
| 12161 | case Hexagon::A2_vaddubs: |
| 12162 | case Hexagon::A2_vadduhs: |
| 12163 | case Hexagon::A2_vaddw: |
| 12164 | case Hexagon::A2_vaddws: |
| 12165 | case Hexagon::A2_vavgh: |
| 12166 | case Hexagon::A2_vavghcr: |
| 12167 | case Hexagon::A2_vavghr: |
| 12168 | case Hexagon::A2_vavgub: |
| 12169 | case Hexagon::A2_vavgubr: |
| 12170 | case Hexagon::A2_vavguh: |
| 12171 | case Hexagon::A2_vavguhr: |
| 12172 | case Hexagon::A2_vavguw: |
| 12173 | case Hexagon::A2_vavguwr: |
| 12174 | case Hexagon::A2_vavgw: |
| 12175 | case Hexagon::A2_vavgwcr: |
| 12176 | case Hexagon::A2_vavgwr: |
| 12177 | case Hexagon::A2_vraddub: |
| 12178 | case Hexagon::A2_vrsadub: |
| 12179 | case Hexagon::A2_xorp: |
| 12180 | case Hexagon::F2_dfadd: |
| 12181 | case Hexagon::F2_dfmax: |
| 12182 | case Hexagon::F2_dfmin: |
| 12183 | case Hexagon::F2_dfmpyfix: |
| 12184 | case Hexagon::F2_dfmpyll: |
| 12185 | case Hexagon::F2_dfsub: |
| 12186 | case Hexagon::M2_mmpyh_rs0: |
| 12187 | case Hexagon::M2_mmpyh_rs1: |
| 12188 | case Hexagon::M2_mmpyh_s0: |
| 12189 | case Hexagon::M2_mmpyh_s1: |
| 12190 | case Hexagon::M2_mmpyl_rs0: |
| 12191 | case Hexagon::M2_mmpyl_rs1: |
| 12192 | case Hexagon::M2_mmpyl_s0: |
| 12193 | case Hexagon::M2_mmpyl_s1: |
| 12194 | case Hexagon::M2_mmpyuh_rs0: |
| 12195 | case Hexagon::M2_mmpyuh_rs1: |
| 12196 | case Hexagon::M2_mmpyuh_s0: |
| 12197 | case Hexagon::M2_mmpyuh_s1: |
| 12198 | case Hexagon::M2_mmpyul_rs0: |
| 12199 | case Hexagon::M2_mmpyul_rs1: |
| 12200 | case Hexagon::M2_mmpyul_s0: |
| 12201 | case Hexagon::M2_mmpyul_s1: |
| 12202 | case Hexagon::M2_vcmpy_s0_sat_i: |
| 12203 | case Hexagon::M2_vcmpy_s0_sat_r: |
| 12204 | case Hexagon::M2_vcmpy_s1_sat_i: |
| 12205 | case Hexagon::M2_vcmpy_s1_sat_r: |
| 12206 | case Hexagon::M2_vdmpys_s0: |
| 12207 | case Hexagon::M2_vdmpys_s1: |
| 12208 | case Hexagon::M2_vmpy2es_s0: |
| 12209 | case Hexagon::M2_vmpy2es_s1: |
| 12210 | case Hexagon::M2_vrcmpyi_s0: |
| 12211 | case Hexagon::M2_vrcmpyi_s0c: |
| 12212 | case Hexagon::M2_vrcmpyr_s0: |
| 12213 | case Hexagon::M2_vrcmpyr_s0c: |
| 12214 | case Hexagon::M2_vrcmpys_s1_h: |
| 12215 | case Hexagon::M2_vrcmpys_s1_l: |
| 12216 | case Hexagon::M2_vrmpy_s0: |
| 12217 | case Hexagon::M4_vrmpyeh_s0: |
| 12218 | case Hexagon::M4_vrmpyeh_s1: |
| 12219 | case Hexagon::M4_vrmpyoh_s0: |
| 12220 | case Hexagon::M4_vrmpyoh_s1: |
| 12221 | case Hexagon::M5_vdmpybsu: |
| 12222 | case Hexagon::M5_vrmpybsu: |
| 12223 | case Hexagon::M5_vrmpybuu: |
| 12224 | case Hexagon::M7_dcmpyiw: |
| 12225 | case Hexagon::M7_dcmpyiwc: |
| 12226 | case Hexagon::M7_dcmpyrw: |
| 12227 | case Hexagon::M7_dcmpyrwc: |
| 12228 | case Hexagon::S2_cabacdecbin: |
| 12229 | case Hexagon::S2_extractup_rp: |
| 12230 | case Hexagon::S2_lfsp: |
| 12231 | case Hexagon::S2_shuffeb: |
| 12232 | case Hexagon::S2_shuffeh: |
| 12233 | case Hexagon::S2_vtrunewh: |
| 12234 | case Hexagon::S2_vtrunowh: |
| 12235 | case Hexagon::S4_extractp_rp: |
| 12236 | case Hexagon::S4_vxaddsubh: |
| 12237 | case Hexagon::S4_vxaddsubhr: |
| 12238 | case Hexagon::S4_vxaddsubw: |
| 12239 | case Hexagon::S4_vxsubaddh: |
| 12240 | case Hexagon::S4_vxsubaddhr: |
| 12241 | case Hexagon::S4_vxsubaddw: |
| 12242 | case Hexagon::S6_vtrunehb_ppp: |
| 12243 | case Hexagon::S6_vtrunohb_ppp: { |
| 12244 | switch (OpNum) { |
| 12245 | case 1: |
| 12246 | // op: Rss32 |
| 12247 | return 16; |
| 12248 | case 2: |
| 12249 | // op: Rtt32 |
| 12250 | return 8; |
| 12251 | case 0: |
| 12252 | // op: Rdd32 |
| 12253 | return 0; |
| 12254 | } |
| 12255 | break; |
| 12256 | } |
| 12257 | case Hexagon::S2_vsplicerb: { |
| 12258 | switch (OpNum) { |
| 12259 | case 1: |
| 12260 | // op: Rss32 |
| 12261 | return 16; |
| 12262 | case 2: |
| 12263 | // op: Rtt32 |
| 12264 | return 8; |
| 12265 | case 3: |
| 12266 | // op: Pu4 |
| 12267 | return 5; |
| 12268 | case 0: |
| 12269 | // op: Rdd32 |
| 12270 | return 0; |
| 12271 | } |
| 12272 | break; |
| 12273 | } |
| 12274 | case Hexagon::V6_pred_scalar2: |
| 12275 | case Hexagon::V6_pred_scalar2v2: { |
| 12276 | switch (OpNum) { |
| 12277 | case 1: |
| 12278 | // op: Rt32 |
| 12279 | return 16; |
| 12280 | case 0: |
| 12281 | // op: Qd4 |
| 12282 | return 0; |
| 12283 | } |
| 12284 | break; |
| 12285 | } |
| 12286 | case Hexagon::V6_lvsplatb: |
| 12287 | case Hexagon::V6_lvsplath: |
| 12288 | case Hexagon::V6_lvsplatw: |
| 12289 | case Hexagon::V6_zextract: { |
| 12290 | switch (OpNum) { |
| 12291 | case 1: |
| 12292 | // op: Rt32 |
| 12293 | return 16; |
| 12294 | case 0: |
| 12295 | // op: Vd32 |
| 12296 | return 0; |
| 12297 | } |
| 12298 | break; |
| 12299 | } |
| 12300 | case Hexagon::A2_addh_h16_hh: |
| 12301 | case Hexagon::A2_addh_h16_hl: |
| 12302 | case Hexagon::A2_addh_h16_lh: |
| 12303 | case Hexagon::A2_addh_h16_ll: |
| 12304 | case Hexagon::A2_addh_h16_sat_hh: |
| 12305 | case Hexagon::A2_addh_h16_sat_hl: |
| 12306 | case Hexagon::A2_addh_h16_sat_lh: |
| 12307 | case Hexagon::A2_addh_h16_sat_ll: |
| 12308 | case Hexagon::A2_addh_l16_hl: |
| 12309 | case Hexagon::A2_addh_l16_ll: |
| 12310 | case Hexagon::A2_addh_l16_sat_hl: |
| 12311 | case Hexagon::A2_addh_l16_sat_ll: |
| 12312 | case Hexagon::A2_combine_hh: |
| 12313 | case Hexagon::A2_combine_hl: |
| 12314 | case Hexagon::A2_combine_lh: |
| 12315 | case Hexagon::A2_combine_ll: |
| 12316 | case Hexagon::A2_min: |
| 12317 | case Hexagon::A2_minu: |
| 12318 | case Hexagon::A2_sub: |
| 12319 | case Hexagon::A2_subh_h16_hh: |
| 12320 | case Hexagon::A2_subh_h16_hl: |
| 12321 | case Hexagon::A2_subh_h16_lh: |
| 12322 | case Hexagon::A2_subh_h16_ll: |
| 12323 | case Hexagon::A2_subh_h16_sat_hh: |
| 12324 | case Hexagon::A2_subh_h16_sat_hl: |
| 12325 | case Hexagon::A2_subh_h16_sat_lh: |
| 12326 | case Hexagon::A2_subh_h16_sat_ll: |
| 12327 | case Hexagon::A2_subh_l16_hl: |
| 12328 | case Hexagon::A2_subh_l16_ll: |
| 12329 | case Hexagon::A2_subh_l16_sat_hl: |
| 12330 | case Hexagon::A2_subh_l16_sat_ll: |
| 12331 | case Hexagon::A2_subsat: |
| 12332 | case Hexagon::A2_svnavgh: |
| 12333 | case Hexagon::A2_svsubh: |
| 12334 | case Hexagon::A2_svsubhs: |
| 12335 | case Hexagon::A2_svsubuhs: |
| 12336 | case Hexagon::A4_andn: |
| 12337 | case Hexagon::A4_orn: |
| 12338 | case Hexagon::dep_A2_subsat: { |
| 12339 | switch (OpNum) { |
| 12340 | case 1: |
| 12341 | // op: Rt32 |
| 12342 | return 8; |
| 12343 | case 2: |
| 12344 | // op: Rs32 |
| 12345 | return 16; |
| 12346 | case 0: |
| 12347 | // op: Rd32 |
| 12348 | return 0; |
| 12349 | } |
| 12350 | break; |
| 12351 | } |
| 12352 | case Hexagon::A2_minp: |
| 12353 | case Hexagon::A2_minup: |
| 12354 | case Hexagon::A2_subp: |
| 12355 | case Hexagon::A2_vmaxb: |
| 12356 | case Hexagon::A2_vmaxh: |
| 12357 | case Hexagon::A2_vmaxub: |
| 12358 | case Hexagon::A2_vmaxuh: |
| 12359 | case Hexagon::A2_vmaxuw: |
| 12360 | case Hexagon::A2_vmaxw: |
| 12361 | case Hexagon::A2_vminb: |
| 12362 | case Hexagon::A2_vminh: |
| 12363 | case Hexagon::A2_vminub: |
| 12364 | case Hexagon::A2_vminuh: |
| 12365 | case Hexagon::A2_vminuw: |
| 12366 | case Hexagon::A2_vminw: |
| 12367 | case Hexagon::A2_vnavgh: |
| 12368 | case Hexagon::A2_vnavghcr: |
| 12369 | case Hexagon::A2_vnavghr: |
| 12370 | case Hexagon::A2_vnavgw: |
| 12371 | case Hexagon::A2_vnavgwcr: |
| 12372 | case Hexagon::A2_vnavgwr: |
| 12373 | case Hexagon::A2_vsubh: |
| 12374 | case Hexagon::A2_vsubhs: |
| 12375 | case Hexagon::A2_vsubub: |
| 12376 | case Hexagon::A2_vsububs: |
| 12377 | case Hexagon::A2_vsubuhs: |
| 12378 | case Hexagon::A2_vsubw: |
| 12379 | case Hexagon::A2_vsubws: |
| 12380 | case Hexagon::A4_andnp: |
| 12381 | case Hexagon::A4_ornp: |
| 12382 | case Hexagon::M2_vabsdiffh: |
| 12383 | case Hexagon::M2_vabsdiffw: |
| 12384 | case Hexagon::M6_vabsdiffb: |
| 12385 | case Hexagon::M6_vabsdiffub: |
| 12386 | case Hexagon::S2_shuffob: |
| 12387 | case Hexagon::S2_shuffoh: { |
| 12388 | switch (OpNum) { |
| 12389 | case 1: |
| 12390 | // op: Rtt32 |
| 12391 | return 8; |
| 12392 | case 2: |
| 12393 | // op: Rss32 |
| 12394 | return 16; |
| 12395 | case 0: |
| 12396 | // op: Rdd32 |
| 12397 | return 0; |
| 12398 | } |
| 12399 | break; |
| 12400 | } |
| 12401 | case Hexagon::S2_valignrb: { |
| 12402 | switch (OpNum) { |
| 12403 | case 1: |
| 12404 | // op: Rtt32 |
| 12405 | return 8; |
| 12406 | case 2: |
| 12407 | // op: Rss32 |
| 12408 | return 16; |
| 12409 | case 3: |
| 12410 | // op: Pu4 |
| 12411 | return 5; |
| 12412 | case 0: |
| 12413 | // op: Rdd32 |
| 12414 | return 0; |
| 12415 | } |
| 12416 | break; |
| 12417 | } |
| 12418 | case Hexagon::M4_mpyrr_addr: { |
| 12419 | switch (OpNum) { |
| 12420 | case 1: |
| 12421 | // op: Ru32 |
| 12422 | return 0; |
| 12423 | case 3: |
| 12424 | // op: Rs32 |
| 12425 | return 16; |
| 12426 | case 0: |
| 12427 | // op: Ry32 |
| 12428 | return 8; |
| 12429 | } |
| 12430 | break; |
| 12431 | } |
| 12432 | case Hexagon::Y2_tfrscrr: { |
| 12433 | switch (OpNum) { |
| 12434 | case 1: |
| 12435 | // op: Ss128 |
| 12436 | return 16; |
| 12437 | case 0: |
| 12438 | // op: Rd32 |
| 12439 | return 0; |
| 12440 | } |
| 12441 | break; |
| 12442 | } |
| 12443 | case Hexagon::Y4_tfrscpp: { |
| 12444 | switch (OpNum) { |
| 12445 | case 1: |
| 12446 | // op: Sss128 |
| 12447 | return 16; |
| 12448 | case 0: |
| 12449 | // op: Rdd32 |
| 12450 | return 0; |
| 12451 | } |
| 12452 | break; |
| 12453 | } |
| 12454 | case Hexagon::V6_vabs_f8: |
| 12455 | case Hexagon::V6_vabs_hf: |
| 12456 | case Hexagon::V6_vabs_qf16_hf: |
| 12457 | case Hexagon::V6_vabs_qf16_qf16: |
| 12458 | case Hexagon::V6_vabs_qf32_qf32: |
| 12459 | case Hexagon::V6_vabs_qf32_sf: |
| 12460 | case Hexagon::V6_vabs_sf: |
| 12461 | case Hexagon::V6_vabsb: |
| 12462 | case Hexagon::V6_vabsb_sat: |
| 12463 | case Hexagon::V6_vabsh: |
| 12464 | case Hexagon::V6_vabsh_sat: |
| 12465 | case Hexagon::V6_vabsw: |
| 12466 | case Hexagon::V6_vabsw_sat: |
| 12467 | case Hexagon::V6_vassign: |
| 12468 | case Hexagon::V6_vassign_fp: |
| 12469 | case Hexagon::V6_vassign_tmp: |
| 12470 | case Hexagon::V6_vcl0h: |
| 12471 | case Hexagon::V6_vcl0w: |
| 12472 | case Hexagon::V6_vconv_f8_qf16: |
| 12473 | case Hexagon::V6_vconv_h_hf: |
| 12474 | case Hexagon::V6_vconv_h_hf_rnd: |
| 12475 | case Hexagon::V6_vconv_hf_h: |
| 12476 | case Hexagon::V6_vconv_hf_qf16: |
| 12477 | case Hexagon::V6_vconv_qf16_hf: |
| 12478 | case Hexagon::V6_vconv_qf16_qf16: |
| 12479 | case Hexagon::V6_vconv_qf32_qf32: |
| 12480 | case Hexagon::V6_vconv_qf32_sf: |
| 12481 | case Hexagon::V6_vconv_sf_qf32: |
| 12482 | case Hexagon::V6_vconv_sf_w: |
| 12483 | case Hexagon::V6_vconv_w_sf: |
| 12484 | case Hexagon::V6_vcvt_h_hf: |
| 12485 | case Hexagon::V6_vcvt_hf_h: |
| 12486 | case Hexagon::V6_vcvt_hf_uh: |
| 12487 | case Hexagon::V6_vcvt_uh_hf: |
| 12488 | case Hexagon::V6_vdealb: |
| 12489 | case Hexagon::V6_vdealh: |
| 12490 | case Hexagon::V6_vfneg_f8: |
| 12491 | case Hexagon::V6_vfneg_hf: |
| 12492 | case Hexagon::V6_vfneg_sf: |
| 12493 | case Hexagon::V6_vilog2_hf: |
| 12494 | case Hexagon::V6_vilog2_qf16: |
| 12495 | case Hexagon::V6_vilog2_qf32: |
| 12496 | case Hexagon::V6_vilog2_sf: |
| 12497 | case Hexagon::V6_vneg_qf16_hf: |
| 12498 | case Hexagon::V6_vneg_qf16_qf16: |
| 12499 | case Hexagon::V6_vneg_qf32_qf32: |
| 12500 | case Hexagon::V6_vneg_qf32_sf: |
| 12501 | case Hexagon::V6_vnormamth: |
| 12502 | case Hexagon::V6_vnormamtw: |
| 12503 | case Hexagon::V6_vnot: |
| 12504 | case Hexagon::V6_vpopcounth: |
| 12505 | case Hexagon::V6_vshuffb: |
| 12506 | case Hexagon::V6_vshuffh: { |
| 12507 | switch (OpNum) { |
| 12508 | case 1: |
| 12509 | // op: Vu32 |
| 12510 | return 8; |
| 12511 | case 0: |
| 12512 | // op: Vd32 |
| 12513 | return 0; |
| 12514 | } |
| 12515 | break; |
| 12516 | } |
| 12517 | case Hexagon::V6_vconv_qf16_f8: |
| 12518 | case Hexagon::V6_vcvt2_hf_b: |
| 12519 | case Hexagon::V6_vcvt2_hf_ub: |
| 12520 | case Hexagon::V6_vcvt_hf_b: |
| 12521 | case Hexagon::V6_vcvt_hf_f8: |
| 12522 | case Hexagon::V6_vcvt_hf_ub: |
| 12523 | case Hexagon::V6_vcvt_sf_hf: |
| 12524 | case Hexagon::V6_vsb: |
| 12525 | case Hexagon::V6_vsh: |
| 12526 | case Hexagon::V6_vunpackb: |
| 12527 | case Hexagon::V6_vunpackh: |
| 12528 | case Hexagon::V6_vunpackub: |
| 12529 | case Hexagon::V6_vunpackuh: |
| 12530 | case Hexagon::V6_vzb: |
| 12531 | case Hexagon::V6_vzh: { |
| 12532 | switch (OpNum) { |
| 12533 | case 1: |
| 12534 | // op: Vu32 |
| 12535 | return 8; |
| 12536 | case 0: |
| 12537 | // op: Vdd32 |
| 12538 | return 0; |
| 12539 | } |
| 12540 | break; |
| 12541 | } |
| 12542 | case Hexagon::V6_extractw: { |
| 12543 | switch (OpNum) { |
| 12544 | case 1: |
| 12545 | // op: Vu32 |
| 12546 | return 8; |
| 12547 | case 2: |
| 12548 | // op: Rs32 |
| 12549 | return 16; |
| 12550 | case 0: |
| 12551 | // op: Rd32 |
| 12552 | return 0; |
| 12553 | } |
| 12554 | break; |
| 12555 | } |
| 12556 | case Hexagon::V6_vandvrt: { |
| 12557 | switch (OpNum) { |
| 12558 | case 1: |
| 12559 | // op: Vu32 |
| 12560 | return 8; |
| 12561 | case 2: |
| 12562 | // op: Rt32 |
| 12563 | return 16; |
| 12564 | case 0: |
| 12565 | // op: Qd4 |
| 12566 | return 0; |
| 12567 | } |
| 12568 | break; |
| 12569 | } |
| 12570 | case Hexagon::V6_get_qfext: |
| 12571 | case Hexagon::V6_set_qfext: |
| 12572 | case Hexagon::V6_vaslh: |
| 12573 | case Hexagon::V6_vaslw: |
| 12574 | case Hexagon::V6_vasrh: |
| 12575 | case Hexagon::V6_vasrw: |
| 12576 | case Hexagon::V6_vdmpybus: |
| 12577 | case Hexagon::V6_vdmpyhb: |
| 12578 | case Hexagon::V6_vdmpyhsat: |
| 12579 | case Hexagon::V6_vdmpyhsusat: |
| 12580 | case Hexagon::V6_vlsrb: |
| 12581 | case Hexagon::V6_vlsrh: |
| 12582 | case Hexagon::V6_vlsrw: |
| 12583 | case Hexagon::V6_vmpy_rt_hf: |
| 12584 | case Hexagon::V6_vmpy_rt_qf16: |
| 12585 | case Hexagon::V6_vmpy_rt_sf: |
| 12586 | case Hexagon::V6_vmpyhsrs: |
| 12587 | case Hexagon::V6_vmpyhss: |
| 12588 | case Hexagon::V6_vmpyihb: |
| 12589 | case Hexagon::V6_vmpyiwb: |
| 12590 | case Hexagon::V6_vmpyiwh: |
| 12591 | case Hexagon::V6_vmpyiwub: |
| 12592 | case Hexagon::V6_vmpyuhe: |
| 12593 | case Hexagon::V6_vrmpybus: |
| 12594 | case Hexagon::V6_vrmpyub: |
| 12595 | case Hexagon::V6_vror: { |
| 12596 | switch (OpNum) { |
| 12597 | case 1: |
| 12598 | // op: Vu32 |
| 12599 | return 8; |
| 12600 | case 2: |
| 12601 | // op: Rt32 |
| 12602 | return 16; |
| 12603 | case 0: |
| 12604 | // op: Vd32 |
| 12605 | return 0; |
| 12606 | } |
| 12607 | break; |
| 12608 | } |
| 12609 | case Hexagon::V6_vmpybus: |
| 12610 | case Hexagon::V6_vmpyh: |
| 12611 | case Hexagon::V6_vmpyub: |
| 12612 | case Hexagon::V6_vmpyuh: { |
| 12613 | switch (OpNum) { |
| 12614 | case 1: |
| 12615 | // op: Vu32 |
| 12616 | return 8; |
| 12617 | case 2: |
| 12618 | // op: Rt32 |
| 12619 | return 16; |
| 12620 | case 0: |
| 12621 | // op: Vdd32 |
| 12622 | return 0; |
| 12623 | } |
| 12624 | break; |
| 12625 | } |
| 12626 | case Hexagon::V6_vrmpyzbb_rt: |
| 12627 | case Hexagon::V6_vrmpyzbub_rt: |
| 12628 | case Hexagon::V6_vrmpyzcb_rt: |
| 12629 | case Hexagon::V6_vrmpyzcbs_rt: |
| 12630 | case Hexagon::V6_vrmpyznb_rt: { |
| 12631 | switch (OpNum) { |
| 12632 | case 1: |
| 12633 | // op: Vu32 |
| 12634 | return 8; |
| 12635 | case 2: |
| 12636 | // op: Rt8 |
| 12637 | return 16; |
| 12638 | case 0: |
| 12639 | // op: Vdddd32 |
| 12640 | return 0; |
| 12641 | } |
| 12642 | break; |
| 12643 | } |
| 12644 | case Hexagon::V6_vlut4: { |
| 12645 | switch (OpNum) { |
| 12646 | case 1: |
| 12647 | // op: Vu32 |
| 12648 | return 8; |
| 12649 | case 2: |
| 12650 | // op: Rtt32 |
| 12651 | return 16; |
| 12652 | case 0: |
| 12653 | // op: Vd32 |
| 12654 | return 0; |
| 12655 | } |
| 12656 | break; |
| 12657 | } |
| 12658 | case Hexagon::V6_vrmpybub_rtt: |
| 12659 | case Hexagon::V6_vrmpyub_rtt: { |
| 12660 | switch (OpNum) { |
| 12661 | case 1: |
| 12662 | // op: Vu32 |
| 12663 | return 8; |
| 12664 | case 2: |
| 12665 | // op: Rtt32 |
| 12666 | return 16; |
| 12667 | case 0: |
| 12668 | // op: Vdd32 |
| 12669 | return 0; |
| 12670 | } |
| 12671 | break; |
| 12672 | } |
| 12673 | case Hexagon::V6_veqb: |
| 12674 | case Hexagon::V6_veqh: |
| 12675 | case Hexagon::V6_veqhf: |
| 12676 | case Hexagon::V6_veqsf: |
| 12677 | case Hexagon::V6_veqw: |
| 12678 | case Hexagon::V6_vgtb: |
| 12679 | case Hexagon::V6_vgtbf: |
| 12680 | case Hexagon::V6_vgth: |
| 12681 | case Hexagon::V6_vgthf: |
| 12682 | case Hexagon::V6_vgtsf: |
| 12683 | case Hexagon::V6_vgtub: |
| 12684 | case Hexagon::V6_vgtuh: |
| 12685 | case Hexagon::V6_vgtuw: |
| 12686 | case Hexagon::V6_vgtw: { |
| 12687 | switch (OpNum) { |
| 12688 | case 1: |
| 12689 | // op: Vu32 |
| 12690 | return 8; |
| 12691 | case 2: |
| 12692 | // op: Vv32 |
| 12693 | return 16; |
| 12694 | case 0: |
| 12695 | // op: Qd4 |
| 12696 | return 0; |
| 12697 | } |
| 12698 | break; |
| 12699 | } |
| 12700 | case Hexagon::V6_vabsdiffh: |
| 12701 | case Hexagon::V6_vabsdiffub: |
| 12702 | case Hexagon::V6_vabsdiffuh: |
| 12703 | case Hexagon::V6_vabsdiffw: |
| 12704 | case Hexagon::V6_vadd_hf: |
| 12705 | case Hexagon::V6_vadd_hf_hf: |
| 12706 | case Hexagon::V6_vadd_qf16: |
| 12707 | case Hexagon::V6_vadd_qf16_mix: |
| 12708 | case Hexagon::V6_vadd_qf32: |
| 12709 | case Hexagon::V6_vadd_qf32_mix: |
| 12710 | case Hexagon::V6_vadd_sf: |
| 12711 | case Hexagon::V6_vadd_sf_sf: |
| 12712 | case Hexagon::V6_vaddb: |
| 12713 | case Hexagon::V6_vaddbsat: |
| 12714 | case Hexagon::V6_vaddclbh: |
| 12715 | case Hexagon::V6_vaddclbw: |
| 12716 | case Hexagon::V6_vaddh: |
| 12717 | case Hexagon::V6_vaddhsat: |
| 12718 | case Hexagon::V6_vaddubsat: |
| 12719 | case Hexagon::V6_vaddububb_sat: |
| 12720 | case Hexagon::V6_vadduhsat: |
| 12721 | case Hexagon::V6_vadduwsat: |
| 12722 | case Hexagon::V6_vaddw: |
| 12723 | case Hexagon::V6_vaddwsat: |
| 12724 | case Hexagon::V6_vand: |
| 12725 | case Hexagon::V6_vaslhv: |
| 12726 | case Hexagon::V6_vaslwv: |
| 12727 | case Hexagon::V6_vasrhv: |
| 12728 | case Hexagon::V6_vasrwv: |
| 12729 | case Hexagon::V6_vavgb: |
| 12730 | case Hexagon::V6_vavgbrnd: |
| 12731 | case Hexagon::V6_vavgh: |
| 12732 | case Hexagon::V6_vavghrnd: |
| 12733 | case Hexagon::V6_vavgub: |
| 12734 | case Hexagon::V6_vavgubrnd: |
| 12735 | case Hexagon::V6_vavguh: |
| 12736 | case Hexagon::V6_vavguhrnd: |
| 12737 | case Hexagon::V6_vavguw: |
| 12738 | case Hexagon::V6_vavguwrnd: |
| 12739 | case Hexagon::V6_vavgw: |
| 12740 | case Hexagon::V6_vavgwrnd: |
| 12741 | case Hexagon::V6_vcvt2_b_hf: |
| 12742 | case Hexagon::V6_vcvt2_ub_hf: |
| 12743 | case Hexagon::V6_vcvt_b_hf: |
| 12744 | case Hexagon::V6_vcvt_bf_sf: |
| 12745 | case Hexagon::V6_vcvt_f8_hf: |
| 12746 | case Hexagon::V6_vcvt_hf_sf: |
| 12747 | case Hexagon::V6_vcvt_ub_hf: |
| 12748 | case Hexagon::V6_vdealb4w: |
| 12749 | case Hexagon::V6_vdelta: |
| 12750 | case Hexagon::V6_vdmpy_sf_hf: |
| 12751 | case Hexagon::V6_vdmpyhvsat: |
| 12752 | case Hexagon::V6_vfmax_f8: |
| 12753 | case Hexagon::V6_vfmax_hf: |
| 12754 | case Hexagon::V6_vfmax_sf: |
| 12755 | case Hexagon::V6_vfmin_f8: |
| 12756 | case Hexagon::V6_vfmin_hf: |
| 12757 | case Hexagon::V6_vfmin_sf: |
| 12758 | case Hexagon::V6_vlsrhv: |
| 12759 | case Hexagon::V6_vlsrwv: |
| 12760 | case Hexagon::V6_vmax_bf: |
| 12761 | case Hexagon::V6_vmax_hf: |
| 12762 | case Hexagon::V6_vmax_sf: |
| 12763 | case Hexagon::V6_vmaxb: |
| 12764 | case Hexagon::V6_vmaxh: |
| 12765 | case Hexagon::V6_vmaxub: |
| 12766 | case Hexagon::V6_vmaxuh: |
| 12767 | case Hexagon::V6_vmaxw: |
| 12768 | case Hexagon::V6_vmerge_qf: |
| 12769 | case Hexagon::V6_vmin_bf: |
| 12770 | case Hexagon::V6_vmin_hf: |
| 12771 | case Hexagon::V6_vmin_sf: |
| 12772 | case Hexagon::V6_vminb: |
| 12773 | case Hexagon::V6_vminh: |
| 12774 | case Hexagon::V6_vminub: |
| 12775 | case Hexagon::V6_vminuh: |
| 12776 | case Hexagon::V6_vminw: |
| 12777 | case Hexagon::V6_vmpy_hf_hf: |
| 12778 | case Hexagon::V6_vmpy_qf16: |
| 12779 | case Hexagon::V6_vmpy_qf16_hf: |
| 12780 | case Hexagon::V6_vmpy_qf16_mix_hf: |
| 12781 | case Hexagon::V6_vmpy_qf32: |
| 12782 | case Hexagon::V6_vmpy_qf32_sf: |
| 12783 | case Hexagon::V6_vmpy_sf_sf: |
| 12784 | case Hexagon::V6_vmpyewuh: |
| 12785 | case Hexagon::V6_vmpyhvsrs: |
| 12786 | case Hexagon::V6_vmpyieoh: |
| 12787 | case Hexagon::V6_vmpyiewuh: |
| 12788 | case Hexagon::V6_vmpyih: |
| 12789 | case Hexagon::V6_vmpyiowh: |
| 12790 | case Hexagon::V6_vmpyowh: |
| 12791 | case Hexagon::V6_vmpyowh_rnd: |
| 12792 | case Hexagon::V6_vmpyuhvs: |
| 12793 | case Hexagon::V6_vnavgb: |
| 12794 | case Hexagon::V6_vnavgh: |
| 12795 | case Hexagon::V6_vnavgub: |
| 12796 | case Hexagon::V6_vnavgw: |
| 12797 | case Hexagon::V6_vor: |
| 12798 | case Hexagon::V6_vpackeb: |
| 12799 | case Hexagon::V6_vpackeh: |
| 12800 | case Hexagon::V6_vpackhb_sat: |
| 12801 | case Hexagon::V6_vpackhub_sat: |
| 12802 | case Hexagon::V6_vpackob: |
| 12803 | case Hexagon::V6_vpackoh: |
| 12804 | case Hexagon::V6_vpackwh_sat: |
| 12805 | case Hexagon::V6_vpackwuh_sat: |
| 12806 | case Hexagon::V6_vrdelta: |
| 12807 | case Hexagon::V6_vrmpybusv: |
| 12808 | case Hexagon::V6_vrmpybv: |
| 12809 | case Hexagon::V6_vrmpyubv: |
| 12810 | case Hexagon::V6_vrotr: |
| 12811 | case Hexagon::V6_vroundhb: |
| 12812 | case Hexagon::V6_vroundhub: |
| 12813 | case Hexagon::V6_vrounduhub: |
| 12814 | case Hexagon::V6_vrounduwuh: |
| 12815 | case Hexagon::V6_vroundwh: |
| 12816 | case Hexagon::V6_vroundwuh: |
| 12817 | case Hexagon::V6_vsatdw: |
| 12818 | case Hexagon::V6_vsathub: |
| 12819 | case Hexagon::V6_vsatuwuh: |
| 12820 | case Hexagon::V6_vsatwh: |
| 12821 | case Hexagon::V6_vshufeh: |
| 12822 | case Hexagon::V6_vshuffeb: |
| 12823 | case Hexagon::V6_vshuffob: |
| 12824 | case Hexagon::V6_vshufoh: |
| 12825 | case Hexagon::V6_vsub_hf: |
| 12826 | case Hexagon::V6_vsub_hf_hf: |
| 12827 | case Hexagon::V6_vsub_hf_mix: |
| 12828 | case Hexagon::V6_vsub_qf16: |
| 12829 | case Hexagon::V6_vsub_qf16_mix: |
| 12830 | case Hexagon::V6_vsub_qf32: |
| 12831 | case Hexagon::V6_vsub_qf32_mix: |
| 12832 | case Hexagon::V6_vsub_sf: |
| 12833 | case Hexagon::V6_vsub_sf_mix: |
| 12834 | case Hexagon::V6_vsub_sf_sf: |
| 12835 | case Hexagon::V6_vsubb: |
| 12836 | case Hexagon::V6_vsubbsat: |
| 12837 | case Hexagon::V6_vsubh: |
| 12838 | case Hexagon::V6_vsubhsat: |
| 12839 | case Hexagon::V6_vsububsat: |
| 12840 | case Hexagon::V6_vsubububb_sat: |
| 12841 | case Hexagon::V6_vsubuhsat: |
| 12842 | case Hexagon::V6_vsubuwsat: |
| 12843 | case Hexagon::V6_vsubw: |
| 12844 | case Hexagon::V6_vsubwsat: |
| 12845 | case Hexagon::V6_vxor: { |
| 12846 | switch (OpNum) { |
| 12847 | case 1: |
| 12848 | // op: Vu32 |
| 12849 | return 8; |
| 12850 | case 2: |
| 12851 | // op: Vv32 |
| 12852 | return 16; |
| 12853 | case 0: |
| 12854 | // op: Vd32 |
| 12855 | return 0; |
| 12856 | } |
| 12857 | break; |
| 12858 | } |
| 12859 | case Hexagon::V6_vadd_hf_f8: |
| 12860 | case Hexagon::V6_vadd_sf_bf: |
| 12861 | case Hexagon::V6_vadd_sf_hf: |
| 12862 | case Hexagon::V6_vaddhw: |
| 12863 | case Hexagon::V6_vaddubh: |
| 12864 | case Hexagon::V6_vadduhw: |
| 12865 | case Hexagon::V6_vcombine: |
| 12866 | case Hexagon::V6_vcombine_tmp: |
| 12867 | case Hexagon::V6_vmpy_hf_f8: |
| 12868 | case Hexagon::V6_vmpy_qf32_hf: |
| 12869 | case Hexagon::V6_vmpy_qf32_mix_hf: |
| 12870 | case Hexagon::V6_vmpy_qf32_qf16: |
| 12871 | case Hexagon::V6_vmpy_sf_bf: |
| 12872 | case Hexagon::V6_vmpy_sf_hf: |
| 12873 | case Hexagon::V6_vmpybusv: |
| 12874 | case Hexagon::V6_vmpybv: |
| 12875 | case Hexagon::V6_vmpyewuh_64: |
| 12876 | case Hexagon::V6_vmpyhus: |
| 12877 | case Hexagon::V6_vmpyhv: |
| 12878 | case Hexagon::V6_vmpyubv: |
| 12879 | case Hexagon::V6_vmpyuhv: |
| 12880 | case Hexagon::V6_vshufoeb: |
| 12881 | case Hexagon::V6_vshufoeh: |
| 12882 | case Hexagon::V6_vsub_hf_f8: |
| 12883 | case Hexagon::V6_vsub_sf_bf: |
| 12884 | case Hexagon::V6_vsub_sf_hf: |
| 12885 | case Hexagon::V6_vsubhw: |
| 12886 | case Hexagon::V6_vsububh: |
| 12887 | case Hexagon::V6_vsubuhw: { |
| 12888 | switch (OpNum) { |
| 12889 | case 1: |
| 12890 | // op: Vu32 |
| 12891 | return 8; |
| 12892 | case 2: |
| 12893 | // op: Vv32 |
| 12894 | return 16; |
| 12895 | case 0: |
| 12896 | // op: Vdd32 |
| 12897 | return 0; |
| 12898 | } |
| 12899 | break; |
| 12900 | } |
| 12901 | case Hexagon::V6_vaddcarrysat: { |
| 12902 | switch (OpNum) { |
| 12903 | case 1: |
| 12904 | // op: Vu32 |
| 12905 | return 8; |
| 12906 | case 2: |
| 12907 | // op: Vv32 |
| 12908 | return 16; |
| 12909 | case 3: |
| 12910 | // op: Qs4 |
| 12911 | return 5; |
| 12912 | case 0: |
| 12913 | // op: Vd32 |
| 12914 | return 0; |
| 12915 | } |
| 12916 | break; |
| 12917 | } |
| 12918 | case Hexagon::V6_valign4: |
| 12919 | case Hexagon::V6_valignb: |
| 12920 | case Hexagon::V6_vasrhbrndsat: |
| 12921 | case Hexagon::V6_vasrhbsat: |
| 12922 | case Hexagon::V6_vasrhubrndsat: |
| 12923 | case Hexagon::V6_vasrhubsat: |
| 12924 | case Hexagon::V6_vasruhubrndsat: |
| 12925 | case Hexagon::V6_vasruhubsat: |
| 12926 | case Hexagon::V6_vasruwuhrndsat: |
| 12927 | case Hexagon::V6_vasruwuhsat: |
| 12928 | case Hexagon::V6_vasrwh: |
| 12929 | case Hexagon::V6_vasrwhrndsat: |
| 12930 | case Hexagon::V6_vasrwhsat: |
| 12931 | case Hexagon::V6_vasrwuhrndsat: |
| 12932 | case Hexagon::V6_vasrwuhsat: |
| 12933 | case Hexagon::V6_vlalignb: |
| 12934 | case Hexagon::V6_vlutvvb: |
| 12935 | case Hexagon::V6_vlutvvb_nm: { |
| 12936 | switch (OpNum) { |
| 12937 | case 1: |
| 12938 | // op: Vu32 |
| 12939 | return 8; |
| 12940 | case 2: |
| 12941 | // op: Vv32 |
| 12942 | return 19; |
| 12943 | case 3: |
| 12944 | // op: Rt8 |
| 12945 | return 16; |
| 12946 | case 0: |
| 12947 | // op: Vd32 |
| 12948 | return 0; |
| 12949 | } |
| 12950 | break; |
| 12951 | } |
| 12952 | case Hexagon::V6_vdealvdd: |
| 12953 | case Hexagon::V6_vlutvwh: |
| 12954 | case Hexagon::V6_vlutvwh_nm: |
| 12955 | case Hexagon::V6_vshuffvdd: { |
| 12956 | switch (OpNum) { |
| 12957 | case 1: |
| 12958 | // op: Vu32 |
| 12959 | return 8; |
| 12960 | case 2: |
| 12961 | // op: Vv32 |
| 12962 | return 19; |
| 12963 | case 3: |
| 12964 | // op: Rt8 |
| 12965 | return 16; |
| 12966 | case 0: |
| 12967 | // op: Vdd32 |
| 12968 | return 0; |
| 12969 | } |
| 12970 | break; |
| 12971 | } |
| 12972 | case Hexagon::V6_vconv_bf_qf32: |
| 12973 | case Hexagon::V6_vconv_hf_qf32: { |
| 12974 | switch (OpNum) { |
| 12975 | case 1: |
| 12976 | // op: Vuu32 |
| 12977 | return 8; |
| 12978 | case 0: |
| 12979 | // op: Vd32 |
| 12980 | return 0; |
| 12981 | } |
| 12982 | break; |
| 12983 | } |
| 12984 | case Hexagon::V6_vdmpyhisat: |
| 12985 | case Hexagon::V6_vdmpyhsuisat: { |
| 12986 | switch (OpNum) { |
| 12987 | case 1: |
| 12988 | // op: Vuu32 |
| 12989 | return 8; |
| 12990 | case 2: |
| 12991 | // op: Rt32 |
| 12992 | return 16; |
| 12993 | case 0: |
| 12994 | // op: Vd32 |
| 12995 | return 0; |
| 12996 | } |
| 12997 | break; |
| 12998 | } |
| 12999 | case Hexagon::V6_vdmpybus_dv: |
| 13000 | case Hexagon::V6_vdmpyhb_dv: |
| 13001 | case Hexagon::V6_vdsaduh: |
| 13002 | case Hexagon::V6_vmpabus: |
| 13003 | case Hexagon::V6_vmpabuu: |
| 13004 | case Hexagon::V6_vmpahb: |
| 13005 | case Hexagon::V6_vmpauhb: |
| 13006 | case Hexagon::V6_vtmpyb: |
| 13007 | case Hexagon::V6_vtmpybus: |
| 13008 | case Hexagon::V6_vtmpyhb: { |
| 13009 | switch (OpNum) { |
| 13010 | case 1: |
| 13011 | // op: Vuu32 |
| 13012 | return 8; |
| 13013 | case 2: |
| 13014 | // op: Rt32 |
| 13015 | return 16; |
| 13016 | case 0: |
| 13017 | // op: Vdd32 |
| 13018 | return 0; |
| 13019 | } |
| 13020 | break; |
| 13021 | } |
| 13022 | case Hexagon::V6_vasrvuhubrndsat: |
| 13023 | case Hexagon::V6_vasrvuhubsat: |
| 13024 | case Hexagon::V6_vasrvwuhrndsat: |
| 13025 | case Hexagon::V6_vasrvwuhsat: { |
| 13026 | switch (OpNum) { |
| 13027 | case 1: |
| 13028 | // op: Vuu32 |
| 13029 | return 8; |
| 13030 | case 2: |
| 13031 | // op: Vv32 |
| 13032 | return 16; |
| 13033 | case 0: |
| 13034 | // op: Vd32 |
| 13035 | return 0; |
| 13036 | } |
| 13037 | break; |
| 13038 | } |
| 13039 | case Hexagon::V6_vaddb_dv: |
| 13040 | case Hexagon::V6_vaddbsat_dv: |
| 13041 | case Hexagon::V6_vaddh_dv: |
| 13042 | case Hexagon::V6_vaddhsat_dv: |
| 13043 | case Hexagon::V6_vaddubsat_dv: |
| 13044 | case Hexagon::V6_vadduhsat_dv: |
| 13045 | case Hexagon::V6_vadduwsat_dv: |
| 13046 | case Hexagon::V6_vaddw_dv: |
| 13047 | case Hexagon::V6_vaddwsat_dv: |
| 13048 | case Hexagon::V6_vmpabusv: |
| 13049 | case Hexagon::V6_vmpabuuv: |
| 13050 | case Hexagon::V6_vsubb_dv: |
| 13051 | case Hexagon::V6_vsubbsat_dv: |
| 13052 | case Hexagon::V6_vsubh_dv: |
| 13053 | case Hexagon::V6_vsubhsat_dv: |
| 13054 | case Hexagon::V6_vsububsat_dv: |
| 13055 | case Hexagon::V6_vsubuhsat_dv: |
| 13056 | case Hexagon::V6_vsubuwsat_dv: |
| 13057 | case Hexagon::V6_vsubw_dv: |
| 13058 | case Hexagon::V6_vsubwsat_dv: { |
| 13059 | switch (OpNum) { |
| 13060 | case 1: |
| 13061 | // op: Vuu32 |
| 13062 | return 8; |
| 13063 | case 2: |
| 13064 | // op: Vvv32 |
| 13065 | return 16; |
| 13066 | case 0: |
| 13067 | // op: Vdd32 |
| 13068 | return 0; |
| 13069 | } |
| 13070 | break; |
| 13071 | } |
| 13072 | case Hexagon::L4_loadbsw2_ap: |
| 13073 | case Hexagon::L4_loadbzw2_ap: |
| 13074 | case Hexagon::L4_loadrb_ap: |
| 13075 | case Hexagon::L4_loadrh_ap: |
| 13076 | case Hexagon::L4_loadri_ap: |
| 13077 | case Hexagon::L4_loadrub_ap: |
| 13078 | case Hexagon::L4_loadruh_ap: { |
| 13079 | switch (OpNum) { |
| 13080 | case 2: |
| 13081 | // op: II |
| 13082 | return 5; |
| 13083 | case 0: |
| 13084 | // op: Rd32 |
| 13085 | return 0; |
| 13086 | case 1: |
| 13087 | // op: Re32 |
| 13088 | return 16; |
| 13089 | } |
| 13090 | break; |
| 13091 | } |
| 13092 | case Hexagon::L4_loadbsw4_ap: |
| 13093 | case Hexagon::L4_loadbzw4_ap: |
| 13094 | case Hexagon::L4_loadrd_ap: { |
| 13095 | switch (OpNum) { |
| 13096 | case 2: |
| 13097 | // op: II |
| 13098 | return 5; |
| 13099 | case 0: |
| 13100 | // op: Rdd32 |
| 13101 | return 0; |
| 13102 | case 1: |
| 13103 | // op: Re32 |
| 13104 | return 16; |
| 13105 | } |
| 13106 | break; |
| 13107 | } |
| 13108 | case Hexagon::A2_tfrih: |
| 13109 | case Hexagon::A2_tfril: |
| 13110 | case Hexagon::S2_allocframe: { |
| 13111 | switch (OpNum) { |
| 13112 | case 2: |
| 13113 | // op: Ii |
| 13114 | return 0; |
| 13115 | case 0: |
| 13116 | // op: Rx32 |
| 13117 | return 16; |
| 13118 | } |
| 13119 | break; |
| 13120 | } |
| 13121 | case Hexagon::J4_cmpeq_f_jumpnv_nt: |
| 13122 | case Hexagon::J4_cmpeq_f_jumpnv_t: |
| 13123 | case Hexagon::J4_cmpeq_t_jumpnv_nt: |
| 13124 | case Hexagon::J4_cmpeq_t_jumpnv_t: |
| 13125 | case Hexagon::J4_cmpgt_f_jumpnv_nt: |
| 13126 | case Hexagon::J4_cmpgt_f_jumpnv_t: |
| 13127 | case Hexagon::J4_cmpgt_t_jumpnv_nt: |
| 13128 | case Hexagon::J4_cmpgt_t_jumpnv_t: |
| 13129 | case Hexagon::J4_cmpgtu_f_jumpnv_nt: |
| 13130 | case Hexagon::J4_cmpgtu_f_jumpnv_t: |
| 13131 | case Hexagon::J4_cmpgtu_t_jumpnv_nt: |
| 13132 | case Hexagon::J4_cmpgtu_t_jumpnv_t: { |
| 13133 | switch (OpNum) { |
| 13134 | case 2: |
| 13135 | // op: Ii |
| 13136 | return 1; |
| 13137 | case 0: |
| 13138 | // op: Ns8 |
| 13139 | return 16; |
| 13140 | case 1: |
| 13141 | // op: Rt32 |
| 13142 | return 8; |
| 13143 | } |
| 13144 | break; |
| 13145 | } |
| 13146 | case Hexagon::J4_cmpeqn1_f_jumpnv_nt: |
| 13147 | case Hexagon::J4_cmpeqn1_f_jumpnv_t: |
| 13148 | case Hexagon::J4_cmpeqn1_t_jumpnv_nt: |
| 13149 | case Hexagon::J4_cmpeqn1_t_jumpnv_t: |
| 13150 | case Hexagon::J4_cmpgtn1_f_jumpnv_nt: |
| 13151 | case Hexagon::J4_cmpgtn1_f_jumpnv_t: |
| 13152 | case Hexagon::J4_cmpgtn1_t_jumpnv_nt: |
| 13153 | case Hexagon::J4_cmpgtn1_t_jumpnv_t: { |
| 13154 | switch (OpNum) { |
| 13155 | case 2: |
| 13156 | // op: Ii |
| 13157 | return 1; |
| 13158 | case 0: |
| 13159 | // op: Ns8 |
| 13160 | return 16; |
| 13161 | } |
| 13162 | break; |
| 13163 | } |
| 13164 | case Hexagon::J4_cmpeq_fp0_jump_nt: |
| 13165 | case Hexagon::J4_cmpeq_fp0_jump_t: |
| 13166 | case Hexagon::J4_cmpeq_fp1_jump_nt: |
| 13167 | case Hexagon::J4_cmpeq_fp1_jump_t: |
| 13168 | case Hexagon::J4_cmpeq_tp0_jump_nt: |
| 13169 | case Hexagon::J4_cmpeq_tp0_jump_t: |
| 13170 | case Hexagon::J4_cmpeq_tp1_jump_nt: |
| 13171 | case Hexagon::J4_cmpeq_tp1_jump_t: |
| 13172 | case Hexagon::J4_cmpgt_fp0_jump_nt: |
| 13173 | case Hexagon::J4_cmpgt_fp0_jump_t: |
| 13174 | case Hexagon::J4_cmpgt_fp1_jump_nt: |
| 13175 | case Hexagon::J4_cmpgt_fp1_jump_t: |
| 13176 | case Hexagon::J4_cmpgt_tp0_jump_nt: |
| 13177 | case Hexagon::J4_cmpgt_tp0_jump_t: |
| 13178 | case Hexagon::J4_cmpgt_tp1_jump_nt: |
| 13179 | case Hexagon::J4_cmpgt_tp1_jump_t: |
| 13180 | case Hexagon::J4_cmpgtu_fp0_jump_nt: |
| 13181 | case Hexagon::J4_cmpgtu_fp0_jump_t: |
| 13182 | case Hexagon::J4_cmpgtu_fp1_jump_nt: |
| 13183 | case Hexagon::J4_cmpgtu_fp1_jump_t: |
| 13184 | case Hexagon::J4_cmpgtu_tp0_jump_nt: |
| 13185 | case Hexagon::J4_cmpgtu_tp0_jump_t: |
| 13186 | case Hexagon::J4_cmpgtu_tp1_jump_nt: |
| 13187 | case Hexagon::J4_cmpgtu_tp1_jump_t: { |
| 13188 | switch (OpNum) { |
| 13189 | case 2: |
| 13190 | // op: Ii |
| 13191 | return 1; |
| 13192 | case 0: |
| 13193 | // op: Rs16 |
| 13194 | return 16; |
| 13195 | case 1: |
| 13196 | // op: Rt16 |
| 13197 | return 8; |
| 13198 | } |
| 13199 | break; |
| 13200 | } |
| 13201 | case Hexagon::J4_cmpeqn1_fp0_jump_nt: |
| 13202 | case Hexagon::J4_cmpeqn1_fp0_jump_t: |
| 13203 | case Hexagon::J4_cmpeqn1_fp1_jump_nt: |
| 13204 | case Hexagon::J4_cmpeqn1_fp1_jump_t: |
| 13205 | case Hexagon::J4_cmpeqn1_tp0_jump_nt: |
| 13206 | case Hexagon::J4_cmpeqn1_tp0_jump_t: |
| 13207 | case Hexagon::J4_cmpeqn1_tp1_jump_nt: |
| 13208 | case Hexagon::J4_cmpeqn1_tp1_jump_t: |
| 13209 | case Hexagon::J4_cmpgtn1_fp0_jump_nt: |
| 13210 | case Hexagon::J4_cmpgtn1_fp0_jump_t: |
| 13211 | case Hexagon::J4_cmpgtn1_fp1_jump_nt: |
| 13212 | case Hexagon::J4_cmpgtn1_fp1_jump_t: |
| 13213 | case Hexagon::J4_cmpgtn1_tp0_jump_nt: |
| 13214 | case Hexagon::J4_cmpgtn1_tp0_jump_t: |
| 13215 | case Hexagon::J4_cmpgtn1_tp1_jump_nt: |
| 13216 | case Hexagon::J4_cmpgtn1_tp1_jump_t: { |
| 13217 | switch (OpNum) { |
| 13218 | case 2: |
| 13219 | // op: Ii |
| 13220 | return 1; |
| 13221 | case 0: |
| 13222 | // op: Rs16 |
| 13223 | return 16; |
| 13224 | } |
| 13225 | break; |
| 13226 | } |
| 13227 | case Hexagon::J4_cmplt_f_jumpnv_nt: |
| 13228 | case Hexagon::J4_cmplt_f_jumpnv_t: |
| 13229 | case Hexagon::J4_cmplt_t_jumpnv_nt: |
| 13230 | case Hexagon::J4_cmplt_t_jumpnv_t: |
| 13231 | case Hexagon::J4_cmpltu_f_jumpnv_nt: |
| 13232 | case Hexagon::J4_cmpltu_f_jumpnv_t: |
| 13233 | case Hexagon::J4_cmpltu_t_jumpnv_nt: |
| 13234 | case Hexagon::J4_cmpltu_t_jumpnv_t: { |
| 13235 | switch (OpNum) { |
| 13236 | case 2: |
| 13237 | // op: Ii |
| 13238 | return 1; |
| 13239 | case 0: |
| 13240 | // op: Rt32 |
| 13241 | return 8; |
| 13242 | case 1: |
| 13243 | // op: Ns8 |
| 13244 | return 16; |
| 13245 | } |
| 13246 | break; |
| 13247 | } |
| 13248 | case Hexagon::J4_jumpsetr: { |
| 13249 | switch (OpNum) { |
| 13250 | case 2: |
| 13251 | // op: Ii |
| 13252 | return 1; |
| 13253 | case 1: |
| 13254 | // op: Rs16 |
| 13255 | return 16; |
| 13256 | case 0: |
| 13257 | // op: Rd16 |
| 13258 | return 8; |
| 13259 | } |
| 13260 | break; |
| 13261 | } |
| 13262 | case Hexagon::J2_trap1: { |
| 13263 | switch (OpNum) { |
| 13264 | case 2: |
| 13265 | // op: Ii |
| 13266 | return 2; |
| 13267 | case 0: |
| 13268 | // op: Rx32 |
| 13269 | return 16; |
| 13270 | } |
| 13271 | break; |
| 13272 | } |
| 13273 | case Hexagon::S2_pstorerbnewf_io: |
| 13274 | case Hexagon::S2_pstorerbnewt_io: |
| 13275 | case Hexagon::S2_pstorerhnewf_io: |
| 13276 | case Hexagon::S2_pstorerhnewt_io: |
| 13277 | case Hexagon::S2_pstorerinewf_io: |
| 13278 | case Hexagon::S2_pstorerinewt_io: |
| 13279 | case Hexagon::S4_pstorerbnewfnew_io: |
| 13280 | case Hexagon::S4_pstorerbnewtnew_io: |
| 13281 | case Hexagon::S4_pstorerhnewfnew_io: |
| 13282 | case Hexagon::S4_pstorerhnewtnew_io: |
| 13283 | case Hexagon::S4_pstorerinewfnew_io: |
| 13284 | case Hexagon::S4_pstorerinewtnew_io: { |
| 13285 | switch (OpNum) { |
| 13286 | case 2: |
| 13287 | // op: Ii |
| 13288 | return 3; |
| 13289 | case 0: |
| 13290 | // op: Pv4 |
| 13291 | return 0; |
| 13292 | case 1: |
| 13293 | // op: Rs32 |
| 13294 | return 16; |
| 13295 | case 3: |
| 13296 | // op: Nt8 |
| 13297 | return 8; |
| 13298 | } |
| 13299 | break; |
| 13300 | } |
| 13301 | case Hexagon::S2_pstorerbf_io: |
| 13302 | case Hexagon::S2_pstorerbt_io: |
| 13303 | case Hexagon::S2_pstorerff_io: |
| 13304 | case Hexagon::S2_pstorerft_io: |
| 13305 | case Hexagon::S2_pstorerhf_io: |
| 13306 | case Hexagon::S2_pstorerht_io: |
| 13307 | case Hexagon::S2_pstorerif_io: |
| 13308 | case Hexagon::S2_pstorerit_io: |
| 13309 | case Hexagon::S4_pstorerbfnew_io: |
| 13310 | case Hexagon::S4_pstorerbtnew_io: |
| 13311 | case Hexagon::S4_pstorerffnew_io: |
| 13312 | case Hexagon::S4_pstorerftnew_io: |
| 13313 | case Hexagon::S4_pstorerhfnew_io: |
| 13314 | case Hexagon::S4_pstorerhtnew_io: |
| 13315 | case Hexagon::S4_pstorerifnew_io: |
| 13316 | case Hexagon::S4_pstoreritnew_io: { |
| 13317 | switch (OpNum) { |
| 13318 | case 2: |
| 13319 | // op: Ii |
| 13320 | return 3; |
| 13321 | case 0: |
| 13322 | // op: Pv4 |
| 13323 | return 0; |
| 13324 | case 1: |
| 13325 | // op: Rs32 |
| 13326 | return 16; |
| 13327 | case 3: |
| 13328 | // op: Rt32 |
| 13329 | return 8; |
| 13330 | } |
| 13331 | break; |
| 13332 | } |
| 13333 | case Hexagon::S2_pstorerdf_io: |
| 13334 | case Hexagon::S2_pstorerdt_io: |
| 13335 | case Hexagon::S4_pstorerdfnew_io: |
| 13336 | case Hexagon::S4_pstorerdtnew_io: { |
| 13337 | switch (OpNum) { |
| 13338 | case 2: |
| 13339 | // op: Ii |
| 13340 | return 3; |
| 13341 | case 0: |
| 13342 | // op: Pv4 |
| 13343 | return 0; |
| 13344 | case 1: |
| 13345 | // op: Rs32 |
| 13346 | return 16; |
| 13347 | case 3: |
| 13348 | // op: Rtt32 |
| 13349 | return 8; |
| 13350 | } |
| 13351 | break; |
| 13352 | } |
| 13353 | case Hexagon::S2_storerbnew_pci: |
| 13354 | case Hexagon::S2_storerhnew_pci: |
| 13355 | case Hexagon::S2_storerinew_pci: { |
| 13356 | switch (OpNum) { |
| 13357 | case 2: |
| 13358 | // op: Ii |
| 13359 | return 3; |
| 13360 | case 3: |
| 13361 | // op: Mu2 |
| 13362 | return 13; |
| 13363 | case 4: |
| 13364 | // op: Nt8 |
| 13365 | return 8; |
| 13366 | case 0: |
| 13367 | // op: Rx32 |
| 13368 | return 16; |
| 13369 | } |
| 13370 | break; |
| 13371 | } |
| 13372 | case Hexagon::S2_storerb_pci: |
| 13373 | case Hexagon::S2_storerf_pci: |
| 13374 | case Hexagon::S2_storerh_pci: |
| 13375 | case Hexagon::S2_storeri_pci: { |
| 13376 | switch (OpNum) { |
| 13377 | case 2: |
| 13378 | // op: Ii |
| 13379 | return 3; |
| 13380 | case 3: |
| 13381 | // op: Mu2 |
| 13382 | return 13; |
| 13383 | case 4: |
| 13384 | // op: Rt32 |
| 13385 | return 8; |
| 13386 | case 0: |
| 13387 | // op: Rx32 |
| 13388 | return 16; |
| 13389 | } |
| 13390 | break; |
| 13391 | } |
| 13392 | case Hexagon::S2_storerd_pci: { |
| 13393 | switch (OpNum) { |
| 13394 | case 2: |
| 13395 | // op: Ii |
| 13396 | return 3; |
| 13397 | case 3: |
| 13398 | // op: Mu2 |
| 13399 | return 13; |
| 13400 | case 4: |
| 13401 | // op: Rtt32 |
| 13402 | return 8; |
| 13403 | case 0: |
| 13404 | // op: Rx32 |
| 13405 | return 16; |
| 13406 | } |
| 13407 | break; |
| 13408 | } |
| 13409 | case Hexagon::S2_storerbnew_pi: |
| 13410 | case Hexagon::S2_storerhnew_pi: |
| 13411 | case Hexagon::S2_storerinew_pi: { |
| 13412 | switch (OpNum) { |
| 13413 | case 2: |
| 13414 | // op: Ii |
| 13415 | return 3; |
| 13416 | case 3: |
| 13417 | // op: Nt8 |
| 13418 | return 8; |
| 13419 | case 0: |
| 13420 | // op: Rx32 |
| 13421 | return 16; |
| 13422 | } |
| 13423 | break; |
| 13424 | } |
| 13425 | case Hexagon::S2_storerb_pi: |
| 13426 | case Hexagon::S2_storerf_pi: |
| 13427 | case Hexagon::S2_storerh_pi: |
| 13428 | case Hexagon::S2_storeri_pi: { |
| 13429 | switch (OpNum) { |
| 13430 | case 2: |
| 13431 | // op: Ii |
| 13432 | return 3; |
| 13433 | case 3: |
| 13434 | // op: Rt32 |
| 13435 | return 8; |
| 13436 | case 0: |
| 13437 | // op: Rx32 |
| 13438 | return 16; |
| 13439 | } |
| 13440 | break; |
| 13441 | } |
| 13442 | case Hexagon::S2_storerd_pi: { |
| 13443 | switch (OpNum) { |
| 13444 | case 2: |
| 13445 | // op: Ii |
| 13446 | return 3; |
| 13447 | case 3: |
| 13448 | // op: Rtt32 |
| 13449 | return 8; |
| 13450 | case 0: |
| 13451 | // op: Rx32 |
| 13452 | return 16; |
| 13453 | } |
| 13454 | break; |
| 13455 | } |
| 13456 | case Hexagon::SA1_addi: { |
| 13457 | switch (OpNum) { |
| 13458 | case 2: |
| 13459 | // op: Ii |
| 13460 | return 4; |
| 13461 | case 0: |
| 13462 | // op: Rx16 |
| 13463 | return 0; |
| 13464 | } |
| 13465 | break; |
| 13466 | } |
| 13467 | case Hexagon::C2_cmoveif: |
| 13468 | case Hexagon::C2_cmoveit: |
| 13469 | case Hexagon::C2_cmovenewif: |
| 13470 | case Hexagon::C2_cmovenewit: { |
| 13471 | switch (OpNum) { |
| 13472 | case 2: |
| 13473 | // op: Ii |
| 13474 | return 5; |
| 13475 | case 1: |
| 13476 | // op: Pu4 |
| 13477 | return 21; |
| 13478 | case 0: |
| 13479 | // op: Rd32 |
| 13480 | return 0; |
| 13481 | } |
| 13482 | break; |
| 13483 | } |
| 13484 | case Hexagon::C2_muxri: { |
| 13485 | switch (OpNum) { |
| 13486 | case 2: |
| 13487 | // op: Ii |
| 13488 | return 5; |
| 13489 | case 1: |
| 13490 | // op: Pu4 |
| 13491 | return 21; |
| 13492 | case 3: |
| 13493 | // op: Rs32 |
| 13494 | return 16; |
| 13495 | case 0: |
| 13496 | // op: Rd32 |
| 13497 | return 0; |
| 13498 | } |
| 13499 | break; |
| 13500 | } |
| 13501 | case Hexagon::A4_cmpbeqi: |
| 13502 | case Hexagon::A4_cmpbgti: |
| 13503 | case Hexagon::A4_cmpbgtui: |
| 13504 | case Hexagon::A4_cmpheqi: |
| 13505 | case Hexagon::A4_cmphgti: |
| 13506 | case Hexagon::A4_cmphgtui: |
| 13507 | case Hexagon::C2_cmpeqi: |
| 13508 | case Hexagon::C2_cmpgti: |
| 13509 | case Hexagon::C2_cmpgtui: |
| 13510 | case Hexagon::C4_cmpltei: |
| 13511 | case Hexagon::C4_cmplteui: |
| 13512 | case Hexagon::C4_cmpneqi: { |
| 13513 | switch (OpNum) { |
| 13514 | case 2: |
| 13515 | // op: Ii |
| 13516 | return 5; |
| 13517 | case 1: |
| 13518 | // op: Rs32 |
| 13519 | return 16; |
| 13520 | case 0: |
| 13521 | // op: Pd4 |
| 13522 | return 0; |
| 13523 | } |
| 13524 | break; |
| 13525 | } |
| 13526 | case Hexagon::A2_addi: |
| 13527 | case Hexagon::A2_andir: |
| 13528 | case Hexagon::A2_orir: |
| 13529 | case Hexagon::A4_rcmpeqi: |
| 13530 | case Hexagon::A4_rcmpneqi: |
| 13531 | case Hexagon::L2_loadbsw2_io: |
| 13532 | case Hexagon::L2_loadbzw2_io: |
| 13533 | case Hexagon::L2_loadrb_io: |
| 13534 | case Hexagon::L2_loadrh_io: |
| 13535 | case Hexagon::L2_loadri_io: |
| 13536 | case Hexagon::L2_loadrub_io: |
| 13537 | case Hexagon::L2_loadruh_io: |
| 13538 | case Hexagon::M2_mpysin: |
| 13539 | case Hexagon::M2_mpysip: { |
| 13540 | switch (OpNum) { |
| 13541 | case 2: |
| 13542 | // op: Ii |
| 13543 | return 5; |
| 13544 | case 1: |
| 13545 | // op: Rs32 |
| 13546 | return 16; |
| 13547 | case 0: |
| 13548 | // op: Rd32 |
| 13549 | return 0; |
| 13550 | } |
| 13551 | break; |
| 13552 | } |
| 13553 | case Hexagon::A4_combineri: |
| 13554 | case Hexagon::L2_loadbsw4_io: |
| 13555 | case Hexagon::L2_loadbzw4_io: |
| 13556 | case Hexagon::L2_loadrd_io: { |
| 13557 | switch (OpNum) { |
| 13558 | case 2: |
| 13559 | // op: Ii |
| 13560 | return 5; |
| 13561 | case 1: |
| 13562 | // op: Rs32 |
| 13563 | return 16; |
| 13564 | case 0: |
| 13565 | // op: Rdd32 |
| 13566 | return 0; |
| 13567 | } |
| 13568 | break; |
| 13569 | } |
| 13570 | case Hexagon::S4_subaddi: { |
| 13571 | switch (OpNum) { |
| 13572 | case 2: |
| 13573 | // op: Ii |
| 13574 | return 5; |
| 13575 | case 1: |
| 13576 | // op: Rs32 |
| 13577 | return 16; |
| 13578 | case 3: |
| 13579 | // op: Ru32 |
| 13580 | return 0; |
| 13581 | case 0: |
| 13582 | // op: Rd32 |
| 13583 | return 8; |
| 13584 | } |
| 13585 | break; |
| 13586 | } |
| 13587 | case Hexagon::A4_vcmpbeqi: |
| 13588 | case Hexagon::A4_vcmpbgti: |
| 13589 | case Hexagon::A4_vcmpbgtui: |
| 13590 | case Hexagon::A4_vcmpheqi: |
| 13591 | case Hexagon::A4_vcmphgti: |
| 13592 | case Hexagon::A4_vcmphgtui: |
| 13593 | case Hexagon::A4_vcmpweqi: |
| 13594 | case Hexagon::A4_vcmpwgti: |
| 13595 | case Hexagon::A4_vcmpwgtui: |
| 13596 | case Hexagon::F2_dfclass: { |
| 13597 | switch (OpNum) { |
| 13598 | case 2: |
| 13599 | // op: Ii |
| 13600 | return 5; |
| 13601 | case 1: |
| 13602 | // op: Rss32 |
| 13603 | return 16; |
| 13604 | case 0: |
| 13605 | // op: Pd4 |
| 13606 | return 0; |
| 13607 | } |
| 13608 | break; |
| 13609 | } |
| 13610 | case Hexagon::M4_mpyri_addr_u2: { |
| 13611 | switch (OpNum) { |
| 13612 | case 2: |
| 13613 | // op: Ii |
| 13614 | return 5; |
| 13615 | case 1: |
| 13616 | // op: Ru32 |
| 13617 | return 0; |
| 13618 | case 3: |
| 13619 | // op: Rs32 |
| 13620 | return 16; |
| 13621 | case 0: |
| 13622 | // op: Rd32 |
| 13623 | return 8; |
| 13624 | } |
| 13625 | break; |
| 13626 | } |
| 13627 | case Hexagon::C2_muxii: { |
| 13628 | switch (OpNum) { |
| 13629 | case 2: |
| 13630 | // op: Ii |
| 13631 | return 5; |
| 13632 | case 3: |
| 13633 | // op: II |
| 13634 | return 13; |
| 13635 | case 1: |
| 13636 | // op: Pu4 |
| 13637 | return 23; |
| 13638 | case 0: |
| 13639 | // op: Rd32 |
| 13640 | return 0; |
| 13641 | } |
| 13642 | break; |
| 13643 | } |
| 13644 | case Hexagon::S4_storerbnew_rr: |
| 13645 | case Hexagon::S4_storerhnew_rr: |
| 13646 | case Hexagon::S4_storerinew_rr: { |
| 13647 | switch (OpNum) { |
| 13648 | case 2: |
| 13649 | // op: Ii |
| 13650 | return 7; |
| 13651 | case 0: |
| 13652 | // op: Rs32 |
| 13653 | return 16; |
| 13654 | case 1: |
| 13655 | // op: Ru32 |
| 13656 | return 8; |
| 13657 | case 3: |
| 13658 | // op: Nt8 |
| 13659 | return 0; |
| 13660 | } |
| 13661 | break; |
| 13662 | } |
| 13663 | case Hexagon::S4_storerb_rr: |
| 13664 | case Hexagon::S4_storerf_rr: |
| 13665 | case Hexagon::S4_storerh_rr: |
| 13666 | case Hexagon::S4_storeri_rr: { |
| 13667 | switch (OpNum) { |
| 13668 | case 2: |
| 13669 | // op: Ii |
| 13670 | return 7; |
| 13671 | case 0: |
| 13672 | // op: Rs32 |
| 13673 | return 16; |
| 13674 | case 1: |
| 13675 | // op: Ru32 |
| 13676 | return 8; |
| 13677 | case 3: |
| 13678 | // op: Rt32 |
| 13679 | return 0; |
| 13680 | } |
| 13681 | break; |
| 13682 | } |
| 13683 | case Hexagon::S4_storerd_rr: { |
| 13684 | switch (OpNum) { |
| 13685 | case 2: |
| 13686 | // op: Ii |
| 13687 | return 7; |
| 13688 | case 0: |
| 13689 | // op: Rs32 |
| 13690 | return 16; |
| 13691 | case 1: |
| 13692 | // op: Ru32 |
| 13693 | return 8; |
| 13694 | case 3: |
| 13695 | // op: Rtt32 |
| 13696 | return 0; |
| 13697 | } |
| 13698 | break; |
| 13699 | } |
| 13700 | case Hexagon::S4_storeirbf_io: |
| 13701 | case Hexagon::S4_storeirbfnew_io: |
| 13702 | case Hexagon::S4_storeirbt_io: |
| 13703 | case Hexagon::S4_storeirbtnew_io: |
| 13704 | case Hexagon::S4_storeirhf_io: |
| 13705 | case Hexagon::S4_storeirhfnew_io: |
| 13706 | case Hexagon::S4_storeirht_io: |
| 13707 | case Hexagon::S4_storeirhtnew_io: |
| 13708 | case Hexagon::S4_storeirif_io: |
| 13709 | case Hexagon::S4_storeirifnew_io: |
| 13710 | case Hexagon::S4_storeirit_io: |
| 13711 | case Hexagon::S4_storeiritnew_io: { |
| 13712 | switch (OpNum) { |
| 13713 | case 2: |
| 13714 | // op: Ii |
| 13715 | return 7; |
| 13716 | case 3: |
| 13717 | // op: II |
| 13718 | return 0; |
| 13719 | case 0: |
| 13720 | // op: Pv4 |
| 13721 | return 5; |
| 13722 | case 1: |
| 13723 | // op: Rs32 |
| 13724 | return 16; |
| 13725 | } |
| 13726 | break; |
| 13727 | } |
| 13728 | case Hexagon::L4_loadbsw2_ur: |
| 13729 | case Hexagon::L4_loadbzw2_ur: |
| 13730 | case Hexagon::L4_loadrb_ur: |
| 13731 | case Hexagon::L4_loadrh_ur: |
| 13732 | case Hexagon::L4_loadri_ur: |
| 13733 | case Hexagon::L4_loadrub_ur: |
| 13734 | case Hexagon::L4_loadruh_ur: { |
| 13735 | switch (OpNum) { |
| 13736 | case 2: |
| 13737 | // op: Ii |
| 13738 | return 7; |
| 13739 | case 3: |
| 13740 | // op: II |
| 13741 | return 5; |
| 13742 | case 1: |
| 13743 | // op: Rt32 |
| 13744 | return 16; |
| 13745 | case 0: |
| 13746 | // op: Rd32 |
| 13747 | return 0; |
| 13748 | } |
| 13749 | break; |
| 13750 | } |
| 13751 | case Hexagon::L4_loadbsw4_ur: |
| 13752 | case Hexagon::L4_loadbzw4_ur: |
| 13753 | case Hexagon::L4_loadrd_ur: { |
| 13754 | switch (OpNum) { |
| 13755 | case 2: |
| 13756 | // op: Ii |
| 13757 | return 7; |
| 13758 | case 3: |
| 13759 | // op: II |
| 13760 | return 5; |
| 13761 | case 1: |
| 13762 | // op: Rt32 |
| 13763 | return 16; |
| 13764 | case 0: |
| 13765 | // op: Rdd32 |
| 13766 | return 0; |
| 13767 | } |
| 13768 | break; |
| 13769 | } |
| 13770 | case Hexagon::V6_vS32b_new_npred_ai: |
| 13771 | case Hexagon::V6_vS32b_new_pred_ai: |
| 13772 | case Hexagon::V6_vS32b_nt_new_npred_ai: |
| 13773 | case Hexagon::V6_vS32b_nt_new_pred_ai: { |
| 13774 | switch (OpNum) { |
| 13775 | case 2: |
| 13776 | // op: Ii |
| 13777 | return 8; |
| 13778 | case 0: |
| 13779 | // op: Pv4 |
| 13780 | return 11; |
| 13781 | case 1: |
| 13782 | // op: Rt32 |
| 13783 | return 16; |
| 13784 | case 3: |
| 13785 | // op: Os8 |
| 13786 | return 0; |
| 13787 | } |
| 13788 | break; |
| 13789 | } |
| 13790 | case Hexagon::V6_vS32Ub_npred_ai: |
| 13791 | case Hexagon::V6_vS32Ub_pred_ai: |
| 13792 | case Hexagon::V6_vS32b_npred_ai: |
| 13793 | case Hexagon::V6_vS32b_nt_npred_ai: |
| 13794 | case Hexagon::V6_vS32b_nt_pred_ai: |
| 13795 | case Hexagon::V6_vS32b_pred_ai: { |
| 13796 | switch (OpNum) { |
| 13797 | case 2: |
| 13798 | // op: Ii |
| 13799 | return 8; |
| 13800 | case 0: |
| 13801 | // op: Pv4 |
| 13802 | return 11; |
| 13803 | case 1: |
| 13804 | // op: Rt32 |
| 13805 | return 16; |
| 13806 | case 3: |
| 13807 | // op: Vs32 |
| 13808 | return 0; |
| 13809 | } |
| 13810 | break; |
| 13811 | } |
| 13812 | case Hexagon::V6_zLd_pred_ai: { |
| 13813 | switch (OpNum) { |
| 13814 | case 2: |
| 13815 | // op: Ii |
| 13816 | return 8; |
| 13817 | case 0: |
| 13818 | // op: Pv4 |
| 13819 | return 11; |
| 13820 | case 1: |
| 13821 | // op: Rt32 |
| 13822 | return 16; |
| 13823 | } |
| 13824 | break; |
| 13825 | } |
| 13826 | case Hexagon::V6_vS32b_nqpred_ai: |
| 13827 | case Hexagon::V6_vS32b_nt_nqpred_ai: |
| 13828 | case Hexagon::V6_vS32b_nt_qpred_ai: |
| 13829 | case Hexagon::V6_vS32b_qpred_ai: { |
| 13830 | switch (OpNum) { |
| 13831 | case 2: |
| 13832 | // op: Ii |
| 13833 | return 8; |
| 13834 | case 0: |
| 13835 | // op: Qv4 |
| 13836 | return 11; |
| 13837 | case 1: |
| 13838 | // op: Rt32 |
| 13839 | return 16; |
| 13840 | case 3: |
| 13841 | // op: Vs32 |
| 13842 | return 0; |
| 13843 | } |
| 13844 | break; |
| 13845 | } |
| 13846 | case Hexagon::V6_vS32b_srls_pi: |
| 13847 | case Hexagon::V6_zLd_pi: { |
| 13848 | switch (OpNum) { |
| 13849 | case 2: |
| 13850 | // op: Ii |
| 13851 | return 8; |
| 13852 | case 0: |
| 13853 | // op: Rx32 |
| 13854 | return 16; |
| 13855 | } |
| 13856 | break; |
| 13857 | } |
| 13858 | case Hexagon::L4_ploadrbf_abs: |
| 13859 | case Hexagon::L4_ploadrbfnew_abs: |
| 13860 | case Hexagon::L4_ploadrbt_abs: |
| 13861 | case Hexagon::L4_ploadrbtnew_abs: |
| 13862 | case Hexagon::L4_ploadrhf_abs: |
| 13863 | case Hexagon::L4_ploadrhfnew_abs: |
| 13864 | case Hexagon::L4_ploadrht_abs: |
| 13865 | case Hexagon::L4_ploadrhtnew_abs: |
| 13866 | case Hexagon::L4_ploadrif_abs: |
| 13867 | case Hexagon::L4_ploadrifnew_abs: |
| 13868 | case Hexagon::L4_ploadrit_abs: |
| 13869 | case Hexagon::L4_ploadritnew_abs: |
| 13870 | case Hexagon::L4_ploadrubf_abs: |
| 13871 | case Hexagon::L4_ploadrubfnew_abs: |
| 13872 | case Hexagon::L4_ploadrubt_abs: |
| 13873 | case Hexagon::L4_ploadrubtnew_abs: |
| 13874 | case Hexagon::L4_ploadruhf_abs: |
| 13875 | case Hexagon::L4_ploadruhfnew_abs: |
| 13876 | case Hexagon::L4_ploadruht_abs: |
| 13877 | case Hexagon::L4_ploadruhtnew_abs: { |
| 13878 | switch (OpNum) { |
| 13879 | case 2: |
| 13880 | // op: Ii |
| 13881 | return 8; |
| 13882 | case 1: |
| 13883 | // op: Pt4 |
| 13884 | return 9; |
| 13885 | case 0: |
| 13886 | // op: Rd32 |
| 13887 | return 0; |
| 13888 | } |
| 13889 | break; |
| 13890 | } |
| 13891 | case Hexagon::L4_ploadrdf_abs: |
| 13892 | case Hexagon::L4_ploadrdfnew_abs: |
| 13893 | case Hexagon::L4_ploadrdt_abs: |
| 13894 | case Hexagon::L4_ploadrdtnew_abs: { |
| 13895 | switch (OpNum) { |
| 13896 | case 2: |
| 13897 | // op: Ii |
| 13898 | return 8; |
| 13899 | case 1: |
| 13900 | // op: Pt4 |
| 13901 | return 9; |
| 13902 | case 0: |
| 13903 | // op: Rdd32 |
| 13904 | return 0; |
| 13905 | } |
| 13906 | break; |
| 13907 | } |
| 13908 | case Hexagon::SL1_loadri_io: |
| 13909 | case Hexagon::SL1_loadrub_io: |
| 13910 | case Hexagon::SL2_loadrb_io: |
| 13911 | case Hexagon::SL2_loadrh_io: |
| 13912 | case Hexagon::SL2_loadruh_io: { |
| 13913 | switch (OpNum) { |
| 13914 | case 2: |
| 13915 | // op: Ii |
| 13916 | return 8; |
| 13917 | case 1: |
| 13918 | // op: Rs16 |
| 13919 | return 4; |
| 13920 | case 0: |
| 13921 | // op: Rd16 |
| 13922 | return 0; |
| 13923 | } |
| 13924 | break; |
| 13925 | } |
| 13926 | case Hexagon::C2_bitsclri: |
| 13927 | case Hexagon::C4_nbitsclri: |
| 13928 | case Hexagon::F2_sfclass: |
| 13929 | case Hexagon::S2_tstbit_i: |
| 13930 | case Hexagon::S4_ntstbit_i: { |
| 13931 | switch (OpNum) { |
| 13932 | case 2: |
| 13933 | // op: Ii |
| 13934 | return 8; |
| 13935 | case 1: |
| 13936 | // op: Rs32 |
| 13937 | return 16; |
| 13938 | case 0: |
| 13939 | // op: Pd4 |
| 13940 | return 0; |
| 13941 | } |
| 13942 | break; |
| 13943 | } |
| 13944 | case Hexagon::A4_cround_ri: |
| 13945 | case Hexagon::A4_round_ri: |
| 13946 | case Hexagon::A4_round_ri_sat: |
| 13947 | case Hexagon::A7_clip: |
| 13948 | case Hexagon::S2_asl_i_r: |
| 13949 | case Hexagon::S2_asl_i_r_sat: |
| 13950 | case Hexagon::S2_asr_i_r: |
| 13951 | case Hexagon::S2_asr_i_r_rnd: |
| 13952 | case Hexagon::S2_clrbit_i: |
| 13953 | case Hexagon::S2_lsr_i_r: |
| 13954 | case Hexagon::S2_setbit_i: |
| 13955 | case Hexagon::S2_togglebit_i: |
| 13956 | case Hexagon::S4_clbaddi: |
| 13957 | case Hexagon::S6_rol_i_r: { |
| 13958 | switch (OpNum) { |
| 13959 | case 2: |
| 13960 | // op: Ii |
| 13961 | return 8; |
| 13962 | case 1: |
| 13963 | // op: Rs32 |
| 13964 | return 16; |
| 13965 | case 0: |
| 13966 | // op: Rd32 |
| 13967 | return 0; |
| 13968 | } |
| 13969 | break; |
| 13970 | } |
| 13971 | case Hexagon::A4_bitspliti: { |
| 13972 | switch (OpNum) { |
| 13973 | case 2: |
| 13974 | // op: Ii |
| 13975 | return 8; |
| 13976 | case 1: |
| 13977 | // op: Rs32 |
| 13978 | return 16; |
| 13979 | case 0: |
| 13980 | // op: Rdd32 |
| 13981 | return 0; |
| 13982 | } |
| 13983 | break; |
| 13984 | } |
| 13985 | case Hexagon::S2_asr_i_svw_trun: |
| 13986 | case Hexagon::S4_clbpaddi: |
| 13987 | case Hexagon::S5_asrhub_rnd_sat: |
| 13988 | case Hexagon::S5_asrhub_sat: { |
| 13989 | switch (OpNum) { |
| 13990 | case 2: |
| 13991 | // op: Ii |
| 13992 | return 8; |
| 13993 | case 1: |
| 13994 | // op: Rss32 |
| 13995 | return 16; |
| 13996 | case 0: |
| 13997 | // op: Rd32 |
| 13998 | return 0; |
| 13999 | } |
| 14000 | break; |
| 14001 | } |
| 14002 | case Hexagon::A7_croundd_ri: |
| 14003 | case Hexagon::A7_vclip: |
| 14004 | case Hexagon::S2_asl_i_p: |
| 14005 | case Hexagon::S2_asl_i_vh: |
| 14006 | case Hexagon::S2_asl_i_vw: |
| 14007 | case Hexagon::S2_asr_i_p: |
| 14008 | case Hexagon::S2_asr_i_p_rnd: |
| 14009 | case Hexagon::S2_asr_i_vh: |
| 14010 | case Hexagon::S2_asr_i_vw: |
| 14011 | case Hexagon::S2_lsr_i_p: |
| 14012 | case Hexagon::S2_lsr_i_vh: |
| 14013 | case Hexagon::S2_lsr_i_vw: |
| 14014 | case Hexagon::S5_vasrhrnd: |
| 14015 | case Hexagon::S6_rol_i_p: { |
| 14016 | switch (OpNum) { |
| 14017 | case 2: |
| 14018 | // op: Ii |
| 14019 | return 8; |
| 14020 | case 1: |
| 14021 | // op: Rss32 |
| 14022 | return 16; |
| 14023 | case 0: |
| 14024 | // op: Rdd32 |
| 14025 | return 0; |
| 14026 | } |
| 14027 | break; |
| 14028 | } |
| 14029 | case Hexagon::V6_vL32Ub_ai: |
| 14030 | case Hexagon::V6_vL32b_ai: |
| 14031 | case Hexagon::V6_vL32b_cur_ai: |
| 14032 | case Hexagon::V6_vL32b_nt_ai: |
| 14033 | case Hexagon::V6_vL32b_nt_cur_ai: |
| 14034 | case Hexagon::V6_vL32b_nt_tmp_ai: |
| 14035 | case Hexagon::V6_vL32b_tmp_ai: { |
| 14036 | switch (OpNum) { |
| 14037 | case 2: |
| 14038 | // op: Ii |
| 14039 | return 8; |
| 14040 | case 1: |
| 14041 | // op: Rt32 |
| 14042 | return 16; |
| 14043 | case 0: |
| 14044 | // op: Vd32 |
| 14045 | return 0; |
| 14046 | } |
| 14047 | break; |
| 14048 | } |
| 14049 | case Hexagon::S2_extractu: |
| 14050 | case Hexagon::S4_extract: { |
| 14051 | switch (OpNum) { |
| 14052 | case 2: |
| 14053 | // op: Ii |
| 14054 | return 8; |
| 14055 | case 3: |
| 14056 | // op: II |
| 14057 | return 5; |
| 14058 | case 1: |
| 14059 | // op: Rs32 |
| 14060 | return 16; |
| 14061 | case 0: |
| 14062 | // op: Rd32 |
| 14063 | return 0; |
| 14064 | } |
| 14065 | break; |
| 14066 | } |
| 14067 | case Hexagon::S2_extractup: |
| 14068 | case Hexagon::S4_extractp: { |
| 14069 | switch (OpNum) { |
| 14070 | case 2: |
| 14071 | // op: Ii |
| 14072 | return 8; |
| 14073 | case 3: |
| 14074 | // op: II |
| 14075 | return 5; |
| 14076 | case 1: |
| 14077 | // op: Rss32 |
| 14078 | return 16; |
| 14079 | case 0: |
| 14080 | // op: Rdd32 |
| 14081 | return 0; |
| 14082 | } |
| 14083 | break; |
| 14084 | } |
| 14085 | case Hexagon::V6_vS32b_new_pi: |
| 14086 | case Hexagon::V6_vS32b_nt_new_pi: { |
| 14087 | switch (OpNum) { |
| 14088 | case 2: |
| 14089 | // op: Ii |
| 14090 | return 8; |
| 14091 | case 3: |
| 14092 | // op: Os8 |
| 14093 | return 0; |
| 14094 | case 0: |
| 14095 | // op: Rx32 |
| 14096 | return 16; |
| 14097 | } |
| 14098 | break; |
| 14099 | } |
| 14100 | case Hexagon::V6_vS32Ub_pi: |
| 14101 | case Hexagon::V6_vS32b_nt_pi: |
| 14102 | case Hexagon::V6_vS32b_pi: { |
| 14103 | switch (OpNum) { |
| 14104 | case 2: |
| 14105 | // op: Ii |
| 14106 | return 8; |
| 14107 | case 3: |
| 14108 | // op: Vs32 |
| 14109 | return 0; |
| 14110 | case 0: |
| 14111 | // op: Rx32 |
| 14112 | return 16; |
| 14113 | } |
| 14114 | break; |
| 14115 | } |
| 14116 | case Hexagon::V6_vS32b_srls_ppu: |
| 14117 | case Hexagon::V6_zLd_ppu: { |
| 14118 | switch (OpNum) { |
| 14119 | case 2: |
| 14120 | // op: Mu2 |
| 14121 | return 13; |
| 14122 | case 0: |
| 14123 | // op: Rx32 |
| 14124 | return 16; |
| 14125 | } |
| 14126 | break; |
| 14127 | } |
| 14128 | case Hexagon::S2_storerbnew_pbr: |
| 14129 | case Hexagon::S2_storerbnew_pcr: |
| 14130 | case Hexagon::S2_storerbnew_pr: |
| 14131 | case Hexagon::S2_storerhnew_pbr: |
| 14132 | case Hexagon::S2_storerhnew_pcr: |
| 14133 | case Hexagon::S2_storerhnew_pr: |
| 14134 | case Hexagon::S2_storerinew_pbr: |
| 14135 | case Hexagon::S2_storerinew_pcr: |
| 14136 | case Hexagon::S2_storerinew_pr: { |
| 14137 | switch (OpNum) { |
| 14138 | case 2: |
| 14139 | // op: Mu2 |
| 14140 | return 13; |
| 14141 | case 3: |
| 14142 | // op: Nt8 |
| 14143 | return 8; |
| 14144 | case 0: |
| 14145 | // op: Rx32 |
| 14146 | return 16; |
| 14147 | } |
| 14148 | break; |
| 14149 | } |
| 14150 | case Hexagon::V6_vS32b_new_ppu: |
| 14151 | case Hexagon::V6_vS32b_nt_new_ppu: { |
| 14152 | switch (OpNum) { |
| 14153 | case 2: |
| 14154 | // op: Mu2 |
| 14155 | return 13; |
| 14156 | case 3: |
| 14157 | // op: Os8 |
| 14158 | return 0; |
| 14159 | case 0: |
| 14160 | // op: Rx32 |
| 14161 | return 16; |
| 14162 | } |
| 14163 | break; |
| 14164 | } |
| 14165 | case Hexagon::S2_storerb_pbr: |
| 14166 | case Hexagon::S2_storerb_pcr: |
| 14167 | case Hexagon::S2_storerb_pr: |
| 14168 | case Hexagon::S2_storerf_pbr: |
| 14169 | case Hexagon::S2_storerf_pcr: |
| 14170 | case Hexagon::S2_storerf_pr: |
| 14171 | case Hexagon::S2_storerh_pbr: |
| 14172 | case Hexagon::S2_storerh_pcr: |
| 14173 | case Hexagon::S2_storerh_pr: |
| 14174 | case Hexagon::S2_storeri_pbr: |
| 14175 | case Hexagon::S2_storeri_pcr: |
| 14176 | case Hexagon::S2_storeri_pr: { |
| 14177 | switch (OpNum) { |
| 14178 | case 2: |
| 14179 | // op: Mu2 |
| 14180 | return 13; |
| 14181 | case 3: |
| 14182 | // op: Rt32 |
| 14183 | return 8; |
| 14184 | case 0: |
| 14185 | // op: Rx32 |
| 14186 | return 16; |
| 14187 | } |
| 14188 | break; |
| 14189 | } |
| 14190 | case Hexagon::S2_storerd_pbr: |
| 14191 | case Hexagon::S2_storerd_pcr: |
| 14192 | case Hexagon::S2_storerd_pr: { |
| 14193 | switch (OpNum) { |
| 14194 | case 2: |
| 14195 | // op: Mu2 |
| 14196 | return 13; |
| 14197 | case 3: |
| 14198 | // op: Rtt32 |
| 14199 | return 8; |
| 14200 | case 0: |
| 14201 | // op: Rx32 |
| 14202 | return 16; |
| 14203 | } |
| 14204 | break; |
| 14205 | } |
| 14206 | case Hexagon::V6_vS32Ub_ppu: |
| 14207 | case Hexagon::V6_vS32b_nt_ppu: |
| 14208 | case Hexagon::V6_vS32b_ppu: { |
| 14209 | switch (OpNum) { |
| 14210 | case 2: |
| 14211 | // op: Mu2 |
| 14212 | return 13; |
| 14213 | case 3: |
| 14214 | // op: Vs32 |
| 14215 | return 0; |
| 14216 | case 0: |
| 14217 | // op: Rx32 |
| 14218 | return 16; |
| 14219 | } |
| 14220 | break; |
| 14221 | } |
| 14222 | case Hexagon::V6_vL32b_cur_npred_ppu: |
| 14223 | case Hexagon::V6_vL32b_cur_pred_ppu: |
| 14224 | case Hexagon::V6_vL32b_npred_ppu: |
| 14225 | case Hexagon::V6_vL32b_nt_cur_npred_ppu: |
| 14226 | case Hexagon::V6_vL32b_nt_cur_pred_ppu: |
| 14227 | case Hexagon::V6_vL32b_nt_npred_ppu: |
| 14228 | case Hexagon::V6_vL32b_nt_pred_ppu: |
| 14229 | case Hexagon::V6_vL32b_nt_tmp_npred_ppu: |
| 14230 | case Hexagon::V6_vL32b_nt_tmp_pred_ppu: |
| 14231 | case Hexagon::V6_vL32b_pred_ppu: |
| 14232 | case Hexagon::V6_vL32b_tmp_npred_ppu: |
| 14233 | case Hexagon::V6_vL32b_tmp_pred_ppu: { |
| 14234 | switch (OpNum) { |
| 14235 | case 2: |
| 14236 | // op: Pv4 |
| 14237 | return 11; |
| 14238 | case 4: |
| 14239 | // op: Mu2 |
| 14240 | return 13; |
| 14241 | case 0: |
| 14242 | // op: Vd32 |
| 14243 | return 0; |
| 14244 | case 1: |
| 14245 | // op: Rx32 |
| 14246 | return 16; |
| 14247 | } |
| 14248 | break; |
| 14249 | } |
| 14250 | case Hexagon::V6_vandnqrt_acc: |
| 14251 | case Hexagon::V6_vandqrt_acc: { |
| 14252 | switch (OpNum) { |
| 14253 | case 2: |
| 14254 | // op: Qu4 |
| 14255 | return 8; |
| 14256 | case 3: |
| 14257 | // op: Rt32 |
| 14258 | return 16; |
| 14259 | case 0: |
| 14260 | // op: Vx32 |
| 14261 | return 0; |
| 14262 | } |
| 14263 | break; |
| 14264 | } |
| 14265 | case Hexagon::SA1_addrx: { |
| 14266 | switch (OpNum) { |
| 14267 | case 2: |
| 14268 | // op: Rs16 |
| 14269 | return 4; |
| 14270 | case 0: |
| 14271 | // op: Rx16 |
| 14272 | return 0; |
| 14273 | } |
| 14274 | break; |
| 14275 | } |
| 14276 | case Hexagon::F2_sfinvsqrta: { |
| 14277 | switch (OpNum) { |
| 14278 | case 2: |
| 14279 | // op: Rs32 |
| 14280 | return 16; |
| 14281 | case 0: |
| 14282 | // op: Rd32 |
| 14283 | return 0; |
| 14284 | case 1: |
| 14285 | // op: Pe4 |
| 14286 | return 5; |
| 14287 | } |
| 14288 | break; |
| 14289 | } |
| 14290 | case Hexagon::F2_sfrecipa: { |
| 14291 | switch (OpNum) { |
| 14292 | case 2: |
| 14293 | // op: Rs32 |
| 14294 | return 16; |
| 14295 | case 3: |
| 14296 | // op: Rt32 |
| 14297 | return 8; |
| 14298 | case 0: |
| 14299 | // op: Rd32 |
| 14300 | return 0; |
| 14301 | case 1: |
| 14302 | // op: Pe4 |
| 14303 | return 5; |
| 14304 | } |
| 14305 | break; |
| 14306 | } |
| 14307 | case Hexagon::F2_sffma: |
| 14308 | case Hexagon::F2_sffma_lib: |
| 14309 | case Hexagon::F2_sffms: |
| 14310 | case Hexagon::F2_sffms_lib: |
| 14311 | case Hexagon::M2_acci: |
| 14312 | case Hexagon::M2_maci: |
| 14313 | case Hexagon::M2_mnaci: |
| 14314 | case Hexagon::M2_mpy_acc_hh_s0: |
| 14315 | case Hexagon::M2_mpy_acc_hh_s1: |
| 14316 | case Hexagon::M2_mpy_acc_hl_s0: |
| 14317 | case Hexagon::M2_mpy_acc_hl_s1: |
| 14318 | case Hexagon::M2_mpy_acc_lh_s0: |
| 14319 | case Hexagon::M2_mpy_acc_lh_s1: |
| 14320 | case Hexagon::M2_mpy_acc_ll_s0: |
| 14321 | case Hexagon::M2_mpy_acc_ll_s1: |
| 14322 | case Hexagon::M2_mpy_acc_sat_hh_s0: |
| 14323 | case Hexagon::M2_mpy_acc_sat_hh_s1: |
| 14324 | case Hexagon::M2_mpy_acc_sat_hl_s0: |
| 14325 | case Hexagon::M2_mpy_acc_sat_hl_s1: |
| 14326 | case Hexagon::M2_mpy_acc_sat_lh_s0: |
| 14327 | case Hexagon::M2_mpy_acc_sat_lh_s1: |
| 14328 | case Hexagon::M2_mpy_acc_sat_ll_s0: |
| 14329 | case Hexagon::M2_mpy_acc_sat_ll_s1: |
| 14330 | case Hexagon::M2_mpy_nac_hh_s0: |
| 14331 | case Hexagon::M2_mpy_nac_hh_s1: |
| 14332 | case Hexagon::M2_mpy_nac_hl_s0: |
| 14333 | case Hexagon::M2_mpy_nac_hl_s1: |
| 14334 | case Hexagon::M2_mpy_nac_lh_s0: |
| 14335 | case Hexagon::M2_mpy_nac_lh_s1: |
| 14336 | case Hexagon::M2_mpy_nac_ll_s0: |
| 14337 | case Hexagon::M2_mpy_nac_ll_s1: |
| 14338 | case Hexagon::M2_mpy_nac_sat_hh_s0: |
| 14339 | case Hexagon::M2_mpy_nac_sat_hh_s1: |
| 14340 | case Hexagon::M2_mpy_nac_sat_hl_s0: |
| 14341 | case Hexagon::M2_mpy_nac_sat_hl_s1: |
| 14342 | case Hexagon::M2_mpy_nac_sat_lh_s0: |
| 14343 | case Hexagon::M2_mpy_nac_sat_lh_s1: |
| 14344 | case Hexagon::M2_mpy_nac_sat_ll_s0: |
| 14345 | case Hexagon::M2_mpy_nac_sat_ll_s1: |
| 14346 | case Hexagon::M2_mpyu_acc_hh_s0: |
| 14347 | case Hexagon::M2_mpyu_acc_hh_s1: |
| 14348 | case Hexagon::M2_mpyu_acc_hl_s0: |
| 14349 | case Hexagon::M2_mpyu_acc_hl_s1: |
| 14350 | case Hexagon::M2_mpyu_acc_lh_s0: |
| 14351 | case Hexagon::M2_mpyu_acc_lh_s1: |
| 14352 | case Hexagon::M2_mpyu_acc_ll_s0: |
| 14353 | case Hexagon::M2_mpyu_acc_ll_s1: |
| 14354 | case Hexagon::M2_mpyu_nac_hh_s0: |
| 14355 | case Hexagon::M2_mpyu_nac_hh_s1: |
| 14356 | case Hexagon::M2_mpyu_nac_hl_s0: |
| 14357 | case Hexagon::M2_mpyu_nac_hl_s1: |
| 14358 | case Hexagon::M2_mpyu_nac_lh_s0: |
| 14359 | case Hexagon::M2_mpyu_nac_lh_s1: |
| 14360 | case Hexagon::M2_mpyu_nac_ll_s0: |
| 14361 | case Hexagon::M2_mpyu_nac_ll_s1: |
| 14362 | case Hexagon::M2_nacci: |
| 14363 | case Hexagon::M2_xor_xacc: |
| 14364 | case Hexagon::M4_and_and: |
| 14365 | case Hexagon::M4_and_andn: |
| 14366 | case Hexagon::M4_and_or: |
| 14367 | case Hexagon::M4_and_xor: |
| 14368 | case Hexagon::M4_mac_up_s1_sat: |
| 14369 | case Hexagon::M4_nac_up_s1_sat: |
| 14370 | case Hexagon::M4_or_and: |
| 14371 | case Hexagon::M4_or_andn: |
| 14372 | case Hexagon::M4_or_or: |
| 14373 | case Hexagon::M4_or_xor: |
| 14374 | case Hexagon::M4_xor_and: |
| 14375 | case Hexagon::M4_xor_andn: |
| 14376 | case Hexagon::M4_xor_or: |
| 14377 | case Hexagon::S2_asl_r_r_acc: |
| 14378 | case Hexagon::S2_asl_r_r_and: |
| 14379 | case Hexagon::S2_asl_r_r_nac: |
| 14380 | case Hexagon::S2_asl_r_r_or: |
| 14381 | case Hexagon::S2_asr_r_r_acc: |
| 14382 | case Hexagon::S2_asr_r_r_and: |
| 14383 | case Hexagon::S2_asr_r_r_nac: |
| 14384 | case Hexagon::S2_asr_r_r_or: |
| 14385 | case Hexagon::S2_lsl_r_r_acc: |
| 14386 | case Hexagon::S2_lsl_r_r_and: |
| 14387 | case Hexagon::S2_lsl_r_r_nac: |
| 14388 | case Hexagon::S2_lsl_r_r_or: |
| 14389 | case Hexagon::S2_lsr_r_r_acc: |
| 14390 | case Hexagon::S2_lsr_r_r_and: |
| 14391 | case Hexagon::S2_lsr_r_r_nac: |
| 14392 | case Hexagon::S2_lsr_r_r_or: { |
| 14393 | switch (OpNum) { |
| 14394 | case 2: |
| 14395 | // op: Rs32 |
| 14396 | return 16; |
| 14397 | case 3: |
| 14398 | // op: Rt32 |
| 14399 | return 8; |
| 14400 | case 0: |
| 14401 | // op: Rx32 |
| 14402 | return 0; |
| 14403 | } |
| 14404 | break; |
| 14405 | } |
| 14406 | case Hexagon::M2_cmaci_s0: |
| 14407 | case Hexagon::M2_cmacr_s0: |
| 14408 | case Hexagon::M2_cmacs_s0: |
| 14409 | case Hexagon::M2_cmacs_s1: |
| 14410 | case Hexagon::M2_cmacsc_s0: |
| 14411 | case Hexagon::M2_cmacsc_s1: |
| 14412 | case Hexagon::M2_cnacs_s0: |
| 14413 | case Hexagon::M2_cnacs_s1: |
| 14414 | case Hexagon::M2_cnacsc_s0: |
| 14415 | case Hexagon::M2_cnacsc_s1: |
| 14416 | case Hexagon::M2_dpmpyss_acc_s0: |
| 14417 | case Hexagon::M2_dpmpyss_nac_s0: |
| 14418 | case Hexagon::M2_dpmpyuu_acc_s0: |
| 14419 | case Hexagon::M2_dpmpyuu_nac_s0: |
| 14420 | case Hexagon::M2_mpyd_acc_hh_s0: |
| 14421 | case Hexagon::M2_mpyd_acc_hh_s1: |
| 14422 | case Hexagon::M2_mpyd_acc_hl_s0: |
| 14423 | case Hexagon::M2_mpyd_acc_hl_s1: |
| 14424 | case Hexagon::M2_mpyd_acc_lh_s0: |
| 14425 | case Hexagon::M2_mpyd_acc_lh_s1: |
| 14426 | case Hexagon::M2_mpyd_acc_ll_s0: |
| 14427 | case Hexagon::M2_mpyd_acc_ll_s1: |
| 14428 | case Hexagon::M2_mpyd_nac_hh_s0: |
| 14429 | case Hexagon::M2_mpyd_nac_hh_s1: |
| 14430 | case Hexagon::M2_mpyd_nac_hl_s0: |
| 14431 | case Hexagon::M2_mpyd_nac_hl_s1: |
| 14432 | case Hexagon::M2_mpyd_nac_lh_s0: |
| 14433 | case Hexagon::M2_mpyd_nac_lh_s1: |
| 14434 | case Hexagon::M2_mpyd_nac_ll_s0: |
| 14435 | case Hexagon::M2_mpyd_nac_ll_s1: |
| 14436 | case Hexagon::M2_mpyud_acc_hh_s0: |
| 14437 | case Hexagon::M2_mpyud_acc_hh_s1: |
| 14438 | case Hexagon::M2_mpyud_acc_hl_s0: |
| 14439 | case Hexagon::M2_mpyud_acc_hl_s1: |
| 14440 | case Hexagon::M2_mpyud_acc_lh_s0: |
| 14441 | case Hexagon::M2_mpyud_acc_lh_s1: |
| 14442 | case Hexagon::M2_mpyud_acc_ll_s0: |
| 14443 | case Hexagon::M2_mpyud_acc_ll_s1: |
| 14444 | case Hexagon::M2_mpyud_nac_hh_s0: |
| 14445 | case Hexagon::M2_mpyud_nac_hh_s1: |
| 14446 | case Hexagon::M2_mpyud_nac_hl_s0: |
| 14447 | case Hexagon::M2_mpyud_nac_hl_s1: |
| 14448 | case Hexagon::M2_mpyud_nac_lh_s0: |
| 14449 | case Hexagon::M2_mpyud_nac_lh_s1: |
| 14450 | case Hexagon::M2_mpyud_nac_ll_s0: |
| 14451 | case Hexagon::M2_mpyud_nac_ll_s1: |
| 14452 | case Hexagon::M2_vmac2: |
| 14453 | case Hexagon::M2_vmac2s_s0: |
| 14454 | case Hexagon::M2_vmac2s_s1: |
| 14455 | case Hexagon::M2_vmac2su_s0: |
| 14456 | case Hexagon::M2_vmac2su_s1: |
| 14457 | case Hexagon::M4_pmpyw_acc: |
| 14458 | case Hexagon::M4_vpmpyh_acc: |
| 14459 | case Hexagon::M5_vmacbsu: |
| 14460 | case Hexagon::M5_vmacbuu: { |
| 14461 | switch (OpNum) { |
| 14462 | case 2: |
| 14463 | // op: Rs32 |
| 14464 | return 16; |
| 14465 | case 3: |
| 14466 | // op: Rt32 |
| 14467 | return 8; |
| 14468 | case 0: |
| 14469 | // op: Rxx32 |
| 14470 | return 0; |
| 14471 | } |
| 14472 | break; |
| 14473 | } |
| 14474 | case Hexagon::F2_sffma_sc: { |
| 14475 | switch (OpNum) { |
| 14476 | case 2: |
| 14477 | // op: Rs32 |
| 14478 | return 16; |
| 14479 | case 3: |
| 14480 | // op: Rt32 |
| 14481 | return 8; |
| 14482 | case 4: |
| 14483 | // op: Pu4 |
| 14484 | return 5; |
| 14485 | case 0: |
| 14486 | // op: Rx32 |
| 14487 | return 0; |
| 14488 | } |
| 14489 | break; |
| 14490 | } |
| 14491 | case Hexagon::S2_insert_rp: { |
| 14492 | switch (OpNum) { |
| 14493 | case 2: |
| 14494 | // op: Rs32 |
| 14495 | return 16; |
| 14496 | case 3: |
| 14497 | // op: Rtt32 |
| 14498 | return 8; |
| 14499 | case 0: |
| 14500 | // op: Rx32 |
| 14501 | return 0; |
| 14502 | } |
| 14503 | break; |
| 14504 | } |
| 14505 | case Hexagon::S2_asl_r_p_acc: |
| 14506 | case Hexagon::S2_asl_r_p_and: |
| 14507 | case Hexagon::S2_asl_r_p_nac: |
| 14508 | case Hexagon::S2_asl_r_p_or: |
| 14509 | case Hexagon::S2_asl_r_p_xor: |
| 14510 | case Hexagon::S2_asr_r_p_acc: |
| 14511 | case Hexagon::S2_asr_r_p_and: |
| 14512 | case Hexagon::S2_asr_r_p_nac: |
| 14513 | case Hexagon::S2_asr_r_p_or: |
| 14514 | case Hexagon::S2_asr_r_p_xor: |
| 14515 | case Hexagon::S2_lsl_r_p_acc: |
| 14516 | case Hexagon::S2_lsl_r_p_and: |
| 14517 | case Hexagon::S2_lsl_r_p_nac: |
| 14518 | case Hexagon::S2_lsl_r_p_or: |
| 14519 | case Hexagon::S2_lsl_r_p_xor: |
| 14520 | case Hexagon::S2_lsr_r_p_acc: |
| 14521 | case Hexagon::S2_lsr_r_p_and: |
| 14522 | case Hexagon::S2_lsr_r_p_nac: |
| 14523 | case Hexagon::S2_lsr_r_p_or: |
| 14524 | case Hexagon::S2_lsr_r_p_xor: |
| 14525 | case Hexagon::S2_vrcnegh: { |
| 14526 | switch (OpNum) { |
| 14527 | case 2: |
| 14528 | // op: Rss32 |
| 14529 | return 16; |
| 14530 | case 3: |
| 14531 | // op: Rt32 |
| 14532 | return 8; |
| 14533 | case 0: |
| 14534 | // op: Rxx32 |
| 14535 | return 0; |
| 14536 | } |
| 14537 | break; |
| 14538 | } |
| 14539 | case Hexagon::A4_addp_c: |
| 14540 | case Hexagon::A4_subp_c: { |
| 14541 | switch (OpNum) { |
| 14542 | case 2: |
| 14543 | // op: Rss32 |
| 14544 | return 16; |
| 14545 | case 3: |
| 14546 | // op: Rtt32 |
| 14547 | return 8; |
| 14548 | case 0: |
| 14549 | // op: Rdd32 |
| 14550 | return 0; |
| 14551 | case 1: |
| 14552 | // op: Px4 |
| 14553 | return 5; |
| 14554 | } |
| 14555 | break; |
| 14556 | } |
| 14557 | case Hexagon::A2_vraddub_acc: |
| 14558 | case Hexagon::A2_vrsadub_acc: |
| 14559 | case Hexagon::F2_dfmpyhh: |
| 14560 | case Hexagon::F2_dfmpylh: |
| 14561 | case Hexagon::M2_mmachs_rs0: |
| 14562 | case Hexagon::M2_mmachs_rs1: |
| 14563 | case Hexagon::M2_mmachs_s0: |
| 14564 | case Hexagon::M2_mmachs_s1: |
| 14565 | case Hexagon::M2_mmacls_rs0: |
| 14566 | case Hexagon::M2_mmacls_rs1: |
| 14567 | case Hexagon::M2_mmacls_s0: |
| 14568 | case Hexagon::M2_mmacls_s1: |
| 14569 | case Hexagon::M2_mmacuhs_rs0: |
| 14570 | case Hexagon::M2_mmacuhs_rs1: |
| 14571 | case Hexagon::M2_mmacuhs_s0: |
| 14572 | case Hexagon::M2_mmacuhs_s1: |
| 14573 | case Hexagon::M2_mmaculs_rs0: |
| 14574 | case Hexagon::M2_mmaculs_rs1: |
| 14575 | case Hexagon::M2_mmaculs_s0: |
| 14576 | case Hexagon::M2_mmaculs_s1: |
| 14577 | case Hexagon::M2_vcmac_s0_sat_i: |
| 14578 | case Hexagon::M2_vcmac_s0_sat_r: |
| 14579 | case Hexagon::M2_vdmacs_s0: |
| 14580 | case Hexagon::M2_vdmacs_s1: |
| 14581 | case Hexagon::M2_vmac2es: |
| 14582 | case Hexagon::M2_vmac2es_s0: |
| 14583 | case Hexagon::M2_vmac2es_s1: |
| 14584 | case Hexagon::M2_vrcmaci_s0: |
| 14585 | case Hexagon::M2_vrcmaci_s0c: |
| 14586 | case Hexagon::M2_vrcmacr_s0: |
| 14587 | case Hexagon::M2_vrcmacr_s0c: |
| 14588 | case Hexagon::M2_vrcmpys_acc_s1_h: |
| 14589 | case Hexagon::M2_vrcmpys_acc_s1_l: |
| 14590 | case Hexagon::M2_vrmac_s0: |
| 14591 | case Hexagon::M4_vrmpyeh_acc_s0: |
| 14592 | case Hexagon::M4_vrmpyeh_acc_s1: |
| 14593 | case Hexagon::M4_vrmpyoh_acc_s0: |
| 14594 | case Hexagon::M4_vrmpyoh_acc_s1: |
| 14595 | case Hexagon::M4_xor_xacc: |
| 14596 | case Hexagon::M5_vdmacbsu: |
| 14597 | case Hexagon::M5_vrmacbsu: |
| 14598 | case Hexagon::M5_vrmacbuu: |
| 14599 | case Hexagon::M7_dcmpyiw_acc: |
| 14600 | case Hexagon::M7_dcmpyiwc_acc: |
| 14601 | case Hexagon::M7_dcmpyrw_acc: |
| 14602 | case Hexagon::M7_dcmpyrwc_acc: |
| 14603 | case Hexagon::S2_insertp_rp: { |
| 14604 | switch (OpNum) { |
| 14605 | case 2: |
| 14606 | // op: Rss32 |
| 14607 | return 16; |
| 14608 | case 3: |
| 14609 | // op: Rtt32 |
| 14610 | return 8; |
| 14611 | case 0: |
| 14612 | // op: Rxx32 |
| 14613 | return 0; |
| 14614 | } |
| 14615 | break; |
| 14616 | } |
| 14617 | case Hexagon::A4_vrmaxh: |
| 14618 | case Hexagon::A4_vrmaxuh: |
| 14619 | case Hexagon::A4_vrmaxuw: |
| 14620 | case Hexagon::A4_vrmaxw: |
| 14621 | case Hexagon::A4_vrminh: |
| 14622 | case Hexagon::A4_vrminuh: |
| 14623 | case Hexagon::A4_vrminuw: |
| 14624 | case Hexagon::A4_vrminw: { |
| 14625 | switch (OpNum) { |
| 14626 | case 2: |
| 14627 | // op: Rss32 |
| 14628 | return 16; |
| 14629 | case 3: |
| 14630 | // op: Ru32 |
| 14631 | return 0; |
| 14632 | case 0: |
| 14633 | // op: Rxx32 |
| 14634 | return 8; |
| 14635 | } |
| 14636 | break; |
| 14637 | } |
| 14638 | case Hexagon::V6_vinsertwr: { |
| 14639 | switch (OpNum) { |
| 14640 | case 2: |
| 14641 | // op: Rt32 |
| 14642 | return 16; |
| 14643 | case 0: |
| 14644 | // op: Vx32 |
| 14645 | return 0; |
| 14646 | } |
| 14647 | break; |
| 14648 | } |
| 14649 | case Hexagon::M2_subacc: { |
| 14650 | switch (OpNum) { |
| 14651 | case 2: |
| 14652 | // op: Rt32 |
| 14653 | return 8; |
| 14654 | case 3: |
| 14655 | // op: Rs32 |
| 14656 | return 16; |
| 14657 | case 0: |
| 14658 | // op: Rx32 |
| 14659 | return 0; |
| 14660 | } |
| 14661 | break; |
| 14662 | } |
| 14663 | case Hexagon::A6_vminub_RdP: { |
| 14664 | switch (OpNum) { |
| 14665 | case 2: |
| 14666 | // op: Rtt32 |
| 14667 | return 8; |
| 14668 | case 3: |
| 14669 | // op: Rss32 |
| 14670 | return 16; |
| 14671 | case 0: |
| 14672 | // op: Rdd32 |
| 14673 | return 0; |
| 14674 | case 1: |
| 14675 | // op: Pe4 |
| 14676 | return 5; |
| 14677 | } |
| 14678 | break; |
| 14679 | } |
| 14680 | case Hexagon::V6_vrmpyzbb_rx: |
| 14681 | case Hexagon::V6_vrmpyzbub_rx: |
| 14682 | case Hexagon::V6_vrmpyzcb_rx: |
| 14683 | case Hexagon::V6_vrmpyzcbs_rx: |
| 14684 | case Hexagon::V6_vrmpyznb_rx: { |
| 14685 | switch (OpNum) { |
| 14686 | case 2: |
| 14687 | // op: Vu32 |
| 14688 | return 8; |
| 14689 | case 0: |
| 14690 | // op: Vdddd32 |
| 14691 | return 0; |
| 14692 | case 1: |
| 14693 | // op: Rx8 |
| 14694 | return 16; |
| 14695 | } |
| 14696 | break; |
| 14697 | } |
| 14698 | case Hexagon::V6_vunpackob: |
| 14699 | case Hexagon::V6_vunpackoh: { |
| 14700 | switch (OpNum) { |
| 14701 | case 2: |
| 14702 | // op: Vu32 |
| 14703 | return 8; |
| 14704 | case 0: |
| 14705 | // op: Vxx32 |
| 14706 | return 0; |
| 14707 | } |
| 14708 | break; |
| 14709 | } |
| 14710 | case Hexagon::V6_vandvrt_acc: { |
| 14711 | switch (OpNum) { |
| 14712 | case 2: |
| 14713 | // op: Vu32 |
| 14714 | return 8; |
| 14715 | case 3: |
| 14716 | // op: Rt32 |
| 14717 | return 16; |
| 14718 | case 0: |
| 14719 | // op: Qx4 |
| 14720 | return 0; |
| 14721 | } |
| 14722 | break; |
| 14723 | } |
| 14724 | case Hexagon::V6_get_qfext_oracc: |
| 14725 | case Hexagon::V6_vaslh_acc: |
| 14726 | case Hexagon::V6_vaslw_acc: |
| 14727 | case Hexagon::V6_vasrh_acc: |
| 14728 | case Hexagon::V6_vasrw_acc: |
| 14729 | case Hexagon::V6_vdmpybus_acc: |
| 14730 | case Hexagon::V6_vdmpyhb_acc: |
| 14731 | case Hexagon::V6_vdmpyhsat_acc: |
| 14732 | case Hexagon::V6_vdmpyhsusat_acc: |
| 14733 | case Hexagon::V6_vmpyihb_acc: |
| 14734 | case Hexagon::V6_vmpyiwb_acc: |
| 14735 | case Hexagon::V6_vmpyiwh_acc: |
| 14736 | case Hexagon::V6_vmpyiwub_acc: |
| 14737 | case Hexagon::V6_vmpyuhe_acc: |
| 14738 | case Hexagon::V6_vrmpybus_acc: |
| 14739 | case Hexagon::V6_vrmpyub_acc: { |
| 14740 | switch (OpNum) { |
| 14741 | case 2: |
| 14742 | // op: Vu32 |
| 14743 | return 8; |
| 14744 | case 3: |
| 14745 | // op: Rt32 |
| 14746 | return 16; |
| 14747 | case 0: |
| 14748 | // op: Vx32 |
| 14749 | return 0; |
| 14750 | } |
| 14751 | break; |
| 14752 | } |
| 14753 | case Hexagon::V6_vmpybus_acc: |
| 14754 | case Hexagon::V6_vmpyh_acc: |
| 14755 | case Hexagon::V6_vmpyhsat_acc: |
| 14756 | case Hexagon::V6_vmpyub_acc: |
| 14757 | case Hexagon::V6_vmpyuh_acc: { |
| 14758 | switch (OpNum) { |
| 14759 | case 2: |
| 14760 | // op: Vu32 |
| 14761 | return 8; |
| 14762 | case 3: |
| 14763 | // op: Rt32 |
| 14764 | return 16; |
| 14765 | case 0: |
| 14766 | // op: Vxx32 |
| 14767 | return 0; |
| 14768 | } |
| 14769 | break; |
| 14770 | } |
| 14771 | case Hexagon::V6_vrmpyzbb_rt_acc: |
| 14772 | case Hexagon::V6_vrmpyzbub_rt_acc: |
| 14773 | case Hexagon::V6_vrmpyzcb_rt_acc: |
| 14774 | case Hexagon::V6_vrmpyzcbs_rt_acc: |
| 14775 | case Hexagon::V6_vrmpyznb_rt_acc: { |
| 14776 | switch (OpNum) { |
| 14777 | case 2: |
| 14778 | // op: Vu32 |
| 14779 | return 8; |
| 14780 | case 3: |
| 14781 | // op: Rt8 |
| 14782 | return 16; |
| 14783 | case 0: |
| 14784 | // op: Vyyyy32 |
| 14785 | return 0; |
| 14786 | } |
| 14787 | break; |
| 14788 | } |
| 14789 | case Hexagon::V6_vmpahhsat: |
| 14790 | case Hexagon::V6_vmpauhuhsat: |
| 14791 | case Hexagon::V6_vmpsuhuhsat: { |
| 14792 | switch (OpNum) { |
| 14793 | case 2: |
| 14794 | // op: Vu32 |
| 14795 | return 8; |
| 14796 | case 3: |
| 14797 | // op: Rtt32 |
| 14798 | return 16; |
| 14799 | case 0: |
| 14800 | // op: Vx32 |
| 14801 | return 0; |
| 14802 | } |
| 14803 | break; |
| 14804 | } |
| 14805 | case Hexagon::V6_vrmpybub_rtt_acc: |
| 14806 | case Hexagon::V6_vrmpyub_rtt_acc: { |
| 14807 | switch (OpNum) { |
| 14808 | case 2: |
| 14809 | // op: Vu32 |
| 14810 | return 8; |
| 14811 | case 3: |
| 14812 | // op: Rtt32 |
| 14813 | return 16; |
| 14814 | case 0: |
| 14815 | // op: Vxx32 |
| 14816 | return 0; |
| 14817 | } |
| 14818 | break; |
| 14819 | } |
| 14820 | case Hexagon::V6_veqb_and: |
| 14821 | case Hexagon::V6_veqb_or: |
| 14822 | case Hexagon::V6_veqb_xor: |
| 14823 | case Hexagon::V6_veqh_and: |
| 14824 | case Hexagon::V6_veqh_or: |
| 14825 | case Hexagon::V6_veqh_xor: |
| 14826 | case Hexagon::V6_veqhf_and: |
| 14827 | case Hexagon::V6_veqhf_or: |
| 14828 | case Hexagon::V6_veqhf_xor: |
| 14829 | case Hexagon::V6_veqsf_and: |
| 14830 | case Hexagon::V6_veqsf_or: |
| 14831 | case Hexagon::V6_veqsf_xor: |
| 14832 | case Hexagon::V6_veqw_and: |
| 14833 | case Hexagon::V6_veqw_or: |
| 14834 | case Hexagon::V6_veqw_xor: |
| 14835 | case Hexagon::V6_vgtb_and: |
| 14836 | case Hexagon::V6_vgtb_or: |
| 14837 | case Hexagon::V6_vgtb_xor: |
| 14838 | case Hexagon::V6_vgtbf_and: |
| 14839 | case Hexagon::V6_vgtbf_or: |
| 14840 | case Hexagon::V6_vgtbf_xor: |
| 14841 | case Hexagon::V6_vgth_and: |
| 14842 | case Hexagon::V6_vgth_or: |
| 14843 | case Hexagon::V6_vgth_xor: |
| 14844 | case Hexagon::V6_vgthf_and: |
| 14845 | case Hexagon::V6_vgthf_or: |
| 14846 | case Hexagon::V6_vgthf_xor: |
| 14847 | case Hexagon::V6_vgtsf_and: |
| 14848 | case Hexagon::V6_vgtsf_or: |
| 14849 | case Hexagon::V6_vgtsf_xor: |
| 14850 | case Hexagon::V6_vgtub_and: |
| 14851 | case Hexagon::V6_vgtub_or: |
| 14852 | case Hexagon::V6_vgtub_xor: |
| 14853 | case Hexagon::V6_vgtuh_and: |
| 14854 | case Hexagon::V6_vgtuh_or: |
| 14855 | case Hexagon::V6_vgtuh_xor: |
| 14856 | case Hexagon::V6_vgtuw_and: |
| 14857 | case Hexagon::V6_vgtuw_or: |
| 14858 | case Hexagon::V6_vgtuw_xor: |
| 14859 | case Hexagon::V6_vgtw_and: |
| 14860 | case Hexagon::V6_vgtw_or: |
| 14861 | case Hexagon::V6_vgtw_xor: { |
| 14862 | switch (OpNum) { |
| 14863 | case 2: |
| 14864 | // op: Vu32 |
| 14865 | return 8; |
| 14866 | case 3: |
| 14867 | // op: Vv32 |
| 14868 | return 16; |
| 14869 | case 0: |
| 14870 | // op: Qx4 |
| 14871 | return 0; |
| 14872 | } |
| 14873 | break; |
| 14874 | } |
| 14875 | case Hexagon::V6_vaddcarryo: |
| 14876 | case Hexagon::V6_vsubcarryo: { |
| 14877 | switch (OpNum) { |
| 14878 | case 2: |
| 14879 | // op: Vu32 |
| 14880 | return 8; |
| 14881 | case 3: |
| 14882 | // op: Vv32 |
| 14883 | return 16; |
| 14884 | case 0: |
| 14885 | // op: Vd32 |
| 14886 | return 0; |
| 14887 | case 1: |
| 14888 | // op: Qe4 |
| 14889 | return 5; |
| 14890 | } |
| 14891 | break; |
| 14892 | } |
| 14893 | case Hexagon::V6_vaddcarry: |
| 14894 | case Hexagon::V6_vsubcarry: { |
| 14895 | switch (OpNum) { |
| 14896 | case 2: |
| 14897 | // op: Vu32 |
| 14898 | return 8; |
| 14899 | case 3: |
| 14900 | // op: Vv32 |
| 14901 | return 16; |
| 14902 | case 0: |
| 14903 | // op: Vd32 |
| 14904 | return 0; |
| 14905 | case 1: |
| 14906 | // op: Qx4 |
| 14907 | return 5; |
| 14908 | } |
| 14909 | break; |
| 14910 | } |
| 14911 | case Hexagon::V6_vdmpy_sf_hf_acc: |
| 14912 | case Hexagon::V6_vdmpyhvsat_acc: |
| 14913 | case Hexagon::V6_vmpy_hf_hf_acc: |
| 14914 | case Hexagon::V6_vmpyiewh_acc: |
| 14915 | case Hexagon::V6_vmpyiewuh_acc: |
| 14916 | case Hexagon::V6_vmpyih_acc: |
| 14917 | case Hexagon::V6_vmpyowh_rnd_sacc: |
| 14918 | case Hexagon::V6_vmpyowh_sacc: |
| 14919 | case Hexagon::V6_vrmpybusv_acc: |
| 14920 | case Hexagon::V6_vrmpybv_acc: |
| 14921 | case Hexagon::V6_vrmpyubv_acc: { |
| 14922 | switch (OpNum) { |
| 14923 | case 2: |
| 14924 | // op: Vu32 |
| 14925 | return 8; |
| 14926 | case 3: |
| 14927 | // op: Vv32 |
| 14928 | return 16; |
| 14929 | case 0: |
| 14930 | // op: Vx32 |
| 14931 | return 0; |
| 14932 | } |
| 14933 | break; |
| 14934 | } |
| 14935 | case Hexagon::V6_vaddhw_acc: |
| 14936 | case Hexagon::V6_vaddubh_acc: |
| 14937 | case Hexagon::V6_vadduhw_acc: |
| 14938 | case Hexagon::V6_vasr_into: |
| 14939 | case Hexagon::V6_vmpy_hf_f8_acc: |
| 14940 | case Hexagon::V6_vmpy_sf_bf_acc: |
| 14941 | case Hexagon::V6_vmpy_sf_hf_acc: |
| 14942 | case Hexagon::V6_vmpybusv_acc: |
| 14943 | case Hexagon::V6_vmpybv_acc: |
| 14944 | case Hexagon::V6_vmpyhus_acc: |
| 14945 | case Hexagon::V6_vmpyhv_acc: |
| 14946 | case Hexagon::V6_vmpyowh_64_acc: |
| 14947 | case Hexagon::V6_vmpyubv_acc: |
| 14948 | case Hexagon::V6_vmpyuhv_acc: { |
| 14949 | switch (OpNum) { |
| 14950 | case 2: |
| 14951 | // op: Vu32 |
| 14952 | return 8; |
| 14953 | case 3: |
| 14954 | // op: Vv32 |
| 14955 | return 16; |
| 14956 | case 0: |
| 14957 | // op: Vxx32 |
| 14958 | return 0; |
| 14959 | } |
| 14960 | break; |
| 14961 | } |
| 14962 | case Hexagon::V6_vlutvvb_oracc: { |
| 14963 | switch (OpNum) { |
| 14964 | case 2: |
| 14965 | // op: Vu32 |
| 14966 | return 8; |
| 14967 | case 3: |
| 14968 | // op: Vv32 |
| 14969 | return 19; |
| 14970 | case 4: |
| 14971 | // op: Rt8 |
| 14972 | return 16; |
| 14973 | case 0: |
| 14974 | // op: Vx32 |
| 14975 | return 0; |
| 14976 | } |
| 14977 | break; |
| 14978 | } |
| 14979 | case Hexagon::V6_vlutvwh_oracc: { |
| 14980 | switch (OpNum) { |
| 14981 | case 2: |
| 14982 | // op: Vu32 |
| 14983 | return 8; |
| 14984 | case 3: |
| 14985 | // op: Vv32 |
| 14986 | return 19; |
| 14987 | case 4: |
| 14988 | // op: Rt8 |
| 14989 | return 16; |
| 14990 | case 0: |
| 14991 | // op: Vxx32 |
| 14992 | return 0; |
| 14993 | } |
| 14994 | break; |
| 14995 | } |
| 14996 | case Hexagon::V6_vdmpyhisat_acc: |
| 14997 | case Hexagon::V6_vdmpyhsuisat_acc: { |
| 14998 | switch (OpNum) { |
| 14999 | case 2: |
| 15000 | // op: Vuu32 |
| 15001 | return 8; |
| 15002 | case 3: |
| 15003 | // op: Rt32 |
| 15004 | return 16; |
| 15005 | case 0: |
| 15006 | // op: Vx32 |
| 15007 | return 0; |
| 15008 | } |
| 15009 | break; |
| 15010 | } |
| 15011 | case Hexagon::V6_vdmpybus_dv_acc: |
| 15012 | case Hexagon::V6_vdmpyhb_dv_acc: |
| 15013 | case Hexagon::V6_vdsaduh_acc: |
| 15014 | case Hexagon::V6_vmpabus_acc: |
| 15015 | case Hexagon::V6_vmpabuu_acc: |
| 15016 | case Hexagon::V6_vmpahb_acc: |
| 15017 | case Hexagon::V6_vmpauhb_acc: |
| 15018 | case Hexagon::V6_vtmpyb_acc: |
| 15019 | case Hexagon::V6_vtmpybus_acc: |
| 15020 | case Hexagon::V6_vtmpyhb_acc: { |
| 15021 | switch (OpNum) { |
| 15022 | case 2: |
| 15023 | // op: Vuu32 |
| 15024 | return 8; |
| 15025 | case 3: |
| 15026 | // op: Rt32 |
| 15027 | return 16; |
| 15028 | case 0: |
| 15029 | // op: Vxx32 |
| 15030 | return 0; |
| 15031 | } |
| 15032 | break; |
| 15033 | } |
| 15034 | case Hexagon::L4_loadalignb_ap: |
| 15035 | case Hexagon::L4_loadalignh_ap: { |
| 15036 | switch (OpNum) { |
| 15037 | case 3: |
| 15038 | // op: II |
| 15039 | return 5; |
| 15040 | case 0: |
| 15041 | // op: Ryy32 |
| 15042 | return 0; |
| 15043 | case 1: |
| 15044 | // op: Re32 |
| 15045 | return 16; |
| 15046 | } |
| 15047 | break; |
| 15048 | } |
| 15049 | case Hexagon::S2_pstorerbnewf_pi: |
| 15050 | case Hexagon::S2_pstorerbnewfnew_pi: |
| 15051 | case Hexagon::S2_pstorerbnewt_pi: |
| 15052 | case Hexagon::S2_pstorerbnewtnew_pi: |
| 15053 | case Hexagon::S2_pstorerhnewf_pi: |
| 15054 | case Hexagon::S2_pstorerhnewfnew_pi: |
| 15055 | case Hexagon::S2_pstorerhnewt_pi: |
| 15056 | case Hexagon::S2_pstorerhnewtnew_pi: |
| 15057 | case Hexagon::S2_pstorerinewf_pi: |
| 15058 | case Hexagon::S2_pstorerinewfnew_pi: |
| 15059 | case Hexagon::S2_pstorerinewt_pi: |
| 15060 | case Hexagon::S2_pstorerinewtnew_pi: { |
| 15061 | switch (OpNum) { |
| 15062 | case 3: |
| 15063 | // op: Ii |
| 15064 | return 3; |
| 15065 | case 1: |
| 15066 | // op: Pv4 |
| 15067 | return 0; |
| 15068 | case 4: |
| 15069 | // op: Nt8 |
| 15070 | return 8; |
| 15071 | case 0: |
| 15072 | // op: Rx32 |
| 15073 | return 16; |
| 15074 | } |
| 15075 | break; |
| 15076 | } |
| 15077 | case Hexagon::S2_pstorerbf_pi: |
| 15078 | case Hexagon::S2_pstorerbfnew_pi: |
| 15079 | case Hexagon::S2_pstorerbt_pi: |
| 15080 | case Hexagon::S2_pstorerbtnew_pi: |
| 15081 | case Hexagon::S2_pstorerff_pi: |
| 15082 | case Hexagon::S2_pstorerffnew_pi: |
| 15083 | case Hexagon::S2_pstorerft_pi: |
| 15084 | case Hexagon::S2_pstorerftnew_pi: |
| 15085 | case Hexagon::S2_pstorerhf_pi: |
| 15086 | case Hexagon::S2_pstorerhfnew_pi: |
| 15087 | case Hexagon::S2_pstorerht_pi: |
| 15088 | case Hexagon::S2_pstorerhtnew_pi: |
| 15089 | case Hexagon::S2_pstorerif_pi: |
| 15090 | case Hexagon::S2_pstorerifnew_pi: |
| 15091 | case Hexagon::S2_pstorerit_pi: |
| 15092 | case Hexagon::S2_pstoreritnew_pi: { |
| 15093 | switch (OpNum) { |
| 15094 | case 3: |
| 15095 | // op: Ii |
| 15096 | return 3; |
| 15097 | case 1: |
| 15098 | // op: Pv4 |
| 15099 | return 0; |
| 15100 | case 4: |
| 15101 | // op: Rt32 |
| 15102 | return 8; |
| 15103 | case 0: |
| 15104 | // op: Rx32 |
| 15105 | return 16; |
| 15106 | } |
| 15107 | break; |
| 15108 | } |
| 15109 | case Hexagon::S2_pstorerdf_pi: |
| 15110 | case Hexagon::S2_pstorerdfnew_pi: |
| 15111 | case Hexagon::S2_pstorerdt_pi: |
| 15112 | case Hexagon::S2_pstorerdtnew_pi: { |
| 15113 | switch (OpNum) { |
| 15114 | case 3: |
| 15115 | // op: Ii |
| 15116 | return 3; |
| 15117 | case 1: |
| 15118 | // op: Pv4 |
| 15119 | return 0; |
| 15120 | case 4: |
| 15121 | // op: Rtt32 |
| 15122 | return 8; |
| 15123 | case 0: |
| 15124 | // op: Rx32 |
| 15125 | return 16; |
| 15126 | } |
| 15127 | break; |
| 15128 | } |
| 15129 | case Hexagon::L2_loadbsw2_pi: |
| 15130 | case Hexagon::L2_loadbzw2_pi: |
| 15131 | case Hexagon::L2_loadrb_pi: |
| 15132 | case Hexagon::L2_loadrh_pi: |
| 15133 | case Hexagon::L2_loadri_pi: |
| 15134 | case Hexagon::L2_loadrub_pi: |
| 15135 | case Hexagon::L2_loadruh_pi: { |
| 15136 | switch (OpNum) { |
| 15137 | case 3: |
| 15138 | // op: Ii |
| 15139 | return 5; |
| 15140 | case 0: |
| 15141 | // op: Rd32 |
| 15142 | return 0; |
| 15143 | case 1: |
| 15144 | // op: Rx32 |
| 15145 | return 16; |
| 15146 | } |
| 15147 | break; |
| 15148 | } |
| 15149 | case Hexagon::L2_loadbsw4_pi: |
| 15150 | case Hexagon::L2_loadbzw4_pi: |
| 15151 | case Hexagon::L2_loadrd_pi: { |
| 15152 | switch (OpNum) { |
| 15153 | case 3: |
| 15154 | // op: Ii |
| 15155 | return 5; |
| 15156 | case 0: |
| 15157 | // op: Rdd32 |
| 15158 | return 0; |
| 15159 | case 1: |
| 15160 | // op: Rx32 |
| 15161 | return 16; |
| 15162 | } |
| 15163 | break; |
| 15164 | } |
| 15165 | case Hexagon::L2_ploadrbf_io: |
| 15166 | case Hexagon::L2_ploadrbfnew_io: |
| 15167 | case Hexagon::L2_ploadrbt_io: |
| 15168 | case Hexagon::L2_ploadrbtnew_io: |
| 15169 | case Hexagon::L2_ploadrhf_io: |
| 15170 | case Hexagon::L2_ploadrhfnew_io: |
| 15171 | case Hexagon::L2_ploadrht_io: |
| 15172 | case Hexagon::L2_ploadrhtnew_io: |
| 15173 | case Hexagon::L2_ploadrif_io: |
| 15174 | case Hexagon::L2_ploadrifnew_io: |
| 15175 | case Hexagon::L2_ploadrit_io: |
| 15176 | case Hexagon::L2_ploadritnew_io: |
| 15177 | case Hexagon::L2_ploadrubf_io: |
| 15178 | case Hexagon::L2_ploadrubfnew_io: |
| 15179 | case Hexagon::L2_ploadrubt_io: |
| 15180 | case Hexagon::L2_ploadrubtnew_io: |
| 15181 | case Hexagon::L2_ploadruhf_io: |
| 15182 | case Hexagon::L2_ploadruhfnew_io: |
| 15183 | case Hexagon::L2_ploadruht_io: |
| 15184 | case Hexagon::L2_ploadruhtnew_io: { |
| 15185 | switch (OpNum) { |
| 15186 | case 3: |
| 15187 | // op: Ii |
| 15188 | return 5; |
| 15189 | case 1: |
| 15190 | // op: Pt4 |
| 15191 | return 11; |
| 15192 | case 2: |
| 15193 | // op: Rs32 |
| 15194 | return 16; |
| 15195 | case 0: |
| 15196 | // op: Rd32 |
| 15197 | return 0; |
| 15198 | } |
| 15199 | break; |
| 15200 | } |
| 15201 | case Hexagon::L2_ploadrdf_io: |
| 15202 | case Hexagon::L2_ploadrdfnew_io: |
| 15203 | case Hexagon::L2_ploadrdt_io: |
| 15204 | case Hexagon::L2_ploadrdtnew_io: { |
| 15205 | switch (OpNum) { |
| 15206 | case 3: |
| 15207 | // op: Ii |
| 15208 | return 5; |
| 15209 | case 1: |
| 15210 | // op: Pt4 |
| 15211 | return 11; |
| 15212 | case 2: |
| 15213 | // op: Rs32 |
| 15214 | return 16; |
| 15215 | case 0: |
| 15216 | // op: Rdd32 |
| 15217 | return 0; |
| 15218 | } |
| 15219 | break; |
| 15220 | } |
| 15221 | case Hexagon::A2_paddif: |
| 15222 | case Hexagon::A2_paddifnew: |
| 15223 | case Hexagon::A2_paddit: |
| 15224 | case Hexagon::A2_padditnew: |
| 15225 | case Hexagon::C2_muxir: { |
| 15226 | switch (OpNum) { |
| 15227 | case 3: |
| 15228 | // op: Ii |
| 15229 | return 5; |
| 15230 | case 1: |
| 15231 | // op: Pu4 |
| 15232 | return 21; |
| 15233 | case 2: |
| 15234 | // op: Rs32 |
| 15235 | return 16; |
| 15236 | case 0: |
| 15237 | // op: Rd32 |
| 15238 | return 0; |
| 15239 | } |
| 15240 | break; |
| 15241 | } |
| 15242 | case Hexagon::S4_addaddi: { |
| 15243 | switch (OpNum) { |
| 15244 | case 3: |
| 15245 | // op: Ii |
| 15246 | return 5; |
| 15247 | case 1: |
| 15248 | // op: Rs32 |
| 15249 | return 16; |
| 15250 | case 2: |
| 15251 | // op: Ru32 |
| 15252 | return 0; |
| 15253 | case 0: |
| 15254 | // op: Rd32 |
| 15255 | return 8; |
| 15256 | } |
| 15257 | break; |
| 15258 | } |
| 15259 | case Hexagon::S4_vrcrotate: { |
| 15260 | switch (OpNum) { |
| 15261 | case 3: |
| 15262 | // op: Ii |
| 15263 | return 5; |
| 15264 | case 1: |
| 15265 | // op: Rss32 |
| 15266 | return 16; |
| 15267 | case 2: |
| 15268 | // op: Rt32 |
| 15269 | return 8; |
| 15270 | case 0: |
| 15271 | // op: Rdd32 |
| 15272 | return 0; |
| 15273 | } |
| 15274 | break; |
| 15275 | } |
| 15276 | case Hexagon::S2_vspliceib: { |
| 15277 | switch (OpNum) { |
| 15278 | case 3: |
| 15279 | // op: Ii |
| 15280 | return 5; |
| 15281 | case 1: |
| 15282 | // op: Rss32 |
| 15283 | return 16; |
| 15284 | case 2: |
| 15285 | // op: Rtt32 |
| 15286 | return 8; |
| 15287 | case 0: |
| 15288 | // op: Rdd32 |
| 15289 | return 0; |
| 15290 | } |
| 15291 | break; |
| 15292 | } |
| 15293 | case Hexagon::S2_addasl_rrri: { |
| 15294 | switch (OpNum) { |
| 15295 | case 3: |
| 15296 | // op: Ii |
| 15297 | return 5; |
| 15298 | case 1: |
| 15299 | // op: Rt32 |
| 15300 | return 8; |
| 15301 | case 2: |
| 15302 | // op: Rs32 |
| 15303 | return 16; |
| 15304 | case 0: |
| 15305 | // op: Rd32 |
| 15306 | return 0; |
| 15307 | } |
| 15308 | break; |
| 15309 | } |
| 15310 | case Hexagon::S2_valignib: { |
| 15311 | switch (OpNum) { |
| 15312 | case 3: |
| 15313 | // op: Ii |
| 15314 | return 5; |
| 15315 | case 1: |
| 15316 | // op: Rtt32 |
| 15317 | return 8; |
| 15318 | case 2: |
| 15319 | // op: Rss32 |
| 15320 | return 16; |
| 15321 | case 0: |
| 15322 | // op: Rdd32 |
| 15323 | return 0; |
| 15324 | } |
| 15325 | break; |
| 15326 | } |
| 15327 | case Hexagon::S4_or_andix: { |
| 15328 | switch (OpNum) { |
| 15329 | case 3: |
| 15330 | // op: Ii |
| 15331 | return 5; |
| 15332 | case 1: |
| 15333 | // op: Ru32 |
| 15334 | return 0; |
| 15335 | case 0: |
| 15336 | // op: Rx32 |
| 15337 | return 16; |
| 15338 | } |
| 15339 | break; |
| 15340 | } |
| 15341 | case Hexagon::M4_mpyri_addr: { |
| 15342 | switch (OpNum) { |
| 15343 | case 3: |
| 15344 | // op: Ii |
| 15345 | return 5; |
| 15346 | case 1: |
| 15347 | // op: Ru32 |
| 15348 | return 0; |
| 15349 | case 2: |
| 15350 | // op: Rs32 |
| 15351 | return 16; |
| 15352 | case 0: |
| 15353 | // op: Rd32 |
| 15354 | return 8; |
| 15355 | } |
| 15356 | break; |
| 15357 | } |
| 15358 | case Hexagon::V6_valignbi: |
| 15359 | case Hexagon::V6_vlalignbi: |
| 15360 | case Hexagon::V6_vlutvvbi: { |
| 15361 | switch (OpNum) { |
| 15362 | case 3: |
| 15363 | // op: Ii |
| 15364 | return 5; |
| 15365 | case 1: |
| 15366 | // op: Vu32 |
| 15367 | return 8; |
| 15368 | case 2: |
| 15369 | // op: Vv32 |
| 15370 | return 16; |
| 15371 | case 0: |
| 15372 | // op: Vd32 |
| 15373 | return 0; |
| 15374 | } |
| 15375 | break; |
| 15376 | } |
| 15377 | case Hexagon::V6_vlutvwhi: { |
| 15378 | switch (OpNum) { |
| 15379 | case 3: |
| 15380 | // op: Ii |
| 15381 | return 5; |
| 15382 | case 1: |
| 15383 | // op: Vu32 |
| 15384 | return 8; |
| 15385 | case 2: |
| 15386 | // op: Vv32 |
| 15387 | return 16; |
| 15388 | case 0: |
| 15389 | // op: Vdd32 |
| 15390 | return 0; |
| 15391 | } |
| 15392 | break; |
| 15393 | } |
| 15394 | case Hexagon::V6_vrmpybusi: |
| 15395 | case Hexagon::V6_vrmpyubi: |
| 15396 | case Hexagon::V6_vrsadubi: { |
| 15397 | switch (OpNum) { |
| 15398 | case 3: |
| 15399 | // op: Ii |
| 15400 | return 5; |
| 15401 | case 1: |
| 15402 | // op: Vuu32 |
| 15403 | return 8; |
| 15404 | case 2: |
| 15405 | // op: Rt32 |
| 15406 | return 16; |
| 15407 | case 0: |
| 15408 | // op: Vdd32 |
| 15409 | return 0; |
| 15410 | } |
| 15411 | break; |
| 15412 | } |
| 15413 | case Hexagon::V6_v6mpyhubs10: |
| 15414 | case Hexagon::V6_v6mpyvubs10: { |
| 15415 | switch (OpNum) { |
| 15416 | case 3: |
| 15417 | // op: Ii |
| 15418 | return 5; |
| 15419 | case 1: |
| 15420 | // op: Vuu32 |
| 15421 | return 8; |
| 15422 | case 2: |
| 15423 | // op: Vvv32 |
| 15424 | return 16; |
| 15425 | case 0: |
| 15426 | // op: Vdd32 |
| 15427 | return 0; |
| 15428 | } |
| 15429 | break; |
| 15430 | } |
| 15431 | case Hexagon::M2_accii: |
| 15432 | case Hexagon::M2_macsin: |
| 15433 | case Hexagon::M2_macsip: |
| 15434 | case Hexagon::M2_naccii: |
| 15435 | case Hexagon::S4_or_andi: |
| 15436 | case Hexagon::S4_or_ori: { |
| 15437 | switch (OpNum) { |
| 15438 | case 3: |
| 15439 | // op: Ii |
| 15440 | return 5; |
| 15441 | case 2: |
| 15442 | // op: Rs32 |
| 15443 | return 16; |
| 15444 | case 0: |
| 15445 | // op: Rx32 |
| 15446 | return 0; |
| 15447 | } |
| 15448 | break; |
| 15449 | } |
| 15450 | case Hexagon::L2_loadalignb_io: |
| 15451 | case Hexagon::L2_loadalignh_io: { |
| 15452 | switch (OpNum) { |
| 15453 | case 3: |
| 15454 | // op: Ii |
| 15455 | return 5; |
| 15456 | case 2: |
| 15457 | // op: Rs32 |
| 15458 | return 16; |
| 15459 | case 0: |
| 15460 | // op: Ryy32 |
| 15461 | return 0; |
| 15462 | } |
| 15463 | break; |
| 15464 | } |
| 15465 | case Hexagon::S2_tableidxb: |
| 15466 | case Hexagon::S2_tableidxd: |
| 15467 | case Hexagon::S2_tableidxh: |
| 15468 | case Hexagon::S2_tableidxw: { |
| 15469 | switch (OpNum) { |
| 15470 | case 3: |
| 15471 | // op: Ii |
| 15472 | return 5; |
| 15473 | case 4: |
| 15474 | // op: II |
| 15475 | return 8; |
| 15476 | case 2: |
| 15477 | // op: Rs32 |
| 15478 | return 16; |
| 15479 | case 0: |
| 15480 | // op: Rx32 |
| 15481 | return 0; |
| 15482 | } |
| 15483 | break; |
| 15484 | } |
| 15485 | case Hexagon::L2_loadbsw2_pci: |
| 15486 | case Hexagon::L2_loadbzw2_pci: |
| 15487 | case Hexagon::L2_loadrb_pci: |
| 15488 | case Hexagon::L2_loadrh_pci: |
| 15489 | case Hexagon::L2_loadri_pci: |
| 15490 | case Hexagon::L2_loadrub_pci: |
| 15491 | case Hexagon::L2_loadruh_pci: { |
| 15492 | switch (OpNum) { |
| 15493 | case 3: |
| 15494 | // op: Ii |
| 15495 | return 5; |
| 15496 | case 4: |
| 15497 | // op: Mu2 |
| 15498 | return 13; |
| 15499 | case 0: |
| 15500 | // op: Rd32 |
| 15501 | return 0; |
| 15502 | case 1: |
| 15503 | // op: Rx32 |
| 15504 | return 16; |
| 15505 | } |
| 15506 | break; |
| 15507 | } |
| 15508 | case Hexagon::L2_loadbsw4_pci: |
| 15509 | case Hexagon::L2_loadbzw4_pci: |
| 15510 | case Hexagon::L2_loadrd_pci: { |
| 15511 | switch (OpNum) { |
| 15512 | case 3: |
| 15513 | // op: Ii |
| 15514 | return 5; |
| 15515 | case 4: |
| 15516 | // op: Mu2 |
| 15517 | return 13; |
| 15518 | case 0: |
| 15519 | // op: Rdd32 |
| 15520 | return 0; |
| 15521 | case 1: |
| 15522 | // op: Rx32 |
| 15523 | return 16; |
| 15524 | } |
| 15525 | break; |
| 15526 | } |
| 15527 | case Hexagon::S4_pstorerbnewf_rr: |
| 15528 | case Hexagon::S4_pstorerbnewfnew_rr: |
| 15529 | case Hexagon::S4_pstorerbnewt_rr: |
| 15530 | case Hexagon::S4_pstorerbnewtnew_rr: |
| 15531 | case Hexagon::S4_pstorerhnewf_rr: |
| 15532 | case Hexagon::S4_pstorerhnewfnew_rr: |
| 15533 | case Hexagon::S4_pstorerhnewt_rr: |
| 15534 | case Hexagon::S4_pstorerhnewtnew_rr: |
| 15535 | case Hexagon::S4_pstorerinewf_rr: |
| 15536 | case Hexagon::S4_pstorerinewfnew_rr: |
| 15537 | case Hexagon::S4_pstorerinewt_rr: |
| 15538 | case Hexagon::S4_pstorerinewtnew_rr: { |
| 15539 | switch (OpNum) { |
| 15540 | case 3: |
| 15541 | // op: Ii |
| 15542 | return 7; |
| 15543 | case 0: |
| 15544 | // op: Pv4 |
| 15545 | return 5; |
| 15546 | case 1: |
| 15547 | // op: Rs32 |
| 15548 | return 16; |
| 15549 | case 2: |
| 15550 | // op: Ru32 |
| 15551 | return 8; |
| 15552 | case 4: |
| 15553 | // op: Nt8 |
| 15554 | return 0; |
| 15555 | } |
| 15556 | break; |
| 15557 | } |
| 15558 | case Hexagon::S4_pstorerbf_rr: |
| 15559 | case Hexagon::S4_pstorerbfnew_rr: |
| 15560 | case Hexagon::S4_pstorerbt_rr: |
| 15561 | case Hexagon::S4_pstorerbtnew_rr: |
| 15562 | case Hexagon::S4_pstorerff_rr: |
| 15563 | case Hexagon::S4_pstorerffnew_rr: |
| 15564 | case Hexagon::S4_pstorerft_rr: |
| 15565 | case Hexagon::S4_pstorerftnew_rr: |
| 15566 | case Hexagon::S4_pstorerhf_rr: |
| 15567 | case Hexagon::S4_pstorerhfnew_rr: |
| 15568 | case Hexagon::S4_pstorerht_rr: |
| 15569 | case Hexagon::S4_pstorerhtnew_rr: |
| 15570 | case Hexagon::S4_pstorerif_rr: |
| 15571 | case Hexagon::S4_pstorerifnew_rr: |
| 15572 | case Hexagon::S4_pstorerit_rr: |
| 15573 | case Hexagon::S4_pstoreritnew_rr: { |
| 15574 | switch (OpNum) { |
| 15575 | case 3: |
| 15576 | // op: Ii |
| 15577 | return 7; |
| 15578 | case 0: |
| 15579 | // op: Pv4 |
| 15580 | return 5; |
| 15581 | case 1: |
| 15582 | // op: Rs32 |
| 15583 | return 16; |
| 15584 | case 2: |
| 15585 | // op: Ru32 |
| 15586 | return 8; |
| 15587 | case 4: |
| 15588 | // op: Rt32 |
| 15589 | return 0; |
| 15590 | } |
| 15591 | break; |
| 15592 | } |
| 15593 | case Hexagon::S4_pstorerdf_rr: |
| 15594 | case Hexagon::S4_pstorerdfnew_rr: |
| 15595 | case Hexagon::S4_pstorerdt_rr: |
| 15596 | case Hexagon::S4_pstorerdtnew_rr: { |
| 15597 | switch (OpNum) { |
| 15598 | case 3: |
| 15599 | // op: Ii |
| 15600 | return 7; |
| 15601 | case 0: |
| 15602 | // op: Pv4 |
| 15603 | return 5; |
| 15604 | case 1: |
| 15605 | // op: Rs32 |
| 15606 | return 16; |
| 15607 | case 2: |
| 15608 | // op: Ru32 |
| 15609 | return 8; |
| 15610 | case 4: |
| 15611 | // op: Rtt32 |
| 15612 | return 0; |
| 15613 | } |
| 15614 | break; |
| 15615 | } |
| 15616 | case Hexagon::L4_loadrb_rr: |
| 15617 | case Hexagon::L4_loadrh_rr: |
| 15618 | case Hexagon::L4_loadri_rr: |
| 15619 | case Hexagon::L4_loadrub_rr: |
| 15620 | case Hexagon::L4_loadruh_rr: { |
| 15621 | switch (OpNum) { |
| 15622 | case 3: |
| 15623 | // op: Ii |
| 15624 | return 7; |
| 15625 | case 1: |
| 15626 | // op: Rs32 |
| 15627 | return 16; |
| 15628 | case 2: |
| 15629 | // op: Rt32 |
| 15630 | return 8; |
| 15631 | case 0: |
| 15632 | // op: Rd32 |
| 15633 | return 0; |
| 15634 | } |
| 15635 | break; |
| 15636 | } |
| 15637 | case Hexagon::L4_loadrd_rr: { |
| 15638 | switch (OpNum) { |
| 15639 | case 3: |
| 15640 | // op: Ii |
| 15641 | return 7; |
| 15642 | case 1: |
| 15643 | // op: Rs32 |
| 15644 | return 16; |
| 15645 | case 2: |
| 15646 | // op: Rt32 |
| 15647 | return 8; |
| 15648 | case 0: |
| 15649 | // op: Rdd32 |
| 15650 | return 0; |
| 15651 | } |
| 15652 | break; |
| 15653 | } |
| 15654 | case Hexagon::L4_loadalignb_ur: |
| 15655 | case Hexagon::L4_loadalignh_ur: { |
| 15656 | switch (OpNum) { |
| 15657 | case 3: |
| 15658 | // op: Ii |
| 15659 | return 7; |
| 15660 | case 4: |
| 15661 | // op: II |
| 15662 | return 5; |
| 15663 | case 2: |
| 15664 | // op: Rt32 |
| 15665 | return 16; |
| 15666 | case 0: |
| 15667 | // op: Ryy32 |
| 15668 | return 0; |
| 15669 | } |
| 15670 | break; |
| 15671 | } |
| 15672 | case Hexagon::V6_vL32Ub_pi: |
| 15673 | case Hexagon::V6_vL32b_cur_pi: |
| 15674 | case Hexagon::V6_vL32b_nt_cur_pi: |
| 15675 | case Hexagon::V6_vL32b_nt_pi: |
| 15676 | case Hexagon::V6_vL32b_nt_tmp_pi: |
| 15677 | case Hexagon::V6_vL32b_pi: |
| 15678 | case Hexagon::V6_vL32b_tmp_pi: { |
| 15679 | switch (OpNum) { |
| 15680 | case 3: |
| 15681 | // op: Ii |
| 15682 | return 8; |
| 15683 | case 0: |
| 15684 | // op: Vd32 |
| 15685 | return 0; |
| 15686 | case 1: |
| 15687 | // op: Rx32 |
| 15688 | return 16; |
| 15689 | } |
| 15690 | break; |
| 15691 | } |
| 15692 | case Hexagon::V6_zLd_pred_pi: { |
| 15693 | switch (OpNum) { |
| 15694 | case 3: |
| 15695 | // op: Ii |
| 15696 | return 8; |
| 15697 | case 1: |
| 15698 | // op: Pv4 |
| 15699 | return 11; |
| 15700 | case 0: |
| 15701 | // op: Rx32 |
| 15702 | return 16; |
| 15703 | } |
| 15704 | break; |
| 15705 | } |
| 15706 | case Hexagon::V6_vL32b_cur_npred_ai: |
| 15707 | case Hexagon::V6_vL32b_cur_pred_ai: |
| 15708 | case Hexagon::V6_vL32b_npred_ai: |
| 15709 | case Hexagon::V6_vL32b_nt_cur_npred_ai: |
| 15710 | case Hexagon::V6_vL32b_nt_cur_pred_ai: |
| 15711 | case Hexagon::V6_vL32b_nt_npred_ai: |
| 15712 | case Hexagon::V6_vL32b_nt_pred_ai: |
| 15713 | case Hexagon::V6_vL32b_nt_tmp_npred_ai: |
| 15714 | case Hexagon::V6_vL32b_nt_tmp_pred_ai: |
| 15715 | case Hexagon::V6_vL32b_pred_ai: |
| 15716 | case Hexagon::V6_vL32b_tmp_npred_ai: |
| 15717 | case Hexagon::V6_vL32b_tmp_pred_ai: { |
| 15718 | switch (OpNum) { |
| 15719 | case 3: |
| 15720 | // op: Ii |
| 15721 | return 8; |
| 15722 | case 1: |
| 15723 | // op: Pv4 |
| 15724 | return 11; |
| 15725 | case 2: |
| 15726 | // op: Rt32 |
| 15727 | return 16; |
| 15728 | case 0: |
| 15729 | // op: Vd32 |
| 15730 | return 0; |
| 15731 | } |
| 15732 | break; |
| 15733 | } |
| 15734 | case Hexagon::V6_vS32b_new_npred_pi: |
| 15735 | case Hexagon::V6_vS32b_new_pred_pi: |
| 15736 | case Hexagon::V6_vS32b_nt_new_npred_pi: |
| 15737 | case Hexagon::V6_vS32b_nt_new_pred_pi: { |
| 15738 | switch (OpNum) { |
| 15739 | case 3: |
| 15740 | // op: Ii |
| 15741 | return 8; |
| 15742 | case 1: |
| 15743 | // op: Pv4 |
| 15744 | return 11; |
| 15745 | case 4: |
| 15746 | // op: Os8 |
| 15747 | return 0; |
| 15748 | case 0: |
| 15749 | // op: Rx32 |
| 15750 | return 16; |
| 15751 | } |
| 15752 | break; |
| 15753 | } |
| 15754 | case Hexagon::V6_vS32Ub_npred_pi: |
| 15755 | case Hexagon::V6_vS32Ub_pred_pi: |
| 15756 | case Hexagon::V6_vS32b_npred_pi: |
| 15757 | case Hexagon::V6_vS32b_nt_npred_pi: |
| 15758 | case Hexagon::V6_vS32b_nt_pred_pi: |
| 15759 | case Hexagon::V6_vS32b_pred_pi: { |
| 15760 | switch (OpNum) { |
| 15761 | case 3: |
| 15762 | // op: Ii |
| 15763 | return 8; |
| 15764 | case 1: |
| 15765 | // op: Pv4 |
| 15766 | return 11; |
| 15767 | case 4: |
| 15768 | // op: Vs32 |
| 15769 | return 0; |
| 15770 | case 0: |
| 15771 | // op: Rx32 |
| 15772 | return 16; |
| 15773 | } |
| 15774 | break; |
| 15775 | } |
| 15776 | case Hexagon::V6_vS32b_nqpred_pi: |
| 15777 | case Hexagon::V6_vS32b_nt_nqpred_pi: |
| 15778 | case Hexagon::V6_vS32b_nt_qpred_pi: |
| 15779 | case Hexagon::V6_vS32b_qpred_pi: { |
| 15780 | switch (OpNum) { |
| 15781 | case 3: |
| 15782 | // op: Ii |
| 15783 | return 8; |
| 15784 | case 1: |
| 15785 | // op: Qv4 |
| 15786 | return 11; |
| 15787 | case 4: |
| 15788 | // op: Vs32 |
| 15789 | return 0; |
| 15790 | case 0: |
| 15791 | // op: Rx32 |
| 15792 | return 16; |
| 15793 | } |
| 15794 | break; |
| 15795 | } |
| 15796 | case Hexagon::S2_asl_i_r_acc: |
| 15797 | case Hexagon::S2_asl_i_r_and: |
| 15798 | case Hexagon::S2_asl_i_r_nac: |
| 15799 | case Hexagon::S2_asl_i_r_or: |
| 15800 | case Hexagon::S2_asl_i_r_xacc: |
| 15801 | case Hexagon::S2_asr_i_r_acc: |
| 15802 | case Hexagon::S2_asr_i_r_and: |
| 15803 | case Hexagon::S2_asr_i_r_nac: |
| 15804 | case Hexagon::S2_asr_i_r_or: |
| 15805 | case Hexagon::S2_lsr_i_r_acc: |
| 15806 | case Hexagon::S2_lsr_i_r_and: |
| 15807 | case Hexagon::S2_lsr_i_r_nac: |
| 15808 | case Hexagon::S2_lsr_i_r_or: |
| 15809 | case Hexagon::S2_lsr_i_r_xacc: |
| 15810 | case Hexagon::S6_rol_i_r_acc: |
| 15811 | case Hexagon::S6_rol_i_r_and: |
| 15812 | case Hexagon::S6_rol_i_r_nac: |
| 15813 | case Hexagon::S6_rol_i_r_or: |
| 15814 | case Hexagon::S6_rol_i_r_xacc: { |
| 15815 | switch (OpNum) { |
| 15816 | case 3: |
| 15817 | // op: Ii |
| 15818 | return 8; |
| 15819 | case 2: |
| 15820 | // op: Rs32 |
| 15821 | return 16; |
| 15822 | case 0: |
| 15823 | // op: Rx32 |
| 15824 | return 0; |
| 15825 | } |
| 15826 | break; |
| 15827 | } |
| 15828 | case Hexagon::S2_asl_i_p_acc: |
| 15829 | case Hexagon::S2_asl_i_p_and: |
| 15830 | case Hexagon::S2_asl_i_p_nac: |
| 15831 | case Hexagon::S2_asl_i_p_or: |
| 15832 | case Hexagon::S2_asl_i_p_xacc: |
| 15833 | case Hexagon::S2_asr_i_p_acc: |
| 15834 | case Hexagon::S2_asr_i_p_and: |
| 15835 | case Hexagon::S2_asr_i_p_nac: |
| 15836 | case Hexagon::S2_asr_i_p_or: |
| 15837 | case Hexagon::S2_lsr_i_p_acc: |
| 15838 | case Hexagon::S2_lsr_i_p_and: |
| 15839 | case Hexagon::S2_lsr_i_p_nac: |
| 15840 | case Hexagon::S2_lsr_i_p_or: |
| 15841 | case Hexagon::S2_lsr_i_p_xacc: |
| 15842 | case Hexagon::S6_rol_i_p_acc: |
| 15843 | case Hexagon::S6_rol_i_p_and: |
| 15844 | case Hexagon::S6_rol_i_p_nac: |
| 15845 | case Hexagon::S6_rol_i_p_or: |
| 15846 | case Hexagon::S6_rol_i_p_xacc: { |
| 15847 | switch (OpNum) { |
| 15848 | case 3: |
| 15849 | // op: Ii |
| 15850 | return 8; |
| 15851 | case 2: |
| 15852 | // op: Rss32 |
| 15853 | return 16; |
| 15854 | case 0: |
| 15855 | // op: Rxx32 |
| 15856 | return 0; |
| 15857 | } |
| 15858 | break; |
| 15859 | } |
| 15860 | case Hexagon::S2_insert: { |
| 15861 | switch (OpNum) { |
| 15862 | case 3: |
| 15863 | // op: Ii |
| 15864 | return 8; |
| 15865 | case 4: |
| 15866 | // op: II |
| 15867 | return 5; |
| 15868 | case 2: |
| 15869 | // op: Rs32 |
| 15870 | return 16; |
| 15871 | case 0: |
| 15872 | // op: Rx32 |
| 15873 | return 0; |
| 15874 | } |
| 15875 | break; |
| 15876 | } |
| 15877 | case Hexagon::S2_insertp: { |
| 15878 | switch (OpNum) { |
| 15879 | case 3: |
| 15880 | // op: Ii |
| 15881 | return 8; |
| 15882 | case 4: |
| 15883 | // op: II |
| 15884 | return 5; |
| 15885 | case 2: |
| 15886 | // op: Rss32 |
| 15887 | return 16; |
| 15888 | case 0: |
| 15889 | // op: Rxx32 |
| 15890 | return 0; |
| 15891 | } |
| 15892 | break; |
| 15893 | } |
| 15894 | case Hexagon::L2_loadbsw2_pbr: |
| 15895 | case Hexagon::L2_loadbsw2_pcr: |
| 15896 | case Hexagon::L2_loadbsw2_pr: |
| 15897 | case Hexagon::L2_loadbzw2_pbr: |
| 15898 | case Hexagon::L2_loadbzw2_pcr: |
| 15899 | case Hexagon::L2_loadbzw2_pr: |
| 15900 | case Hexagon::L2_loadrb_pbr: |
| 15901 | case Hexagon::L2_loadrb_pcr: |
| 15902 | case Hexagon::L2_loadrb_pr: |
| 15903 | case Hexagon::L2_loadrh_pbr: |
| 15904 | case Hexagon::L2_loadrh_pcr: |
| 15905 | case Hexagon::L2_loadrh_pr: |
| 15906 | case Hexagon::L2_loadri_pbr: |
| 15907 | case Hexagon::L2_loadri_pcr: |
| 15908 | case Hexagon::L2_loadri_pr: |
| 15909 | case Hexagon::L2_loadrub_pbr: |
| 15910 | case Hexagon::L2_loadrub_pcr: |
| 15911 | case Hexagon::L2_loadrub_pr: |
| 15912 | case Hexagon::L2_loadruh_pbr: |
| 15913 | case Hexagon::L2_loadruh_pcr: |
| 15914 | case Hexagon::L2_loadruh_pr: { |
| 15915 | switch (OpNum) { |
| 15916 | case 3: |
| 15917 | // op: Mu2 |
| 15918 | return 13; |
| 15919 | case 0: |
| 15920 | // op: Rd32 |
| 15921 | return 0; |
| 15922 | case 1: |
| 15923 | // op: Rx32 |
| 15924 | return 16; |
| 15925 | } |
| 15926 | break; |
| 15927 | } |
| 15928 | case Hexagon::L2_loadbsw4_pbr: |
| 15929 | case Hexagon::L2_loadbsw4_pcr: |
| 15930 | case Hexagon::L2_loadbsw4_pr: |
| 15931 | case Hexagon::L2_loadbzw4_pbr: |
| 15932 | case Hexagon::L2_loadbzw4_pcr: |
| 15933 | case Hexagon::L2_loadbzw4_pr: |
| 15934 | case Hexagon::L2_loadrd_pbr: |
| 15935 | case Hexagon::L2_loadrd_pcr: |
| 15936 | case Hexagon::L2_loadrd_pr: { |
| 15937 | switch (OpNum) { |
| 15938 | case 3: |
| 15939 | // op: Mu2 |
| 15940 | return 13; |
| 15941 | case 0: |
| 15942 | // op: Rdd32 |
| 15943 | return 0; |
| 15944 | case 1: |
| 15945 | // op: Rx32 |
| 15946 | return 16; |
| 15947 | } |
| 15948 | break; |
| 15949 | } |
| 15950 | case Hexagon::V6_vL32Ub_ppu: |
| 15951 | case Hexagon::V6_vL32b_cur_ppu: |
| 15952 | case Hexagon::V6_vL32b_nt_cur_ppu: |
| 15953 | case Hexagon::V6_vL32b_nt_ppu: |
| 15954 | case Hexagon::V6_vL32b_nt_tmp_ppu: |
| 15955 | case Hexagon::V6_vL32b_ppu: |
| 15956 | case Hexagon::V6_vL32b_tmp_ppu: { |
| 15957 | switch (OpNum) { |
| 15958 | case 3: |
| 15959 | // op: Mu2 |
| 15960 | return 13; |
| 15961 | case 0: |
| 15962 | // op: Vd32 |
| 15963 | return 0; |
| 15964 | case 1: |
| 15965 | // op: Rx32 |
| 15966 | return 16; |
| 15967 | } |
| 15968 | break; |
| 15969 | } |
| 15970 | case Hexagon::A5_ACS: { |
| 15971 | switch (OpNum) { |
| 15972 | case 3: |
| 15973 | // op: Rss32 |
| 15974 | return 16; |
| 15975 | case 4: |
| 15976 | // op: Rtt32 |
| 15977 | return 8; |
| 15978 | case 0: |
| 15979 | // op: Rxx32 |
| 15980 | return 0; |
| 15981 | case 1: |
| 15982 | // op: Pe4 |
| 15983 | return 5; |
| 15984 | } |
| 15985 | break; |
| 15986 | } |
| 15987 | case Hexagon::V6_vrmpyzbb_rx_acc: |
| 15988 | case Hexagon::V6_vrmpyzbub_rx_acc: |
| 15989 | case Hexagon::V6_vrmpyzcb_rx_acc: |
| 15990 | case Hexagon::V6_vrmpyzcbs_rx_acc: |
| 15991 | case Hexagon::V6_vrmpyznb_rx_acc: { |
| 15992 | switch (OpNum) { |
| 15993 | case 3: |
| 15994 | // op: Vu32 |
| 15995 | return 8; |
| 15996 | case 0: |
| 15997 | // op: Vyyyy32 |
| 15998 | return 0; |
| 15999 | case 1: |
| 16000 | // op: Rx8 |
| 16001 | return 16; |
| 16002 | } |
| 16003 | break; |
| 16004 | } |
| 16005 | case Hexagon::L2_loadalignb_pi: |
| 16006 | case Hexagon::L2_loadalignh_pi: { |
| 16007 | switch (OpNum) { |
| 16008 | case 4: |
| 16009 | // op: Ii |
| 16010 | return 5; |
| 16011 | case 0: |
| 16012 | // op: Ryy32 |
| 16013 | return 0; |
| 16014 | case 1: |
| 16015 | // op: Rx32 |
| 16016 | return 16; |
| 16017 | } |
| 16018 | break; |
| 16019 | } |
| 16020 | case Hexagon::L2_ploadrbf_pi: |
| 16021 | case Hexagon::L2_ploadrbfnew_pi: |
| 16022 | case Hexagon::L2_ploadrbt_pi: |
| 16023 | case Hexagon::L2_ploadrbtnew_pi: |
| 16024 | case Hexagon::L2_ploadrhf_pi: |
| 16025 | case Hexagon::L2_ploadrhfnew_pi: |
| 16026 | case Hexagon::L2_ploadrht_pi: |
| 16027 | case Hexagon::L2_ploadrhtnew_pi: |
| 16028 | case Hexagon::L2_ploadrif_pi: |
| 16029 | case Hexagon::L2_ploadrifnew_pi: |
| 16030 | case Hexagon::L2_ploadrit_pi: |
| 16031 | case Hexagon::L2_ploadritnew_pi: |
| 16032 | case Hexagon::L2_ploadrubf_pi: |
| 16033 | case Hexagon::L2_ploadrubfnew_pi: |
| 16034 | case Hexagon::L2_ploadrubt_pi: |
| 16035 | case Hexagon::L2_ploadrubtnew_pi: |
| 16036 | case Hexagon::L2_ploadruhf_pi: |
| 16037 | case Hexagon::L2_ploadruhfnew_pi: |
| 16038 | case Hexagon::L2_ploadruht_pi: |
| 16039 | case Hexagon::L2_ploadruhtnew_pi: { |
| 16040 | switch (OpNum) { |
| 16041 | case 4: |
| 16042 | // op: Ii |
| 16043 | return 5; |
| 16044 | case 2: |
| 16045 | // op: Pt4 |
| 16046 | return 9; |
| 16047 | case 0: |
| 16048 | // op: Rd32 |
| 16049 | return 0; |
| 16050 | case 1: |
| 16051 | // op: Rx32 |
| 16052 | return 16; |
| 16053 | } |
| 16054 | break; |
| 16055 | } |
| 16056 | case Hexagon::L2_ploadrdf_pi: |
| 16057 | case Hexagon::L2_ploadrdfnew_pi: |
| 16058 | case Hexagon::L2_ploadrdt_pi: |
| 16059 | case Hexagon::L2_ploadrdtnew_pi: { |
| 16060 | switch (OpNum) { |
| 16061 | case 4: |
| 16062 | // op: Ii |
| 16063 | return 5; |
| 16064 | case 2: |
| 16065 | // op: Pt4 |
| 16066 | return 9; |
| 16067 | case 0: |
| 16068 | // op: Rdd32 |
| 16069 | return 0; |
| 16070 | case 1: |
| 16071 | // op: Rx32 |
| 16072 | return 16; |
| 16073 | } |
| 16074 | break; |
| 16075 | } |
| 16076 | case Hexagon::S4_vrcrotate_acc: { |
| 16077 | switch (OpNum) { |
| 16078 | case 4: |
| 16079 | // op: Ii |
| 16080 | return 5; |
| 16081 | case 2: |
| 16082 | // op: Rss32 |
| 16083 | return 16; |
| 16084 | case 3: |
| 16085 | // op: Rt32 |
| 16086 | return 8; |
| 16087 | case 0: |
| 16088 | // op: Rxx32 |
| 16089 | return 0; |
| 16090 | } |
| 16091 | break; |
| 16092 | } |
| 16093 | case Hexagon::V6_vlutvvb_oracci: { |
| 16094 | switch (OpNum) { |
| 16095 | case 4: |
| 16096 | // op: Ii |
| 16097 | return 5; |
| 16098 | case 2: |
| 16099 | // op: Vu32 |
| 16100 | return 8; |
| 16101 | case 3: |
| 16102 | // op: Vv32 |
| 16103 | return 16; |
| 16104 | case 0: |
| 16105 | // op: Vx32 |
| 16106 | return 0; |
| 16107 | } |
| 16108 | break; |
| 16109 | } |
| 16110 | case Hexagon::V6_vlutvwh_oracci: { |
| 16111 | switch (OpNum) { |
| 16112 | case 4: |
| 16113 | // op: Ii |
| 16114 | return 5; |
| 16115 | case 2: |
| 16116 | // op: Vu32 |
| 16117 | return 8; |
| 16118 | case 3: |
| 16119 | // op: Vv32 |
| 16120 | return 16; |
| 16121 | case 0: |
| 16122 | // op: Vxx32 |
| 16123 | return 0; |
| 16124 | } |
| 16125 | break; |
| 16126 | } |
| 16127 | case Hexagon::V6_vrmpybusi_acc: |
| 16128 | case Hexagon::V6_vrmpyubi_acc: |
| 16129 | case Hexagon::V6_vrsadubi_acc: { |
| 16130 | switch (OpNum) { |
| 16131 | case 4: |
| 16132 | // op: Ii |
| 16133 | return 5; |
| 16134 | case 2: |
| 16135 | // op: Vuu32 |
| 16136 | return 8; |
| 16137 | case 3: |
| 16138 | // op: Rt32 |
| 16139 | return 16; |
| 16140 | case 0: |
| 16141 | // op: Vxx32 |
| 16142 | return 0; |
| 16143 | } |
| 16144 | break; |
| 16145 | } |
| 16146 | case Hexagon::V6_v6mpyhubs10_vxx: |
| 16147 | case Hexagon::V6_v6mpyvubs10_vxx: { |
| 16148 | switch (OpNum) { |
| 16149 | case 4: |
| 16150 | // op: Ii |
| 16151 | return 5; |
| 16152 | case 2: |
| 16153 | // op: Vuu32 |
| 16154 | return 8; |
| 16155 | case 3: |
| 16156 | // op: Vvv32 |
| 16157 | return 16; |
| 16158 | case 0: |
| 16159 | // op: Vxx32 |
| 16160 | return 0; |
| 16161 | } |
| 16162 | break; |
| 16163 | } |
| 16164 | case Hexagon::L2_loadalignb_pci: |
| 16165 | case Hexagon::L2_loadalignh_pci: { |
| 16166 | switch (OpNum) { |
| 16167 | case 4: |
| 16168 | // op: Ii |
| 16169 | return 5; |
| 16170 | case 5: |
| 16171 | // op: Mu2 |
| 16172 | return 13; |
| 16173 | case 0: |
| 16174 | // op: Ryy32 |
| 16175 | return 0; |
| 16176 | case 1: |
| 16177 | // op: Rx32 |
| 16178 | return 16; |
| 16179 | } |
| 16180 | break; |
| 16181 | } |
| 16182 | case Hexagon::L4_ploadrbf_rr: |
| 16183 | case Hexagon::L4_ploadrbfnew_rr: |
| 16184 | case Hexagon::L4_ploadrbt_rr: |
| 16185 | case Hexagon::L4_ploadrbtnew_rr: |
| 16186 | case Hexagon::L4_ploadrhf_rr: |
| 16187 | case Hexagon::L4_ploadrhfnew_rr: |
| 16188 | case Hexagon::L4_ploadrht_rr: |
| 16189 | case Hexagon::L4_ploadrhtnew_rr: |
| 16190 | case Hexagon::L4_ploadrif_rr: |
| 16191 | case Hexagon::L4_ploadrifnew_rr: |
| 16192 | case Hexagon::L4_ploadrit_rr: |
| 16193 | case Hexagon::L4_ploadritnew_rr: |
| 16194 | case Hexagon::L4_ploadrubf_rr: |
| 16195 | case Hexagon::L4_ploadrubfnew_rr: |
| 16196 | case Hexagon::L4_ploadrubt_rr: |
| 16197 | case Hexagon::L4_ploadrubtnew_rr: |
| 16198 | case Hexagon::L4_ploadruhf_rr: |
| 16199 | case Hexagon::L4_ploadruhfnew_rr: |
| 16200 | case Hexagon::L4_ploadruht_rr: |
| 16201 | case Hexagon::L4_ploadruhtnew_rr: { |
| 16202 | switch (OpNum) { |
| 16203 | case 4: |
| 16204 | // op: Ii |
| 16205 | return 7; |
| 16206 | case 1: |
| 16207 | // op: Pv4 |
| 16208 | return 5; |
| 16209 | case 2: |
| 16210 | // op: Rs32 |
| 16211 | return 16; |
| 16212 | case 3: |
| 16213 | // op: Rt32 |
| 16214 | return 8; |
| 16215 | case 0: |
| 16216 | // op: Rd32 |
| 16217 | return 0; |
| 16218 | } |
| 16219 | break; |
| 16220 | } |
| 16221 | case Hexagon::L4_ploadrdf_rr: |
| 16222 | case Hexagon::L4_ploadrdfnew_rr: |
| 16223 | case Hexagon::L4_ploadrdt_rr: |
| 16224 | case Hexagon::L4_ploadrdtnew_rr: { |
| 16225 | switch (OpNum) { |
| 16226 | case 4: |
| 16227 | // op: Ii |
| 16228 | return 7; |
| 16229 | case 1: |
| 16230 | // op: Pv4 |
| 16231 | return 5; |
| 16232 | case 2: |
| 16233 | // op: Rs32 |
| 16234 | return 16; |
| 16235 | case 3: |
| 16236 | // op: Rt32 |
| 16237 | return 8; |
| 16238 | case 0: |
| 16239 | // op: Rdd32 |
| 16240 | return 0; |
| 16241 | } |
| 16242 | break; |
| 16243 | } |
| 16244 | case Hexagon::V6_vL32b_cur_npred_pi: |
| 16245 | case Hexagon::V6_vL32b_cur_pred_pi: |
| 16246 | case Hexagon::V6_vL32b_npred_pi: |
| 16247 | case Hexagon::V6_vL32b_nt_cur_npred_pi: |
| 16248 | case Hexagon::V6_vL32b_nt_cur_pred_pi: |
| 16249 | case Hexagon::V6_vL32b_nt_npred_pi: |
| 16250 | case Hexagon::V6_vL32b_nt_pred_pi: |
| 16251 | case Hexagon::V6_vL32b_nt_tmp_npred_pi: |
| 16252 | case Hexagon::V6_vL32b_nt_tmp_pred_pi: |
| 16253 | case Hexagon::V6_vL32b_pred_pi: |
| 16254 | case Hexagon::V6_vL32b_tmp_npred_pi: |
| 16255 | case Hexagon::V6_vL32b_tmp_pred_pi: { |
| 16256 | switch (OpNum) { |
| 16257 | case 4: |
| 16258 | // op: Ii |
| 16259 | return 8; |
| 16260 | case 2: |
| 16261 | // op: Pv4 |
| 16262 | return 11; |
| 16263 | case 0: |
| 16264 | // op: Vd32 |
| 16265 | return 0; |
| 16266 | case 1: |
| 16267 | // op: Rx32 |
| 16268 | return 16; |
| 16269 | } |
| 16270 | break; |
| 16271 | } |
| 16272 | case Hexagon::L2_loadalignb_pbr: |
| 16273 | case Hexagon::L2_loadalignb_pcr: |
| 16274 | case Hexagon::L2_loadalignb_pr: |
| 16275 | case Hexagon::L2_loadalignh_pbr: |
| 16276 | case Hexagon::L2_loadalignh_pcr: |
| 16277 | case Hexagon::L2_loadalignh_pr: { |
| 16278 | switch (OpNum) { |
| 16279 | case 4: |
| 16280 | // op: Mu2 |
| 16281 | return 13; |
| 16282 | case 0: |
| 16283 | // op: Ryy32 |
| 16284 | return 0; |
| 16285 | case 1: |
| 16286 | // op: Rx32 |
| 16287 | return 16; |
| 16288 | } |
| 16289 | break; |
| 16290 | } |
| 16291 | case Hexagon::V6_vdeal: |
| 16292 | case Hexagon::V6_vshuff: { |
| 16293 | switch (OpNum) { |
| 16294 | case 4: |
| 16295 | // op: Rt32 |
| 16296 | return 16; |
| 16297 | case 0: |
| 16298 | // op: Vy32 |
| 16299 | return 8; |
| 16300 | case 1: |
| 16301 | // op: Vx32 |
| 16302 | return 0; |
| 16303 | } |
| 16304 | break; |
| 16305 | } |
| 16306 | default: |
| 16307 | reportUnsupportedInst(MI); |
| 16308 | } |
| 16309 | reportUnsupportedOperand(MI, OpNum); |
| 16310 | } |
| 16311 | |
| 16312 | #endif // GET_OPERAND_BIT_OFFSET |
| 16313 | |
| 16314 |
Generated while processing llvm_projects/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp
Generated on 2026-Feb-03 from project llvm_projects revision abdf66d60
Powered by 
Code Browser 2.1
Generator usage only permitted with license.