1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* * Lanai Disassembler *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9
10#include "llvm/MC/MCInst.h"
11#include "llvm/MC/MCSubtargetInfo.h"
12#include "llvm/Support/DataTypes.h"
13#include "llvm/Support/Debug.h"
14#include "llvm/Support/LEB128.h"
15#include "llvm/Support/raw_ostream.h"
16#include "llvm/TargetParser/SubtargetFeature.h"
17#include <assert.h>
18
19namespace {
20
21// InsnBitWidth is essentially a type trait used by the decoder emitter to query
22// the supported bitwidth for a given type. But default, the value is 0, making
23// it an invalid type for use as `InsnType` when instantiating the decoder.
24// Individual targets are expected to provide specializations for these based
25// on their usage.
26template <typename T> constexpr uint32_t InsnBitWidth = 0;
27
28static const uint8_t DecoderTableLanai32[743] = {
29 OPC_SwitchField, 28, 4, // 0: switch Inst[31:28] {
30 0, 92, // 3: case 0x0: {
31 OPC_SwitchField, 16, 2, // 5: switch Inst[17:16] {
32 0, 69, // 8: case 0x0: {
33 OPC_Scope, 63, // 10: try {
34 OPC_SwitchField, 0, 16, // 12: switch Inst[15:0] {
35 1, 8, // 15: case 0x1: {
36 OPC_CheckField, 18, 10, 0, // 17: check Inst[27:18] == 0x0
37 OPC_Decode, 243, 2, 0, // 21: decode to NOP using decoder 0
38 // 21: }
39 2, 8, // 25: case 0x2: {
40 OPC_CheckField, 18, 10, 0, // 27: check Inst[27:18] == 0x0
41 OPC_Decode, 237, 2, 0, // 31: decode to LOG0 using decoder 0
42 // 31: }
43 3, 8, // 35: case 0x3: {
44 OPC_CheckField, 18, 10, 0, // 37: check Inst[27:18] == 0x0
45 OPC_Decode, 238, 2, 0, // 41: decode to LOG1 using decoder 0
46 // 41: }
47 4, 8, // 45: case 0x4: {
48 OPC_CheckField, 18, 10, 0, // 47: check Inst[27:18] == 0x0
49 OPC_Decode, 239, 2, 0, // 51: decode to LOG2 using decoder 0
50 // 51: }
51 5, 8, // 55: case 0x5: {
52 OPC_CheckField, 18, 10, 0, // 57: check Inst[27:18] == 0x0
53 OPC_Decode, 240, 2, 0, // 61: decode to LOG3 using decoder 0
54 // 61: }
55 6, 0, // 65: case 0x6: {
56 OPC_CheckField, 18, 10, 0, // 67: check Inst[27:18] == 0x0
57 OPC_Decode, 241, 2, 0, // 71: decode to LOG4 using decoder 0
58 // 71: }
59 // 71: } // switch Inst[15:0]
60 // 71: } else try {
61 OPC_Decode, 210, 2, 1, // 75: decode to ADD_I_LO using decoder 1
62 // 75: }
63 // 75: }
64 1, 4, // 79: case 0x1: {
65 OPC_Decode, 209, 2, 1, // 81: decode to ADD_I_HI using decoder 1
66 // 81: }
67 2, 4, // 85: case 0x2: {
68 OPC_Decode, 207, 2, 1, // 87: decode to ADD_F_I_LO using decoder 1
69 // 87: }
70 3, 0, // 91: case 0x3: {
71 OPC_Decode, 206, 2, 1, // 93: decode to ADD_F_I_HI using decoder 1
72 // 93: }
73 // 93: } // switch Inst[17:16]
74 // 93: }
75 1, 27, // 97: case 0x1: {
76 OPC_SwitchField, 16, 2, // 99: switch Inst[17:16] {
77 0, 4, // 102: case 0x0: {
78 OPC_Decode, 204, 2, 1, // 104: decode to ADDC_I_LO using decoder 1
79 // 104: }
80 1, 4, // 108: case 0x1: {
81 OPC_Decode, 203, 2, 1, // 110: decode to ADDC_I_HI using decoder 1
82 // 110: }
83 2, 4, // 114: case 0x2: {
84 OPC_Decode, 201, 2, 1, // 116: decode to ADDC_F_I_LO using decoder 1
85 // 116: }
86 3, 0, // 120: case 0x3: {
87 OPC_Decode, 200, 2, 1, // 122: decode to ADDC_F_I_HI using decoder 1
88 // 122: }
89 // 122: } // switch Inst[17:16]
90 // 122: }
91 2, 27, // 126: case 0x2: {
92 OPC_SwitchField, 16, 2, // 128: switch Inst[17:16] {
93 0, 4, // 131: case 0x0: {
94 OPC_Decode, 155, 3, 1, // 133: decode to SUB_I_LO using decoder 1
95 // 133: }
96 1, 4, // 137: case 0x1: {
97 OPC_Decode, 154, 3, 1, // 139: decode to SUB_I_HI using decoder 1
98 // 139: }
99 2, 4, // 143: case 0x2: {
100 OPC_Decode, 152, 3, 1, // 145: decode to SUB_F_I_LO using decoder 1
101 // 145: }
102 3, 0, // 149: case 0x3: {
103 OPC_Decode, 151, 3, 1, // 151: decode to SUB_F_I_HI using decoder 1
104 // 151: }
105 // 151: } // switch Inst[17:16]
106 // 151: }
107 3, 27, // 155: case 0x3: {
108 OPC_SwitchField, 16, 2, // 157: switch Inst[17:16] {
109 0, 4, // 160: case 0x0: {
110 OPC_Decode, 149, 3, 1, // 162: decode to SUBB_I_LO using decoder 1
111 // 162: }
112 1, 4, // 166: case 0x1: {
113 OPC_Decode, 148, 3, 1, // 168: decode to SUBB_I_HI using decoder 1
114 // 168: }
115 2, 4, // 172: case 0x2: {
116 OPC_Decode, 146, 3, 1, // 174: decode to SUBB_F_I_LO using decoder 1
117 // 174: }
118 3, 0, // 178: case 0x3: {
119 OPC_Decode, 145, 3, 1, // 180: decode to SUBB_F_I_HI using decoder 1
120 // 180: }
121 // 180: } // switch Inst[17:16]
122 // 180: }
123 4, 27, // 184: case 0x4: {
124 OPC_SwitchField, 16, 2, // 186: switch Inst[17:16] {
125 0, 4, // 189: case 0x0: {
126 OPC_Decode, 216, 2, 1, // 191: decode to AND_I_LO using decoder 1
127 // 191: }
128 1, 4, // 195: case 0x1: {
129 OPC_Decode, 215, 2, 1, // 197: decode to AND_I_HI using decoder 1
130 // 197: }
131 2, 4, // 201: case 0x2: {
132 OPC_Decode, 213, 2, 1, // 203: decode to AND_F_I_LO using decoder 1
133 // 203: }
134 3, 0, // 207: case 0x3: {
135 OPC_Decode, 212, 2, 1, // 209: decode to AND_F_I_HI using decoder 1
136 // 209: }
137 // 209: } // switch Inst[17:16]
138 // 209: }
139 5, 27, // 213: case 0x5: {
140 OPC_SwitchField, 16, 2, // 215: switch Inst[17:16] {
141 0, 4, // 218: case 0x0: {
142 OPC_Decode, 248, 2, 1, // 220: decode to OR_I_LO using decoder 1
143 // 220: }
144 1, 4, // 224: case 0x1: {
145 OPC_Decode, 247, 2, 1, // 226: decode to OR_I_HI using decoder 1
146 // 226: }
147 2, 4, // 230: case 0x2: {
148 OPC_Decode, 245, 2, 1, // 232: decode to OR_F_I_LO using decoder 1
149 // 232: }
150 3, 0, // 236: case 0x3: {
151 OPC_Decode, 244, 2, 1, // 238: decode to OR_F_I_HI using decoder 1
152 // 238: }
153 // 238: } // switch Inst[17:16]
154 // 238: }
155 6, 27, // 242: case 0x6: {
156 OPC_SwitchField, 16, 2, // 244: switch Inst[17:16] {
157 0, 4, // 247: case 0x0: {
158 OPC_Decode, 164, 3, 1, // 249: decode to XOR_I_LO using decoder 1
159 // 249: }
160 1, 4, // 253: case 0x1: {
161 OPC_Decode, 163, 3, 1, // 255: decode to XOR_I_HI using decoder 1
162 // 255: }
163 2, 4, // 259: case 0x2: {
164 OPC_Decode, 161, 3, 1, // 261: decode to XOR_F_I_LO using decoder 1
165 // 261: }
166 3, 0, // 265: case 0x3: {
167 OPC_Decode, 160, 3, 1, // 267: decode to XOR_F_I_HI using decoder 1
168 // 267: }
169 // 267: } // switch Inst[17:16]
170 // 267: }
171 7, 27, // 271: case 0x7: {
172 OPC_SwitchField, 16, 2, // 273: switch Inst[17:16] {
173 0, 4, // 276: case 0x0: {
174 OPC_Decode, 135, 3, 2, // 278: decode to SL_I using decoder 2
175 // 278: }
176 1, 4, // 282: case 0x1: {
177 OPC_Decode, 253, 2, 2, // 284: decode to SA_I using decoder 2
178 // 284: }
179 2, 4, // 288: case 0x2: {
180 OPC_Decode, 134, 3, 2, // 290: decode to SL_F_I using decoder 2
181 // 290: }
182 3, 0, // 294: case 0x3: {
183 OPC_Decode, 252, 2, 2, // 296: decode to SA_F_I using decoder 2
184 // 296: }
185 // 296: } // switch Inst[17:16]
186 // 296: }
187 8, 17, // 300: case 0x8: {
188 OPC_Scope, 11, // 302: try {
189 OPC_CheckField, 0, 28, 252, 255, 219, 8, // 304: check Inst[27:0] == 0x116fffc
190 OPC_Decode, 251, 2, 0, // 311: decode to RET using decoder 0
191 // 311: } else try {
192 OPC_Decode, 233, 2, 3, // 315: decode to LDW_RI using decoder 3
193 // 315: }
194 // 315: }
195 9, 4, // 319: case 0x9: {
196 OPC_Decode, 157, 3, 3, // 321: decode to SW_RI using decoder 3
197 // 321: }
198 10, 39, // 325: case 0xa: {
199 OPC_SwitchField, 0, 3, // 327: switch Inst[2:0] {
200 0, 4, // 330: case 0x0: {
201 OPC_Decode, 230, 2, 4, // 332: decode to LDHs_RR using decoder 4
202 // 332: }
203 1, 4, // 336: case 0x1: {
204 OPC_Decode, 232, 2, 4, // 338: decode to LDHz_RR using decoder 4
205 // 338: }
206 2, 4, // 342: case 0x2: {
207 OPC_Decode, 234, 2, 4, // 344: decode to LDW_RR using decoder 4
208 // 344: }
209 3, 4, // 348: case 0x3: {
210 OPC_Decode, 235, 2, 4, // 350: decode to LDWz_RR using decoder 4
211 // 350: }
212 4, 4, // 354: case 0x4: {
213 OPC_Decode, 226, 2, 4, // 356: decode to LDBs_RR using decoder 4
214 // 356: }
215 5, 0, // 360: case 0x5: {
216 OPC_Decode, 228, 2, 4, // 362: decode to LDBz_RR using decoder 4
217 // 362: }
218 // 362: } // switch Inst[2:0]
219 // 362: }
220 11, 21, // 366: case 0xb: {
221 OPC_SwitchField, 0, 3, // 368: switch Inst[2:0] {
222 0, 4, // 371: case 0x0: {
223 OPC_Decode, 144, 3, 4, // 373: decode to STH_RR using decoder 4
224 // 373: }
225 2, 4, // 377: case 0x2: {
226 OPC_Decode, 158, 3, 4, // 379: decode to SW_RR using decoder 4
227 // 379: }
228 4, 0, // 383: case 0x4: {
229 OPC_Decode, 142, 3, 4, // 385: decode to STB_RR using decoder 4
230 // 385: }
231 // 385: } // switch Inst[2:0]
232 // 385: }
233 12, 214, 1, // 389: case 0xc: {
234 OPC_SwitchField, 3, 8, // 392: switch Inst[10:3] {
235 0, 15, // 395: case 0x0: {
236 OPC_SwitchField, 17, 1, // 397: switch Inst[17] {
237 0, 4, // 400: case 0x0: {
238 OPC_Decode, 211, 2, 5, // 402: decode to ADD_R using decoder 5
239 // 402: }
240 1, 0, // 406: case 0x1: {
241 OPC_Decode, 208, 2, 5, // 408: decode to ADD_F_R using decoder 5
242 // 408: }
243 // 408: } // switch Inst[17]
244 // 408: }
245 32, 15, // 412: case 0x20: {
246 OPC_SwitchField, 17, 1, // 414: switch Inst[17] {
247 0, 4, // 417: case 0x0: {
248 OPC_Decode, 205, 2, 5, // 419: decode to ADDC_R using decoder 5
249 // 419: }
250 1, 0, // 423: case 0x1: {
251 OPC_Decode, 202, 2, 5, // 425: decode to ADDC_F_R using decoder 5
252 // 425: }
253 // 425: } // switch Inst[17]
254 // 425: }
255 64, 15, // 429: case 0x40: {
256 OPC_SwitchField, 17, 1, // 431: switch Inst[17] {
257 0, 4, // 434: case 0x0: {
258 OPC_Decode, 156, 3, 5, // 436: decode to SUB_R using decoder 5
259 // 436: }
260 1, 0, // 440: case 0x1: {
261 OPC_Decode, 153, 3, 5, // 442: decode to SUB_F_R using decoder 5
262 // 442: }
263 // 442: } // switch Inst[17]
264 // 442: }
265 96, 15, // 446: case 0x60: {
266 OPC_SwitchField, 17, 1, // 448: switch Inst[17] {
267 0, 4, // 451: case 0x0: {
268 OPC_Decode, 150, 3, 5, // 453: decode to SUBB_R using decoder 5
269 // 453: }
270 1, 0, // 457: case 0x1: {
271 OPC_Decode, 147, 3, 5, // 459: decode to SUBB_F_R using decoder 5
272 // 459: }
273 // 459: } // switch Inst[17]
274 // 459: }
275 128, 1, 15, // 463: case 0x80: {
276 OPC_SwitchField, 17, 1, // 466: switch Inst[17] {
277 0, 4, // 469: case 0x0: {
278 OPC_Decode, 217, 2, 5, // 471: decode to AND_R using decoder 5
279 // 471: }
280 1, 0, // 475: case 0x1: {
281 OPC_Decode, 214, 2, 5, // 477: decode to AND_F_R using decoder 5
282 // 477: }
283 // 477: } // switch Inst[17]
284 // 477: }
285 160, 1, 57, // 481: case 0xa0: {
286 OPC_SwitchField, 17, 1, // 484: switch Inst[17] {
287 0, 46, // 487: case 0x0: {
288 OPC_Scope, 16, // 489: try {
289 OPC_CheckField, 0, 3, 0, // 491: check Inst[2:0] == 0x0
290 OPC_CheckField, 18, 10, 64, // 495: check Inst[27:18] == 0x40
291 OPC_CheckField, 16, 1, 0, // 499: check Inst[16] == 0x0
292 OPC_Decode, 223, 2, 6, // 503: decode to JR using decoder 6
293 OPC_Scope, 12, // 507: } else try {
294 OPC_CheckField, 11, 5, 0, // 509: check Inst[15:11] == 0x0
295 OPC_CheckField, 23, 5, 2, // 513: check Inst[27:23] == 0x2
296 OPC_Decode, 219, 2, 7, // 517: decode to BRIND_CC using decoder 7
297 OPC_Scope, 8, // 521: } else try {
298 OPC_CheckField, 23, 5, 2, // 523: check Inst[27:23] == 0x2
299 OPC_Decode, 220, 2, 8, // 527: decode to BRIND_CCA using decoder 8
300 // 527: } else try {
301 OPC_Decode, 249, 2, 5, // 531: decode to OR_R using decoder 5
302 // 531: }
303 // 531: }
304 1, 0, // 535: case 0x1: {
305 OPC_Decode, 246, 2, 5, // 537: decode to OR_F_R using decoder 5
306 // 537: }
307 // 537: } // switch Inst[17]
308 // 537: }
309 192, 1, 15, // 541: case 0xc0: {
310 OPC_SwitchField, 17, 1, // 544: switch Inst[17] {
311 0, 4, // 547: case 0x0: {
312 OPC_Decode, 165, 3, 5, // 549: decode to XOR_R using decoder 5
313 // 549: }
314 1, 0, // 553: case 0x1: {
315 OPC_Decode, 162, 3, 5, // 555: decode to XOR_F_R using decoder 5
316 // 555: }
317 // 555: } // switch Inst[17]
318 // 555: }
319 224, 1, 8, // 559: case 0xe0: {
320 OPC_CheckField, 17, 1, 0, // 562: check Inst[17] == 0x0
321 OPC_Decode, 255, 2, 9, // 566: decode to SELECT using decoder 9
322 // 566: }
323 240, 1, 15, // 570: case 0xf0: {
324 OPC_SwitchField, 17, 1, // 573: switch Inst[17] {
325 0, 4, // 576: case 0x0: {
326 OPC_Decode, 132, 3, 5, // 578: decode to SHL_R using decoder 5
327 // 578: }
328 1, 0, // 582: case 0x1: {
329 OPC_Decode, 131, 3, 5, // 584: decode to SHL_F_R using decoder 5
330 // 584: }
331 // 584: } // switch Inst[17]
332 // 584: }
333 248, 1, 0, // 588: case 0xf8: {
334 OPC_SwitchField, 17, 1, // 591: switch Inst[17] {
335 0, 4, // 594: case 0x0: {
336 OPC_Decode, 137, 3, 5, // 596: decode to SRA_R using decoder 5
337 // 596: }
338 1, 0, // 600: case 0x1: {
339 OPC_Decode, 136, 3, 5, // 602: decode to SRA_F_R using decoder 5
340 // 602: }
341 // 602: } // switch Inst[17]
342 // 602: }
343 // 602: } // switch Inst[10:3]
344 // 602: }
345 13, 21, // 606: case 0xd: {
346 OPC_SwitchField, 0, 18, // 608: switch Inst[17:0] {
347 1, 4, // 611: case 0x1: {
348 OPC_Decode, 250, 2, 10, // 613: decode to POPC using decoder 10
349 // 613: }
350 2, 4, // 617: case 0x2: {
351 OPC_Decode, 236, 2, 10, // 619: decode to LEADZ using decoder 10
352 // 619: }
353 3, 0, // 623: case 0x3: {
354 OPC_Decode, 159, 3, 10, // 625: decode to TRAILZ using decoder 10
355 // 625: }
356 // 625: } // switch Inst[17:0]
357 // 625: }
358 14, 48, // 629: case 0xe: {
359 OPC_SwitchField, 1, 1, // 631: switch Inst[1] {
360 0, 18, // 634: case 0x0: {
361 OPC_Scope, 12, // 636: try {
362 OPC_CheckField, 0, 1, 0, // 638: check Inst[0] == 0x0
363 OPC_CheckField, 25, 3, 0, // 642: check Inst[27:25] == 0x0
364 OPC_Decode, 222, 2, 11, // 646: decode to BT using decoder 11
365 // 646: } else try {
366 OPC_Decode, 218, 2, 12, // 650: decode to BRCC using decoder 12
367 // 650: }
368 // 650: }
369 1, 0, // 654: case 0x1: {
370 OPC_SwitchField, 23, 2, // 656: switch Inst[24:23] {
371 0, 8, // 659: case 0x0: {
372 OPC_CheckField, 2, 16, 0, // 661: check Inst[17:2] == 0x0
373 OPC_Decode, 254, 2, 13, // 665: decode to SCC using decoder 13
374 // 665: }
375 2, 0, // 669: case 0x2: {
376 OPC_CheckField, 16, 7, 0, // 671: check Inst[22:16] == 0x0
377 OPC_Decode, 221, 2, 14, // 675: decode to BRR using decoder 14
378 // 675: }
379 // 675: } // switch Inst[24:23]
380 // 675: }
381 // 675: } // switch Inst[1]
382 // 675: }
383 15, 0, // 679: case 0xf: {
384 OPC_SwitchField, 16, 2, // 681: switch Inst[17:16] {
385 0, 4, // 684: case 0x0: {
386 OPC_Decode, 224, 2, 15, // 686: decode to LDADDR using decoder 15
387 // 686: }
388 1, 4, // 690: case 0x1: {
389 OPC_Decode, 140, 3, 15, // 692: decode to STADDR using decoder 15
390 // 692: }
391 2, 4, // 696: case 0x2: {
392 OPC_Decode, 133, 3, 15, // 698: decode to SLI using decoder 15
393 // 698: }
394 3, 0, // 702: case 0x3: {
395 OPC_SwitchField, 12, 4, // 704: switch Inst[15:12] {
396 0, 4, // 707: case 0x0: {
397 OPC_Decode, 229, 2, 16, // 709: decode to LDHs_RI using decoder 16
398 // 709: }
399 1, 4, // 713: case 0x1: {
400 OPC_Decode, 231, 2, 16, // 715: decode to LDHz_RI using decoder 16
401 // 715: }
402 2, 4, // 719: case 0x2: {
403 OPC_Decode, 143, 3, 16, // 721: decode to STH_RI using decoder 16
404 // 721: }
405 4, 4, // 725: case 0x4: {
406 OPC_Decode, 225, 2, 16, // 727: decode to LDBs_RI using decoder 16
407 // 727: }
408 5, 4, // 731: case 0x5: {
409 OPC_Decode, 227, 2, 16, // 733: decode to LDBz_RI using decoder 16
410 // 733: }
411 6, 0, // 737: case 0x6: {
412 OPC_Decode, 141, 3, 16, // 739: decode to STB_RI using decoder 16
413 // 739: }
414 // 739: } // switch Inst[15:12]
415 // 739: }
416 // 739: } // switch Inst[17:16]
417 // 739: }
418 // 739: } // switch Inst[31:28]
419};
420// Handling 17 cases.
421template <typename InsnType>
422static DecodeStatus decodeToMCInst(unsigned Idx, DecodeStatus S, InsnType insn, MCInst &MI, uint64_t Address, const MCDisassembler *Decoder, bool &DecodeComplete) {
423 DecodeComplete = true;
424 using TmpType = std::conditional_t<std::is_integral<InsnType>::value, InsnType, uint64_t>;
425 TmpType tmp;
426 switch (Idx) {
427 default: llvm_unreachable("Invalid decoder index!");
428 case 0:
429 return S;
430 case 1:
431 tmp = fieldFromInstruction(insn, 23, 5);
432 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
433 tmp = fieldFromInstruction(insn, 18, 5);
434 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
435 tmp = fieldFromInstruction(insn, 0, 16);
436 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
437 return S;
438 case 2:
439 tmp = fieldFromInstruction(insn, 23, 5);
440 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
441 tmp = fieldFromInstruction(insn, 18, 5);
442 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
443 tmp = fieldFromInstruction(insn, 0, 16);
444 if (!Check(S, decodeShiftImm(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
445 return S;
446 case 3:
447 tmp = fieldFromInstruction(insn, 23, 5);
448 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
449 tmp = fieldFromInstruction(insn, 0, 23);
450 if (!Check(S, decodeRiMemoryValue(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
451 return S;
452 case 4:
453 tmp = fieldFromInstruction(insn, 23, 5);
454 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
455 tmp = 0x0;
456 tmp |= fieldFromInstruction(insn, 3, 8);
457 tmp |= fieldFromInstruction(insn, 11, 5) << 10;
458 tmp |= fieldFromInstruction(insn, 16, 2) << 8;
459 tmp |= fieldFromInstruction(insn, 18, 5) << 15;
460 if (!Check(S, decodeRrMemoryValue(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
461 return S;
462 case 5:
463 tmp = fieldFromInstruction(insn, 23, 5);
464 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
465 tmp = fieldFromInstruction(insn, 18, 5);
466 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
467 tmp = fieldFromInstruction(insn, 11, 5);
468 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
469 tmp = 0x0;
470 tmp |= fieldFromInstruction(insn, 0, 3) << 1;
471 tmp |= fieldFromInstruction(insn, 16, 1);
472 if (!Check(S, decodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
473 return S;
474 case 6:
475 tmp = fieldFromInstruction(insn, 11, 5);
476 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
477 return S;
478 case 7:
479 tmp = fieldFromInstruction(insn, 18, 5);
480 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
481 tmp = 0x0;
482 tmp |= fieldFromInstruction(insn, 0, 3) << 1;
483 tmp |= fieldFromInstruction(insn, 16, 1);
484 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
485 return S;
486 case 8:
487 tmp = fieldFromInstruction(insn, 18, 5);
488 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
489 tmp = fieldFromInstruction(insn, 11, 5);
490 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
491 tmp = 0x0;
492 tmp |= fieldFromInstruction(insn, 0, 3) << 1;
493 tmp |= fieldFromInstruction(insn, 16, 1);
494 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
495 return S;
496 case 9:
497 tmp = fieldFromInstruction(insn, 23, 5);
498 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
499 tmp = fieldFromInstruction(insn, 18, 5);
500 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
501 tmp = fieldFromInstruction(insn, 11, 5);
502 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
503 tmp = 0x0;
504 tmp |= fieldFromInstruction(insn, 0, 3) << 1;
505 tmp |= fieldFromInstruction(insn, 16, 1);
506 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
507 return S;
508 case 10:
509 tmp = fieldFromInstruction(insn, 23, 5);
510 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
511 tmp = fieldFromInstruction(insn, 18, 5);
512 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
513 return S;
514 case 11:
515 tmp = fieldFromInstruction(insn, 2, 23) << 2;
516 if (!Check(S, decodeBranch(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
517 return S;
518 case 12:
519 tmp = fieldFromInstruction(insn, 2, 23) << 2;
520 if (!Check(S, decodeBranch(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
521 tmp = 0x0;
522 tmp |= fieldFromInstruction(insn, 0, 1);
523 tmp |= fieldFromInstruction(insn, 25, 3) << 1;
524 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
525 return S;
526 case 13:
527 tmp = fieldFromInstruction(insn, 18, 5);
528 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
529 tmp = 0x0;
530 tmp |= fieldFromInstruction(insn, 0, 1);
531 tmp |= fieldFromInstruction(insn, 25, 3) << 1;
532 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
533 return S;
534 case 14:
535 tmp = fieldFromInstruction(insn, 2, 14) << 2;
536 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
537 tmp = 0x0;
538 tmp |= fieldFromInstruction(insn, 0, 1);
539 tmp |= fieldFromInstruction(insn, 25, 3) << 1;
540 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
541 return S;
542 case 15:
543 tmp = fieldFromInstruction(insn, 23, 5);
544 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
545 tmp = 0x0;
546 tmp |= fieldFromInstruction(insn, 0, 16);
547 tmp |= fieldFromInstruction(insn, 18, 5) << 16;
548 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
549 return S;
550 case 16:
551 tmp = fieldFromInstruction(insn, 23, 5);
552 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
553 tmp = 0x0;
554 tmp |= fieldFromInstruction(insn, 0, 12);
555 tmp |= fieldFromInstruction(insn, 18, 5) << 12;
556 if (!Check(S, decodeSplsValue(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
557 return S;
558 }
559}
560
561template <typename InsnType>
562static DecodeStatus decodeInstruction(const uint8_t DecodeTable[], MCInst &MI,
563 InsnType insn, uint64_t Address,
564 const MCDisassembler *DisAsm,
565 const MCSubtargetInfo &STI) {
566 const uint8_t *Ptr = DecodeTable;
567
568 SmallVector<const uint8_t *, 8> ScopeStack;
569 DecodeStatus S = MCDisassembler::Success;
570 while (true) {
571 ptrdiff_t Loc = Ptr - DecodeTable;
572 const uint8_t DecoderOp = *Ptr++;
573 switch (DecoderOp) {
574 default:
575 errs() << Loc << ": Unexpected decode table opcode: "
576 << (int)DecoderOp << '\n';
577 return MCDisassembler::Fail;
578 case OPC_Scope: {
579 unsigned NumToSkip = decodeULEB128AndIncUnsafe(p&: Ptr);
580 const uint8_t *SkipTo = Ptr + NumToSkip;
581 ScopeStack.push_back(Elt: SkipTo);
582 LLVM_DEBUG(dbgs() << Loc << ": OPC_Scope(" << SkipTo - DecodeTable
583 << ")\n");
584 continue;
585 }
586 case OPC_SwitchField: {
587 // Decode the start value.
588 unsigned Start = decodeULEB128AndIncUnsafe(p&: Ptr);
589 unsigned Len = *Ptr++;
590 uint64_t FieldValue = fieldFromInstruction(insn, Start, Len);
591 uint64_t CaseValue;
592 unsigned CaseSize;
593 while (true) {
594 CaseValue = decodeULEB128AndIncUnsafe(p&: Ptr);
595 CaseSize = decodeULEB128AndIncUnsafe(p&: Ptr);
596 if (FieldValue == CaseValue || !CaseSize)
597 break;
598 Ptr += CaseSize;
599 }
600 if (FieldValue == CaseValue) {
601 LLVM_DEBUG(dbgs() << Loc << ": OPC_SwitchField(" << Start << ", " << Len
602 << "): " << FieldValue << '\n');
603 continue;
604 }
605 break;
606 }
607 case OPC_CheckField: {
608 // Decode the start value.
609 unsigned Start = decodeULEB128AndIncUnsafe(p&: Ptr);
610 unsigned Len = *Ptr;
611 uint64_t FieldValue = fieldFromInstruction(insn, Start, Len);
612 // Decode the field value.
613 unsigned PtrLen = 0;
614 uint64_t ExpectedValue = decodeULEB128(p: ++Ptr, n: &PtrLen);
615 Ptr += PtrLen;
616 bool Failed = ExpectedValue != FieldValue;
617
618 LLVM_DEBUG(dbgs() << Loc << ": OPC_CheckField(" << Start << ", " << Len
619 << ", " << ExpectedValue << "): FieldValue = "
620 << FieldValue << ", ExpectedValue = " << ExpectedValue
621 << ": " << (Failed ? "FAIL, " : "PASS\n"););
622 if (!Failed)
623 continue;
624 break;
625 }
626 case OPC_Decode: {
627 // Decode the Opcode value.
628 unsigned Opc = decodeULEB128AndIncUnsafe(p&: Ptr);
629 unsigned DecodeIdx = decodeULEB128AndIncUnsafe(p&: Ptr);
630
631 MI.clear();
632 MI.setOpcode(Opc);
633 bool DecodeComplete;
634 S = decodeToMCInst(DecodeIdx, S, insn, MI, Address, DisAsm,
635 DecodeComplete);
636 LLVM_DEBUG(dbgs() << Loc << ": OPC_Decode: opcode " << Opc
637 << ", using decoder " << DecodeIdx << ": "
638 << (S ? "PASS, " : "FAIL, "));
639
640 if (DecodeComplete) {
641 LLVM_DEBUG(dbgs() << "decoding complete\n");
642 return S;
643 }
644 assert(S == MCDisassembler::Fail);
645 // Reset decode status. This also drops a SoftFail status that could be
646 // set before the decode attempt.
647 S = MCDisassembler::Success;
648 break;
649 }
650 }
651 if (ScopeStack.empty()) {
652 LLVM_DEBUG(dbgs() << "returning Fail\n");
653 return MCDisassembler::Fail;
654 }
655 Ptr = ScopeStack.pop_back_val();
656 LLVM_DEBUG(dbgs() << "continuing at " << Ptr - DecodeTable << '\n');
657 }
658 llvm_unreachable("bogosity detected in disassembler state machine!");
659}
660
661
662} // namespace
663