1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Instruction Enum Values and Descriptors *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_INSTRINFO_ENUM
10#undef GET_INSTRINFO_ENUM
11
12namespace llvm::Lanai {
13
14 enum {
15 PHI = 0, // Target.td:1314
16 INLINEASM = 1, // Target.td:1320
17 INLINEASM_BR = 2, // Target.td:1326
18 CFI_INSTRUCTION = 3, // Target.td:1335
19 EH_LABEL = 4, // Target.td:1344
20 GC_LABEL = 5, // Target.td:1353
21 ANNOTATION_LABEL = 6, // Target.td:1362
22 KILL = 7, // Target.td:1370
23 EXTRACT_SUBREG = 8, // Target.td:1377
24 INSERT_SUBREG = 9, // Target.td:1383
25 IMPLICIT_DEF = 10, // Target.td:1390
26 INIT_UNDEF = 11, // Target.td:1399
27 SUBREG_TO_REG = 12, // Target.td:1406
28 COPY_TO_REGCLASS = 13, // Target.td:1412
29 DBG_VALUE = 14, // Target.td:1419
30 DBG_VALUE_LIST = 15, // Target.td:1426
31 DBG_INSTR_REF = 16, // Target.td:1433
32 DBG_PHI = 17, // Target.td:1440
33 DBG_LABEL = 18, // Target.td:1447
34 REG_SEQUENCE = 19, // Target.td:1454
35 COPY = 20, // Target.td:1461
36 COPY_LANEMASK = 21, // Target.td:1469
37 BUNDLE = 22, // Target.td:1476
38 LIFETIME_START = 23, // Target.td:1482
39 LIFETIME_END = 24, // Target.td:1489
40 PSEUDO_PROBE = 25, // Target.td:1496
41 ARITH_FENCE = 26, // Target.td:1503
42 STACKMAP = 27, // Target.td:1512
43 FENTRY_CALL = 28, // Target.td:1647
44 PATCHPOINT = 29, // Target.td:1520
45 LOAD_STACK_GUARD = 30, // Target.td:1538
46 PREALLOCATED_SETUP = 31, // Target.td:1546
47 PREALLOCATED_ARG = 32, // Target.td:1552
48 STATEPOINT = 33, // Target.td:1529
49 LOCAL_ESCAPE = 34, // Target.td:1558
50 FAULTING_OP = 35, // Target.td:1567
51 PATCHABLE_OP = 36, // Target.td:1587
52 PATCHABLE_FUNCTION_ENTER = 37, // Target.td:1595
53 PATCHABLE_RET = 38, // Target.td:1602
54 PATCHABLE_FUNCTION_EXIT = 39, // Target.td:1611
55 PATCHABLE_TAIL_CALL = 40, // Target.td:1619
56 PATCHABLE_EVENT_CALL = 41, // Target.td:1627
57 PATCHABLE_TYPED_EVENT_CALL = 42, // Target.td:1637
58 ICALL_BRANCH_FUNNEL = 43, // Target.td:1657
59 FAKE_USE = 44, // Target.td:1577
60 MEMBARRIER = 45, // Target.td:1663
61 JUMP_TABLE_DEBUG_INFO = 46, // Target.td:1671
62 RELOC_NONE = 47, // Target.td:1679
63 CONVERGENCECTRL_ENTRY = 48, // Target.td:1691
64 CONVERGENCECTRL_ANCHOR = 49, // Target.td:1687
65 CONVERGENCECTRL_LOOP = 50, // Target.td:1695
66 CONVERGENCECTRL_GLUE = 51, // Target.td:1699
67 G_ASSERT_SEXT = 52, // GenericOpcodes.td:1955
68 G_ASSERT_ZEXT = 53, // GenericOpcodes.td:1947
69 G_ASSERT_ALIGN = 54, // GenericOpcodes.td:1962
70 G_ADD = 55, // GenericOpcodes.td:308
71 G_SUB = 56, // GenericOpcodes.td:316
72 G_MUL = 57, // GenericOpcodes.td:324
73 G_SDIV = 58, // GenericOpcodes.td:332
74 G_UDIV = 59, // GenericOpcodes.td:340
75 G_SREM = 60, // GenericOpcodes.td:348
76 G_UREM = 61, // GenericOpcodes.td:356
77 G_SDIVREM = 62, // GenericOpcodes.td:364
78 G_UDIVREM = 63, // GenericOpcodes.td:372
79 G_AND = 64, // GenericOpcodes.td:380
80 G_OR = 65, // GenericOpcodes.td:388
81 G_XOR = 66, // GenericOpcodes.td:396
82 G_ABDS = 67, // GenericOpcodes.td:425
83 G_ABDU = 68, // GenericOpcodes.td:433
84 G_UAVGFLOOR = 69, // GenericOpcodes.td:441
85 G_UAVGCEIL = 70, // GenericOpcodes.td:448
86 G_SAVGFLOOR = 71, // GenericOpcodes.td:455
87 G_SAVGCEIL = 72, // GenericOpcodes.td:462
88 G_IMPLICIT_DEF = 73, // GenericOpcodes.td:111
89 G_PHI = 74, // GenericOpcodes.td:118
90 G_FRAME_INDEX = 75, // GenericOpcodes.td:125
91 G_GLOBAL_VALUE = 76, // GenericOpcodes.td:131
92 G_PTRAUTH_GLOBAL_VALUE = 77, // GenericOpcodes.td:137
93 G_CONSTANT_POOL = 78, // GenericOpcodes.td:143
94 G_EXTRACT = 79, // GenericOpcodes.td:1540
95 G_UNMERGE_VALUES = 80, // GenericOpcodes.td:1553
96 G_INSERT = 81, // GenericOpcodes.td:1562
97 G_MERGE_VALUES = 82, // GenericOpcodes.td:1572
98 G_BUILD_VECTOR = 83, // GenericOpcodes.td:1592
99 G_BUILD_VECTOR_TRUNC = 84, // GenericOpcodes.td:1602
100 G_CONCAT_VECTORS = 85, // GenericOpcodes.td:1609
101 G_PTRTOINT = 86, // GenericOpcodes.td:155
102 G_INTTOPTR = 87, // GenericOpcodes.td:149
103 G_BITCAST = 88, // GenericOpcodes.td:161
104 G_FREEZE = 89, // GenericOpcodes.td:284
105 G_CONSTANT_FOLD_BARRIER = 90, // GenericOpcodes.td:1969
106 G_INTRINSIC_FPTRUNC_ROUND = 91, // GenericOpcodes.td:1298
107 G_INTRINSIC_TRUNC = 92, // GenericOpcodes.td:1304
108 G_INTRINSIC_ROUND = 93, // GenericOpcodes.td:1310
109 G_INTRINSIC_LRINT = 94, // GenericOpcodes.td:1316
110 G_INTRINSIC_LLRINT = 95, // GenericOpcodes.td:1322
111 G_INTRINSIC_ROUNDEVEN = 96, // GenericOpcodes.td:1328
112 G_READCYCLECOUNTER = 97, // GenericOpcodes.td:1334
113 G_READSTEADYCOUNTER = 98, // GenericOpcodes.td:1340
114 G_LOAD = 99, // GenericOpcodes.td:1367
115 G_SEXTLOAD = 100, // GenericOpcodes.td:1376
116 G_ZEXTLOAD = 101, // GenericOpcodes.td:1384
117 G_FPEXTLOAD = 102, // GenericOpcodes.td:1393
118 G_INDEXED_LOAD = 103, // GenericOpcodes.td:1403
119 G_INDEXED_SEXTLOAD = 104, // GenericOpcodes.td:1412
120 G_INDEXED_ZEXTLOAD = 105, // GenericOpcodes.td:1420
121 G_STORE = 106, // GenericOpcodes.td:1428
122 G_FPTRUNCSTORE = 107, // GenericOpcodes.td:1438
123 G_INDEXED_STORE = 108, // GenericOpcodes.td:1446
124 G_ATOMIC_CMPXCHG_WITH_SUCCESS = 109, // GenericOpcodes.td:1457
125 G_ATOMIC_CMPXCHG = 110, // GenericOpcodes.td:1468
126 G_ATOMICRMW_XCHG = 111, // GenericOpcodes.td:1488
127 G_ATOMICRMW_ADD = 112, // GenericOpcodes.td:1489
128 G_ATOMICRMW_SUB = 113, // GenericOpcodes.td:1490
129 G_ATOMICRMW_AND = 114, // GenericOpcodes.td:1491
130 G_ATOMICRMW_NAND = 115, // GenericOpcodes.td:1492
131 G_ATOMICRMW_OR = 116, // GenericOpcodes.td:1493
132 G_ATOMICRMW_XOR = 117, // GenericOpcodes.td:1494
133 G_ATOMICRMW_MAX = 118, // GenericOpcodes.td:1495
134 G_ATOMICRMW_MIN = 119, // GenericOpcodes.td:1496
135 G_ATOMICRMW_UMAX = 120, // GenericOpcodes.td:1497
136 G_ATOMICRMW_UMIN = 121, // GenericOpcodes.td:1498
137 G_ATOMICRMW_FADD = 122, // GenericOpcodes.td:1509
138 G_ATOMICRMW_FSUB = 123, // GenericOpcodes.td:1510
139 G_ATOMICRMW_FMAX = 124, // GenericOpcodes.td:1511
140 G_ATOMICRMW_FMIN = 125, // GenericOpcodes.td:1512
141 G_ATOMICRMW_FMAXIMUM = 126, // GenericOpcodes.td:1513
142 G_ATOMICRMW_FMINIMUM = 127, // GenericOpcodes.td:1514
143 G_ATOMICRMW_FMAXIMUMNUM = 128, // GenericOpcodes.td:1515
144 G_ATOMICRMW_FMINIMUMNUM = 129, // GenericOpcodes.td:1516
145 G_ATOMICRMW_UINC_WRAP = 130, // GenericOpcodes.td:1499
146 G_ATOMICRMW_UDEC_WRAP = 131, // GenericOpcodes.td:1500
147 G_ATOMICRMW_USUB_COND = 132, // GenericOpcodes.td:1501
148 G_ATOMICRMW_USUB_SAT = 133, // GenericOpcodes.td:1502
149 G_FENCE = 134, // GenericOpcodes.td:1518
150 G_PREFETCH = 135, // GenericOpcodes.td:1525
151 G_BRCOND = 136, // GenericOpcodes.td:1665
152 G_BRINDIRECT = 137, // GenericOpcodes.td:1674
153 G_INVOKE_REGION_START = 138, // GenericOpcodes.td:1697
154 G_INTRINSIC = 139, // GenericOpcodes.td:1617
155 G_INTRINSIC_W_SIDE_EFFECTS = 140, // GenericOpcodes.td:1624
156 G_INTRINSIC_CONVERGENT = 141, // GenericOpcodes.td:1633
157 G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 142, // GenericOpcodes.td:1641
158 G_ANYEXT = 143, // GenericOpcodes.td:44
159 G_TRUNC = 144, // GenericOpcodes.td:83
160 G_TRUNC_SSAT_S = 145, // GenericOpcodes.td:91
161 G_TRUNC_SSAT_U = 146, // GenericOpcodes.td:98
162 G_TRUNC_USAT_U = 147, // GenericOpcodes.td:105
163 G_CONSTANT = 148, // GenericOpcodes.td:169
164 G_FCONSTANT = 149, // GenericOpcodes.td:177
165 G_VASTART = 150, // GenericOpcodes.td:184
166 G_VAARG = 151, // GenericOpcodes.td:191
167 G_SEXT = 152, // GenericOpcodes.td:52
168 G_SEXT_INREG = 153, // GenericOpcodes.td:66
169 G_ZEXT = 154, // GenericOpcodes.td:74
170 G_SHL = 155, // GenericOpcodes.td:404
171 G_LSHR = 156, // GenericOpcodes.td:411
172 G_ASHR = 157, // GenericOpcodes.td:418
173 G_FSHL = 158, // GenericOpcodes.td:470
174 G_FSHR = 159, // GenericOpcodes.td:478
175 G_ROTR = 160, // GenericOpcodes.td:485
176 G_ROTL = 161, // GenericOpcodes.td:492
177 G_ICMP = 162, // GenericOpcodes.td:499
178 G_FCMP = 163, // GenericOpcodes.td:506
179 G_SCMP = 164, // GenericOpcodes.td:513
180 G_UCMP = 165, // GenericOpcodes.td:520
181 G_SELECT = 166, // GenericOpcodes.td:527
182 G_UADDO = 167, // GenericOpcodes.td:619
183 G_UADDE = 168, // GenericOpcodes.td:627
184 G_USUBO = 169, // GenericOpcodes.td:649
185 G_USUBE = 170, // GenericOpcodes.td:655
186 G_SADDO = 171, // GenericOpcodes.td:634
187 G_SADDE = 172, // GenericOpcodes.td:642
188 G_SSUBO = 173, // GenericOpcodes.td:662
189 G_SSUBE = 174, // GenericOpcodes.td:669
190 G_UMULO = 175, // GenericOpcodes.td:676
191 G_SMULO = 176, // GenericOpcodes.td:684
192 G_UMULH = 177, // GenericOpcodes.td:693
193 G_SMULH = 178, // GenericOpcodes.td:702
194 G_UADDSAT = 179, // GenericOpcodes.td:714
195 G_SADDSAT = 180, // GenericOpcodes.td:722
196 G_USUBSAT = 181, // GenericOpcodes.td:730
197 G_SSUBSAT = 182, // GenericOpcodes.td:738
198 G_USHLSAT = 183, // GenericOpcodes.td:746
199 G_SSHLSAT = 184, // GenericOpcodes.td:754
200 G_SMULFIX = 185, // GenericOpcodes.td:766
201 G_UMULFIX = 186, // GenericOpcodes.td:773
202 G_SMULFIXSAT = 187, // GenericOpcodes.td:783
203 G_UMULFIXSAT = 188, // GenericOpcodes.td:790
204 G_SDIVFIX = 189, // GenericOpcodes.td:801
205 G_UDIVFIX = 190, // GenericOpcodes.td:808
206 G_SDIVFIXSAT = 191, // GenericOpcodes.td:818
207 G_UDIVFIXSAT = 192, // GenericOpcodes.td:825
208 G_FADD = 193, // GenericOpcodes.td:998
209 G_FSUB = 194, // GenericOpcodes.td:1006
210 G_FMUL = 195, // GenericOpcodes.td:1014
211 G_FMA = 196, // GenericOpcodes.td:1023
212 G_FMAD = 197, // GenericOpcodes.td:1032
213 G_FDIV = 198, // GenericOpcodes.td:1040
214 G_FREM = 199, // GenericOpcodes.td:1047
215 G_FMODF = 200, // GenericOpcodes.td:1054
216 G_FPOW = 201, // GenericOpcodes.td:1061
217 G_FPOWI = 202, // GenericOpcodes.td:1068
218 G_FEXP = 203, // GenericOpcodes.td:1075
219 G_FEXP2 = 204, // GenericOpcodes.td:1082
220 G_FEXP10 = 205, // GenericOpcodes.td:1089
221 G_FLOG = 206, // GenericOpcodes.td:1096
222 G_FLOG2 = 207, // GenericOpcodes.td:1103
223 G_FLOG10 = 208, // GenericOpcodes.td:1110
224 G_FLDEXP = 209, // GenericOpcodes.td:1117
225 G_FFREXP = 210, // GenericOpcodes.td:1124
226 G_FNEG = 211, // GenericOpcodes.td:836
227 G_FPEXT = 212, // GenericOpcodes.td:842
228 G_FPTRUNC = 213, // GenericOpcodes.td:848
229 G_FPTOSI = 214, // GenericOpcodes.td:854
230 G_FPTOUI = 215, // GenericOpcodes.td:860
231 G_SITOFP = 216, // GenericOpcodes.td:866
232 G_UITOFP = 217, // GenericOpcodes.td:872
233 G_FPTOSI_SAT = 218, // GenericOpcodes.td:878
234 G_FPTOUI_SAT = 219, // GenericOpcodes.td:884
235 G_FABS = 220, // GenericOpcodes.td:890
236 G_FCOPYSIGN = 221, // GenericOpcodes.td:896
237 G_IS_FPCLASS = 222, // GenericOpcodes.td:909
238 G_FCANONICALIZE = 223, // GenericOpcodes.td:902
239 G_FMINNUM = 224, // GenericOpcodes.td:922
240 G_FMAXNUM = 225, // GenericOpcodes.td:929
241 G_FMINNUM_IEEE = 226, // GenericOpcodes.td:947
242 G_FMAXNUM_IEEE = 227, // GenericOpcodes.td:954
243 G_FMINIMUM = 228, // GenericOpcodes.td:964
244 G_FMAXIMUM = 229, // GenericOpcodes.td:971
245 G_FMINIMUMNUM = 230, // GenericOpcodes.td:979
246 G_FMAXIMUMNUM = 231, // GenericOpcodes.td:986
247 G_GET_FPENV = 232, // GenericOpcodes.td:1254
248 G_SET_FPENV = 233, // GenericOpcodes.td:1261
249 G_RESET_FPENV = 234, // GenericOpcodes.td:1268
250 G_GET_FPMODE = 235, // GenericOpcodes.td:1275
251 G_SET_FPMODE = 236, // GenericOpcodes.td:1282
252 G_RESET_FPMODE = 237, // GenericOpcodes.td:1289
253 G_GET_ROUNDING = 238, // GenericOpcodes.td:1346
254 G_SET_ROUNDING = 239, // GenericOpcodes.td:1352
255 G_PTR_ADD = 240, // GenericOpcodes.td:534
256 G_PTRMASK = 241, // GenericOpcodes.td:542
257 G_SMIN = 242, // GenericOpcodes.td:549
258 G_SMAX = 243, // GenericOpcodes.td:557
259 G_UMIN = 244, // GenericOpcodes.td:565
260 G_UMAX = 245, // GenericOpcodes.td:573
261 G_ABS = 246, // GenericOpcodes.td:581
262 G_LROUND = 247, // GenericOpcodes.td:291
263 G_LLROUND = 248, // GenericOpcodes.td:297
264 G_BR = 249, // GenericOpcodes.td:1655
265 G_BRJT = 250, // GenericOpcodes.td:1685
266 G_VSCALE = 251, // GenericOpcodes.td:1583
267 G_INSERT_SUBVECTOR = 252, // GenericOpcodes.td:1729
268 G_EXTRACT_SUBVECTOR = 253, // GenericOpcodes.td:1737
269 G_INSERT_VECTOR_ELT = 254, // GenericOpcodes.td:1745
270 G_EXTRACT_VECTOR_ELT = 255, // GenericOpcodes.td:1753
271 G_SHUFFLE_VECTOR = 256, // GenericOpcodes.td:1764
272 G_SPLAT_VECTOR = 257, // GenericOpcodes.td:1772
273 G_STEP_VECTOR = 258, // GenericOpcodes.td:1780
274 G_VECTOR_COMPRESS = 259, // GenericOpcodes.td:1787
275 G_CTTZ = 260, // GenericOpcodes.td:211
276 G_CTTZ_ZERO_POISON = 261, // GenericOpcodes.td:217
277 G_CTLZ = 262, // GenericOpcodes.td:199
278 G_CTLZ_ZERO_POISON = 263, // GenericOpcodes.td:205
279 G_CTLS = 264, // GenericOpcodes.td:223
280 G_CTPOP = 265, // GenericOpcodes.td:229
281 G_BSWAP = 266, // GenericOpcodes.td:235
282 G_BITREVERSE = 267, // GenericOpcodes.td:242
283 G_CLMUL = 268, // GenericOpcodes.td:588
284 G_CLMULH = 269, // GenericOpcodes.td:596
285 G_CLMULR = 270, // GenericOpcodes.td:606
286 G_FCEIL = 271, // GenericOpcodes.td:1131
287 G_FCOS = 272, // GenericOpcodes.td:1138
288 G_FSIN = 273, // GenericOpcodes.td:1145
289 G_FSINCOS = 274, // GenericOpcodes.td:1152
290 G_FTAN = 275, // GenericOpcodes.td:1159
291 G_FACOS = 276, // GenericOpcodes.td:1166
292 G_FASIN = 277, // GenericOpcodes.td:1173
293 G_FATAN = 278, // GenericOpcodes.td:1180
294 G_FATAN2 = 279, // GenericOpcodes.td:1187
295 G_FCOSH = 280, // GenericOpcodes.td:1194
296 G_FSINH = 281, // GenericOpcodes.td:1201
297 G_FTANH = 282, // GenericOpcodes.td:1208
298 G_FSQRT = 283, // GenericOpcodes.td:1218
299 G_FFLOOR = 284, // GenericOpcodes.td:1225
300 G_FRINT = 285, // GenericOpcodes.td:1232
301 G_FNEARBYINT = 286, // GenericOpcodes.td:1239
302 G_ADDRSPACE_CAST = 287, // GenericOpcodes.td:248
303 G_BLOCK_ADDR = 288, // GenericOpcodes.td:254
304 G_JUMP_TABLE = 289, // GenericOpcodes.td:260
305 G_DYN_STACKALLOC = 290, // GenericOpcodes.td:266
306 G_STACKSAVE = 291, // GenericOpcodes.td:272
307 G_STACKRESTORE = 292, // GenericOpcodes.td:278
308 G_STRICT_FADD = 293, // GenericOpcodes.td:1839
309 G_STRICT_FSUB = 294, // GenericOpcodes.td:1840
310 G_STRICT_FMUL = 295, // GenericOpcodes.td:1841
311 G_STRICT_FDIV = 296, // GenericOpcodes.td:1842
312 G_STRICT_FREM = 297, // GenericOpcodes.td:1843
313 G_STRICT_FMA = 298, // GenericOpcodes.td:1844
314 G_STRICT_FSQRT = 299, // GenericOpcodes.td:1845
315 G_STRICT_FLDEXP = 300, // GenericOpcodes.td:1846
316 G_STRICT_FCMP = 301, // GenericOpcodes.td:1847
317 G_STRICT_FCMPS = 302, // GenericOpcodes.td:1848
318 G_READ_REGISTER = 303, // GenericOpcodes.td:1704
319 G_WRITE_REGISTER = 304, // GenericOpcodes.td:1714
320 G_MEMCPY = 305, // GenericOpcodes.td:1854
321 G_MEMCPY_INLINE = 306, // GenericOpcodes.td:1862
322 G_MEMMOVE = 307, // GenericOpcodes.td:1870
323 G_MEMSET = 308, // GenericOpcodes.td:1878
324 G_BZERO = 309, // GenericOpcodes.td:1885
325 G_MEMSET_INLINE = 310, // GenericOpcodes.td:1892
326 G_TRAP = 311, // GenericOpcodes.td:1902
327 G_DEBUGTRAP = 312, // GenericOpcodes.td:1909
328 G_UBSANTRAP = 313, // GenericOpcodes.td:1915
329 G_VECREDUCE_SEQ_FADD = 314, // GenericOpcodes.td:1803
330 G_VECREDUCE_SEQ_FMUL = 315, // GenericOpcodes.td:1809
331 G_VECREDUCE_FADD = 316, // GenericOpcodes.td:1815
332 G_VECREDUCE_FMUL = 317, // GenericOpcodes.td:1816
333 G_VECREDUCE_FMAX = 318, // GenericOpcodes.td:1818
334 G_VECREDUCE_FMIN = 319, // GenericOpcodes.td:1819
335 G_VECREDUCE_FMAXIMUM = 320, // GenericOpcodes.td:1820
336 G_VECREDUCE_FMINIMUM = 321, // GenericOpcodes.td:1821
337 G_VECREDUCE_FMAXIMUMNUM = 322, // GenericOpcodes.td:1822
338 G_VECREDUCE_FMINIMUMNUM = 323, // GenericOpcodes.td:1823
339 G_VECREDUCE_ADD = 324, // GenericOpcodes.td:1825
340 G_VECREDUCE_MUL = 325, // GenericOpcodes.td:1826
341 G_VECREDUCE_AND = 326, // GenericOpcodes.td:1827
342 G_VECREDUCE_OR = 327, // GenericOpcodes.td:1828
343 G_VECREDUCE_XOR = 328, // GenericOpcodes.td:1829
344 G_VECREDUCE_SMAX = 329, // GenericOpcodes.td:1830
345 G_VECREDUCE_SMIN = 330, // GenericOpcodes.td:1831
346 G_VECREDUCE_UMAX = 331, // GenericOpcodes.td:1832
347 G_VECREDUCE_UMIN = 332, // GenericOpcodes.td:1833
348 G_SBFX = 333, // GenericOpcodes.td:1927
349 G_UBFX = 334, // GenericOpcodes.td:1935
350 ADJCALLSTACKDOWN = 335, // LanaiInstrInfo.td:754
351 ADJCALLSTACKUP = 336, // LanaiInstrInfo.td:757
352 ADJDYNALLOC = 337, // LanaiInstrInfo.td:763
353 CALL = 338, // LanaiInstrInfo.td:728
354 CALLR = 339, // LanaiInstrInfo.td:729
355 ADDC_F_I_HI = 340, // LanaiInstrInfo.td:281
356 ADDC_F_I_LO = 341, // LanaiInstrInfo.td:277
357 ADDC_F_R = 342, // LanaiInstrInfo.td:293
358 ADDC_I_HI = 343, // LanaiInstrInfo.td:281
359 ADDC_I_LO = 344, // LanaiInstrInfo.td:277
360 ADDC_R = 345, // LanaiInstrInfo.td:293
361 ADD_F_I_HI = 346, // LanaiInstrInfo.td:281
362 ADD_F_I_LO = 347, // LanaiInstrInfo.td:277
363 ADD_F_R = 348, // LanaiInstrInfo.td:293
364 ADD_I_HI = 349, // LanaiInstrInfo.td:281
365 ADD_I_LO = 350, // LanaiInstrInfo.td:277
366 ADD_R = 351, // LanaiInstrInfo.td:293
367 AND_F_I_HI = 352, // LanaiInstrInfo.td:281
368 AND_F_I_LO = 353, // LanaiInstrInfo.td:277
369 AND_F_R = 354, // LanaiInstrInfo.td:306
370 AND_I_HI = 355, // LanaiInstrInfo.td:281
371 AND_I_LO = 356, // LanaiInstrInfo.td:277
372 AND_R = 357, // LanaiInstrInfo.td:306
373 BRCC = 358, // LanaiInstrInfo.td:686
374 BRIND_CC = 359, // LanaiInstrInfo.td:789
375 BRIND_CCA = 360, // LanaiInstrInfo.td:797
376 BRR = 361, // LanaiInstrInfo.td:809
377 BT = 362, // LanaiInstrInfo.td:679
378 JR = 363, // LanaiInstrInfo.td:691
379 LDADDR = 364, // LanaiInstrInfo.td:542
380 LDBs_RI = 365, // LanaiInstrInfo.td:580
381 LDBs_RR = 366, // LanaiInstrInfo.td:539
382 LDBz_RI = 367, // LanaiInstrInfo.td:577
383 LDBz_RR = 368, // LanaiInstrInfo.td:532
384 LDHs_RI = 369, // LanaiInstrInfo.td:574
385 LDHs_RR = 370, // LanaiInstrInfo.td:537
386 LDHz_RI = 371, // LanaiInstrInfo.td:571
387 LDHz_RR = 372, // LanaiInstrInfo.td:530
388 LDW_RI = 373, // LanaiInstrInfo.td:515
389 LDW_RR = 374, // LanaiInstrInfo.td:516
390 LDWz_RR = 375, // LanaiInstrInfo.td:524
391 LEADZ = 376, // LanaiInstrInfo.td:819
392 LOG0 = 377, // LanaiInstrInfo.td:249
393 LOG1 = 378, // LanaiInstrInfo.td:251
394 LOG2 = 379, // LanaiInstrInfo.td:253
395 LOG3 = 380, // LanaiInstrInfo.td:255
396 LOG4 = 381, // LanaiInstrInfo.td:257
397 MOVHI = 382, // LanaiInstrInfo.td:408
398 NOP = 383, // LanaiInstrInfo.td:245
399 OR_F_I_HI = 384, // LanaiInstrInfo.td:281
400 OR_F_I_LO = 385, // LanaiInstrInfo.td:277
401 OR_F_R = 386, // LanaiInstrInfo.td:306
402 OR_I_HI = 387, // LanaiInstrInfo.td:281
403 OR_I_LO = 388, // LanaiInstrInfo.td:277
404 OR_R = 389, // LanaiInstrInfo.td:306
405 POPC = 390, // LanaiInstrInfo.td:814
406 RET = 391, // LanaiInstrInfo.td:734
407 SA_F_I = 392, // LanaiInstrInfo.td:439
408 SA_I = 393, // LanaiInstrInfo.td:430
409 SCC = 394, // LanaiInstrInfo.td:769
410 SELECT = 395, // LanaiInstrInfo.td:776
411 SFSUB_F_RI_HI = 396, // LanaiInstrInfo.td:717
412 SFSUB_F_RI_LO = 397, // LanaiInstrInfo.td:713
413 SFSUB_F_RR = 398, // LanaiInstrInfo.td:709
414 SHL_F_R = 399, // LanaiInstrInfo.td:460
415 SHL_R = 400, // LanaiInstrInfo.td:448
416 SLI = 401, // LanaiInstrInfo.td:582
417 SL_F_I = 402, // LanaiInstrInfo.td:437
418 SL_I = 403, // LanaiInstrInfo.td:428
419 SRA_F_R = 404, // LanaiInstrInfo.td:466
420 SRA_R = 405, // LanaiInstrInfo.td:455
421 SRL_F_R = 406, // LanaiInstrInfo.td:463
422 SRL_R = 407, // LanaiInstrInfo.td:452
423 STADDR = 408, // LanaiInstrInfo.td:641
424 STB_RI = 409, // LanaiInstrInfo.td:672
425 STB_RR = 410, // LanaiInstrInfo.td:638
426 STH_RI = 411, // LanaiInstrInfo.td:669
427 STH_RR = 412, // LanaiInstrInfo.td:636
428 SUBB_F_I_HI = 413, // LanaiInstrInfo.td:281
429 SUBB_F_I_LO = 414, // LanaiInstrInfo.td:277
430 SUBB_F_R = 415, // LanaiInstrInfo.td:293
431 SUBB_I_HI = 416, // LanaiInstrInfo.td:281
432 SUBB_I_LO = 417, // LanaiInstrInfo.td:277
433 SUBB_R = 418, // LanaiInstrInfo.td:293
434 SUB_F_I_HI = 419, // LanaiInstrInfo.td:281
435 SUB_F_I_LO = 420, // LanaiInstrInfo.td:277
436 SUB_F_R = 421, // LanaiInstrInfo.td:293
437 SUB_I_HI = 422, // LanaiInstrInfo.td:281
438 SUB_I_LO = 423, // LanaiInstrInfo.td:277
439 SUB_R = 424, // LanaiInstrInfo.td:293
440 SW_RI = 425, // LanaiInstrInfo.td:631
441 SW_RR = 426, // LanaiInstrInfo.td:630
442 TRAILZ = 427, // LanaiInstrInfo.td:823
443 XOR_F_I_HI = 428, // LanaiInstrInfo.td:281
444 XOR_F_I_LO = 429, // LanaiInstrInfo.td:277
445 XOR_F_R = 430, // LanaiInstrInfo.td:306
446 XOR_I_HI = 431, // LanaiInstrInfo.td:281
447 XOR_I_LO = 432, // LanaiInstrInfo.td:277
448 XOR_R = 433, // LanaiInstrInfo.td:306
449 INSTRUCTION_LIST_END = 434
450 };
451
452} // namespace llvm::Lanai
453
454#endif // GET_INSTRINFO_ENUM
455
456#ifdef GET_INSTRINFO_SCHED_ENUM
457#undef GET_INSTRINFO_SCHED_ENUM
458
459namespace llvm::Lanai::Sched {
460
461 enum {
462 NoInstrModel = 0,
463 IIC_ALU_WriteALU = 1,
464 IIC_ALU = 2,
465 IIC_LD_WriteLD = 3,
466 IIC_LDSW_WriteLDSW = 4,
467 WriteLD = 5,
468 IIC_ST_WriteST = 6,
469 IIC_STSW_WriteSTSW = 7,
470 SCHED_LIST_END = 8
471 };
472
473} // namespace llvm::Lanai::Sched
474
475#endif // GET_INSTRINFO_SCHED_ENUM
476
477#if defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
478
479namespace llvm {
480
481struct LanaiInstrTable {
482 MCInstrDesc Insts[434];
483 static_assert(alignof(MCInstrDesc) >= alignof(MCPhysReg), "Unwanted padding between Insts and ImplicitOps");
484 MCPhysReg ImplicitOps[8];
485 char Padding[sizeof(MCOperandInfo) - sizeof ImplicitOps % sizeof(MCOperandInfo)];
486 static_assert(alignof(MCInstrDesc) >= alignof(MCOperandInfo), "Unwanted padding between Insts and OperandInfo");
487 MCOperandInfo OperandInfo[174];
488};
489} // namespace llvm
490
491#endif // defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
492
493#ifdef GET_INSTRINFO_MC_DESC
494#undef GET_INSTRINFO_MC_DESC
495
496namespace llvm {
497
498static_assert((sizeof LanaiInstrTable::ImplicitOps + sizeof LanaiInstrTable::Padding) % sizeof(MCOperandInfo) == 0);
499static constexpr unsigned LanaiOpInfoBase = (sizeof LanaiInstrTable::ImplicitOps + sizeof LanaiInstrTable::Padding) / sizeof(MCOperandInfo);
500
501extern const LanaiInstrTable LanaiDescs = {
502 {
503 { 433, 4, 1, 4, 1, 0, 0, LanaiOpInfoBase + 156, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR_R
504 { 432, 3, 1, 4, 1, 0, 0, LanaiOpInfoBase + 153, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR_I_LO
505 { 431, 3, 1, 4, 1, 0, 0, LanaiOpInfoBase + 153, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR_I_HI
506 { 430, 4, 1, 4, 1, 0, 1, LanaiOpInfoBase + 156, 6, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR_F_R
507 { 429, 3, 1, 4, 1, 0, 1, LanaiOpInfoBase + 153, 6, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR_F_I_LO
508 { 428, 3, 1, 4, 1, 0, 1, LanaiOpInfoBase + 153, 6, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR_F_I_HI
509 { 427, 2, 1, 4, 1, 0, 0, LanaiOpInfoBase + 151, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TRAILZ
510 { 426, 4, 0, 4, 6, 0, 0, LanaiOpInfoBase + 166, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SW_RR
511 { 425, 4, 0, 4, 6, 0, 0, LanaiOpInfoBase + 162, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SW_RI
512 { 424, 4, 1, 4, 1, 0, 0, LanaiOpInfoBase + 156, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_R
513 { 423, 3, 1, 4, 1, 0, 0, LanaiOpInfoBase + 153, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_I_LO
514 { 422, 3, 1, 4, 1, 0, 0, LanaiOpInfoBase + 153, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_I_HI
515 { 421, 4, 1, 4, 1, 0, 1, LanaiOpInfoBase + 156, 6, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_F_R
516 { 420, 3, 1, 4, 1, 0, 1, LanaiOpInfoBase + 153, 6, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_F_I_LO
517 { 419, 3, 1, 4, 1, 0, 1, LanaiOpInfoBase + 153, 6, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_F_I_HI
518 { 418, 4, 1, 4, 1, 1, 0, LanaiOpInfoBase + 156, 6, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBB_R
519 { 417, 3, 1, 4, 1, 1, 0, LanaiOpInfoBase + 153, 6, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBB_I_LO
520 { 416, 3, 1, 4, 1, 1, 0, LanaiOpInfoBase + 153, 6, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBB_I_HI
521 { 415, 4, 1, 4, 1, 1, 1, LanaiOpInfoBase + 156, 4, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBB_F_R
522 { 414, 3, 1, 4, 1, 1, 1, LanaiOpInfoBase + 153, 4, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBB_F_I_LO
523 { 413, 3, 1, 4, 1, 1, 1, LanaiOpInfoBase + 153, 4, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBB_F_I_HI
524 { 412, 4, 0, 4, 6, 0, 0, LanaiOpInfoBase + 166, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STH_RR
525 { 411, 4, 0, 4, 7, 0, 0, LanaiOpInfoBase + 162, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STH_RI
526 { 410, 4, 0, 4, 6, 0, 0, LanaiOpInfoBase + 166, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STB_RR
527 { 409, 4, 0, 4, 7, 0, 0, LanaiOpInfoBase + 162, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STB_RI
528 { 408, 2, 0, 4, 6, 0, 0, LanaiOpInfoBase + 34, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STADDR
529 { 407, 4, 1, 4, 1, 0, 0, LanaiOpInfoBase + 156, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SRL_R
530 { 406, 4, 1, 4, 1, 0, 1, LanaiOpInfoBase + 156, 6, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SRL_F_R
531 { 405, 4, 1, 4, 1, 0, 0, LanaiOpInfoBase + 156, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SRA_R
532 { 404, 4, 1, 4, 1, 0, 1, LanaiOpInfoBase + 156, 6, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SRA_F_R
533 { 403, 3, 1, 4, 1, 0, 0, LanaiOpInfoBase + 153, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SL_I
534 { 402, 3, 1, 4, 1, 0, 1, LanaiOpInfoBase + 153, 6, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SL_F_I
535 { 401, 2, 1, 4, 0, 0, 0, LanaiOpInfoBase + 34, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SLI
536 { 400, 4, 1, 4, 1, 0, 0, LanaiOpInfoBase + 156, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHL_R
537 { 399, 4, 1, 4, 1, 0, 1, LanaiOpInfoBase + 156, 6, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHL_F_R
538 { 398, 2, 0, 4, 1, 0, 1, LanaiOpInfoBase + 151, 6, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SFSUB_F_RR
539 { 397, 2, 0, 4, 1, 0, 1, LanaiOpInfoBase + 34, 6, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SFSUB_F_RI_LO
540 { 396, 2, 0, 4, 1, 0, 1, LanaiOpInfoBase + 34, 6, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SFSUB_F_RI_HI
541 { 395, 4, 1, 4, 1, 1, 0, LanaiOpInfoBase + 170, 6, 0|(1ULL<<MCID::Select)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SELECT
542 { 394, 2, 1, 4, 2, 1, 0, LanaiOpInfoBase + 34, 6, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SCC
543 { 393, 3, 1, 4, 1, 0, 0, LanaiOpInfoBase + 153, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SA_I
544 { 392, 3, 1, 4, 1, 0, 1, LanaiOpInfoBase + 153, 6, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SA_F_I
545 { 391, 0, 0, 4, 0, 1, 0, LanaiOpInfoBase + 1, 7, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RET
546 { 390, 2, 1, 4, 1, 0, 0, LanaiOpInfoBase + 151, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // POPC
547 { 389, 4, 1, 4, 1, 0, 0, LanaiOpInfoBase + 156, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OR_R
548 { 388, 3, 1, 4, 1, 0, 0, LanaiOpInfoBase + 153, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OR_I_LO
549 { 387, 3, 1, 4, 1, 0, 0, LanaiOpInfoBase + 153, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OR_I_HI
550 { 386, 4, 1, 4, 1, 0, 1, LanaiOpInfoBase + 156, 6, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OR_F_R
551 { 385, 3, 1, 4, 1, 0, 1, LanaiOpInfoBase + 153, 6, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OR_F_I_LO
552 { 384, 3, 1, 4, 1, 0, 1, LanaiOpInfoBase + 153, 6, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OR_F_I_HI
553 { 383, 0, 0, 4, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NOP
554 { 382, 2, 1, 4, 1, 0, 0, LanaiOpInfoBase + 34, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOVHI
555 { 381, 0, 0, 4, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOG4
556 { 380, 0, 0, 4, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOG3
557 { 379, 0, 0, 4, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOG2
558 { 378, 0, 0, 4, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOG1
559 { 377, 0, 0, 4, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOG0
560 { 376, 2, 1, 4, 1, 0, 0, LanaiOpInfoBase + 151, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LEADZ
561 { 375, 4, 1, 4, 5, 0, 0, LanaiOpInfoBase + 166, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDWz_RR
562 { 374, 4, 1, 4, 5, 0, 0, LanaiOpInfoBase + 166, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDW_RR
563 { 373, 4, 1, 4, 3, 0, 0, LanaiOpInfoBase + 162, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDW_RI
564 { 372, 4, 1, 4, 5, 0, 0, LanaiOpInfoBase + 166, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDHz_RR
565 { 371, 4, 1, 4, 4, 0, 0, LanaiOpInfoBase + 162, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDHz_RI
566 { 370, 4, 1, 4, 5, 0, 0, LanaiOpInfoBase + 166, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDHs_RR
567 { 369, 4, 1, 4, 4, 0, 0, LanaiOpInfoBase + 162, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDHs_RI
568 { 368, 4, 1, 4, 5, 0, 0, LanaiOpInfoBase + 166, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDBz_RR
569 { 367, 4, 1, 4, 4, 0, 0, LanaiOpInfoBase + 162, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDBz_RI
570 { 366, 4, 1, 4, 5, 0, 0, LanaiOpInfoBase + 166, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDBs_RR
571 { 365, 4, 1, 4, 4, 0, 0, LanaiOpInfoBase + 162, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDBs_RI
572 { 364, 2, 1, 4, 3, 0, 0, LanaiOpInfoBase + 34, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDADDR
573 { 363, 1, 0, 4, 1, 0, 0, LanaiOpInfoBase + 28, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JR
574 { 362, 1, 0, 4, 2, 0, 0, LanaiOpInfoBase + 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BT
575 { 361, 2, 0, 4, 0, 1, 0, LanaiOpInfoBase + 160, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BRR
576 { 360, 3, 0, 4, 1, 1, 0, LanaiOpInfoBase + 153, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BRIND_CCA
577 { 359, 2, 0, 4, 1, 1, 0, LanaiOpInfoBase + 34, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BRIND_CC
578 { 358, 2, 0, 4, 2, 1, 0, LanaiOpInfoBase + 9, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BRCC
579 { 357, 4, 1, 4, 1, 0, 0, LanaiOpInfoBase + 156, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND_R
580 { 356, 3, 1, 4, 1, 0, 0, LanaiOpInfoBase + 153, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND_I_LO
581 { 355, 3, 1, 4, 1, 0, 0, LanaiOpInfoBase + 153, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND_I_HI
582 { 354, 4, 1, 4, 1, 0, 1, LanaiOpInfoBase + 156, 6, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND_F_R
583 { 353, 3, 1, 4, 1, 0, 1, LanaiOpInfoBase + 153, 6, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND_F_I_LO
584 { 352, 3, 1, 4, 1, 0, 1, LanaiOpInfoBase + 153, 6, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND_F_I_HI
585 { 351, 4, 1, 4, 1, 0, 0, LanaiOpInfoBase + 156, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_R
586 { 350, 3, 1, 4, 1, 0, 0, LanaiOpInfoBase + 153, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_I_LO
587 { 349, 3, 1, 4, 1, 0, 0, LanaiOpInfoBase + 153, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_I_HI
588 { 348, 4, 1, 4, 1, 0, 1, LanaiOpInfoBase + 156, 6, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_F_R
589 { 347, 3, 1, 4, 1, 0, 1, LanaiOpInfoBase + 153, 6, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_F_I_LO
590 { 346, 3, 1, 4, 1, 0, 1, LanaiOpInfoBase + 153, 6, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_F_I_HI
591 { 345, 4, 1, 4, 1, 1, 0, LanaiOpInfoBase + 156, 6, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC_R
592 { 344, 3, 1, 4, 1, 1, 0, LanaiOpInfoBase + 153, 6, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC_I_LO
593 { 343, 3, 1, 4, 1, 1, 0, LanaiOpInfoBase + 153, 6, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC_I_HI
594 { 342, 4, 1, 4, 1, 1, 1, LanaiOpInfoBase + 156, 4, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC_F_R
595 { 341, 3, 1, 4, 1, 1, 1, LanaiOpInfoBase + 153, 4, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC_F_I_LO
596 { 340, 3, 1, 4, 1, 1, 1, LanaiOpInfoBase + 153, 4, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC_F_I_HI
597 { 339, 1, 0, 4, 0, 1, 1, LanaiOpInfoBase + 28, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CALLR
598 { 338, 1, 0, 4, 0, 1, 1, LanaiOpInfoBase + 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CALL
599 { 337, 2, 1, 4, 0, 1, 1, LanaiOpInfoBase + 151, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADJDYNALLOC
600 { 336, 2, 0, 4, 0, 1, 1, LanaiOpInfoBase + 20, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADJCALLSTACKUP
601 { 335, 2, 0, 4, 0, 1, 1, LanaiOpInfoBase + 20, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADJCALLSTACKDOWN
602 { 334, 4, 1, 0, 0, 0, 0, LanaiOpInfoBase + 147, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UBFX
603 { 333, 4, 1, 0, 0, 0, 0, LanaiOpInfoBase + 147, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SBFX
604 { 332, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_UMIN
605 { 331, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_UMAX
606 { 330, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SMIN
607 { 329, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SMAX
608 { 328, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_XOR
609 { 327, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_OR
610 { 326, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_AND
611 { 325, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_MUL
612 { 324, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_ADD
613 { 323, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMINIMUMNUM
614 { 322, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMAXIMUMNUM
615 { 321, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMINIMUM
616 { 320, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMAXIMUM
617 { 319, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMIN
618 { 318, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMAX
619 { 317, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMUL
620 { 316, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FADD
621 { 315, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SEQ_FMUL
622 { 314, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SEQ_FADD
623 { 313, 1, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UBSANTRAP
624 { 312, 0, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_DEBUGTRAP
625 { 311, 0, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRAP
626 { 310, 3, 0, 0, 0, 0, 0, LanaiOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMSET_INLINE
627 { 309, 3, 0, 0, 0, 0, 0, LanaiOpInfoBase + 57, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BZERO
628 { 308, 4, 0, 0, 0, 0, 0, LanaiOpInfoBase + 143, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMSET
629 { 307, 4, 0, 0, 0, 0, 0, LanaiOpInfoBase + 143, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMMOVE
630 { 306, 3, 0, 0, 0, 0, 0, LanaiOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMCPY_INLINE
631 { 305, 4, 0, 0, 0, 0, 0, LanaiOpInfoBase + 143, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMCPY
632 { 304, 2, 0, 0, 0, 0, 0, LanaiOpInfoBase + 141, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_WRITE_REGISTER
633 { 303, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_READ_REGISTER
634 { 302, 4, 1, 0, 0, 0, 0, LanaiOpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FCMPS
635 { 301, 4, 1, 0, 0, 0, 0, LanaiOpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FCMP
636 { 300, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FLDEXP
637 { 299, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FSQRT
638 { 298, 4, 1, 0, 0, 0, 0, LanaiOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FMA
639 { 297, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FREM
640 { 296, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FDIV
641 { 295, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FMUL
642 { 294, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FSUB
643 { 293, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FADD
644 { 292, 1, 0, 0, 0, 0, 0, LanaiOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STACKRESTORE
645 { 291, 1, 1, 0, 0, 0, 0, LanaiOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STACKSAVE
646 { 290, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 68, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_DYN_STACKALLOC
647 { 289, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_JUMP_TABLE
648 { 288, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BLOCK_ADDR
649 { 287, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ADDRSPACE_CAST
650 { 286, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FNEARBYINT
651 { 285, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FRINT
652 { 284, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FFLOOR
653 { 283, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSQRT
654 { 282, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FTANH
655 { 281, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSINH
656 { 280, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCOSH
657 { 279, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FATAN2
658 { 278, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FATAN
659 { 277, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FASIN
660 { 276, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FACOS
661 { 275, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FTAN
662 { 274, 3, 2, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSINCOS
663 { 273, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSIN
664 { 272, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCOS
665 { 271, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCEIL
666 { 270, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CLMULR
667 { 269, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CLMULH
668 { 268, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CLMUL
669 { 267, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BITREVERSE
670 { 266, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BSWAP
671 { 265, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTPOP
672 { 264, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTLS
673 { 263, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTLZ_ZERO_POISON
674 { 262, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTLZ
675 { 261, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTTZ_ZERO_POISON
676 { 260, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTTZ
677 { 259, 4, 1, 0, 0, 0, 0, LanaiOpInfoBase + 137, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECTOR_COMPRESS
678 { 258, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STEP_VECTOR
679 { 257, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SPLAT_VECTOR
680 { 256, 4, 1, 0, 0, 0, 0, LanaiOpInfoBase + 133, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SHUFFLE_VECTOR
681 { 255, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_EXTRACT_VECTOR_ELT
682 { 254, 4, 1, 0, 0, 0, 0, LanaiOpInfoBase + 126, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INSERT_VECTOR_ELT
683 { 253, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 57, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_EXTRACT_SUBVECTOR
684 { 252, 4, 1, 0, 0, 0, 0, LanaiOpInfoBase + 62, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INSERT_SUBVECTOR
685 { 251, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VSCALE
686 { 250, 3, 0, 0, 0, 0, 0, LanaiOpInfoBase + 123, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BRJT
687 { 249, 1, 0, 0, 0, 0, 0, LanaiOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BR
688 { 248, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LLROUND
689 { 247, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LROUND
690 { 246, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ABS
691 { 245, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMAX
692 { 244, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMIN
693 { 243, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMAX
694 { 242, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMIN
695 { 241, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTRMASK
696 { 240, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTR_ADD
697 { 239, 1, 0, 0, 0, 0, 0, LanaiOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SET_ROUNDING
698 { 238, 1, 1, 0, 0, 0, 0, LanaiOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GET_ROUNDING
699 { 237, 0, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_RESET_FPMODE
700 { 236, 1, 0, 0, 0, 0, 0, LanaiOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SET_FPMODE
701 { 235, 1, 1, 0, 0, 0, 0, LanaiOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GET_FPMODE
702 { 234, 0, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_RESET_FPENV
703 { 233, 1, 0, 0, 0, 0, 0, LanaiOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SET_FPENV
704 { 232, 1, 1, 0, 0, 0, 0, LanaiOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GET_FPENV
705 { 231, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXIMUMNUM
706 { 230, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINIMUMNUM
707 { 229, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXIMUM
708 { 228, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINIMUM
709 { 227, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXNUM_IEEE
710 { 226, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINNUM_IEEE
711 { 225, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXNUM
712 { 224, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINNUM
713 { 223, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCANONICALIZE
714 { 222, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 97, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_IS_FPCLASS
715 { 221, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCOPYSIGN
716 { 220, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FABS
717 { 219, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOUI_SAT
718 { 218, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOSI_SAT
719 { 217, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UITOFP
720 { 216, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SITOFP
721 { 215, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOUI
722 { 214, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOSI
723 { 213, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTRUNC
724 { 212, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPEXT
725 { 211, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FNEG
726 { 210, 3, 2, 0, 0, 0, 0, LanaiOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FFREXP
727 { 209, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLDEXP
728 { 208, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLOG10
729 { 207, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLOG2
730 { 206, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLOG
731 { 205, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FEXP10
732 { 204, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FEXP2
733 { 203, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FEXP
734 { 202, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPOWI
735 { 201, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPOW
736 { 200, 3, 2, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMODF
737 { 199, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FREM
738 { 198, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FDIV
739 { 197, 4, 1, 0, 0, 0, 0, LanaiOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAD
740 { 196, 4, 1, 0, 0, 0, 0, LanaiOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMA
741 { 195, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMUL
742 { 194, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSUB
743 { 193, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FADD
744 { 192, 4, 1, 0, 0, 0, 0, LanaiOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIVFIXSAT
745 { 191, 4, 1, 0, 0, 0, 0, LanaiOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIVFIXSAT
746 { 190, 4, 1, 0, 0, 0, 0, LanaiOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIVFIX
747 { 189, 4, 1, 0, 0, 0, 0, LanaiOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIVFIX
748 { 188, 4, 1, 0, 0, 0, 0, LanaiOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULFIXSAT
749 { 187, 4, 1, 0, 0, 0, 0, LanaiOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULFIXSAT
750 { 186, 4, 1, 0, 0, 0, 0, LanaiOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULFIX
751 { 185, 4, 1, 0, 0, 0, 0, LanaiOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULFIX
752 { 184, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSHLSAT
753 { 183, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USHLSAT
754 { 182, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSUBSAT
755 { 181, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USUBSAT
756 { 180, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SADDSAT
757 { 179, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UADDSAT
758 { 178, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULH
759 { 177, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULH
760 { 176, 4, 2, 0, 0, 0, 0, LanaiOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULO
761 { 175, 4, 2, 0, 0, 0, 0, LanaiOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULO
762 { 174, 5, 2, 0, 0, 0, 0, LanaiOpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSUBE
763 { 173, 4, 2, 0, 0, 0, 0, LanaiOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSUBO
764 { 172, 5, 2, 0, 0, 0, 0, LanaiOpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SADDE
765 { 171, 4, 2, 0, 0, 0, 0, LanaiOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SADDO
766 { 170, 5, 2, 0, 0, 0, 0, LanaiOpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USUBE
767 { 169, 4, 2, 0, 0, 0, 0, LanaiOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USUBO
768 { 168, 5, 2, 0, 0, 0, 0, LanaiOpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UADDE
769 { 167, 4, 2, 0, 0, 0, 0, LanaiOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UADDO
770 { 166, 4, 1, 0, 0, 0, 0, LanaiOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SELECT
771 { 165, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 111, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UCMP
772 { 164, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 111, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SCMP
773 { 163, 4, 1, 0, 0, 0, 0, LanaiOpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCMP
774 { 162, 4, 1, 0, 0, 0, 0, LanaiOpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ICMP
775 { 161, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ROTL
776 { 160, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ROTR
777 { 159, 4, 1, 0, 0, 0, 0, LanaiOpInfoBase + 103, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSHR
778 { 158, 4, 1, 0, 0, 0, 0, LanaiOpInfoBase + 103, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSHL
779 { 157, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASHR
780 { 156, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LSHR
781 { 155, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SHL
782 { 154, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ZEXT
783 { 153, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SEXT_INREG
784 { 152, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SEXT
785 { 151, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 97, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VAARG
786 { 150, 1, 0, 0, 0, 0, 0, LanaiOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VASTART
787 { 149, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCONSTANT
788 { 148, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONSTANT
789 { 147, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC_USAT_U
790 { 146, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC_SSAT_U
791 { 145, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC_SSAT_S
792 { 144, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC
793 { 143, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ANYEXT
794 { 142, 1, 0, 0, 0, 0, 0, LanaiOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
795 { 141, 1, 0, 0, 0, 0, 0, LanaiOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_INTRINSIC_CONVERGENT
796 { 140, 1, 0, 0, 0, 0, 0, LanaiOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_W_SIDE_EFFECTS
797 { 139, 1, 0, 0, 0, 0, 0, LanaiOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC
798 { 138, 0, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INVOKE_REGION_START
799 { 137, 1, 0, 0, 0, 0, 0, LanaiOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BRINDIRECT
800 { 136, 2, 0, 0, 0, 0, 0, LanaiOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BRCOND
801 { 135, 4, 0, 0, 0, 0, 0, LanaiOpInfoBase + 93, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PREFETCH
802 { 134, 2, 0, 0, 0, 0, 0, LanaiOpInfoBase + 20, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FENCE
803 { 133, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_USUB_SAT
804 { 132, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_USUB_COND
805 { 131, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UDEC_WRAP
806 { 130, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UINC_WRAP
807 { 129, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMINIMUMNUM
808 { 128, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMAXIMUMNUM
809 { 127, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMINIMUM
810 { 126, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMAXIMUM
811 { 125, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMIN
812 { 124, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMAX
813 { 123, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FSUB
814 { 122, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FADD
815 { 121, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UMIN
816 { 120, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UMAX
817 { 119, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_MIN
818 { 118, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_MAX
819 { 117, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_XOR
820 { 116, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_OR
821 { 115, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_NAND
822 { 114, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_AND
823 { 113, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_SUB
824 { 112, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_ADD
825 { 111, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_XCHG
826 { 110, 4, 1, 0, 0, 0, 0, LanaiOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMIC_CMPXCHG
827 { 109, 5, 2, 0, 0, 0, 0, LanaiOpInfoBase + 81, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
828 { 108, 5, 1, 0, 0, 0, 0, LanaiOpInfoBase + 76, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_STORE
829 { 107, 2, 0, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTRUNCSTORE
830 { 106, 2, 0, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STORE
831 { 105, 5, 2, 0, 0, 0, 0, LanaiOpInfoBase + 71, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_ZEXTLOAD
832 { 104, 5, 2, 0, 0, 0, 0, LanaiOpInfoBase + 71, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_SEXTLOAD
833 { 103, 5, 2, 0, 0, 0, 0, LanaiOpInfoBase + 71, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_LOAD
834 { 102, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPEXTLOAD
835 { 101, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ZEXTLOAD
836 { 100, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SEXTLOAD
837 { 99, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LOAD
838 { 98, 1, 1, 0, 0, 0, 0, LanaiOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_READSTEADYCOUNTER
839 { 97, 1, 1, 0, 0, 0, 0, LanaiOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_READCYCLECOUNTER
840 { 96, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_ROUNDEVEN
841 { 95, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_LLRINT
842 { 94, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_LRINT
843 { 93, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_ROUND
844 { 92, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_TRUNC
845 { 91, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 68, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_FPTRUNC_ROUND
846 { 90, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONSTANT_FOLD_BARRIER
847 { 89, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FREEZE
848 { 88, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BITCAST
849 { 87, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTTOPTR
850 { 86, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTRTOINT
851 { 85, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONCAT_VECTORS
852 { 84, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BUILD_VECTOR_TRUNC
853 { 83, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BUILD_VECTOR
854 { 82, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MERGE_VALUES
855 { 81, 4, 1, 0, 0, 0, 0, LanaiOpInfoBase + 62, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INSERT
856 { 80, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UNMERGE_VALUES
857 { 79, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 57, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_EXTRACT
858 { 78, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONSTANT_POOL
859 { 77, 5, 1, 0, 0, 0, 0, LanaiOpInfoBase + 52, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTRAUTH_GLOBAL_VALUE
860 { 76, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GLOBAL_VALUE
861 { 75, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FRAME_INDEX
862 { 74, 1, 1, 0, 0, 0, 0, LanaiOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PHI
863 { 73, 1, 1, 0, 0, 0, 0, LanaiOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_IMPLICIT_DEF
864 { 72, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SAVGCEIL
865 { 71, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SAVGFLOOR
866 { 70, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UAVGCEIL
867 { 69, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UAVGFLOOR
868 { 68, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ABDU
869 { 67, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ABDS
870 { 66, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_XOR
871 { 65, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_OR
872 { 64, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_AND
873 { 63, 4, 2, 0, 0, 0, 0, LanaiOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIVREM
874 { 62, 4, 2, 0, 0, 0, 0, LanaiOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIVREM
875 { 61, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UREM
876 { 60, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SREM
877 { 59, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIV
878 { 58, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIV
879 { 57, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MUL
880 { 56, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SUB
881 { 55, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ADD
882 { 54, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASSERT_ALIGN
883 { 53, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASSERT_ZEXT
884 { 52, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASSERT_SEXT
885 { 51, 1, 0, 0, 0, 0, 0, LanaiOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_GLUE
886 { 50, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_LOOP
887 { 49, 1, 1, 0, 0, 0, 0, LanaiOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_ANCHOR
888 { 48, 1, 1, 0, 0, 0, 0, LanaiOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_ENTRY
889 { 47, 1, 0, 0, 0, 0, 0, LanaiOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RELOC_NONE
890 { 46, 1, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JUMP_TABLE_DEBUG_INFO
891 { 45, 0, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMBARRIER
892 { 44, 0, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FAKE_USE
893 { 43, 0, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ICALL_BRANCH_FUNNEL
894 { 42, 3, 0, 0, 0, 0, 0, LanaiOpInfoBase + 36, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_14787
895 { 41, 2, 0, 0, 0, 0, 0, LanaiOpInfoBase + 34, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_14786
896 { 40, 0, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_TAIL_CALL
897 { 39, 0, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_FUNCTION_EXIT
898 { 38, 0, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_RET
899 { 37, 0, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_FUNCTION_ENTER
900 { 36, 0, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_OP
901 { 35, 1, 1, 0, 0, 0, 0, LanaiOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FAULTING_OP
902 { 34, 2, 0, 0, 0, 0, 0, LanaiOpInfoBase + 32, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_ESCAPE
903 { 33, 0, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STATEPOINT
904 { 32, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 29, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_14785
905 { 31, 1, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PREALLOCATED_SETUP
906 { 30, 1, 1, 0, 0, 0, 0, LanaiOpInfoBase + 28, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_14418
907 { 29, 6, 1, 0, 0, 0, 0, LanaiOpInfoBase + 22, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHPOINT
908 { 28, 0, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FENTRY_CALL
909 { 27, 2, 0, 0, 0, 0, 0, LanaiOpInfoBase + 20, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STACKMAP
910 { 26, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 18, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARITH_FENCE
911 { 25, 4, 0, 0, 0, 0, 0, LanaiOpInfoBase + 14, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PSEUDO_PROBE
912 { 24, 1, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LIFETIME_END
913 { 23, 1, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LIFETIME_START
914 { 22, 0, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BUNDLE
915 { 21, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 11, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_LANEMASK
916 { 20, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY
917 { 19, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REG_SEQUENCE
918 { 18, 1, 0, 0, 0, 0, 0, LanaiOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_LABEL
919 { 17, 0, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_PHI
920 { 16, 0, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_INSTR_REF
921 { 15, 0, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_VALUE_LIST
922 { 14, 0, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_VALUE
923 { 13, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_TO_REGCLASS
924 { 12, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBREG_TO_REG
925 { 11, 1, 1, 0, 0, 0, 0, LanaiOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INIT_UNDEF
926 { 10, 1, 1, 0, 0, 0, 0, LanaiOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // IMPLICIT_DEF
927 { 9, 4, 1, 0, 0, 0, 0, LanaiOpInfoBase + 5, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INSERT_SUBREG
928 { 8, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTRACT_SUBREG
929 { 7, 0, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // KILL
930 { 6, 1, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ANNOTATION_LABEL
931 { 5, 1, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GC_LABEL
932 { 4, 1, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EH_LABEL
933 { 3, 1, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CFI_INSTRUCTION
934 { 2, 0, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INLINEASM_BR
935 { 1, 0, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INLINEASM
936 { 0, 1, 1, 0, 0, 0, 0, LanaiOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PHI
937 }, {
938 /* 0 */
939 /* 0 */ Lanai::SP, Lanai::SP,
940 /* 2 */ Lanai::SP, Lanai::RCA,
941 /* 4 */ Lanai::SR, Lanai::SR,
942 /* 6 */ Lanai::SR,
943 /* 7 */ Lanai::RCA,
944 }, {
945 0
946 }, {
947 /* 0 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
948 /* 1 */
949 /* 1 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
950 /* 2 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
951 /* 5 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
952 /* 9 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
953 /* 11 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
954 /* 14 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
955 /* 18 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) },
956 /* 20 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
957 /* 22 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
958 /* 28 */ { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
959 /* 29 */ { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
960 /* 32 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
961 /* 34 */ { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
962 /* 36 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
963 /* 39 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
964 /* 42 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
965 /* 45 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
966 /* 49 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
967 /* 50 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
968 /* 52 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
969 /* 57 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
970 /* 60 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
971 /* 62 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
972 /* 66 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
973 /* 68 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
974 /* 71 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
975 /* 76 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
976 /* 81 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
977 /* 86 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
978 /* 90 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
979 /* 93 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_2, 0 },
980 /* 97 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
981 /* 100 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
982 /* 103 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
983 /* 107 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
984 /* 111 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
985 /* 114 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
986 /* 119 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
987 /* 123 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
988 /* 126 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
989 /* 130 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
990 /* 133 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
991 /* 137 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
992 /* 141 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
993 /* 143 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
994 /* 147 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
995 /* 151 */ { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
996 /* 153 */ { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
997 /* 156 */ { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 },
998 /* 160 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
999 /* 162 */ { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1000 /* 166 */ { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1001 /* 170 */ { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1002 }
1003};
1004
1005
1006#ifdef __GNUC__
1007#pragma GCC diagnostic push
1008#pragma GCC diagnostic ignored "-Woverlength-strings"
1009#endif
1010extern const char LanaiInstrNameData[] = {
1011 /* 0 */ "G_FLOG10\000"
1012 /* 9 */ "G_FEXP10\000"
1013 /* 18 */ "LOG0\000"
1014 /* 23 */ "LOG1\000"
1015 /* 28 */ "G_FLOG2\000"
1016 /* 36 */ "G_FATAN2\000"
1017 /* 45 */ "G_FEXP2\000"
1018 /* 53 */ "LOG3\000"
1019 /* 58 */ "LOG4\000"
1020 /* 63 */ "BRIND_CCA\000"
1021 /* 73 */ "G_FMA\000"
1022 /* 79 */ "G_STRICT_FMA\000"
1023 /* 92 */ "G_FSUB\000"
1024 /* 99 */ "G_STRICT_FSUB\000"
1025 /* 113 */ "G_ATOMICRMW_FSUB\000"
1026 /* 130 */ "G_SUB\000"
1027 /* 136 */ "G_ATOMICRMW_SUB\000"
1028 /* 152 */ "BRCC\000"
1029 /* 157 */ "SCC\000"
1030 /* 161 */ "BRIND_CC\000"
1031 /* 170 */ "G_INTRINSIC\000"
1032 /* 182 */ "G_FPTRUNC\000"
1033 /* 192 */ "G_INTRINSIC_TRUNC\000"
1034 /* 210 */ "G_TRUNC\000"
1035 /* 218 */ "G_BUILD_VECTOR_TRUNC\000"
1036 /* 239 */ "G_DYN_STACKALLOC\000"
1037 /* 256 */ "ADJDYNALLOC\000"
1038 /* 268 */ "POPC\000"
1039 /* 273 */ "G_FMAD\000"
1040 /* 280 */ "G_FPEXTLOAD\000"
1041 /* 292 */ "G_INDEXED_SEXTLOAD\000"
1042 /* 311 */ "G_SEXTLOAD\000"
1043 /* 322 */ "G_INDEXED_ZEXTLOAD\000"
1044 /* 341 */ "G_ZEXTLOAD\000"
1045 /* 352 */ "G_INDEXED_LOAD\000"
1046 /* 367 */ "G_LOAD\000"
1047 /* 374 */ "G_VECREDUCE_FADD\000"
1048 /* 391 */ "G_FADD\000"
1049 /* 398 */ "G_VECREDUCE_SEQ_FADD\000"
1050 /* 419 */ "G_STRICT_FADD\000"
1051 /* 433 */ "G_ATOMICRMW_FADD\000"
1052 /* 450 */ "G_VECREDUCE_ADD\000"
1053 /* 466 */ "G_ADD\000"
1054 /* 472 */ "G_PTR_ADD\000"
1055 /* 482 */ "G_ATOMICRMW_ADD\000"
1056 /* 498 */ "G_ATOMICRMW_NAND\000"
1057 /* 515 */ "G_VECREDUCE_AND\000"
1058 /* 531 */ "G_AND\000"
1059 /* 537 */ "G_ATOMICRMW_AND\000"
1060 /* 553 */ "LIFETIME_END\000"
1061 /* 566 */ "G_BRCOND\000"
1062 /* 575 */ "G_ATOMICRMW_USUB_COND\000"
1063 /* 597 */ "G_LLROUND\000"
1064 /* 607 */ "G_LROUND\000"
1065 /* 616 */ "G_INTRINSIC_ROUND\000"
1066 /* 634 */ "G_INTRINSIC_FPTRUNC_ROUND\000"
1067 /* 660 */ "LOAD_STACK_GUARD\000"
1068 /* 677 */ "PSEUDO_PROBE\000"
1069 /* 690 */ "G_SSUBE\000"
1070 /* 698 */ "G_USUBE\000"
1071 /* 706 */ "G_FENCE\000"
1072 /* 714 */ "ARITH_FENCE\000"
1073 /* 726 */ "REG_SEQUENCE\000"
1074 /* 739 */ "G_SADDE\000"
1075 /* 747 */ "G_UADDE\000"
1076 /* 755 */ "G_GET_FPMODE\000"
1077 /* 768 */ "G_RESET_FPMODE\000"
1078 /* 783 */ "G_SET_FPMODE\000"
1079 /* 796 */ "G_FMINNUM_IEEE\000"
1080 /* 811 */ "G_FMAXNUM_IEEE\000"
1081 /* 826 */ "G_VSCALE\000"
1082 /* 835 */ "G_JUMP_TABLE\000"
1083 /* 848 */ "BUNDLE\000"
1084 /* 855 */ "G_MEMSET_INLINE\000"
1085 /* 871 */ "G_MEMCPY_INLINE\000"
1086 /* 887 */ "RELOC_NONE\000"
1087 /* 898 */ "LOCAL_ESCAPE\000"
1088 /* 911 */ "G_FPTRUNCSTORE\000"
1089 /* 926 */ "G_STACKRESTORE\000"
1090 /* 941 */ "G_INDEXED_STORE\000"
1091 /* 957 */ "G_STORE\000"
1092 /* 965 */ "G_BITREVERSE\000"
1093 /* 978 */ "FAKE_USE\000"
1094 /* 987 */ "DBG_VALUE\000"
1095 /* 997 */ "G_GLOBAL_VALUE\000"
1096 /* 1012 */ "G_PTRAUTH_GLOBAL_VALUE\000"
1097 /* 1035 */ "CONVERGENCECTRL_GLUE\000"
1098 /* 1056 */ "G_STACKSAVE\000"
1099 /* 1068 */ "G_MEMMOVE\000"
1100 /* 1078 */ "G_FREEZE\000"
1101 /* 1087 */ "G_FCANONICALIZE\000"
1102 /* 1103 */ "G_FMODF\000"
1103 /* 1111 */ "INIT_UNDEF\000"
1104 /* 1122 */ "G_IMPLICIT_DEF\000"
1105 /* 1137 */ "DBG_INSTR_REF\000"
1106 /* 1151 */ "G_FNEG\000"
1107 /* 1158 */ "EXTRACT_SUBREG\000"
1108 /* 1173 */ "INSERT_SUBREG\000"
1109 /* 1187 */ "G_SEXT_INREG\000"
1110 /* 1200 */ "SUBREG_TO_REG\000"
1111 /* 1214 */ "G_ATOMIC_CMPXCHG\000"
1112 /* 1231 */ "G_ATOMICRMW_XCHG\000"
1113 /* 1248 */ "G_GET_ROUNDING\000"
1114 /* 1263 */ "G_SET_ROUNDING\000"
1115 /* 1278 */ "G_FLOG\000"
1116 /* 1285 */ "G_VAARG\000"
1117 /* 1293 */ "PREALLOCATED_ARG\000"
1118 /* 1310 */ "G_PREFETCH\000"
1119 /* 1321 */ "G_CLMULH\000"
1120 /* 1330 */ "G_SMULH\000"
1121 /* 1338 */ "G_UMULH\000"
1122 /* 1346 */ "G_FTANH\000"
1123 /* 1354 */ "G_FSINH\000"
1124 /* 1362 */ "G_FCOSH\000"
1125 /* 1370 */ "DBG_PHI\000"
1126 /* 1378 */ "MOVHI\000"
1127 /* 1384 */ "SFSUB_F_RI_HI\000"
1128 /* 1398 */ "SUBB_I_HI\000"
1129 /* 1408 */ "SUB_I_HI\000"
1130 /* 1417 */ "ADDC_I_HI\000"
1131 /* 1427 */ "ADD_I_HI\000"
1132 /* 1436 */ "AND_I_HI\000"
1133 /* 1445 */ "SUBB_F_I_HI\000"
1134 /* 1457 */ "SUB_F_I_HI\000"
1135 /* 1468 */ "ADDC_F_I_HI\000"
1136 /* 1480 */ "ADD_F_I_HI\000"
1137 /* 1491 */ "AND_F_I_HI\000"
1138 /* 1502 */ "XOR_F_I_HI\000"
1139 /* 1513 */ "XOR_I_HI\000"
1140 /* 1522 */ "SLI\000"
1141 /* 1526 */ "STB_RI\000"
1142 /* 1533 */ "STH_RI\000"
1143 /* 1540 */ "LDW_RI\000"
1144 /* 1547 */ "SW_RI\000"
1145 /* 1553 */ "LDBs_RI\000"
1146 /* 1561 */ "LDHs_RI\000"
1147 /* 1569 */ "LDBz_RI\000"
1148 /* 1577 */ "LDHz_RI\000"
1149 /* 1585 */ "G_FPTOSI\000"
1150 /* 1594 */ "G_FPTOUI\000"
1151 /* 1603 */ "G_FPOWI\000"
1152 /* 1611 */ "SA_I\000"
1153 /* 1616 */ "SA_F_I\000"
1154 /* 1623 */ "SL_F_I\000"
1155 /* 1630 */ "SL_I\000"
1156 /* 1635 */ "COPY_LANEMASK\000"
1157 /* 1649 */ "G_PTRMASK\000"
1158 /* 1659 */ "GC_LABEL\000"
1159 /* 1668 */ "DBG_LABEL\000"
1160 /* 1678 */ "EH_LABEL\000"
1161 /* 1687 */ "ANNOTATION_LABEL\000"
1162 /* 1704 */ "ICALL_BRANCH_FUNNEL\000"
1163 /* 1724 */ "G_FSHL\000"
1164 /* 1731 */ "G_SHL\000"
1165 /* 1737 */ "G_FCEIL\000"
1166 /* 1745 */ "G_SAVGCEIL\000"
1167 /* 1756 */ "G_UAVGCEIL\000"
1168 /* 1767 */ "PATCHABLE_TAIL_CALL\000"
1169 /* 1787 */ "PATCHABLE_TYPED_EVENT_CALL\000"
1170 /* 1814 */ "PATCHABLE_EVENT_CALL\000"
1171 /* 1835 */ "FENTRY_CALL\000"
1172 /* 1847 */ "KILL\000"
1173 /* 1852 */ "G_CONSTANT_POOL\000"
1174 /* 1868 */ "G_ROTL\000"
1175 /* 1875 */ "G_VECREDUCE_FMUL\000"
1176 /* 1892 */ "G_FMUL\000"
1177 /* 1899 */ "G_VECREDUCE_SEQ_FMUL\000"
1178 /* 1920 */ "G_STRICT_FMUL\000"
1179 /* 1934 */ "G_CLMUL\000"
1180 /* 1942 */ "G_VECREDUCE_MUL\000"
1181 /* 1958 */ "G_MUL\000"
1182 /* 1964 */ "G_FREM\000"
1183 /* 1971 */ "G_STRICT_FREM\000"
1184 /* 1985 */ "G_SREM\000"
1185 /* 1992 */ "G_UREM\000"
1186 /* 1999 */ "G_SDIVREM\000"
1187 /* 2009 */ "G_UDIVREM\000"
1188 /* 2019 */ "INLINEASM\000"
1189 /* 2029 */ "G_VECREDUCE_FMINIMUM\000"
1190 /* 2050 */ "G_FMINIMUM\000"
1191 /* 2061 */ "G_ATOMICRMW_FMINIMUM\000"
1192 /* 2082 */ "G_VECREDUCE_FMAXIMUM\000"
1193 /* 2103 */ "G_FMAXIMUM\000"
1194 /* 2114 */ "G_ATOMICRMW_FMAXIMUM\000"
1195 /* 2135 */ "G_VECREDUCE_FMINIMUMNUM\000"
1196 /* 2159 */ "G_FMINIMUMNUM\000"
1197 /* 2173 */ "G_ATOMICRMW_FMINIMUMNUM\000"
1198 /* 2197 */ "G_VECREDUCE_FMAXIMUMNUM\000"
1199 /* 2221 */ "G_FMAXIMUMNUM\000"
1200 /* 2235 */ "G_ATOMICRMW_FMAXIMUMNUM\000"
1201 /* 2259 */ "G_FMINNUM\000"
1202 /* 2269 */ "G_FMAXNUM\000"
1203 /* 2279 */ "G_FATAN\000"
1204 /* 2287 */ "G_FTAN\000"
1205 /* 2294 */ "G_INTRINSIC_ROUNDEVEN\000"
1206 /* 2316 */ "G_ASSERT_ALIGN\000"
1207 /* 2331 */ "G_FCOPYSIGN\000"
1208 /* 2343 */ "G_VECREDUCE_FMIN\000"
1209 /* 2360 */ "G_ATOMICRMW_FMIN\000"
1210 /* 2377 */ "G_VECREDUCE_SMIN\000"
1211 /* 2394 */ "G_SMIN\000"
1212 /* 2401 */ "G_VECREDUCE_UMIN\000"
1213 /* 2418 */ "G_UMIN\000"
1214 /* 2425 */ "G_ATOMICRMW_UMIN\000"
1215 /* 2442 */ "G_ATOMICRMW_MIN\000"
1216 /* 2458 */ "G_FASIN\000"
1217 /* 2466 */ "G_FSIN\000"
1218 /* 2473 */ "CFI_INSTRUCTION\000"
1219 /* 2489 */ "G_CTLZ_ZERO_POISON\000"
1220 /* 2508 */ "G_CTTZ_ZERO_POISON\000"
1221 /* 2527 */ "ADJCALLSTACKDOWN\000"
1222 /* 2544 */ "G_SSUBO\000"
1223 /* 2552 */ "G_USUBO\000"
1224 /* 2560 */ "G_SADDO\000"
1225 /* 2568 */ "G_UADDO\000"
1226 /* 2576 */ "JUMP_TABLE_DEBUG_INFO\000"
1227 /* 2598 */ "G_SMULO\000"
1228 /* 2606 */ "G_UMULO\000"
1229 /* 2614 */ "SFSUB_F_RI_LO\000"
1230 /* 2628 */ "SUBB_I_LO\000"
1231 /* 2638 */ "SUB_I_LO\000"
1232 /* 2647 */ "ADDC_I_LO\000"
1233 /* 2657 */ "ADD_I_LO\000"
1234 /* 2666 */ "AND_I_LO\000"
1235 /* 2675 */ "SUBB_F_I_LO\000"
1236 /* 2687 */ "SUB_F_I_LO\000"
1237 /* 2698 */ "ADDC_F_I_LO\000"
1238 /* 2710 */ "ADD_F_I_LO\000"
1239 /* 2721 */ "AND_F_I_LO\000"
1240 /* 2732 */ "XOR_F_I_LO\000"
1241 /* 2743 */ "XOR_I_LO\000"
1242 /* 2752 */ "G_BZERO\000"
1243 /* 2760 */ "STACKMAP\000"
1244 /* 2769 */ "G_DEBUGTRAP\000"
1245 /* 2781 */ "G_UBSANTRAP\000"
1246 /* 2793 */ "G_TRAP\000"
1247 /* 2800 */ "G_ATOMICRMW_UDEC_WRAP\000"
1248 /* 2822 */ "G_ATOMICRMW_UINC_WRAP\000"
1249 /* 2844 */ "G_BSWAP\000"
1250 /* 2852 */ "G_SITOFP\000"
1251 /* 2861 */ "G_UITOFP\000"
1252 /* 2870 */ "G_FCMP\000"
1253 /* 2877 */ "G_STRICT_FCMP\000"
1254 /* 2891 */ "G_ICMP\000"
1255 /* 2898 */ "G_SCMP\000"
1256 /* 2905 */ "G_UCMP\000"
1257 /* 2912 */ "NOP\000"
1258 /* 2916 */ "CONVERGENCECTRL_LOOP\000"
1259 /* 2937 */ "G_CTPOP\000"
1260 /* 2945 */ "PATCHABLE_OP\000"
1261 /* 2958 */ "FAULTING_OP\000"
1262 /* 2970 */ "ADJCALLSTACKUP\000"
1263 /* 2985 */ "PREALLOCATED_SETUP\000"
1264 /* 3004 */ "G_FLDEXP\000"
1265 /* 3013 */ "G_STRICT_FLDEXP\000"
1266 /* 3029 */ "G_FEXP\000"
1267 /* 3036 */ "G_FFREXP\000"
1268 /* 3045 */ "G_BR\000"
1269 /* 3050 */ "INLINEASM_BR\000"
1270 /* 3063 */ "LDADDR\000"
1271 /* 3070 */ "STADDR\000"
1272 /* 3077 */ "G_BLOCK_ADDR\000"
1273 /* 3090 */ "MEMBARRIER\000"
1274 /* 3101 */ "G_CONSTANT_FOLD_BARRIER\000"
1275 /* 3125 */ "PATCHABLE_FUNCTION_ENTER\000"
1276 /* 3150 */ "G_READCYCLECOUNTER\000"
1277 /* 3169 */ "G_READSTEADYCOUNTER\000"
1278 /* 3189 */ "G_READ_REGISTER\000"
1279 /* 3205 */ "G_WRITE_REGISTER\000"
1280 /* 3222 */ "G_ASHR\000"
1281 /* 3229 */ "G_FSHR\000"
1282 /* 3236 */ "G_LSHR\000"
1283 /* 3243 */ "JR\000"
1284 /* 3246 */ "CALLR\000"
1285 /* 3252 */ "G_CLMULR\000"
1286 /* 3261 */ "CONVERGENCECTRL_ANCHOR\000"
1287 /* 3284 */ "G_FFLOOR\000"
1288 /* 3293 */ "G_SAVGFLOOR\000"
1289 /* 3305 */ "G_UAVGFLOOR\000"
1290 /* 3317 */ "G_EXTRACT_SUBVECTOR\000"
1291 /* 3337 */ "G_INSERT_SUBVECTOR\000"
1292 /* 3356 */ "G_BUILD_VECTOR\000"
1293 /* 3371 */ "G_SHUFFLE_VECTOR\000"
1294 /* 3388 */ "G_STEP_VECTOR\000"
1295 /* 3402 */ "G_SPLAT_VECTOR\000"
1296 /* 3417 */ "G_VECREDUCE_XOR\000"
1297 /* 3433 */ "G_XOR\000"
1298 /* 3439 */ "G_ATOMICRMW_XOR\000"
1299 /* 3455 */ "G_VECREDUCE_OR\000"
1300 /* 3470 */ "G_OR\000"
1301 /* 3475 */ "G_ATOMICRMW_OR\000"
1302 /* 3490 */ "BRR\000"
1303 /* 3494 */ "STB_RR\000"
1304 /* 3501 */ "SFSUB_F_RR\000"
1305 /* 3512 */ "STH_RR\000"
1306 /* 3519 */ "LDW_RR\000"
1307 /* 3526 */ "SW_RR\000"
1308 /* 3532 */ "LDBs_RR\000"
1309 /* 3540 */ "LDHs_RR\000"
1310 /* 3548 */ "LDBz_RR\000"
1311 /* 3556 */ "LDHz_RR\000"
1312 /* 3564 */ "LDWz_RR\000"
1313 /* 3572 */ "G_ROTR\000"
1314 /* 3579 */ "G_INTTOPTR\000"
1315 /* 3590 */ "SRA_R\000"
1316 /* 3596 */ "SUBB_R\000"
1317 /* 3603 */ "SUB_R\000"
1318 /* 3609 */ "ADDC_R\000"
1319 /* 3616 */ "ADD_R\000"
1320 /* 3622 */ "AND_R\000"
1321 /* 3628 */ "SRA_F_R\000"
1322 /* 3636 */ "SUBB_F_R\000"
1323 /* 3645 */ "SUB_F_R\000"
1324 /* 3653 */ "ADDC_F_R\000"
1325 /* 3662 */ "ADD_F_R\000"
1326 /* 3670 */ "AND_F_R\000"
1327 /* 3678 */ "SHL_F_R\000"
1328 /* 3686 */ "SRL_F_R\000"
1329 /* 3694 */ "XOR_F_R\000"
1330 /* 3702 */ "SHL_R\000"
1331 /* 3708 */ "SRL_R\000"
1332 /* 3714 */ "XOR_R\000"
1333 /* 3720 */ "G_FABS\000"
1334 /* 3727 */ "G_ABS\000"
1335 /* 3733 */ "G_ABDS\000"
1336 /* 3740 */ "G_UNMERGE_VALUES\000"
1337 /* 3757 */ "G_MERGE_VALUES\000"
1338 /* 3772 */ "G_CTLS\000"
1339 /* 3779 */ "G_FACOS\000"
1340 /* 3787 */ "G_FCOS\000"
1341 /* 3794 */ "G_FSINCOS\000"
1342 /* 3804 */ "G_STRICT_FCMPS\000"
1343 /* 3819 */ "G_CONCAT_VECTORS\000"
1344 /* 3836 */ "COPY_TO_REGCLASS\000"
1345 /* 3853 */ "G_IS_FPCLASS\000"
1346 /* 3866 */ "G_ATOMIC_CMPXCHG_WITH_SUCCESS\000"
1347 /* 3896 */ "G_VECTOR_COMPRESS\000"
1348 /* 3914 */ "G_INTRINSIC_W_SIDE_EFFECTS\000"
1349 /* 3941 */ "G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS\000"
1350 /* 3979 */ "G_TRUNC_SSAT_S\000"
1351 /* 3994 */ "G_SSUBSAT\000"
1352 /* 4004 */ "G_USUBSAT\000"
1353 /* 4014 */ "G_SADDSAT\000"
1354 /* 4024 */ "G_UADDSAT\000"
1355 /* 4034 */ "G_SSHLSAT\000"
1356 /* 4044 */ "G_USHLSAT\000"
1357 /* 4054 */ "G_SMULFIXSAT\000"
1358 /* 4067 */ "G_UMULFIXSAT\000"
1359 /* 4080 */ "G_SDIVFIXSAT\000"
1360 /* 4093 */ "G_UDIVFIXSAT\000"
1361 /* 4106 */ "G_ATOMICRMW_USUB_SAT\000"
1362 /* 4127 */ "G_FPTOSI_SAT\000"
1363 /* 4140 */ "G_FPTOUI_SAT\000"
1364 /* 4153 */ "BT\000"
1365 /* 4156 */ "G_EXTRACT\000"
1366 /* 4166 */ "G_SELECT\000"
1367 /* 4175 */ "G_BRINDIRECT\000"
1368 /* 4188 */ "PATCHABLE_RET\000"
1369 /* 4202 */ "G_MEMSET\000"
1370 /* 4211 */ "PATCHABLE_FUNCTION_EXIT\000"
1371 /* 4235 */ "G_BRJT\000"
1372 /* 4242 */ "G_EXTRACT_VECTOR_ELT\000"
1373 /* 4263 */ "G_INSERT_VECTOR_ELT\000"
1374 /* 4283 */ "G_FCONSTANT\000"
1375 /* 4295 */ "G_CONSTANT\000"
1376 /* 4306 */ "G_INTRINSIC_CONVERGENT\000"
1377 /* 4329 */ "STATEPOINT\000"
1378 /* 4340 */ "PATCHPOINT\000"
1379 /* 4351 */ "G_PTRTOINT\000"
1380 /* 4362 */ "G_FRINT\000"
1381 /* 4370 */ "G_INTRINSIC_LLRINT\000"
1382 /* 4389 */ "G_INTRINSIC_LRINT\000"
1383 /* 4407 */ "G_FNEARBYINT\000"
1384 /* 4420 */ "G_VASTART\000"
1385 /* 4430 */ "LIFETIME_START\000"
1386 /* 4445 */ "G_INVOKE_REGION_START\000"
1387 /* 4467 */ "G_INSERT\000"
1388 /* 4476 */ "G_FSQRT\000"
1389 /* 4484 */ "G_STRICT_FSQRT\000"
1390 /* 4499 */ "G_BITCAST\000"
1391 /* 4509 */ "G_ADDRSPACE_CAST\000"
1392 /* 4526 */ "DBG_VALUE_LIST\000"
1393 /* 4541 */ "G_FPEXT\000"
1394 /* 4549 */ "G_SEXT\000"
1395 /* 4556 */ "G_ASSERT_SEXT\000"
1396 /* 4570 */ "G_ANYEXT\000"
1397 /* 4579 */ "G_ZEXT\000"
1398 /* 4586 */ "G_ASSERT_ZEXT\000"
1399 /* 4600 */ "G_ABDU\000"
1400 /* 4607 */ "G_TRUNC_SSAT_U\000"
1401 /* 4622 */ "G_TRUNC_USAT_U\000"
1402 /* 4637 */ "G_FDIV\000"
1403 /* 4644 */ "G_STRICT_FDIV\000"
1404 /* 4658 */ "G_SDIV\000"
1405 /* 4665 */ "G_UDIV\000"
1406 /* 4672 */ "G_GET_FPENV\000"
1407 /* 4684 */ "G_RESET_FPENV\000"
1408 /* 4698 */ "G_SET_FPENV\000"
1409 /* 4710 */ "G_FPOW\000"
1410 /* 4717 */ "G_VECREDUCE_FMAX\000"
1411 /* 4734 */ "G_ATOMICRMW_FMAX\000"
1412 /* 4751 */ "G_VECREDUCE_SMAX\000"
1413 /* 4768 */ "G_SMAX\000"
1414 /* 4775 */ "G_VECREDUCE_UMAX\000"
1415 /* 4792 */ "G_UMAX\000"
1416 /* 4799 */ "G_ATOMICRMW_UMAX\000"
1417 /* 4816 */ "G_ATOMICRMW_MAX\000"
1418 /* 4832 */ "G_FRAME_INDEX\000"
1419 /* 4846 */ "G_SBFX\000"
1420 /* 4853 */ "G_UBFX\000"
1421 /* 4860 */ "G_SMULFIX\000"
1422 /* 4870 */ "G_UMULFIX\000"
1423 /* 4880 */ "G_SDIVFIX\000"
1424 /* 4890 */ "G_UDIVFIX\000"
1425 /* 4900 */ "G_MEMCPY\000"
1426 /* 4909 */ "COPY\000"
1427 /* 4914 */ "CONVERGENCECTRL_ENTRY\000"
1428 /* 4936 */ "LEADZ\000"
1429 /* 4942 */ "TRAILZ\000"
1430 /* 4949 */ "G_CTLZ\000"
1431 /* 4956 */ "G_CTTZ\000"
1432};
1433#ifdef __GNUC__
1434#pragma GCC diagnostic pop
1435#endif
1436
1437extern const unsigned LanaiInstrNameIndices[] = {
1438 1374U, 2019U, 3050U, 2473U, 1678U, 1659U, 1687U, 1847U,
1439 1158U, 1173U, 1124U, 1111U, 1200U, 3836U, 987U, 4526U,
1440 1137U, 1370U, 1668U, 726U, 4909U, 1635U, 848U, 4430U,
1441 553U, 677U, 714U, 2760U, 1835U, 4340U, 660U, 2985U,
1442 1293U, 4329U, 898U, 2958U, 2945U, 3125U, 4188U, 4211U,
1443 1767U, 1814U, 1787U, 1704U, 978U, 3090U, 2576U, 887U,
1444 4914U, 3261U, 2916U, 1035U, 4556U, 4586U, 2316U, 466U,
1445 130U, 1958U, 4658U, 4665U, 1985U, 1992U, 1999U, 2009U,
1446 531U, 3470U, 3433U, 3733U, 4600U, 3305U, 1756U, 3293U,
1447 1745U, 1122U, 1372U, 4832U, 997U, 1012U, 1852U, 4156U,
1448 3740U, 4467U, 3757U, 3356U, 218U, 3819U, 4351U, 3579U,
1449 4499U, 1078U, 3101U, 634U, 192U, 616U, 4389U, 4370U,
1450 2294U, 3150U, 3169U, 367U, 311U, 341U, 280U, 352U,
1451 292U, 322U, 957U, 911U, 941U, 3866U, 1214U, 1231U,
1452 482U, 136U, 537U, 498U, 3475U, 3439U, 4816U, 2442U,
1453 4799U, 2425U, 433U, 113U, 4734U, 2360U, 2114U, 2061U,
1454 2235U, 2173U, 2822U, 2800U, 575U, 4106U, 706U, 1310U,
1455 566U, 4175U, 4445U, 170U, 3914U, 4306U, 3941U, 4570U,
1456 210U, 3979U, 4607U, 4622U, 4295U, 4283U, 4420U, 1285U,
1457 4549U, 1187U, 4579U, 1731U, 3236U, 3222U, 1724U, 3229U,
1458 3572U, 1868U, 2891U, 2870U, 2898U, 2905U, 4166U, 2568U,
1459 747U, 2552U, 698U, 2560U, 739U, 2544U, 690U, 2606U,
1460 2598U, 1338U, 1330U, 4024U, 4014U, 4004U, 3994U, 4044U,
1461 4034U, 4860U, 4870U, 4054U, 4067U, 4880U, 4890U, 4080U,
1462 4093U, 391U, 92U, 1892U, 73U, 273U, 4637U, 1964U,
1463 1103U, 4710U, 1603U, 3029U, 45U, 9U, 1278U, 28U,
1464 0U, 3004U, 3036U, 1151U, 4541U, 182U, 1585U, 1594U,
1465 2852U, 2861U, 4127U, 4140U, 3720U, 2331U, 3853U, 1087U,
1466 2259U, 2269U, 796U, 811U, 2050U, 2103U, 2159U, 2221U,
1467 4672U, 4698U, 4684U, 755U, 783U, 768U, 1248U, 1263U,
1468 472U, 1649U, 2394U, 4768U, 2418U, 4792U, 3727U, 607U,
1469 597U, 3045U, 4235U, 826U, 3337U, 3317U, 4263U, 4242U,
1470 3371U, 3402U, 3388U, 3896U, 4956U, 2508U, 4949U, 2489U,
1471 3772U, 2937U, 2844U, 965U, 1934U, 1321U, 3252U, 1737U,
1472 3787U, 2466U, 3794U, 2287U, 3779U, 2458U, 2279U, 36U,
1473 1362U, 1354U, 1346U, 4476U, 3284U, 4362U, 4407U, 4509U,
1474 3077U, 835U, 239U, 1056U, 926U, 419U, 99U, 1920U,
1475 4644U, 1971U, 79U, 4484U, 3013U, 2877U, 3804U, 3189U,
1476 3205U, 4900U, 871U, 1068U, 4202U, 2752U, 855U, 2793U,
1477 2769U, 2781U, 398U, 1899U, 374U, 1875U, 4717U, 2343U,
1478 2082U, 2029U, 2197U, 2135U, 450U, 1942U, 515U, 3455U,
1479 3417U, 4751U, 2377U, 4775U, 2401U, 4846U, 4853U, 2527U,
1480 2970U, 256U, 1782U, 3246U, 1468U, 2698U, 3653U, 1417U,
1481 2647U, 3609U, 1480U, 2710U, 3662U, 1427U, 2657U, 3616U,
1482 1491U, 2721U, 3670U, 1436U, 2666U, 3622U, 152U, 161U,
1483 63U, 3490U, 4153U, 3243U, 3063U, 1553U, 3532U, 1569U,
1484 3548U, 1561U, 3540U, 1577U, 3556U, 1540U, 3519U, 3564U,
1485 4936U, 18U, 23U, 31U, 53U, 58U, 1378U, 2912U,
1486 1503U, 2733U, 3695U, 1514U, 2744U, 3715U, 268U, 4198U,
1487 1616U, 1611U, 157U, 4168U, 1384U, 2614U, 3501U, 3678U,
1488 3702U, 1522U, 1623U, 1630U, 3628U, 3590U, 3686U, 3708U,
1489 3070U, 1526U, 3494U, 1533U, 3512U, 1445U, 2675U, 3636U,
1490 1398U, 2628U, 3596U, 1457U, 2687U, 3645U, 1408U, 2638U,
1491 3603U, 1547U, 3526U, 4942U, 1502U, 2732U, 3694U, 1513U,
1492 2743U, 3714U,
1493};
1494
1495static inline void InitLanaiMCInstrInfo(MCInstrInfo *II) {
1496 II->InitMCInstrInfo(LanaiDescs.Insts, LanaiInstrNameIndices, LanaiInstrNameData, nullptr, nullptr, 434, nullptr, 0);
1497}
1498
1499
1500} // namespace llvm
1501
1502#endif // GET_INSTRINFO_MC_DESC
1503
1504#ifdef GET_INSTRINFO_HEADER
1505#undef GET_INSTRINFO_HEADER
1506
1507namespace llvm {
1508
1509struct LanaiGenInstrInfo : public TargetInstrInfo {
1510 explicit LanaiGenInstrInfo(const TargetSubtargetInfo &STI, const TargetRegisterInfo &TRI, unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u, unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u);
1511 ~LanaiGenInstrInfo() override = default;
1512};
1513
1514} // namespace llvm
1515
1516namespace llvm::Lanai {
1517
1518constexpr unsigned SUBOP_MEMri_base = 0;
1519constexpr unsigned SUBOP_MEMri_offset = 1;
1520constexpr unsigned SUBOP_MEMri_Opcode = 2;
1521constexpr unsigned SUBOP_MEMrr_Op1 = 0;
1522constexpr unsigned SUBOP_MEMrr_Op2 = 1;
1523constexpr unsigned SUBOP_MEMrr_Opcode = 2;
1524constexpr unsigned SUBOP_MEMspls_base = 0;
1525constexpr unsigned SUBOP_MEMspls_offset = 1;
1526constexpr unsigned SUBOP_MEMspls_Opcode = 2;
1527
1528} // namespace llvm::Lanai
1529
1530#endif // GET_INSTRINFO_HEADER
1531
1532#ifdef GET_INSTRINFO_HELPER_DECLS
1533#undef GET_INSTRINFO_HELPER_DECLS
1534
1535
1536#endif // GET_INSTRINFO_HELPER_DECLS
1537
1538#ifdef GET_INSTRINFO_HELPERS
1539#undef GET_INSTRINFO_HELPERS
1540
1541
1542#endif // GET_INSTRINFO_HELPERS
1543
1544#ifdef GET_INSTRINFO_CTOR_DTOR
1545#undef GET_INSTRINFO_CTOR_DTOR
1546
1547namespace llvm {
1548
1549extern const LanaiInstrTable LanaiDescs;
1550extern const unsigned LanaiInstrNameIndices[];
1551extern const char LanaiInstrNameData[];
1552LanaiGenInstrInfo::LanaiGenInstrInfo(const TargetSubtargetInfo &STI, const TargetRegisterInfo &TRI, unsigned CFSetupOpcode, unsigned CFDestroyOpcode, unsigned CatchRetOpcode, unsigned ReturnOpcode)
1553 : TargetInstrInfo(TRI, CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) {
1554 InitMCInstrInfo(LanaiDescs.Insts, LanaiInstrNameIndices, LanaiInstrNameData, nullptr, nullptr, 434);
1555}
1556
1557} // namespace llvm
1558
1559#endif // GET_INSTRINFO_CTOR_DTOR
1560
1561#ifdef GET_INSTRINFO_MC_HELPER_DECLS
1562#undef GET_INSTRINFO_MC_HELPER_DECLS
1563
1564namespace llvm {
1565
1566class MCInst;
1567class FeatureBitset;
1568
1569namespace Lanai_MC {
1570
1571void verifyInstructionPredicates(unsigned Opcode, const FeatureBitset &Features);
1572
1573} // namespace Lanai_MC
1574
1575} // namespace llvm
1576
1577#endif // GET_INSTRINFO_MC_HELPER_DECLS
1578
1579#ifdef GET_INSTRINFO_MC_HELPERS
1580#undef GET_INSTRINFO_MC_HELPERS
1581
1582namespace llvm::Lanai_MC {
1583
1584
1585} // namespace llvm::Lanai_MC
1586
1587#endif // GET_INSTRINFO_MC_HELPERS
1588
1589#if (defined(ENABLE_INSTR_PREDICATE_VERIFIER) && !defined(NDEBUG)) ||\
1590 defined(GET_AVAILABLE_OPCODE_CHECKER)
1591#define GET_COMPUTE_FEATURES
1592#endif
1593#ifdef GET_COMPUTE_FEATURES
1594#undef GET_COMPUTE_FEATURES
1595
1596namespace llvm::Lanai_MC {
1597
1598// Bits for subtarget features that participate in instruction matching.
1599enum SubtargetFeatureBits : uint8_t {
1600};
1601
1602inline FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) {
1603 FeatureBitset Features;
1604 return Features;
1605}
1606
1607inline FeatureBitset computeRequiredFeatures(unsigned Opcode) {
1608 enum : uint8_t {
1609 CEFBS_None,
1610 };
1611
1612 static constexpr FeatureBitset FeatureBitsets[] = {
1613 {}, // CEFBS_None
1614 };
1615 static constexpr uint8_t RequiredFeaturesRefs[] = {
1616 CEFBS_None, // PHI
1617 CEFBS_None, // INLINEASM
1618 CEFBS_None, // INLINEASM_BR
1619 CEFBS_None, // CFI_INSTRUCTION
1620 CEFBS_None, // EH_LABEL
1621 CEFBS_None, // GC_LABEL
1622 CEFBS_None, // ANNOTATION_LABEL
1623 CEFBS_None, // KILL
1624 CEFBS_None, // EXTRACT_SUBREG
1625 CEFBS_None, // INSERT_SUBREG
1626 CEFBS_None, // IMPLICIT_DEF
1627 CEFBS_None, // INIT_UNDEF
1628 CEFBS_None, // SUBREG_TO_REG
1629 CEFBS_None, // COPY_TO_REGCLASS
1630 CEFBS_None, // DBG_VALUE
1631 CEFBS_None, // DBG_VALUE_LIST
1632 CEFBS_None, // DBG_INSTR_REF
1633 CEFBS_None, // DBG_PHI
1634 CEFBS_None, // DBG_LABEL
1635 CEFBS_None, // REG_SEQUENCE
1636 CEFBS_None, // COPY
1637 CEFBS_None, // COPY_LANEMASK
1638 CEFBS_None, // BUNDLE
1639 CEFBS_None, // LIFETIME_START
1640 CEFBS_None, // LIFETIME_END
1641 CEFBS_None, // PSEUDO_PROBE
1642 CEFBS_None, // ARITH_FENCE
1643 CEFBS_None, // STACKMAP
1644 CEFBS_None, // FENTRY_CALL
1645 CEFBS_None, // PATCHPOINT
1646 CEFBS_None, // LOAD_STACK_GUARD
1647 CEFBS_None, // PREALLOCATED_SETUP
1648 CEFBS_None, // PREALLOCATED_ARG
1649 CEFBS_None, // STATEPOINT
1650 CEFBS_None, // LOCAL_ESCAPE
1651 CEFBS_None, // FAULTING_OP
1652 CEFBS_None, // PATCHABLE_OP
1653 CEFBS_None, // PATCHABLE_FUNCTION_ENTER
1654 CEFBS_None, // PATCHABLE_RET
1655 CEFBS_None, // PATCHABLE_FUNCTION_EXIT
1656 CEFBS_None, // PATCHABLE_TAIL_CALL
1657 CEFBS_None, // PATCHABLE_EVENT_CALL
1658 CEFBS_None, // PATCHABLE_TYPED_EVENT_CALL
1659 CEFBS_None, // ICALL_BRANCH_FUNNEL
1660 CEFBS_None, // FAKE_USE
1661 CEFBS_None, // MEMBARRIER
1662 CEFBS_None, // JUMP_TABLE_DEBUG_INFO
1663 CEFBS_None, // RELOC_NONE
1664 CEFBS_None, // CONVERGENCECTRL_ENTRY
1665 CEFBS_None, // CONVERGENCECTRL_ANCHOR
1666 CEFBS_None, // CONVERGENCECTRL_LOOP
1667 CEFBS_None, // CONVERGENCECTRL_GLUE
1668 CEFBS_None, // G_ASSERT_SEXT
1669 CEFBS_None, // G_ASSERT_ZEXT
1670 CEFBS_None, // G_ASSERT_ALIGN
1671 CEFBS_None, // G_ADD
1672 CEFBS_None, // G_SUB
1673 CEFBS_None, // G_MUL
1674 CEFBS_None, // G_SDIV
1675 CEFBS_None, // G_UDIV
1676 CEFBS_None, // G_SREM
1677 CEFBS_None, // G_UREM
1678 CEFBS_None, // G_SDIVREM
1679 CEFBS_None, // G_UDIVREM
1680 CEFBS_None, // G_AND
1681 CEFBS_None, // G_OR
1682 CEFBS_None, // G_XOR
1683 CEFBS_None, // G_ABDS
1684 CEFBS_None, // G_ABDU
1685 CEFBS_None, // G_UAVGFLOOR
1686 CEFBS_None, // G_UAVGCEIL
1687 CEFBS_None, // G_SAVGFLOOR
1688 CEFBS_None, // G_SAVGCEIL
1689 CEFBS_None, // G_IMPLICIT_DEF
1690 CEFBS_None, // G_PHI
1691 CEFBS_None, // G_FRAME_INDEX
1692 CEFBS_None, // G_GLOBAL_VALUE
1693 CEFBS_None, // G_PTRAUTH_GLOBAL_VALUE
1694 CEFBS_None, // G_CONSTANT_POOL
1695 CEFBS_None, // G_EXTRACT
1696 CEFBS_None, // G_UNMERGE_VALUES
1697 CEFBS_None, // G_INSERT
1698 CEFBS_None, // G_MERGE_VALUES
1699 CEFBS_None, // G_BUILD_VECTOR
1700 CEFBS_None, // G_BUILD_VECTOR_TRUNC
1701 CEFBS_None, // G_CONCAT_VECTORS
1702 CEFBS_None, // G_PTRTOINT
1703 CEFBS_None, // G_INTTOPTR
1704 CEFBS_None, // G_BITCAST
1705 CEFBS_None, // G_FREEZE
1706 CEFBS_None, // G_CONSTANT_FOLD_BARRIER
1707 CEFBS_None, // G_INTRINSIC_FPTRUNC_ROUND
1708 CEFBS_None, // G_INTRINSIC_TRUNC
1709 CEFBS_None, // G_INTRINSIC_ROUND
1710 CEFBS_None, // G_INTRINSIC_LRINT
1711 CEFBS_None, // G_INTRINSIC_LLRINT
1712 CEFBS_None, // G_INTRINSIC_ROUNDEVEN
1713 CEFBS_None, // G_READCYCLECOUNTER
1714 CEFBS_None, // G_READSTEADYCOUNTER
1715 CEFBS_None, // G_LOAD
1716 CEFBS_None, // G_SEXTLOAD
1717 CEFBS_None, // G_ZEXTLOAD
1718 CEFBS_None, // G_FPEXTLOAD
1719 CEFBS_None, // G_INDEXED_LOAD
1720 CEFBS_None, // G_INDEXED_SEXTLOAD
1721 CEFBS_None, // G_INDEXED_ZEXTLOAD
1722 CEFBS_None, // G_STORE
1723 CEFBS_None, // G_FPTRUNCSTORE
1724 CEFBS_None, // G_INDEXED_STORE
1725 CEFBS_None, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
1726 CEFBS_None, // G_ATOMIC_CMPXCHG
1727 CEFBS_None, // G_ATOMICRMW_XCHG
1728 CEFBS_None, // G_ATOMICRMW_ADD
1729 CEFBS_None, // G_ATOMICRMW_SUB
1730 CEFBS_None, // G_ATOMICRMW_AND
1731 CEFBS_None, // G_ATOMICRMW_NAND
1732 CEFBS_None, // G_ATOMICRMW_OR
1733 CEFBS_None, // G_ATOMICRMW_XOR
1734 CEFBS_None, // G_ATOMICRMW_MAX
1735 CEFBS_None, // G_ATOMICRMW_MIN
1736 CEFBS_None, // G_ATOMICRMW_UMAX
1737 CEFBS_None, // G_ATOMICRMW_UMIN
1738 CEFBS_None, // G_ATOMICRMW_FADD
1739 CEFBS_None, // G_ATOMICRMW_FSUB
1740 CEFBS_None, // G_ATOMICRMW_FMAX
1741 CEFBS_None, // G_ATOMICRMW_FMIN
1742 CEFBS_None, // G_ATOMICRMW_FMAXIMUM
1743 CEFBS_None, // G_ATOMICRMW_FMINIMUM
1744 CEFBS_None, // G_ATOMICRMW_FMAXIMUMNUM
1745 CEFBS_None, // G_ATOMICRMW_FMINIMUMNUM
1746 CEFBS_None, // G_ATOMICRMW_UINC_WRAP
1747 CEFBS_None, // G_ATOMICRMW_UDEC_WRAP
1748 CEFBS_None, // G_ATOMICRMW_USUB_COND
1749 CEFBS_None, // G_ATOMICRMW_USUB_SAT
1750 CEFBS_None, // G_FENCE
1751 CEFBS_None, // G_PREFETCH
1752 CEFBS_None, // G_BRCOND
1753 CEFBS_None, // G_BRINDIRECT
1754 CEFBS_None, // G_INVOKE_REGION_START
1755 CEFBS_None, // G_INTRINSIC
1756 CEFBS_None, // G_INTRINSIC_W_SIDE_EFFECTS
1757 CEFBS_None, // G_INTRINSIC_CONVERGENT
1758 CEFBS_None, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
1759 CEFBS_None, // G_ANYEXT
1760 CEFBS_None, // G_TRUNC
1761 CEFBS_None, // G_TRUNC_SSAT_S
1762 CEFBS_None, // G_TRUNC_SSAT_U
1763 CEFBS_None, // G_TRUNC_USAT_U
1764 CEFBS_None, // G_CONSTANT
1765 CEFBS_None, // G_FCONSTANT
1766 CEFBS_None, // G_VASTART
1767 CEFBS_None, // G_VAARG
1768 CEFBS_None, // G_SEXT
1769 CEFBS_None, // G_SEXT_INREG
1770 CEFBS_None, // G_ZEXT
1771 CEFBS_None, // G_SHL
1772 CEFBS_None, // G_LSHR
1773 CEFBS_None, // G_ASHR
1774 CEFBS_None, // G_FSHL
1775 CEFBS_None, // G_FSHR
1776 CEFBS_None, // G_ROTR
1777 CEFBS_None, // G_ROTL
1778 CEFBS_None, // G_ICMP
1779 CEFBS_None, // G_FCMP
1780 CEFBS_None, // G_SCMP
1781 CEFBS_None, // G_UCMP
1782 CEFBS_None, // G_SELECT
1783 CEFBS_None, // G_UADDO
1784 CEFBS_None, // G_UADDE
1785 CEFBS_None, // G_USUBO
1786 CEFBS_None, // G_USUBE
1787 CEFBS_None, // G_SADDO
1788 CEFBS_None, // G_SADDE
1789 CEFBS_None, // G_SSUBO
1790 CEFBS_None, // G_SSUBE
1791 CEFBS_None, // G_UMULO
1792 CEFBS_None, // G_SMULO
1793 CEFBS_None, // G_UMULH
1794 CEFBS_None, // G_SMULH
1795 CEFBS_None, // G_UADDSAT
1796 CEFBS_None, // G_SADDSAT
1797 CEFBS_None, // G_USUBSAT
1798 CEFBS_None, // G_SSUBSAT
1799 CEFBS_None, // G_USHLSAT
1800 CEFBS_None, // G_SSHLSAT
1801 CEFBS_None, // G_SMULFIX
1802 CEFBS_None, // G_UMULFIX
1803 CEFBS_None, // G_SMULFIXSAT
1804 CEFBS_None, // G_UMULFIXSAT
1805 CEFBS_None, // G_SDIVFIX
1806 CEFBS_None, // G_UDIVFIX
1807 CEFBS_None, // G_SDIVFIXSAT
1808 CEFBS_None, // G_UDIVFIXSAT
1809 CEFBS_None, // G_FADD
1810 CEFBS_None, // G_FSUB
1811 CEFBS_None, // G_FMUL
1812 CEFBS_None, // G_FMA
1813 CEFBS_None, // G_FMAD
1814 CEFBS_None, // G_FDIV
1815 CEFBS_None, // G_FREM
1816 CEFBS_None, // G_FMODF
1817 CEFBS_None, // G_FPOW
1818 CEFBS_None, // G_FPOWI
1819 CEFBS_None, // G_FEXP
1820 CEFBS_None, // G_FEXP2
1821 CEFBS_None, // G_FEXP10
1822 CEFBS_None, // G_FLOG
1823 CEFBS_None, // G_FLOG2
1824 CEFBS_None, // G_FLOG10
1825 CEFBS_None, // G_FLDEXP
1826 CEFBS_None, // G_FFREXP
1827 CEFBS_None, // G_FNEG
1828 CEFBS_None, // G_FPEXT
1829 CEFBS_None, // G_FPTRUNC
1830 CEFBS_None, // G_FPTOSI
1831 CEFBS_None, // G_FPTOUI
1832 CEFBS_None, // G_SITOFP
1833 CEFBS_None, // G_UITOFP
1834 CEFBS_None, // G_FPTOSI_SAT
1835 CEFBS_None, // G_FPTOUI_SAT
1836 CEFBS_None, // G_FABS
1837 CEFBS_None, // G_FCOPYSIGN
1838 CEFBS_None, // G_IS_FPCLASS
1839 CEFBS_None, // G_FCANONICALIZE
1840 CEFBS_None, // G_FMINNUM
1841 CEFBS_None, // G_FMAXNUM
1842 CEFBS_None, // G_FMINNUM_IEEE
1843 CEFBS_None, // G_FMAXNUM_IEEE
1844 CEFBS_None, // G_FMINIMUM
1845 CEFBS_None, // G_FMAXIMUM
1846 CEFBS_None, // G_FMINIMUMNUM
1847 CEFBS_None, // G_FMAXIMUMNUM
1848 CEFBS_None, // G_GET_FPENV
1849 CEFBS_None, // G_SET_FPENV
1850 CEFBS_None, // G_RESET_FPENV
1851 CEFBS_None, // G_GET_FPMODE
1852 CEFBS_None, // G_SET_FPMODE
1853 CEFBS_None, // G_RESET_FPMODE
1854 CEFBS_None, // G_GET_ROUNDING
1855 CEFBS_None, // G_SET_ROUNDING
1856 CEFBS_None, // G_PTR_ADD
1857 CEFBS_None, // G_PTRMASK
1858 CEFBS_None, // G_SMIN
1859 CEFBS_None, // G_SMAX
1860 CEFBS_None, // G_UMIN
1861 CEFBS_None, // G_UMAX
1862 CEFBS_None, // G_ABS
1863 CEFBS_None, // G_LROUND
1864 CEFBS_None, // G_LLROUND
1865 CEFBS_None, // G_BR
1866 CEFBS_None, // G_BRJT
1867 CEFBS_None, // G_VSCALE
1868 CEFBS_None, // G_INSERT_SUBVECTOR
1869 CEFBS_None, // G_EXTRACT_SUBVECTOR
1870 CEFBS_None, // G_INSERT_VECTOR_ELT
1871 CEFBS_None, // G_EXTRACT_VECTOR_ELT
1872 CEFBS_None, // G_SHUFFLE_VECTOR
1873 CEFBS_None, // G_SPLAT_VECTOR
1874 CEFBS_None, // G_STEP_VECTOR
1875 CEFBS_None, // G_VECTOR_COMPRESS
1876 CEFBS_None, // G_CTTZ
1877 CEFBS_None, // G_CTTZ_ZERO_POISON
1878 CEFBS_None, // G_CTLZ
1879 CEFBS_None, // G_CTLZ_ZERO_POISON
1880 CEFBS_None, // G_CTLS
1881 CEFBS_None, // G_CTPOP
1882 CEFBS_None, // G_BSWAP
1883 CEFBS_None, // G_BITREVERSE
1884 CEFBS_None, // G_CLMUL
1885 CEFBS_None, // G_CLMULH
1886 CEFBS_None, // G_CLMULR
1887 CEFBS_None, // G_FCEIL
1888 CEFBS_None, // G_FCOS
1889 CEFBS_None, // G_FSIN
1890 CEFBS_None, // G_FSINCOS
1891 CEFBS_None, // G_FTAN
1892 CEFBS_None, // G_FACOS
1893 CEFBS_None, // G_FASIN
1894 CEFBS_None, // G_FATAN
1895 CEFBS_None, // G_FATAN2
1896 CEFBS_None, // G_FCOSH
1897 CEFBS_None, // G_FSINH
1898 CEFBS_None, // G_FTANH
1899 CEFBS_None, // G_FSQRT
1900 CEFBS_None, // G_FFLOOR
1901 CEFBS_None, // G_FRINT
1902 CEFBS_None, // G_FNEARBYINT
1903 CEFBS_None, // G_ADDRSPACE_CAST
1904 CEFBS_None, // G_BLOCK_ADDR
1905 CEFBS_None, // G_JUMP_TABLE
1906 CEFBS_None, // G_DYN_STACKALLOC
1907 CEFBS_None, // G_STACKSAVE
1908 CEFBS_None, // G_STACKRESTORE
1909 CEFBS_None, // G_STRICT_FADD
1910 CEFBS_None, // G_STRICT_FSUB
1911 CEFBS_None, // G_STRICT_FMUL
1912 CEFBS_None, // G_STRICT_FDIV
1913 CEFBS_None, // G_STRICT_FREM
1914 CEFBS_None, // G_STRICT_FMA
1915 CEFBS_None, // G_STRICT_FSQRT
1916 CEFBS_None, // G_STRICT_FLDEXP
1917 CEFBS_None, // G_STRICT_FCMP
1918 CEFBS_None, // G_STRICT_FCMPS
1919 CEFBS_None, // G_READ_REGISTER
1920 CEFBS_None, // G_WRITE_REGISTER
1921 CEFBS_None, // G_MEMCPY
1922 CEFBS_None, // G_MEMCPY_INLINE
1923 CEFBS_None, // G_MEMMOVE
1924 CEFBS_None, // G_MEMSET
1925 CEFBS_None, // G_BZERO
1926 CEFBS_None, // G_MEMSET_INLINE
1927 CEFBS_None, // G_TRAP
1928 CEFBS_None, // G_DEBUGTRAP
1929 CEFBS_None, // G_UBSANTRAP
1930 CEFBS_None, // G_VECREDUCE_SEQ_FADD
1931 CEFBS_None, // G_VECREDUCE_SEQ_FMUL
1932 CEFBS_None, // G_VECREDUCE_FADD
1933 CEFBS_None, // G_VECREDUCE_FMUL
1934 CEFBS_None, // G_VECREDUCE_FMAX
1935 CEFBS_None, // G_VECREDUCE_FMIN
1936 CEFBS_None, // G_VECREDUCE_FMAXIMUM
1937 CEFBS_None, // G_VECREDUCE_FMINIMUM
1938 CEFBS_None, // G_VECREDUCE_FMAXIMUMNUM
1939 CEFBS_None, // G_VECREDUCE_FMINIMUMNUM
1940 CEFBS_None, // G_VECREDUCE_ADD
1941 CEFBS_None, // G_VECREDUCE_MUL
1942 CEFBS_None, // G_VECREDUCE_AND
1943 CEFBS_None, // G_VECREDUCE_OR
1944 CEFBS_None, // G_VECREDUCE_XOR
1945 CEFBS_None, // G_VECREDUCE_SMAX
1946 CEFBS_None, // G_VECREDUCE_SMIN
1947 CEFBS_None, // G_VECREDUCE_UMAX
1948 CEFBS_None, // G_VECREDUCE_UMIN
1949 CEFBS_None, // G_SBFX
1950 CEFBS_None, // G_UBFX
1951 CEFBS_None, // ADJCALLSTACKDOWN
1952 CEFBS_None, // ADJCALLSTACKUP
1953 CEFBS_None, // ADJDYNALLOC
1954 CEFBS_None, // CALL
1955 CEFBS_None, // CALLR
1956 CEFBS_None, // ADDC_F_I_HI
1957 CEFBS_None, // ADDC_F_I_LO
1958 CEFBS_None, // ADDC_F_R
1959 CEFBS_None, // ADDC_I_HI
1960 CEFBS_None, // ADDC_I_LO
1961 CEFBS_None, // ADDC_R
1962 CEFBS_None, // ADD_F_I_HI
1963 CEFBS_None, // ADD_F_I_LO
1964 CEFBS_None, // ADD_F_R
1965 CEFBS_None, // ADD_I_HI
1966 CEFBS_None, // ADD_I_LO
1967 CEFBS_None, // ADD_R
1968 CEFBS_None, // AND_F_I_HI
1969 CEFBS_None, // AND_F_I_LO
1970 CEFBS_None, // AND_F_R
1971 CEFBS_None, // AND_I_HI
1972 CEFBS_None, // AND_I_LO
1973 CEFBS_None, // AND_R
1974 CEFBS_None, // BRCC
1975 CEFBS_None, // BRIND_CC
1976 CEFBS_None, // BRIND_CCA
1977 CEFBS_None, // BRR
1978 CEFBS_None, // BT
1979 CEFBS_None, // JR
1980 CEFBS_None, // LDADDR
1981 CEFBS_None, // LDBs_RI
1982 CEFBS_None, // LDBs_RR
1983 CEFBS_None, // LDBz_RI
1984 CEFBS_None, // LDBz_RR
1985 CEFBS_None, // LDHs_RI
1986 CEFBS_None, // LDHs_RR
1987 CEFBS_None, // LDHz_RI
1988 CEFBS_None, // LDHz_RR
1989 CEFBS_None, // LDW_RI
1990 CEFBS_None, // LDW_RR
1991 CEFBS_None, // LDWz_RR
1992 CEFBS_None, // LEADZ
1993 CEFBS_None, // LOG0
1994 CEFBS_None, // LOG1
1995 CEFBS_None, // LOG2
1996 CEFBS_None, // LOG3
1997 CEFBS_None, // LOG4
1998 CEFBS_None, // MOVHI
1999 CEFBS_None, // NOP
2000 CEFBS_None, // OR_F_I_HI
2001 CEFBS_None, // OR_F_I_LO
2002 CEFBS_None, // OR_F_R
2003 CEFBS_None, // OR_I_HI
2004 CEFBS_None, // OR_I_LO
2005 CEFBS_None, // OR_R
2006 CEFBS_None, // POPC
2007 CEFBS_None, // RET
2008 CEFBS_None, // SA_F_I
2009 CEFBS_None, // SA_I
2010 CEFBS_None, // SCC
2011 CEFBS_None, // SELECT
2012 CEFBS_None, // SFSUB_F_RI_HI
2013 CEFBS_None, // SFSUB_F_RI_LO
2014 CEFBS_None, // SFSUB_F_RR
2015 CEFBS_None, // SHL_F_R
2016 CEFBS_None, // SHL_R
2017 CEFBS_None, // SLI
2018 CEFBS_None, // SL_F_I
2019 CEFBS_None, // SL_I
2020 CEFBS_None, // SRA_F_R
2021 CEFBS_None, // SRA_R
2022 CEFBS_None, // SRL_F_R
2023 CEFBS_None, // SRL_R
2024 CEFBS_None, // STADDR
2025 CEFBS_None, // STB_RI
2026 CEFBS_None, // STB_RR
2027 CEFBS_None, // STH_RI
2028 CEFBS_None, // STH_RR
2029 CEFBS_None, // SUBB_F_I_HI
2030 CEFBS_None, // SUBB_F_I_LO
2031 CEFBS_None, // SUBB_F_R
2032 CEFBS_None, // SUBB_I_HI
2033 CEFBS_None, // SUBB_I_LO
2034 CEFBS_None, // SUBB_R
2035 CEFBS_None, // SUB_F_I_HI
2036 CEFBS_None, // SUB_F_I_LO
2037 CEFBS_None, // SUB_F_R
2038 CEFBS_None, // SUB_I_HI
2039 CEFBS_None, // SUB_I_LO
2040 CEFBS_None, // SUB_R
2041 CEFBS_None, // SW_RI
2042 CEFBS_None, // SW_RR
2043 CEFBS_None, // TRAILZ
2044 CEFBS_None, // XOR_F_I_HI
2045 CEFBS_None, // XOR_F_I_LO
2046 CEFBS_None, // XOR_F_R
2047 CEFBS_None, // XOR_I_HI
2048 CEFBS_None, // XOR_I_LO
2049 CEFBS_None, // XOR_R
2050 };
2051
2052 assert(Opcode < 434);
2053 return FeatureBitsets[RequiredFeaturesRefs[Opcode]];
2054}
2055
2056
2057} // namespace llvm::Lanai_MC
2058
2059#endif // GET_COMPUTE_FEATURES
2060
2061#ifdef GET_AVAILABLE_OPCODE_CHECKER
2062#undef GET_AVAILABLE_OPCODE_CHECKER
2063
2064namespace llvm::Lanai_MC {
2065
2066bool isOpcodeAvailable(unsigned Opcode, const FeatureBitset &Features) {
2067 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
2068 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
2069 FeatureBitset MissingFeatures =
2070 (AvailableFeatures & RequiredFeatures) ^
2071 RequiredFeatures;
2072 return !MissingFeatures.any();
2073}
2074
2075} // namespace llvm::Lanai_MC
2076
2077#endif // GET_AVAILABLE_OPCODE_CHECKER
2078
2079#ifdef ENABLE_INSTR_PREDICATE_VERIFIER
2080#undef ENABLE_INSTR_PREDICATE_VERIFIER
2081
2082#include <sstream>
2083
2084namespace llvm::Lanai_MC {
2085
2086#ifndef NDEBUG
2087static const char *SubtargetFeatureNames[] = {
2088 nullptr
2089};
2090
2091#endif // NDEBUG
2092
2093void verifyInstructionPredicates(
2094 unsigned Opcode, const FeatureBitset &Features) {
2095#ifndef NDEBUG
2096 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
2097 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
2098 FeatureBitset MissingFeatures =
2099 (AvailableFeatures & RequiredFeatures) ^
2100 RequiredFeatures;
2101 if (MissingFeatures.any()) {
2102 std::ostringstream Msg;
2103 Msg << "Attempting to emit " << &LanaiInstrNameData[LanaiInstrNameIndices[Opcode]]
2104 << " instruction but the ";
2105 for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i)
2106 if (MissingFeatures.test(i))
2107 Msg << SubtargetFeatureNames[i] << " ";
2108 Msg << "predicate(s) are not met";
2109 report_fatal_error(Msg.str().c_str());
2110 }
2111#endif // NDEBUG
2112}
2113
2114} // namespace llvm::Lanai_MC
2115
2116#endif // ENABLE_INSTR_PREDICATE_VERIFIER
2117
2118#ifdef GET_INSTRMAP_INFO
2119#undef GET_INSTRMAP_INFO
2120
2121namespace llvm::Lanai {
2122
2123enum PostEncoderMethod {
2124 PostEncoderMethod_adjustPqBitsSpls
2125};
2126
2127// splsIdempotent
2128LLVM_READONLY
2129int32_t splsIdempotent(uint32_t Opcode) {
2130 using namespace Lanai;
2131 static constexpr uint32_t Table[][2] = {
2132 { LDBs_RI, LDBs_RI },
2133 { LDBz_RI, LDBz_RI },
2134 { LDHs_RI, LDHs_RI },
2135 { LDHz_RI, LDHz_RI },
2136 { STB_RI, STB_RI },
2137 { STH_RI, STH_RI },
2138 }; // End of Table
2139
2140 unsigned mid;
2141 unsigned start = 0;
2142 unsigned end = 6;
2143 while (start < end) {
2144 mid = start + (end - start) / 2;
2145 if (Opcode == Table[mid][0])
2146 break;
2147 if (Opcode < Table[mid][0])
2148 end = mid;
2149 else
2150 start = mid + 1;
2151 }
2152 if (start == end)
2153 return -1; // Instruction doesn't exist in this table.
2154
2155 return Table[mid][1];
2156}
2157
2158
2159} // namespace llvm::Lanai
2160
2161#endif // GET_INSTRMAP_INFO
2162
2163