1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Instruction Enum Values and Descriptors *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_INSTRINFO_ENUM
10#undef GET_INSTRINFO_ENUM
11
12namespace llvm::Lanai {
13
14 enum {
15 PHI = 0, // Target.td:1200
16 INLINEASM = 1, // Target.td:1206
17 INLINEASM_BR = 2, // Target.td:1212
18 CFI_INSTRUCTION = 3, // Target.td:1221
19 EH_LABEL = 4, // Target.td:1230
20 GC_LABEL = 5, // Target.td:1239
21 ANNOTATION_LABEL = 6, // Target.td:1248
22 KILL = 7, // Target.td:1256
23 EXTRACT_SUBREG = 8, // Target.td:1263
24 INSERT_SUBREG = 9, // Target.td:1269
25 IMPLICIT_DEF = 10, // Target.td:1276
26 INIT_UNDEF = 11, // Target.td:1285
27 SUBREG_TO_REG = 12, // Target.td:1292
28 COPY_TO_REGCLASS = 13, // Target.td:1298
29 DBG_VALUE = 14, // Target.td:1305
30 DBG_VALUE_LIST = 15, // Target.td:1312
31 DBG_INSTR_REF = 16, // Target.td:1319
32 DBG_PHI = 17, // Target.td:1326
33 DBG_LABEL = 18, // Target.td:1333
34 REG_SEQUENCE = 19, // Target.td:1340
35 COPY = 20, // Target.td:1347
36 COPY_LANEMASK = 21, // Target.td:1355
37 BUNDLE = 22, // Target.td:1362
38 LIFETIME_START = 23, // Target.td:1368
39 LIFETIME_END = 24, // Target.td:1375
40 PSEUDO_PROBE = 25, // Target.td:1382
41 ARITH_FENCE = 26, // Target.td:1389
42 STACKMAP = 27, // Target.td:1398
43 FENTRY_CALL = 28, // Target.td:1533
44 PATCHPOINT = 29, // Target.td:1406
45 LOAD_STACK_GUARD = 30, // Target.td:1424
46 PREALLOCATED_SETUP = 31, // Target.td:1432
47 PREALLOCATED_ARG = 32, // Target.td:1438
48 STATEPOINT = 33, // Target.td:1415
49 LOCAL_ESCAPE = 34, // Target.td:1444
50 FAULTING_OP = 35, // Target.td:1453
51 PATCHABLE_OP = 36, // Target.td:1473
52 PATCHABLE_FUNCTION_ENTER = 37, // Target.td:1481
53 PATCHABLE_RET = 38, // Target.td:1488
54 PATCHABLE_FUNCTION_EXIT = 39, // Target.td:1497
55 PATCHABLE_TAIL_CALL = 40, // Target.td:1505
56 PATCHABLE_EVENT_CALL = 41, // Target.td:1513
57 PATCHABLE_TYPED_EVENT_CALL = 42, // Target.td:1523
58 ICALL_BRANCH_FUNNEL = 43, // Target.td:1543
59 FAKE_USE = 44, // Target.td:1463
60 MEMBARRIER = 45, // Target.td:1549
61 JUMP_TABLE_DEBUG_INFO = 46, // Target.td:1557
62 RELOC_NONE = 47, // Target.td:1565
63 CONVERGENCECTRL_ENTRY = 48, // Target.td:1576
64 CONVERGENCECTRL_ANCHOR = 49, // Target.td:1572
65 CONVERGENCECTRL_LOOP = 50, // Target.td:1580
66 CONVERGENCECTRL_GLUE = 51, // Target.td:1584
67 G_ASSERT_SEXT = 52, // GenericOpcodes.td:1865
68 G_ASSERT_ZEXT = 53, // GenericOpcodes.td:1857
69 G_ASSERT_ALIGN = 54, // GenericOpcodes.td:1872
70 G_ADD = 55, // GenericOpcodes.td:300
71 G_SUB = 56, // GenericOpcodes.td:308
72 G_MUL = 57, // GenericOpcodes.td:316
73 G_SDIV = 58, // GenericOpcodes.td:324
74 G_UDIV = 59, // GenericOpcodes.td:332
75 G_SREM = 60, // GenericOpcodes.td:340
76 G_UREM = 61, // GenericOpcodes.td:348
77 G_SDIVREM = 62, // GenericOpcodes.td:356
78 G_UDIVREM = 63, // GenericOpcodes.td:364
79 G_AND = 64, // GenericOpcodes.td:372
80 G_OR = 65, // GenericOpcodes.td:380
81 G_XOR = 66, // GenericOpcodes.td:388
82 G_ABDS = 67, // GenericOpcodes.td:417
83 G_ABDU = 68, // GenericOpcodes.td:425
84 G_UAVGFLOOR = 69, // GenericOpcodes.td:433
85 G_UAVGCEIL = 70, // GenericOpcodes.td:440
86 G_SAVGFLOOR = 71, // GenericOpcodes.td:447
87 G_SAVGCEIL = 72, // GenericOpcodes.td:454
88 G_IMPLICIT_DEF = 73, // GenericOpcodes.td:110
89 G_PHI = 74, // GenericOpcodes.td:116
90 G_FRAME_INDEX = 75, // GenericOpcodes.td:122
91 G_GLOBAL_VALUE = 76, // GenericOpcodes.td:128
92 G_PTRAUTH_GLOBAL_VALUE = 77, // GenericOpcodes.td:134
93 G_CONSTANT_POOL = 78, // GenericOpcodes.td:140
94 G_EXTRACT = 79, // GenericOpcodes.td:1472
95 G_UNMERGE_VALUES = 80, // GenericOpcodes.td:1484
96 G_INSERT = 81, // GenericOpcodes.td:1492
97 G_MERGE_VALUES = 82, // GenericOpcodes.td:1502
98 G_BUILD_VECTOR = 83, // GenericOpcodes.td:1521
99 G_BUILD_VECTOR_TRUNC = 84, // GenericOpcodes.td:1530
100 G_CONCAT_VECTORS = 85, // GenericOpcodes.td:1537
101 G_PTRTOINT = 86, // GenericOpcodes.td:152
102 G_INTTOPTR = 87, // GenericOpcodes.td:146
103 G_BITCAST = 88, // GenericOpcodes.td:158
104 G_FREEZE = 89, // GenericOpcodes.td:277
105 G_CONSTANT_FOLD_BARRIER = 90, // GenericOpcodes.td:1879
106 G_INTRINSIC_FPTRUNC_ROUND = 91, // GenericOpcodes.td:1263
107 G_INTRINSIC_TRUNC = 92, // GenericOpcodes.td:1269
108 G_INTRINSIC_ROUND = 93, // GenericOpcodes.td:1275
109 G_INTRINSIC_LRINT = 94, // GenericOpcodes.td:1281
110 G_INTRINSIC_LLRINT = 95, // GenericOpcodes.td:1287
111 G_INTRINSIC_ROUNDEVEN = 96, // GenericOpcodes.td:1293
112 G_READCYCLECOUNTER = 97, // GenericOpcodes.td:1299
113 G_READSTEADYCOUNTER = 98, // GenericOpcodes.td:1305
114 G_LOAD = 99, // GenericOpcodes.td:1332
115 G_SEXTLOAD = 100, // GenericOpcodes.td:1340
116 G_ZEXTLOAD = 101, // GenericOpcodes.td:1348
117 G_INDEXED_LOAD = 102, // GenericOpcodes.td:1358
118 G_INDEXED_SEXTLOAD = 103, // GenericOpcodes.td:1366
119 G_INDEXED_ZEXTLOAD = 104, // GenericOpcodes.td:1374
120 G_STORE = 105, // GenericOpcodes.td:1382
121 G_INDEXED_STORE = 106, // GenericOpcodes.td:1390
122 G_ATOMIC_CMPXCHG_WITH_SUCCESS = 107, // GenericOpcodes.td:1400
123 G_ATOMIC_CMPXCHG = 108, // GenericOpcodes.td:1410
124 G_ATOMICRMW_XCHG = 109, // GenericOpcodes.td:1428
125 G_ATOMICRMW_ADD = 110, // GenericOpcodes.td:1429
126 G_ATOMICRMW_SUB = 111, // GenericOpcodes.td:1430
127 G_ATOMICRMW_AND = 112, // GenericOpcodes.td:1431
128 G_ATOMICRMW_NAND = 113, // GenericOpcodes.td:1432
129 G_ATOMICRMW_OR = 114, // GenericOpcodes.td:1433
130 G_ATOMICRMW_XOR = 115, // GenericOpcodes.td:1434
131 G_ATOMICRMW_MAX = 116, // GenericOpcodes.td:1435
132 G_ATOMICRMW_MIN = 117, // GenericOpcodes.td:1436
133 G_ATOMICRMW_UMAX = 118, // GenericOpcodes.td:1437
134 G_ATOMICRMW_UMIN = 119, // GenericOpcodes.td:1438
135 G_ATOMICRMW_FADD = 120, // GenericOpcodes.td:1439
136 G_ATOMICRMW_FSUB = 121, // GenericOpcodes.td:1440
137 G_ATOMICRMW_FMAX = 122, // GenericOpcodes.td:1441
138 G_ATOMICRMW_FMIN = 123, // GenericOpcodes.td:1442
139 G_ATOMICRMW_FMAXIMUM = 124, // GenericOpcodes.td:1443
140 G_ATOMICRMW_FMINIMUM = 125, // GenericOpcodes.td:1444
141 G_ATOMICRMW_UINC_WRAP = 126, // GenericOpcodes.td:1445
142 G_ATOMICRMW_UDEC_WRAP = 127, // GenericOpcodes.td:1446
143 G_ATOMICRMW_USUB_COND = 128, // GenericOpcodes.td:1447
144 G_ATOMICRMW_USUB_SAT = 129, // GenericOpcodes.td:1448
145 G_FENCE = 130, // GenericOpcodes.td:1450
146 G_PREFETCH = 131, // GenericOpcodes.td:1457
147 G_BRCOND = 132, // GenericOpcodes.td:1592
148 G_BRINDIRECT = 133, // GenericOpcodes.td:1601
149 G_INVOKE_REGION_START = 134, // GenericOpcodes.td:1624
150 G_INTRINSIC = 135, // GenericOpcodes.td:1544
151 G_INTRINSIC_W_SIDE_EFFECTS = 136, // GenericOpcodes.td:1551
152 G_INTRINSIC_CONVERGENT = 137, // GenericOpcodes.td:1560
153 G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 138, // GenericOpcodes.td:1568
154 G_ANYEXT = 139, // GenericOpcodes.td:44
155 G_TRUNC = 140, // GenericOpcodes.td:83
156 G_TRUNC_SSAT_S = 141, // GenericOpcodes.td:90
157 G_TRUNC_SSAT_U = 142, // GenericOpcodes.td:97
158 G_TRUNC_USAT_U = 143, // GenericOpcodes.td:104
159 G_CONSTANT = 144, // GenericOpcodes.td:165
160 G_FCONSTANT = 145, // GenericOpcodes.td:172
161 G_VASTART = 146, // GenericOpcodes.td:178
162 G_VAARG = 147, // GenericOpcodes.td:185
163 G_SEXT = 148, // GenericOpcodes.td:52
164 G_SEXT_INREG = 149, // GenericOpcodes.td:66
165 G_ZEXT = 150, // GenericOpcodes.td:74
166 G_SHL = 151, // GenericOpcodes.td:396
167 G_LSHR = 152, // GenericOpcodes.td:403
168 G_ASHR = 153, // GenericOpcodes.td:410
169 G_FSHL = 154, // GenericOpcodes.td:462
170 G_FSHR = 155, // GenericOpcodes.td:470
171 G_ROTR = 156, // GenericOpcodes.td:477
172 G_ROTL = 157, // GenericOpcodes.td:484
173 G_ICMP = 158, // GenericOpcodes.td:491
174 G_FCMP = 159, // GenericOpcodes.td:498
175 G_SCMP = 160, // GenericOpcodes.td:505
176 G_UCMP = 161, // GenericOpcodes.td:512
177 G_SELECT = 162, // GenericOpcodes.td:519
178 G_UADDO = 163, // GenericOpcodes.td:584
179 G_UADDE = 164, // GenericOpcodes.td:592
180 G_USUBO = 165, // GenericOpcodes.td:614
181 G_USUBE = 166, // GenericOpcodes.td:620
182 G_SADDO = 167, // GenericOpcodes.td:599
183 G_SADDE = 168, // GenericOpcodes.td:607
184 G_SSUBO = 169, // GenericOpcodes.td:627
185 G_SSUBE = 170, // GenericOpcodes.td:634
186 G_UMULO = 171, // GenericOpcodes.td:641
187 G_SMULO = 172, // GenericOpcodes.td:649
188 G_UMULH = 173, // GenericOpcodes.td:658
189 G_SMULH = 174, // GenericOpcodes.td:667
190 G_UADDSAT = 175, // GenericOpcodes.td:679
191 G_SADDSAT = 176, // GenericOpcodes.td:687
192 G_USUBSAT = 177, // GenericOpcodes.td:695
193 G_SSUBSAT = 178, // GenericOpcodes.td:703
194 G_USHLSAT = 179, // GenericOpcodes.td:711
195 G_SSHLSAT = 180, // GenericOpcodes.td:719
196 G_SMULFIX = 181, // GenericOpcodes.td:731
197 G_UMULFIX = 182, // GenericOpcodes.td:738
198 G_SMULFIXSAT = 183, // GenericOpcodes.td:748
199 G_UMULFIXSAT = 184, // GenericOpcodes.td:755
200 G_SDIVFIX = 185, // GenericOpcodes.td:766
201 G_UDIVFIX = 186, // GenericOpcodes.td:773
202 G_SDIVFIXSAT = 187, // GenericOpcodes.td:783
203 G_UDIVFIXSAT = 188, // GenericOpcodes.td:790
204 G_FADD = 189, // GenericOpcodes.td:963
205 G_FSUB = 190, // GenericOpcodes.td:971
206 G_FMUL = 191, // GenericOpcodes.td:979
207 G_FMA = 192, // GenericOpcodes.td:988
208 G_FMAD = 193, // GenericOpcodes.td:997
209 G_FDIV = 194, // GenericOpcodes.td:1005
210 G_FREM = 195, // GenericOpcodes.td:1012
211 G_FMODF = 196, // GenericOpcodes.td:1019
212 G_FPOW = 197, // GenericOpcodes.td:1026
213 G_FPOWI = 198, // GenericOpcodes.td:1033
214 G_FEXP = 199, // GenericOpcodes.td:1040
215 G_FEXP2 = 200, // GenericOpcodes.td:1047
216 G_FEXP10 = 201, // GenericOpcodes.td:1054
217 G_FLOG = 202, // GenericOpcodes.td:1061
218 G_FLOG2 = 203, // GenericOpcodes.td:1068
219 G_FLOG10 = 204, // GenericOpcodes.td:1075
220 G_FLDEXP = 205, // GenericOpcodes.td:1082
221 G_FFREXP = 206, // GenericOpcodes.td:1089
222 G_FNEG = 207, // GenericOpcodes.td:801
223 G_FPEXT = 208, // GenericOpcodes.td:807
224 G_FPTRUNC = 209, // GenericOpcodes.td:813
225 G_FPTOSI = 210, // GenericOpcodes.td:819
226 G_FPTOUI = 211, // GenericOpcodes.td:825
227 G_SITOFP = 212, // GenericOpcodes.td:831
228 G_UITOFP = 213, // GenericOpcodes.td:837
229 G_FPTOSI_SAT = 214, // GenericOpcodes.td:843
230 G_FPTOUI_SAT = 215, // GenericOpcodes.td:849
231 G_FABS = 216, // GenericOpcodes.td:855
232 G_FCOPYSIGN = 217, // GenericOpcodes.td:861
233 G_IS_FPCLASS = 218, // GenericOpcodes.td:874
234 G_FCANONICALIZE = 219, // GenericOpcodes.td:867
235 G_FMINNUM = 220, // GenericOpcodes.td:887
236 G_FMAXNUM = 221, // GenericOpcodes.td:894
237 G_FMINNUM_IEEE = 222, // GenericOpcodes.td:912
238 G_FMAXNUM_IEEE = 223, // GenericOpcodes.td:919
239 G_FMINIMUM = 224, // GenericOpcodes.td:929
240 G_FMAXIMUM = 225, // GenericOpcodes.td:936
241 G_FMINIMUMNUM = 226, // GenericOpcodes.td:944
242 G_FMAXIMUMNUM = 227, // GenericOpcodes.td:951
243 G_GET_FPENV = 228, // GenericOpcodes.td:1219
244 G_SET_FPENV = 229, // GenericOpcodes.td:1226
245 G_RESET_FPENV = 230, // GenericOpcodes.td:1233
246 G_GET_FPMODE = 231, // GenericOpcodes.td:1240
247 G_SET_FPMODE = 232, // GenericOpcodes.td:1247
248 G_RESET_FPMODE = 233, // GenericOpcodes.td:1254
249 G_GET_ROUNDING = 234, // GenericOpcodes.td:1311
250 G_SET_ROUNDING = 235, // GenericOpcodes.td:1317
251 G_PTR_ADD = 236, // GenericOpcodes.td:526
252 G_PTRMASK = 237, // GenericOpcodes.td:534
253 G_SMIN = 238, // GenericOpcodes.td:541
254 G_SMAX = 239, // GenericOpcodes.td:549
255 G_UMIN = 240, // GenericOpcodes.td:557
256 G_UMAX = 241, // GenericOpcodes.td:565
257 G_ABS = 242, // GenericOpcodes.td:573
258 G_LROUND = 243, // GenericOpcodes.td:283
259 G_LLROUND = 244, // GenericOpcodes.td:289
260 G_BR = 245, // GenericOpcodes.td:1582
261 G_BRJT = 246, // GenericOpcodes.td:1612
262 G_VSCALE = 247, // GenericOpcodes.td:1512
263 G_INSERT_SUBVECTOR = 248, // GenericOpcodes.td:1656
264 G_EXTRACT_SUBVECTOR = 249, // GenericOpcodes.td:1663
265 G_INSERT_VECTOR_ELT = 250, // GenericOpcodes.td:1670
266 G_EXTRACT_VECTOR_ELT = 251, // GenericOpcodes.td:1677
267 G_SHUFFLE_VECTOR = 252, // GenericOpcodes.td:1687
268 G_SPLAT_VECTOR = 253, // GenericOpcodes.td:1694
269 G_STEP_VECTOR = 254, // GenericOpcodes.td:1701
270 G_VECTOR_COMPRESS = 255, // GenericOpcodes.td:1708
271 G_CTTZ = 256, // GenericOpcodes.td:205
272 G_CTTZ_ZERO_UNDEF = 257, // GenericOpcodes.td:211
273 G_CTLZ = 258, // GenericOpcodes.td:193
274 G_CTLZ_ZERO_UNDEF = 259, // GenericOpcodes.td:199
275 G_CTLS = 260, // GenericOpcodes.td:217
276 G_CTPOP = 261, // GenericOpcodes.td:223
277 G_BSWAP = 262, // GenericOpcodes.td:229
278 G_BITREVERSE = 263, // GenericOpcodes.td:235
279 G_FCEIL = 264, // GenericOpcodes.td:1096
280 G_FCOS = 265, // GenericOpcodes.td:1103
281 G_FSIN = 266, // GenericOpcodes.td:1110
282 G_FSINCOS = 267, // GenericOpcodes.td:1117
283 G_FTAN = 268, // GenericOpcodes.td:1124
284 G_FACOS = 269, // GenericOpcodes.td:1131
285 G_FASIN = 270, // GenericOpcodes.td:1138
286 G_FATAN = 271, // GenericOpcodes.td:1145
287 G_FATAN2 = 272, // GenericOpcodes.td:1152
288 G_FCOSH = 273, // GenericOpcodes.td:1159
289 G_FSINH = 274, // GenericOpcodes.td:1166
290 G_FTANH = 275, // GenericOpcodes.td:1173
291 G_FSQRT = 276, // GenericOpcodes.td:1183
292 G_FFLOOR = 277, // GenericOpcodes.td:1190
293 G_FRINT = 278, // GenericOpcodes.td:1197
294 G_FNEARBYINT = 279, // GenericOpcodes.td:1204
295 G_ADDRSPACE_CAST = 280, // GenericOpcodes.td:241
296 G_BLOCK_ADDR = 281, // GenericOpcodes.td:247
297 G_JUMP_TABLE = 282, // GenericOpcodes.td:253
298 G_DYN_STACKALLOC = 283, // GenericOpcodes.td:259
299 G_STACKSAVE = 284, // GenericOpcodes.td:265
300 G_STACKRESTORE = 285, // GenericOpcodes.td:271
301 G_STRICT_FADD = 286, // GenericOpcodes.td:1758
302 G_STRICT_FSUB = 287, // GenericOpcodes.td:1759
303 G_STRICT_FMUL = 288, // GenericOpcodes.td:1760
304 G_STRICT_FDIV = 289, // GenericOpcodes.td:1761
305 G_STRICT_FREM = 290, // GenericOpcodes.td:1762
306 G_STRICT_FMA = 291, // GenericOpcodes.td:1763
307 G_STRICT_FSQRT = 292, // GenericOpcodes.td:1764
308 G_STRICT_FLDEXP = 293, // GenericOpcodes.td:1765
309 G_READ_REGISTER = 294, // GenericOpcodes.td:1631
310 G_WRITE_REGISTER = 295, // GenericOpcodes.td:1641
311 G_MEMCPY = 296, // GenericOpcodes.td:1771
312 G_MEMCPY_INLINE = 297, // GenericOpcodes.td:1779
313 G_MEMMOVE = 298, // GenericOpcodes.td:1787
314 G_MEMSET = 299, // GenericOpcodes.td:1795
315 G_BZERO = 300, // GenericOpcodes.td:1802
316 G_TRAP = 301, // GenericOpcodes.td:1812
317 G_DEBUGTRAP = 302, // GenericOpcodes.td:1819
318 G_UBSANTRAP = 303, // GenericOpcodes.td:1825
319 G_VECREDUCE_SEQ_FADD = 304, // GenericOpcodes.td:1724
320 G_VECREDUCE_SEQ_FMUL = 305, // GenericOpcodes.td:1730
321 G_VECREDUCE_FADD = 306, // GenericOpcodes.td:1736
322 G_VECREDUCE_FMUL = 307, // GenericOpcodes.td:1737
323 G_VECREDUCE_FMAX = 308, // GenericOpcodes.td:1739
324 G_VECREDUCE_FMIN = 309, // GenericOpcodes.td:1740
325 G_VECREDUCE_FMAXIMUM = 310, // GenericOpcodes.td:1741
326 G_VECREDUCE_FMINIMUM = 311, // GenericOpcodes.td:1742
327 G_VECREDUCE_ADD = 312, // GenericOpcodes.td:1744
328 G_VECREDUCE_MUL = 313, // GenericOpcodes.td:1745
329 G_VECREDUCE_AND = 314, // GenericOpcodes.td:1746
330 G_VECREDUCE_OR = 315, // GenericOpcodes.td:1747
331 G_VECREDUCE_XOR = 316, // GenericOpcodes.td:1748
332 G_VECREDUCE_SMAX = 317, // GenericOpcodes.td:1749
333 G_VECREDUCE_SMIN = 318, // GenericOpcodes.td:1750
334 G_VECREDUCE_UMAX = 319, // GenericOpcodes.td:1751
335 G_VECREDUCE_UMIN = 320, // GenericOpcodes.td:1752
336 G_SBFX = 321, // GenericOpcodes.td:1837
337 G_UBFX = 322, // GenericOpcodes.td:1845
338 ADJCALLSTACKDOWN = 323, // LanaiInstrInfo.td:753
339 ADJCALLSTACKUP = 324, // LanaiInstrInfo.td:756
340 ADJDYNALLOC = 325, // LanaiInstrInfo.td:762
341 CALL = 326, // LanaiInstrInfo.td:727
342 CALLR = 327, // LanaiInstrInfo.td:728
343 ADDC_F_I_HI = 328, // LanaiInstrInfo.td:281
344 ADDC_F_I_LO = 329, // LanaiInstrInfo.td:277
345 ADDC_F_R = 330, // LanaiInstrInfo.td:293
346 ADDC_I_HI = 331, // LanaiInstrInfo.td:281
347 ADDC_I_LO = 332, // LanaiInstrInfo.td:277
348 ADDC_R = 333, // LanaiInstrInfo.td:293
349 ADD_F_I_HI = 334, // LanaiInstrInfo.td:281
350 ADD_F_I_LO = 335, // LanaiInstrInfo.td:277
351 ADD_F_R = 336, // LanaiInstrInfo.td:293
352 ADD_I_HI = 337, // LanaiInstrInfo.td:281
353 ADD_I_LO = 338, // LanaiInstrInfo.td:277
354 ADD_R = 339, // LanaiInstrInfo.td:293
355 AND_F_I_HI = 340, // LanaiInstrInfo.td:281
356 AND_F_I_LO = 341, // LanaiInstrInfo.td:277
357 AND_F_R = 342, // LanaiInstrInfo.td:306
358 AND_I_HI = 343, // LanaiInstrInfo.td:281
359 AND_I_LO = 344, // LanaiInstrInfo.td:277
360 AND_R = 345, // LanaiInstrInfo.td:306
361 BRCC = 346, // LanaiInstrInfo.td:685
362 BRIND_CC = 347, // LanaiInstrInfo.td:788
363 BRIND_CCA = 348, // LanaiInstrInfo.td:796
364 BRR = 349, // LanaiInstrInfo.td:808
365 BT = 350, // LanaiInstrInfo.td:679
366 JR = 351, // LanaiInstrInfo.td:690
367 LDADDR = 352, // LanaiInstrInfo.td:542
368 LDBs_RI = 353, // LanaiInstrInfo.td:580
369 LDBs_RR = 354, // LanaiInstrInfo.td:539
370 LDBz_RI = 355, // LanaiInstrInfo.td:577
371 LDBz_RR = 356, // LanaiInstrInfo.td:532
372 LDHs_RI = 357, // LanaiInstrInfo.td:574
373 LDHs_RR = 358, // LanaiInstrInfo.td:537
374 LDHz_RI = 359, // LanaiInstrInfo.td:571
375 LDHz_RR = 360, // LanaiInstrInfo.td:530
376 LDW_RI = 361, // LanaiInstrInfo.td:515
377 LDW_RR = 362, // LanaiInstrInfo.td:516
378 LDWz_RR = 363, // LanaiInstrInfo.td:524
379 LEADZ = 364, // LanaiInstrInfo.td:818
380 LOG0 = 365, // LanaiInstrInfo.td:249
381 LOG1 = 366, // LanaiInstrInfo.td:251
382 LOG2 = 367, // LanaiInstrInfo.td:253
383 LOG3 = 368, // LanaiInstrInfo.td:255
384 LOG4 = 369, // LanaiInstrInfo.td:257
385 MOVHI = 370, // LanaiInstrInfo.td:408
386 NOP = 371, // LanaiInstrInfo.td:245
387 OR_F_I_HI = 372, // LanaiInstrInfo.td:281
388 OR_F_I_LO = 373, // LanaiInstrInfo.td:277
389 OR_F_R = 374, // LanaiInstrInfo.td:306
390 OR_I_HI = 375, // LanaiInstrInfo.td:281
391 OR_I_LO = 376, // LanaiInstrInfo.td:277
392 OR_R = 377, // LanaiInstrInfo.td:306
393 POPC = 378, // LanaiInstrInfo.td:813
394 RET = 379, // LanaiInstrInfo.td:733
395 SA_F_I = 380, // LanaiInstrInfo.td:439
396 SA_I = 381, // LanaiInstrInfo.td:430
397 SCC = 382, // LanaiInstrInfo.td:768
398 SELECT = 383, // LanaiInstrInfo.td:775
399 SFSUB_F_RI_HI = 384, // LanaiInstrInfo.td:716
400 SFSUB_F_RI_LO = 385, // LanaiInstrInfo.td:712
401 SFSUB_F_RR = 386, // LanaiInstrInfo.td:708
402 SHL_F_R = 387, // LanaiInstrInfo.td:460
403 SHL_R = 388, // LanaiInstrInfo.td:448
404 SLI = 389, // LanaiInstrInfo.td:582
405 SL_F_I = 390, // LanaiInstrInfo.td:437
406 SL_I = 391, // LanaiInstrInfo.td:428
407 SRA_F_R = 392, // LanaiInstrInfo.td:466
408 SRA_R = 393, // LanaiInstrInfo.td:455
409 SRL_F_R = 394, // LanaiInstrInfo.td:463
410 SRL_R = 395, // LanaiInstrInfo.td:452
411 STADDR = 396, // LanaiInstrInfo.td:641
412 STB_RI = 397, // LanaiInstrInfo.td:672
413 STB_RR = 398, // LanaiInstrInfo.td:638
414 STH_RI = 399, // LanaiInstrInfo.td:669
415 STH_RR = 400, // LanaiInstrInfo.td:636
416 SUBB_F_I_HI = 401, // LanaiInstrInfo.td:281
417 SUBB_F_I_LO = 402, // LanaiInstrInfo.td:277
418 SUBB_F_R = 403, // LanaiInstrInfo.td:293
419 SUBB_I_HI = 404, // LanaiInstrInfo.td:281
420 SUBB_I_LO = 405, // LanaiInstrInfo.td:277
421 SUBB_R = 406, // LanaiInstrInfo.td:293
422 SUB_F_I_HI = 407, // LanaiInstrInfo.td:281
423 SUB_F_I_LO = 408, // LanaiInstrInfo.td:277
424 SUB_F_R = 409, // LanaiInstrInfo.td:293
425 SUB_I_HI = 410, // LanaiInstrInfo.td:281
426 SUB_I_LO = 411, // LanaiInstrInfo.td:277
427 SUB_R = 412, // LanaiInstrInfo.td:293
428 SW_RI = 413, // LanaiInstrInfo.td:631
429 SW_RR = 414, // LanaiInstrInfo.td:630
430 TRAILZ = 415, // LanaiInstrInfo.td:822
431 XOR_F_I_HI = 416, // LanaiInstrInfo.td:281
432 XOR_F_I_LO = 417, // LanaiInstrInfo.td:277
433 XOR_F_R = 418, // LanaiInstrInfo.td:306
434 XOR_I_HI = 419, // LanaiInstrInfo.td:281
435 XOR_I_LO = 420, // LanaiInstrInfo.td:277
436 XOR_R = 421, // LanaiInstrInfo.td:306
437 INSTRUCTION_LIST_END = 422
438 };
439
440} // namespace llvm::Lanai
441
442#endif // GET_INSTRINFO_ENUM
443
444#ifdef GET_INSTRINFO_SCHED_ENUM
445#undef GET_INSTRINFO_SCHED_ENUM
446
447namespace llvm::Lanai::Sched {
448
449 enum {
450 NoInstrModel = 0,
451 IIC_ALU_WriteALU = 1,
452 IIC_ALU = 2,
453 IIC_LD_WriteLD = 3,
454 IIC_LDSW_WriteLDSW = 4,
455 WriteLD = 5,
456 IIC_ST_WriteST = 6,
457 IIC_STSW_WriteSTSW = 7,
458 SCHED_LIST_END = 8
459 };
460
461} // namespace llvm::Lanai::Sched
462
463#endif // GET_INSTRINFO_SCHED_ENUM
464
465#if defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
466
467namespace llvm {
468
469struct LanaiInstrTable {
470 MCInstrDesc Insts[422];
471 static_assert(alignof(MCInstrDesc) >= alignof(MCPhysReg), "Unwanted padding between Insts and ImplicitOps");
472 MCPhysReg ImplicitOps[8];
473 char Padding[sizeof(MCOperandInfo) - sizeof ImplicitOps % sizeof(MCOperandInfo)];
474 static_assert(alignof(MCInstrDesc) >= alignof(MCOperandInfo), "Unwanted padding between Insts and OperandInfo");
475 MCOperandInfo OperandInfo[178];
476};
477} // namespace llvm
478
479#endif // defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
480
481#ifdef GET_INSTRINFO_MC_DESC
482#undef GET_INSTRINFO_MC_DESC
483
484namespace llvm {
485
486static_assert((sizeof LanaiInstrTable::ImplicitOps + sizeof LanaiInstrTable::Padding) % sizeof(MCOperandInfo) == 0);
487static constexpr unsigned LanaiOpInfoBase = (sizeof LanaiInstrTable::ImplicitOps + sizeof LanaiInstrTable::Padding) / sizeof(MCOperandInfo);
488
489extern const LanaiInstrTable LanaiDescs = {
490 {
491 { 421, 4, 1, 4, 1, 0, 0, LanaiOpInfoBase + 160, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR_R
492 { 420, 3, 1, 4, 1, 0, 0, LanaiOpInfoBase + 157, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR_I_LO
493 { 419, 3, 1, 4, 1, 0, 0, LanaiOpInfoBase + 157, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR_I_HI
494 { 418, 4, 1, 4, 1, 0, 1, LanaiOpInfoBase + 160, 6, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR_F_R
495 { 417, 3, 1, 4, 1, 0, 1, LanaiOpInfoBase + 157, 6, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR_F_I_LO
496 { 416, 3, 1, 4, 1, 0, 1, LanaiOpInfoBase + 157, 6, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR_F_I_HI
497 { 415, 2, 1, 4, 1, 0, 0, LanaiOpInfoBase + 155, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TRAILZ
498 { 414, 4, 0, 4, 6, 0, 0, LanaiOpInfoBase + 170, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SW_RR
499 { 413, 4, 0, 4, 6, 0, 0, LanaiOpInfoBase + 166, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SW_RI
500 { 412, 4, 1, 4, 1, 0, 0, LanaiOpInfoBase + 160, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_R
501 { 411, 3, 1, 4, 1, 0, 0, LanaiOpInfoBase + 157, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_I_LO
502 { 410, 3, 1, 4, 1, 0, 0, LanaiOpInfoBase + 157, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_I_HI
503 { 409, 4, 1, 4, 1, 0, 1, LanaiOpInfoBase + 160, 6, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_F_R
504 { 408, 3, 1, 4, 1, 0, 1, LanaiOpInfoBase + 157, 6, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_F_I_LO
505 { 407, 3, 1, 4, 1, 0, 1, LanaiOpInfoBase + 157, 6, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_F_I_HI
506 { 406, 4, 1, 4, 1, 1, 0, LanaiOpInfoBase + 160, 6, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBB_R
507 { 405, 3, 1, 4, 1, 1, 0, LanaiOpInfoBase + 157, 6, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBB_I_LO
508 { 404, 3, 1, 4, 1, 1, 0, LanaiOpInfoBase + 157, 6, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBB_I_HI
509 { 403, 4, 1, 4, 1, 1, 1, LanaiOpInfoBase + 160, 4, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBB_F_R
510 { 402, 3, 1, 4, 1, 1, 1, LanaiOpInfoBase + 157, 4, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBB_F_I_LO
511 { 401, 3, 1, 4, 1, 1, 1, LanaiOpInfoBase + 157, 4, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBB_F_I_HI
512 { 400, 4, 0, 4, 6, 0, 0, LanaiOpInfoBase + 170, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STH_RR
513 { 399, 4, 0, 4, 7, 0, 0, LanaiOpInfoBase + 166, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STH_RI
514 { 398, 4, 0, 4, 6, 0, 0, LanaiOpInfoBase + 170, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STB_RR
515 { 397, 4, 0, 4, 7, 0, 0, LanaiOpInfoBase + 166, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STB_RI
516 { 396, 2, 0, 4, 6, 0, 0, LanaiOpInfoBase + 38, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STADDR
517 { 395, 4, 1, 4, 1, 0, 0, LanaiOpInfoBase + 160, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SRL_R
518 { 394, 4, 1, 4, 1, 0, 1, LanaiOpInfoBase + 160, 6, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SRL_F_R
519 { 393, 4, 1, 4, 1, 0, 0, LanaiOpInfoBase + 160, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SRA_R
520 { 392, 4, 1, 4, 1, 0, 1, LanaiOpInfoBase + 160, 6, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SRA_F_R
521 { 391, 3, 1, 4, 1, 0, 0, LanaiOpInfoBase + 157, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SL_I
522 { 390, 3, 1, 4, 1, 0, 1, LanaiOpInfoBase + 157, 6, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SL_F_I
523 { 389, 2, 1, 4, 0, 0, 0, LanaiOpInfoBase + 38, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SLI
524 { 388, 4, 1, 4, 1, 0, 0, LanaiOpInfoBase + 160, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHL_R
525 { 387, 4, 1, 4, 1, 0, 1, LanaiOpInfoBase + 160, 6, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHL_F_R
526 { 386, 2, 0, 4, 1, 0, 1, LanaiOpInfoBase + 155, 6, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SFSUB_F_RR
527 { 385, 2, 0, 4, 1, 0, 1, LanaiOpInfoBase + 38, 6, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SFSUB_F_RI_LO
528 { 384, 2, 0, 4, 1, 0, 1, LanaiOpInfoBase + 38, 6, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SFSUB_F_RI_HI
529 { 383, 4, 1, 4, 1, 1, 0, LanaiOpInfoBase + 174, 6, 0|(1ULL<<MCID::Select)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SELECT
530 { 382, 2, 1, 4, 2, 1, 0, LanaiOpInfoBase + 38, 6, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SCC
531 { 381, 3, 1, 4, 1, 0, 0, LanaiOpInfoBase + 157, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SA_I
532 { 380, 3, 1, 4, 1, 0, 1, LanaiOpInfoBase + 157, 6, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SA_F_I
533 { 379, 0, 0, 4, 0, 1, 0, LanaiOpInfoBase + 1, 7, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RET
534 { 378, 2, 1, 4, 1, 0, 0, LanaiOpInfoBase + 155, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // POPC
535 { 377, 4, 1, 4, 1, 0, 0, LanaiOpInfoBase + 160, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OR_R
536 { 376, 3, 1, 4, 1, 0, 0, LanaiOpInfoBase + 157, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OR_I_LO
537 { 375, 3, 1, 4, 1, 0, 0, LanaiOpInfoBase + 157, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OR_I_HI
538 { 374, 4, 1, 4, 1, 0, 1, LanaiOpInfoBase + 160, 6, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OR_F_R
539 { 373, 3, 1, 4, 1, 0, 1, LanaiOpInfoBase + 157, 6, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OR_F_I_LO
540 { 372, 3, 1, 4, 1, 0, 1, LanaiOpInfoBase + 157, 6, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OR_F_I_HI
541 { 371, 0, 0, 4, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NOP
542 { 370, 2, 1, 4, 1, 0, 0, LanaiOpInfoBase + 38, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOVHI
543 { 369, 0, 0, 4, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOG4
544 { 368, 0, 0, 4, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOG3
545 { 367, 0, 0, 4, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOG2
546 { 366, 0, 0, 4, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOG1
547 { 365, 0, 0, 4, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOG0
548 { 364, 2, 1, 4, 1, 0, 0, LanaiOpInfoBase + 155, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LEADZ
549 { 363, 4, 1, 4, 5, 0, 0, LanaiOpInfoBase + 170, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDWz_RR
550 { 362, 4, 1, 4, 5, 0, 0, LanaiOpInfoBase + 170, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDW_RR
551 { 361, 4, 1, 4, 3, 0, 0, LanaiOpInfoBase + 166, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDW_RI
552 { 360, 4, 1, 4, 5, 0, 0, LanaiOpInfoBase + 170, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDHz_RR
553 { 359, 4, 1, 4, 4, 0, 0, LanaiOpInfoBase + 166, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDHz_RI
554 { 358, 4, 1, 4, 5, 0, 0, LanaiOpInfoBase + 170, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDHs_RR
555 { 357, 4, 1, 4, 4, 0, 0, LanaiOpInfoBase + 166, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDHs_RI
556 { 356, 4, 1, 4, 5, 0, 0, LanaiOpInfoBase + 170, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDBz_RR
557 { 355, 4, 1, 4, 4, 0, 0, LanaiOpInfoBase + 166, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDBz_RI
558 { 354, 4, 1, 4, 5, 0, 0, LanaiOpInfoBase + 170, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDBs_RR
559 { 353, 4, 1, 4, 4, 0, 0, LanaiOpInfoBase + 166, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDBs_RI
560 { 352, 2, 1, 4, 3, 0, 0, LanaiOpInfoBase + 38, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDADDR
561 { 351, 1, 0, 4, 1, 0, 0, LanaiOpInfoBase + 32, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JR
562 { 350, 1, 0, 4, 2, 0, 0, LanaiOpInfoBase + 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BT
563 { 349, 2, 0, 4, 0, 1, 0, LanaiOpInfoBase + 164, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BRR
564 { 348, 3, 0, 4, 1, 1, 0, LanaiOpInfoBase + 157, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BRIND_CCA
565 { 347, 2, 0, 4, 1, 1, 0, LanaiOpInfoBase + 38, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BRIND_CC
566 { 346, 2, 0, 4, 2, 1, 0, LanaiOpInfoBase + 13, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BRCC
567 { 345, 4, 1, 4, 1, 0, 0, LanaiOpInfoBase + 160, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND_R
568 { 344, 3, 1, 4, 1, 0, 0, LanaiOpInfoBase + 157, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND_I_LO
569 { 343, 3, 1, 4, 1, 0, 0, LanaiOpInfoBase + 157, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND_I_HI
570 { 342, 4, 1, 4, 1, 0, 1, LanaiOpInfoBase + 160, 6, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND_F_R
571 { 341, 3, 1, 4, 1, 0, 1, LanaiOpInfoBase + 157, 6, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND_F_I_LO
572 { 340, 3, 1, 4, 1, 0, 1, LanaiOpInfoBase + 157, 6, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND_F_I_HI
573 { 339, 4, 1, 4, 1, 0, 0, LanaiOpInfoBase + 160, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_R
574 { 338, 3, 1, 4, 1, 0, 0, LanaiOpInfoBase + 157, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_I_LO
575 { 337, 3, 1, 4, 1, 0, 0, LanaiOpInfoBase + 157, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_I_HI
576 { 336, 4, 1, 4, 1, 0, 1, LanaiOpInfoBase + 160, 6, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_F_R
577 { 335, 3, 1, 4, 1, 0, 1, LanaiOpInfoBase + 157, 6, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_F_I_LO
578 { 334, 3, 1, 4, 1, 0, 1, LanaiOpInfoBase + 157, 6, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_F_I_HI
579 { 333, 4, 1, 4, 1, 1, 0, LanaiOpInfoBase + 160, 6, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC_R
580 { 332, 3, 1, 4, 1, 1, 0, LanaiOpInfoBase + 157, 6, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC_I_LO
581 { 331, 3, 1, 4, 1, 1, 0, LanaiOpInfoBase + 157, 6, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC_I_HI
582 { 330, 4, 1, 4, 1, 1, 1, LanaiOpInfoBase + 160, 4, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC_F_R
583 { 329, 3, 1, 4, 1, 1, 1, LanaiOpInfoBase + 157, 4, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC_F_I_LO
584 { 328, 3, 1, 4, 1, 1, 1, LanaiOpInfoBase + 157, 4, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC_F_I_HI
585 { 327, 1, 0, 4, 0, 1, 1, LanaiOpInfoBase + 32, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CALLR
586 { 326, 1, 0, 4, 0, 1, 1, LanaiOpInfoBase + 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CALL
587 { 325, 2, 1, 4, 0, 1, 1, LanaiOpInfoBase + 155, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADJDYNALLOC
588 { 324, 2, 0, 4, 0, 1, 1, LanaiOpInfoBase + 24, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADJCALLSTACKUP
589 { 323, 2, 0, 4, 0, 1, 1, LanaiOpInfoBase + 24, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADJCALLSTACKDOWN
590 { 322, 4, 1, 0, 0, 0, 0, LanaiOpInfoBase + 151, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UBFX
591 { 321, 4, 1, 0, 0, 0, 0, LanaiOpInfoBase + 151, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SBFX
592 { 320, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_UMIN
593 { 319, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_UMAX
594 { 318, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SMIN
595 { 317, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SMAX
596 { 316, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_XOR
597 { 315, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_OR
598 { 314, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_AND
599 { 313, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_MUL
600 { 312, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_ADD
601 { 311, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMINIMUM
602 { 310, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMAXIMUM
603 { 309, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMIN
604 { 308, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMAX
605 { 307, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMUL
606 { 306, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FADD
607 { 305, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 134, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SEQ_FMUL
608 { 304, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 134, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SEQ_FADD
609 { 303, 1, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UBSANTRAP
610 { 302, 0, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_DEBUGTRAP
611 { 301, 0, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRAP
612 { 300, 3, 0, 0, 0, 0, 0, LanaiOpInfoBase + 61, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BZERO
613 { 299, 4, 0, 0, 0, 0, 0, LanaiOpInfoBase + 147, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMSET
614 { 298, 4, 0, 0, 0, 0, 0, LanaiOpInfoBase + 147, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMMOVE
615 { 297, 3, 0, 0, 0, 0, 0, LanaiOpInfoBase + 134, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMCPY_INLINE
616 { 296, 4, 0, 0, 0, 0, 0, LanaiOpInfoBase + 147, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMCPY
617 { 295, 2, 0, 0, 0, 0, 0, LanaiOpInfoBase + 145, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_WRITE_REGISTER
618 { 294, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 54, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_READ_REGISTER
619 { 293, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 104, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FLDEXP
620 { 292, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FSQRT
621 { 291, 4, 1, 0, 0, 0, 0, LanaiOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FMA
622 { 290, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FREM
623 { 289, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FDIV
624 { 288, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FMUL
625 { 287, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FSUB
626 { 286, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FADD
627 { 285, 1, 0, 0, 0, 0, 0, LanaiOpInfoBase + 53, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STACKRESTORE
628 { 284, 1, 1, 0, 0, 0, 0, LanaiOpInfoBase + 53, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STACKSAVE
629 { 283, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 72, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_DYN_STACKALLOC
630 { 282, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 54, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_JUMP_TABLE
631 { 281, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 54, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BLOCK_ADDR
632 { 280, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ADDRSPACE_CAST
633 { 279, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FNEARBYINT
634 { 278, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FRINT
635 { 277, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FFLOOR
636 { 276, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSQRT
637 { 275, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FTANH
638 { 274, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSINH
639 { 273, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCOSH
640 { 272, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FATAN2
641 { 271, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FATAN
642 { 270, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FASIN
643 { 269, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FACOS
644 { 268, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FTAN
645 { 267, 3, 2, 0, 0, 0, 0, LanaiOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSINCOS
646 { 266, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSIN
647 { 265, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCOS
648 { 264, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCEIL
649 { 263, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BITREVERSE
650 { 262, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BSWAP
651 { 261, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTPOP
652 { 260, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTLS
653 { 259, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTLZ_ZERO_UNDEF
654 { 258, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTLZ
655 { 257, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTTZ_ZERO_UNDEF
656 { 256, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTTZ
657 { 255, 4, 1, 0, 0, 0, 0, LanaiOpInfoBase + 141, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECTOR_COMPRESS
658 { 254, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 54, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STEP_VECTOR
659 { 253, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SPLAT_VECTOR
660 { 252, 4, 1, 0, 0, 0, 0, LanaiOpInfoBase + 137, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SHUFFLE_VECTOR
661 { 251, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 134, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_EXTRACT_VECTOR_ELT
662 { 250, 4, 1, 0, 0, 0, 0, LanaiOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INSERT_VECTOR_ELT
663 { 249, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 61, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_EXTRACT_SUBVECTOR
664 { 248, 4, 1, 0, 0, 0, 0, LanaiOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INSERT_SUBVECTOR
665 { 247, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 54, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VSCALE
666 { 246, 3, 0, 0, 0, 0, 0, LanaiOpInfoBase + 127, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BRJT
667 { 245, 1, 0, 0, 0, 0, 0, LanaiOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BR
668 { 244, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LLROUND
669 { 243, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LROUND
670 { 242, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ABS
671 { 241, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMAX
672 { 240, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMIN
673 { 239, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMAX
674 { 238, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMIN
675 { 237, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 104, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTRMASK
676 { 236, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 104, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTR_ADD
677 { 235, 1, 0, 0, 0, 0, 0, LanaiOpInfoBase + 53, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SET_ROUNDING
678 { 234, 1, 1, 0, 0, 0, 0, LanaiOpInfoBase + 53, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GET_ROUNDING
679 { 233, 0, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_RESET_FPMODE
680 { 232, 1, 0, 0, 0, 0, 0, LanaiOpInfoBase + 53, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SET_FPMODE
681 { 231, 1, 1, 0, 0, 0, 0, LanaiOpInfoBase + 53, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GET_FPMODE
682 { 230, 0, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_RESET_FPENV
683 { 229, 1, 0, 0, 0, 0, 0, LanaiOpInfoBase + 53, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SET_FPENV
684 { 228, 1, 1, 0, 0, 0, 0, LanaiOpInfoBase + 53, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GET_FPENV
685 { 227, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXIMUMNUM
686 { 226, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINIMUMNUM
687 { 225, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXIMUM
688 { 224, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINIMUM
689 { 223, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXNUM_IEEE
690 { 222, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINNUM_IEEE
691 { 221, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXNUM
692 { 220, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINNUM
693 { 219, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCANONICALIZE
694 { 218, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 101, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_IS_FPCLASS
695 { 217, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 104, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCOPYSIGN
696 { 216, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FABS
697 { 215, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOUI_SAT
698 { 214, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOSI_SAT
699 { 213, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UITOFP
700 { 212, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SITOFP
701 { 211, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOUI
702 { 210, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOSI
703 { 209, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTRUNC
704 { 208, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPEXT
705 { 207, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FNEG
706 { 206, 3, 2, 0, 0, 0, 0, LanaiOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FFREXP
707 { 205, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 104, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLDEXP
708 { 204, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLOG10
709 { 203, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLOG2
710 { 202, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLOG
711 { 201, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FEXP10
712 { 200, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FEXP2
713 { 199, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FEXP
714 { 198, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 104, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPOWI
715 { 197, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPOW
716 { 196, 3, 2, 0, 0, 0, 0, LanaiOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMODF
717 { 195, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FREM
718 { 194, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FDIV
719 { 193, 4, 1, 0, 0, 0, 0, LanaiOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAD
720 { 192, 4, 1, 0, 0, 0, 0, LanaiOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMA
721 { 191, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMUL
722 { 190, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSUB
723 { 189, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FADD
724 { 188, 4, 1, 0, 0, 0, 0, LanaiOpInfoBase + 123, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIVFIXSAT
725 { 187, 4, 1, 0, 0, 0, 0, LanaiOpInfoBase + 123, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIVFIXSAT
726 { 186, 4, 1, 0, 0, 0, 0, LanaiOpInfoBase + 123, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIVFIX
727 { 185, 4, 1, 0, 0, 0, 0, LanaiOpInfoBase + 123, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIVFIX
728 { 184, 4, 1, 0, 0, 0, 0, LanaiOpInfoBase + 123, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULFIXSAT
729 { 183, 4, 1, 0, 0, 0, 0, LanaiOpInfoBase + 123, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULFIXSAT
730 { 182, 4, 1, 0, 0, 0, 0, LanaiOpInfoBase + 123, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULFIX
731 { 181, 4, 1, 0, 0, 0, 0, LanaiOpInfoBase + 123, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULFIX
732 { 180, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 104, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSHLSAT
733 { 179, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 104, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USHLSAT
734 { 178, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSUBSAT
735 { 177, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USUBSAT
736 { 176, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SADDSAT
737 { 175, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UADDSAT
738 { 174, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULH
739 { 173, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULH
740 { 172, 4, 2, 0, 0, 0, 0, LanaiOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULO
741 { 171, 4, 2, 0, 0, 0, 0, LanaiOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULO
742 { 170, 5, 2, 0, 0, 0, 0, LanaiOpInfoBase + 118, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSUBE
743 { 169, 4, 2, 0, 0, 0, 0, LanaiOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSUBO
744 { 168, 5, 2, 0, 0, 0, 0, LanaiOpInfoBase + 118, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SADDE
745 { 167, 4, 2, 0, 0, 0, 0, LanaiOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SADDO
746 { 166, 5, 2, 0, 0, 0, 0, LanaiOpInfoBase + 118, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USUBE
747 { 165, 4, 2, 0, 0, 0, 0, LanaiOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USUBO
748 { 164, 5, 2, 0, 0, 0, 0, LanaiOpInfoBase + 118, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UADDE
749 { 163, 4, 2, 0, 0, 0, 0, LanaiOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UADDO
750 { 162, 4, 1, 0, 0, 0, 0, LanaiOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SELECT
751 { 161, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 115, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UCMP
752 { 160, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 115, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SCMP
753 { 159, 4, 1, 0, 0, 0, 0, LanaiOpInfoBase + 111, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCMP
754 { 158, 4, 1, 0, 0, 0, 0, LanaiOpInfoBase + 111, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ICMP
755 { 157, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 104, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ROTL
756 { 156, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 104, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ROTR
757 { 155, 4, 1, 0, 0, 0, 0, LanaiOpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSHR
758 { 154, 4, 1, 0, 0, 0, 0, LanaiOpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSHL
759 { 153, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 104, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASHR
760 { 152, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 104, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LSHR
761 { 151, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 104, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SHL
762 { 150, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ZEXT
763 { 149, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 43, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SEXT_INREG
764 { 148, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SEXT
765 { 147, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 101, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VAARG
766 { 146, 1, 0, 0, 0, 0, 0, LanaiOpInfoBase + 53, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VASTART
767 { 145, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 54, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCONSTANT
768 { 144, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 54, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONSTANT
769 { 143, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC_USAT_U
770 { 142, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC_SSAT_U
771 { 141, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC_SSAT_S
772 { 140, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC
773 { 139, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ANYEXT
774 { 138, 1, 0, 0, 0, 0, 0, LanaiOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
775 { 137, 1, 0, 0, 0, 0, 0, LanaiOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_INTRINSIC_CONVERGENT
776 { 136, 1, 0, 0, 0, 0, 0, LanaiOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_W_SIDE_EFFECTS
777 { 135, 1, 0, 0, 0, 0, 0, LanaiOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC
778 { 134, 0, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INVOKE_REGION_START
779 { 133, 1, 0, 0, 0, 0, 0, LanaiOpInfoBase + 53, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BRINDIRECT
780 { 132, 2, 0, 0, 0, 0, 0, LanaiOpInfoBase + 54, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BRCOND
781 { 131, 4, 0, 0, 0, 0, 0, LanaiOpInfoBase + 97, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PREFETCH
782 { 130, 2, 0, 0, 0, 0, 0, LanaiOpInfoBase + 24, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FENCE
783 { 129, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_USUB_SAT
784 { 128, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_USUB_COND
785 { 127, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UDEC_WRAP
786 { 126, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UINC_WRAP
787 { 125, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMINIMUM
788 { 124, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMAXIMUM
789 { 123, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMIN
790 { 122, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMAX
791 { 121, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FSUB
792 { 120, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FADD
793 { 119, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UMIN
794 { 118, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UMAX
795 { 117, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_MIN
796 { 116, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_MAX
797 { 115, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_XOR
798 { 114, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_OR
799 { 113, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_NAND
800 { 112, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_AND
801 { 111, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_SUB
802 { 110, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_ADD
803 { 109, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_XCHG
804 { 108, 4, 1, 0, 0, 0, 0, LanaiOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMIC_CMPXCHG
805 { 107, 5, 2, 0, 0, 0, 0, LanaiOpInfoBase + 85, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
806 { 106, 5, 1, 0, 0, 0, 0, LanaiOpInfoBase + 80, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_STORE
807 { 105, 2, 0, 0, 0, 0, 0, LanaiOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STORE
808 { 104, 5, 2, 0, 0, 0, 0, LanaiOpInfoBase + 75, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_ZEXTLOAD
809 { 103, 5, 2, 0, 0, 0, 0, LanaiOpInfoBase + 75, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_SEXTLOAD
810 { 102, 5, 2, 0, 0, 0, 0, LanaiOpInfoBase + 75, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_LOAD
811 { 101, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ZEXTLOAD
812 { 100, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SEXTLOAD
813 { 99, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LOAD
814 { 98, 1, 1, 0, 0, 0, 0, LanaiOpInfoBase + 53, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_READSTEADYCOUNTER
815 { 97, 1, 1, 0, 0, 0, 0, LanaiOpInfoBase + 53, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_READCYCLECOUNTER
816 { 96, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_ROUNDEVEN
817 { 95, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_LLRINT
818 { 94, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_LRINT
819 { 93, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_ROUND
820 { 92, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_TRUNC
821 { 91, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 72, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_FPTRUNC_ROUND
822 { 90, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONSTANT_FOLD_BARRIER
823 { 89, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FREEZE
824 { 88, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BITCAST
825 { 87, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTTOPTR
826 { 86, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTRTOINT
827 { 85, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONCAT_VECTORS
828 { 84, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BUILD_VECTOR_TRUNC
829 { 83, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BUILD_VECTOR
830 { 82, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MERGE_VALUES
831 { 81, 4, 1, 0, 0, 0, 0, LanaiOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INSERT
832 { 80, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UNMERGE_VALUES
833 { 79, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 61, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_EXTRACT
834 { 78, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 54, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONSTANT_POOL
835 { 77, 5, 1, 0, 0, 0, 0, LanaiOpInfoBase + 56, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTRAUTH_GLOBAL_VALUE
836 { 76, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 54, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GLOBAL_VALUE
837 { 75, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 54, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FRAME_INDEX
838 { 74, 1, 1, 0, 0, 0, 0, LanaiOpInfoBase + 53, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PHI
839 { 73, 1, 1, 0, 0, 0, 0, LanaiOpInfoBase + 53, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_IMPLICIT_DEF
840 { 72, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SAVGCEIL
841 { 71, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SAVGFLOOR
842 { 70, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UAVGCEIL
843 { 69, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UAVGFLOOR
844 { 68, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ABDU
845 { 67, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ABDS
846 { 66, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_XOR
847 { 65, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_OR
848 { 64, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_AND
849 { 63, 4, 2, 0, 0, 0, 0, LanaiOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIVREM
850 { 62, 4, 2, 0, 0, 0, 0, LanaiOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIVREM
851 { 61, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UREM
852 { 60, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SREM
853 { 59, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIV
854 { 58, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIV
855 { 57, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MUL
856 { 56, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SUB
857 { 55, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ADD
858 { 54, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 43, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASSERT_ALIGN
859 { 53, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 43, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASSERT_ZEXT
860 { 52, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 43, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASSERT_SEXT
861 { 51, 1, 0, 0, 0, 0, 0, LanaiOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_GLUE
862 { 50, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 13, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_LOOP
863 { 49, 1, 1, 0, 0, 0, 0, LanaiOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_ANCHOR
864 { 48, 1, 1, 0, 0, 0, 0, LanaiOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_ENTRY
865 { 47, 1, 0, 0, 0, 0, 0, LanaiOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RELOC_NONE
866 { 46, 1, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JUMP_TABLE_DEBUG_INFO
867 { 45, 0, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMBARRIER
868 { 44, 0, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FAKE_USE
869 { 43, 0, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ICALL_BRANCH_FUNNEL
870 { 42, 3, 0, 0, 0, 0, 0, LanaiOpInfoBase + 40, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_14662
871 { 41, 2, 0, 0, 0, 0, 0, LanaiOpInfoBase + 38, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_14661
872 { 40, 0, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_TAIL_CALL
873 { 39, 0, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_FUNCTION_EXIT
874 { 38, 0, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_RET
875 { 37, 0, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_FUNCTION_ENTER
876 { 36, 0, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_OP
877 { 35, 1, 1, 0, 0, 0, 0, LanaiOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FAULTING_OP
878 { 34, 2, 0, 0, 0, 0, 0, LanaiOpInfoBase + 36, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_ESCAPE
879 { 33, 0, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STATEPOINT
880 { 32, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 33, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_14660
881 { 31, 1, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PREALLOCATED_SETUP
882 { 30, 1, 1, 0, 0, 0, 0, LanaiOpInfoBase + 32, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_14301
883 { 29, 6, 1, 0, 0, 0, 0, LanaiOpInfoBase + 26, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHPOINT
884 { 28, 0, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FENTRY_CALL
885 { 27, 2, 0, 0, 0, 0, 0, LanaiOpInfoBase + 24, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STACKMAP
886 { 26, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 22, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARITH_FENCE
887 { 25, 4, 0, 0, 0, 0, 0, LanaiOpInfoBase + 18, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PSEUDO_PROBE
888 { 24, 1, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LIFETIME_END
889 { 23, 1, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LIFETIME_START
890 { 22, 0, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BUNDLE
891 { 21, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 15, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_LANEMASK
892 { 20, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 13, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY
893 { 19, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 13, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REG_SEQUENCE
894 { 18, 1, 0, 0, 0, 0, 0, LanaiOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_LABEL
895 { 17, 0, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_PHI
896 { 16, 0, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_INSTR_REF
897 { 15, 0, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_VALUE_LIST
898 { 14, 0, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_VALUE
899 { 13, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_TO_REGCLASS
900 { 12, 4, 1, 0, 0, 0, 0, LanaiOpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBREG_TO_REG
901 { 11, 1, 1, 0, 0, 0, 0, LanaiOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INIT_UNDEF
902 { 10, 1, 1, 0, 0, 0, 0, LanaiOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // IMPLICIT_DEF
903 { 9, 4, 1, 0, 0, 0, 0, LanaiOpInfoBase + 5, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INSERT_SUBREG
904 { 8, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTRACT_SUBREG
905 { 7, 0, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // KILL
906 { 6, 1, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ANNOTATION_LABEL
907 { 5, 1, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GC_LABEL
908 { 4, 1, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EH_LABEL
909 { 3, 1, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CFI_INSTRUCTION
910 { 2, 0, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INLINEASM_BR
911 { 1, 0, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INLINEASM
912 { 0, 1, 1, 0, 0, 0, 0, LanaiOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PHI
913 }, {
914 /* 0 */
915 /* 0 */ Lanai::SP, Lanai::SP,
916 /* 2 */ Lanai::SP, Lanai::RCA,
917 /* 4 */ Lanai::SR, Lanai::SR,
918 /* 6 */ Lanai::SR,
919 /* 7 */ Lanai::RCA,
920 }, {
921 0
922 }, {
923 /* 0 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
924 /* 1 */
925 /* 1 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
926 /* 2 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
927 /* 5 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
928 /* 9 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
929 /* 13 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
930 /* 15 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
931 /* 18 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
932 /* 22 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) },
933 /* 24 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
934 /* 26 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
935 /* 32 */ { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
936 /* 33 */ { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
937 /* 36 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
938 /* 38 */ { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
939 /* 40 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
940 /* 43 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
941 /* 46 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
942 /* 49 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
943 /* 53 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
944 /* 54 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
945 /* 56 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
946 /* 61 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
947 /* 64 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
948 /* 66 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
949 /* 70 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
950 /* 72 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
951 /* 75 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
952 /* 80 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
953 /* 85 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
954 /* 90 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
955 /* 94 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
956 /* 97 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
957 /* 101 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
958 /* 104 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
959 /* 107 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
960 /* 111 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
961 /* 115 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
962 /* 118 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
963 /* 123 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
964 /* 127 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
965 /* 130 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
966 /* 134 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
967 /* 137 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
968 /* 141 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
969 /* 145 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
970 /* 147 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
971 /* 151 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
972 /* 155 */ { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
973 /* 157 */ { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
974 /* 160 */ { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 },
975 /* 164 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
976 /* 166 */ { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
977 /* 170 */ { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
978 /* 174 */ { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
979 }
980};
981
982
983#ifdef __GNUC__
984#pragma GCC diagnostic push
985#pragma GCC diagnostic ignored "-Woverlength-strings"
986#endif
987extern const char LanaiInstrNameData[] = {
988 /* 0 */ "G_FLOG10\000"
989 /* 9 */ "G_FEXP10\000"
990 /* 18 */ "LOG0\000"
991 /* 23 */ "LOG1\000"
992 /* 28 */ "G_FLOG2\000"
993 /* 36 */ "G_FATAN2\000"
994 /* 45 */ "G_FEXP2\000"
995 /* 53 */ "LOG3\000"
996 /* 58 */ "LOG4\000"
997 /* 63 */ "BRIND_CCA\000"
998 /* 73 */ "G_FMA\000"
999 /* 79 */ "G_STRICT_FMA\000"
1000 /* 92 */ "G_FSUB\000"
1001 /* 99 */ "G_STRICT_FSUB\000"
1002 /* 113 */ "G_ATOMICRMW_FSUB\000"
1003 /* 130 */ "G_SUB\000"
1004 /* 136 */ "G_ATOMICRMW_SUB\000"
1005 /* 152 */ "BRCC\000"
1006 /* 157 */ "SCC\000"
1007 /* 161 */ "BRIND_CC\000"
1008 /* 170 */ "G_INTRINSIC\000"
1009 /* 182 */ "G_FPTRUNC\000"
1010 /* 192 */ "G_INTRINSIC_TRUNC\000"
1011 /* 210 */ "G_TRUNC\000"
1012 /* 218 */ "G_BUILD_VECTOR_TRUNC\000"
1013 /* 239 */ "G_DYN_STACKALLOC\000"
1014 /* 256 */ "ADJDYNALLOC\000"
1015 /* 268 */ "POPC\000"
1016 /* 273 */ "G_FMAD\000"
1017 /* 280 */ "G_INDEXED_SEXTLOAD\000"
1018 /* 299 */ "G_SEXTLOAD\000"
1019 /* 310 */ "G_INDEXED_ZEXTLOAD\000"
1020 /* 329 */ "G_ZEXTLOAD\000"
1021 /* 340 */ "G_INDEXED_LOAD\000"
1022 /* 355 */ "G_LOAD\000"
1023 /* 362 */ "G_VECREDUCE_FADD\000"
1024 /* 379 */ "G_FADD\000"
1025 /* 386 */ "G_VECREDUCE_SEQ_FADD\000"
1026 /* 407 */ "G_STRICT_FADD\000"
1027 /* 421 */ "G_ATOMICRMW_FADD\000"
1028 /* 438 */ "G_VECREDUCE_ADD\000"
1029 /* 454 */ "G_ADD\000"
1030 /* 460 */ "G_PTR_ADD\000"
1031 /* 470 */ "G_ATOMICRMW_ADD\000"
1032 /* 486 */ "G_ATOMICRMW_NAND\000"
1033 /* 503 */ "G_VECREDUCE_AND\000"
1034 /* 519 */ "G_AND\000"
1035 /* 525 */ "G_ATOMICRMW_AND\000"
1036 /* 541 */ "LIFETIME_END\000"
1037 /* 554 */ "G_BRCOND\000"
1038 /* 563 */ "G_ATOMICRMW_USUB_COND\000"
1039 /* 585 */ "G_LLROUND\000"
1040 /* 595 */ "G_LROUND\000"
1041 /* 604 */ "G_INTRINSIC_ROUND\000"
1042 /* 622 */ "G_INTRINSIC_FPTRUNC_ROUND\000"
1043 /* 648 */ "LOAD_STACK_GUARD\000"
1044 /* 665 */ "PSEUDO_PROBE\000"
1045 /* 678 */ "G_SSUBE\000"
1046 /* 686 */ "G_USUBE\000"
1047 /* 694 */ "G_FENCE\000"
1048 /* 702 */ "ARITH_FENCE\000"
1049 /* 714 */ "REG_SEQUENCE\000"
1050 /* 727 */ "G_SADDE\000"
1051 /* 735 */ "G_UADDE\000"
1052 /* 743 */ "G_GET_FPMODE\000"
1053 /* 756 */ "G_RESET_FPMODE\000"
1054 /* 771 */ "G_SET_FPMODE\000"
1055 /* 784 */ "G_FMINNUM_IEEE\000"
1056 /* 799 */ "G_FMAXNUM_IEEE\000"
1057 /* 814 */ "G_VSCALE\000"
1058 /* 823 */ "G_JUMP_TABLE\000"
1059 /* 836 */ "BUNDLE\000"
1060 /* 843 */ "G_MEMCPY_INLINE\000"
1061 /* 859 */ "RELOC_NONE\000"
1062 /* 870 */ "LOCAL_ESCAPE\000"
1063 /* 883 */ "G_STACKRESTORE\000"
1064 /* 898 */ "G_INDEXED_STORE\000"
1065 /* 914 */ "G_STORE\000"
1066 /* 922 */ "G_BITREVERSE\000"
1067 /* 935 */ "FAKE_USE\000"
1068 /* 944 */ "DBG_VALUE\000"
1069 /* 954 */ "G_GLOBAL_VALUE\000"
1070 /* 969 */ "G_PTRAUTH_GLOBAL_VALUE\000"
1071 /* 992 */ "CONVERGENCECTRL_GLUE\000"
1072 /* 1013 */ "G_STACKSAVE\000"
1073 /* 1025 */ "G_MEMMOVE\000"
1074 /* 1035 */ "G_FREEZE\000"
1075 /* 1044 */ "G_FCANONICALIZE\000"
1076 /* 1060 */ "G_FMODF\000"
1077 /* 1068 */ "G_CTLZ_ZERO_UNDEF\000"
1078 /* 1086 */ "G_CTTZ_ZERO_UNDEF\000"
1079 /* 1104 */ "INIT_UNDEF\000"
1080 /* 1115 */ "G_IMPLICIT_DEF\000"
1081 /* 1130 */ "DBG_INSTR_REF\000"
1082 /* 1144 */ "G_FNEG\000"
1083 /* 1151 */ "EXTRACT_SUBREG\000"
1084 /* 1166 */ "INSERT_SUBREG\000"
1085 /* 1180 */ "G_SEXT_INREG\000"
1086 /* 1193 */ "SUBREG_TO_REG\000"
1087 /* 1207 */ "G_ATOMIC_CMPXCHG\000"
1088 /* 1224 */ "G_ATOMICRMW_XCHG\000"
1089 /* 1241 */ "G_GET_ROUNDING\000"
1090 /* 1256 */ "G_SET_ROUNDING\000"
1091 /* 1271 */ "G_FLOG\000"
1092 /* 1278 */ "G_VAARG\000"
1093 /* 1286 */ "PREALLOCATED_ARG\000"
1094 /* 1303 */ "G_PREFETCH\000"
1095 /* 1314 */ "G_SMULH\000"
1096 /* 1322 */ "G_UMULH\000"
1097 /* 1330 */ "G_FTANH\000"
1098 /* 1338 */ "G_FSINH\000"
1099 /* 1346 */ "G_FCOSH\000"
1100 /* 1354 */ "DBG_PHI\000"
1101 /* 1362 */ "MOVHI\000"
1102 /* 1368 */ "SFSUB_F_RI_HI\000"
1103 /* 1382 */ "SUBB_I_HI\000"
1104 /* 1392 */ "SUB_I_HI\000"
1105 /* 1401 */ "ADDC_I_HI\000"
1106 /* 1411 */ "ADD_I_HI\000"
1107 /* 1420 */ "AND_I_HI\000"
1108 /* 1429 */ "SUBB_F_I_HI\000"
1109 /* 1441 */ "SUB_F_I_HI\000"
1110 /* 1452 */ "ADDC_F_I_HI\000"
1111 /* 1464 */ "ADD_F_I_HI\000"
1112 /* 1475 */ "AND_F_I_HI\000"
1113 /* 1486 */ "XOR_F_I_HI\000"
1114 /* 1497 */ "XOR_I_HI\000"
1115 /* 1506 */ "SLI\000"
1116 /* 1510 */ "STB_RI\000"
1117 /* 1517 */ "STH_RI\000"
1118 /* 1524 */ "LDW_RI\000"
1119 /* 1531 */ "SW_RI\000"
1120 /* 1537 */ "LDBs_RI\000"
1121 /* 1545 */ "LDHs_RI\000"
1122 /* 1553 */ "LDBz_RI\000"
1123 /* 1561 */ "LDHz_RI\000"
1124 /* 1569 */ "G_FPTOSI\000"
1125 /* 1578 */ "G_FPTOUI\000"
1126 /* 1587 */ "G_FPOWI\000"
1127 /* 1595 */ "SA_I\000"
1128 /* 1600 */ "SA_F_I\000"
1129 /* 1607 */ "SL_F_I\000"
1130 /* 1614 */ "SL_I\000"
1131 /* 1619 */ "COPY_LANEMASK\000"
1132 /* 1633 */ "G_PTRMASK\000"
1133 /* 1643 */ "GC_LABEL\000"
1134 /* 1652 */ "DBG_LABEL\000"
1135 /* 1662 */ "EH_LABEL\000"
1136 /* 1671 */ "ANNOTATION_LABEL\000"
1137 /* 1688 */ "ICALL_BRANCH_FUNNEL\000"
1138 /* 1708 */ "G_FSHL\000"
1139 /* 1715 */ "G_SHL\000"
1140 /* 1721 */ "G_FCEIL\000"
1141 /* 1729 */ "G_SAVGCEIL\000"
1142 /* 1740 */ "G_UAVGCEIL\000"
1143 /* 1751 */ "PATCHABLE_TAIL_CALL\000"
1144 /* 1771 */ "PATCHABLE_TYPED_EVENT_CALL\000"
1145 /* 1798 */ "PATCHABLE_EVENT_CALL\000"
1146 /* 1819 */ "FENTRY_CALL\000"
1147 /* 1831 */ "KILL\000"
1148 /* 1836 */ "G_CONSTANT_POOL\000"
1149 /* 1852 */ "G_ROTL\000"
1150 /* 1859 */ "G_VECREDUCE_FMUL\000"
1151 /* 1876 */ "G_FMUL\000"
1152 /* 1883 */ "G_VECREDUCE_SEQ_FMUL\000"
1153 /* 1904 */ "G_STRICT_FMUL\000"
1154 /* 1918 */ "G_VECREDUCE_MUL\000"
1155 /* 1934 */ "G_MUL\000"
1156 /* 1940 */ "G_FREM\000"
1157 /* 1947 */ "G_STRICT_FREM\000"
1158 /* 1961 */ "G_SREM\000"
1159 /* 1968 */ "G_UREM\000"
1160 /* 1975 */ "G_SDIVREM\000"
1161 /* 1985 */ "G_UDIVREM\000"
1162 /* 1995 */ "INLINEASM\000"
1163 /* 2005 */ "G_VECREDUCE_FMINIMUM\000"
1164 /* 2026 */ "G_FMINIMUM\000"
1165 /* 2037 */ "G_ATOMICRMW_FMINIMUM\000"
1166 /* 2058 */ "G_VECREDUCE_FMAXIMUM\000"
1167 /* 2079 */ "G_FMAXIMUM\000"
1168 /* 2090 */ "G_ATOMICRMW_FMAXIMUM\000"
1169 /* 2111 */ "G_FMINIMUMNUM\000"
1170 /* 2125 */ "G_FMAXIMUMNUM\000"
1171 /* 2139 */ "G_FMINNUM\000"
1172 /* 2149 */ "G_FMAXNUM\000"
1173 /* 2159 */ "G_FATAN\000"
1174 /* 2167 */ "G_FTAN\000"
1175 /* 2174 */ "G_INTRINSIC_ROUNDEVEN\000"
1176 /* 2196 */ "G_ASSERT_ALIGN\000"
1177 /* 2211 */ "G_FCOPYSIGN\000"
1178 /* 2223 */ "G_VECREDUCE_FMIN\000"
1179 /* 2240 */ "G_ATOMICRMW_FMIN\000"
1180 /* 2257 */ "G_VECREDUCE_SMIN\000"
1181 /* 2274 */ "G_SMIN\000"
1182 /* 2281 */ "G_VECREDUCE_UMIN\000"
1183 /* 2298 */ "G_UMIN\000"
1184 /* 2305 */ "G_ATOMICRMW_UMIN\000"
1185 /* 2322 */ "G_ATOMICRMW_MIN\000"
1186 /* 2338 */ "G_FASIN\000"
1187 /* 2346 */ "G_FSIN\000"
1188 /* 2353 */ "CFI_INSTRUCTION\000"
1189 /* 2369 */ "ADJCALLSTACKDOWN\000"
1190 /* 2386 */ "G_SSUBO\000"
1191 /* 2394 */ "G_USUBO\000"
1192 /* 2402 */ "G_SADDO\000"
1193 /* 2410 */ "G_UADDO\000"
1194 /* 2418 */ "JUMP_TABLE_DEBUG_INFO\000"
1195 /* 2440 */ "G_SMULO\000"
1196 /* 2448 */ "G_UMULO\000"
1197 /* 2456 */ "SFSUB_F_RI_LO\000"
1198 /* 2470 */ "SUBB_I_LO\000"
1199 /* 2480 */ "SUB_I_LO\000"
1200 /* 2489 */ "ADDC_I_LO\000"
1201 /* 2499 */ "ADD_I_LO\000"
1202 /* 2508 */ "AND_I_LO\000"
1203 /* 2517 */ "SUBB_F_I_LO\000"
1204 /* 2529 */ "SUB_F_I_LO\000"
1205 /* 2540 */ "ADDC_F_I_LO\000"
1206 /* 2552 */ "ADD_F_I_LO\000"
1207 /* 2563 */ "AND_F_I_LO\000"
1208 /* 2574 */ "XOR_F_I_LO\000"
1209 /* 2585 */ "XOR_I_LO\000"
1210 /* 2594 */ "G_BZERO\000"
1211 /* 2602 */ "STACKMAP\000"
1212 /* 2611 */ "G_DEBUGTRAP\000"
1213 /* 2623 */ "G_UBSANTRAP\000"
1214 /* 2635 */ "G_TRAP\000"
1215 /* 2642 */ "G_ATOMICRMW_UDEC_WRAP\000"
1216 /* 2664 */ "G_ATOMICRMW_UINC_WRAP\000"
1217 /* 2686 */ "G_BSWAP\000"
1218 /* 2694 */ "G_SITOFP\000"
1219 /* 2703 */ "G_UITOFP\000"
1220 /* 2712 */ "G_FCMP\000"
1221 /* 2719 */ "G_ICMP\000"
1222 /* 2726 */ "G_SCMP\000"
1223 /* 2733 */ "G_UCMP\000"
1224 /* 2740 */ "NOP\000"
1225 /* 2744 */ "CONVERGENCECTRL_LOOP\000"
1226 /* 2765 */ "G_CTPOP\000"
1227 /* 2773 */ "PATCHABLE_OP\000"
1228 /* 2786 */ "FAULTING_OP\000"
1229 /* 2798 */ "ADJCALLSTACKUP\000"
1230 /* 2813 */ "PREALLOCATED_SETUP\000"
1231 /* 2832 */ "G_FLDEXP\000"
1232 /* 2841 */ "G_STRICT_FLDEXP\000"
1233 /* 2857 */ "G_FEXP\000"
1234 /* 2864 */ "G_FFREXP\000"
1235 /* 2873 */ "G_BR\000"
1236 /* 2878 */ "INLINEASM_BR\000"
1237 /* 2891 */ "LDADDR\000"
1238 /* 2898 */ "STADDR\000"
1239 /* 2905 */ "G_BLOCK_ADDR\000"
1240 /* 2918 */ "MEMBARRIER\000"
1241 /* 2929 */ "G_CONSTANT_FOLD_BARRIER\000"
1242 /* 2953 */ "PATCHABLE_FUNCTION_ENTER\000"
1243 /* 2978 */ "G_READCYCLECOUNTER\000"
1244 /* 2997 */ "G_READSTEADYCOUNTER\000"
1245 /* 3017 */ "G_READ_REGISTER\000"
1246 /* 3033 */ "G_WRITE_REGISTER\000"
1247 /* 3050 */ "G_ASHR\000"
1248 /* 3057 */ "G_FSHR\000"
1249 /* 3064 */ "G_LSHR\000"
1250 /* 3071 */ "JR\000"
1251 /* 3074 */ "CALLR\000"
1252 /* 3080 */ "CONVERGENCECTRL_ANCHOR\000"
1253 /* 3103 */ "G_FFLOOR\000"
1254 /* 3112 */ "G_SAVGFLOOR\000"
1255 /* 3124 */ "G_UAVGFLOOR\000"
1256 /* 3136 */ "G_EXTRACT_SUBVECTOR\000"
1257 /* 3156 */ "G_INSERT_SUBVECTOR\000"
1258 /* 3175 */ "G_BUILD_VECTOR\000"
1259 /* 3190 */ "G_SHUFFLE_VECTOR\000"
1260 /* 3207 */ "G_STEP_VECTOR\000"
1261 /* 3221 */ "G_SPLAT_VECTOR\000"
1262 /* 3236 */ "G_VECREDUCE_XOR\000"
1263 /* 3252 */ "G_XOR\000"
1264 /* 3258 */ "G_ATOMICRMW_XOR\000"
1265 /* 3274 */ "G_VECREDUCE_OR\000"
1266 /* 3289 */ "G_OR\000"
1267 /* 3294 */ "G_ATOMICRMW_OR\000"
1268 /* 3309 */ "BRR\000"
1269 /* 3313 */ "STB_RR\000"
1270 /* 3320 */ "SFSUB_F_RR\000"
1271 /* 3331 */ "STH_RR\000"
1272 /* 3338 */ "LDW_RR\000"
1273 /* 3345 */ "SW_RR\000"
1274 /* 3351 */ "LDBs_RR\000"
1275 /* 3359 */ "LDHs_RR\000"
1276 /* 3367 */ "LDBz_RR\000"
1277 /* 3375 */ "LDHz_RR\000"
1278 /* 3383 */ "LDWz_RR\000"
1279 /* 3391 */ "G_ROTR\000"
1280 /* 3398 */ "G_INTTOPTR\000"
1281 /* 3409 */ "SRA_R\000"
1282 /* 3415 */ "SUBB_R\000"
1283 /* 3422 */ "SUB_R\000"
1284 /* 3428 */ "ADDC_R\000"
1285 /* 3435 */ "ADD_R\000"
1286 /* 3441 */ "AND_R\000"
1287 /* 3447 */ "SRA_F_R\000"
1288 /* 3455 */ "SUBB_F_R\000"
1289 /* 3464 */ "SUB_F_R\000"
1290 /* 3472 */ "ADDC_F_R\000"
1291 /* 3481 */ "ADD_F_R\000"
1292 /* 3489 */ "AND_F_R\000"
1293 /* 3497 */ "SHL_F_R\000"
1294 /* 3505 */ "SRL_F_R\000"
1295 /* 3513 */ "XOR_F_R\000"
1296 /* 3521 */ "SHL_R\000"
1297 /* 3527 */ "SRL_R\000"
1298 /* 3533 */ "XOR_R\000"
1299 /* 3539 */ "G_FABS\000"
1300 /* 3546 */ "G_ABS\000"
1301 /* 3552 */ "G_ABDS\000"
1302 /* 3559 */ "G_UNMERGE_VALUES\000"
1303 /* 3576 */ "G_MERGE_VALUES\000"
1304 /* 3591 */ "G_CTLS\000"
1305 /* 3598 */ "G_FACOS\000"
1306 /* 3606 */ "G_FCOS\000"
1307 /* 3613 */ "G_FSINCOS\000"
1308 /* 3623 */ "G_CONCAT_VECTORS\000"
1309 /* 3640 */ "COPY_TO_REGCLASS\000"
1310 /* 3657 */ "G_IS_FPCLASS\000"
1311 /* 3670 */ "G_ATOMIC_CMPXCHG_WITH_SUCCESS\000"
1312 /* 3700 */ "G_VECTOR_COMPRESS\000"
1313 /* 3718 */ "G_INTRINSIC_W_SIDE_EFFECTS\000"
1314 /* 3745 */ "G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS\000"
1315 /* 3783 */ "G_TRUNC_SSAT_S\000"
1316 /* 3798 */ "G_SSUBSAT\000"
1317 /* 3808 */ "G_USUBSAT\000"
1318 /* 3818 */ "G_SADDSAT\000"
1319 /* 3828 */ "G_UADDSAT\000"
1320 /* 3838 */ "G_SSHLSAT\000"
1321 /* 3848 */ "G_USHLSAT\000"
1322 /* 3858 */ "G_SMULFIXSAT\000"
1323 /* 3871 */ "G_UMULFIXSAT\000"
1324 /* 3884 */ "G_SDIVFIXSAT\000"
1325 /* 3897 */ "G_UDIVFIXSAT\000"
1326 /* 3910 */ "G_ATOMICRMW_USUB_SAT\000"
1327 /* 3931 */ "G_FPTOSI_SAT\000"
1328 /* 3944 */ "G_FPTOUI_SAT\000"
1329 /* 3957 */ "BT\000"
1330 /* 3960 */ "G_EXTRACT\000"
1331 /* 3970 */ "G_SELECT\000"
1332 /* 3979 */ "G_BRINDIRECT\000"
1333 /* 3992 */ "PATCHABLE_RET\000"
1334 /* 4006 */ "G_MEMSET\000"
1335 /* 4015 */ "PATCHABLE_FUNCTION_EXIT\000"
1336 /* 4039 */ "G_BRJT\000"
1337 /* 4046 */ "G_EXTRACT_VECTOR_ELT\000"
1338 /* 4067 */ "G_INSERT_VECTOR_ELT\000"
1339 /* 4087 */ "G_FCONSTANT\000"
1340 /* 4099 */ "G_CONSTANT\000"
1341 /* 4110 */ "G_INTRINSIC_CONVERGENT\000"
1342 /* 4133 */ "STATEPOINT\000"
1343 /* 4144 */ "PATCHPOINT\000"
1344 /* 4155 */ "G_PTRTOINT\000"
1345 /* 4166 */ "G_FRINT\000"
1346 /* 4174 */ "G_INTRINSIC_LLRINT\000"
1347 /* 4193 */ "G_INTRINSIC_LRINT\000"
1348 /* 4211 */ "G_FNEARBYINT\000"
1349 /* 4224 */ "G_VASTART\000"
1350 /* 4234 */ "LIFETIME_START\000"
1351 /* 4249 */ "G_INVOKE_REGION_START\000"
1352 /* 4271 */ "G_INSERT\000"
1353 /* 4280 */ "G_FSQRT\000"
1354 /* 4288 */ "G_STRICT_FSQRT\000"
1355 /* 4303 */ "G_BITCAST\000"
1356 /* 4313 */ "G_ADDRSPACE_CAST\000"
1357 /* 4330 */ "DBG_VALUE_LIST\000"
1358 /* 4345 */ "G_FPEXT\000"
1359 /* 4353 */ "G_SEXT\000"
1360 /* 4360 */ "G_ASSERT_SEXT\000"
1361 /* 4374 */ "G_ANYEXT\000"
1362 /* 4383 */ "G_ZEXT\000"
1363 /* 4390 */ "G_ASSERT_ZEXT\000"
1364 /* 4404 */ "G_ABDU\000"
1365 /* 4411 */ "G_TRUNC_SSAT_U\000"
1366 /* 4426 */ "G_TRUNC_USAT_U\000"
1367 /* 4441 */ "G_FDIV\000"
1368 /* 4448 */ "G_STRICT_FDIV\000"
1369 /* 4462 */ "G_SDIV\000"
1370 /* 4469 */ "G_UDIV\000"
1371 /* 4476 */ "G_GET_FPENV\000"
1372 /* 4488 */ "G_RESET_FPENV\000"
1373 /* 4502 */ "G_SET_FPENV\000"
1374 /* 4514 */ "G_FPOW\000"
1375 /* 4521 */ "G_VECREDUCE_FMAX\000"
1376 /* 4538 */ "G_ATOMICRMW_FMAX\000"
1377 /* 4555 */ "G_VECREDUCE_SMAX\000"
1378 /* 4572 */ "G_SMAX\000"
1379 /* 4579 */ "G_VECREDUCE_UMAX\000"
1380 /* 4596 */ "G_UMAX\000"
1381 /* 4603 */ "G_ATOMICRMW_UMAX\000"
1382 /* 4620 */ "G_ATOMICRMW_MAX\000"
1383 /* 4636 */ "G_FRAME_INDEX\000"
1384 /* 4650 */ "G_SBFX\000"
1385 /* 4657 */ "G_UBFX\000"
1386 /* 4664 */ "G_SMULFIX\000"
1387 /* 4674 */ "G_UMULFIX\000"
1388 /* 4684 */ "G_SDIVFIX\000"
1389 /* 4694 */ "G_UDIVFIX\000"
1390 /* 4704 */ "G_MEMCPY\000"
1391 /* 4713 */ "COPY\000"
1392 /* 4718 */ "CONVERGENCECTRL_ENTRY\000"
1393 /* 4740 */ "LEADZ\000"
1394 /* 4746 */ "TRAILZ\000"
1395 /* 4753 */ "G_CTLZ\000"
1396 /* 4760 */ "G_CTTZ\000"
1397};
1398#ifdef __GNUC__
1399#pragma GCC diagnostic pop
1400#endif
1401
1402extern const unsigned LanaiInstrNameIndices[] = {
1403 1358U, 1995U, 2878U, 2353U, 1662U, 1643U, 1671U, 1831U,
1404 1151U, 1166U, 1117U, 1104U, 1193U, 3640U, 944U, 4330U,
1405 1130U, 1354U, 1652U, 714U, 4713U, 1619U, 836U, 4234U,
1406 541U, 665U, 702U, 2602U, 1819U, 4144U, 648U, 2813U,
1407 1286U, 4133U, 870U, 2786U, 2773U, 2953U, 3992U, 4015U,
1408 1751U, 1798U, 1771U, 1688U, 935U, 2918U, 2418U, 859U,
1409 4718U, 3080U, 2744U, 992U, 4360U, 4390U, 2196U, 454U,
1410 130U, 1934U, 4462U, 4469U, 1961U, 1968U, 1975U, 1985U,
1411 519U, 3289U, 3252U, 3552U, 4404U, 3124U, 1740U, 3112U,
1412 1729U, 1115U, 1356U, 4636U, 954U, 969U, 1836U, 3960U,
1413 3559U, 4271U, 3576U, 3175U, 218U, 3623U, 4155U, 3398U,
1414 4303U, 1035U, 2929U, 622U, 192U, 604U, 4193U, 4174U,
1415 2174U, 2978U, 2997U, 355U, 299U, 329U, 340U, 280U,
1416 310U, 914U, 898U, 3670U, 1207U, 1224U, 470U, 136U,
1417 525U, 486U, 3294U, 3258U, 4620U, 2322U, 4603U, 2305U,
1418 421U, 113U, 4538U, 2240U, 2090U, 2037U, 2664U, 2642U,
1419 563U, 3910U, 694U, 1303U, 554U, 3979U, 4249U, 170U,
1420 3718U, 4110U, 3745U, 4374U, 210U, 3783U, 4411U, 4426U,
1421 4099U, 4087U, 4224U, 1278U, 4353U, 1180U, 4383U, 1715U,
1422 3064U, 3050U, 1708U, 3057U, 3391U, 1852U, 2719U, 2712U,
1423 2726U, 2733U, 3970U, 2410U, 735U, 2394U, 686U, 2402U,
1424 727U, 2386U, 678U, 2448U, 2440U, 1322U, 1314U, 3828U,
1425 3818U, 3808U, 3798U, 3848U, 3838U, 4664U, 4674U, 3858U,
1426 3871U, 4684U, 4694U, 3884U, 3897U, 379U, 92U, 1876U,
1427 73U, 273U, 4441U, 1940U, 1060U, 4514U, 1587U, 2857U,
1428 45U, 9U, 1271U, 28U, 0U, 2832U, 2864U, 1144U,
1429 4345U, 182U, 1569U, 1578U, 2694U, 2703U, 3931U, 3944U,
1430 3539U, 2211U, 3657U, 1044U, 2139U, 2149U, 784U, 799U,
1431 2026U, 2079U, 2111U, 2125U, 4476U, 4502U, 4488U, 743U,
1432 771U, 756U, 1241U, 1256U, 460U, 1633U, 2274U, 4572U,
1433 2298U, 4596U, 3546U, 595U, 585U, 2873U, 4039U, 814U,
1434 3156U, 3136U, 4067U, 4046U, 3190U, 3221U, 3207U, 3700U,
1435 4760U, 1086U, 4753U, 1068U, 3591U, 2765U, 2686U, 922U,
1436 1721U, 3606U, 2346U, 3613U, 2167U, 3598U, 2338U, 2159U,
1437 36U, 1346U, 1338U, 1330U, 4280U, 3103U, 4166U, 4211U,
1438 4313U, 2905U, 823U, 239U, 1013U, 883U, 407U, 99U,
1439 1904U, 4448U, 1947U, 79U, 4288U, 2841U, 3017U, 3033U,
1440 4704U, 843U, 1025U, 4006U, 2594U, 2635U, 2611U, 2623U,
1441 386U, 1883U, 362U, 1859U, 4521U, 2223U, 2058U, 2005U,
1442 438U, 1918U, 503U, 3274U, 3236U, 4555U, 2257U, 4579U,
1443 2281U, 4650U, 4657U, 2369U, 2798U, 256U, 1766U, 3074U,
1444 1452U, 2540U, 3472U, 1401U, 2489U, 3428U, 1464U, 2552U,
1445 3481U, 1411U, 2499U, 3435U, 1475U, 2563U, 3489U, 1420U,
1446 2508U, 3441U, 152U, 161U, 63U, 3309U, 3957U, 3071U,
1447 2891U, 1537U, 3351U, 1553U, 3367U, 1545U, 3359U, 1561U,
1448 3375U, 1524U, 3338U, 3383U, 4740U, 18U, 23U, 31U,
1449 53U, 58U, 1362U, 2740U, 1487U, 2575U, 3514U, 1498U,
1450 2586U, 3534U, 268U, 4002U, 1600U, 1595U, 157U, 3972U,
1451 1368U, 2456U, 3320U, 3497U, 3521U, 1506U, 1607U, 1614U,
1452 3447U, 3409U, 3505U, 3527U, 2898U, 1510U, 3313U, 1517U,
1453 3331U, 1429U, 2517U, 3455U, 1382U, 2470U, 3415U, 1441U,
1454 2529U, 3464U, 1392U, 2480U, 3422U, 1531U, 3345U, 4746U,
1455 1486U, 2574U, 3513U, 1497U, 2585U, 3533U,
1456};
1457
1458static inline void InitLanaiMCInstrInfo(MCInstrInfo *II) {
1459 II->InitMCInstrInfo(LanaiDescs.Insts, LanaiInstrNameIndices, LanaiInstrNameData, nullptr, nullptr, 422, nullptr, 0);
1460}
1461
1462
1463} // namespace llvm
1464
1465#endif // GET_INSTRINFO_MC_DESC
1466
1467#ifdef GET_INSTRINFO_HEADER
1468#undef GET_INSTRINFO_HEADER
1469
1470namespace llvm {
1471
1472struct LanaiGenInstrInfo : public TargetInstrInfo {
1473 explicit LanaiGenInstrInfo(const TargetSubtargetInfo &STI, const TargetRegisterInfo &TRI, unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u, unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u);
1474 ~LanaiGenInstrInfo() override = default;
1475};
1476
1477} // namespace llvm
1478
1479namespace llvm::Lanai {
1480
1481constexpr unsigned SUBOP_MEMri_base = 0;
1482constexpr unsigned SUBOP_MEMri_offset = 1;
1483constexpr unsigned SUBOP_MEMri_Opcode = 2;
1484constexpr unsigned SUBOP_MEMrr_Op1 = 0;
1485constexpr unsigned SUBOP_MEMrr_Op2 = 1;
1486constexpr unsigned SUBOP_MEMrr_Opcode = 2;
1487constexpr unsigned SUBOP_MEMspls_base = 0;
1488constexpr unsigned SUBOP_MEMspls_offset = 1;
1489constexpr unsigned SUBOP_MEMspls_Opcode = 2;
1490
1491} // namespace llvm::Lanai
1492
1493#endif // GET_INSTRINFO_HEADER
1494
1495#ifdef GET_INSTRINFO_HELPER_DECLS
1496#undef GET_INSTRINFO_HELPER_DECLS
1497
1498
1499#endif // GET_INSTRINFO_HELPER_DECLS
1500
1501#ifdef GET_INSTRINFO_HELPERS
1502#undef GET_INSTRINFO_HELPERS
1503
1504
1505#endif // GET_INSTRINFO_HELPERS
1506
1507#ifdef GET_INSTRINFO_CTOR_DTOR
1508#undef GET_INSTRINFO_CTOR_DTOR
1509
1510namespace llvm {
1511
1512extern const LanaiInstrTable LanaiDescs;
1513extern const unsigned LanaiInstrNameIndices[];
1514extern const char LanaiInstrNameData[];
1515LanaiGenInstrInfo::LanaiGenInstrInfo(const TargetSubtargetInfo &STI, const TargetRegisterInfo &TRI, unsigned CFSetupOpcode, unsigned CFDestroyOpcode, unsigned CatchRetOpcode, unsigned ReturnOpcode)
1516 : TargetInstrInfo(TRI, CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) {
1517 InitMCInstrInfo(LanaiDescs.Insts, LanaiInstrNameIndices, LanaiInstrNameData, nullptr, nullptr, 422);
1518}
1519
1520} // namespace llvm
1521
1522#endif // GET_INSTRINFO_CTOR_DTOR
1523
1524#ifdef GET_INSTRINFO_MC_HELPER_DECLS
1525#undef GET_INSTRINFO_MC_HELPER_DECLS
1526
1527namespace llvm {
1528
1529class MCInst;
1530class FeatureBitset;
1531
1532namespace Lanai_MC {
1533
1534void verifyInstructionPredicates(unsigned Opcode, const FeatureBitset &Features);
1535
1536} // namespace Lanai_MC
1537
1538} // namespace llvm
1539
1540#endif // GET_INSTRINFO_MC_HELPER_DECLS
1541
1542#ifdef GET_INSTRINFO_MC_HELPERS
1543#undef GET_INSTRINFO_MC_HELPERS
1544
1545namespace llvm::Lanai_MC {
1546
1547
1548} // namespace llvm::Lanai_MC
1549
1550#endif // GET_INSTRINFO_MC_HELPERS
1551
1552#if (defined(ENABLE_INSTR_PREDICATE_VERIFIER) && !defined(NDEBUG)) ||\
1553 defined(GET_AVAILABLE_OPCODE_CHECKER)
1554#define GET_COMPUTE_FEATURES
1555#endif
1556#ifdef GET_COMPUTE_FEATURES
1557#undef GET_COMPUTE_FEATURES
1558
1559namespace llvm::Lanai_MC {
1560
1561// Bits for subtarget features that participate in instruction matching.
1562enum SubtargetFeatureBits : uint8_t {
1563};
1564
1565inline FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) {
1566 FeatureBitset Features;
1567 return Features;
1568}
1569
1570inline FeatureBitset computeRequiredFeatures(unsigned Opcode) {
1571 enum : uint8_t {
1572 CEFBS_None,
1573 };
1574
1575 static constexpr FeatureBitset FeatureBitsets[] = {
1576 {}, // CEFBS_None
1577 };
1578 static constexpr uint8_t RequiredFeaturesRefs[] = {
1579 CEFBS_None, // PHI
1580 CEFBS_None, // INLINEASM
1581 CEFBS_None, // INLINEASM_BR
1582 CEFBS_None, // CFI_INSTRUCTION
1583 CEFBS_None, // EH_LABEL
1584 CEFBS_None, // GC_LABEL
1585 CEFBS_None, // ANNOTATION_LABEL
1586 CEFBS_None, // KILL
1587 CEFBS_None, // EXTRACT_SUBREG
1588 CEFBS_None, // INSERT_SUBREG
1589 CEFBS_None, // IMPLICIT_DEF
1590 CEFBS_None, // INIT_UNDEF
1591 CEFBS_None, // SUBREG_TO_REG
1592 CEFBS_None, // COPY_TO_REGCLASS
1593 CEFBS_None, // DBG_VALUE
1594 CEFBS_None, // DBG_VALUE_LIST
1595 CEFBS_None, // DBG_INSTR_REF
1596 CEFBS_None, // DBG_PHI
1597 CEFBS_None, // DBG_LABEL
1598 CEFBS_None, // REG_SEQUENCE
1599 CEFBS_None, // COPY
1600 CEFBS_None, // COPY_LANEMASK
1601 CEFBS_None, // BUNDLE
1602 CEFBS_None, // LIFETIME_START
1603 CEFBS_None, // LIFETIME_END
1604 CEFBS_None, // PSEUDO_PROBE
1605 CEFBS_None, // ARITH_FENCE
1606 CEFBS_None, // STACKMAP
1607 CEFBS_None, // FENTRY_CALL
1608 CEFBS_None, // PATCHPOINT
1609 CEFBS_None, // LOAD_STACK_GUARD
1610 CEFBS_None, // PREALLOCATED_SETUP
1611 CEFBS_None, // PREALLOCATED_ARG
1612 CEFBS_None, // STATEPOINT
1613 CEFBS_None, // LOCAL_ESCAPE
1614 CEFBS_None, // FAULTING_OP
1615 CEFBS_None, // PATCHABLE_OP
1616 CEFBS_None, // PATCHABLE_FUNCTION_ENTER
1617 CEFBS_None, // PATCHABLE_RET
1618 CEFBS_None, // PATCHABLE_FUNCTION_EXIT
1619 CEFBS_None, // PATCHABLE_TAIL_CALL
1620 CEFBS_None, // PATCHABLE_EVENT_CALL
1621 CEFBS_None, // PATCHABLE_TYPED_EVENT_CALL
1622 CEFBS_None, // ICALL_BRANCH_FUNNEL
1623 CEFBS_None, // FAKE_USE
1624 CEFBS_None, // MEMBARRIER
1625 CEFBS_None, // JUMP_TABLE_DEBUG_INFO
1626 CEFBS_None, // RELOC_NONE
1627 CEFBS_None, // CONVERGENCECTRL_ENTRY
1628 CEFBS_None, // CONVERGENCECTRL_ANCHOR
1629 CEFBS_None, // CONVERGENCECTRL_LOOP
1630 CEFBS_None, // CONVERGENCECTRL_GLUE
1631 CEFBS_None, // G_ASSERT_SEXT
1632 CEFBS_None, // G_ASSERT_ZEXT
1633 CEFBS_None, // G_ASSERT_ALIGN
1634 CEFBS_None, // G_ADD
1635 CEFBS_None, // G_SUB
1636 CEFBS_None, // G_MUL
1637 CEFBS_None, // G_SDIV
1638 CEFBS_None, // G_UDIV
1639 CEFBS_None, // G_SREM
1640 CEFBS_None, // G_UREM
1641 CEFBS_None, // G_SDIVREM
1642 CEFBS_None, // G_UDIVREM
1643 CEFBS_None, // G_AND
1644 CEFBS_None, // G_OR
1645 CEFBS_None, // G_XOR
1646 CEFBS_None, // G_ABDS
1647 CEFBS_None, // G_ABDU
1648 CEFBS_None, // G_UAVGFLOOR
1649 CEFBS_None, // G_UAVGCEIL
1650 CEFBS_None, // G_SAVGFLOOR
1651 CEFBS_None, // G_SAVGCEIL
1652 CEFBS_None, // G_IMPLICIT_DEF
1653 CEFBS_None, // G_PHI
1654 CEFBS_None, // G_FRAME_INDEX
1655 CEFBS_None, // G_GLOBAL_VALUE
1656 CEFBS_None, // G_PTRAUTH_GLOBAL_VALUE
1657 CEFBS_None, // G_CONSTANT_POOL
1658 CEFBS_None, // G_EXTRACT
1659 CEFBS_None, // G_UNMERGE_VALUES
1660 CEFBS_None, // G_INSERT
1661 CEFBS_None, // G_MERGE_VALUES
1662 CEFBS_None, // G_BUILD_VECTOR
1663 CEFBS_None, // G_BUILD_VECTOR_TRUNC
1664 CEFBS_None, // G_CONCAT_VECTORS
1665 CEFBS_None, // G_PTRTOINT
1666 CEFBS_None, // G_INTTOPTR
1667 CEFBS_None, // G_BITCAST
1668 CEFBS_None, // G_FREEZE
1669 CEFBS_None, // G_CONSTANT_FOLD_BARRIER
1670 CEFBS_None, // G_INTRINSIC_FPTRUNC_ROUND
1671 CEFBS_None, // G_INTRINSIC_TRUNC
1672 CEFBS_None, // G_INTRINSIC_ROUND
1673 CEFBS_None, // G_INTRINSIC_LRINT
1674 CEFBS_None, // G_INTRINSIC_LLRINT
1675 CEFBS_None, // G_INTRINSIC_ROUNDEVEN
1676 CEFBS_None, // G_READCYCLECOUNTER
1677 CEFBS_None, // G_READSTEADYCOUNTER
1678 CEFBS_None, // G_LOAD
1679 CEFBS_None, // G_SEXTLOAD
1680 CEFBS_None, // G_ZEXTLOAD
1681 CEFBS_None, // G_INDEXED_LOAD
1682 CEFBS_None, // G_INDEXED_SEXTLOAD
1683 CEFBS_None, // G_INDEXED_ZEXTLOAD
1684 CEFBS_None, // G_STORE
1685 CEFBS_None, // G_INDEXED_STORE
1686 CEFBS_None, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
1687 CEFBS_None, // G_ATOMIC_CMPXCHG
1688 CEFBS_None, // G_ATOMICRMW_XCHG
1689 CEFBS_None, // G_ATOMICRMW_ADD
1690 CEFBS_None, // G_ATOMICRMW_SUB
1691 CEFBS_None, // G_ATOMICRMW_AND
1692 CEFBS_None, // G_ATOMICRMW_NAND
1693 CEFBS_None, // G_ATOMICRMW_OR
1694 CEFBS_None, // G_ATOMICRMW_XOR
1695 CEFBS_None, // G_ATOMICRMW_MAX
1696 CEFBS_None, // G_ATOMICRMW_MIN
1697 CEFBS_None, // G_ATOMICRMW_UMAX
1698 CEFBS_None, // G_ATOMICRMW_UMIN
1699 CEFBS_None, // G_ATOMICRMW_FADD
1700 CEFBS_None, // G_ATOMICRMW_FSUB
1701 CEFBS_None, // G_ATOMICRMW_FMAX
1702 CEFBS_None, // G_ATOMICRMW_FMIN
1703 CEFBS_None, // G_ATOMICRMW_FMAXIMUM
1704 CEFBS_None, // G_ATOMICRMW_FMINIMUM
1705 CEFBS_None, // G_ATOMICRMW_UINC_WRAP
1706 CEFBS_None, // G_ATOMICRMW_UDEC_WRAP
1707 CEFBS_None, // G_ATOMICRMW_USUB_COND
1708 CEFBS_None, // G_ATOMICRMW_USUB_SAT
1709 CEFBS_None, // G_FENCE
1710 CEFBS_None, // G_PREFETCH
1711 CEFBS_None, // G_BRCOND
1712 CEFBS_None, // G_BRINDIRECT
1713 CEFBS_None, // G_INVOKE_REGION_START
1714 CEFBS_None, // G_INTRINSIC
1715 CEFBS_None, // G_INTRINSIC_W_SIDE_EFFECTS
1716 CEFBS_None, // G_INTRINSIC_CONVERGENT
1717 CEFBS_None, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
1718 CEFBS_None, // G_ANYEXT
1719 CEFBS_None, // G_TRUNC
1720 CEFBS_None, // G_TRUNC_SSAT_S
1721 CEFBS_None, // G_TRUNC_SSAT_U
1722 CEFBS_None, // G_TRUNC_USAT_U
1723 CEFBS_None, // G_CONSTANT
1724 CEFBS_None, // G_FCONSTANT
1725 CEFBS_None, // G_VASTART
1726 CEFBS_None, // G_VAARG
1727 CEFBS_None, // G_SEXT
1728 CEFBS_None, // G_SEXT_INREG
1729 CEFBS_None, // G_ZEXT
1730 CEFBS_None, // G_SHL
1731 CEFBS_None, // G_LSHR
1732 CEFBS_None, // G_ASHR
1733 CEFBS_None, // G_FSHL
1734 CEFBS_None, // G_FSHR
1735 CEFBS_None, // G_ROTR
1736 CEFBS_None, // G_ROTL
1737 CEFBS_None, // G_ICMP
1738 CEFBS_None, // G_FCMP
1739 CEFBS_None, // G_SCMP
1740 CEFBS_None, // G_UCMP
1741 CEFBS_None, // G_SELECT
1742 CEFBS_None, // G_UADDO
1743 CEFBS_None, // G_UADDE
1744 CEFBS_None, // G_USUBO
1745 CEFBS_None, // G_USUBE
1746 CEFBS_None, // G_SADDO
1747 CEFBS_None, // G_SADDE
1748 CEFBS_None, // G_SSUBO
1749 CEFBS_None, // G_SSUBE
1750 CEFBS_None, // G_UMULO
1751 CEFBS_None, // G_SMULO
1752 CEFBS_None, // G_UMULH
1753 CEFBS_None, // G_SMULH
1754 CEFBS_None, // G_UADDSAT
1755 CEFBS_None, // G_SADDSAT
1756 CEFBS_None, // G_USUBSAT
1757 CEFBS_None, // G_SSUBSAT
1758 CEFBS_None, // G_USHLSAT
1759 CEFBS_None, // G_SSHLSAT
1760 CEFBS_None, // G_SMULFIX
1761 CEFBS_None, // G_UMULFIX
1762 CEFBS_None, // G_SMULFIXSAT
1763 CEFBS_None, // G_UMULFIXSAT
1764 CEFBS_None, // G_SDIVFIX
1765 CEFBS_None, // G_UDIVFIX
1766 CEFBS_None, // G_SDIVFIXSAT
1767 CEFBS_None, // G_UDIVFIXSAT
1768 CEFBS_None, // G_FADD
1769 CEFBS_None, // G_FSUB
1770 CEFBS_None, // G_FMUL
1771 CEFBS_None, // G_FMA
1772 CEFBS_None, // G_FMAD
1773 CEFBS_None, // G_FDIV
1774 CEFBS_None, // G_FREM
1775 CEFBS_None, // G_FMODF
1776 CEFBS_None, // G_FPOW
1777 CEFBS_None, // G_FPOWI
1778 CEFBS_None, // G_FEXP
1779 CEFBS_None, // G_FEXP2
1780 CEFBS_None, // G_FEXP10
1781 CEFBS_None, // G_FLOG
1782 CEFBS_None, // G_FLOG2
1783 CEFBS_None, // G_FLOG10
1784 CEFBS_None, // G_FLDEXP
1785 CEFBS_None, // G_FFREXP
1786 CEFBS_None, // G_FNEG
1787 CEFBS_None, // G_FPEXT
1788 CEFBS_None, // G_FPTRUNC
1789 CEFBS_None, // G_FPTOSI
1790 CEFBS_None, // G_FPTOUI
1791 CEFBS_None, // G_SITOFP
1792 CEFBS_None, // G_UITOFP
1793 CEFBS_None, // G_FPTOSI_SAT
1794 CEFBS_None, // G_FPTOUI_SAT
1795 CEFBS_None, // G_FABS
1796 CEFBS_None, // G_FCOPYSIGN
1797 CEFBS_None, // G_IS_FPCLASS
1798 CEFBS_None, // G_FCANONICALIZE
1799 CEFBS_None, // G_FMINNUM
1800 CEFBS_None, // G_FMAXNUM
1801 CEFBS_None, // G_FMINNUM_IEEE
1802 CEFBS_None, // G_FMAXNUM_IEEE
1803 CEFBS_None, // G_FMINIMUM
1804 CEFBS_None, // G_FMAXIMUM
1805 CEFBS_None, // G_FMINIMUMNUM
1806 CEFBS_None, // G_FMAXIMUMNUM
1807 CEFBS_None, // G_GET_FPENV
1808 CEFBS_None, // G_SET_FPENV
1809 CEFBS_None, // G_RESET_FPENV
1810 CEFBS_None, // G_GET_FPMODE
1811 CEFBS_None, // G_SET_FPMODE
1812 CEFBS_None, // G_RESET_FPMODE
1813 CEFBS_None, // G_GET_ROUNDING
1814 CEFBS_None, // G_SET_ROUNDING
1815 CEFBS_None, // G_PTR_ADD
1816 CEFBS_None, // G_PTRMASK
1817 CEFBS_None, // G_SMIN
1818 CEFBS_None, // G_SMAX
1819 CEFBS_None, // G_UMIN
1820 CEFBS_None, // G_UMAX
1821 CEFBS_None, // G_ABS
1822 CEFBS_None, // G_LROUND
1823 CEFBS_None, // G_LLROUND
1824 CEFBS_None, // G_BR
1825 CEFBS_None, // G_BRJT
1826 CEFBS_None, // G_VSCALE
1827 CEFBS_None, // G_INSERT_SUBVECTOR
1828 CEFBS_None, // G_EXTRACT_SUBVECTOR
1829 CEFBS_None, // G_INSERT_VECTOR_ELT
1830 CEFBS_None, // G_EXTRACT_VECTOR_ELT
1831 CEFBS_None, // G_SHUFFLE_VECTOR
1832 CEFBS_None, // G_SPLAT_VECTOR
1833 CEFBS_None, // G_STEP_VECTOR
1834 CEFBS_None, // G_VECTOR_COMPRESS
1835 CEFBS_None, // G_CTTZ
1836 CEFBS_None, // G_CTTZ_ZERO_UNDEF
1837 CEFBS_None, // G_CTLZ
1838 CEFBS_None, // G_CTLZ_ZERO_UNDEF
1839 CEFBS_None, // G_CTLS
1840 CEFBS_None, // G_CTPOP
1841 CEFBS_None, // G_BSWAP
1842 CEFBS_None, // G_BITREVERSE
1843 CEFBS_None, // G_FCEIL
1844 CEFBS_None, // G_FCOS
1845 CEFBS_None, // G_FSIN
1846 CEFBS_None, // G_FSINCOS
1847 CEFBS_None, // G_FTAN
1848 CEFBS_None, // G_FACOS
1849 CEFBS_None, // G_FASIN
1850 CEFBS_None, // G_FATAN
1851 CEFBS_None, // G_FATAN2
1852 CEFBS_None, // G_FCOSH
1853 CEFBS_None, // G_FSINH
1854 CEFBS_None, // G_FTANH
1855 CEFBS_None, // G_FSQRT
1856 CEFBS_None, // G_FFLOOR
1857 CEFBS_None, // G_FRINT
1858 CEFBS_None, // G_FNEARBYINT
1859 CEFBS_None, // G_ADDRSPACE_CAST
1860 CEFBS_None, // G_BLOCK_ADDR
1861 CEFBS_None, // G_JUMP_TABLE
1862 CEFBS_None, // G_DYN_STACKALLOC
1863 CEFBS_None, // G_STACKSAVE
1864 CEFBS_None, // G_STACKRESTORE
1865 CEFBS_None, // G_STRICT_FADD
1866 CEFBS_None, // G_STRICT_FSUB
1867 CEFBS_None, // G_STRICT_FMUL
1868 CEFBS_None, // G_STRICT_FDIV
1869 CEFBS_None, // G_STRICT_FREM
1870 CEFBS_None, // G_STRICT_FMA
1871 CEFBS_None, // G_STRICT_FSQRT
1872 CEFBS_None, // G_STRICT_FLDEXP
1873 CEFBS_None, // G_READ_REGISTER
1874 CEFBS_None, // G_WRITE_REGISTER
1875 CEFBS_None, // G_MEMCPY
1876 CEFBS_None, // G_MEMCPY_INLINE
1877 CEFBS_None, // G_MEMMOVE
1878 CEFBS_None, // G_MEMSET
1879 CEFBS_None, // G_BZERO
1880 CEFBS_None, // G_TRAP
1881 CEFBS_None, // G_DEBUGTRAP
1882 CEFBS_None, // G_UBSANTRAP
1883 CEFBS_None, // G_VECREDUCE_SEQ_FADD
1884 CEFBS_None, // G_VECREDUCE_SEQ_FMUL
1885 CEFBS_None, // G_VECREDUCE_FADD
1886 CEFBS_None, // G_VECREDUCE_FMUL
1887 CEFBS_None, // G_VECREDUCE_FMAX
1888 CEFBS_None, // G_VECREDUCE_FMIN
1889 CEFBS_None, // G_VECREDUCE_FMAXIMUM
1890 CEFBS_None, // G_VECREDUCE_FMINIMUM
1891 CEFBS_None, // G_VECREDUCE_ADD
1892 CEFBS_None, // G_VECREDUCE_MUL
1893 CEFBS_None, // G_VECREDUCE_AND
1894 CEFBS_None, // G_VECREDUCE_OR
1895 CEFBS_None, // G_VECREDUCE_XOR
1896 CEFBS_None, // G_VECREDUCE_SMAX
1897 CEFBS_None, // G_VECREDUCE_SMIN
1898 CEFBS_None, // G_VECREDUCE_UMAX
1899 CEFBS_None, // G_VECREDUCE_UMIN
1900 CEFBS_None, // G_SBFX
1901 CEFBS_None, // G_UBFX
1902 CEFBS_None, // ADJCALLSTACKDOWN
1903 CEFBS_None, // ADJCALLSTACKUP
1904 CEFBS_None, // ADJDYNALLOC
1905 CEFBS_None, // CALL
1906 CEFBS_None, // CALLR
1907 CEFBS_None, // ADDC_F_I_HI
1908 CEFBS_None, // ADDC_F_I_LO
1909 CEFBS_None, // ADDC_F_R
1910 CEFBS_None, // ADDC_I_HI
1911 CEFBS_None, // ADDC_I_LO
1912 CEFBS_None, // ADDC_R
1913 CEFBS_None, // ADD_F_I_HI
1914 CEFBS_None, // ADD_F_I_LO
1915 CEFBS_None, // ADD_F_R
1916 CEFBS_None, // ADD_I_HI
1917 CEFBS_None, // ADD_I_LO
1918 CEFBS_None, // ADD_R
1919 CEFBS_None, // AND_F_I_HI
1920 CEFBS_None, // AND_F_I_LO
1921 CEFBS_None, // AND_F_R
1922 CEFBS_None, // AND_I_HI
1923 CEFBS_None, // AND_I_LO
1924 CEFBS_None, // AND_R
1925 CEFBS_None, // BRCC
1926 CEFBS_None, // BRIND_CC
1927 CEFBS_None, // BRIND_CCA
1928 CEFBS_None, // BRR
1929 CEFBS_None, // BT
1930 CEFBS_None, // JR
1931 CEFBS_None, // LDADDR
1932 CEFBS_None, // LDBs_RI
1933 CEFBS_None, // LDBs_RR
1934 CEFBS_None, // LDBz_RI
1935 CEFBS_None, // LDBz_RR
1936 CEFBS_None, // LDHs_RI
1937 CEFBS_None, // LDHs_RR
1938 CEFBS_None, // LDHz_RI
1939 CEFBS_None, // LDHz_RR
1940 CEFBS_None, // LDW_RI
1941 CEFBS_None, // LDW_RR
1942 CEFBS_None, // LDWz_RR
1943 CEFBS_None, // LEADZ
1944 CEFBS_None, // LOG0
1945 CEFBS_None, // LOG1
1946 CEFBS_None, // LOG2
1947 CEFBS_None, // LOG3
1948 CEFBS_None, // LOG4
1949 CEFBS_None, // MOVHI
1950 CEFBS_None, // NOP
1951 CEFBS_None, // OR_F_I_HI
1952 CEFBS_None, // OR_F_I_LO
1953 CEFBS_None, // OR_F_R
1954 CEFBS_None, // OR_I_HI
1955 CEFBS_None, // OR_I_LO
1956 CEFBS_None, // OR_R
1957 CEFBS_None, // POPC
1958 CEFBS_None, // RET
1959 CEFBS_None, // SA_F_I
1960 CEFBS_None, // SA_I
1961 CEFBS_None, // SCC
1962 CEFBS_None, // SELECT
1963 CEFBS_None, // SFSUB_F_RI_HI
1964 CEFBS_None, // SFSUB_F_RI_LO
1965 CEFBS_None, // SFSUB_F_RR
1966 CEFBS_None, // SHL_F_R
1967 CEFBS_None, // SHL_R
1968 CEFBS_None, // SLI
1969 CEFBS_None, // SL_F_I
1970 CEFBS_None, // SL_I
1971 CEFBS_None, // SRA_F_R
1972 CEFBS_None, // SRA_R
1973 CEFBS_None, // SRL_F_R
1974 CEFBS_None, // SRL_R
1975 CEFBS_None, // STADDR
1976 CEFBS_None, // STB_RI
1977 CEFBS_None, // STB_RR
1978 CEFBS_None, // STH_RI
1979 CEFBS_None, // STH_RR
1980 CEFBS_None, // SUBB_F_I_HI
1981 CEFBS_None, // SUBB_F_I_LO
1982 CEFBS_None, // SUBB_F_R
1983 CEFBS_None, // SUBB_I_HI
1984 CEFBS_None, // SUBB_I_LO
1985 CEFBS_None, // SUBB_R
1986 CEFBS_None, // SUB_F_I_HI
1987 CEFBS_None, // SUB_F_I_LO
1988 CEFBS_None, // SUB_F_R
1989 CEFBS_None, // SUB_I_HI
1990 CEFBS_None, // SUB_I_LO
1991 CEFBS_None, // SUB_R
1992 CEFBS_None, // SW_RI
1993 CEFBS_None, // SW_RR
1994 CEFBS_None, // TRAILZ
1995 CEFBS_None, // XOR_F_I_HI
1996 CEFBS_None, // XOR_F_I_LO
1997 CEFBS_None, // XOR_F_R
1998 CEFBS_None, // XOR_I_HI
1999 CEFBS_None, // XOR_I_LO
2000 CEFBS_None, // XOR_R
2001 };
2002
2003 assert(Opcode < 422);
2004 return FeatureBitsets[RequiredFeaturesRefs[Opcode]];
2005}
2006
2007
2008} // namespace llvm::Lanai_MC
2009
2010#endif // GET_COMPUTE_FEATURES
2011
2012#ifdef GET_AVAILABLE_OPCODE_CHECKER
2013#undef GET_AVAILABLE_OPCODE_CHECKER
2014
2015namespace llvm::Lanai_MC {
2016
2017bool isOpcodeAvailable(unsigned Opcode, const FeatureBitset &Features) {
2018 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
2019 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
2020 FeatureBitset MissingFeatures =
2021 (AvailableFeatures & RequiredFeatures) ^
2022 RequiredFeatures;
2023 return !MissingFeatures.any();
2024}
2025
2026} // namespace llvm::Lanai_MC
2027
2028#endif // GET_AVAILABLE_OPCODE_CHECKER
2029
2030#ifdef ENABLE_INSTR_PREDICATE_VERIFIER
2031#undef ENABLE_INSTR_PREDICATE_VERIFIER
2032
2033#include <sstream>
2034
2035namespace llvm::Lanai_MC {
2036
2037#ifndef NDEBUG
2038static const char *SubtargetFeatureNames[] = {
2039 nullptr
2040};
2041
2042#endif // NDEBUG
2043
2044void verifyInstructionPredicates(
2045 unsigned Opcode, const FeatureBitset &Features) {
2046#ifndef NDEBUG
2047 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
2048 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
2049 FeatureBitset MissingFeatures =
2050 (AvailableFeatures & RequiredFeatures) ^
2051 RequiredFeatures;
2052 if (MissingFeatures.any()) {
2053 std::ostringstream Msg;
2054 Msg << "Attempting to emit " << &LanaiInstrNameData[LanaiInstrNameIndices[Opcode]]
2055 << " instruction but the ";
2056 for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i)
2057 if (MissingFeatures.test(i))
2058 Msg << SubtargetFeatureNames[i] << " ";
2059 Msg << "predicate(s) are not met";
2060 report_fatal_error(Msg.str().c_str());
2061 }
2062#endif // NDEBUG
2063}
2064
2065} // namespace llvm::Lanai_MC
2066
2067#endif // ENABLE_INSTR_PREDICATE_VERIFIER
2068
2069#ifdef GET_INSTRMAP_INFO
2070#undef GET_INSTRMAP_INFO
2071
2072namespace llvm::Lanai {
2073
2074enum PostEncoderMethod {
2075 PostEncoderMethod_adjustPqBitsSpls
2076};
2077
2078// splsIdempotent
2079LLVM_READONLY
2080int splsIdempotent(uint16_t Opcode) {
2081 using namespace Lanai;
2082 static constexpr uint16_t Table[][2] = {
2083 { LDBs_RI, LDBs_RI },
2084 { LDBz_RI, LDBz_RI },
2085 { LDHs_RI, LDHs_RI },
2086 { LDHz_RI, LDHz_RI },
2087 { STB_RI, STB_RI },
2088 { STH_RI, STH_RI },
2089 }; // End of Table
2090
2091 unsigned mid;
2092 unsigned start = 0;
2093 unsigned end = 6;
2094 while (start < end) {
2095 mid = start + (end - start) / 2;
2096 if (Opcode == Table[mid][0])
2097 break;
2098 if (Opcode < Table[mid][0])
2099 end = mid;
2100 else
2101 start = mid + 1;
2102 }
2103 if (start == end)
2104 return -1; // Instruction doesn't exist in this table.
2105
2106 return Table[mid][1];
2107}
2108
2109
2110} // namespace llvm::Lanai
2111
2112#endif // GET_INSTRMAP_INFO
2113
2114