1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Instruction Enum Values and Descriptors *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_INSTRINFO_ENUM
10#undef GET_INSTRINFO_ENUM
11
12namespace llvm::Lanai {
13
14 enum {
15 PHI = 0, // Target.td:1324
16 INLINEASM = 1, // Target.td:1330
17 INLINEASM_BR = 2, // Target.td:1336
18 CFI_INSTRUCTION = 3, // Target.td:1345
19 EH_LABEL = 4, // Target.td:1354
20 GC_LABEL = 5, // Target.td:1363
21 ANNOTATION_LABEL = 6, // Target.td:1372
22 KILL = 7, // Target.td:1380
23 EXTRACT_SUBREG = 8, // Target.td:1387
24 INSERT_SUBREG = 9, // Target.td:1393
25 IMPLICIT_DEF = 10, // Target.td:1400
26 INIT_UNDEF = 11, // Target.td:1409
27 SUBREG_TO_REG = 12, // Target.td:1416
28 COPY_TO_REGCLASS = 13, // Target.td:1422
29 DBG_VALUE = 14, // Target.td:1429
30 DBG_VALUE_LIST = 15, // Target.td:1436
31 DBG_INSTR_REF = 16, // Target.td:1443
32 DBG_PHI = 17, // Target.td:1450
33 DBG_LABEL = 18, // Target.td:1457
34 REG_SEQUENCE = 19, // Target.td:1464
35 COPY = 20, // Target.td:1471
36 COPY_LANEMASK = 21, // Target.td:1479
37 BUNDLE = 22, // Target.td:1486
38 LIFETIME_START = 23, // Target.td:1492
39 LIFETIME_END = 24, // Target.td:1499
40 PSEUDO_PROBE = 25, // Target.td:1506
41 ARITH_FENCE = 26, // Target.td:1513
42 STACKMAP = 27, // Target.td:1522
43 FENTRY_CALL = 28, // Target.td:1657
44 PATCHPOINT = 29, // Target.td:1530
45 LOAD_STACK_GUARD = 30, // Target.td:1548
46 PREALLOCATED_SETUP = 31, // Target.td:1556
47 PREALLOCATED_ARG = 32, // Target.td:1562
48 STATEPOINT = 33, // Target.td:1539
49 LOCAL_ESCAPE = 34, // Target.td:1568
50 FAULTING_OP = 35, // Target.td:1577
51 PATCHABLE_OP = 36, // Target.td:1597
52 PATCHABLE_FUNCTION_ENTER = 37, // Target.td:1605
53 PATCHABLE_RET = 38, // Target.td:1612
54 PATCHABLE_FUNCTION_EXIT = 39, // Target.td:1621
55 PATCHABLE_TAIL_CALL = 40, // Target.td:1629
56 PATCHABLE_EVENT_CALL = 41, // Target.td:1637
57 PATCHABLE_TYPED_EVENT_CALL = 42, // Target.td:1647
58 ICALL_BRANCH_FUNNEL = 43, // Target.td:1667
59 FAKE_USE = 44, // Target.td:1587
60 MEMBARRIER = 45, // Target.td:1673
61 JUMP_TABLE_DEBUG_INFO = 46, // Target.td:1681
62 RELOC_NONE = 47, // Target.td:1689
63 CONVERGENCECTRL_ENTRY = 48, // Target.td:1701
64 CONVERGENCECTRL_ANCHOR = 49, // Target.td:1697
65 CONVERGENCECTRL_LOOP = 50, // Target.td:1705
66 CONVERGENCECTRL_GLUE = 51, // Target.td:1709
67 G_ASSERT_SEXT = 52, // GenericOpcodes.td:1929
68 G_ASSERT_ZEXT = 53, // GenericOpcodes.td:1921
69 G_ASSERT_ALIGN = 54, // GenericOpcodes.td:1936
70 G_ADD = 55, // GenericOpcodes.td:308
71 G_SUB = 56, // GenericOpcodes.td:316
72 G_MUL = 57, // GenericOpcodes.td:324
73 G_SDIV = 58, // GenericOpcodes.td:332
74 G_UDIV = 59, // GenericOpcodes.td:340
75 G_SREM = 60, // GenericOpcodes.td:348
76 G_UREM = 61, // GenericOpcodes.td:356
77 G_SDIVREM = 62, // GenericOpcodes.td:364
78 G_UDIVREM = 63, // GenericOpcodes.td:372
79 G_AND = 64, // GenericOpcodes.td:380
80 G_OR = 65, // GenericOpcodes.td:388
81 G_XOR = 66, // GenericOpcodes.td:396
82 G_ABDS = 67, // GenericOpcodes.td:425
83 G_ABDU = 68, // GenericOpcodes.td:433
84 G_UAVGFLOOR = 69, // GenericOpcodes.td:441
85 G_UAVGCEIL = 70, // GenericOpcodes.td:448
86 G_SAVGFLOOR = 71, // GenericOpcodes.td:455
87 G_SAVGCEIL = 72, // GenericOpcodes.td:462
88 G_IMPLICIT_DEF = 73, // GenericOpcodes.td:111
89 G_PHI = 74, // GenericOpcodes.td:118
90 G_FRAME_INDEX = 75, // GenericOpcodes.td:125
91 G_GLOBAL_VALUE = 76, // GenericOpcodes.td:131
92 G_PTRAUTH_GLOBAL_VALUE = 77, // GenericOpcodes.td:137
93 G_CONSTANT_POOL = 78, // GenericOpcodes.td:143
94 G_EXTRACT = 79, // GenericOpcodes.td:1516
95 G_UNMERGE_VALUES = 80, // GenericOpcodes.td:1529
96 G_INSERT = 81, // GenericOpcodes.td:1538
97 G_MERGE_VALUES = 82, // GenericOpcodes.td:1548
98 G_BUILD_VECTOR = 83, // GenericOpcodes.td:1568
99 G_BUILD_VECTOR_TRUNC = 84, // GenericOpcodes.td:1578
100 G_CONCAT_VECTORS = 85, // GenericOpcodes.td:1585
101 G_PTRTOINT = 86, // GenericOpcodes.td:155
102 G_INTTOPTR = 87, // GenericOpcodes.td:149
103 G_BITCAST = 88, // GenericOpcodes.td:161
104 G_FREEZE = 89, // GenericOpcodes.td:284
105 G_CONSTANT_FOLD_BARRIER = 90, // GenericOpcodes.td:1943
106 G_INTRINSIC_FPTRUNC_ROUND = 91, // GenericOpcodes.td:1280
107 G_INTRINSIC_TRUNC = 92, // GenericOpcodes.td:1286
108 G_INTRINSIC_ROUND = 93, // GenericOpcodes.td:1292
109 G_INTRINSIC_LRINT = 94, // GenericOpcodes.td:1298
110 G_INTRINSIC_LLRINT = 95, // GenericOpcodes.td:1304
111 G_INTRINSIC_ROUNDEVEN = 96, // GenericOpcodes.td:1310
112 G_READCYCLECOUNTER = 97, // GenericOpcodes.td:1316
113 G_READSTEADYCOUNTER = 98, // GenericOpcodes.td:1322
114 G_LOAD = 99, // GenericOpcodes.td:1349
115 G_SEXTLOAD = 100, // GenericOpcodes.td:1358
116 G_ZEXTLOAD = 101, // GenericOpcodes.td:1366
117 G_FPEXTLOAD = 102, // GenericOpcodes.td:1375
118 G_INDEXED_LOAD = 103, // GenericOpcodes.td:1385
119 G_INDEXED_SEXTLOAD = 104, // GenericOpcodes.td:1394
120 G_INDEXED_ZEXTLOAD = 105, // GenericOpcodes.td:1402
121 G_STORE = 106, // GenericOpcodes.td:1410
122 G_FPTRUNCSTORE = 107, // GenericOpcodes.td:1420
123 G_INDEXED_STORE = 108, // GenericOpcodes.td:1428
124 G_ATOMIC_CMPXCHG_WITH_SUCCESS = 109, // GenericOpcodes.td:1439
125 G_ATOMIC_CMPXCHG = 110, // GenericOpcodes.td:1450
126 G_ATOMICRMW_XCHG = 111, // GenericOpcodes.td:1470
127 G_ATOMICRMW_ADD = 112, // GenericOpcodes.td:1471
128 G_ATOMICRMW_SUB = 113, // GenericOpcodes.td:1472
129 G_ATOMICRMW_AND = 114, // GenericOpcodes.td:1473
130 G_ATOMICRMW_NAND = 115, // GenericOpcodes.td:1474
131 G_ATOMICRMW_OR = 116, // GenericOpcodes.td:1475
132 G_ATOMICRMW_XOR = 117, // GenericOpcodes.td:1476
133 G_ATOMICRMW_MAX = 118, // GenericOpcodes.td:1477
134 G_ATOMICRMW_MIN = 119, // GenericOpcodes.td:1478
135 G_ATOMICRMW_UMAX = 120, // GenericOpcodes.td:1479
136 G_ATOMICRMW_UMIN = 121, // GenericOpcodes.td:1480
137 G_ATOMICRMW_FADD = 122, // GenericOpcodes.td:1481
138 G_ATOMICRMW_FSUB = 123, // GenericOpcodes.td:1482
139 G_ATOMICRMW_FMAX = 124, // GenericOpcodes.td:1483
140 G_ATOMICRMW_FMIN = 125, // GenericOpcodes.td:1484
141 G_ATOMICRMW_FMAXIMUM = 126, // GenericOpcodes.td:1485
142 G_ATOMICRMW_FMINIMUM = 127, // GenericOpcodes.td:1486
143 G_ATOMICRMW_FMAXIMUMNUM = 128, // GenericOpcodes.td:1487
144 G_ATOMICRMW_FMINIMUMNUM = 129, // GenericOpcodes.td:1488
145 G_ATOMICRMW_UINC_WRAP = 130, // GenericOpcodes.td:1489
146 G_ATOMICRMW_UDEC_WRAP = 131, // GenericOpcodes.td:1490
147 G_ATOMICRMW_USUB_COND = 132, // GenericOpcodes.td:1491
148 G_ATOMICRMW_USUB_SAT = 133, // GenericOpcodes.td:1492
149 G_FENCE = 134, // GenericOpcodes.td:1494
150 G_PREFETCH = 135, // GenericOpcodes.td:1501
151 G_BRCOND = 136, // GenericOpcodes.td:1641
152 G_BRINDIRECT = 137, // GenericOpcodes.td:1650
153 G_INVOKE_REGION_START = 138, // GenericOpcodes.td:1673
154 G_INTRINSIC = 139, // GenericOpcodes.td:1593
155 G_INTRINSIC_W_SIDE_EFFECTS = 140, // GenericOpcodes.td:1600
156 G_INTRINSIC_CONVERGENT = 141, // GenericOpcodes.td:1609
157 G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 142, // GenericOpcodes.td:1617
158 G_ANYEXT = 143, // GenericOpcodes.td:44
159 G_TRUNC = 144, // GenericOpcodes.td:83
160 G_TRUNC_SSAT_S = 145, // GenericOpcodes.td:91
161 G_TRUNC_SSAT_U = 146, // GenericOpcodes.td:98
162 G_TRUNC_USAT_U = 147, // GenericOpcodes.td:105
163 G_CONSTANT = 148, // GenericOpcodes.td:169
164 G_FCONSTANT = 149, // GenericOpcodes.td:177
165 G_VASTART = 150, // GenericOpcodes.td:184
166 G_VAARG = 151, // GenericOpcodes.td:191
167 G_SEXT = 152, // GenericOpcodes.td:52
168 G_SEXT_INREG = 153, // GenericOpcodes.td:66
169 G_ZEXT = 154, // GenericOpcodes.td:74
170 G_SHL = 155, // GenericOpcodes.td:404
171 G_LSHR = 156, // GenericOpcodes.td:411
172 G_ASHR = 157, // GenericOpcodes.td:418
173 G_FSHL = 158, // GenericOpcodes.td:470
174 G_FSHR = 159, // GenericOpcodes.td:478
175 G_ROTR = 160, // GenericOpcodes.td:485
176 G_ROTL = 161, // GenericOpcodes.td:492
177 G_ICMP = 162, // GenericOpcodes.td:499
178 G_FCMP = 163, // GenericOpcodes.td:506
179 G_SCMP = 164, // GenericOpcodes.td:513
180 G_UCMP = 165, // GenericOpcodes.td:520
181 G_SELECT = 166, // GenericOpcodes.td:527
182 G_UADDO = 167, // GenericOpcodes.td:601
183 G_UADDE = 168, // GenericOpcodes.td:609
184 G_USUBO = 169, // GenericOpcodes.td:631
185 G_USUBE = 170, // GenericOpcodes.td:637
186 G_SADDO = 171, // GenericOpcodes.td:616
187 G_SADDE = 172, // GenericOpcodes.td:624
188 G_SSUBO = 173, // GenericOpcodes.td:644
189 G_SSUBE = 174, // GenericOpcodes.td:651
190 G_UMULO = 175, // GenericOpcodes.td:658
191 G_SMULO = 176, // GenericOpcodes.td:666
192 G_UMULH = 177, // GenericOpcodes.td:675
193 G_SMULH = 178, // GenericOpcodes.td:684
194 G_UADDSAT = 179, // GenericOpcodes.td:696
195 G_SADDSAT = 180, // GenericOpcodes.td:704
196 G_USUBSAT = 181, // GenericOpcodes.td:712
197 G_SSUBSAT = 182, // GenericOpcodes.td:720
198 G_USHLSAT = 183, // GenericOpcodes.td:728
199 G_SSHLSAT = 184, // GenericOpcodes.td:736
200 G_SMULFIX = 185, // GenericOpcodes.td:748
201 G_UMULFIX = 186, // GenericOpcodes.td:755
202 G_SMULFIXSAT = 187, // GenericOpcodes.td:765
203 G_UMULFIXSAT = 188, // GenericOpcodes.td:772
204 G_SDIVFIX = 189, // GenericOpcodes.td:783
205 G_UDIVFIX = 190, // GenericOpcodes.td:790
206 G_SDIVFIXSAT = 191, // GenericOpcodes.td:800
207 G_UDIVFIXSAT = 192, // GenericOpcodes.td:807
208 G_FADD = 193, // GenericOpcodes.td:980
209 G_FSUB = 194, // GenericOpcodes.td:988
210 G_FMUL = 195, // GenericOpcodes.td:996
211 G_FMA = 196, // GenericOpcodes.td:1005
212 G_FMAD = 197, // GenericOpcodes.td:1014
213 G_FDIV = 198, // GenericOpcodes.td:1022
214 G_FREM = 199, // GenericOpcodes.td:1029
215 G_FMODF = 200, // GenericOpcodes.td:1036
216 G_FPOW = 201, // GenericOpcodes.td:1043
217 G_FPOWI = 202, // GenericOpcodes.td:1050
218 G_FEXP = 203, // GenericOpcodes.td:1057
219 G_FEXP2 = 204, // GenericOpcodes.td:1064
220 G_FEXP10 = 205, // GenericOpcodes.td:1071
221 G_FLOG = 206, // GenericOpcodes.td:1078
222 G_FLOG2 = 207, // GenericOpcodes.td:1085
223 G_FLOG10 = 208, // GenericOpcodes.td:1092
224 G_FLDEXP = 209, // GenericOpcodes.td:1099
225 G_FFREXP = 210, // GenericOpcodes.td:1106
226 G_FNEG = 211, // GenericOpcodes.td:818
227 G_FPEXT = 212, // GenericOpcodes.td:824
228 G_FPTRUNC = 213, // GenericOpcodes.td:830
229 G_FPTOSI = 214, // GenericOpcodes.td:836
230 G_FPTOUI = 215, // GenericOpcodes.td:842
231 G_SITOFP = 216, // GenericOpcodes.td:848
232 G_UITOFP = 217, // GenericOpcodes.td:854
233 G_FPTOSI_SAT = 218, // GenericOpcodes.td:860
234 G_FPTOUI_SAT = 219, // GenericOpcodes.td:866
235 G_FABS = 220, // GenericOpcodes.td:872
236 G_FCOPYSIGN = 221, // GenericOpcodes.td:878
237 G_IS_FPCLASS = 222, // GenericOpcodes.td:891
238 G_FCANONICALIZE = 223, // GenericOpcodes.td:884
239 G_FMINNUM = 224, // GenericOpcodes.td:904
240 G_FMAXNUM = 225, // GenericOpcodes.td:911
241 G_FMINNUM_IEEE = 226, // GenericOpcodes.td:929
242 G_FMAXNUM_IEEE = 227, // GenericOpcodes.td:936
243 G_FMINIMUM = 228, // GenericOpcodes.td:946
244 G_FMAXIMUM = 229, // GenericOpcodes.td:953
245 G_FMINIMUMNUM = 230, // GenericOpcodes.td:961
246 G_FMAXIMUMNUM = 231, // GenericOpcodes.td:968
247 G_GET_FPENV = 232, // GenericOpcodes.td:1236
248 G_SET_FPENV = 233, // GenericOpcodes.td:1243
249 G_RESET_FPENV = 234, // GenericOpcodes.td:1250
250 G_GET_FPMODE = 235, // GenericOpcodes.td:1257
251 G_SET_FPMODE = 236, // GenericOpcodes.td:1264
252 G_RESET_FPMODE = 237, // GenericOpcodes.td:1271
253 G_GET_ROUNDING = 238, // GenericOpcodes.td:1328
254 G_SET_ROUNDING = 239, // GenericOpcodes.td:1334
255 G_PTR_ADD = 240, // GenericOpcodes.td:534
256 G_PTRMASK = 241, // GenericOpcodes.td:542
257 G_SMIN = 242, // GenericOpcodes.td:549
258 G_SMAX = 243, // GenericOpcodes.td:557
259 G_UMIN = 244, // GenericOpcodes.td:565
260 G_UMAX = 245, // GenericOpcodes.td:573
261 G_ABS = 246, // GenericOpcodes.td:581
262 G_LROUND = 247, // GenericOpcodes.td:291
263 G_LLROUND = 248, // GenericOpcodes.td:297
264 G_BR = 249, // GenericOpcodes.td:1631
265 G_BRJT = 250, // GenericOpcodes.td:1661
266 G_VSCALE = 251, // GenericOpcodes.td:1559
267 G_INSERT_SUBVECTOR = 252, // GenericOpcodes.td:1705
268 G_EXTRACT_SUBVECTOR = 253, // GenericOpcodes.td:1713
269 G_INSERT_VECTOR_ELT = 254, // GenericOpcodes.td:1721
270 G_EXTRACT_VECTOR_ELT = 255, // GenericOpcodes.td:1729
271 G_SHUFFLE_VECTOR = 256, // GenericOpcodes.td:1740
272 G_SPLAT_VECTOR = 257, // GenericOpcodes.td:1748
273 G_STEP_VECTOR = 258, // GenericOpcodes.td:1756
274 G_VECTOR_COMPRESS = 259, // GenericOpcodes.td:1763
275 G_CTTZ = 260, // GenericOpcodes.td:211
276 G_CTTZ_ZERO_POISON = 261, // GenericOpcodes.td:217
277 G_CTLZ = 262, // GenericOpcodes.td:199
278 G_CTLZ_ZERO_POISON = 263, // GenericOpcodes.td:205
279 G_CTLS = 264, // GenericOpcodes.td:223
280 G_CTPOP = 265, // GenericOpcodes.td:229
281 G_BSWAP = 266, // GenericOpcodes.td:235
282 G_BITREVERSE = 267, // GenericOpcodes.td:242
283 G_CLMUL = 268, // GenericOpcodes.td:588
284 G_FCEIL = 269, // GenericOpcodes.td:1113
285 G_FCOS = 270, // GenericOpcodes.td:1120
286 G_FSIN = 271, // GenericOpcodes.td:1127
287 G_FSINCOS = 272, // GenericOpcodes.td:1134
288 G_FTAN = 273, // GenericOpcodes.td:1141
289 G_FACOS = 274, // GenericOpcodes.td:1148
290 G_FASIN = 275, // GenericOpcodes.td:1155
291 G_FATAN = 276, // GenericOpcodes.td:1162
292 G_FATAN2 = 277, // GenericOpcodes.td:1169
293 G_FCOSH = 278, // GenericOpcodes.td:1176
294 G_FSINH = 279, // GenericOpcodes.td:1183
295 G_FTANH = 280, // GenericOpcodes.td:1190
296 G_FSQRT = 281, // GenericOpcodes.td:1200
297 G_FFLOOR = 282, // GenericOpcodes.td:1207
298 G_FRINT = 283, // GenericOpcodes.td:1214
299 G_FNEARBYINT = 284, // GenericOpcodes.td:1221
300 G_ADDRSPACE_CAST = 285, // GenericOpcodes.td:248
301 G_BLOCK_ADDR = 286, // GenericOpcodes.td:254
302 G_JUMP_TABLE = 287, // GenericOpcodes.td:260
303 G_DYN_STACKALLOC = 288, // GenericOpcodes.td:266
304 G_STACKSAVE = 289, // GenericOpcodes.td:272
305 G_STACKRESTORE = 290, // GenericOpcodes.td:278
306 G_STRICT_FADD = 291, // GenericOpcodes.td:1813
307 G_STRICT_FSUB = 292, // GenericOpcodes.td:1814
308 G_STRICT_FMUL = 293, // GenericOpcodes.td:1815
309 G_STRICT_FDIV = 294, // GenericOpcodes.td:1816
310 G_STRICT_FREM = 295, // GenericOpcodes.td:1817
311 G_STRICT_FMA = 296, // GenericOpcodes.td:1818
312 G_STRICT_FSQRT = 297, // GenericOpcodes.td:1819
313 G_STRICT_FLDEXP = 298, // GenericOpcodes.td:1820
314 G_STRICT_FCMP = 299, // GenericOpcodes.td:1821
315 G_STRICT_FCMPS = 300, // GenericOpcodes.td:1822
316 G_READ_REGISTER = 301, // GenericOpcodes.td:1680
317 G_WRITE_REGISTER = 302, // GenericOpcodes.td:1690
318 G_MEMCPY = 303, // GenericOpcodes.td:1828
319 G_MEMCPY_INLINE = 304, // GenericOpcodes.td:1836
320 G_MEMMOVE = 305, // GenericOpcodes.td:1844
321 G_MEMSET = 306, // GenericOpcodes.td:1852
322 G_BZERO = 307, // GenericOpcodes.td:1859
323 G_MEMSET_INLINE = 308, // GenericOpcodes.td:1866
324 G_TRAP = 309, // GenericOpcodes.td:1876
325 G_DEBUGTRAP = 310, // GenericOpcodes.td:1883
326 G_UBSANTRAP = 311, // GenericOpcodes.td:1889
327 G_VECREDUCE_SEQ_FADD = 312, // GenericOpcodes.td:1779
328 G_VECREDUCE_SEQ_FMUL = 313, // GenericOpcodes.td:1785
329 G_VECREDUCE_FADD = 314, // GenericOpcodes.td:1791
330 G_VECREDUCE_FMUL = 315, // GenericOpcodes.td:1792
331 G_VECREDUCE_FMAX = 316, // GenericOpcodes.td:1794
332 G_VECREDUCE_FMIN = 317, // GenericOpcodes.td:1795
333 G_VECREDUCE_FMAXIMUM = 318, // GenericOpcodes.td:1796
334 G_VECREDUCE_FMINIMUM = 319, // GenericOpcodes.td:1797
335 G_VECREDUCE_ADD = 320, // GenericOpcodes.td:1799
336 G_VECREDUCE_MUL = 321, // GenericOpcodes.td:1800
337 G_VECREDUCE_AND = 322, // GenericOpcodes.td:1801
338 G_VECREDUCE_OR = 323, // GenericOpcodes.td:1802
339 G_VECREDUCE_XOR = 324, // GenericOpcodes.td:1803
340 G_VECREDUCE_SMAX = 325, // GenericOpcodes.td:1804
341 G_VECREDUCE_SMIN = 326, // GenericOpcodes.td:1805
342 G_VECREDUCE_UMAX = 327, // GenericOpcodes.td:1806
343 G_VECREDUCE_UMIN = 328, // GenericOpcodes.td:1807
344 G_SBFX = 329, // GenericOpcodes.td:1901
345 G_UBFX = 330, // GenericOpcodes.td:1909
346 ADJCALLSTACKDOWN = 331, // LanaiInstrInfo.td:754
347 ADJCALLSTACKUP = 332, // LanaiInstrInfo.td:757
348 ADJDYNALLOC = 333, // LanaiInstrInfo.td:763
349 CALL = 334, // LanaiInstrInfo.td:728
350 CALLR = 335, // LanaiInstrInfo.td:729
351 ADDC_F_I_HI = 336, // LanaiInstrInfo.td:281
352 ADDC_F_I_LO = 337, // LanaiInstrInfo.td:277
353 ADDC_F_R = 338, // LanaiInstrInfo.td:293
354 ADDC_I_HI = 339, // LanaiInstrInfo.td:281
355 ADDC_I_LO = 340, // LanaiInstrInfo.td:277
356 ADDC_R = 341, // LanaiInstrInfo.td:293
357 ADD_F_I_HI = 342, // LanaiInstrInfo.td:281
358 ADD_F_I_LO = 343, // LanaiInstrInfo.td:277
359 ADD_F_R = 344, // LanaiInstrInfo.td:293
360 ADD_I_HI = 345, // LanaiInstrInfo.td:281
361 ADD_I_LO = 346, // LanaiInstrInfo.td:277
362 ADD_R = 347, // LanaiInstrInfo.td:293
363 AND_F_I_HI = 348, // LanaiInstrInfo.td:281
364 AND_F_I_LO = 349, // LanaiInstrInfo.td:277
365 AND_F_R = 350, // LanaiInstrInfo.td:306
366 AND_I_HI = 351, // LanaiInstrInfo.td:281
367 AND_I_LO = 352, // LanaiInstrInfo.td:277
368 AND_R = 353, // LanaiInstrInfo.td:306
369 BRCC = 354, // LanaiInstrInfo.td:686
370 BRIND_CC = 355, // LanaiInstrInfo.td:789
371 BRIND_CCA = 356, // LanaiInstrInfo.td:797
372 BRR = 357, // LanaiInstrInfo.td:809
373 BT = 358, // LanaiInstrInfo.td:679
374 JR = 359, // LanaiInstrInfo.td:691
375 LDADDR = 360, // LanaiInstrInfo.td:542
376 LDBs_RI = 361, // LanaiInstrInfo.td:580
377 LDBs_RR = 362, // LanaiInstrInfo.td:539
378 LDBz_RI = 363, // LanaiInstrInfo.td:577
379 LDBz_RR = 364, // LanaiInstrInfo.td:532
380 LDHs_RI = 365, // LanaiInstrInfo.td:574
381 LDHs_RR = 366, // LanaiInstrInfo.td:537
382 LDHz_RI = 367, // LanaiInstrInfo.td:571
383 LDHz_RR = 368, // LanaiInstrInfo.td:530
384 LDW_RI = 369, // LanaiInstrInfo.td:515
385 LDW_RR = 370, // LanaiInstrInfo.td:516
386 LDWz_RR = 371, // LanaiInstrInfo.td:524
387 LEADZ = 372, // LanaiInstrInfo.td:819
388 LOG0 = 373, // LanaiInstrInfo.td:249
389 LOG1 = 374, // LanaiInstrInfo.td:251
390 LOG2 = 375, // LanaiInstrInfo.td:253
391 LOG3 = 376, // LanaiInstrInfo.td:255
392 LOG4 = 377, // LanaiInstrInfo.td:257
393 MOVHI = 378, // LanaiInstrInfo.td:408
394 NOP = 379, // LanaiInstrInfo.td:245
395 OR_F_I_HI = 380, // LanaiInstrInfo.td:281
396 OR_F_I_LO = 381, // LanaiInstrInfo.td:277
397 OR_F_R = 382, // LanaiInstrInfo.td:306
398 OR_I_HI = 383, // LanaiInstrInfo.td:281
399 OR_I_LO = 384, // LanaiInstrInfo.td:277
400 OR_R = 385, // LanaiInstrInfo.td:306
401 POPC = 386, // LanaiInstrInfo.td:814
402 RET = 387, // LanaiInstrInfo.td:734
403 SA_F_I = 388, // LanaiInstrInfo.td:439
404 SA_I = 389, // LanaiInstrInfo.td:430
405 SCC = 390, // LanaiInstrInfo.td:769
406 SELECT = 391, // LanaiInstrInfo.td:776
407 SFSUB_F_RI_HI = 392, // LanaiInstrInfo.td:717
408 SFSUB_F_RI_LO = 393, // LanaiInstrInfo.td:713
409 SFSUB_F_RR = 394, // LanaiInstrInfo.td:709
410 SHL_F_R = 395, // LanaiInstrInfo.td:460
411 SHL_R = 396, // LanaiInstrInfo.td:448
412 SLI = 397, // LanaiInstrInfo.td:582
413 SL_F_I = 398, // LanaiInstrInfo.td:437
414 SL_I = 399, // LanaiInstrInfo.td:428
415 SRA_F_R = 400, // LanaiInstrInfo.td:466
416 SRA_R = 401, // LanaiInstrInfo.td:455
417 SRL_F_R = 402, // LanaiInstrInfo.td:463
418 SRL_R = 403, // LanaiInstrInfo.td:452
419 STADDR = 404, // LanaiInstrInfo.td:641
420 STB_RI = 405, // LanaiInstrInfo.td:672
421 STB_RR = 406, // LanaiInstrInfo.td:638
422 STH_RI = 407, // LanaiInstrInfo.td:669
423 STH_RR = 408, // LanaiInstrInfo.td:636
424 SUBB_F_I_HI = 409, // LanaiInstrInfo.td:281
425 SUBB_F_I_LO = 410, // LanaiInstrInfo.td:277
426 SUBB_F_R = 411, // LanaiInstrInfo.td:293
427 SUBB_I_HI = 412, // LanaiInstrInfo.td:281
428 SUBB_I_LO = 413, // LanaiInstrInfo.td:277
429 SUBB_R = 414, // LanaiInstrInfo.td:293
430 SUB_F_I_HI = 415, // LanaiInstrInfo.td:281
431 SUB_F_I_LO = 416, // LanaiInstrInfo.td:277
432 SUB_F_R = 417, // LanaiInstrInfo.td:293
433 SUB_I_HI = 418, // LanaiInstrInfo.td:281
434 SUB_I_LO = 419, // LanaiInstrInfo.td:277
435 SUB_R = 420, // LanaiInstrInfo.td:293
436 SW_RI = 421, // LanaiInstrInfo.td:631
437 SW_RR = 422, // LanaiInstrInfo.td:630
438 TRAILZ = 423, // LanaiInstrInfo.td:823
439 XOR_F_I_HI = 424, // LanaiInstrInfo.td:281
440 XOR_F_I_LO = 425, // LanaiInstrInfo.td:277
441 XOR_F_R = 426, // LanaiInstrInfo.td:306
442 XOR_I_HI = 427, // LanaiInstrInfo.td:281
443 XOR_I_LO = 428, // LanaiInstrInfo.td:277
444 XOR_R = 429, // LanaiInstrInfo.td:306
445 INSTRUCTION_LIST_END = 430
446 };
447
448} // namespace llvm::Lanai
449
450#endif // GET_INSTRINFO_ENUM
451
452#ifdef GET_INSTRINFO_SCHED_ENUM
453#undef GET_INSTRINFO_SCHED_ENUM
454
455namespace llvm::Lanai::Sched {
456
457 enum {
458 NoInstrModel = 0,
459 IIC_ALU_WriteALU = 1,
460 IIC_ALU = 2,
461 IIC_LD_WriteLD = 3,
462 IIC_LDSW_WriteLDSW = 4,
463 WriteLD = 5,
464 IIC_ST_WriteST = 6,
465 IIC_STSW_WriteSTSW = 7,
466 SCHED_LIST_END = 8
467 };
468
469} // namespace llvm::Lanai::Sched
470
471#endif // GET_INSTRINFO_SCHED_ENUM
472
473#if defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
474
475namespace llvm {
476
477struct LanaiInstrTable {
478 MCInstrDesc Insts[430];
479 static_assert(alignof(MCInstrDesc) >= alignof(MCPhysReg), "Unwanted padding between Insts and ImplicitOps");
480 MCPhysReg ImplicitOps[8];
481 char Padding[sizeof(MCOperandInfo) - sizeof ImplicitOps % sizeof(MCOperandInfo)];
482 static_assert(alignof(MCInstrDesc) >= alignof(MCOperandInfo), "Unwanted padding between Insts and OperandInfo");
483 MCOperandInfo OperandInfo[174];
484};
485} // namespace llvm
486
487#endif // defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
488
489#ifdef GET_INSTRINFO_MC_DESC
490#undef GET_INSTRINFO_MC_DESC
491
492namespace llvm {
493
494static_assert((sizeof LanaiInstrTable::ImplicitOps + sizeof LanaiInstrTable::Padding) % sizeof(MCOperandInfo) == 0);
495static constexpr unsigned LanaiOpInfoBase = (sizeof LanaiInstrTable::ImplicitOps + sizeof LanaiInstrTable::Padding) / sizeof(MCOperandInfo);
496
497extern const LanaiInstrTable LanaiDescs = {
498 {
499 { 429, 4, 1, 4, 1, 0, 0, LanaiOpInfoBase + 156, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR_R
500 { 428, 3, 1, 4, 1, 0, 0, LanaiOpInfoBase + 153, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR_I_LO
501 { 427, 3, 1, 4, 1, 0, 0, LanaiOpInfoBase + 153, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR_I_HI
502 { 426, 4, 1, 4, 1, 0, 1, LanaiOpInfoBase + 156, 6, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR_F_R
503 { 425, 3, 1, 4, 1, 0, 1, LanaiOpInfoBase + 153, 6, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR_F_I_LO
504 { 424, 3, 1, 4, 1, 0, 1, LanaiOpInfoBase + 153, 6, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR_F_I_HI
505 { 423, 2, 1, 4, 1, 0, 0, LanaiOpInfoBase + 151, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TRAILZ
506 { 422, 4, 0, 4, 6, 0, 0, LanaiOpInfoBase + 166, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SW_RR
507 { 421, 4, 0, 4, 6, 0, 0, LanaiOpInfoBase + 162, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SW_RI
508 { 420, 4, 1, 4, 1, 0, 0, LanaiOpInfoBase + 156, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_R
509 { 419, 3, 1, 4, 1, 0, 0, LanaiOpInfoBase + 153, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_I_LO
510 { 418, 3, 1, 4, 1, 0, 0, LanaiOpInfoBase + 153, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_I_HI
511 { 417, 4, 1, 4, 1, 0, 1, LanaiOpInfoBase + 156, 6, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_F_R
512 { 416, 3, 1, 4, 1, 0, 1, LanaiOpInfoBase + 153, 6, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_F_I_LO
513 { 415, 3, 1, 4, 1, 0, 1, LanaiOpInfoBase + 153, 6, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_F_I_HI
514 { 414, 4, 1, 4, 1, 1, 0, LanaiOpInfoBase + 156, 6, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBB_R
515 { 413, 3, 1, 4, 1, 1, 0, LanaiOpInfoBase + 153, 6, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBB_I_LO
516 { 412, 3, 1, 4, 1, 1, 0, LanaiOpInfoBase + 153, 6, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBB_I_HI
517 { 411, 4, 1, 4, 1, 1, 1, LanaiOpInfoBase + 156, 4, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBB_F_R
518 { 410, 3, 1, 4, 1, 1, 1, LanaiOpInfoBase + 153, 4, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBB_F_I_LO
519 { 409, 3, 1, 4, 1, 1, 1, LanaiOpInfoBase + 153, 4, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBB_F_I_HI
520 { 408, 4, 0, 4, 6, 0, 0, LanaiOpInfoBase + 166, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STH_RR
521 { 407, 4, 0, 4, 7, 0, 0, LanaiOpInfoBase + 162, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STH_RI
522 { 406, 4, 0, 4, 6, 0, 0, LanaiOpInfoBase + 166, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STB_RR
523 { 405, 4, 0, 4, 7, 0, 0, LanaiOpInfoBase + 162, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STB_RI
524 { 404, 2, 0, 4, 6, 0, 0, LanaiOpInfoBase + 34, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STADDR
525 { 403, 4, 1, 4, 1, 0, 0, LanaiOpInfoBase + 156, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SRL_R
526 { 402, 4, 1, 4, 1, 0, 1, LanaiOpInfoBase + 156, 6, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SRL_F_R
527 { 401, 4, 1, 4, 1, 0, 0, LanaiOpInfoBase + 156, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SRA_R
528 { 400, 4, 1, 4, 1, 0, 1, LanaiOpInfoBase + 156, 6, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SRA_F_R
529 { 399, 3, 1, 4, 1, 0, 0, LanaiOpInfoBase + 153, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SL_I
530 { 398, 3, 1, 4, 1, 0, 1, LanaiOpInfoBase + 153, 6, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SL_F_I
531 { 397, 2, 1, 4, 0, 0, 0, LanaiOpInfoBase + 34, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SLI
532 { 396, 4, 1, 4, 1, 0, 0, LanaiOpInfoBase + 156, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHL_R
533 { 395, 4, 1, 4, 1, 0, 1, LanaiOpInfoBase + 156, 6, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHL_F_R
534 { 394, 2, 0, 4, 1, 0, 1, LanaiOpInfoBase + 151, 6, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SFSUB_F_RR
535 { 393, 2, 0, 4, 1, 0, 1, LanaiOpInfoBase + 34, 6, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SFSUB_F_RI_LO
536 { 392, 2, 0, 4, 1, 0, 1, LanaiOpInfoBase + 34, 6, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SFSUB_F_RI_HI
537 { 391, 4, 1, 4, 1, 1, 0, LanaiOpInfoBase + 170, 6, 0|(1ULL<<MCID::Select)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SELECT
538 { 390, 2, 1, 4, 2, 1, 0, LanaiOpInfoBase + 34, 6, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SCC
539 { 389, 3, 1, 4, 1, 0, 0, LanaiOpInfoBase + 153, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SA_I
540 { 388, 3, 1, 4, 1, 0, 1, LanaiOpInfoBase + 153, 6, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SA_F_I
541 { 387, 0, 0, 4, 0, 1, 0, LanaiOpInfoBase + 1, 7, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RET
542 { 386, 2, 1, 4, 1, 0, 0, LanaiOpInfoBase + 151, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // POPC
543 { 385, 4, 1, 4, 1, 0, 0, LanaiOpInfoBase + 156, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OR_R
544 { 384, 3, 1, 4, 1, 0, 0, LanaiOpInfoBase + 153, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OR_I_LO
545 { 383, 3, 1, 4, 1, 0, 0, LanaiOpInfoBase + 153, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OR_I_HI
546 { 382, 4, 1, 4, 1, 0, 1, LanaiOpInfoBase + 156, 6, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OR_F_R
547 { 381, 3, 1, 4, 1, 0, 1, LanaiOpInfoBase + 153, 6, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OR_F_I_LO
548 { 380, 3, 1, 4, 1, 0, 1, LanaiOpInfoBase + 153, 6, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OR_F_I_HI
549 { 379, 0, 0, 4, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NOP
550 { 378, 2, 1, 4, 1, 0, 0, LanaiOpInfoBase + 34, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOVHI
551 { 377, 0, 0, 4, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOG4
552 { 376, 0, 0, 4, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOG3
553 { 375, 0, 0, 4, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOG2
554 { 374, 0, 0, 4, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOG1
555 { 373, 0, 0, 4, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOG0
556 { 372, 2, 1, 4, 1, 0, 0, LanaiOpInfoBase + 151, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LEADZ
557 { 371, 4, 1, 4, 5, 0, 0, LanaiOpInfoBase + 166, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDWz_RR
558 { 370, 4, 1, 4, 5, 0, 0, LanaiOpInfoBase + 166, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDW_RR
559 { 369, 4, 1, 4, 3, 0, 0, LanaiOpInfoBase + 162, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDW_RI
560 { 368, 4, 1, 4, 5, 0, 0, LanaiOpInfoBase + 166, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDHz_RR
561 { 367, 4, 1, 4, 4, 0, 0, LanaiOpInfoBase + 162, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDHz_RI
562 { 366, 4, 1, 4, 5, 0, 0, LanaiOpInfoBase + 166, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDHs_RR
563 { 365, 4, 1, 4, 4, 0, 0, LanaiOpInfoBase + 162, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDHs_RI
564 { 364, 4, 1, 4, 5, 0, 0, LanaiOpInfoBase + 166, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDBz_RR
565 { 363, 4, 1, 4, 4, 0, 0, LanaiOpInfoBase + 162, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDBz_RI
566 { 362, 4, 1, 4, 5, 0, 0, LanaiOpInfoBase + 166, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDBs_RR
567 { 361, 4, 1, 4, 4, 0, 0, LanaiOpInfoBase + 162, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDBs_RI
568 { 360, 2, 1, 4, 3, 0, 0, LanaiOpInfoBase + 34, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDADDR
569 { 359, 1, 0, 4, 1, 0, 0, LanaiOpInfoBase + 28, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JR
570 { 358, 1, 0, 4, 2, 0, 0, LanaiOpInfoBase + 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BT
571 { 357, 2, 0, 4, 0, 1, 0, LanaiOpInfoBase + 160, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BRR
572 { 356, 3, 0, 4, 1, 1, 0, LanaiOpInfoBase + 153, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BRIND_CCA
573 { 355, 2, 0, 4, 1, 1, 0, LanaiOpInfoBase + 34, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BRIND_CC
574 { 354, 2, 0, 4, 2, 1, 0, LanaiOpInfoBase + 9, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BRCC
575 { 353, 4, 1, 4, 1, 0, 0, LanaiOpInfoBase + 156, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND_R
576 { 352, 3, 1, 4, 1, 0, 0, LanaiOpInfoBase + 153, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND_I_LO
577 { 351, 3, 1, 4, 1, 0, 0, LanaiOpInfoBase + 153, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND_I_HI
578 { 350, 4, 1, 4, 1, 0, 1, LanaiOpInfoBase + 156, 6, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND_F_R
579 { 349, 3, 1, 4, 1, 0, 1, LanaiOpInfoBase + 153, 6, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND_F_I_LO
580 { 348, 3, 1, 4, 1, 0, 1, LanaiOpInfoBase + 153, 6, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND_F_I_HI
581 { 347, 4, 1, 4, 1, 0, 0, LanaiOpInfoBase + 156, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_R
582 { 346, 3, 1, 4, 1, 0, 0, LanaiOpInfoBase + 153, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_I_LO
583 { 345, 3, 1, 4, 1, 0, 0, LanaiOpInfoBase + 153, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_I_HI
584 { 344, 4, 1, 4, 1, 0, 1, LanaiOpInfoBase + 156, 6, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_F_R
585 { 343, 3, 1, 4, 1, 0, 1, LanaiOpInfoBase + 153, 6, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_F_I_LO
586 { 342, 3, 1, 4, 1, 0, 1, LanaiOpInfoBase + 153, 6, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_F_I_HI
587 { 341, 4, 1, 4, 1, 1, 0, LanaiOpInfoBase + 156, 6, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC_R
588 { 340, 3, 1, 4, 1, 1, 0, LanaiOpInfoBase + 153, 6, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC_I_LO
589 { 339, 3, 1, 4, 1, 1, 0, LanaiOpInfoBase + 153, 6, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC_I_HI
590 { 338, 4, 1, 4, 1, 1, 1, LanaiOpInfoBase + 156, 4, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC_F_R
591 { 337, 3, 1, 4, 1, 1, 1, LanaiOpInfoBase + 153, 4, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC_F_I_LO
592 { 336, 3, 1, 4, 1, 1, 1, LanaiOpInfoBase + 153, 4, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC_F_I_HI
593 { 335, 1, 0, 4, 0, 1, 1, LanaiOpInfoBase + 28, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CALLR
594 { 334, 1, 0, 4, 0, 1, 1, LanaiOpInfoBase + 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CALL
595 { 333, 2, 1, 4, 0, 1, 1, LanaiOpInfoBase + 151, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADJDYNALLOC
596 { 332, 2, 0, 4, 0, 1, 1, LanaiOpInfoBase + 20, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADJCALLSTACKUP
597 { 331, 2, 0, 4, 0, 1, 1, LanaiOpInfoBase + 20, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADJCALLSTACKDOWN
598 { 330, 4, 1, 0, 0, 0, 0, LanaiOpInfoBase + 147, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UBFX
599 { 329, 4, 1, 0, 0, 0, 0, LanaiOpInfoBase + 147, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SBFX
600 { 328, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_UMIN
601 { 327, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_UMAX
602 { 326, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SMIN
603 { 325, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SMAX
604 { 324, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_XOR
605 { 323, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_OR
606 { 322, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_AND
607 { 321, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_MUL
608 { 320, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_ADD
609 { 319, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMINIMUM
610 { 318, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMAXIMUM
611 { 317, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMIN
612 { 316, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMAX
613 { 315, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMUL
614 { 314, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FADD
615 { 313, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SEQ_FMUL
616 { 312, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SEQ_FADD
617 { 311, 1, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UBSANTRAP
618 { 310, 0, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_DEBUGTRAP
619 { 309, 0, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRAP
620 { 308, 3, 0, 0, 0, 0, 0, LanaiOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMSET_INLINE
621 { 307, 3, 0, 0, 0, 0, 0, LanaiOpInfoBase + 57, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BZERO
622 { 306, 4, 0, 0, 0, 0, 0, LanaiOpInfoBase + 143, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMSET
623 { 305, 4, 0, 0, 0, 0, 0, LanaiOpInfoBase + 143, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMMOVE
624 { 304, 3, 0, 0, 0, 0, 0, LanaiOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMCPY_INLINE
625 { 303, 4, 0, 0, 0, 0, 0, LanaiOpInfoBase + 143, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMCPY
626 { 302, 2, 0, 0, 0, 0, 0, LanaiOpInfoBase + 141, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_WRITE_REGISTER
627 { 301, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_READ_REGISTER
628 { 300, 4, 1, 0, 0, 0, 0, LanaiOpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FCMPS
629 { 299, 4, 1, 0, 0, 0, 0, LanaiOpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FCMP
630 { 298, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FLDEXP
631 { 297, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FSQRT
632 { 296, 4, 1, 0, 0, 0, 0, LanaiOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FMA
633 { 295, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FREM
634 { 294, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FDIV
635 { 293, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FMUL
636 { 292, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FSUB
637 { 291, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FADD
638 { 290, 1, 0, 0, 0, 0, 0, LanaiOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STACKRESTORE
639 { 289, 1, 1, 0, 0, 0, 0, LanaiOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STACKSAVE
640 { 288, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 68, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_DYN_STACKALLOC
641 { 287, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_JUMP_TABLE
642 { 286, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BLOCK_ADDR
643 { 285, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ADDRSPACE_CAST
644 { 284, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FNEARBYINT
645 { 283, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FRINT
646 { 282, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FFLOOR
647 { 281, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSQRT
648 { 280, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FTANH
649 { 279, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSINH
650 { 278, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCOSH
651 { 277, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FATAN2
652 { 276, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FATAN
653 { 275, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FASIN
654 { 274, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FACOS
655 { 273, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FTAN
656 { 272, 3, 2, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSINCOS
657 { 271, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSIN
658 { 270, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCOS
659 { 269, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCEIL
660 { 268, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CLMUL
661 { 267, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BITREVERSE
662 { 266, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BSWAP
663 { 265, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTPOP
664 { 264, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTLS
665 { 263, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTLZ_ZERO_POISON
666 { 262, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTLZ
667 { 261, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTTZ_ZERO_POISON
668 { 260, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTTZ
669 { 259, 4, 1, 0, 0, 0, 0, LanaiOpInfoBase + 137, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECTOR_COMPRESS
670 { 258, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STEP_VECTOR
671 { 257, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SPLAT_VECTOR
672 { 256, 4, 1, 0, 0, 0, 0, LanaiOpInfoBase + 133, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SHUFFLE_VECTOR
673 { 255, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_EXTRACT_VECTOR_ELT
674 { 254, 4, 1, 0, 0, 0, 0, LanaiOpInfoBase + 126, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INSERT_VECTOR_ELT
675 { 253, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 57, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_EXTRACT_SUBVECTOR
676 { 252, 4, 1, 0, 0, 0, 0, LanaiOpInfoBase + 62, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INSERT_SUBVECTOR
677 { 251, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VSCALE
678 { 250, 3, 0, 0, 0, 0, 0, LanaiOpInfoBase + 123, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BRJT
679 { 249, 1, 0, 0, 0, 0, 0, LanaiOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BR
680 { 248, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LLROUND
681 { 247, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LROUND
682 { 246, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ABS
683 { 245, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMAX
684 { 244, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMIN
685 { 243, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMAX
686 { 242, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMIN
687 { 241, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTRMASK
688 { 240, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTR_ADD
689 { 239, 1, 0, 0, 0, 0, 0, LanaiOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SET_ROUNDING
690 { 238, 1, 1, 0, 0, 0, 0, LanaiOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GET_ROUNDING
691 { 237, 0, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_RESET_FPMODE
692 { 236, 1, 0, 0, 0, 0, 0, LanaiOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SET_FPMODE
693 { 235, 1, 1, 0, 0, 0, 0, LanaiOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GET_FPMODE
694 { 234, 0, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_RESET_FPENV
695 { 233, 1, 0, 0, 0, 0, 0, LanaiOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SET_FPENV
696 { 232, 1, 1, 0, 0, 0, 0, LanaiOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GET_FPENV
697 { 231, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXIMUMNUM
698 { 230, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINIMUMNUM
699 { 229, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXIMUM
700 { 228, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINIMUM
701 { 227, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXNUM_IEEE
702 { 226, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINNUM_IEEE
703 { 225, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXNUM
704 { 224, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINNUM
705 { 223, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCANONICALIZE
706 { 222, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 97, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_IS_FPCLASS
707 { 221, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCOPYSIGN
708 { 220, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FABS
709 { 219, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOUI_SAT
710 { 218, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOSI_SAT
711 { 217, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UITOFP
712 { 216, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SITOFP
713 { 215, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOUI
714 { 214, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOSI
715 { 213, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTRUNC
716 { 212, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPEXT
717 { 211, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FNEG
718 { 210, 3, 2, 0, 0, 0, 0, LanaiOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FFREXP
719 { 209, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLDEXP
720 { 208, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLOG10
721 { 207, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLOG2
722 { 206, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLOG
723 { 205, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FEXP10
724 { 204, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FEXP2
725 { 203, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FEXP
726 { 202, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPOWI
727 { 201, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPOW
728 { 200, 3, 2, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMODF
729 { 199, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FREM
730 { 198, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FDIV
731 { 197, 4, 1, 0, 0, 0, 0, LanaiOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAD
732 { 196, 4, 1, 0, 0, 0, 0, LanaiOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMA
733 { 195, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMUL
734 { 194, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSUB
735 { 193, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FADD
736 { 192, 4, 1, 0, 0, 0, 0, LanaiOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIVFIXSAT
737 { 191, 4, 1, 0, 0, 0, 0, LanaiOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIVFIXSAT
738 { 190, 4, 1, 0, 0, 0, 0, LanaiOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIVFIX
739 { 189, 4, 1, 0, 0, 0, 0, LanaiOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIVFIX
740 { 188, 4, 1, 0, 0, 0, 0, LanaiOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULFIXSAT
741 { 187, 4, 1, 0, 0, 0, 0, LanaiOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULFIXSAT
742 { 186, 4, 1, 0, 0, 0, 0, LanaiOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULFIX
743 { 185, 4, 1, 0, 0, 0, 0, LanaiOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULFIX
744 { 184, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSHLSAT
745 { 183, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USHLSAT
746 { 182, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSUBSAT
747 { 181, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USUBSAT
748 { 180, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SADDSAT
749 { 179, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UADDSAT
750 { 178, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULH
751 { 177, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULH
752 { 176, 4, 2, 0, 0, 0, 0, LanaiOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULO
753 { 175, 4, 2, 0, 0, 0, 0, LanaiOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULO
754 { 174, 5, 2, 0, 0, 0, 0, LanaiOpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSUBE
755 { 173, 4, 2, 0, 0, 0, 0, LanaiOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSUBO
756 { 172, 5, 2, 0, 0, 0, 0, LanaiOpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SADDE
757 { 171, 4, 2, 0, 0, 0, 0, LanaiOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SADDO
758 { 170, 5, 2, 0, 0, 0, 0, LanaiOpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USUBE
759 { 169, 4, 2, 0, 0, 0, 0, LanaiOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USUBO
760 { 168, 5, 2, 0, 0, 0, 0, LanaiOpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UADDE
761 { 167, 4, 2, 0, 0, 0, 0, LanaiOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UADDO
762 { 166, 4, 1, 0, 0, 0, 0, LanaiOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SELECT
763 { 165, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 111, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UCMP
764 { 164, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 111, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SCMP
765 { 163, 4, 1, 0, 0, 0, 0, LanaiOpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCMP
766 { 162, 4, 1, 0, 0, 0, 0, LanaiOpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ICMP
767 { 161, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ROTL
768 { 160, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ROTR
769 { 159, 4, 1, 0, 0, 0, 0, LanaiOpInfoBase + 103, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSHR
770 { 158, 4, 1, 0, 0, 0, 0, LanaiOpInfoBase + 103, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSHL
771 { 157, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASHR
772 { 156, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LSHR
773 { 155, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SHL
774 { 154, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ZEXT
775 { 153, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SEXT_INREG
776 { 152, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SEXT
777 { 151, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 97, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VAARG
778 { 150, 1, 0, 0, 0, 0, 0, LanaiOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VASTART
779 { 149, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCONSTANT
780 { 148, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONSTANT
781 { 147, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC_USAT_U
782 { 146, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC_SSAT_U
783 { 145, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC_SSAT_S
784 { 144, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC
785 { 143, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ANYEXT
786 { 142, 1, 0, 0, 0, 0, 0, LanaiOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
787 { 141, 1, 0, 0, 0, 0, 0, LanaiOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_INTRINSIC_CONVERGENT
788 { 140, 1, 0, 0, 0, 0, 0, LanaiOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_W_SIDE_EFFECTS
789 { 139, 1, 0, 0, 0, 0, 0, LanaiOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC
790 { 138, 0, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INVOKE_REGION_START
791 { 137, 1, 0, 0, 0, 0, 0, LanaiOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BRINDIRECT
792 { 136, 2, 0, 0, 0, 0, 0, LanaiOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BRCOND
793 { 135, 4, 0, 0, 0, 0, 0, LanaiOpInfoBase + 93, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PREFETCH
794 { 134, 2, 0, 0, 0, 0, 0, LanaiOpInfoBase + 20, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FENCE
795 { 133, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_USUB_SAT
796 { 132, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_USUB_COND
797 { 131, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UDEC_WRAP
798 { 130, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UINC_WRAP
799 { 129, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMINIMUMNUM
800 { 128, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMAXIMUMNUM
801 { 127, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMINIMUM
802 { 126, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMAXIMUM
803 { 125, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMIN
804 { 124, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMAX
805 { 123, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FSUB
806 { 122, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FADD
807 { 121, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UMIN
808 { 120, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UMAX
809 { 119, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_MIN
810 { 118, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_MAX
811 { 117, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_XOR
812 { 116, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_OR
813 { 115, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_NAND
814 { 114, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_AND
815 { 113, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_SUB
816 { 112, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_ADD
817 { 111, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_XCHG
818 { 110, 4, 1, 0, 0, 0, 0, LanaiOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMIC_CMPXCHG
819 { 109, 5, 2, 0, 0, 0, 0, LanaiOpInfoBase + 81, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
820 { 108, 5, 1, 0, 0, 0, 0, LanaiOpInfoBase + 76, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_STORE
821 { 107, 2, 0, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTRUNCSTORE
822 { 106, 2, 0, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STORE
823 { 105, 5, 2, 0, 0, 0, 0, LanaiOpInfoBase + 71, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_ZEXTLOAD
824 { 104, 5, 2, 0, 0, 0, 0, LanaiOpInfoBase + 71, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_SEXTLOAD
825 { 103, 5, 2, 0, 0, 0, 0, LanaiOpInfoBase + 71, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_LOAD
826 { 102, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPEXTLOAD
827 { 101, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ZEXTLOAD
828 { 100, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SEXTLOAD
829 { 99, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LOAD
830 { 98, 1, 1, 0, 0, 0, 0, LanaiOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_READSTEADYCOUNTER
831 { 97, 1, 1, 0, 0, 0, 0, LanaiOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_READCYCLECOUNTER
832 { 96, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_ROUNDEVEN
833 { 95, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_LLRINT
834 { 94, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_LRINT
835 { 93, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_ROUND
836 { 92, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_TRUNC
837 { 91, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 68, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_FPTRUNC_ROUND
838 { 90, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONSTANT_FOLD_BARRIER
839 { 89, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FREEZE
840 { 88, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BITCAST
841 { 87, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTTOPTR
842 { 86, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTRTOINT
843 { 85, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONCAT_VECTORS
844 { 84, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BUILD_VECTOR_TRUNC
845 { 83, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BUILD_VECTOR
846 { 82, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MERGE_VALUES
847 { 81, 4, 1, 0, 0, 0, 0, LanaiOpInfoBase + 62, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INSERT
848 { 80, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UNMERGE_VALUES
849 { 79, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 57, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_EXTRACT
850 { 78, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONSTANT_POOL
851 { 77, 5, 1, 0, 0, 0, 0, LanaiOpInfoBase + 52, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTRAUTH_GLOBAL_VALUE
852 { 76, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GLOBAL_VALUE
853 { 75, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FRAME_INDEX
854 { 74, 1, 1, 0, 0, 0, 0, LanaiOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PHI
855 { 73, 1, 1, 0, 0, 0, 0, LanaiOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_IMPLICIT_DEF
856 { 72, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SAVGCEIL
857 { 71, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SAVGFLOOR
858 { 70, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UAVGCEIL
859 { 69, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UAVGFLOOR
860 { 68, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ABDU
861 { 67, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ABDS
862 { 66, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_XOR
863 { 65, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_OR
864 { 64, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_AND
865 { 63, 4, 2, 0, 0, 0, 0, LanaiOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIVREM
866 { 62, 4, 2, 0, 0, 0, 0, LanaiOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIVREM
867 { 61, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UREM
868 { 60, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SREM
869 { 59, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIV
870 { 58, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIV
871 { 57, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MUL
872 { 56, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SUB
873 { 55, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ADD
874 { 54, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASSERT_ALIGN
875 { 53, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASSERT_ZEXT
876 { 52, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASSERT_SEXT
877 { 51, 1, 0, 0, 0, 0, 0, LanaiOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_GLUE
878 { 50, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_LOOP
879 { 49, 1, 1, 0, 0, 0, 0, LanaiOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_ANCHOR
880 { 48, 1, 1, 0, 0, 0, 0, LanaiOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_ENTRY
881 { 47, 1, 0, 0, 0, 0, 0, LanaiOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RELOC_NONE
882 { 46, 1, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JUMP_TABLE_DEBUG_INFO
883 { 45, 0, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMBARRIER
884 { 44, 0, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FAKE_USE
885 { 43, 0, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ICALL_BRANCH_FUNNEL
886 { 42, 3, 0, 0, 0, 0, 0, LanaiOpInfoBase + 36, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_13917
887 { 41, 2, 0, 0, 0, 0, 0, LanaiOpInfoBase + 34, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_13916
888 { 40, 0, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_TAIL_CALL
889 { 39, 0, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_FUNCTION_EXIT
890 { 38, 0, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_RET
891 { 37, 0, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_FUNCTION_ENTER
892 { 36, 0, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_OP
893 { 35, 1, 1, 0, 0, 0, 0, LanaiOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FAULTING_OP
894 { 34, 2, 0, 0, 0, 0, 0, LanaiOpInfoBase + 32, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_ESCAPE
895 { 33, 0, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STATEPOINT
896 { 32, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 29, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_13915
897 { 31, 1, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PREALLOCATED_SETUP
898 { 30, 1, 1, 0, 0, 0, 0, LanaiOpInfoBase + 28, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_13555
899 { 29, 6, 1, 0, 0, 0, 0, LanaiOpInfoBase + 22, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHPOINT
900 { 28, 0, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FENTRY_CALL
901 { 27, 2, 0, 0, 0, 0, 0, LanaiOpInfoBase + 20, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STACKMAP
902 { 26, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 18, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARITH_FENCE
903 { 25, 4, 0, 0, 0, 0, 0, LanaiOpInfoBase + 14, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PSEUDO_PROBE
904 { 24, 1, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LIFETIME_END
905 { 23, 1, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LIFETIME_START
906 { 22, 0, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BUNDLE
907 { 21, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 11, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_LANEMASK
908 { 20, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY
909 { 19, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REG_SEQUENCE
910 { 18, 1, 0, 0, 0, 0, 0, LanaiOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_LABEL
911 { 17, 0, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_PHI
912 { 16, 0, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_INSTR_REF
913 { 15, 0, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_VALUE_LIST
914 { 14, 0, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_VALUE
915 { 13, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_TO_REGCLASS
916 { 12, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBREG_TO_REG
917 { 11, 1, 1, 0, 0, 0, 0, LanaiOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INIT_UNDEF
918 { 10, 1, 1, 0, 0, 0, 0, LanaiOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // IMPLICIT_DEF
919 { 9, 4, 1, 0, 0, 0, 0, LanaiOpInfoBase + 5, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INSERT_SUBREG
920 { 8, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTRACT_SUBREG
921 { 7, 0, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // KILL
922 { 6, 1, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ANNOTATION_LABEL
923 { 5, 1, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GC_LABEL
924 { 4, 1, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EH_LABEL
925 { 3, 1, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CFI_INSTRUCTION
926 { 2, 0, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INLINEASM_BR
927 { 1, 0, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INLINEASM
928 { 0, 1, 1, 0, 0, 0, 0, LanaiOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PHI
929 }, {
930 /* 0 */
931 /* 0 */ Lanai::SP, Lanai::SP,
932 /* 2 */ Lanai::SP, Lanai::RCA,
933 /* 4 */ Lanai::SR, Lanai::SR,
934 /* 6 */ Lanai::SR,
935 /* 7 */ Lanai::RCA,
936 }, {
937 0
938 }, {
939 /* 0 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
940 /* 1 */
941 /* 1 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
942 /* 2 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
943 /* 5 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
944 /* 9 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
945 /* 11 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
946 /* 14 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
947 /* 18 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) },
948 /* 20 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
949 /* 22 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
950 /* 28 */ { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
951 /* 29 */ { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
952 /* 32 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
953 /* 34 */ { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
954 /* 36 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
955 /* 39 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
956 /* 42 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
957 /* 45 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
958 /* 49 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
959 /* 50 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
960 /* 52 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
961 /* 57 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
962 /* 60 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
963 /* 62 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
964 /* 66 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
965 /* 68 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
966 /* 71 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
967 /* 76 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
968 /* 81 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
969 /* 86 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
970 /* 90 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
971 /* 93 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
972 /* 97 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
973 /* 100 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
974 /* 103 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
975 /* 107 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
976 /* 111 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
977 /* 114 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
978 /* 119 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
979 /* 123 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
980 /* 126 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
981 /* 130 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
982 /* 133 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
983 /* 137 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
984 /* 141 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
985 /* 143 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
986 /* 147 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
987 /* 151 */ { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
988 /* 153 */ { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
989 /* 156 */ { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 },
990 /* 160 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
991 /* 162 */ { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
992 /* 166 */ { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
993 /* 170 */ { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
994 }
995};
996
997
998#ifdef __GNUC__
999#pragma GCC diagnostic push
1000#pragma GCC diagnostic ignored "-Woverlength-strings"
1001#endif
1002extern const char LanaiInstrNameData[] = {
1003 /* 0 */ "G_FLOG10\000"
1004 /* 9 */ "G_FEXP10\000"
1005 /* 18 */ "LOG0\000"
1006 /* 23 */ "LOG1\000"
1007 /* 28 */ "G_FLOG2\000"
1008 /* 36 */ "G_FATAN2\000"
1009 /* 45 */ "G_FEXP2\000"
1010 /* 53 */ "LOG3\000"
1011 /* 58 */ "LOG4\000"
1012 /* 63 */ "BRIND_CCA\000"
1013 /* 73 */ "G_FMA\000"
1014 /* 79 */ "G_STRICT_FMA\000"
1015 /* 92 */ "G_FSUB\000"
1016 /* 99 */ "G_STRICT_FSUB\000"
1017 /* 113 */ "G_ATOMICRMW_FSUB\000"
1018 /* 130 */ "G_SUB\000"
1019 /* 136 */ "G_ATOMICRMW_SUB\000"
1020 /* 152 */ "BRCC\000"
1021 /* 157 */ "SCC\000"
1022 /* 161 */ "BRIND_CC\000"
1023 /* 170 */ "G_INTRINSIC\000"
1024 /* 182 */ "G_FPTRUNC\000"
1025 /* 192 */ "G_INTRINSIC_TRUNC\000"
1026 /* 210 */ "G_TRUNC\000"
1027 /* 218 */ "G_BUILD_VECTOR_TRUNC\000"
1028 /* 239 */ "G_DYN_STACKALLOC\000"
1029 /* 256 */ "ADJDYNALLOC\000"
1030 /* 268 */ "POPC\000"
1031 /* 273 */ "G_FMAD\000"
1032 /* 280 */ "G_FPEXTLOAD\000"
1033 /* 292 */ "G_INDEXED_SEXTLOAD\000"
1034 /* 311 */ "G_SEXTLOAD\000"
1035 /* 322 */ "G_INDEXED_ZEXTLOAD\000"
1036 /* 341 */ "G_ZEXTLOAD\000"
1037 /* 352 */ "G_INDEXED_LOAD\000"
1038 /* 367 */ "G_LOAD\000"
1039 /* 374 */ "G_VECREDUCE_FADD\000"
1040 /* 391 */ "G_FADD\000"
1041 /* 398 */ "G_VECREDUCE_SEQ_FADD\000"
1042 /* 419 */ "G_STRICT_FADD\000"
1043 /* 433 */ "G_ATOMICRMW_FADD\000"
1044 /* 450 */ "G_VECREDUCE_ADD\000"
1045 /* 466 */ "G_ADD\000"
1046 /* 472 */ "G_PTR_ADD\000"
1047 /* 482 */ "G_ATOMICRMW_ADD\000"
1048 /* 498 */ "G_ATOMICRMW_NAND\000"
1049 /* 515 */ "G_VECREDUCE_AND\000"
1050 /* 531 */ "G_AND\000"
1051 /* 537 */ "G_ATOMICRMW_AND\000"
1052 /* 553 */ "LIFETIME_END\000"
1053 /* 566 */ "G_BRCOND\000"
1054 /* 575 */ "G_ATOMICRMW_USUB_COND\000"
1055 /* 597 */ "G_LLROUND\000"
1056 /* 607 */ "G_LROUND\000"
1057 /* 616 */ "G_INTRINSIC_ROUND\000"
1058 /* 634 */ "G_INTRINSIC_FPTRUNC_ROUND\000"
1059 /* 660 */ "LOAD_STACK_GUARD\000"
1060 /* 677 */ "PSEUDO_PROBE\000"
1061 /* 690 */ "G_SSUBE\000"
1062 /* 698 */ "G_USUBE\000"
1063 /* 706 */ "G_FENCE\000"
1064 /* 714 */ "ARITH_FENCE\000"
1065 /* 726 */ "REG_SEQUENCE\000"
1066 /* 739 */ "G_SADDE\000"
1067 /* 747 */ "G_UADDE\000"
1068 /* 755 */ "G_GET_FPMODE\000"
1069 /* 768 */ "G_RESET_FPMODE\000"
1070 /* 783 */ "G_SET_FPMODE\000"
1071 /* 796 */ "G_FMINNUM_IEEE\000"
1072 /* 811 */ "G_FMAXNUM_IEEE\000"
1073 /* 826 */ "G_VSCALE\000"
1074 /* 835 */ "G_JUMP_TABLE\000"
1075 /* 848 */ "BUNDLE\000"
1076 /* 855 */ "G_MEMSET_INLINE\000"
1077 /* 871 */ "G_MEMCPY_INLINE\000"
1078 /* 887 */ "RELOC_NONE\000"
1079 /* 898 */ "LOCAL_ESCAPE\000"
1080 /* 911 */ "G_FPTRUNCSTORE\000"
1081 /* 926 */ "G_STACKRESTORE\000"
1082 /* 941 */ "G_INDEXED_STORE\000"
1083 /* 957 */ "G_STORE\000"
1084 /* 965 */ "G_BITREVERSE\000"
1085 /* 978 */ "FAKE_USE\000"
1086 /* 987 */ "DBG_VALUE\000"
1087 /* 997 */ "G_GLOBAL_VALUE\000"
1088 /* 1012 */ "G_PTRAUTH_GLOBAL_VALUE\000"
1089 /* 1035 */ "CONVERGENCECTRL_GLUE\000"
1090 /* 1056 */ "G_STACKSAVE\000"
1091 /* 1068 */ "G_MEMMOVE\000"
1092 /* 1078 */ "G_FREEZE\000"
1093 /* 1087 */ "G_FCANONICALIZE\000"
1094 /* 1103 */ "G_FMODF\000"
1095 /* 1111 */ "INIT_UNDEF\000"
1096 /* 1122 */ "G_IMPLICIT_DEF\000"
1097 /* 1137 */ "DBG_INSTR_REF\000"
1098 /* 1151 */ "G_FNEG\000"
1099 /* 1158 */ "EXTRACT_SUBREG\000"
1100 /* 1173 */ "INSERT_SUBREG\000"
1101 /* 1187 */ "G_SEXT_INREG\000"
1102 /* 1200 */ "SUBREG_TO_REG\000"
1103 /* 1214 */ "G_ATOMIC_CMPXCHG\000"
1104 /* 1231 */ "G_ATOMICRMW_XCHG\000"
1105 /* 1248 */ "G_GET_ROUNDING\000"
1106 /* 1263 */ "G_SET_ROUNDING\000"
1107 /* 1278 */ "G_FLOG\000"
1108 /* 1285 */ "G_VAARG\000"
1109 /* 1293 */ "PREALLOCATED_ARG\000"
1110 /* 1310 */ "G_PREFETCH\000"
1111 /* 1321 */ "G_SMULH\000"
1112 /* 1329 */ "G_UMULH\000"
1113 /* 1337 */ "G_FTANH\000"
1114 /* 1345 */ "G_FSINH\000"
1115 /* 1353 */ "G_FCOSH\000"
1116 /* 1361 */ "DBG_PHI\000"
1117 /* 1369 */ "MOVHI\000"
1118 /* 1375 */ "SFSUB_F_RI_HI\000"
1119 /* 1389 */ "SUBB_I_HI\000"
1120 /* 1399 */ "SUB_I_HI\000"
1121 /* 1408 */ "ADDC_I_HI\000"
1122 /* 1418 */ "ADD_I_HI\000"
1123 /* 1427 */ "AND_I_HI\000"
1124 /* 1436 */ "SUBB_F_I_HI\000"
1125 /* 1448 */ "SUB_F_I_HI\000"
1126 /* 1459 */ "ADDC_F_I_HI\000"
1127 /* 1471 */ "ADD_F_I_HI\000"
1128 /* 1482 */ "AND_F_I_HI\000"
1129 /* 1493 */ "XOR_F_I_HI\000"
1130 /* 1504 */ "XOR_I_HI\000"
1131 /* 1513 */ "SLI\000"
1132 /* 1517 */ "STB_RI\000"
1133 /* 1524 */ "STH_RI\000"
1134 /* 1531 */ "LDW_RI\000"
1135 /* 1538 */ "SW_RI\000"
1136 /* 1544 */ "LDBs_RI\000"
1137 /* 1552 */ "LDHs_RI\000"
1138 /* 1560 */ "LDBz_RI\000"
1139 /* 1568 */ "LDHz_RI\000"
1140 /* 1576 */ "G_FPTOSI\000"
1141 /* 1585 */ "G_FPTOUI\000"
1142 /* 1594 */ "G_FPOWI\000"
1143 /* 1602 */ "SA_I\000"
1144 /* 1607 */ "SA_F_I\000"
1145 /* 1614 */ "SL_F_I\000"
1146 /* 1621 */ "SL_I\000"
1147 /* 1626 */ "COPY_LANEMASK\000"
1148 /* 1640 */ "G_PTRMASK\000"
1149 /* 1650 */ "GC_LABEL\000"
1150 /* 1659 */ "DBG_LABEL\000"
1151 /* 1669 */ "EH_LABEL\000"
1152 /* 1678 */ "ANNOTATION_LABEL\000"
1153 /* 1695 */ "ICALL_BRANCH_FUNNEL\000"
1154 /* 1715 */ "G_FSHL\000"
1155 /* 1722 */ "G_SHL\000"
1156 /* 1728 */ "G_FCEIL\000"
1157 /* 1736 */ "G_SAVGCEIL\000"
1158 /* 1747 */ "G_UAVGCEIL\000"
1159 /* 1758 */ "PATCHABLE_TAIL_CALL\000"
1160 /* 1778 */ "PATCHABLE_TYPED_EVENT_CALL\000"
1161 /* 1805 */ "PATCHABLE_EVENT_CALL\000"
1162 /* 1826 */ "FENTRY_CALL\000"
1163 /* 1838 */ "KILL\000"
1164 /* 1843 */ "G_CONSTANT_POOL\000"
1165 /* 1859 */ "G_ROTL\000"
1166 /* 1866 */ "G_VECREDUCE_FMUL\000"
1167 /* 1883 */ "G_FMUL\000"
1168 /* 1890 */ "G_VECREDUCE_SEQ_FMUL\000"
1169 /* 1911 */ "G_STRICT_FMUL\000"
1170 /* 1925 */ "G_CLMUL\000"
1171 /* 1933 */ "G_VECREDUCE_MUL\000"
1172 /* 1949 */ "G_MUL\000"
1173 /* 1955 */ "G_FREM\000"
1174 /* 1962 */ "G_STRICT_FREM\000"
1175 /* 1976 */ "G_SREM\000"
1176 /* 1983 */ "G_UREM\000"
1177 /* 1990 */ "G_SDIVREM\000"
1178 /* 2000 */ "G_UDIVREM\000"
1179 /* 2010 */ "INLINEASM\000"
1180 /* 2020 */ "G_VECREDUCE_FMINIMUM\000"
1181 /* 2041 */ "G_FMINIMUM\000"
1182 /* 2052 */ "G_ATOMICRMW_FMINIMUM\000"
1183 /* 2073 */ "G_VECREDUCE_FMAXIMUM\000"
1184 /* 2094 */ "G_FMAXIMUM\000"
1185 /* 2105 */ "G_ATOMICRMW_FMAXIMUM\000"
1186 /* 2126 */ "G_FMINIMUMNUM\000"
1187 /* 2140 */ "G_ATOMICRMW_FMINIMUMNUM\000"
1188 /* 2164 */ "G_FMAXIMUMNUM\000"
1189 /* 2178 */ "G_ATOMICRMW_FMAXIMUMNUM\000"
1190 /* 2202 */ "G_FMINNUM\000"
1191 /* 2212 */ "G_FMAXNUM\000"
1192 /* 2222 */ "G_FATAN\000"
1193 /* 2230 */ "G_FTAN\000"
1194 /* 2237 */ "G_INTRINSIC_ROUNDEVEN\000"
1195 /* 2259 */ "G_ASSERT_ALIGN\000"
1196 /* 2274 */ "G_FCOPYSIGN\000"
1197 /* 2286 */ "G_VECREDUCE_FMIN\000"
1198 /* 2303 */ "G_ATOMICRMW_FMIN\000"
1199 /* 2320 */ "G_VECREDUCE_SMIN\000"
1200 /* 2337 */ "G_SMIN\000"
1201 /* 2344 */ "G_VECREDUCE_UMIN\000"
1202 /* 2361 */ "G_UMIN\000"
1203 /* 2368 */ "G_ATOMICRMW_UMIN\000"
1204 /* 2385 */ "G_ATOMICRMW_MIN\000"
1205 /* 2401 */ "G_FASIN\000"
1206 /* 2409 */ "G_FSIN\000"
1207 /* 2416 */ "CFI_INSTRUCTION\000"
1208 /* 2432 */ "G_CTLZ_ZERO_POISON\000"
1209 /* 2451 */ "G_CTTZ_ZERO_POISON\000"
1210 /* 2470 */ "ADJCALLSTACKDOWN\000"
1211 /* 2487 */ "G_SSUBO\000"
1212 /* 2495 */ "G_USUBO\000"
1213 /* 2503 */ "G_SADDO\000"
1214 /* 2511 */ "G_UADDO\000"
1215 /* 2519 */ "JUMP_TABLE_DEBUG_INFO\000"
1216 /* 2541 */ "G_SMULO\000"
1217 /* 2549 */ "G_UMULO\000"
1218 /* 2557 */ "SFSUB_F_RI_LO\000"
1219 /* 2571 */ "SUBB_I_LO\000"
1220 /* 2581 */ "SUB_I_LO\000"
1221 /* 2590 */ "ADDC_I_LO\000"
1222 /* 2600 */ "ADD_I_LO\000"
1223 /* 2609 */ "AND_I_LO\000"
1224 /* 2618 */ "SUBB_F_I_LO\000"
1225 /* 2630 */ "SUB_F_I_LO\000"
1226 /* 2641 */ "ADDC_F_I_LO\000"
1227 /* 2653 */ "ADD_F_I_LO\000"
1228 /* 2664 */ "AND_F_I_LO\000"
1229 /* 2675 */ "XOR_F_I_LO\000"
1230 /* 2686 */ "XOR_I_LO\000"
1231 /* 2695 */ "G_BZERO\000"
1232 /* 2703 */ "STACKMAP\000"
1233 /* 2712 */ "G_DEBUGTRAP\000"
1234 /* 2724 */ "G_UBSANTRAP\000"
1235 /* 2736 */ "G_TRAP\000"
1236 /* 2743 */ "G_ATOMICRMW_UDEC_WRAP\000"
1237 /* 2765 */ "G_ATOMICRMW_UINC_WRAP\000"
1238 /* 2787 */ "G_BSWAP\000"
1239 /* 2795 */ "G_SITOFP\000"
1240 /* 2804 */ "G_UITOFP\000"
1241 /* 2813 */ "G_FCMP\000"
1242 /* 2820 */ "G_STRICT_FCMP\000"
1243 /* 2834 */ "G_ICMP\000"
1244 /* 2841 */ "G_SCMP\000"
1245 /* 2848 */ "G_UCMP\000"
1246 /* 2855 */ "NOP\000"
1247 /* 2859 */ "CONVERGENCECTRL_LOOP\000"
1248 /* 2880 */ "G_CTPOP\000"
1249 /* 2888 */ "PATCHABLE_OP\000"
1250 /* 2901 */ "FAULTING_OP\000"
1251 /* 2913 */ "ADJCALLSTACKUP\000"
1252 /* 2928 */ "PREALLOCATED_SETUP\000"
1253 /* 2947 */ "G_FLDEXP\000"
1254 /* 2956 */ "G_STRICT_FLDEXP\000"
1255 /* 2972 */ "G_FEXP\000"
1256 /* 2979 */ "G_FFREXP\000"
1257 /* 2988 */ "G_BR\000"
1258 /* 2993 */ "INLINEASM_BR\000"
1259 /* 3006 */ "LDADDR\000"
1260 /* 3013 */ "STADDR\000"
1261 /* 3020 */ "G_BLOCK_ADDR\000"
1262 /* 3033 */ "MEMBARRIER\000"
1263 /* 3044 */ "G_CONSTANT_FOLD_BARRIER\000"
1264 /* 3068 */ "PATCHABLE_FUNCTION_ENTER\000"
1265 /* 3093 */ "G_READCYCLECOUNTER\000"
1266 /* 3112 */ "G_READSTEADYCOUNTER\000"
1267 /* 3132 */ "G_READ_REGISTER\000"
1268 /* 3148 */ "G_WRITE_REGISTER\000"
1269 /* 3165 */ "G_ASHR\000"
1270 /* 3172 */ "G_FSHR\000"
1271 /* 3179 */ "G_LSHR\000"
1272 /* 3186 */ "JR\000"
1273 /* 3189 */ "CALLR\000"
1274 /* 3195 */ "CONVERGENCECTRL_ANCHOR\000"
1275 /* 3218 */ "G_FFLOOR\000"
1276 /* 3227 */ "G_SAVGFLOOR\000"
1277 /* 3239 */ "G_UAVGFLOOR\000"
1278 /* 3251 */ "G_EXTRACT_SUBVECTOR\000"
1279 /* 3271 */ "G_INSERT_SUBVECTOR\000"
1280 /* 3290 */ "G_BUILD_VECTOR\000"
1281 /* 3305 */ "G_SHUFFLE_VECTOR\000"
1282 /* 3322 */ "G_STEP_VECTOR\000"
1283 /* 3336 */ "G_SPLAT_VECTOR\000"
1284 /* 3351 */ "G_VECREDUCE_XOR\000"
1285 /* 3367 */ "G_XOR\000"
1286 /* 3373 */ "G_ATOMICRMW_XOR\000"
1287 /* 3389 */ "G_VECREDUCE_OR\000"
1288 /* 3404 */ "G_OR\000"
1289 /* 3409 */ "G_ATOMICRMW_OR\000"
1290 /* 3424 */ "BRR\000"
1291 /* 3428 */ "STB_RR\000"
1292 /* 3435 */ "SFSUB_F_RR\000"
1293 /* 3446 */ "STH_RR\000"
1294 /* 3453 */ "LDW_RR\000"
1295 /* 3460 */ "SW_RR\000"
1296 /* 3466 */ "LDBs_RR\000"
1297 /* 3474 */ "LDHs_RR\000"
1298 /* 3482 */ "LDBz_RR\000"
1299 /* 3490 */ "LDHz_RR\000"
1300 /* 3498 */ "LDWz_RR\000"
1301 /* 3506 */ "G_ROTR\000"
1302 /* 3513 */ "G_INTTOPTR\000"
1303 /* 3524 */ "SRA_R\000"
1304 /* 3530 */ "SUBB_R\000"
1305 /* 3537 */ "SUB_R\000"
1306 /* 3543 */ "ADDC_R\000"
1307 /* 3550 */ "ADD_R\000"
1308 /* 3556 */ "AND_R\000"
1309 /* 3562 */ "SRA_F_R\000"
1310 /* 3570 */ "SUBB_F_R\000"
1311 /* 3579 */ "SUB_F_R\000"
1312 /* 3587 */ "ADDC_F_R\000"
1313 /* 3596 */ "ADD_F_R\000"
1314 /* 3604 */ "AND_F_R\000"
1315 /* 3612 */ "SHL_F_R\000"
1316 /* 3620 */ "SRL_F_R\000"
1317 /* 3628 */ "XOR_F_R\000"
1318 /* 3636 */ "SHL_R\000"
1319 /* 3642 */ "SRL_R\000"
1320 /* 3648 */ "XOR_R\000"
1321 /* 3654 */ "G_FABS\000"
1322 /* 3661 */ "G_ABS\000"
1323 /* 3667 */ "G_ABDS\000"
1324 /* 3674 */ "G_UNMERGE_VALUES\000"
1325 /* 3691 */ "G_MERGE_VALUES\000"
1326 /* 3706 */ "G_CTLS\000"
1327 /* 3713 */ "G_FACOS\000"
1328 /* 3721 */ "G_FCOS\000"
1329 /* 3728 */ "G_FSINCOS\000"
1330 /* 3738 */ "G_STRICT_FCMPS\000"
1331 /* 3753 */ "G_CONCAT_VECTORS\000"
1332 /* 3770 */ "COPY_TO_REGCLASS\000"
1333 /* 3787 */ "G_IS_FPCLASS\000"
1334 /* 3800 */ "G_ATOMIC_CMPXCHG_WITH_SUCCESS\000"
1335 /* 3830 */ "G_VECTOR_COMPRESS\000"
1336 /* 3848 */ "G_INTRINSIC_W_SIDE_EFFECTS\000"
1337 /* 3875 */ "G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS\000"
1338 /* 3913 */ "G_TRUNC_SSAT_S\000"
1339 /* 3928 */ "G_SSUBSAT\000"
1340 /* 3938 */ "G_USUBSAT\000"
1341 /* 3948 */ "G_SADDSAT\000"
1342 /* 3958 */ "G_UADDSAT\000"
1343 /* 3968 */ "G_SSHLSAT\000"
1344 /* 3978 */ "G_USHLSAT\000"
1345 /* 3988 */ "G_SMULFIXSAT\000"
1346 /* 4001 */ "G_UMULFIXSAT\000"
1347 /* 4014 */ "G_SDIVFIXSAT\000"
1348 /* 4027 */ "G_UDIVFIXSAT\000"
1349 /* 4040 */ "G_ATOMICRMW_USUB_SAT\000"
1350 /* 4061 */ "G_FPTOSI_SAT\000"
1351 /* 4074 */ "G_FPTOUI_SAT\000"
1352 /* 4087 */ "BT\000"
1353 /* 4090 */ "G_EXTRACT\000"
1354 /* 4100 */ "G_SELECT\000"
1355 /* 4109 */ "G_BRINDIRECT\000"
1356 /* 4122 */ "PATCHABLE_RET\000"
1357 /* 4136 */ "G_MEMSET\000"
1358 /* 4145 */ "PATCHABLE_FUNCTION_EXIT\000"
1359 /* 4169 */ "G_BRJT\000"
1360 /* 4176 */ "G_EXTRACT_VECTOR_ELT\000"
1361 /* 4197 */ "G_INSERT_VECTOR_ELT\000"
1362 /* 4217 */ "G_FCONSTANT\000"
1363 /* 4229 */ "G_CONSTANT\000"
1364 /* 4240 */ "G_INTRINSIC_CONVERGENT\000"
1365 /* 4263 */ "STATEPOINT\000"
1366 /* 4274 */ "PATCHPOINT\000"
1367 /* 4285 */ "G_PTRTOINT\000"
1368 /* 4296 */ "G_FRINT\000"
1369 /* 4304 */ "G_INTRINSIC_LLRINT\000"
1370 /* 4323 */ "G_INTRINSIC_LRINT\000"
1371 /* 4341 */ "G_FNEARBYINT\000"
1372 /* 4354 */ "G_VASTART\000"
1373 /* 4364 */ "LIFETIME_START\000"
1374 /* 4379 */ "G_INVOKE_REGION_START\000"
1375 /* 4401 */ "G_INSERT\000"
1376 /* 4410 */ "G_FSQRT\000"
1377 /* 4418 */ "G_STRICT_FSQRT\000"
1378 /* 4433 */ "G_BITCAST\000"
1379 /* 4443 */ "G_ADDRSPACE_CAST\000"
1380 /* 4460 */ "DBG_VALUE_LIST\000"
1381 /* 4475 */ "G_FPEXT\000"
1382 /* 4483 */ "G_SEXT\000"
1383 /* 4490 */ "G_ASSERT_SEXT\000"
1384 /* 4504 */ "G_ANYEXT\000"
1385 /* 4513 */ "G_ZEXT\000"
1386 /* 4520 */ "G_ASSERT_ZEXT\000"
1387 /* 4534 */ "G_ABDU\000"
1388 /* 4541 */ "G_TRUNC_SSAT_U\000"
1389 /* 4556 */ "G_TRUNC_USAT_U\000"
1390 /* 4571 */ "G_FDIV\000"
1391 /* 4578 */ "G_STRICT_FDIV\000"
1392 /* 4592 */ "G_SDIV\000"
1393 /* 4599 */ "G_UDIV\000"
1394 /* 4606 */ "G_GET_FPENV\000"
1395 /* 4618 */ "G_RESET_FPENV\000"
1396 /* 4632 */ "G_SET_FPENV\000"
1397 /* 4644 */ "G_FPOW\000"
1398 /* 4651 */ "G_VECREDUCE_FMAX\000"
1399 /* 4668 */ "G_ATOMICRMW_FMAX\000"
1400 /* 4685 */ "G_VECREDUCE_SMAX\000"
1401 /* 4702 */ "G_SMAX\000"
1402 /* 4709 */ "G_VECREDUCE_UMAX\000"
1403 /* 4726 */ "G_UMAX\000"
1404 /* 4733 */ "G_ATOMICRMW_UMAX\000"
1405 /* 4750 */ "G_ATOMICRMW_MAX\000"
1406 /* 4766 */ "G_FRAME_INDEX\000"
1407 /* 4780 */ "G_SBFX\000"
1408 /* 4787 */ "G_UBFX\000"
1409 /* 4794 */ "G_SMULFIX\000"
1410 /* 4804 */ "G_UMULFIX\000"
1411 /* 4814 */ "G_SDIVFIX\000"
1412 /* 4824 */ "G_UDIVFIX\000"
1413 /* 4834 */ "G_MEMCPY\000"
1414 /* 4843 */ "COPY\000"
1415 /* 4848 */ "CONVERGENCECTRL_ENTRY\000"
1416 /* 4870 */ "LEADZ\000"
1417 /* 4876 */ "TRAILZ\000"
1418 /* 4883 */ "G_CTLZ\000"
1419 /* 4890 */ "G_CTTZ\000"
1420};
1421#ifdef __GNUC__
1422#pragma GCC diagnostic pop
1423#endif
1424
1425extern const unsigned LanaiInstrNameIndices[] = {
1426 1365U, 2010U, 2993U, 2416U, 1669U, 1650U, 1678U, 1838U,
1427 1158U, 1173U, 1124U, 1111U, 1200U, 3770U, 987U, 4460U,
1428 1137U, 1361U, 1659U, 726U, 4843U, 1626U, 848U, 4364U,
1429 553U, 677U, 714U, 2703U, 1826U, 4274U, 660U, 2928U,
1430 1293U, 4263U, 898U, 2901U, 2888U, 3068U, 4122U, 4145U,
1431 1758U, 1805U, 1778U, 1695U, 978U, 3033U, 2519U, 887U,
1432 4848U, 3195U, 2859U, 1035U, 4490U, 4520U, 2259U, 466U,
1433 130U, 1949U, 4592U, 4599U, 1976U, 1983U, 1990U, 2000U,
1434 531U, 3404U, 3367U, 3667U, 4534U, 3239U, 1747U, 3227U,
1435 1736U, 1122U, 1363U, 4766U, 997U, 1012U, 1843U, 4090U,
1436 3674U, 4401U, 3691U, 3290U, 218U, 3753U, 4285U, 3513U,
1437 4433U, 1078U, 3044U, 634U, 192U, 616U, 4323U, 4304U,
1438 2237U, 3093U, 3112U, 367U, 311U, 341U, 280U, 352U,
1439 292U, 322U, 957U, 911U, 941U, 3800U, 1214U, 1231U,
1440 482U, 136U, 537U, 498U, 3409U, 3373U, 4750U, 2385U,
1441 4733U, 2368U, 433U, 113U, 4668U, 2303U, 2105U, 2052U,
1442 2178U, 2140U, 2765U, 2743U, 575U, 4040U, 706U, 1310U,
1443 566U, 4109U, 4379U, 170U, 3848U, 4240U, 3875U, 4504U,
1444 210U, 3913U, 4541U, 4556U, 4229U, 4217U, 4354U, 1285U,
1445 4483U, 1187U, 4513U, 1722U, 3179U, 3165U, 1715U, 3172U,
1446 3506U, 1859U, 2834U, 2813U, 2841U, 2848U, 4100U, 2511U,
1447 747U, 2495U, 698U, 2503U, 739U, 2487U, 690U, 2549U,
1448 2541U, 1329U, 1321U, 3958U, 3948U, 3938U, 3928U, 3978U,
1449 3968U, 4794U, 4804U, 3988U, 4001U, 4814U, 4824U, 4014U,
1450 4027U, 391U, 92U, 1883U, 73U, 273U, 4571U, 1955U,
1451 1103U, 4644U, 1594U, 2972U, 45U, 9U, 1278U, 28U,
1452 0U, 2947U, 2979U, 1151U, 4475U, 182U, 1576U, 1585U,
1453 2795U, 2804U, 4061U, 4074U, 3654U, 2274U, 3787U, 1087U,
1454 2202U, 2212U, 796U, 811U, 2041U, 2094U, 2126U, 2164U,
1455 4606U, 4632U, 4618U, 755U, 783U, 768U, 1248U, 1263U,
1456 472U, 1640U, 2337U, 4702U, 2361U, 4726U, 3661U, 607U,
1457 597U, 2988U, 4169U, 826U, 3271U, 3251U, 4197U, 4176U,
1458 3305U, 3336U, 3322U, 3830U, 4890U, 2451U, 4883U, 2432U,
1459 3706U, 2880U, 2787U, 965U, 1925U, 1728U, 3721U, 2409U,
1460 3728U, 2230U, 3713U, 2401U, 2222U, 36U, 1353U, 1345U,
1461 1337U, 4410U, 3218U, 4296U, 4341U, 4443U, 3020U, 835U,
1462 239U, 1056U, 926U, 419U, 99U, 1911U, 4578U, 1962U,
1463 79U, 4418U, 2956U, 2820U, 3738U, 3132U, 3148U, 4834U,
1464 871U, 1068U, 4136U, 2695U, 855U, 2736U, 2712U, 2724U,
1465 398U, 1890U, 374U, 1866U, 4651U, 2286U, 2073U, 2020U,
1466 450U, 1933U, 515U, 3389U, 3351U, 4685U, 2320U, 4709U,
1467 2344U, 4780U, 4787U, 2470U, 2913U, 256U, 1773U, 3189U,
1468 1459U, 2641U, 3587U, 1408U, 2590U, 3543U, 1471U, 2653U,
1469 3596U, 1418U, 2600U, 3550U, 1482U, 2664U, 3604U, 1427U,
1470 2609U, 3556U, 152U, 161U, 63U, 3424U, 4087U, 3186U,
1471 3006U, 1544U, 3466U, 1560U, 3482U, 1552U, 3474U, 1568U,
1472 3490U, 1531U, 3453U, 3498U, 4870U, 18U, 23U, 31U,
1473 53U, 58U, 1369U, 2855U, 1494U, 2676U, 3629U, 1505U,
1474 2687U, 3649U, 268U, 4132U, 1607U, 1602U, 157U, 4102U,
1475 1375U, 2557U, 3435U, 3612U, 3636U, 1513U, 1614U, 1621U,
1476 3562U, 3524U, 3620U, 3642U, 3013U, 1517U, 3428U, 1524U,
1477 3446U, 1436U, 2618U, 3570U, 1389U, 2571U, 3530U, 1448U,
1478 2630U, 3579U, 1399U, 2581U, 3537U, 1538U, 3460U, 4876U,
1479 1493U, 2675U, 3628U, 1504U, 2686U, 3648U,
1480};
1481
1482static inline void InitLanaiMCInstrInfo(MCInstrInfo *II) {
1483 II->InitMCInstrInfo(LanaiDescs.Insts, LanaiInstrNameIndices, LanaiInstrNameData, nullptr, nullptr, 430, nullptr, 0);
1484}
1485
1486
1487} // namespace llvm
1488
1489#endif // GET_INSTRINFO_MC_DESC
1490
1491#ifdef GET_INSTRINFO_HEADER
1492#undef GET_INSTRINFO_HEADER
1493
1494namespace llvm {
1495
1496struct LanaiGenInstrInfo : public TargetInstrInfo {
1497 explicit LanaiGenInstrInfo(const TargetSubtargetInfo &STI, const TargetRegisterInfo &TRI, unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u, unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u);
1498 ~LanaiGenInstrInfo() override = default;
1499};
1500
1501} // namespace llvm
1502
1503namespace llvm::Lanai {
1504
1505constexpr unsigned SUBOP_MEMri_base = 0;
1506constexpr unsigned SUBOP_MEMri_offset = 1;
1507constexpr unsigned SUBOP_MEMri_Opcode = 2;
1508constexpr unsigned SUBOP_MEMrr_Op1 = 0;
1509constexpr unsigned SUBOP_MEMrr_Op2 = 1;
1510constexpr unsigned SUBOP_MEMrr_Opcode = 2;
1511constexpr unsigned SUBOP_MEMspls_base = 0;
1512constexpr unsigned SUBOP_MEMspls_offset = 1;
1513constexpr unsigned SUBOP_MEMspls_Opcode = 2;
1514
1515} // namespace llvm::Lanai
1516
1517#endif // GET_INSTRINFO_HEADER
1518
1519#ifdef GET_INSTRINFO_HELPER_DECLS
1520#undef GET_INSTRINFO_HELPER_DECLS
1521
1522
1523#endif // GET_INSTRINFO_HELPER_DECLS
1524
1525#ifdef GET_INSTRINFO_HELPERS
1526#undef GET_INSTRINFO_HELPERS
1527
1528
1529#endif // GET_INSTRINFO_HELPERS
1530
1531#ifdef GET_INSTRINFO_CTOR_DTOR
1532#undef GET_INSTRINFO_CTOR_DTOR
1533
1534namespace llvm {
1535
1536extern const LanaiInstrTable LanaiDescs;
1537extern const unsigned LanaiInstrNameIndices[];
1538extern const char LanaiInstrNameData[];
1539LanaiGenInstrInfo::LanaiGenInstrInfo(const TargetSubtargetInfo &STI, const TargetRegisterInfo &TRI, unsigned CFSetupOpcode, unsigned CFDestroyOpcode, unsigned CatchRetOpcode, unsigned ReturnOpcode)
1540 : TargetInstrInfo(TRI, CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) {
1541 InitMCInstrInfo(LanaiDescs.Insts, LanaiInstrNameIndices, LanaiInstrNameData, nullptr, nullptr, 430);
1542}
1543
1544} // namespace llvm
1545
1546#endif // GET_INSTRINFO_CTOR_DTOR
1547
1548#ifdef GET_INSTRINFO_MC_HELPER_DECLS
1549#undef GET_INSTRINFO_MC_HELPER_DECLS
1550
1551namespace llvm {
1552
1553class MCInst;
1554class FeatureBitset;
1555
1556namespace Lanai_MC {
1557
1558void verifyInstructionPredicates(unsigned Opcode, const FeatureBitset &Features);
1559
1560} // namespace Lanai_MC
1561
1562} // namespace llvm
1563
1564#endif // GET_INSTRINFO_MC_HELPER_DECLS
1565
1566#ifdef GET_INSTRINFO_MC_HELPERS
1567#undef GET_INSTRINFO_MC_HELPERS
1568
1569namespace llvm::Lanai_MC {
1570
1571
1572} // namespace llvm::Lanai_MC
1573
1574#endif // GET_INSTRINFO_MC_HELPERS
1575
1576#if (defined(ENABLE_INSTR_PREDICATE_VERIFIER) && !defined(NDEBUG)) ||\
1577 defined(GET_AVAILABLE_OPCODE_CHECKER)
1578#define GET_COMPUTE_FEATURES
1579#endif
1580#ifdef GET_COMPUTE_FEATURES
1581#undef GET_COMPUTE_FEATURES
1582
1583namespace llvm::Lanai_MC {
1584
1585// Bits for subtarget features that participate in instruction matching.
1586enum SubtargetFeatureBits : uint8_t {
1587};
1588
1589inline FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) {
1590 FeatureBitset Features;
1591 return Features;
1592}
1593
1594inline FeatureBitset computeRequiredFeatures(unsigned Opcode) {
1595 enum : uint8_t {
1596 CEFBS_None,
1597 };
1598
1599 static constexpr FeatureBitset FeatureBitsets[] = {
1600 {}, // CEFBS_None
1601 };
1602 static constexpr uint8_t RequiredFeaturesRefs[] = {
1603 CEFBS_None, // PHI
1604 CEFBS_None, // INLINEASM
1605 CEFBS_None, // INLINEASM_BR
1606 CEFBS_None, // CFI_INSTRUCTION
1607 CEFBS_None, // EH_LABEL
1608 CEFBS_None, // GC_LABEL
1609 CEFBS_None, // ANNOTATION_LABEL
1610 CEFBS_None, // KILL
1611 CEFBS_None, // EXTRACT_SUBREG
1612 CEFBS_None, // INSERT_SUBREG
1613 CEFBS_None, // IMPLICIT_DEF
1614 CEFBS_None, // INIT_UNDEF
1615 CEFBS_None, // SUBREG_TO_REG
1616 CEFBS_None, // COPY_TO_REGCLASS
1617 CEFBS_None, // DBG_VALUE
1618 CEFBS_None, // DBG_VALUE_LIST
1619 CEFBS_None, // DBG_INSTR_REF
1620 CEFBS_None, // DBG_PHI
1621 CEFBS_None, // DBG_LABEL
1622 CEFBS_None, // REG_SEQUENCE
1623 CEFBS_None, // COPY
1624 CEFBS_None, // COPY_LANEMASK
1625 CEFBS_None, // BUNDLE
1626 CEFBS_None, // LIFETIME_START
1627 CEFBS_None, // LIFETIME_END
1628 CEFBS_None, // PSEUDO_PROBE
1629 CEFBS_None, // ARITH_FENCE
1630 CEFBS_None, // STACKMAP
1631 CEFBS_None, // FENTRY_CALL
1632 CEFBS_None, // PATCHPOINT
1633 CEFBS_None, // LOAD_STACK_GUARD
1634 CEFBS_None, // PREALLOCATED_SETUP
1635 CEFBS_None, // PREALLOCATED_ARG
1636 CEFBS_None, // STATEPOINT
1637 CEFBS_None, // LOCAL_ESCAPE
1638 CEFBS_None, // FAULTING_OP
1639 CEFBS_None, // PATCHABLE_OP
1640 CEFBS_None, // PATCHABLE_FUNCTION_ENTER
1641 CEFBS_None, // PATCHABLE_RET
1642 CEFBS_None, // PATCHABLE_FUNCTION_EXIT
1643 CEFBS_None, // PATCHABLE_TAIL_CALL
1644 CEFBS_None, // PATCHABLE_EVENT_CALL
1645 CEFBS_None, // PATCHABLE_TYPED_EVENT_CALL
1646 CEFBS_None, // ICALL_BRANCH_FUNNEL
1647 CEFBS_None, // FAKE_USE
1648 CEFBS_None, // MEMBARRIER
1649 CEFBS_None, // JUMP_TABLE_DEBUG_INFO
1650 CEFBS_None, // RELOC_NONE
1651 CEFBS_None, // CONVERGENCECTRL_ENTRY
1652 CEFBS_None, // CONVERGENCECTRL_ANCHOR
1653 CEFBS_None, // CONVERGENCECTRL_LOOP
1654 CEFBS_None, // CONVERGENCECTRL_GLUE
1655 CEFBS_None, // G_ASSERT_SEXT
1656 CEFBS_None, // G_ASSERT_ZEXT
1657 CEFBS_None, // G_ASSERT_ALIGN
1658 CEFBS_None, // G_ADD
1659 CEFBS_None, // G_SUB
1660 CEFBS_None, // G_MUL
1661 CEFBS_None, // G_SDIV
1662 CEFBS_None, // G_UDIV
1663 CEFBS_None, // G_SREM
1664 CEFBS_None, // G_UREM
1665 CEFBS_None, // G_SDIVREM
1666 CEFBS_None, // G_UDIVREM
1667 CEFBS_None, // G_AND
1668 CEFBS_None, // G_OR
1669 CEFBS_None, // G_XOR
1670 CEFBS_None, // G_ABDS
1671 CEFBS_None, // G_ABDU
1672 CEFBS_None, // G_UAVGFLOOR
1673 CEFBS_None, // G_UAVGCEIL
1674 CEFBS_None, // G_SAVGFLOOR
1675 CEFBS_None, // G_SAVGCEIL
1676 CEFBS_None, // G_IMPLICIT_DEF
1677 CEFBS_None, // G_PHI
1678 CEFBS_None, // G_FRAME_INDEX
1679 CEFBS_None, // G_GLOBAL_VALUE
1680 CEFBS_None, // G_PTRAUTH_GLOBAL_VALUE
1681 CEFBS_None, // G_CONSTANT_POOL
1682 CEFBS_None, // G_EXTRACT
1683 CEFBS_None, // G_UNMERGE_VALUES
1684 CEFBS_None, // G_INSERT
1685 CEFBS_None, // G_MERGE_VALUES
1686 CEFBS_None, // G_BUILD_VECTOR
1687 CEFBS_None, // G_BUILD_VECTOR_TRUNC
1688 CEFBS_None, // G_CONCAT_VECTORS
1689 CEFBS_None, // G_PTRTOINT
1690 CEFBS_None, // G_INTTOPTR
1691 CEFBS_None, // G_BITCAST
1692 CEFBS_None, // G_FREEZE
1693 CEFBS_None, // G_CONSTANT_FOLD_BARRIER
1694 CEFBS_None, // G_INTRINSIC_FPTRUNC_ROUND
1695 CEFBS_None, // G_INTRINSIC_TRUNC
1696 CEFBS_None, // G_INTRINSIC_ROUND
1697 CEFBS_None, // G_INTRINSIC_LRINT
1698 CEFBS_None, // G_INTRINSIC_LLRINT
1699 CEFBS_None, // G_INTRINSIC_ROUNDEVEN
1700 CEFBS_None, // G_READCYCLECOUNTER
1701 CEFBS_None, // G_READSTEADYCOUNTER
1702 CEFBS_None, // G_LOAD
1703 CEFBS_None, // G_SEXTLOAD
1704 CEFBS_None, // G_ZEXTLOAD
1705 CEFBS_None, // G_FPEXTLOAD
1706 CEFBS_None, // G_INDEXED_LOAD
1707 CEFBS_None, // G_INDEXED_SEXTLOAD
1708 CEFBS_None, // G_INDEXED_ZEXTLOAD
1709 CEFBS_None, // G_STORE
1710 CEFBS_None, // G_FPTRUNCSTORE
1711 CEFBS_None, // G_INDEXED_STORE
1712 CEFBS_None, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
1713 CEFBS_None, // G_ATOMIC_CMPXCHG
1714 CEFBS_None, // G_ATOMICRMW_XCHG
1715 CEFBS_None, // G_ATOMICRMW_ADD
1716 CEFBS_None, // G_ATOMICRMW_SUB
1717 CEFBS_None, // G_ATOMICRMW_AND
1718 CEFBS_None, // G_ATOMICRMW_NAND
1719 CEFBS_None, // G_ATOMICRMW_OR
1720 CEFBS_None, // G_ATOMICRMW_XOR
1721 CEFBS_None, // G_ATOMICRMW_MAX
1722 CEFBS_None, // G_ATOMICRMW_MIN
1723 CEFBS_None, // G_ATOMICRMW_UMAX
1724 CEFBS_None, // G_ATOMICRMW_UMIN
1725 CEFBS_None, // G_ATOMICRMW_FADD
1726 CEFBS_None, // G_ATOMICRMW_FSUB
1727 CEFBS_None, // G_ATOMICRMW_FMAX
1728 CEFBS_None, // G_ATOMICRMW_FMIN
1729 CEFBS_None, // G_ATOMICRMW_FMAXIMUM
1730 CEFBS_None, // G_ATOMICRMW_FMINIMUM
1731 CEFBS_None, // G_ATOMICRMW_FMAXIMUMNUM
1732 CEFBS_None, // G_ATOMICRMW_FMINIMUMNUM
1733 CEFBS_None, // G_ATOMICRMW_UINC_WRAP
1734 CEFBS_None, // G_ATOMICRMW_UDEC_WRAP
1735 CEFBS_None, // G_ATOMICRMW_USUB_COND
1736 CEFBS_None, // G_ATOMICRMW_USUB_SAT
1737 CEFBS_None, // G_FENCE
1738 CEFBS_None, // G_PREFETCH
1739 CEFBS_None, // G_BRCOND
1740 CEFBS_None, // G_BRINDIRECT
1741 CEFBS_None, // G_INVOKE_REGION_START
1742 CEFBS_None, // G_INTRINSIC
1743 CEFBS_None, // G_INTRINSIC_W_SIDE_EFFECTS
1744 CEFBS_None, // G_INTRINSIC_CONVERGENT
1745 CEFBS_None, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
1746 CEFBS_None, // G_ANYEXT
1747 CEFBS_None, // G_TRUNC
1748 CEFBS_None, // G_TRUNC_SSAT_S
1749 CEFBS_None, // G_TRUNC_SSAT_U
1750 CEFBS_None, // G_TRUNC_USAT_U
1751 CEFBS_None, // G_CONSTANT
1752 CEFBS_None, // G_FCONSTANT
1753 CEFBS_None, // G_VASTART
1754 CEFBS_None, // G_VAARG
1755 CEFBS_None, // G_SEXT
1756 CEFBS_None, // G_SEXT_INREG
1757 CEFBS_None, // G_ZEXT
1758 CEFBS_None, // G_SHL
1759 CEFBS_None, // G_LSHR
1760 CEFBS_None, // G_ASHR
1761 CEFBS_None, // G_FSHL
1762 CEFBS_None, // G_FSHR
1763 CEFBS_None, // G_ROTR
1764 CEFBS_None, // G_ROTL
1765 CEFBS_None, // G_ICMP
1766 CEFBS_None, // G_FCMP
1767 CEFBS_None, // G_SCMP
1768 CEFBS_None, // G_UCMP
1769 CEFBS_None, // G_SELECT
1770 CEFBS_None, // G_UADDO
1771 CEFBS_None, // G_UADDE
1772 CEFBS_None, // G_USUBO
1773 CEFBS_None, // G_USUBE
1774 CEFBS_None, // G_SADDO
1775 CEFBS_None, // G_SADDE
1776 CEFBS_None, // G_SSUBO
1777 CEFBS_None, // G_SSUBE
1778 CEFBS_None, // G_UMULO
1779 CEFBS_None, // G_SMULO
1780 CEFBS_None, // G_UMULH
1781 CEFBS_None, // G_SMULH
1782 CEFBS_None, // G_UADDSAT
1783 CEFBS_None, // G_SADDSAT
1784 CEFBS_None, // G_USUBSAT
1785 CEFBS_None, // G_SSUBSAT
1786 CEFBS_None, // G_USHLSAT
1787 CEFBS_None, // G_SSHLSAT
1788 CEFBS_None, // G_SMULFIX
1789 CEFBS_None, // G_UMULFIX
1790 CEFBS_None, // G_SMULFIXSAT
1791 CEFBS_None, // G_UMULFIXSAT
1792 CEFBS_None, // G_SDIVFIX
1793 CEFBS_None, // G_UDIVFIX
1794 CEFBS_None, // G_SDIVFIXSAT
1795 CEFBS_None, // G_UDIVFIXSAT
1796 CEFBS_None, // G_FADD
1797 CEFBS_None, // G_FSUB
1798 CEFBS_None, // G_FMUL
1799 CEFBS_None, // G_FMA
1800 CEFBS_None, // G_FMAD
1801 CEFBS_None, // G_FDIV
1802 CEFBS_None, // G_FREM
1803 CEFBS_None, // G_FMODF
1804 CEFBS_None, // G_FPOW
1805 CEFBS_None, // G_FPOWI
1806 CEFBS_None, // G_FEXP
1807 CEFBS_None, // G_FEXP2
1808 CEFBS_None, // G_FEXP10
1809 CEFBS_None, // G_FLOG
1810 CEFBS_None, // G_FLOG2
1811 CEFBS_None, // G_FLOG10
1812 CEFBS_None, // G_FLDEXP
1813 CEFBS_None, // G_FFREXP
1814 CEFBS_None, // G_FNEG
1815 CEFBS_None, // G_FPEXT
1816 CEFBS_None, // G_FPTRUNC
1817 CEFBS_None, // G_FPTOSI
1818 CEFBS_None, // G_FPTOUI
1819 CEFBS_None, // G_SITOFP
1820 CEFBS_None, // G_UITOFP
1821 CEFBS_None, // G_FPTOSI_SAT
1822 CEFBS_None, // G_FPTOUI_SAT
1823 CEFBS_None, // G_FABS
1824 CEFBS_None, // G_FCOPYSIGN
1825 CEFBS_None, // G_IS_FPCLASS
1826 CEFBS_None, // G_FCANONICALIZE
1827 CEFBS_None, // G_FMINNUM
1828 CEFBS_None, // G_FMAXNUM
1829 CEFBS_None, // G_FMINNUM_IEEE
1830 CEFBS_None, // G_FMAXNUM_IEEE
1831 CEFBS_None, // G_FMINIMUM
1832 CEFBS_None, // G_FMAXIMUM
1833 CEFBS_None, // G_FMINIMUMNUM
1834 CEFBS_None, // G_FMAXIMUMNUM
1835 CEFBS_None, // G_GET_FPENV
1836 CEFBS_None, // G_SET_FPENV
1837 CEFBS_None, // G_RESET_FPENV
1838 CEFBS_None, // G_GET_FPMODE
1839 CEFBS_None, // G_SET_FPMODE
1840 CEFBS_None, // G_RESET_FPMODE
1841 CEFBS_None, // G_GET_ROUNDING
1842 CEFBS_None, // G_SET_ROUNDING
1843 CEFBS_None, // G_PTR_ADD
1844 CEFBS_None, // G_PTRMASK
1845 CEFBS_None, // G_SMIN
1846 CEFBS_None, // G_SMAX
1847 CEFBS_None, // G_UMIN
1848 CEFBS_None, // G_UMAX
1849 CEFBS_None, // G_ABS
1850 CEFBS_None, // G_LROUND
1851 CEFBS_None, // G_LLROUND
1852 CEFBS_None, // G_BR
1853 CEFBS_None, // G_BRJT
1854 CEFBS_None, // G_VSCALE
1855 CEFBS_None, // G_INSERT_SUBVECTOR
1856 CEFBS_None, // G_EXTRACT_SUBVECTOR
1857 CEFBS_None, // G_INSERT_VECTOR_ELT
1858 CEFBS_None, // G_EXTRACT_VECTOR_ELT
1859 CEFBS_None, // G_SHUFFLE_VECTOR
1860 CEFBS_None, // G_SPLAT_VECTOR
1861 CEFBS_None, // G_STEP_VECTOR
1862 CEFBS_None, // G_VECTOR_COMPRESS
1863 CEFBS_None, // G_CTTZ
1864 CEFBS_None, // G_CTTZ_ZERO_POISON
1865 CEFBS_None, // G_CTLZ
1866 CEFBS_None, // G_CTLZ_ZERO_POISON
1867 CEFBS_None, // G_CTLS
1868 CEFBS_None, // G_CTPOP
1869 CEFBS_None, // G_BSWAP
1870 CEFBS_None, // G_BITREVERSE
1871 CEFBS_None, // G_CLMUL
1872 CEFBS_None, // G_FCEIL
1873 CEFBS_None, // G_FCOS
1874 CEFBS_None, // G_FSIN
1875 CEFBS_None, // G_FSINCOS
1876 CEFBS_None, // G_FTAN
1877 CEFBS_None, // G_FACOS
1878 CEFBS_None, // G_FASIN
1879 CEFBS_None, // G_FATAN
1880 CEFBS_None, // G_FATAN2
1881 CEFBS_None, // G_FCOSH
1882 CEFBS_None, // G_FSINH
1883 CEFBS_None, // G_FTANH
1884 CEFBS_None, // G_FSQRT
1885 CEFBS_None, // G_FFLOOR
1886 CEFBS_None, // G_FRINT
1887 CEFBS_None, // G_FNEARBYINT
1888 CEFBS_None, // G_ADDRSPACE_CAST
1889 CEFBS_None, // G_BLOCK_ADDR
1890 CEFBS_None, // G_JUMP_TABLE
1891 CEFBS_None, // G_DYN_STACKALLOC
1892 CEFBS_None, // G_STACKSAVE
1893 CEFBS_None, // G_STACKRESTORE
1894 CEFBS_None, // G_STRICT_FADD
1895 CEFBS_None, // G_STRICT_FSUB
1896 CEFBS_None, // G_STRICT_FMUL
1897 CEFBS_None, // G_STRICT_FDIV
1898 CEFBS_None, // G_STRICT_FREM
1899 CEFBS_None, // G_STRICT_FMA
1900 CEFBS_None, // G_STRICT_FSQRT
1901 CEFBS_None, // G_STRICT_FLDEXP
1902 CEFBS_None, // G_STRICT_FCMP
1903 CEFBS_None, // G_STRICT_FCMPS
1904 CEFBS_None, // G_READ_REGISTER
1905 CEFBS_None, // G_WRITE_REGISTER
1906 CEFBS_None, // G_MEMCPY
1907 CEFBS_None, // G_MEMCPY_INLINE
1908 CEFBS_None, // G_MEMMOVE
1909 CEFBS_None, // G_MEMSET
1910 CEFBS_None, // G_BZERO
1911 CEFBS_None, // G_MEMSET_INLINE
1912 CEFBS_None, // G_TRAP
1913 CEFBS_None, // G_DEBUGTRAP
1914 CEFBS_None, // G_UBSANTRAP
1915 CEFBS_None, // G_VECREDUCE_SEQ_FADD
1916 CEFBS_None, // G_VECREDUCE_SEQ_FMUL
1917 CEFBS_None, // G_VECREDUCE_FADD
1918 CEFBS_None, // G_VECREDUCE_FMUL
1919 CEFBS_None, // G_VECREDUCE_FMAX
1920 CEFBS_None, // G_VECREDUCE_FMIN
1921 CEFBS_None, // G_VECREDUCE_FMAXIMUM
1922 CEFBS_None, // G_VECREDUCE_FMINIMUM
1923 CEFBS_None, // G_VECREDUCE_ADD
1924 CEFBS_None, // G_VECREDUCE_MUL
1925 CEFBS_None, // G_VECREDUCE_AND
1926 CEFBS_None, // G_VECREDUCE_OR
1927 CEFBS_None, // G_VECREDUCE_XOR
1928 CEFBS_None, // G_VECREDUCE_SMAX
1929 CEFBS_None, // G_VECREDUCE_SMIN
1930 CEFBS_None, // G_VECREDUCE_UMAX
1931 CEFBS_None, // G_VECREDUCE_UMIN
1932 CEFBS_None, // G_SBFX
1933 CEFBS_None, // G_UBFX
1934 CEFBS_None, // ADJCALLSTACKDOWN
1935 CEFBS_None, // ADJCALLSTACKUP
1936 CEFBS_None, // ADJDYNALLOC
1937 CEFBS_None, // CALL
1938 CEFBS_None, // CALLR
1939 CEFBS_None, // ADDC_F_I_HI
1940 CEFBS_None, // ADDC_F_I_LO
1941 CEFBS_None, // ADDC_F_R
1942 CEFBS_None, // ADDC_I_HI
1943 CEFBS_None, // ADDC_I_LO
1944 CEFBS_None, // ADDC_R
1945 CEFBS_None, // ADD_F_I_HI
1946 CEFBS_None, // ADD_F_I_LO
1947 CEFBS_None, // ADD_F_R
1948 CEFBS_None, // ADD_I_HI
1949 CEFBS_None, // ADD_I_LO
1950 CEFBS_None, // ADD_R
1951 CEFBS_None, // AND_F_I_HI
1952 CEFBS_None, // AND_F_I_LO
1953 CEFBS_None, // AND_F_R
1954 CEFBS_None, // AND_I_HI
1955 CEFBS_None, // AND_I_LO
1956 CEFBS_None, // AND_R
1957 CEFBS_None, // BRCC
1958 CEFBS_None, // BRIND_CC
1959 CEFBS_None, // BRIND_CCA
1960 CEFBS_None, // BRR
1961 CEFBS_None, // BT
1962 CEFBS_None, // JR
1963 CEFBS_None, // LDADDR
1964 CEFBS_None, // LDBs_RI
1965 CEFBS_None, // LDBs_RR
1966 CEFBS_None, // LDBz_RI
1967 CEFBS_None, // LDBz_RR
1968 CEFBS_None, // LDHs_RI
1969 CEFBS_None, // LDHs_RR
1970 CEFBS_None, // LDHz_RI
1971 CEFBS_None, // LDHz_RR
1972 CEFBS_None, // LDW_RI
1973 CEFBS_None, // LDW_RR
1974 CEFBS_None, // LDWz_RR
1975 CEFBS_None, // LEADZ
1976 CEFBS_None, // LOG0
1977 CEFBS_None, // LOG1
1978 CEFBS_None, // LOG2
1979 CEFBS_None, // LOG3
1980 CEFBS_None, // LOG4
1981 CEFBS_None, // MOVHI
1982 CEFBS_None, // NOP
1983 CEFBS_None, // OR_F_I_HI
1984 CEFBS_None, // OR_F_I_LO
1985 CEFBS_None, // OR_F_R
1986 CEFBS_None, // OR_I_HI
1987 CEFBS_None, // OR_I_LO
1988 CEFBS_None, // OR_R
1989 CEFBS_None, // POPC
1990 CEFBS_None, // RET
1991 CEFBS_None, // SA_F_I
1992 CEFBS_None, // SA_I
1993 CEFBS_None, // SCC
1994 CEFBS_None, // SELECT
1995 CEFBS_None, // SFSUB_F_RI_HI
1996 CEFBS_None, // SFSUB_F_RI_LO
1997 CEFBS_None, // SFSUB_F_RR
1998 CEFBS_None, // SHL_F_R
1999 CEFBS_None, // SHL_R
2000 CEFBS_None, // SLI
2001 CEFBS_None, // SL_F_I
2002 CEFBS_None, // SL_I
2003 CEFBS_None, // SRA_F_R
2004 CEFBS_None, // SRA_R
2005 CEFBS_None, // SRL_F_R
2006 CEFBS_None, // SRL_R
2007 CEFBS_None, // STADDR
2008 CEFBS_None, // STB_RI
2009 CEFBS_None, // STB_RR
2010 CEFBS_None, // STH_RI
2011 CEFBS_None, // STH_RR
2012 CEFBS_None, // SUBB_F_I_HI
2013 CEFBS_None, // SUBB_F_I_LO
2014 CEFBS_None, // SUBB_F_R
2015 CEFBS_None, // SUBB_I_HI
2016 CEFBS_None, // SUBB_I_LO
2017 CEFBS_None, // SUBB_R
2018 CEFBS_None, // SUB_F_I_HI
2019 CEFBS_None, // SUB_F_I_LO
2020 CEFBS_None, // SUB_F_R
2021 CEFBS_None, // SUB_I_HI
2022 CEFBS_None, // SUB_I_LO
2023 CEFBS_None, // SUB_R
2024 CEFBS_None, // SW_RI
2025 CEFBS_None, // SW_RR
2026 CEFBS_None, // TRAILZ
2027 CEFBS_None, // XOR_F_I_HI
2028 CEFBS_None, // XOR_F_I_LO
2029 CEFBS_None, // XOR_F_R
2030 CEFBS_None, // XOR_I_HI
2031 CEFBS_None, // XOR_I_LO
2032 CEFBS_None, // XOR_R
2033 };
2034
2035 assert(Opcode < 430);
2036 return FeatureBitsets[RequiredFeaturesRefs[Opcode]];
2037}
2038
2039
2040} // namespace llvm::Lanai_MC
2041
2042#endif // GET_COMPUTE_FEATURES
2043
2044#ifdef GET_AVAILABLE_OPCODE_CHECKER
2045#undef GET_AVAILABLE_OPCODE_CHECKER
2046
2047namespace llvm::Lanai_MC {
2048
2049bool isOpcodeAvailable(unsigned Opcode, const FeatureBitset &Features) {
2050 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
2051 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
2052 FeatureBitset MissingFeatures =
2053 (AvailableFeatures & RequiredFeatures) ^
2054 RequiredFeatures;
2055 return !MissingFeatures.any();
2056}
2057
2058} // namespace llvm::Lanai_MC
2059
2060#endif // GET_AVAILABLE_OPCODE_CHECKER
2061
2062#ifdef ENABLE_INSTR_PREDICATE_VERIFIER
2063#undef ENABLE_INSTR_PREDICATE_VERIFIER
2064
2065#include <sstream>
2066
2067namespace llvm::Lanai_MC {
2068
2069#ifndef NDEBUG
2070static const char *SubtargetFeatureNames[] = {
2071 nullptr
2072};
2073
2074#endif // NDEBUG
2075
2076void verifyInstructionPredicates(
2077 unsigned Opcode, const FeatureBitset &Features) {
2078#ifndef NDEBUG
2079 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
2080 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
2081 FeatureBitset MissingFeatures =
2082 (AvailableFeatures & RequiredFeatures) ^
2083 RequiredFeatures;
2084 if (MissingFeatures.any()) {
2085 std::ostringstream Msg;
2086 Msg << "Attempting to emit " << &LanaiInstrNameData[LanaiInstrNameIndices[Opcode]]
2087 << " instruction but the ";
2088 for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i)
2089 if (MissingFeatures.test(i))
2090 Msg << SubtargetFeatureNames[i] << " ";
2091 Msg << "predicate(s) are not met";
2092 report_fatal_error(Msg.str().c_str());
2093 }
2094#endif // NDEBUG
2095}
2096
2097} // namespace llvm::Lanai_MC
2098
2099#endif // ENABLE_INSTR_PREDICATE_VERIFIER
2100
2101#ifdef GET_INSTRMAP_INFO
2102#undef GET_INSTRMAP_INFO
2103
2104namespace llvm::Lanai {
2105
2106enum PostEncoderMethod {
2107 PostEncoderMethod_adjustPqBitsSpls
2108};
2109
2110// splsIdempotent
2111LLVM_READONLY
2112int32_t splsIdempotent(uint32_t Opcode) {
2113 using namespace Lanai;
2114 static constexpr uint32_t Table[][2] = {
2115 { LDBs_RI, LDBs_RI },
2116 { LDBz_RI, LDBz_RI },
2117 { LDHs_RI, LDHs_RI },
2118 { LDHz_RI, LDHz_RI },
2119 { STB_RI, STB_RI },
2120 { STH_RI, STH_RI },
2121 }; // End of Table
2122
2123 unsigned mid;
2124 unsigned start = 0;
2125 unsigned end = 6;
2126 while (start < end) {
2127 mid = start + (end - start) / 2;
2128 if (Opcode == Table[mid][0])
2129 break;
2130 if (Opcode < Table[mid][0])
2131 end = mid;
2132 else
2133 start = mid + 1;
2134 }
2135 if (start == end)
2136 return -1; // Instruction doesn't exist in this table.
2137
2138 return Table[mid][1];
2139}
2140
2141
2142} // namespace llvm::Lanai
2143
2144#endif // GET_INSTRMAP_INFO
2145
2146