1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Instruction Enum Values and Descriptors *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_INSTRINFO_ENUM
10#undef GET_INSTRINFO_ENUM
11
12namespace llvm::Lanai {
13
14 enum {
15 PHI = 0, // Target.td:1301
16 INLINEASM = 1, // Target.td:1307
17 INLINEASM_BR = 2, // Target.td:1313
18 CFI_INSTRUCTION = 3, // Target.td:1322
19 EH_LABEL = 4, // Target.td:1331
20 GC_LABEL = 5, // Target.td:1340
21 ANNOTATION_LABEL = 6, // Target.td:1349
22 KILL = 7, // Target.td:1357
23 EXTRACT_SUBREG = 8, // Target.td:1364
24 INSERT_SUBREG = 9, // Target.td:1370
25 IMPLICIT_DEF = 10, // Target.td:1377
26 INIT_UNDEF = 11, // Target.td:1386
27 SUBREG_TO_REG = 12, // Target.td:1393
28 COPY_TO_REGCLASS = 13, // Target.td:1399
29 DBG_VALUE = 14, // Target.td:1406
30 DBG_VALUE_LIST = 15, // Target.td:1413
31 DBG_INSTR_REF = 16, // Target.td:1420
32 DBG_PHI = 17, // Target.td:1427
33 DBG_LABEL = 18, // Target.td:1434
34 REG_SEQUENCE = 19, // Target.td:1441
35 COPY = 20, // Target.td:1448
36 COPY_LANEMASK = 21, // Target.td:1456
37 BUNDLE = 22, // Target.td:1463
38 LIFETIME_START = 23, // Target.td:1469
39 LIFETIME_END = 24, // Target.td:1476
40 PSEUDO_PROBE = 25, // Target.td:1483
41 ARITH_FENCE = 26, // Target.td:1490
42 STACKMAP = 27, // Target.td:1499
43 FENTRY_CALL = 28, // Target.td:1634
44 PATCHPOINT = 29, // Target.td:1507
45 LOAD_STACK_GUARD = 30, // Target.td:1525
46 PREALLOCATED_SETUP = 31, // Target.td:1533
47 PREALLOCATED_ARG = 32, // Target.td:1539
48 STATEPOINT = 33, // Target.td:1516
49 LOCAL_ESCAPE = 34, // Target.td:1545
50 FAULTING_OP = 35, // Target.td:1554
51 PATCHABLE_OP = 36, // Target.td:1574
52 PATCHABLE_FUNCTION_ENTER = 37, // Target.td:1582
53 PATCHABLE_RET = 38, // Target.td:1589
54 PATCHABLE_FUNCTION_EXIT = 39, // Target.td:1598
55 PATCHABLE_TAIL_CALL = 40, // Target.td:1606
56 PATCHABLE_EVENT_CALL = 41, // Target.td:1614
57 PATCHABLE_TYPED_EVENT_CALL = 42, // Target.td:1624
58 ICALL_BRANCH_FUNNEL = 43, // Target.td:1644
59 FAKE_USE = 44, // Target.td:1564
60 MEMBARRIER = 45, // Target.td:1650
61 JUMP_TABLE_DEBUG_INFO = 46, // Target.td:1658
62 RELOC_NONE = 47, // Target.td:1666
63 CONVERGENCECTRL_ENTRY = 48, // Target.td:1678
64 CONVERGENCECTRL_ANCHOR = 49, // Target.td:1674
65 CONVERGENCECTRL_LOOP = 50, // Target.td:1682
66 CONVERGENCECTRL_GLUE = 51, // Target.td:1686
67 G_ASSERT_SEXT = 52, // GenericOpcodes.td:1867
68 G_ASSERT_ZEXT = 53, // GenericOpcodes.td:1859
69 G_ASSERT_ALIGN = 54, // GenericOpcodes.td:1874
70 G_ADD = 55, // GenericOpcodes.td:300
71 G_SUB = 56, // GenericOpcodes.td:308
72 G_MUL = 57, // GenericOpcodes.td:316
73 G_SDIV = 58, // GenericOpcodes.td:324
74 G_UDIV = 59, // GenericOpcodes.td:332
75 G_SREM = 60, // GenericOpcodes.td:340
76 G_UREM = 61, // GenericOpcodes.td:348
77 G_SDIVREM = 62, // GenericOpcodes.td:356
78 G_UDIVREM = 63, // GenericOpcodes.td:364
79 G_AND = 64, // GenericOpcodes.td:372
80 G_OR = 65, // GenericOpcodes.td:380
81 G_XOR = 66, // GenericOpcodes.td:388
82 G_ABDS = 67, // GenericOpcodes.td:417
83 G_ABDU = 68, // GenericOpcodes.td:425
84 G_UAVGFLOOR = 69, // GenericOpcodes.td:433
85 G_UAVGCEIL = 70, // GenericOpcodes.td:440
86 G_SAVGFLOOR = 71, // GenericOpcodes.td:447
87 G_SAVGCEIL = 72, // GenericOpcodes.td:454
88 G_IMPLICIT_DEF = 73, // GenericOpcodes.td:110
89 G_PHI = 74, // GenericOpcodes.td:116
90 G_FRAME_INDEX = 75, // GenericOpcodes.td:122
91 G_GLOBAL_VALUE = 76, // GenericOpcodes.td:128
92 G_PTRAUTH_GLOBAL_VALUE = 77, // GenericOpcodes.td:134
93 G_CONSTANT_POOL = 78, // GenericOpcodes.td:140
94 G_EXTRACT = 79, // GenericOpcodes.td:1474
95 G_UNMERGE_VALUES = 80, // GenericOpcodes.td:1486
96 G_INSERT = 81, // GenericOpcodes.td:1494
97 G_MERGE_VALUES = 82, // GenericOpcodes.td:1504
98 G_BUILD_VECTOR = 83, // GenericOpcodes.td:1523
99 G_BUILD_VECTOR_TRUNC = 84, // GenericOpcodes.td:1532
100 G_CONCAT_VECTORS = 85, // GenericOpcodes.td:1539
101 G_PTRTOINT = 86, // GenericOpcodes.td:152
102 G_INTTOPTR = 87, // GenericOpcodes.td:146
103 G_BITCAST = 88, // GenericOpcodes.td:158
104 G_FREEZE = 89, // GenericOpcodes.td:277
105 G_CONSTANT_FOLD_BARRIER = 90, // GenericOpcodes.td:1881
106 G_INTRINSIC_FPTRUNC_ROUND = 91, // GenericOpcodes.td:1263
107 G_INTRINSIC_TRUNC = 92, // GenericOpcodes.td:1269
108 G_INTRINSIC_ROUND = 93, // GenericOpcodes.td:1275
109 G_INTRINSIC_LRINT = 94, // GenericOpcodes.td:1281
110 G_INTRINSIC_LLRINT = 95, // GenericOpcodes.td:1287
111 G_INTRINSIC_ROUNDEVEN = 96, // GenericOpcodes.td:1293
112 G_READCYCLECOUNTER = 97, // GenericOpcodes.td:1299
113 G_READSTEADYCOUNTER = 98, // GenericOpcodes.td:1305
114 G_LOAD = 99, // GenericOpcodes.td:1332
115 G_SEXTLOAD = 100, // GenericOpcodes.td:1340
116 G_ZEXTLOAD = 101, // GenericOpcodes.td:1348
117 G_INDEXED_LOAD = 102, // GenericOpcodes.td:1358
118 G_INDEXED_SEXTLOAD = 103, // GenericOpcodes.td:1366
119 G_INDEXED_ZEXTLOAD = 104, // GenericOpcodes.td:1374
120 G_STORE = 105, // GenericOpcodes.td:1382
121 G_INDEXED_STORE = 106, // GenericOpcodes.td:1390
122 G_ATOMIC_CMPXCHG_WITH_SUCCESS = 107, // GenericOpcodes.td:1400
123 G_ATOMIC_CMPXCHG = 108, // GenericOpcodes.td:1410
124 G_ATOMICRMW_XCHG = 109, // GenericOpcodes.td:1428
125 G_ATOMICRMW_ADD = 110, // GenericOpcodes.td:1429
126 G_ATOMICRMW_SUB = 111, // GenericOpcodes.td:1430
127 G_ATOMICRMW_AND = 112, // GenericOpcodes.td:1431
128 G_ATOMICRMW_NAND = 113, // GenericOpcodes.td:1432
129 G_ATOMICRMW_OR = 114, // GenericOpcodes.td:1433
130 G_ATOMICRMW_XOR = 115, // GenericOpcodes.td:1434
131 G_ATOMICRMW_MAX = 116, // GenericOpcodes.td:1435
132 G_ATOMICRMW_MIN = 117, // GenericOpcodes.td:1436
133 G_ATOMICRMW_UMAX = 118, // GenericOpcodes.td:1437
134 G_ATOMICRMW_UMIN = 119, // GenericOpcodes.td:1438
135 G_ATOMICRMW_FADD = 120, // GenericOpcodes.td:1439
136 G_ATOMICRMW_FSUB = 121, // GenericOpcodes.td:1440
137 G_ATOMICRMW_FMAX = 122, // GenericOpcodes.td:1441
138 G_ATOMICRMW_FMIN = 123, // GenericOpcodes.td:1442
139 G_ATOMICRMW_FMAXIMUM = 124, // GenericOpcodes.td:1443
140 G_ATOMICRMW_FMINIMUM = 125, // GenericOpcodes.td:1444
141 G_ATOMICRMW_FMAXIMUMNUM = 126, // GenericOpcodes.td:1445
142 G_ATOMICRMW_FMINIMUMNUM = 127, // GenericOpcodes.td:1446
143 G_ATOMICRMW_UINC_WRAP = 128, // GenericOpcodes.td:1447
144 G_ATOMICRMW_UDEC_WRAP = 129, // GenericOpcodes.td:1448
145 G_ATOMICRMW_USUB_COND = 130, // GenericOpcodes.td:1449
146 G_ATOMICRMW_USUB_SAT = 131, // GenericOpcodes.td:1450
147 G_FENCE = 132, // GenericOpcodes.td:1452
148 G_PREFETCH = 133, // GenericOpcodes.td:1459
149 G_BRCOND = 134, // GenericOpcodes.td:1594
150 G_BRINDIRECT = 135, // GenericOpcodes.td:1603
151 G_INVOKE_REGION_START = 136, // GenericOpcodes.td:1626
152 G_INTRINSIC = 137, // GenericOpcodes.td:1546
153 G_INTRINSIC_W_SIDE_EFFECTS = 138, // GenericOpcodes.td:1553
154 G_INTRINSIC_CONVERGENT = 139, // GenericOpcodes.td:1562
155 G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 140, // GenericOpcodes.td:1570
156 G_ANYEXT = 141, // GenericOpcodes.td:44
157 G_TRUNC = 142, // GenericOpcodes.td:83
158 G_TRUNC_SSAT_S = 143, // GenericOpcodes.td:90
159 G_TRUNC_SSAT_U = 144, // GenericOpcodes.td:97
160 G_TRUNC_USAT_U = 145, // GenericOpcodes.td:104
161 G_CONSTANT = 146, // GenericOpcodes.td:165
162 G_FCONSTANT = 147, // GenericOpcodes.td:172
163 G_VASTART = 148, // GenericOpcodes.td:178
164 G_VAARG = 149, // GenericOpcodes.td:185
165 G_SEXT = 150, // GenericOpcodes.td:52
166 G_SEXT_INREG = 151, // GenericOpcodes.td:66
167 G_ZEXT = 152, // GenericOpcodes.td:74
168 G_SHL = 153, // GenericOpcodes.td:396
169 G_LSHR = 154, // GenericOpcodes.td:403
170 G_ASHR = 155, // GenericOpcodes.td:410
171 G_FSHL = 156, // GenericOpcodes.td:462
172 G_FSHR = 157, // GenericOpcodes.td:470
173 G_ROTR = 158, // GenericOpcodes.td:477
174 G_ROTL = 159, // GenericOpcodes.td:484
175 G_ICMP = 160, // GenericOpcodes.td:491
176 G_FCMP = 161, // GenericOpcodes.td:498
177 G_SCMP = 162, // GenericOpcodes.td:505
178 G_UCMP = 163, // GenericOpcodes.td:512
179 G_SELECT = 164, // GenericOpcodes.td:519
180 G_UADDO = 165, // GenericOpcodes.td:584
181 G_UADDE = 166, // GenericOpcodes.td:592
182 G_USUBO = 167, // GenericOpcodes.td:614
183 G_USUBE = 168, // GenericOpcodes.td:620
184 G_SADDO = 169, // GenericOpcodes.td:599
185 G_SADDE = 170, // GenericOpcodes.td:607
186 G_SSUBO = 171, // GenericOpcodes.td:627
187 G_SSUBE = 172, // GenericOpcodes.td:634
188 G_UMULO = 173, // GenericOpcodes.td:641
189 G_SMULO = 174, // GenericOpcodes.td:649
190 G_UMULH = 175, // GenericOpcodes.td:658
191 G_SMULH = 176, // GenericOpcodes.td:667
192 G_UADDSAT = 177, // GenericOpcodes.td:679
193 G_SADDSAT = 178, // GenericOpcodes.td:687
194 G_USUBSAT = 179, // GenericOpcodes.td:695
195 G_SSUBSAT = 180, // GenericOpcodes.td:703
196 G_USHLSAT = 181, // GenericOpcodes.td:711
197 G_SSHLSAT = 182, // GenericOpcodes.td:719
198 G_SMULFIX = 183, // GenericOpcodes.td:731
199 G_UMULFIX = 184, // GenericOpcodes.td:738
200 G_SMULFIXSAT = 185, // GenericOpcodes.td:748
201 G_UMULFIXSAT = 186, // GenericOpcodes.td:755
202 G_SDIVFIX = 187, // GenericOpcodes.td:766
203 G_UDIVFIX = 188, // GenericOpcodes.td:773
204 G_SDIVFIXSAT = 189, // GenericOpcodes.td:783
205 G_UDIVFIXSAT = 190, // GenericOpcodes.td:790
206 G_FADD = 191, // GenericOpcodes.td:963
207 G_FSUB = 192, // GenericOpcodes.td:971
208 G_FMUL = 193, // GenericOpcodes.td:979
209 G_FMA = 194, // GenericOpcodes.td:988
210 G_FMAD = 195, // GenericOpcodes.td:997
211 G_FDIV = 196, // GenericOpcodes.td:1005
212 G_FREM = 197, // GenericOpcodes.td:1012
213 G_FMODF = 198, // GenericOpcodes.td:1019
214 G_FPOW = 199, // GenericOpcodes.td:1026
215 G_FPOWI = 200, // GenericOpcodes.td:1033
216 G_FEXP = 201, // GenericOpcodes.td:1040
217 G_FEXP2 = 202, // GenericOpcodes.td:1047
218 G_FEXP10 = 203, // GenericOpcodes.td:1054
219 G_FLOG = 204, // GenericOpcodes.td:1061
220 G_FLOG2 = 205, // GenericOpcodes.td:1068
221 G_FLOG10 = 206, // GenericOpcodes.td:1075
222 G_FLDEXP = 207, // GenericOpcodes.td:1082
223 G_FFREXP = 208, // GenericOpcodes.td:1089
224 G_FNEG = 209, // GenericOpcodes.td:801
225 G_FPEXT = 210, // GenericOpcodes.td:807
226 G_FPTRUNC = 211, // GenericOpcodes.td:813
227 G_FPTOSI = 212, // GenericOpcodes.td:819
228 G_FPTOUI = 213, // GenericOpcodes.td:825
229 G_SITOFP = 214, // GenericOpcodes.td:831
230 G_UITOFP = 215, // GenericOpcodes.td:837
231 G_FPTOSI_SAT = 216, // GenericOpcodes.td:843
232 G_FPTOUI_SAT = 217, // GenericOpcodes.td:849
233 G_FABS = 218, // GenericOpcodes.td:855
234 G_FCOPYSIGN = 219, // GenericOpcodes.td:861
235 G_IS_FPCLASS = 220, // GenericOpcodes.td:874
236 G_FCANONICALIZE = 221, // GenericOpcodes.td:867
237 G_FMINNUM = 222, // GenericOpcodes.td:887
238 G_FMAXNUM = 223, // GenericOpcodes.td:894
239 G_FMINNUM_IEEE = 224, // GenericOpcodes.td:912
240 G_FMAXNUM_IEEE = 225, // GenericOpcodes.td:919
241 G_FMINIMUM = 226, // GenericOpcodes.td:929
242 G_FMAXIMUM = 227, // GenericOpcodes.td:936
243 G_FMINIMUMNUM = 228, // GenericOpcodes.td:944
244 G_FMAXIMUMNUM = 229, // GenericOpcodes.td:951
245 G_GET_FPENV = 230, // GenericOpcodes.td:1219
246 G_SET_FPENV = 231, // GenericOpcodes.td:1226
247 G_RESET_FPENV = 232, // GenericOpcodes.td:1233
248 G_GET_FPMODE = 233, // GenericOpcodes.td:1240
249 G_SET_FPMODE = 234, // GenericOpcodes.td:1247
250 G_RESET_FPMODE = 235, // GenericOpcodes.td:1254
251 G_GET_ROUNDING = 236, // GenericOpcodes.td:1311
252 G_SET_ROUNDING = 237, // GenericOpcodes.td:1317
253 G_PTR_ADD = 238, // GenericOpcodes.td:526
254 G_PTRMASK = 239, // GenericOpcodes.td:534
255 G_SMIN = 240, // GenericOpcodes.td:541
256 G_SMAX = 241, // GenericOpcodes.td:549
257 G_UMIN = 242, // GenericOpcodes.td:557
258 G_UMAX = 243, // GenericOpcodes.td:565
259 G_ABS = 244, // GenericOpcodes.td:573
260 G_LROUND = 245, // GenericOpcodes.td:283
261 G_LLROUND = 246, // GenericOpcodes.td:289
262 G_BR = 247, // GenericOpcodes.td:1584
263 G_BRJT = 248, // GenericOpcodes.td:1614
264 G_VSCALE = 249, // GenericOpcodes.td:1514
265 G_INSERT_SUBVECTOR = 250, // GenericOpcodes.td:1658
266 G_EXTRACT_SUBVECTOR = 251, // GenericOpcodes.td:1665
267 G_INSERT_VECTOR_ELT = 252, // GenericOpcodes.td:1672
268 G_EXTRACT_VECTOR_ELT = 253, // GenericOpcodes.td:1679
269 G_SHUFFLE_VECTOR = 254, // GenericOpcodes.td:1689
270 G_SPLAT_VECTOR = 255, // GenericOpcodes.td:1696
271 G_STEP_VECTOR = 256, // GenericOpcodes.td:1703
272 G_VECTOR_COMPRESS = 257, // GenericOpcodes.td:1710
273 G_CTTZ = 258, // GenericOpcodes.td:205
274 G_CTTZ_ZERO_UNDEF = 259, // GenericOpcodes.td:211
275 G_CTLZ = 260, // GenericOpcodes.td:193
276 G_CTLZ_ZERO_UNDEF = 261, // GenericOpcodes.td:199
277 G_CTLS = 262, // GenericOpcodes.td:217
278 G_CTPOP = 263, // GenericOpcodes.td:223
279 G_BSWAP = 264, // GenericOpcodes.td:229
280 G_BITREVERSE = 265, // GenericOpcodes.td:235
281 G_FCEIL = 266, // GenericOpcodes.td:1096
282 G_FCOS = 267, // GenericOpcodes.td:1103
283 G_FSIN = 268, // GenericOpcodes.td:1110
284 G_FSINCOS = 269, // GenericOpcodes.td:1117
285 G_FTAN = 270, // GenericOpcodes.td:1124
286 G_FACOS = 271, // GenericOpcodes.td:1131
287 G_FASIN = 272, // GenericOpcodes.td:1138
288 G_FATAN = 273, // GenericOpcodes.td:1145
289 G_FATAN2 = 274, // GenericOpcodes.td:1152
290 G_FCOSH = 275, // GenericOpcodes.td:1159
291 G_FSINH = 276, // GenericOpcodes.td:1166
292 G_FTANH = 277, // GenericOpcodes.td:1173
293 G_FSQRT = 278, // GenericOpcodes.td:1183
294 G_FFLOOR = 279, // GenericOpcodes.td:1190
295 G_FRINT = 280, // GenericOpcodes.td:1197
296 G_FNEARBYINT = 281, // GenericOpcodes.td:1204
297 G_ADDRSPACE_CAST = 282, // GenericOpcodes.td:241
298 G_BLOCK_ADDR = 283, // GenericOpcodes.td:247
299 G_JUMP_TABLE = 284, // GenericOpcodes.td:253
300 G_DYN_STACKALLOC = 285, // GenericOpcodes.td:259
301 G_STACKSAVE = 286, // GenericOpcodes.td:265
302 G_STACKRESTORE = 287, // GenericOpcodes.td:271
303 G_STRICT_FADD = 288, // GenericOpcodes.td:1760
304 G_STRICT_FSUB = 289, // GenericOpcodes.td:1761
305 G_STRICT_FMUL = 290, // GenericOpcodes.td:1762
306 G_STRICT_FDIV = 291, // GenericOpcodes.td:1763
307 G_STRICT_FREM = 292, // GenericOpcodes.td:1764
308 G_STRICT_FMA = 293, // GenericOpcodes.td:1765
309 G_STRICT_FSQRT = 294, // GenericOpcodes.td:1766
310 G_STRICT_FLDEXP = 295, // GenericOpcodes.td:1767
311 G_READ_REGISTER = 296, // GenericOpcodes.td:1633
312 G_WRITE_REGISTER = 297, // GenericOpcodes.td:1643
313 G_MEMCPY = 298, // GenericOpcodes.td:1773
314 G_MEMCPY_INLINE = 299, // GenericOpcodes.td:1781
315 G_MEMMOVE = 300, // GenericOpcodes.td:1789
316 G_MEMSET = 301, // GenericOpcodes.td:1797
317 G_BZERO = 302, // GenericOpcodes.td:1804
318 G_TRAP = 303, // GenericOpcodes.td:1814
319 G_DEBUGTRAP = 304, // GenericOpcodes.td:1821
320 G_UBSANTRAP = 305, // GenericOpcodes.td:1827
321 G_VECREDUCE_SEQ_FADD = 306, // GenericOpcodes.td:1726
322 G_VECREDUCE_SEQ_FMUL = 307, // GenericOpcodes.td:1732
323 G_VECREDUCE_FADD = 308, // GenericOpcodes.td:1738
324 G_VECREDUCE_FMUL = 309, // GenericOpcodes.td:1739
325 G_VECREDUCE_FMAX = 310, // GenericOpcodes.td:1741
326 G_VECREDUCE_FMIN = 311, // GenericOpcodes.td:1742
327 G_VECREDUCE_FMAXIMUM = 312, // GenericOpcodes.td:1743
328 G_VECREDUCE_FMINIMUM = 313, // GenericOpcodes.td:1744
329 G_VECREDUCE_ADD = 314, // GenericOpcodes.td:1746
330 G_VECREDUCE_MUL = 315, // GenericOpcodes.td:1747
331 G_VECREDUCE_AND = 316, // GenericOpcodes.td:1748
332 G_VECREDUCE_OR = 317, // GenericOpcodes.td:1749
333 G_VECREDUCE_XOR = 318, // GenericOpcodes.td:1750
334 G_VECREDUCE_SMAX = 319, // GenericOpcodes.td:1751
335 G_VECREDUCE_SMIN = 320, // GenericOpcodes.td:1752
336 G_VECREDUCE_UMAX = 321, // GenericOpcodes.td:1753
337 G_VECREDUCE_UMIN = 322, // GenericOpcodes.td:1754
338 G_SBFX = 323, // GenericOpcodes.td:1839
339 G_UBFX = 324, // GenericOpcodes.td:1847
340 ADJCALLSTACKDOWN = 325, // LanaiInstrInfo.td:753
341 ADJCALLSTACKUP = 326, // LanaiInstrInfo.td:756
342 ADJDYNALLOC = 327, // LanaiInstrInfo.td:762
343 CALL = 328, // LanaiInstrInfo.td:727
344 CALLR = 329, // LanaiInstrInfo.td:728
345 ADDC_F_I_HI = 330, // LanaiInstrInfo.td:281
346 ADDC_F_I_LO = 331, // LanaiInstrInfo.td:277
347 ADDC_F_R = 332, // LanaiInstrInfo.td:293
348 ADDC_I_HI = 333, // LanaiInstrInfo.td:281
349 ADDC_I_LO = 334, // LanaiInstrInfo.td:277
350 ADDC_R = 335, // LanaiInstrInfo.td:293
351 ADD_F_I_HI = 336, // LanaiInstrInfo.td:281
352 ADD_F_I_LO = 337, // LanaiInstrInfo.td:277
353 ADD_F_R = 338, // LanaiInstrInfo.td:293
354 ADD_I_HI = 339, // LanaiInstrInfo.td:281
355 ADD_I_LO = 340, // LanaiInstrInfo.td:277
356 ADD_R = 341, // LanaiInstrInfo.td:293
357 AND_F_I_HI = 342, // LanaiInstrInfo.td:281
358 AND_F_I_LO = 343, // LanaiInstrInfo.td:277
359 AND_F_R = 344, // LanaiInstrInfo.td:306
360 AND_I_HI = 345, // LanaiInstrInfo.td:281
361 AND_I_LO = 346, // LanaiInstrInfo.td:277
362 AND_R = 347, // LanaiInstrInfo.td:306
363 BRCC = 348, // LanaiInstrInfo.td:685
364 BRIND_CC = 349, // LanaiInstrInfo.td:788
365 BRIND_CCA = 350, // LanaiInstrInfo.td:796
366 BRR = 351, // LanaiInstrInfo.td:808
367 BT = 352, // LanaiInstrInfo.td:679
368 JR = 353, // LanaiInstrInfo.td:690
369 LDADDR = 354, // LanaiInstrInfo.td:542
370 LDBs_RI = 355, // LanaiInstrInfo.td:580
371 LDBs_RR = 356, // LanaiInstrInfo.td:539
372 LDBz_RI = 357, // LanaiInstrInfo.td:577
373 LDBz_RR = 358, // LanaiInstrInfo.td:532
374 LDHs_RI = 359, // LanaiInstrInfo.td:574
375 LDHs_RR = 360, // LanaiInstrInfo.td:537
376 LDHz_RI = 361, // LanaiInstrInfo.td:571
377 LDHz_RR = 362, // LanaiInstrInfo.td:530
378 LDW_RI = 363, // LanaiInstrInfo.td:515
379 LDW_RR = 364, // LanaiInstrInfo.td:516
380 LDWz_RR = 365, // LanaiInstrInfo.td:524
381 LEADZ = 366, // LanaiInstrInfo.td:818
382 LOG0 = 367, // LanaiInstrInfo.td:249
383 LOG1 = 368, // LanaiInstrInfo.td:251
384 LOG2 = 369, // LanaiInstrInfo.td:253
385 LOG3 = 370, // LanaiInstrInfo.td:255
386 LOG4 = 371, // LanaiInstrInfo.td:257
387 MOVHI = 372, // LanaiInstrInfo.td:408
388 NOP = 373, // LanaiInstrInfo.td:245
389 OR_F_I_HI = 374, // LanaiInstrInfo.td:281
390 OR_F_I_LO = 375, // LanaiInstrInfo.td:277
391 OR_F_R = 376, // LanaiInstrInfo.td:306
392 OR_I_HI = 377, // LanaiInstrInfo.td:281
393 OR_I_LO = 378, // LanaiInstrInfo.td:277
394 OR_R = 379, // LanaiInstrInfo.td:306
395 POPC = 380, // LanaiInstrInfo.td:813
396 RET = 381, // LanaiInstrInfo.td:733
397 SA_F_I = 382, // LanaiInstrInfo.td:439
398 SA_I = 383, // LanaiInstrInfo.td:430
399 SCC = 384, // LanaiInstrInfo.td:768
400 SELECT = 385, // LanaiInstrInfo.td:775
401 SFSUB_F_RI_HI = 386, // LanaiInstrInfo.td:716
402 SFSUB_F_RI_LO = 387, // LanaiInstrInfo.td:712
403 SFSUB_F_RR = 388, // LanaiInstrInfo.td:708
404 SHL_F_R = 389, // LanaiInstrInfo.td:460
405 SHL_R = 390, // LanaiInstrInfo.td:448
406 SLI = 391, // LanaiInstrInfo.td:582
407 SL_F_I = 392, // LanaiInstrInfo.td:437
408 SL_I = 393, // LanaiInstrInfo.td:428
409 SRA_F_R = 394, // LanaiInstrInfo.td:466
410 SRA_R = 395, // LanaiInstrInfo.td:455
411 SRL_F_R = 396, // LanaiInstrInfo.td:463
412 SRL_R = 397, // LanaiInstrInfo.td:452
413 STADDR = 398, // LanaiInstrInfo.td:641
414 STB_RI = 399, // LanaiInstrInfo.td:672
415 STB_RR = 400, // LanaiInstrInfo.td:638
416 STH_RI = 401, // LanaiInstrInfo.td:669
417 STH_RR = 402, // LanaiInstrInfo.td:636
418 SUBB_F_I_HI = 403, // LanaiInstrInfo.td:281
419 SUBB_F_I_LO = 404, // LanaiInstrInfo.td:277
420 SUBB_F_R = 405, // LanaiInstrInfo.td:293
421 SUBB_I_HI = 406, // LanaiInstrInfo.td:281
422 SUBB_I_LO = 407, // LanaiInstrInfo.td:277
423 SUBB_R = 408, // LanaiInstrInfo.td:293
424 SUB_F_I_HI = 409, // LanaiInstrInfo.td:281
425 SUB_F_I_LO = 410, // LanaiInstrInfo.td:277
426 SUB_F_R = 411, // LanaiInstrInfo.td:293
427 SUB_I_HI = 412, // LanaiInstrInfo.td:281
428 SUB_I_LO = 413, // LanaiInstrInfo.td:277
429 SUB_R = 414, // LanaiInstrInfo.td:293
430 SW_RI = 415, // LanaiInstrInfo.td:631
431 SW_RR = 416, // LanaiInstrInfo.td:630
432 TRAILZ = 417, // LanaiInstrInfo.td:822
433 XOR_F_I_HI = 418, // LanaiInstrInfo.td:281
434 XOR_F_I_LO = 419, // LanaiInstrInfo.td:277
435 XOR_F_R = 420, // LanaiInstrInfo.td:306
436 XOR_I_HI = 421, // LanaiInstrInfo.td:281
437 XOR_I_LO = 422, // LanaiInstrInfo.td:277
438 XOR_R = 423, // LanaiInstrInfo.td:306
439 INSTRUCTION_LIST_END = 424
440 };
441
442} // namespace llvm::Lanai
443
444#endif // GET_INSTRINFO_ENUM
445
446#ifdef GET_INSTRINFO_SCHED_ENUM
447#undef GET_INSTRINFO_SCHED_ENUM
448
449namespace llvm::Lanai::Sched {
450
451 enum {
452 NoInstrModel = 0,
453 IIC_ALU_WriteALU = 1,
454 IIC_ALU = 2,
455 IIC_LD_WriteLD = 3,
456 IIC_LDSW_WriteLDSW = 4,
457 WriteLD = 5,
458 IIC_ST_WriteST = 6,
459 IIC_STSW_WriteSTSW = 7,
460 SCHED_LIST_END = 8
461 };
462
463} // namespace llvm::Lanai::Sched
464
465#endif // GET_INSTRINFO_SCHED_ENUM
466
467#if defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
468
469namespace llvm {
470
471struct LanaiInstrTable {
472 MCInstrDesc Insts[424];
473 static_assert(alignof(MCInstrDesc) >= alignof(MCPhysReg), "Unwanted padding between Insts and ImplicitOps");
474 MCPhysReg ImplicitOps[8];
475 char Padding[sizeof(MCOperandInfo) - sizeof ImplicitOps % sizeof(MCOperandInfo)];
476 static_assert(alignof(MCInstrDesc) >= alignof(MCOperandInfo), "Unwanted padding between Insts and OperandInfo");
477 MCOperandInfo OperandInfo[174];
478};
479} // namespace llvm
480
481#endif // defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
482
483#ifdef GET_INSTRINFO_MC_DESC
484#undef GET_INSTRINFO_MC_DESC
485
486namespace llvm {
487
488static_assert((sizeof LanaiInstrTable::ImplicitOps + sizeof LanaiInstrTable::Padding) % sizeof(MCOperandInfo) == 0);
489static constexpr unsigned LanaiOpInfoBase = (sizeof LanaiInstrTable::ImplicitOps + sizeof LanaiInstrTable::Padding) / sizeof(MCOperandInfo);
490
491extern const LanaiInstrTable LanaiDescs = {
492 {
493 { 423, 4, 1, 4, 1, 0, 0, LanaiOpInfoBase + 156, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR_R
494 { 422, 3, 1, 4, 1, 0, 0, LanaiOpInfoBase + 153, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR_I_LO
495 { 421, 3, 1, 4, 1, 0, 0, LanaiOpInfoBase + 153, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR_I_HI
496 { 420, 4, 1, 4, 1, 0, 1, LanaiOpInfoBase + 156, 6, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR_F_R
497 { 419, 3, 1, 4, 1, 0, 1, LanaiOpInfoBase + 153, 6, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR_F_I_LO
498 { 418, 3, 1, 4, 1, 0, 1, LanaiOpInfoBase + 153, 6, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR_F_I_HI
499 { 417, 2, 1, 4, 1, 0, 0, LanaiOpInfoBase + 151, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TRAILZ
500 { 416, 4, 0, 4, 6, 0, 0, LanaiOpInfoBase + 166, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SW_RR
501 { 415, 4, 0, 4, 6, 0, 0, LanaiOpInfoBase + 162, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SW_RI
502 { 414, 4, 1, 4, 1, 0, 0, LanaiOpInfoBase + 156, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_R
503 { 413, 3, 1, 4, 1, 0, 0, LanaiOpInfoBase + 153, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_I_LO
504 { 412, 3, 1, 4, 1, 0, 0, LanaiOpInfoBase + 153, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_I_HI
505 { 411, 4, 1, 4, 1, 0, 1, LanaiOpInfoBase + 156, 6, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_F_R
506 { 410, 3, 1, 4, 1, 0, 1, LanaiOpInfoBase + 153, 6, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_F_I_LO
507 { 409, 3, 1, 4, 1, 0, 1, LanaiOpInfoBase + 153, 6, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_F_I_HI
508 { 408, 4, 1, 4, 1, 1, 0, LanaiOpInfoBase + 156, 6, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBB_R
509 { 407, 3, 1, 4, 1, 1, 0, LanaiOpInfoBase + 153, 6, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBB_I_LO
510 { 406, 3, 1, 4, 1, 1, 0, LanaiOpInfoBase + 153, 6, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBB_I_HI
511 { 405, 4, 1, 4, 1, 1, 1, LanaiOpInfoBase + 156, 4, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBB_F_R
512 { 404, 3, 1, 4, 1, 1, 1, LanaiOpInfoBase + 153, 4, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBB_F_I_LO
513 { 403, 3, 1, 4, 1, 1, 1, LanaiOpInfoBase + 153, 4, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBB_F_I_HI
514 { 402, 4, 0, 4, 6, 0, 0, LanaiOpInfoBase + 166, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STH_RR
515 { 401, 4, 0, 4, 7, 0, 0, LanaiOpInfoBase + 162, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STH_RI
516 { 400, 4, 0, 4, 6, 0, 0, LanaiOpInfoBase + 166, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STB_RR
517 { 399, 4, 0, 4, 7, 0, 0, LanaiOpInfoBase + 162, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STB_RI
518 { 398, 2, 0, 4, 6, 0, 0, LanaiOpInfoBase + 34, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STADDR
519 { 397, 4, 1, 4, 1, 0, 0, LanaiOpInfoBase + 156, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SRL_R
520 { 396, 4, 1, 4, 1, 0, 1, LanaiOpInfoBase + 156, 6, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SRL_F_R
521 { 395, 4, 1, 4, 1, 0, 0, LanaiOpInfoBase + 156, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SRA_R
522 { 394, 4, 1, 4, 1, 0, 1, LanaiOpInfoBase + 156, 6, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SRA_F_R
523 { 393, 3, 1, 4, 1, 0, 0, LanaiOpInfoBase + 153, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SL_I
524 { 392, 3, 1, 4, 1, 0, 1, LanaiOpInfoBase + 153, 6, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SL_F_I
525 { 391, 2, 1, 4, 0, 0, 0, LanaiOpInfoBase + 34, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SLI
526 { 390, 4, 1, 4, 1, 0, 0, LanaiOpInfoBase + 156, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHL_R
527 { 389, 4, 1, 4, 1, 0, 1, LanaiOpInfoBase + 156, 6, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHL_F_R
528 { 388, 2, 0, 4, 1, 0, 1, LanaiOpInfoBase + 151, 6, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SFSUB_F_RR
529 { 387, 2, 0, 4, 1, 0, 1, LanaiOpInfoBase + 34, 6, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SFSUB_F_RI_LO
530 { 386, 2, 0, 4, 1, 0, 1, LanaiOpInfoBase + 34, 6, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SFSUB_F_RI_HI
531 { 385, 4, 1, 4, 1, 1, 0, LanaiOpInfoBase + 170, 6, 0|(1ULL<<MCID::Select)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SELECT
532 { 384, 2, 1, 4, 2, 1, 0, LanaiOpInfoBase + 34, 6, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SCC
533 { 383, 3, 1, 4, 1, 0, 0, LanaiOpInfoBase + 153, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SA_I
534 { 382, 3, 1, 4, 1, 0, 1, LanaiOpInfoBase + 153, 6, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SA_F_I
535 { 381, 0, 0, 4, 0, 1, 0, LanaiOpInfoBase + 1, 7, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RET
536 { 380, 2, 1, 4, 1, 0, 0, LanaiOpInfoBase + 151, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // POPC
537 { 379, 4, 1, 4, 1, 0, 0, LanaiOpInfoBase + 156, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OR_R
538 { 378, 3, 1, 4, 1, 0, 0, LanaiOpInfoBase + 153, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OR_I_LO
539 { 377, 3, 1, 4, 1, 0, 0, LanaiOpInfoBase + 153, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OR_I_HI
540 { 376, 4, 1, 4, 1, 0, 1, LanaiOpInfoBase + 156, 6, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OR_F_R
541 { 375, 3, 1, 4, 1, 0, 1, LanaiOpInfoBase + 153, 6, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OR_F_I_LO
542 { 374, 3, 1, 4, 1, 0, 1, LanaiOpInfoBase + 153, 6, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OR_F_I_HI
543 { 373, 0, 0, 4, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NOP
544 { 372, 2, 1, 4, 1, 0, 0, LanaiOpInfoBase + 34, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOVHI
545 { 371, 0, 0, 4, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOG4
546 { 370, 0, 0, 4, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOG3
547 { 369, 0, 0, 4, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOG2
548 { 368, 0, 0, 4, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOG1
549 { 367, 0, 0, 4, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOG0
550 { 366, 2, 1, 4, 1, 0, 0, LanaiOpInfoBase + 151, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LEADZ
551 { 365, 4, 1, 4, 5, 0, 0, LanaiOpInfoBase + 166, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDWz_RR
552 { 364, 4, 1, 4, 5, 0, 0, LanaiOpInfoBase + 166, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDW_RR
553 { 363, 4, 1, 4, 3, 0, 0, LanaiOpInfoBase + 162, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDW_RI
554 { 362, 4, 1, 4, 5, 0, 0, LanaiOpInfoBase + 166, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDHz_RR
555 { 361, 4, 1, 4, 4, 0, 0, LanaiOpInfoBase + 162, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDHz_RI
556 { 360, 4, 1, 4, 5, 0, 0, LanaiOpInfoBase + 166, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDHs_RR
557 { 359, 4, 1, 4, 4, 0, 0, LanaiOpInfoBase + 162, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDHs_RI
558 { 358, 4, 1, 4, 5, 0, 0, LanaiOpInfoBase + 166, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDBz_RR
559 { 357, 4, 1, 4, 4, 0, 0, LanaiOpInfoBase + 162, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDBz_RI
560 { 356, 4, 1, 4, 5, 0, 0, LanaiOpInfoBase + 166, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDBs_RR
561 { 355, 4, 1, 4, 4, 0, 0, LanaiOpInfoBase + 162, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDBs_RI
562 { 354, 2, 1, 4, 3, 0, 0, LanaiOpInfoBase + 34, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDADDR
563 { 353, 1, 0, 4, 1, 0, 0, LanaiOpInfoBase + 28, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JR
564 { 352, 1, 0, 4, 2, 0, 0, LanaiOpInfoBase + 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BT
565 { 351, 2, 0, 4, 0, 1, 0, LanaiOpInfoBase + 160, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BRR
566 { 350, 3, 0, 4, 1, 1, 0, LanaiOpInfoBase + 153, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BRIND_CCA
567 { 349, 2, 0, 4, 1, 1, 0, LanaiOpInfoBase + 34, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BRIND_CC
568 { 348, 2, 0, 4, 2, 1, 0, LanaiOpInfoBase + 9, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BRCC
569 { 347, 4, 1, 4, 1, 0, 0, LanaiOpInfoBase + 156, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND_R
570 { 346, 3, 1, 4, 1, 0, 0, LanaiOpInfoBase + 153, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND_I_LO
571 { 345, 3, 1, 4, 1, 0, 0, LanaiOpInfoBase + 153, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND_I_HI
572 { 344, 4, 1, 4, 1, 0, 1, LanaiOpInfoBase + 156, 6, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND_F_R
573 { 343, 3, 1, 4, 1, 0, 1, LanaiOpInfoBase + 153, 6, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND_F_I_LO
574 { 342, 3, 1, 4, 1, 0, 1, LanaiOpInfoBase + 153, 6, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND_F_I_HI
575 { 341, 4, 1, 4, 1, 0, 0, LanaiOpInfoBase + 156, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_R
576 { 340, 3, 1, 4, 1, 0, 0, LanaiOpInfoBase + 153, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_I_LO
577 { 339, 3, 1, 4, 1, 0, 0, LanaiOpInfoBase + 153, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_I_HI
578 { 338, 4, 1, 4, 1, 0, 1, LanaiOpInfoBase + 156, 6, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_F_R
579 { 337, 3, 1, 4, 1, 0, 1, LanaiOpInfoBase + 153, 6, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_F_I_LO
580 { 336, 3, 1, 4, 1, 0, 1, LanaiOpInfoBase + 153, 6, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_F_I_HI
581 { 335, 4, 1, 4, 1, 1, 0, LanaiOpInfoBase + 156, 6, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC_R
582 { 334, 3, 1, 4, 1, 1, 0, LanaiOpInfoBase + 153, 6, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC_I_LO
583 { 333, 3, 1, 4, 1, 1, 0, LanaiOpInfoBase + 153, 6, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC_I_HI
584 { 332, 4, 1, 4, 1, 1, 1, LanaiOpInfoBase + 156, 4, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC_F_R
585 { 331, 3, 1, 4, 1, 1, 1, LanaiOpInfoBase + 153, 4, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC_F_I_LO
586 { 330, 3, 1, 4, 1, 1, 1, LanaiOpInfoBase + 153, 4, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC_F_I_HI
587 { 329, 1, 0, 4, 0, 1, 1, LanaiOpInfoBase + 28, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CALLR
588 { 328, 1, 0, 4, 0, 1, 1, LanaiOpInfoBase + 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CALL
589 { 327, 2, 1, 4, 0, 1, 1, LanaiOpInfoBase + 151, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADJDYNALLOC
590 { 326, 2, 0, 4, 0, 1, 1, LanaiOpInfoBase + 20, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADJCALLSTACKUP
591 { 325, 2, 0, 4, 0, 1, 1, LanaiOpInfoBase + 20, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADJCALLSTACKDOWN
592 { 324, 4, 1, 0, 0, 0, 0, LanaiOpInfoBase + 147, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UBFX
593 { 323, 4, 1, 0, 0, 0, 0, LanaiOpInfoBase + 147, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SBFX
594 { 322, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_UMIN
595 { 321, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_UMAX
596 { 320, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SMIN
597 { 319, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SMAX
598 { 318, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_XOR
599 { 317, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_OR
600 { 316, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_AND
601 { 315, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_MUL
602 { 314, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_ADD
603 { 313, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMINIMUM
604 { 312, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMAXIMUM
605 { 311, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMIN
606 { 310, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMAX
607 { 309, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMUL
608 { 308, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FADD
609 { 307, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SEQ_FMUL
610 { 306, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SEQ_FADD
611 { 305, 1, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UBSANTRAP
612 { 304, 0, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_DEBUGTRAP
613 { 303, 0, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRAP
614 { 302, 3, 0, 0, 0, 0, 0, LanaiOpInfoBase + 57, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BZERO
615 { 301, 4, 0, 0, 0, 0, 0, LanaiOpInfoBase + 143, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMSET
616 { 300, 4, 0, 0, 0, 0, 0, LanaiOpInfoBase + 143, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMMOVE
617 { 299, 3, 0, 0, 0, 0, 0, LanaiOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMCPY_INLINE
618 { 298, 4, 0, 0, 0, 0, 0, LanaiOpInfoBase + 143, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMCPY
619 { 297, 2, 0, 0, 0, 0, 0, LanaiOpInfoBase + 141, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_WRITE_REGISTER
620 { 296, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_READ_REGISTER
621 { 295, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FLDEXP
622 { 294, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FSQRT
623 { 293, 4, 1, 0, 0, 0, 0, LanaiOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FMA
624 { 292, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FREM
625 { 291, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FDIV
626 { 290, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FMUL
627 { 289, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FSUB
628 { 288, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FADD
629 { 287, 1, 0, 0, 0, 0, 0, LanaiOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STACKRESTORE
630 { 286, 1, 1, 0, 0, 0, 0, LanaiOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STACKSAVE
631 { 285, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 68, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_DYN_STACKALLOC
632 { 284, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_JUMP_TABLE
633 { 283, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BLOCK_ADDR
634 { 282, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ADDRSPACE_CAST
635 { 281, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FNEARBYINT
636 { 280, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FRINT
637 { 279, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FFLOOR
638 { 278, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSQRT
639 { 277, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FTANH
640 { 276, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSINH
641 { 275, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCOSH
642 { 274, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FATAN2
643 { 273, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FATAN
644 { 272, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FASIN
645 { 271, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FACOS
646 { 270, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FTAN
647 { 269, 3, 2, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSINCOS
648 { 268, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSIN
649 { 267, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCOS
650 { 266, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCEIL
651 { 265, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BITREVERSE
652 { 264, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BSWAP
653 { 263, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTPOP
654 { 262, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTLS
655 { 261, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTLZ_ZERO_UNDEF
656 { 260, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTLZ
657 { 259, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTTZ_ZERO_UNDEF
658 { 258, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTTZ
659 { 257, 4, 1, 0, 0, 0, 0, LanaiOpInfoBase + 137, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECTOR_COMPRESS
660 { 256, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STEP_VECTOR
661 { 255, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SPLAT_VECTOR
662 { 254, 4, 1, 0, 0, 0, 0, LanaiOpInfoBase + 133, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SHUFFLE_VECTOR
663 { 253, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_EXTRACT_VECTOR_ELT
664 { 252, 4, 1, 0, 0, 0, 0, LanaiOpInfoBase + 126, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INSERT_VECTOR_ELT
665 { 251, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 57, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_EXTRACT_SUBVECTOR
666 { 250, 4, 1, 0, 0, 0, 0, LanaiOpInfoBase + 62, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INSERT_SUBVECTOR
667 { 249, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VSCALE
668 { 248, 3, 0, 0, 0, 0, 0, LanaiOpInfoBase + 123, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BRJT
669 { 247, 1, 0, 0, 0, 0, 0, LanaiOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BR
670 { 246, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LLROUND
671 { 245, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LROUND
672 { 244, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ABS
673 { 243, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMAX
674 { 242, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMIN
675 { 241, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMAX
676 { 240, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMIN
677 { 239, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTRMASK
678 { 238, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTR_ADD
679 { 237, 1, 0, 0, 0, 0, 0, LanaiOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SET_ROUNDING
680 { 236, 1, 1, 0, 0, 0, 0, LanaiOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GET_ROUNDING
681 { 235, 0, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_RESET_FPMODE
682 { 234, 1, 0, 0, 0, 0, 0, LanaiOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SET_FPMODE
683 { 233, 1, 1, 0, 0, 0, 0, LanaiOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GET_FPMODE
684 { 232, 0, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_RESET_FPENV
685 { 231, 1, 0, 0, 0, 0, 0, LanaiOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SET_FPENV
686 { 230, 1, 1, 0, 0, 0, 0, LanaiOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GET_FPENV
687 { 229, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXIMUMNUM
688 { 228, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINIMUMNUM
689 { 227, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXIMUM
690 { 226, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINIMUM
691 { 225, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXNUM_IEEE
692 { 224, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINNUM_IEEE
693 { 223, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXNUM
694 { 222, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINNUM
695 { 221, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCANONICALIZE
696 { 220, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 97, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_IS_FPCLASS
697 { 219, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCOPYSIGN
698 { 218, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FABS
699 { 217, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOUI_SAT
700 { 216, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOSI_SAT
701 { 215, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UITOFP
702 { 214, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SITOFP
703 { 213, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOUI
704 { 212, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOSI
705 { 211, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTRUNC
706 { 210, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPEXT
707 { 209, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FNEG
708 { 208, 3, 2, 0, 0, 0, 0, LanaiOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FFREXP
709 { 207, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLDEXP
710 { 206, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLOG10
711 { 205, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLOG2
712 { 204, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLOG
713 { 203, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FEXP10
714 { 202, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FEXP2
715 { 201, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FEXP
716 { 200, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPOWI
717 { 199, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPOW
718 { 198, 3, 2, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMODF
719 { 197, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FREM
720 { 196, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FDIV
721 { 195, 4, 1, 0, 0, 0, 0, LanaiOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAD
722 { 194, 4, 1, 0, 0, 0, 0, LanaiOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMA
723 { 193, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMUL
724 { 192, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSUB
725 { 191, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FADD
726 { 190, 4, 1, 0, 0, 0, 0, LanaiOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIVFIXSAT
727 { 189, 4, 1, 0, 0, 0, 0, LanaiOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIVFIXSAT
728 { 188, 4, 1, 0, 0, 0, 0, LanaiOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIVFIX
729 { 187, 4, 1, 0, 0, 0, 0, LanaiOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIVFIX
730 { 186, 4, 1, 0, 0, 0, 0, LanaiOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULFIXSAT
731 { 185, 4, 1, 0, 0, 0, 0, LanaiOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULFIXSAT
732 { 184, 4, 1, 0, 0, 0, 0, LanaiOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULFIX
733 { 183, 4, 1, 0, 0, 0, 0, LanaiOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULFIX
734 { 182, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSHLSAT
735 { 181, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USHLSAT
736 { 180, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSUBSAT
737 { 179, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USUBSAT
738 { 178, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SADDSAT
739 { 177, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UADDSAT
740 { 176, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULH
741 { 175, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULH
742 { 174, 4, 2, 0, 0, 0, 0, LanaiOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULO
743 { 173, 4, 2, 0, 0, 0, 0, LanaiOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULO
744 { 172, 5, 2, 0, 0, 0, 0, LanaiOpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSUBE
745 { 171, 4, 2, 0, 0, 0, 0, LanaiOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSUBO
746 { 170, 5, 2, 0, 0, 0, 0, LanaiOpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SADDE
747 { 169, 4, 2, 0, 0, 0, 0, LanaiOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SADDO
748 { 168, 5, 2, 0, 0, 0, 0, LanaiOpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USUBE
749 { 167, 4, 2, 0, 0, 0, 0, LanaiOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USUBO
750 { 166, 5, 2, 0, 0, 0, 0, LanaiOpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UADDE
751 { 165, 4, 2, 0, 0, 0, 0, LanaiOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UADDO
752 { 164, 4, 1, 0, 0, 0, 0, LanaiOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SELECT
753 { 163, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 111, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UCMP
754 { 162, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 111, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SCMP
755 { 161, 4, 1, 0, 0, 0, 0, LanaiOpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCMP
756 { 160, 4, 1, 0, 0, 0, 0, LanaiOpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ICMP
757 { 159, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ROTL
758 { 158, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ROTR
759 { 157, 4, 1, 0, 0, 0, 0, LanaiOpInfoBase + 103, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSHR
760 { 156, 4, 1, 0, 0, 0, 0, LanaiOpInfoBase + 103, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSHL
761 { 155, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASHR
762 { 154, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LSHR
763 { 153, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SHL
764 { 152, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ZEXT
765 { 151, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SEXT_INREG
766 { 150, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SEXT
767 { 149, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 97, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VAARG
768 { 148, 1, 0, 0, 0, 0, 0, LanaiOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VASTART
769 { 147, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCONSTANT
770 { 146, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONSTANT
771 { 145, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC_USAT_U
772 { 144, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC_SSAT_U
773 { 143, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC_SSAT_S
774 { 142, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC
775 { 141, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ANYEXT
776 { 140, 1, 0, 0, 0, 0, 0, LanaiOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
777 { 139, 1, 0, 0, 0, 0, 0, LanaiOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_INTRINSIC_CONVERGENT
778 { 138, 1, 0, 0, 0, 0, 0, LanaiOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_W_SIDE_EFFECTS
779 { 137, 1, 0, 0, 0, 0, 0, LanaiOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC
780 { 136, 0, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INVOKE_REGION_START
781 { 135, 1, 0, 0, 0, 0, 0, LanaiOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BRINDIRECT
782 { 134, 2, 0, 0, 0, 0, 0, LanaiOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BRCOND
783 { 133, 4, 0, 0, 0, 0, 0, LanaiOpInfoBase + 93, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PREFETCH
784 { 132, 2, 0, 0, 0, 0, 0, LanaiOpInfoBase + 20, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FENCE
785 { 131, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_USUB_SAT
786 { 130, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_USUB_COND
787 { 129, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UDEC_WRAP
788 { 128, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UINC_WRAP
789 { 127, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMINIMUMNUM
790 { 126, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMAXIMUMNUM
791 { 125, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMINIMUM
792 { 124, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMAXIMUM
793 { 123, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMIN
794 { 122, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMAX
795 { 121, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FSUB
796 { 120, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FADD
797 { 119, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UMIN
798 { 118, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UMAX
799 { 117, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_MIN
800 { 116, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_MAX
801 { 115, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_XOR
802 { 114, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_OR
803 { 113, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_NAND
804 { 112, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_AND
805 { 111, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_SUB
806 { 110, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_ADD
807 { 109, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_XCHG
808 { 108, 4, 1, 0, 0, 0, 0, LanaiOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMIC_CMPXCHG
809 { 107, 5, 2, 0, 0, 0, 0, LanaiOpInfoBase + 81, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
810 { 106, 5, 1, 0, 0, 0, 0, LanaiOpInfoBase + 76, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_STORE
811 { 105, 2, 0, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STORE
812 { 104, 5, 2, 0, 0, 0, 0, LanaiOpInfoBase + 71, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_ZEXTLOAD
813 { 103, 5, 2, 0, 0, 0, 0, LanaiOpInfoBase + 71, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_SEXTLOAD
814 { 102, 5, 2, 0, 0, 0, 0, LanaiOpInfoBase + 71, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_LOAD
815 { 101, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ZEXTLOAD
816 { 100, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SEXTLOAD
817 { 99, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LOAD
818 { 98, 1, 1, 0, 0, 0, 0, LanaiOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_READSTEADYCOUNTER
819 { 97, 1, 1, 0, 0, 0, 0, LanaiOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_READCYCLECOUNTER
820 { 96, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_ROUNDEVEN
821 { 95, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_LLRINT
822 { 94, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_LRINT
823 { 93, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_ROUND
824 { 92, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_TRUNC
825 { 91, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 68, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_FPTRUNC_ROUND
826 { 90, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONSTANT_FOLD_BARRIER
827 { 89, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FREEZE
828 { 88, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BITCAST
829 { 87, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTTOPTR
830 { 86, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTRTOINT
831 { 85, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONCAT_VECTORS
832 { 84, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BUILD_VECTOR_TRUNC
833 { 83, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BUILD_VECTOR
834 { 82, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MERGE_VALUES
835 { 81, 4, 1, 0, 0, 0, 0, LanaiOpInfoBase + 62, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INSERT
836 { 80, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UNMERGE_VALUES
837 { 79, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 57, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_EXTRACT
838 { 78, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONSTANT_POOL
839 { 77, 5, 1, 0, 0, 0, 0, LanaiOpInfoBase + 52, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTRAUTH_GLOBAL_VALUE
840 { 76, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GLOBAL_VALUE
841 { 75, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FRAME_INDEX
842 { 74, 1, 1, 0, 0, 0, 0, LanaiOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PHI
843 { 73, 1, 1, 0, 0, 0, 0, LanaiOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_IMPLICIT_DEF
844 { 72, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SAVGCEIL
845 { 71, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SAVGFLOOR
846 { 70, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UAVGCEIL
847 { 69, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UAVGFLOOR
848 { 68, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ABDU
849 { 67, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ABDS
850 { 66, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_XOR
851 { 65, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_OR
852 { 64, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_AND
853 { 63, 4, 2, 0, 0, 0, 0, LanaiOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIVREM
854 { 62, 4, 2, 0, 0, 0, 0, LanaiOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIVREM
855 { 61, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UREM
856 { 60, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SREM
857 { 59, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIV
858 { 58, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIV
859 { 57, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MUL
860 { 56, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SUB
861 { 55, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ADD
862 { 54, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASSERT_ALIGN
863 { 53, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASSERT_ZEXT
864 { 52, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASSERT_SEXT
865 { 51, 1, 0, 0, 0, 0, 0, LanaiOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_GLUE
866 { 50, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_LOOP
867 { 49, 1, 1, 0, 0, 0, 0, LanaiOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_ANCHOR
868 { 48, 1, 1, 0, 0, 0, 0, LanaiOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_ENTRY
869 { 47, 1, 0, 0, 0, 0, 0, LanaiOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RELOC_NONE
870 { 46, 1, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JUMP_TABLE_DEBUG_INFO
871 { 45, 0, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMBARRIER
872 { 44, 0, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FAKE_USE
873 { 43, 0, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ICALL_BRANCH_FUNNEL
874 { 42, 3, 0, 0, 0, 0, 0, LanaiOpInfoBase + 36, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_13903
875 { 41, 2, 0, 0, 0, 0, 0, LanaiOpInfoBase + 34, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_13902
876 { 40, 0, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_TAIL_CALL
877 { 39, 0, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_FUNCTION_EXIT
878 { 38, 0, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_RET
879 { 37, 0, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_FUNCTION_ENTER
880 { 36, 0, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_OP
881 { 35, 1, 1, 0, 0, 0, 0, LanaiOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FAULTING_OP
882 { 34, 2, 0, 0, 0, 0, 0, LanaiOpInfoBase + 32, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_ESCAPE
883 { 33, 0, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STATEPOINT
884 { 32, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 29, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_13901
885 { 31, 1, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PREALLOCATED_SETUP
886 { 30, 1, 1, 0, 0, 0, 0, LanaiOpInfoBase + 28, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_13542
887 { 29, 6, 1, 0, 0, 0, 0, LanaiOpInfoBase + 22, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHPOINT
888 { 28, 0, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FENTRY_CALL
889 { 27, 2, 0, 0, 0, 0, 0, LanaiOpInfoBase + 20, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STACKMAP
890 { 26, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 18, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARITH_FENCE
891 { 25, 4, 0, 0, 0, 0, 0, LanaiOpInfoBase + 14, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PSEUDO_PROBE
892 { 24, 1, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LIFETIME_END
893 { 23, 1, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LIFETIME_START
894 { 22, 0, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BUNDLE
895 { 21, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 11, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_LANEMASK
896 { 20, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY
897 { 19, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REG_SEQUENCE
898 { 18, 1, 0, 0, 0, 0, 0, LanaiOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_LABEL
899 { 17, 0, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_PHI
900 { 16, 0, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_INSTR_REF
901 { 15, 0, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_VALUE_LIST
902 { 14, 0, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_VALUE
903 { 13, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_TO_REGCLASS
904 { 12, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBREG_TO_REG
905 { 11, 1, 1, 0, 0, 0, 0, LanaiOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INIT_UNDEF
906 { 10, 1, 1, 0, 0, 0, 0, LanaiOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // IMPLICIT_DEF
907 { 9, 4, 1, 0, 0, 0, 0, LanaiOpInfoBase + 5, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INSERT_SUBREG
908 { 8, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTRACT_SUBREG
909 { 7, 0, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // KILL
910 { 6, 1, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ANNOTATION_LABEL
911 { 5, 1, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GC_LABEL
912 { 4, 1, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EH_LABEL
913 { 3, 1, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CFI_INSTRUCTION
914 { 2, 0, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INLINEASM_BR
915 { 1, 0, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INLINEASM
916 { 0, 1, 1, 0, 0, 0, 0, LanaiOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PHI
917 }, {
918 /* 0 */
919 /* 0 */ Lanai::SP, Lanai::SP,
920 /* 2 */ Lanai::SP, Lanai::RCA,
921 /* 4 */ Lanai::SR, Lanai::SR,
922 /* 6 */ Lanai::SR,
923 /* 7 */ Lanai::RCA,
924 }, {
925 0
926 }, {
927 /* 0 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
928 /* 1 */
929 /* 1 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
930 /* 2 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
931 /* 5 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
932 /* 9 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
933 /* 11 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
934 /* 14 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
935 /* 18 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) },
936 /* 20 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
937 /* 22 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
938 /* 28 */ { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
939 /* 29 */ { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
940 /* 32 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
941 /* 34 */ { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
942 /* 36 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
943 /* 39 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
944 /* 42 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
945 /* 45 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
946 /* 49 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
947 /* 50 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
948 /* 52 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
949 /* 57 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
950 /* 60 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
951 /* 62 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
952 /* 66 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
953 /* 68 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
954 /* 71 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
955 /* 76 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
956 /* 81 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
957 /* 86 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
958 /* 90 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
959 /* 93 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
960 /* 97 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
961 /* 100 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
962 /* 103 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
963 /* 107 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
964 /* 111 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
965 /* 114 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
966 /* 119 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
967 /* 123 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
968 /* 126 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
969 /* 130 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
970 /* 133 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
971 /* 137 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
972 /* 141 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
973 /* 143 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
974 /* 147 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
975 /* 151 */ { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
976 /* 153 */ { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
977 /* 156 */ { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 },
978 /* 160 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
979 /* 162 */ { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
980 /* 166 */ { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
981 /* 170 */ { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
982 }
983};
984
985
986#ifdef __GNUC__
987#pragma GCC diagnostic push
988#pragma GCC diagnostic ignored "-Woverlength-strings"
989#endif
990extern const char LanaiInstrNameData[] = {
991 /* 0 */ "G_FLOG10\000"
992 /* 9 */ "G_FEXP10\000"
993 /* 18 */ "LOG0\000"
994 /* 23 */ "LOG1\000"
995 /* 28 */ "G_FLOG2\000"
996 /* 36 */ "G_FATAN2\000"
997 /* 45 */ "G_FEXP2\000"
998 /* 53 */ "LOG3\000"
999 /* 58 */ "LOG4\000"
1000 /* 63 */ "BRIND_CCA\000"
1001 /* 73 */ "G_FMA\000"
1002 /* 79 */ "G_STRICT_FMA\000"
1003 /* 92 */ "G_FSUB\000"
1004 /* 99 */ "G_STRICT_FSUB\000"
1005 /* 113 */ "G_ATOMICRMW_FSUB\000"
1006 /* 130 */ "G_SUB\000"
1007 /* 136 */ "G_ATOMICRMW_SUB\000"
1008 /* 152 */ "BRCC\000"
1009 /* 157 */ "SCC\000"
1010 /* 161 */ "BRIND_CC\000"
1011 /* 170 */ "G_INTRINSIC\000"
1012 /* 182 */ "G_FPTRUNC\000"
1013 /* 192 */ "G_INTRINSIC_TRUNC\000"
1014 /* 210 */ "G_TRUNC\000"
1015 /* 218 */ "G_BUILD_VECTOR_TRUNC\000"
1016 /* 239 */ "G_DYN_STACKALLOC\000"
1017 /* 256 */ "ADJDYNALLOC\000"
1018 /* 268 */ "POPC\000"
1019 /* 273 */ "G_FMAD\000"
1020 /* 280 */ "G_INDEXED_SEXTLOAD\000"
1021 /* 299 */ "G_SEXTLOAD\000"
1022 /* 310 */ "G_INDEXED_ZEXTLOAD\000"
1023 /* 329 */ "G_ZEXTLOAD\000"
1024 /* 340 */ "G_INDEXED_LOAD\000"
1025 /* 355 */ "G_LOAD\000"
1026 /* 362 */ "G_VECREDUCE_FADD\000"
1027 /* 379 */ "G_FADD\000"
1028 /* 386 */ "G_VECREDUCE_SEQ_FADD\000"
1029 /* 407 */ "G_STRICT_FADD\000"
1030 /* 421 */ "G_ATOMICRMW_FADD\000"
1031 /* 438 */ "G_VECREDUCE_ADD\000"
1032 /* 454 */ "G_ADD\000"
1033 /* 460 */ "G_PTR_ADD\000"
1034 /* 470 */ "G_ATOMICRMW_ADD\000"
1035 /* 486 */ "G_ATOMICRMW_NAND\000"
1036 /* 503 */ "G_VECREDUCE_AND\000"
1037 /* 519 */ "G_AND\000"
1038 /* 525 */ "G_ATOMICRMW_AND\000"
1039 /* 541 */ "LIFETIME_END\000"
1040 /* 554 */ "G_BRCOND\000"
1041 /* 563 */ "G_ATOMICRMW_USUB_COND\000"
1042 /* 585 */ "G_LLROUND\000"
1043 /* 595 */ "G_LROUND\000"
1044 /* 604 */ "G_INTRINSIC_ROUND\000"
1045 /* 622 */ "G_INTRINSIC_FPTRUNC_ROUND\000"
1046 /* 648 */ "LOAD_STACK_GUARD\000"
1047 /* 665 */ "PSEUDO_PROBE\000"
1048 /* 678 */ "G_SSUBE\000"
1049 /* 686 */ "G_USUBE\000"
1050 /* 694 */ "G_FENCE\000"
1051 /* 702 */ "ARITH_FENCE\000"
1052 /* 714 */ "REG_SEQUENCE\000"
1053 /* 727 */ "G_SADDE\000"
1054 /* 735 */ "G_UADDE\000"
1055 /* 743 */ "G_GET_FPMODE\000"
1056 /* 756 */ "G_RESET_FPMODE\000"
1057 /* 771 */ "G_SET_FPMODE\000"
1058 /* 784 */ "G_FMINNUM_IEEE\000"
1059 /* 799 */ "G_FMAXNUM_IEEE\000"
1060 /* 814 */ "G_VSCALE\000"
1061 /* 823 */ "G_JUMP_TABLE\000"
1062 /* 836 */ "BUNDLE\000"
1063 /* 843 */ "G_MEMCPY_INLINE\000"
1064 /* 859 */ "RELOC_NONE\000"
1065 /* 870 */ "LOCAL_ESCAPE\000"
1066 /* 883 */ "G_STACKRESTORE\000"
1067 /* 898 */ "G_INDEXED_STORE\000"
1068 /* 914 */ "G_STORE\000"
1069 /* 922 */ "G_BITREVERSE\000"
1070 /* 935 */ "FAKE_USE\000"
1071 /* 944 */ "DBG_VALUE\000"
1072 /* 954 */ "G_GLOBAL_VALUE\000"
1073 /* 969 */ "G_PTRAUTH_GLOBAL_VALUE\000"
1074 /* 992 */ "CONVERGENCECTRL_GLUE\000"
1075 /* 1013 */ "G_STACKSAVE\000"
1076 /* 1025 */ "G_MEMMOVE\000"
1077 /* 1035 */ "G_FREEZE\000"
1078 /* 1044 */ "G_FCANONICALIZE\000"
1079 /* 1060 */ "G_FMODF\000"
1080 /* 1068 */ "G_CTLZ_ZERO_UNDEF\000"
1081 /* 1086 */ "G_CTTZ_ZERO_UNDEF\000"
1082 /* 1104 */ "INIT_UNDEF\000"
1083 /* 1115 */ "G_IMPLICIT_DEF\000"
1084 /* 1130 */ "DBG_INSTR_REF\000"
1085 /* 1144 */ "G_FNEG\000"
1086 /* 1151 */ "EXTRACT_SUBREG\000"
1087 /* 1166 */ "INSERT_SUBREG\000"
1088 /* 1180 */ "G_SEXT_INREG\000"
1089 /* 1193 */ "SUBREG_TO_REG\000"
1090 /* 1207 */ "G_ATOMIC_CMPXCHG\000"
1091 /* 1224 */ "G_ATOMICRMW_XCHG\000"
1092 /* 1241 */ "G_GET_ROUNDING\000"
1093 /* 1256 */ "G_SET_ROUNDING\000"
1094 /* 1271 */ "G_FLOG\000"
1095 /* 1278 */ "G_VAARG\000"
1096 /* 1286 */ "PREALLOCATED_ARG\000"
1097 /* 1303 */ "G_PREFETCH\000"
1098 /* 1314 */ "G_SMULH\000"
1099 /* 1322 */ "G_UMULH\000"
1100 /* 1330 */ "G_FTANH\000"
1101 /* 1338 */ "G_FSINH\000"
1102 /* 1346 */ "G_FCOSH\000"
1103 /* 1354 */ "DBG_PHI\000"
1104 /* 1362 */ "MOVHI\000"
1105 /* 1368 */ "SFSUB_F_RI_HI\000"
1106 /* 1382 */ "SUBB_I_HI\000"
1107 /* 1392 */ "SUB_I_HI\000"
1108 /* 1401 */ "ADDC_I_HI\000"
1109 /* 1411 */ "ADD_I_HI\000"
1110 /* 1420 */ "AND_I_HI\000"
1111 /* 1429 */ "SUBB_F_I_HI\000"
1112 /* 1441 */ "SUB_F_I_HI\000"
1113 /* 1452 */ "ADDC_F_I_HI\000"
1114 /* 1464 */ "ADD_F_I_HI\000"
1115 /* 1475 */ "AND_F_I_HI\000"
1116 /* 1486 */ "XOR_F_I_HI\000"
1117 /* 1497 */ "XOR_I_HI\000"
1118 /* 1506 */ "SLI\000"
1119 /* 1510 */ "STB_RI\000"
1120 /* 1517 */ "STH_RI\000"
1121 /* 1524 */ "LDW_RI\000"
1122 /* 1531 */ "SW_RI\000"
1123 /* 1537 */ "LDBs_RI\000"
1124 /* 1545 */ "LDHs_RI\000"
1125 /* 1553 */ "LDBz_RI\000"
1126 /* 1561 */ "LDHz_RI\000"
1127 /* 1569 */ "G_FPTOSI\000"
1128 /* 1578 */ "G_FPTOUI\000"
1129 /* 1587 */ "G_FPOWI\000"
1130 /* 1595 */ "SA_I\000"
1131 /* 1600 */ "SA_F_I\000"
1132 /* 1607 */ "SL_F_I\000"
1133 /* 1614 */ "SL_I\000"
1134 /* 1619 */ "COPY_LANEMASK\000"
1135 /* 1633 */ "G_PTRMASK\000"
1136 /* 1643 */ "GC_LABEL\000"
1137 /* 1652 */ "DBG_LABEL\000"
1138 /* 1662 */ "EH_LABEL\000"
1139 /* 1671 */ "ANNOTATION_LABEL\000"
1140 /* 1688 */ "ICALL_BRANCH_FUNNEL\000"
1141 /* 1708 */ "G_FSHL\000"
1142 /* 1715 */ "G_SHL\000"
1143 /* 1721 */ "G_FCEIL\000"
1144 /* 1729 */ "G_SAVGCEIL\000"
1145 /* 1740 */ "G_UAVGCEIL\000"
1146 /* 1751 */ "PATCHABLE_TAIL_CALL\000"
1147 /* 1771 */ "PATCHABLE_TYPED_EVENT_CALL\000"
1148 /* 1798 */ "PATCHABLE_EVENT_CALL\000"
1149 /* 1819 */ "FENTRY_CALL\000"
1150 /* 1831 */ "KILL\000"
1151 /* 1836 */ "G_CONSTANT_POOL\000"
1152 /* 1852 */ "G_ROTL\000"
1153 /* 1859 */ "G_VECREDUCE_FMUL\000"
1154 /* 1876 */ "G_FMUL\000"
1155 /* 1883 */ "G_VECREDUCE_SEQ_FMUL\000"
1156 /* 1904 */ "G_STRICT_FMUL\000"
1157 /* 1918 */ "G_VECREDUCE_MUL\000"
1158 /* 1934 */ "G_MUL\000"
1159 /* 1940 */ "G_FREM\000"
1160 /* 1947 */ "G_STRICT_FREM\000"
1161 /* 1961 */ "G_SREM\000"
1162 /* 1968 */ "G_UREM\000"
1163 /* 1975 */ "G_SDIVREM\000"
1164 /* 1985 */ "G_UDIVREM\000"
1165 /* 1995 */ "INLINEASM\000"
1166 /* 2005 */ "G_VECREDUCE_FMINIMUM\000"
1167 /* 2026 */ "G_FMINIMUM\000"
1168 /* 2037 */ "G_ATOMICRMW_FMINIMUM\000"
1169 /* 2058 */ "G_VECREDUCE_FMAXIMUM\000"
1170 /* 2079 */ "G_FMAXIMUM\000"
1171 /* 2090 */ "G_ATOMICRMW_FMAXIMUM\000"
1172 /* 2111 */ "G_FMINIMUMNUM\000"
1173 /* 2125 */ "G_ATOMICRMW_FMINIMUMNUM\000"
1174 /* 2149 */ "G_FMAXIMUMNUM\000"
1175 /* 2163 */ "G_ATOMICRMW_FMAXIMUMNUM\000"
1176 /* 2187 */ "G_FMINNUM\000"
1177 /* 2197 */ "G_FMAXNUM\000"
1178 /* 2207 */ "G_FATAN\000"
1179 /* 2215 */ "G_FTAN\000"
1180 /* 2222 */ "G_INTRINSIC_ROUNDEVEN\000"
1181 /* 2244 */ "G_ASSERT_ALIGN\000"
1182 /* 2259 */ "G_FCOPYSIGN\000"
1183 /* 2271 */ "G_VECREDUCE_FMIN\000"
1184 /* 2288 */ "G_ATOMICRMW_FMIN\000"
1185 /* 2305 */ "G_VECREDUCE_SMIN\000"
1186 /* 2322 */ "G_SMIN\000"
1187 /* 2329 */ "G_VECREDUCE_UMIN\000"
1188 /* 2346 */ "G_UMIN\000"
1189 /* 2353 */ "G_ATOMICRMW_UMIN\000"
1190 /* 2370 */ "G_ATOMICRMW_MIN\000"
1191 /* 2386 */ "G_FASIN\000"
1192 /* 2394 */ "G_FSIN\000"
1193 /* 2401 */ "CFI_INSTRUCTION\000"
1194 /* 2417 */ "ADJCALLSTACKDOWN\000"
1195 /* 2434 */ "G_SSUBO\000"
1196 /* 2442 */ "G_USUBO\000"
1197 /* 2450 */ "G_SADDO\000"
1198 /* 2458 */ "G_UADDO\000"
1199 /* 2466 */ "JUMP_TABLE_DEBUG_INFO\000"
1200 /* 2488 */ "G_SMULO\000"
1201 /* 2496 */ "G_UMULO\000"
1202 /* 2504 */ "SFSUB_F_RI_LO\000"
1203 /* 2518 */ "SUBB_I_LO\000"
1204 /* 2528 */ "SUB_I_LO\000"
1205 /* 2537 */ "ADDC_I_LO\000"
1206 /* 2547 */ "ADD_I_LO\000"
1207 /* 2556 */ "AND_I_LO\000"
1208 /* 2565 */ "SUBB_F_I_LO\000"
1209 /* 2577 */ "SUB_F_I_LO\000"
1210 /* 2588 */ "ADDC_F_I_LO\000"
1211 /* 2600 */ "ADD_F_I_LO\000"
1212 /* 2611 */ "AND_F_I_LO\000"
1213 /* 2622 */ "XOR_F_I_LO\000"
1214 /* 2633 */ "XOR_I_LO\000"
1215 /* 2642 */ "G_BZERO\000"
1216 /* 2650 */ "STACKMAP\000"
1217 /* 2659 */ "G_DEBUGTRAP\000"
1218 /* 2671 */ "G_UBSANTRAP\000"
1219 /* 2683 */ "G_TRAP\000"
1220 /* 2690 */ "G_ATOMICRMW_UDEC_WRAP\000"
1221 /* 2712 */ "G_ATOMICRMW_UINC_WRAP\000"
1222 /* 2734 */ "G_BSWAP\000"
1223 /* 2742 */ "G_SITOFP\000"
1224 /* 2751 */ "G_UITOFP\000"
1225 /* 2760 */ "G_FCMP\000"
1226 /* 2767 */ "G_ICMP\000"
1227 /* 2774 */ "G_SCMP\000"
1228 /* 2781 */ "G_UCMP\000"
1229 /* 2788 */ "NOP\000"
1230 /* 2792 */ "CONVERGENCECTRL_LOOP\000"
1231 /* 2813 */ "G_CTPOP\000"
1232 /* 2821 */ "PATCHABLE_OP\000"
1233 /* 2834 */ "FAULTING_OP\000"
1234 /* 2846 */ "ADJCALLSTACKUP\000"
1235 /* 2861 */ "PREALLOCATED_SETUP\000"
1236 /* 2880 */ "G_FLDEXP\000"
1237 /* 2889 */ "G_STRICT_FLDEXP\000"
1238 /* 2905 */ "G_FEXP\000"
1239 /* 2912 */ "G_FFREXP\000"
1240 /* 2921 */ "G_BR\000"
1241 /* 2926 */ "INLINEASM_BR\000"
1242 /* 2939 */ "LDADDR\000"
1243 /* 2946 */ "STADDR\000"
1244 /* 2953 */ "G_BLOCK_ADDR\000"
1245 /* 2966 */ "MEMBARRIER\000"
1246 /* 2977 */ "G_CONSTANT_FOLD_BARRIER\000"
1247 /* 3001 */ "PATCHABLE_FUNCTION_ENTER\000"
1248 /* 3026 */ "G_READCYCLECOUNTER\000"
1249 /* 3045 */ "G_READSTEADYCOUNTER\000"
1250 /* 3065 */ "G_READ_REGISTER\000"
1251 /* 3081 */ "G_WRITE_REGISTER\000"
1252 /* 3098 */ "G_ASHR\000"
1253 /* 3105 */ "G_FSHR\000"
1254 /* 3112 */ "G_LSHR\000"
1255 /* 3119 */ "JR\000"
1256 /* 3122 */ "CALLR\000"
1257 /* 3128 */ "CONVERGENCECTRL_ANCHOR\000"
1258 /* 3151 */ "G_FFLOOR\000"
1259 /* 3160 */ "G_SAVGFLOOR\000"
1260 /* 3172 */ "G_UAVGFLOOR\000"
1261 /* 3184 */ "G_EXTRACT_SUBVECTOR\000"
1262 /* 3204 */ "G_INSERT_SUBVECTOR\000"
1263 /* 3223 */ "G_BUILD_VECTOR\000"
1264 /* 3238 */ "G_SHUFFLE_VECTOR\000"
1265 /* 3255 */ "G_STEP_VECTOR\000"
1266 /* 3269 */ "G_SPLAT_VECTOR\000"
1267 /* 3284 */ "G_VECREDUCE_XOR\000"
1268 /* 3300 */ "G_XOR\000"
1269 /* 3306 */ "G_ATOMICRMW_XOR\000"
1270 /* 3322 */ "G_VECREDUCE_OR\000"
1271 /* 3337 */ "G_OR\000"
1272 /* 3342 */ "G_ATOMICRMW_OR\000"
1273 /* 3357 */ "BRR\000"
1274 /* 3361 */ "STB_RR\000"
1275 /* 3368 */ "SFSUB_F_RR\000"
1276 /* 3379 */ "STH_RR\000"
1277 /* 3386 */ "LDW_RR\000"
1278 /* 3393 */ "SW_RR\000"
1279 /* 3399 */ "LDBs_RR\000"
1280 /* 3407 */ "LDHs_RR\000"
1281 /* 3415 */ "LDBz_RR\000"
1282 /* 3423 */ "LDHz_RR\000"
1283 /* 3431 */ "LDWz_RR\000"
1284 /* 3439 */ "G_ROTR\000"
1285 /* 3446 */ "G_INTTOPTR\000"
1286 /* 3457 */ "SRA_R\000"
1287 /* 3463 */ "SUBB_R\000"
1288 /* 3470 */ "SUB_R\000"
1289 /* 3476 */ "ADDC_R\000"
1290 /* 3483 */ "ADD_R\000"
1291 /* 3489 */ "AND_R\000"
1292 /* 3495 */ "SRA_F_R\000"
1293 /* 3503 */ "SUBB_F_R\000"
1294 /* 3512 */ "SUB_F_R\000"
1295 /* 3520 */ "ADDC_F_R\000"
1296 /* 3529 */ "ADD_F_R\000"
1297 /* 3537 */ "AND_F_R\000"
1298 /* 3545 */ "SHL_F_R\000"
1299 /* 3553 */ "SRL_F_R\000"
1300 /* 3561 */ "XOR_F_R\000"
1301 /* 3569 */ "SHL_R\000"
1302 /* 3575 */ "SRL_R\000"
1303 /* 3581 */ "XOR_R\000"
1304 /* 3587 */ "G_FABS\000"
1305 /* 3594 */ "G_ABS\000"
1306 /* 3600 */ "G_ABDS\000"
1307 /* 3607 */ "G_UNMERGE_VALUES\000"
1308 /* 3624 */ "G_MERGE_VALUES\000"
1309 /* 3639 */ "G_CTLS\000"
1310 /* 3646 */ "G_FACOS\000"
1311 /* 3654 */ "G_FCOS\000"
1312 /* 3661 */ "G_FSINCOS\000"
1313 /* 3671 */ "G_CONCAT_VECTORS\000"
1314 /* 3688 */ "COPY_TO_REGCLASS\000"
1315 /* 3705 */ "G_IS_FPCLASS\000"
1316 /* 3718 */ "G_ATOMIC_CMPXCHG_WITH_SUCCESS\000"
1317 /* 3748 */ "G_VECTOR_COMPRESS\000"
1318 /* 3766 */ "G_INTRINSIC_W_SIDE_EFFECTS\000"
1319 /* 3793 */ "G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS\000"
1320 /* 3831 */ "G_TRUNC_SSAT_S\000"
1321 /* 3846 */ "G_SSUBSAT\000"
1322 /* 3856 */ "G_USUBSAT\000"
1323 /* 3866 */ "G_SADDSAT\000"
1324 /* 3876 */ "G_UADDSAT\000"
1325 /* 3886 */ "G_SSHLSAT\000"
1326 /* 3896 */ "G_USHLSAT\000"
1327 /* 3906 */ "G_SMULFIXSAT\000"
1328 /* 3919 */ "G_UMULFIXSAT\000"
1329 /* 3932 */ "G_SDIVFIXSAT\000"
1330 /* 3945 */ "G_UDIVFIXSAT\000"
1331 /* 3958 */ "G_ATOMICRMW_USUB_SAT\000"
1332 /* 3979 */ "G_FPTOSI_SAT\000"
1333 /* 3992 */ "G_FPTOUI_SAT\000"
1334 /* 4005 */ "BT\000"
1335 /* 4008 */ "G_EXTRACT\000"
1336 /* 4018 */ "G_SELECT\000"
1337 /* 4027 */ "G_BRINDIRECT\000"
1338 /* 4040 */ "PATCHABLE_RET\000"
1339 /* 4054 */ "G_MEMSET\000"
1340 /* 4063 */ "PATCHABLE_FUNCTION_EXIT\000"
1341 /* 4087 */ "G_BRJT\000"
1342 /* 4094 */ "G_EXTRACT_VECTOR_ELT\000"
1343 /* 4115 */ "G_INSERT_VECTOR_ELT\000"
1344 /* 4135 */ "G_FCONSTANT\000"
1345 /* 4147 */ "G_CONSTANT\000"
1346 /* 4158 */ "G_INTRINSIC_CONVERGENT\000"
1347 /* 4181 */ "STATEPOINT\000"
1348 /* 4192 */ "PATCHPOINT\000"
1349 /* 4203 */ "G_PTRTOINT\000"
1350 /* 4214 */ "G_FRINT\000"
1351 /* 4222 */ "G_INTRINSIC_LLRINT\000"
1352 /* 4241 */ "G_INTRINSIC_LRINT\000"
1353 /* 4259 */ "G_FNEARBYINT\000"
1354 /* 4272 */ "G_VASTART\000"
1355 /* 4282 */ "LIFETIME_START\000"
1356 /* 4297 */ "G_INVOKE_REGION_START\000"
1357 /* 4319 */ "G_INSERT\000"
1358 /* 4328 */ "G_FSQRT\000"
1359 /* 4336 */ "G_STRICT_FSQRT\000"
1360 /* 4351 */ "G_BITCAST\000"
1361 /* 4361 */ "G_ADDRSPACE_CAST\000"
1362 /* 4378 */ "DBG_VALUE_LIST\000"
1363 /* 4393 */ "G_FPEXT\000"
1364 /* 4401 */ "G_SEXT\000"
1365 /* 4408 */ "G_ASSERT_SEXT\000"
1366 /* 4422 */ "G_ANYEXT\000"
1367 /* 4431 */ "G_ZEXT\000"
1368 /* 4438 */ "G_ASSERT_ZEXT\000"
1369 /* 4452 */ "G_ABDU\000"
1370 /* 4459 */ "G_TRUNC_SSAT_U\000"
1371 /* 4474 */ "G_TRUNC_USAT_U\000"
1372 /* 4489 */ "G_FDIV\000"
1373 /* 4496 */ "G_STRICT_FDIV\000"
1374 /* 4510 */ "G_SDIV\000"
1375 /* 4517 */ "G_UDIV\000"
1376 /* 4524 */ "G_GET_FPENV\000"
1377 /* 4536 */ "G_RESET_FPENV\000"
1378 /* 4550 */ "G_SET_FPENV\000"
1379 /* 4562 */ "G_FPOW\000"
1380 /* 4569 */ "G_VECREDUCE_FMAX\000"
1381 /* 4586 */ "G_ATOMICRMW_FMAX\000"
1382 /* 4603 */ "G_VECREDUCE_SMAX\000"
1383 /* 4620 */ "G_SMAX\000"
1384 /* 4627 */ "G_VECREDUCE_UMAX\000"
1385 /* 4644 */ "G_UMAX\000"
1386 /* 4651 */ "G_ATOMICRMW_UMAX\000"
1387 /* 4668 */ "G_ATOMICRMW_MAX\000"
1388 /* 4684 */ "G_FRAME_INDEX\000"
1389 /* 4698 */ "G_SBFX\000"
1390 /* 4705 */ "G_UBFX\000"
1391 /* 4712 */ "G_SMULFIX\000"
1392 /* 4722 */ "G_UMULFIX\000"
1393 /* 4732 */ "G_SDIVFIX\000"
1394 /* 4742 */ "G_UDIVFIX\000"
1395 /* 4752 */ "G_MEMCPY\000"
1396 /* 4761 */ "COPY\000"
1397 /* 4766 */ "CONVERGENCECTRL_ENTRY\000"
1398 /* 4788 */ "LEADZ\000"
1399 /* 4794 */ "TRAILZ\000"
1400 /* 4801 */ "G_CTLZ\000"
1401 /* 4808 */ "G_CTTZ\000"
1402};
1403#ifdef __GNUC__
1404#pragma GCC diagnostic pop
1405#endif
1406
1407extern const unsigned LanaiInstrNameIndices[] = {
1408 1358U, 1995U, 2926U, 2401U, 1662U, 1643U, 1671U, 1831U,
1409 1151U, 1166U, 1117U, 1104U, 1193U, 3688U, 944U, 4378U,
1410 1130U, 1354U, 1652U, 714U, 4761U, 1619U, 836U, 4282U,
1411 541U, 665U, 702U, 2650U, 1819U, 4192U, 648U, 2861U,
1412 1286U, 4181U, 870U, 2834U, 2821U, 3001U, 4040U, 4063U,
1413 1751U, 1798U, 1771U, 1688U, 935U, 2966U, 2466U, 859U,
1414 4766U, 3128U, 2792U, 992U, 4408U, 4438U, 2244U, 454U,
1415 130U, 1934U, 4510U, 4517U, 1961U, 1968U, 1975U, 1985U,
1416 519U, 3337U, 3300U, 3600U, 4452U, 3172U, 1740U, 3160U,
1417 1729U, 1115U, 1356U, 4684U, 954U, 969U, 1836U, 4008U,
1418 3607U, 4319U, 3624U, 3223U, 218U, 3671U, 4203U, 3446U,
1419 4351U, 1035U, 2977U, 622U, 192U, 604U, 4241U, 4222U,
1420 2222U, 3026U, 3045U, 355U, 299U, 329U, 340U, 280U,
1421 310U, 914U, 898U, 3718U, 1207U, 1224U, 470U, 136U,
1422 525U, 486U, 3342U, 3306U, 4668U, 2370U, 4651U, 2353U,
1423 421U, 113U, 4586U, 2288U, 2090U, 2037U, 2163U, 2125U,
1424 2712U, 2690U, 563U, 3958U, 694U, 1303U, 554U, 4027U,
1425 4297U, 170U, 3766U, 4158U, 3793U, 4422U, 210U, 3831U,
1426 4459U, 4474U, 4147U, 4135U, 4272U, 1278U, 4401U, 1180U,
1427 4431U, 1715U, 3112U, 3098U, 1708U, 3105U, 3439U, 1852U,
1428 2767U, 2760U, 2774U, 2781U, 4018U, 2458U, 735U, 2442U,
1429 686U, 2450U, 727U, 2434U, 678U, 2496U, 2488U, 1322U,
1430 1314U, 3876U, 3866U, 3856U, 3846U, 3896U, 3886U, 4712U,
1431 4722U, 3906U, 3919U, 4732U, 4742U, 3932U, 3945U, 379U,
1432 92U, 1876U, 73U, 273U, 4489U, 1940U, 1060U, 4562U,
1433 1587U, 2905U, 45U, 9U, 1271U, 28U, 0U, 2880U,
1434 2912U, 1144U, 4393U, 182U, 1569U, 1578U, 2742U, 2751U,
1435 3979U, 3992U, 3587U, 2259U, 3705U, 1044U, 2187U, 2197U,
1436 784U, 799U, 2026U, 2079U, 2111U, 2149U, 4524U, 4550U,
1437 4536U, 743U, 771U, 756U, 1241U, 1256U, 460U, 1633U,
1438 2322U, 4620U, 2346U, 4644U, 3594U, 595U, 585U, 2921U,
1439 4087U, 814U, 3204U, 3184U, 4115U, 4094U, 3238U, 3269U,
1440 3255U, 3748U, 4808U, 1086U, 4801U, 1068U, 3639U, 2813U,
1441 2734U, 922U, 1721U, 3654U, 2394U, 3661U, 2215U, 3646U,
1442 2386U, 2207U, 36U, 1346U, 1338U, 1330U, 4328U, 3151U,
1443 4214U, 4259U, 4361U, 2953U, 823U, 239U, 1013U, 883U,
1444 407U, 99U, 1904U, 4496U, 1947U, 79U, 4336U, 2889U,
1445 3065U, 3081U, 4752U, 843U, 1025U, 4054U, 2642U, 2683U,
1446 2659U, 2671U, 386U, 1883U, 362U, 1859U, 4569U, 2271U,
1447 2058U, 2005U, 438U, 1918U, 503U, 3322U, 3284U, 4603U,
1448 2305U, 4627U, 2329U, 4698U, 4705U, 2417U, 2846U, 256U,
1449 1766U, 3122U, 1452U, 2588U, 3520U, 1401U, 2537U, 3476U,
1450 1464U, 2600U, 3529U, 1411U, 2547U, 3483U, 1475U, 2611U,
1451 3537U, 1420U, 2556U, 3489U, 152U, 161U, 63U, 3357U,
1452 4005U, 3119U, 2939U, 1537U, 3399U, 1553U, 3415U, 1545U,
1453 3407U, 1561U, 3423U, 1524U, 3386U, 3431U, 4788U, 18U,
1454 23U, 31U, 53U, 58U, 1362U, 2788U, 1487U, 2623U,
1455 3562U, 1498U, 2634U, 3582U, 268U, 4050U, 1600U, 1595U,
1456 157U, 4020U, 1368U, 2504U, 3368U, 3545U, 3569U, 1506U,
1457 1607U, 1614U, 3495U, 3457U, 3553U, 3575U, 2946U, 1510U,
1458 3361U, 1517U, 3379U, 1429U, 2565U, 3503U, 1382U, 2518U,
1459 3463U, 1441U, 2577U, 3512U, 1392U, 2528U, 3470U, 1531U,
1460 3393U, 4794U, 1486U, 2622U, 3561U, 1497U, 2633U, 3581U,
1461};
1462
1463static inline void InitLanaiMCInstrInfo(MCInstrInfo *II) {
1464 II->InitMCInstrInfo(LanaiDescs.Insts, LanaiInstrNameIndices, LanaiInstrNameData, nullptr, nullptr, 424, nullptr, 0);
1465}
1466
1467
1468} // namespace llvm
1469
1470#endif // GET_INSTRINFO_MC_DESC
1471
1472#ifdef GET_INSTRINFO_HEADER
1473#undef GET_INSTRINFO_HEADER
1474
1475namespace llvm {
1476
1477struct LanaiGenInstrInfo : public TargetInstrInfo {
1478 explicit LanaiGenInstrInfo(const TargetSubtargetInfo &STI, const TargetRegisterInfo &TRI, unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u, unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u);
1479 ~LanaiGenInstrInfo() override = default;
1480};
1481
1482} // namespace llvm
1483
1484namespace llvm::Lanai {
1485
1486constexpr unsigned SUBOP_MEMri_base = 0;
1487constexpr unsigned SUBOP_MEMri_offset = 1;
1488constexpr unsigned SUBOP_MEMri_Opcode = 2;
1489constexpr unsigned SUBOP_MEMrr_Op1 = 0;
1490constexpr unsigned SUBOP_MEMrr_Op2 = 1;
1491constexpr unsigned SUBOP_MEMrr_Opcode = 2;
1492constexpr unsigned SUBOP_MEMspls_base = 0;
1493constexpr unsigned SUBOP_MEMspls_offset = 1;
1494constexpr unsigned SUBOP_MEMspls_Opcode = 2;
1495
1496} // namespace llvm::Lanai
1497
1498#endif // GET_INSTRINFO_HEADER
1499
1500#ifdef GET_INSTRINFO_HELPER_DECLS
1501#undef GET_INSTRINFO_HELPER_DECLS
1502
1503
1504#endif // GET_INSTRINFO_HELPER_DECLS
1505
1506#ifdef GET_INSTRINFO_HELPERS
1507#undef GET_INSTRINFO_HELPERS
1508
1509
1510#endif // GET_INSTRINFO_HELPERS
1511
1512#ifdef GET_INSTRINFO_CTOR_DTOR
1513#undef GET_INSTRINFO_CTOR_DTOR
1514
1515namespace llvm {
1516
1517extern const LanaiInstrTable LanaiDescs;
1518extern const unsigned LanaiInstrNameIndices[];
1519extern const char LanaiInstrNameData[];
1520LanaiGenInstrInfo::LanaiGenInstrInfo(const TargetSubtargetInfo &STI, const TargetRegisterInfo &TRI, unsigned CFSetupOpcode, unsigned CFDestroyOpcode, unsigned CatchRetOpcode, unsigned ReturnOpcode)
1521 : TargetInstrInfo(TRI, CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) {
1522 InitMCInstrInfo(LanaiDescs.Insts, LanaiInstrNameIndices, LanaiInstrNameData, nullptr, nullptr, 424);
1523}
1524
1525} // namespace llvm
1526
1527#endif // GET_INSTRINFO_CTOR_DTOR
1528
1529#ifdef GET_INSTRINFO_MC_HELPER_DECLS
1530#undef GET_INSTRINFO_MC_HELPER_DECLS
1531
1532namespace llvm {
1533
1534class MCInst;
1535class FeatureBitset;
1536
1537namespace Lanai_MC {
1538
1539void verifyInstructionPredicates(unsigned Opcode, const FeatureBitset &Features);
1540
1541} // namespace Lanai_MC
1542
1543} // namespace llvm
1544
1545#endif // GET_INSTRINFO_MC_HELPER_DECLS
1546
1547#ifdef GET_INSTRINFO_MC_HELPERS
1548#undef GET_INSTRINFO_MC_HELPERS
1549
1550namespace llvm::Lanai_MC {
1551
1552
1553} // namespace llvm::Lanai_MC
1554
1555#endif // GET_INSTRINFO_MC_HELPERS
1556
1557#if (defined(ENABLE_INSTR_PREDICATE_VERIFIER) && !defined(NDEBUG)) ||\
1558 defined(GET_AVAILABLE_OPCODE_CHECKER)
1559#define GET_COMPUTE_FEATURES
1560#endif
1561#ifdef GET_COMPUTE_FEATURES
1562#undef GET_COMPUTE_FEATURES
1563
1564namespace llvm::Lanai_MC {
1565
1566// Bits for subtarget features that participate in instruction matching.
1567enum SubtargetFeatureBits : uint8_t {
1568};
1569
1570inline FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) {
1571 FeatureBitset Features;
1572 return Features;
1573}
1574
1575inline FeatureBitset computeRequiredFeatures(unsigned Opcode) {
1576 enum : uint8_t {
1577 CEFBS_None,
1578 };
1579
1580 static constexpr FeatureBitset FeatureBitsets[] = {
1581 {}, // CEFBS_None
1582 };
1583 static constexpr uint8_t RequiredFeaturesRefs[] = {
1584 CEFBS_None, // PHI
1585 CEFBS_None, // INLINEASM
1586 CEFBS_None, // INLINEASM_BR
1587 CEFBS_None, // CFI_INSTRUCTION
1588 CEFBS_None, // EH_LABEL
1589 CEFBS_None, // GC_LABEL
1590 CEFBS_None, // ANNOTATION_LABEL
1591 CEFBS_None, // KILL
1592 CEFBS_None, // EXTRACT_SUBREG
1593 CEFBS_None, // INSERT_SUBREG
1594 CEFBS_None, // IMPLICIT_DEF
1595 CEFBS_None, // INIT_UNDEF
1596 CEFBS_None, // SUBREG_TO_REG
1597 CEFBS_None, // COPY_TO_REGCLASS
1598 CEFBS_None, // DBG_VALUE
1599 CEFBS_None, // DBG_VALUE_LIST
1600 CEFBS_None, // DBG_INSTR_REF
1601 CEFBS_None, // DBG_PHI
1602 CEFBS_None, // DBG_LABEL
1603 CEFBS_None, // REG_SEQUENCE
1604 CEFBS_None, // COPY
1605 CEFBS_None, // COPY_LANEMASK
1606 CEFBS_None, // BUNDLE
1607 CEFBS_None, // LIFETIME_START
1608 CEFBS_None, // LIFETIME_END
1609 CEFBS_None, // PSEUDO_PROBE
1610 CEFBS_None, // ARITH_FENCE
1611 CEFBS_None, // STACKMAP
1612 CEFBS_None, // FENTRY_CALL
1613 CEFBS_None, // PATCHPOINT
1614 CEFBS_None, // LOAD_STACK_GUARD
1615 CEFBS_None, // PREALLOCATED_SETUP
1616 CEFBS_None, // PREALLOCATED_ARG
1617 CEFBS_None, // STATEPOINT
1618 CEFBS_None, // LOCAL_ESCAPE
1619 CEFBS_None, // FAULTING_OP
1620 CEFBS_None, // PATCHABLE_OP
1621 CEFBS_None, // PATCHABLE_FUNCTION_ENTER
1622 CEFBS_None, // PATCHABLE_RET
1623 CEFBS_None, // PATCHABLE_FUNCTION_EXIT
1624 CEFBS_None, // PATCHABLE_TAIL_CALL
1625 CEFBS_None, // PATCHABLE_EVENT_CALL
1626 CEFBS_None, // PATCHABLE_TYPED_EVENT_CALL
1627 CEFBS_None, // ICALL_BRANCH_FUNNEL
1628 CEFBS_None, // FAKE_USE
1629 CEFBS_None, // MEMBARRIER
1630 CEFBS_None, // JUMP_TABLE_DEBUG_INFO
1631 CEFBS_None, // RELOC_NONE
1632 CEFBS_None, // CONVERGENCECTRL_ENTRY
1633 CEFBS_None, // CONVERGENCECTRL_ANCHOR
1634 CEFBS_None, // CONVERGENCECTRL_LOOP
1635 CEFBS_None, // CONVERGENCECTRL_GLUE
1636 CEFBS_None, // G_ASSERT_SEXT
1637 CEFBS_None, // G_ASSERT_ZEXT
1638 CEFBS_None, // G_ASSERT_ALIGN
1639 CEFBS_None, // G_ADD
1640 CEFBS_None, // G_SUB
1641 CEFBS_None, // G_MUL
1642 CEFBS_None, // G_SDIV
1643 CEFBS_None, // G_UDIV
1644 CEFBS_None, // G_SREM
1645 CEFBS_None, // G_UREM
1646 CEFBS_None, // G_SDIVREM
1647 CEFBS_None, // G_UDIVREM
1648 CEFBS_None, // G_AND
1649 CEFBS_None, // G_OR
1650 CEFBS_None, // G_XOR
1651 CEFBS_None, // G_ABDS
1652 CEFBS_None, // G_ABDU
1653 CEFBS_None, // G_UAVGFLOOR
1654 CEFBS_None, // G_UAVGCEIL
1655 CEFBS_None, // G_SAVGFLOOR
1656 CEFBS_None, // G_SAVGCEIL
1657 CEFBS_None, // G_IMPLICIT_DEF
1658 CEFBS_None, // G_PHI
1659 CEFBS_None, // G_FRAME_INDEX
1660 CEFBS_None, // G_GLOBAL_VALUE
1661 CEFBS_None, // G_PTRAUTH_GLOBAL_VALUE
1662 CEFBS_None, // G_CONSTANT_POOL
1663 CEFBS_None, // G_EXTRACT
1664 CEFBS_None, // G_UNMERGE_VALUES
1665 CEFBS_None, // G_INSERT
1666 CEFBS_None, // G_MERGE_VALUES
1667 CEFBS_None, // G_BUILD_VECTOR
1668 CEFBS_None, // G_BUILD_VECTOR_TRUNC
1669 CEFBS_None, // G_CONCAT_VECTORS
1670 CEFBS_None, // G_PTRTOINT
1671 CEFBS_None, // G_INTTOPTR
1672 CEFBS_None, // G_BITCAST
1673 CEFBS_None, // G_FREEZE
1674 CEFBS_None, // G_CONSTANT_FOLD_BARRIER
1675 CEFBS_None, // G_INTRINSIC_FPTRUNC_ROUND
1676 CEFBS_None, // G_INTRINSIC_TRUNC
1677 CEFBS_None, // G_INTRINSIC_ROUND
1678 CEFBS_None, // G_INTRINSIC_LRINT
1679 CEFBS_None, // G_INTRINSIC_LLRINT
1680 CEFBS_None, // G_INTRINSIC_ROUNDEVEN
1681 CEFBS_None, // G_READCYCLECOUNTER
1682 CEFBS_None, // G_READSTEADYCOUNTER
1683 CEFBS_None, // G_LOAD
1684 CEFBS_None, // G_SEXTLOAD
1685 CEFBS_None, // G_ZEXTLOAD
1686 CEFBS_None, // G_INDEXED_LOAD
1687 CEFBS_None, // G_INDEXED_SEXTLOAD
1688 CEFBS_None, // G_INDEXED_ZEXTLOAD
1689 CEFBS_None, // G_STORE
1690 CEFBS_None, // G_INDEXED_STORE
1691 CEFBS_None, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
1692 CEFBS_None, // G_ATOMIC_CMPXCHG
1693 CEFBS_None, // G_ATOMICRMW_XCHG
1694 CEFBS_None, // G_ATOMICRMW_ADD
1695 CEFBS_None, // G_ATOMICRMW_SUB
1696 CEFBS_None, // G_ATOMICRMW_AND
1697 CEFBS_None, // G_ATOMICRMW_NAND
1698 CEFBS_None, // G_ATOMICRMW_OR
1699 CEFBS_None, // G_ATOMICRMW_XOR
1700 CEFBS_None, // G_ATOMICRMW_MAX
1701 CEFBS_None, // G_ATOMICRMW_MIN
1702 CEFBS_None, // G_ATOMICRMW_UMAX
1703 CEFBS_None, // G_ATOMICRMW_UMIN
1704 CEFBS_None, // G_ATOMICRMW_FADD
1705 CEFBS_None, // G_ATOMICRMW_FSUB
1706 CEFBS_None, // G_ATOMICRMW_FMAX
1707 CEFBS_None, // G_ATOMICRMW_FMIN
1708 CEFBS_None, // G_ATOMICRMW_FMAXIMUM
1709 CEFBS_None, // G_ATOMICRMW_FMINIMUM
1710 CEFBS_None, // G_ATOMICRMW_FMAXIMUMNUM
1711 CEFBS_None, // G_ATOMICRMW_FMINIMUMNUM
1712 CEFBS_None, // G_ATOMICRMW_UINC_WRAP
1713 CEFBS_None, // G_ATOMICRMW_UDEC_WRAP
1714 CEFBS_None, // G_ATOMICRMW_USUB_COND
1715 CEFBS_None, // G_ATOMICRMW_USUB_SAT
1716 CEFBS_None, // G_FENCE
1717 CEFBS_None, // G_PREFETCH
1718 CEFBS_None, // G_BRCOND
1719 CEFBS_None, // G_BRINDIRECT
1720 CEFBS_None, // G_INVOKE_REGION_START
1721 CEFBS_None, // G_INTRINSIC
1722 CEFBS_None, // G_INTRINSIC_W_SIDE_EFFECTS
1723 CEFBS_None, // G_INTRINSIC_CONVERGENT
1724 CEFBS_None, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
1725 CEFBS_None, // G_ANYEXT
1726 CEFBS_None, // G_TRUNC
1727 CEFBS_None, // G_TRUNC_SSAT_S
1728 CEFBS_None, // G_TRUNC_SSAT_U
1729 CEFBS_None, // G_TRUNC_USAT_U
1730 CEFBS_None, // G_CONSTANT
1731 CEFBS_None, // G_FCONSTANT
1732 CEFBS_None, // G_VASTART
1733 CEFBS_None, // G_VAARG
1734 CEFBS_None, // G_SEXT
1735 CEFBS_None, // G_SEXT_INREG
1736 CEFBS_None, // G_ZEXT
1737 CEFBS_None, // G_SHL
1738 CEFBS_None, // G_LSHR
1739 CEFBS_None, // G_ASHR
1740 CEFBS_None, // G_FSHL
1741 CEFBS_None, // G_FSHR
1742 CEFBS_None, // G_ROTR
1743 CEFBS_None, // G_ROTL
1744 CEFBS_None, // G_ICMP
1745 CEFBS_None, // G_FCMP
1746 CEFBS_None, // G_SCMP
1747 CEFBS_None, // G_UCMP
1748 CEFBS_None, // G_SELECT
1749 CEFBS_None, // G_UADDO
1750 CEFBS_None, // G_UADDE
1751 CEFBS_None, // G_USUBO
1752 CEFBS_None, // G_USUBE
1753 CEFBS_None, // G_SADDO
1754 CEFBS_None, // G_SADDE
1755 CEFBS_None, // G_SSUBO
1756 CEFBS_None, // G_SSUBE
1757 CEFBS_None, // G_UMULO
1758 CEFBS_None, // G_SMULO
1759 CEFBS_None, // G_UMULH
1760 CEFBS_None, // G_SMULH
1761 CEFBS_None, // G_UADDSAT
1762 CEFBS_None, // G_SADDSAT
1763 CEFBS_None, // G_USUBSAT
1764 CEFBS_None, // G_SSUBSAT
1765 CEFBS_None, // G_USHLSAT
1766 CEFBS_None, // G_SSHLSAT
1767 CEFBS_None, // G_SMULFIX
1768 CEFBS_None, // G_UMULFIX
1769 CEFBS_None, // G_SMULFIXSAT
1770 CEFBS_None, // G_UMULFIXSAT
1771 CEFBS_None, // G_SDIVFIX
1772 CEFBS_None, // G_UDIVFIX
1773 CEFBS_None, // G_SDIVFIXSAT
1774 CEFBS_None, // G_UDIVFIXSAT
1775 CEFBS_None, // G_FADD
1776 CEFBS_None, // G_FSUB
1777 CEFBS_None, // G_FMUL
1778 CEFBS_None, // G_FMA
1779 CEFBS_None, // G_FMAD
1780 CEFBS_None, // G_FDIV
1781 CEFBS_None, // G_FREM
1782 CEFBS_None, // G_FMODF
1783 CEFBS_None, // G_FPOW
1784 CEFBS_None, // G_FPOWI
1785 CEFBS_None, // G_FEXP
1786 CEFBS_None, // G_FEXP2
1787 CEFBS_None, // G_FEXP10
1788 CEFBS_None, // G_FLOG
1789 CEFBS_None, // G_FLOG2
1790 CEFBS_None, // G_FLOG10
1791 CEFBS_None, // G_FLDEXP
1792 CEFBS_None, // G_FFREXP
1793 CEFBS_None, // G_FNEG
1794 CEFBS_None, // G_FPEXT
1795 CEFBS_None, // G_FPTRUNC
1796 CEFBS_None, // G_FPTOSI
1797 CEFBS_None, // G_FPTOUI
1798 CEFBS_None, // G_SITOFP
1799 CEFBS_None, // G_UITOFP
1800 CEFBS_None, // G_FPTOSI_SAT
1801 CEFBS_None, // G_FPTOUI_SAT
1802 CEFBS_None, // G_FABS
1803 CEFBS_None, // G_FCOPYSIGN
1804 CEFBS_None, // G_IS_FPCLASS
1805 CEFBS_None, // G_FCANONICALIZE
1806 CEFBS_None, // G_FMINNUM
1807 CEFBS_None, // G_FMAXNUM
1808 CEFBS_None, // G_FMINNUM_IEEE
1809 CEFBS_None, // G_FMAXNUM_IEEE
1810 CEFBS_None, // G_FMINIMUM
1811 CEFBS_None, // G_FMAXIMUM
1812 CEFBS_None, // G_FMINIMUMNUM
1813 CEFBS_None, // G_FMAXIMUMNUM
1814 CEFBS_None, // G_GET_FPENV
1815 CEFBS_None, // G_SET_FPENV
1816 CEFBS_None, // G_RESET_FPENV
1817 CEFBS_None, // G_GET_FPMODE
1818 CEFBS_None, // G_SET_FPMODE
1819 CEFBS_None, // G_RESET_FPMODE
1820 CEFBS_None, // G_GET_ROUNDING
1821 CEFBS_None, // G_SET_ROUNDING
1822 CEFBS_None, // G_PTR_ADD
1823 CEFBS_None, // G_PTRMASK
1824 CEFBS_None, // G_SMIN
1825 CEFBS_None, // G_SMAX
1826 CEFBS_None, // G_UMIN
1827 CEFBS_None, // G_UMAX
1828 CEFBS_None, // G_ABS
1829 CEFBS_None, // G_LROUND
1830 CEFBS_None, // G_LLROUND
1831 CEFBS_None, // G_BR
1832 CEFBS_None, // G_BRJT
1833 CEFBS_None, // G_VSCALE
1834 CEFBS_None, // G_INSERT_SUBVECTOR
1835 CEFBS_None, // G_EXTRACT_SUBVECTOR
1836 CEFBS_None, // G_INSERT_VECTOR_ELT
1837 CEFBS_None, // G_EXTRACT_VECTOR_ELT
1838 CEFBS_None, // G_SHUFFLE_VECTOR
1839 CEFBS_None, // G_SPLAT_VECTOR
1840 CEFBS_None, // G_STEP_VECTOR
1841 CEFBS_None, // G_VECTOR_COMPRESS
1842 CEFBS_None, // G_CTTZ
1843 CEFBS_None, // G_CTTZ_ZERO_UNDEF
1844 CEFBS_None, // G_CTLZ
1845 CEFBS_None, // G_CTLZ_ZERO_UNDEF
1846 CEFBS_None, // G_CTLS
1847 CEFBS_None, // G_CTPOP
1848 CEFBS_None, // G_BSWAP
1849 CEFBS_None, // G_BITREVERSE
1850 CEFBS_None, // G_FCEIL
1851 CEFBS_None, // G_FCOS
1852 CEFBS_None, // G_FSIN
1853 CEFBS_None, // G_FSINCOS
1854 CEFBS_None, // G_FTAN
1855 CEFBS_None, // G_FACOS
1856 CEFBS_None, // G_FASIN
1857 CEFBS_None, // G_FATAN
1858 CEFBS_None, // G_FATAN2
1859 CEFBS_None, // G_FCOSH
1860 CEFBS_None, // G_FSINH
1861 CEFBS_None, // G_FTANH
1862 CEFBS_None, // G_FSQRT
1863 CEFBS_None, // G_FFLOOR
1864 CEFBS_None, // G_FRINT
1865 CEFBS_None, // G_FNEARBYINT
1866 CEFBS_None, // G_ADDRSPACE_CAST
1867 CEFBS_None, // G_BLOCK_ADDR
1868 CEFBS_None, // G_JUMP_TABLE
1869 CEFBS_None, // G_DYN_STACKALLOC
1870 CEFBS_None, // G_STACKSAVE
1871 CEFBS_None, // G_STACKRESTORE
1872 CEFBS_None, // G_STRICT_FADD
1873 CEFBS_None, // G_STRICT_FSUB
1874 CEFBS_None, // G_STRICT_FMUL
1875 CEFBS_None, // G_STRICT_FDIV
1876 CEFBS_None, // G_STRICT_FREM
1877 CEFBS_None, // G_STRICT_FMA
1878 CEFBS_None, // G_STRICT_FSQRT
1879 CEFBS_None, // G_STRICT_FLDEXP
1880 CEFBS_None, // G_READ_REGISTER
1881 CEFBS_None, // G_WRITE_REGISTER
1882 CEFBS_None, // G_MEMCPY
1883 CEFBS_None, // G_MEMCPY_INLINE
1884 CEFBS_None, // G_MEMMOVE
1885 CEFBS_None, // G_MEMSET
1886 CEFBS_None, // G_BZERO
1887 CEFBS_None, // G_TRAP
1888 CEFBS_None, // G_DEBUGTRAP
1889 CEFBS_None, // G_UBSANTRAP
1890 CEFBS_None, // G_VECREDUCE_SEQ_FADD
1891 CEFBS_None, // G_VECREDUCE_SEQ_FMUL
1892 CEFBS_None, // G_VECREDUCE_FADD
1893 CEFBS_None, // G_VECREDUCE_FMUL
1894 CEFBS_None, // G_VECREDUCE_FMAX
1895 CEFBS_None, // G_VECREDUCE_FMIN
1896 CEFBS_None, // G_VECREDUCE_FMAXIMUM
1897 CEFBS_None, // G_VECREDUCE_FMINIMUM
1898 CEFBS_None, // G_VECREDUCE_ADD
1899 CEFBS_None, // G_VECREDUCE_MUL
1900 CEFBS_None, // G_VECREDUCE_AND
1901 CEFBS_None, // G_VECREDUCE_OR
1902 CEFBS_None, // G_VECREDUCE_XOR
1903 CEFBS_None, // G_VECREDUCE_SMAX
1904 CEFBS_None, // G_VECREDUCE_SMIN
1905 CEFBS_None, // G_VECREDUCE_UMAX
1906 CEFBS_None, // G_VECREDUCE_UMIN
1907 CEFBS_None, // G_SBFX
1908 CEFBS_None, // G_UBFX
1909 CEFBS_None, // ADJCALLSTACKDOWN
1910 CEFBS_None, // ADJCALLSTACKUP
1911 CEFBS_None, // ADJDYNALLOC
1912 CEFBS_None, // CALL
1913 CEFBS_None, // CALLR
1914 CEFBS_None, // ADDC_F_I_HI
1915 CEFBS_None, // ADDC_F_I_LO
1916 CEFBS_None, // ADDC_F_R
1917 CEFBS_None, // ADDC_I_HI
1918 CEFBS_None, // ADDC_I_LO
1919 CEFBS_None, // ADDC_R
1920 CEFBS_None, // ADD_F_I_HI
1921 CEFBS_None, // ADD_F_I_LO
1922 CEFBS_None, // ADD_F_R
1923 CEFBS_None, // ADD_I_HI
1924 CEFBS_None, // ADD_I_LO
1925 CEFBS_None, // ADD_R
1926 CEFBS_None, // AND_F_I_HI
1927 CEFBS_None, // AND_F_I_LO
1928 CEFBS_None, // AND_F_R
1929 CEFBS_None, // AND_I_HI
1930 CEFBS_None, // AND_I_LO
1931 CEFBS_None, // AND_R
1932 CEFBS_None, // BRCC
1933 CEFBS_None, // BRIND_CC
1934 CEFBS_None, // BRIND_CCA
1935 CEFBS_None, // BRR
1936 CEFBS_None, // BT
1937 CEFBS_None, // JR
1938 CEFBS_None, // LDADDR
1939 CEFBS_None, // LDBs_RI
1940 CEFBS_None, // LDBs_RR
1941 CEFBS_None, // LDBz_RI
1942 CEFBS_None, // LDBz_RR
1943 CEFBS_None, // LDHs_RI
1944 CEFBS_None, // LDHs_RR
1945 CEFBS_None, // LDHz_RI
1946 CEFBS_None, // LDHz_RR
1947 CEFBS_None, // LDW_RI
1948 CEFBS_None, // LDW_RR
1949 CEFBS_None, // LDWz_RR
1950 CEFBS_None, // LEADZ
1951 CEFBS_None, // LOG0
1952 CEFBS_None, // LOG1
1953 CEFBS_None, // LOG2
1954 CEFBS_None, // LOG3
1955 CEFBS_None, // LOG4
1956 CEFBS_None, // MOVHI
1957 CEFBS_None, // NOP
1958 CEFBS_None, // OR_F_I_HI
1959 CEFBS_None, // OR_F_I_LO
1960 CEFBS_None, // OR_F_R
1961 CEFBS_None, // OR_I_HI
1962 CEFBS_None, // OR_I_LO
1963 CEFBS_None, // OR_R
1964 CEFBS_None, // POPC
1965 CEFBS_None, // RET
1966 CEFBS_None, // SA_F_I
1967 CEFBS_None, // SA_I
1968 CEFBS_None, // SCC
1969 CEFBS_None, // SELECT
1970 CEFBS_None, // SFSUB_F_RI_HI
1971 CEFBS_None, // SFSUB_F_RI_LO
1972 CEFBS_None, // SFSUB_F_RR
1973 CEFBS_None, // SHL_F_R
1974 CEFBS_None, // SHL_R
1975 CEFBS_None, // SLI
1976 CEFBS_None, // SL_F_I
1977 CEFBS_None, // SL_I
1978 CEFBS_None, // SRA_F_R
1979 CEFBS_None, // SRA_R
1980 CEFBS_None, // SRL_F_R
1981 CEFBS_None, // SRL_R
1982 CEFBS_None, // STADDR
1983 CEFBS_None, // STB_RI
1984 CEFBS_None, // STB_RR
1985 CEFBS_None, // STH_RI
1986 CEFBS_None, // STH_RR
1987 CEFBS_None, // SUBB_F_I_HI
1988 CEFBS_None, // SUBB_F_I_LO
1989 CEFBS_None, // SUBB_F_R
1990 CEFBS_None, // SUBB_I_HI
1991 CEFBS_None, // SUBB_I_LO
1992 CEFBS_None, // SUBB_R
1993 CEFBS_None, // SUB_F_I_HI
1994 CEFBS_None, // SUB_F_I_LO
1995 CEFBS_None, // SUB_F_R
1996 CEFBS_None, // SUB_I_HI
1997 CEFBS_None, // SUB_I_LO
1998 CEFBS_None, // SUB_R
1999 CEFBS_None, // SW_RI
2000 CEFBS_None, // SW_RR
2001 CEFBS_None, // TRAILZ
2002 CEFBS_None, // XOR_F_I_HI
2003 CEFBS_None, // XOR_F_I_LO
2004 CEFBS_None, // XOR_F_R
2005 CEFBS_None, // XOR_I_HI
2006 CEFBS_None, // XOR_I_LO
2007 CEFBS_None, // XOR_R
2008 };
2009
2010 assert(Opcode < 424);
2011 return FeatureBitsets[RequiredFeaturesRefs[Opcode]];
2012}
2013
2014
2015} // namespace llvm::Lanai_MC
2016
2017#endif // GET_COMPUTE_FEATURES
2018
2019#ifdef GET_AVAILABLE_OPCODE_CHECKER
2020#undef GET_AVAILABLE_OPCODE_CHECKER
2021
2022namespace llvm::Lanai_MC {
2023
2024bool isOpcodeAvailable(unsigned Opcode, const FeatureBitset &Features) {
2025 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
2026 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
2027 FeatureBitset MissingFeatures =
2028 (AvailableFeatures & RequiredFeatures) ^
2029 RequiredFeatures;
2030 return !MissingFeatures.any();
2031}
2032
2033} // namespace llvm::Lanai_MC
2034
2035#endif // GET_AVAILABLE_OPCODE_CHECKER
2036
2037#ifdef ENABLE_INSTR_PREDICATE_VERIFIER
2038#undef ENABLE_INSTR_PREDICATE_VERIFIER
2039
2040#include <sstream>
2041
2042namespace llvm::Lanai_MC {
2043
2044#ifndef NDEBUG
2045static const char *SubtargetFeatureNames[] = {
2046 nullptr
2047};
2048
2049#endif // NDEBUG
2050
2051void verifyInstructionPredicates(
2052 unsigned Opcode, const FeatureBitset &Features) {
2053#ifndef NDEBUG
2054 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
2055 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
2056 FeatureBitset MissingFeatures =
2057 (AvailableFeatures & RequiredFeatures) ^
2058 RequiredFeatures;
2059 if (MissingFeatures.any()) {
2060 std::ostringstream Msg;
2061 Msg << "Attempting to emit " << &LanaiInstrNameData[LanaiInstrNameIndices[Opcode]]
2062 << " instruction but the ";
2063 for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i)
2064 if (MissingFeatures.test(i))
2065 Msg << SubtargetFeatureNames[i] << " ";
2066 Msg << "predicate(s) are not met";
2067 report_fatal_error(Msg.str().c_str());
2068 }
2069#endif // NDEBUG
2070}
2071
2072} // namespace llvm::Lanai_MC
2073
2074#endif // ENABLE_INSTR_PREDICATE_VERIFIER
2075
2076#ifdef GET_INSTRMAP_INFO
2077#undef GET_INSTRMAP_INFO
2078
2079namespace llvm::Lanai {
2080
2081enum PostEncoderMethod {
2082 PostEncoderMethod_adjustPqBitsSpls
2083};
2084
2085// splsIdempotent
2086LLVM_READONLY
2087int32_t splsIdempotent(uint32_t Opcode) {
2088 using namespace Lanai;
2089 static constexpr uint32_t Table[][2] = {
2090 { LDBs_RI, LDBs_RI },
2091 { LDBz_RI, LDBz_RI },
2092 { LDHs_RI, LDHs_RI },
2093 { LDHz_RI, LDHz_RI },
2094 { STB_RI, STB_RI },
2095 { STH_RI, STH_RI },
2096 }; // End of Table
2097
2098 unsigned mid;
2099 unsigned start = 0;
2100 unsigned end = 6;
2101 while (start < end) {
2102 mid = start + (end - start) / 2;
2103 if (Opcode == Table[mid][0])
2104 break;
2105 if (Opcode < Table[mid][0])
2106 end = mid;
2107 else
2108 start = mid + 1;
2109 }
2110 if (start == end)
2111 return -1; // Instruction doesn't exist in this table.
2112
2113 return Table[mid][1];
2114}
2115
2116
2117} // namespace llvm::Lanai
2118
2119#endif // GET_INSTRMAP_INFO
2120
2121