1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Instruction Enum Values and Descriptors *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_INSTRINFO_ENUM
10#undef GET_INSTRINFO_ENUM
11
12namespace llvm::Lanai {
13
14 enum {
15 PHI = 0, // Target.td:1314
16 INLINEASM = 1, // Target.td:1320
17 INLINEASM_BR = 2, // Target.td:1326
18 CFI_INSTRUCTION = 3, // Target.td:1335
19 EH_LABEL = 4, // Target.td:1344
20 GC_LABEL = 5, // Target.td:1353
21 ANNOTATION_LABEL = 6, // Target.td:1362
22 KILL = 7, // Target.td:1370
23 EXTRACT_SUBREG = 8, // Target.td:1377
24 INSERT_SUBREG = 9, // Target.td:1383
25 IMPLICIT_DEF = 10, // Target.td:1390
26 INIT_UNDEF = 11, // Target.td:1399
27 SUBREG_TO_REG = 12, // Target.td:1406
28 COPY_TO_REGCLASS = 13, // Target.td:1412
29 DBG_VALUE = 14, // Target.td:1419
30 DBG_VALUE_LIST = 15, // Target.td:1426
31 DBG_INSTR_REF = 16, // Target.td:1433
32 DBG_PHI = 17, // Target.td:1440
33 DBG_LABEL = 18, // Target.td:1447
34 REG_SEQUENCE = 19, // Target.td:1454
35 COPY = 20, // Target.td:1461
36 COPY_LANEMASK = 21, // Target.td:1469
37 BUNDLE = 22, // Target.td:1476
38 LIFETIME_START = 23, // Target.td:1482
39 LIFETIME_END = 24, // Target.td:1489
40 PSEUDO_PROBE = 25, // Target.td:1496
41 ARITH_FENCE = 26, // Target.td:1503
42 STACKMAP = 27, // Target.td:1512
43 FENTRY_CALL = 28, // Target.td:1647
44 PATCHPOINT = 29, // Target.td:1520
45 LOAD_STACK_GUARD = 30, // Target.td:1538
46 PREALLOCATED_SETUP = 31, // Target.td:1546
47 PREALLOCATED_ARG = 32, // Target.td:1552
48 STATEPOINT = 33, // Target.td:1529
49 LOCAL_ESCAPE = 34, // Target.td:1558
50 FAULTING_OP = 35, // Target.td:1567
51 PATCHABLE_OP = 36, // Target.td:1587
52 PATCHABLE_FUNCTION_ENTER = 37, // Target.td:1595
53 PATCHABLE_RET = 38, // Target.td:1602
54 PATCHABLE_FUNCTION_EXIT = 39, // Target.td:1611
55 PATCHABLE_TAIL_CALL = 40, // Target.td:1619
56 PATCHABLE_EVENT_CALL = 41, // Target.td:1627
57 PATCHABLE_TYPED_EVENT_CALL = 42, // Target.td:1637
58 ICALL_BRANCH_FUNNEL = 43, // Target.td:1657
59 FAKE_USE = 44, // Target.td:1577
60 MEMBARRIER = 45, // Target.td:1663
61 JUMP_TABLE_DEBUG_INFO = 46, // Target.td:1671
62 RELOC_NONE = 47, // Target.td:1679
63 CONVERGENCECTRL_ENTRY = 48, // Target.td:1691
64 CONVERGENCECTRL_ANCHOR = 49, // Target.td:1687
65 CONVERGENCECTRL_LOOP = 50, // Target.td:1695
66 CONVERGENCECTRL_GLUE = 51, // Target.td:1699
67 G_ASSERT_SEXT = 52, // GenericOpcodes.td:1945
68 G_ASSERT_ZEXT = 53, // GenericOpcodes.td:1937
69 G_ASSERT_ALIGN = 54, // GenericOpcodes.td:1952
70 G_ADD = 55, // GenericOpcodes.td:308
71 G_SUB = 56, // GenericOpcodes.td:316
72 G_MUL = 57, // GenericOpcodes.td:324
73 G_SDIV = 58, // GenericOpcodes.td:332
74 G_UDIV = 59, // GenericOpcodes.td:340
75 G_SREM = 60, // GenericOpcodes.td:348
76 G_UREM = 61, // GenericOpcodes.td:356
77 G_SDIVREM = 62, // GenericOpcodes.td:364
78 G_UDIVREM = 63, // GenericOpcodes.td:372
79 G_AND = 64, // GenericOpcodes.td:380
80 G_OR = 65, // GenericOpcodes.td:388
81 G_XOR = 66, // GenericOpcodes.td:396
82 G_ABDS = 67, // GenericOpcodes.td:425
83 G_ABDU = 68, // GenericOpcodes.td:433
84 G_UAVGFLOOR = 69, // GenericOpcodes.td:441
85 G_UAVGCEIL = 70, // GenericOpcodes.td:448
86 G_SAVGFLOOR = 71, // GenericOpcodes.td:455
87 G_SAVGCEIL = 72, // GenericOpcodes.td:462
88 G_IMPLICIT_DEF = 73, // GenericOpcodes.td:111
89 G_PHI = 74, // GenericOpcodes.td:118
90 G_FRAME_INDEX = 75, // GenericOpcodes.td:125
91 G_GLOBAL_VALUE = 76, // GenericOpcodes.td:131
92 G_PTRAUTH_GLOBAL_VALUE = 77, // GenericOpcodes.td:137
93 G_CONSTANT_POOL = 78, // GenericOpcodes.td:143
94 G_EXTRACT = 79, // GenericOpcodes.td:1530
95 G_UNMERGE_VALUES = 80, // GenericOpcodes.td:1543
96 G_INSERT = 81, // GenericOpcodes.td:1552
97 G_MERGE_VALUES = 82, // GenericOpcodes.td:1562
98 G_BUILD_VECTOR = 83, // GenericOpcodes.td:1582
99 G_BUILD_VECTOR_TRUNC = 84, // GenericOpcodes.td:1592
100 G_CONCAT_VECTORS = 85, // GenericOpcodes.td:1599
101 G_PTRTOINT = 86, // GenericOpcodes.td:155
102 G_INTTOPTR = 87, // GenericOpcodes.td:149
103 G_BITCAST = 88, // GenericOpcodes.td:161
104 G_FREEZE = 89, // GenericOpcodes.td:284
105 G_CONSTANT_FOLD_BARRIER = 90, // GenericOpcodes.td:1959
106 G_INTRINSIC_FPTRUNC_ROUND = 91, // GenericOpcodes.td:1288
107 G_INTRINSIC_TRUNC = 92, // GenericOpcodes.td:1294
108 G_INTRINSIC_ROUND = 93, // GenericOpcodes.td:1300
109 G_INTRINSIC_LRINT = 94, // GenericOpcodes.td:1306
110 G_INTRINSIC_LLRINT = 95, // GenericOpcodes.td:1312
111 G_INTRINSIC_ROUNDEVEN = 96, // GenericOpcodes.td:1318
112 G_READCYCLECOUNTER = 97, // GenericOpcodes.td:1324
113 G_READSTEADYCOUNTER = 98, // GenericOpcodes.td:1330
114 G_LOAD = 99, // GenericOpcodes.td:1357
115 G_SEXTLOAD = 100, // GenericOpcodes.td:1366
116 G_ZEXTLOAD = 101, // GenericOpcodes.td:1374
117 G_FPEXTLOAD = 102, // GenericOpcodes.td:1383
118 G_INDEXED_LOAD = 103, // GenericOpcodes.td:1393
119 G_INDEXED_SEXTLOAD = 104, // GenericOpcodes.td:1402
120 G_INDEXED_ZEXTLOAD = 105, // GenericOpcodes.td:1410
121 G_STORE = 106, // GenericOpcodes.td:1418
122 G_FPTRUNCSTORE = 107, // GenericOpcodes.td:1428
123 G_INDEXED_STORE = 108, // GenericOpcodes.td:1436
124 G_ATOMIC_CMPXCHG_WITH_SUCCESS = 109, // GenericOpcodes.td:1447
125 G_ATOMIC_CMPXCHG = 110, // GenericOpcodes.td:1458
126 G_ATOMICRMW_XCHG = 111, // GenericOpcodes.td:1478
127 G_ATOMICRMW_ADD = 112, // GenericOpcodes.td:1479
128 G_ATOMICRMW_SUB = 113, // GenericOpcodes.td:1480
129 G_ATOMICRMW_AND = 114, // GenericOpcodes.td:1481
130 G_ATOMICRMW_NAND = 115, // GenericOpcodes.td:1482
131 G_ATOMICRMW_OR = 116, // GenericOpcodes.td:1483
132 G_ATOMICRMW_XOR = 117, // GenericOpcodes.td:1484
133 G_ATOMICRMW_MAX = 118, // GenericOpcodes.td:1485
134 G_ATOMICRMW_MIN = 119, // GenericOpcodes.td:1486
135 G_ATOMICRMW_UMAX = 120, // GenericOpcodes.td:1487
136 G_ATOMICRMW_UMIN = 121, // GenericOpcodes.td:1488
137 G_ATOMICRMW_FADD = 122, // GenericOpcodes.td:1499
138 G_ATOMICRMW_FSUB = 123, // GenericOpcodes.td:1500
139 G_ATOMICRMW_FMAX = 124, // GenericOpcodes.td:1501
140 G_ATOMICRMW_FMIN = 125, // GenericOpcodes.td:1502
141 G_ATOMICRMW_FMAXIMUM = 126, // GenericOpcodes.td:1503
142 G_ATOMICRMW_FMINIMUM = 127, // GenericOpcodes.td:1504
143 G_ATOMICRMW_FMAXIMUMNUM = 128, // GenericOpcodes.td:1505
144 G_ATOMICRMW_FMINIMUMNUM = 129, // GenericOpcodes.td:1506
145 G_ATOMICRMW_UINC_WRAP = 130, // GenericOpcodes.td:1489
146 G_ATOMICRMW_UDEC_WRAP = 131, // GenericOpcodes.td:1490
147 G_ATOMICRMW_USUB_COND = 132, // GenericOpcodes.td:1491
148 G_ATOMICRMW_USUB_SAT = 133, // GenericOpcodes.td:1492
149 G_FENCE = 134, // GenericOpcodes.td:1508
150 G_PREFETCH = 135, // GenericOpcodes.td:1515
151 G_BRCOND = 136, // GenericOpcodes.td:1655
152 G_BRINDIRECT = 137, // GenericOpcodes.td:1664
153 G_INVOKE_REGION_START = 138, // GenericOpcodes.td:1687
154 G_INTRINSIC = 139, // GenericOpcodes.td:1607
155 G_INTRINSIC_W_SIDE_EFFECTS = 140, // GenericOpcodes.td:1614
156 G_INTRINSIC_CONVERGENT = 141, // GenericOpcodes.td:1623
157 G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 142, // GenericOpcodes.td:1631
158 G_ANYEXT = 143, // GenericOpcodes.td:44
159 G_TRUNC = 144, // GenericOpcodes.td:83
160 G_TRUNC_SSAT_S = 145, // GenericOpcodes.td:91
161 G_TRUNC_SSAT_U = 146, // GenericOpcodes.td:98
162 G_TRUNC_USAT_U = 147, // GenericOpcodes.td:105
163 G_CONSTANT = 148, // GenericOpcodes.td:169
164 G_FCONSTANT = 149, // GenericOpcodes.td:177
165 G_VASTART = 150, // GenericOpcodes.td:184
166 G_VAARG = 151, // GenericOpcodes.td:191
167 G_SEXT = 152, // GenericOpcodes.td:52
168 G_SEXT_INREG = 153, // GenericOpcodes.td:66
169 G_ZEXT = 154, // GenericOpcodes.td:74
170 G_SHL = 155, // GenericOpcodes.td:404
171 G_LSHR = 156, // GenericOpcodes.td:411
172 G_ASHR = 157, // GenericOpcodes.td:418
173 G_FSHL = 158, // GenericOpcodes.td:470
174 G_FSHR = 159, // GenericOpcodes.td:478
175 G_ROTR = 160, // GenericOpcodes.td:485
176 G_ROTL = 161, // GenericOpcodes.td:492
177 G_ICMP = 162, // GenericOpcodes.td:499
178 G_FCMP = 163, // GenericOpcodes.td:506
179 G_SCMP = 164, // GenericOpcodes.td:513
180 G_UCMP = 165, // GenericOpcodes.td:520
181 G_SELECT = 166, // GenericOpcodes.td:527
182 G_UADDO = 167, // GenericOpcodes.td:609
183 G_UADDE = 168, // GenericOpcodes.td:617
184 G_USUBO = 169, // GenericOpcodes.td:639
185 G_USUBE = 170, // GenericOpcodes.td:645
186 G_SADDO = 171, // GenericOpcodes.td:624
187 G_SADDE = 172, // GenericOpcodes.td:632
188 G_SSUBO = 173, // GenericOpcodes.td:652
189 G_SSUBE = 174, // GenericOpcodes.td:659
190 G_UMULO = 175, // GenericOpcodes.td:666
191 G_SMULO = 176, // GenericOpcodes.td:674
192 G_UMULH = 177, // GenericOpcodes.td:683
193 G_SMULH = 178, // GenericOpcodes.td:692
194 G_UADDSAT = 179, // GenericOpcodes.td:704
195 G_SADDSAT = 180, // GenericOpcodes.td:712
196 G_USUBSAT = 181, // GenericOpcodes.td:720
197 G_SSUBSAT = 182, // GenericOpcodes.td:728
198 G_USHLSAT = 183, // GenericOpcodes.td:736
199 G_SSHLSAT = 184, // GenericOpcodes.td:744
200 G_SMULFIX = 185, // GenericOpcodes.td:756
201 G_UMULFIX = 186, // GenericOpcodes.td:763
202 G_SMULFIXSAT = 187, // GenericOpcodes.td:773
203 G_UMULFIXSAT = 188, // GenericOpcodes.td:780
204 G_SDIVFIX = 189, // GenericOpcodes.td:791
205 G_UDIVFIX = 190, // GenericOpcodes.td:798
206 G_SDIVFIXSAT = 191, // GenericOpcodes.td:808
207 G_UDIVFIXSAT = 192, // GenericOpcodes.td:815
208 G_FADD = 193, // GenericOpcodes.td:988
209 G_FSUB = 194, // GenericOpcodes.td:996
210 G_FMUL = 195, // GenericOpcodes.td:1004
211 G_FMA = 196, // GenericOpcodes.td:1013
212 G_FMAD = 197, // GenericOpcodes.td:1022
213 G_FDIV = 198, // GenericOpcodes.td:1030
214 G_FREM = 199, // GenericOpcodes.td:1037
215 G_FMODF = 200, // GenericOpcodes.td:1044
216 G_FPOW = 201, // GenericOpcodes.td:1051
217 G_FPOWI = 202, // GenericOpcodes.td:1058
218 G_FEXP = 203, // GenericOpcodes.td:1065
219 G_FEXP2 = 204, // GenericOpcodes.td:1072
220 G_FEXP10 = 205, // GenericOpcodes.td:1079
221 G_FLOG = 206, // GenericOpcodes.td:1086
222 G_FLOG2 = 207, // GenericOpcodes.td:1093
223 G_FLOG10 = 208, // GenericOpcodes.td:1100
224 G_FLDEXP = 209, // GenericOpcodes.td:1107
225 G_FFREXP = 210, // GenericOpcodes.td:1114
226 G_FNEG = 211, // GenericOpcodes.td:826
227 G_FPEXT = 212, // GenericOpcodes.td:832
228 G_FPTRUNC = 213, // GenericOpcodes.td:838
229 G_FPTOSI = 214, // GenericOpcodes.td:844
230 G_FPTOUI = 215, // GenericOpcodes.td:850
231 G_SITOFP = 216, // GenericOpcodes.td:856
232 G_UITOFP = 217, // GenericOpcodes.td:862
233 G_FPTOSI_SAT = 218, // GenericOpcodes.td:868
234 G_FPTOUI_SAT = 219, // GenericOpcodes.td:874
235 G_FABS = 220, // GenericOpcodes.td:880
236 G_FCOPYSIGN = 221, // GenericOpcodes.td:886
237 G_IS_FPCLASS = 222, // GenericOpcodes.td:899
238 G_FCANONICALIZE = 223, // GenericOpcodes.td:892
239 G_FMINNUM = 224, // GenericOpcodes.td:912
240 G_FMAXNUM = 225, // GenericOpcodes.td:919
241 G_FMINNUM_IEEE = 226, // GenericOpcodes.td:937
242 G_FMAXNUM_IEEE = 227, // GenericOpcodes.td:944
243 G_FMINIMUM = 228, // GenericOpcodes.td:954
244 G_FMAXIMUM = 229, // GenericOpcodes.td:961
245 G_FMINIMUMNUM = 230, // GenericOpcodes.td:969
246 G_FMAXIMUMNUM = 231, // GenericOpcodes.td:976
247 G_GET_FPENV = 232, // GenericOpcodes.td:1244
248 G_SET_FPENV = 233, // GenericOpcodes.td:1251
249 G_RESET_FPENV = 234, // GenericOpcodes.td:1258
250 G_GET_FPMODE = 235, // GenericOpcodes.td:1265
251 G_SET_FPMODE = 236, // GenericOpcodes.td:1272
252 G_RESET_FPMODE = 237, // GenericOpcodes.td:1279
253 G_GET_ROUNDING = 238, // GenericOpcodes.td:1336
254 G_SET_ROUNDING = 239, // GenericOpcodes.td:1342
255 G_PTR_ADD = 240, // GenericOpcodes.td:534
256 G_PTRMASK = 241, // GenericOpcodes.td:542
257 G_SMIN = 242, // GenericOpcodes.td:549
258 G_SMAX = 243, // GenericOpcodes.td:557
259 G_UMIN = 244, // GenericOpcodes.td:565
260 G_UMAX = 245, // GenericOpcodes.td:573
261 G_ABS = 246, // GenericOpcodes.td:581
262 G_LROUND = 247, // GenericOpcodes.td:291
263 G_LLROUND = 248, // GenericOpcodes.td:297
264 G_BR = 249, // GenericOpcodes.td:1645
265 G_BRJT = 250, // GenericOpcodes.td:1675
266 G_VSCALE = 251, // GenericOpcodes.td:1573
267 G_INSERT_SUBVECTOR = 252, // GenericOpcodes.td:1719
268 G_EXTRACT_SUBVECTOR = 253, // GenericOpcodes.td:1727
269 G_INSERT_VECTOR_ELT = 254, // GenericOpcodes.td:1735
270 G_EXTRACT_VECTOR_ELT = 255, // GenericOpcodes.td:1743
271 G_SHUFFLE_VECTOR = 256, // GenericOpcodes.td:1754
272 G_SPLAT_VECTOR = 257, // GenericOpcodes.td:1762
273 G_STEP_VECTOR = 258, // GenericOpcodes.td:1770
274 G_VECTOR_COMPRESS = 259, // GenericOpcodes.td:1777
275 G_CTTZ = 260, // GenericOpcodes.td:211
276 G_CTTZ_ZERO_POISON = 261, // GenericOpcodes.td:217
277 G_CTLZ = 262, // GenericOpcodes.td:199
278 G_CTLZ_ZERO_POISON = 263, // GenericOpcodes.td:205
279 G_CTLS = 264, // GenericOpcodes.td:223
280 G_CTPOP = 265, // GenericOpcodes.td:229
281 G_BSWAP = 266, // GenericOpcodes.td:235
282 G_BITREVERSE = 267, // GenericOpcodes.td:242
283 G_CLMUL = 268, // GenericOpcodes.td:588
284 G_CLMULH = 269, // GenericOpcodes.td:596
285 G_FCEIL = 270, // GenericOpcodes.td:1121
286 G_FCOS = 271, // GenericOpcodes.td:1128
287 G_FSIN = 272, // GenericOpcodes.td:1135
288 G_FSINCOS = 273, // GenericOpcodes.td:1142
289 G_FTAN = 274, // GenericOpcodes.td:1149
290 G_FACOS = 275, // GenericOpcodes.td:1156
291 G_FASIN = 276, // GenericOpcodes.td:1163
292 G_FATAN = 277, // GenericOpcodes.td:1170
293 G_FATAN2 = 278, // GenericOpcodes.td:1177
294 G_FCOSH = 279, // GenericOpcodes.td:1184
295 G_FSINH = 280, // GenericOpcodes.td:1191
296 G_FTANH = 281, // GenericOpcodes.td:1198
297 G_FSQRT = 282, // GenericOpcodes.td:1208
298 G_FFLOOR = 283, // GenericOpcodes.td:1215
299 G_FRINT = 284, // GenericOpcodes.td:1222
300 G_FNEARBYINT = 285, // GenericOpcodes.td:1229
301 G_ADDRSPACE_CAST = 286, // GenericOpcodes.td:248
302 G_BLOCK_ADDR = 287, // GenericOpcodes.td:254
303 G_JUMP_TABLE = 288, // GenericOpcodes.td:260
304 G_DYN_STACKALLOC = 289, // GenericOpcodes.td:266
305 G_STACKSAVE = 290, // GenericOpcodes.td:272
306 G_STACKRESTORE = 291, // GenericOpcodes.td:278
307 G_STRICT_FADD = 292, // GenericOpcodes.td:1829
308 G_STRICT_FSUB = 293, // GenericOpcodes.td:1830
309 G_STRICT_FMUL = 294, // GenericOpcodes.td:1831
310 G_STRICT_FDIV = 295, // GenericOpcodes.td:1832
311 G_STRICT_FREM = 296, // GenericOpcodes.td:1833
312 G_STRICT_FMA = 297, // GenericOpcodes.td:1834
313 G_STRICT_FSQRT = 298, // GenericOpcodes.td:1835
314 G_STRICT_FLDEXP = 299, // GenericOpcodes.td:1836
315 G_STRICT_FCMP = 300, // GenericOpcodes.td:1837
316 G_STRICT_FCMPS = 301, // GenericOpcodes.td:1838
317 G_READ_REGISTER = 302, // GenericOpcodes.td:1694
318 G_WRITE_REGISTER = 303, // GenericOpcodes.td:1704
319 G_MEMCPY = 304, // GenericOpcodes.td:1844
320 G_MEMCPY_INLINE = 305, // GenericOpcodes.td:1852
321 G_MEMMOVE = 306, // GenericOpcodes.td:1860
322 G_MEMSET = 307, // GenericOpcodes.td:1868
323 G_BZERO = 308, // GenericOpcodes.td:1875
324 G_MEMSET_INLINE = 309, // GenericOpcodes.td:1882
325 G_TRAP = 310, // GenericOpcodes.td:1892
326 G_DEBUGTRAP = 311, // GenericOpcodes.td:1899
327 G_UBSANTRAP = 312, // GenericOpcodes.td:1905
328 G_VECREDUCE_SEQ_FADD = 313, // GenericOpcodes.td:1793
329 G_VECREDUCE_SEQ_FMUL = 314, // GenericOpcodes.td:1799
330 G_VECREDUCE_FADD = 315, // GenericOpcodes.td:1805
331 G_VECREDUCE_FMUL = 316, // GenericOpcodes.td:1806
332 G_VECREDUCE_FMAX = 317, // GenericOpcodes.td:1808
333 G_VECREDUCE_FMIN = 318, // GenericOpcodes.td:1809
334 G_VECREDUCE_FMAXIMUM = 319, // GenericOpcodes.td:1810
335 G_VECREDUCE_FMINIMUM = 320, // GenericOpcodes.td:1811
336 G_VECREDUCE_FMAXIMUMNUM = 321, // GenericOpcodes.td:1812
337 G_VECREDUCE_FMINIMUMNUM = 322, // GenericOpcodes.td:1813
338 G_VECREDUCE_ADD = 323, // GenericOpcodes.td:1815
339 G_VECREDUCE_MUL = 324, // GenericOpcodes.td:1816
340 G_VECREDUCE_AND = 325, // GenericOpcodes.td:1817
341 G_VECREDUCE_OR = 326, // GenericOpcodes.td:1818
342 G_VECREDUCE_XOR = 327, // GenericOpcodes.td:1819
343 G_VECREDUCE_SMAX = 328, // GenericOpcodes.td:1820
344 G_VECREDUCE_SMIN = 329, // GenericOpcodes.td:1821
345 G_VECREDUCE_UMAX = 330, // GenericOpcodes.td:1822
346 G_VECREDUCE_UMIN = 331, // GenericOpcodes.td:1823
347 G_SBFX = 332, // GenericOpcodes.td:1917
348 G_UBFX = 333, // GenericOpcodes.td:1925
349 ADJCALLSTACKDOWN = 334, // LanaiInstrInfo.td:754
350 ADJCALLSTACKUP = 335, // LanaiInstrInfo.td:757
351 ADJDYNALLOC = 336, // LanaiInstrInfo.td:763
352 CALL = 337, // LanaiInstrInfo.td:728
353 CALLR = 338, // LanaiInstrInfo.td:729
354 ADDC_F_I_HI = 339, // LanaiInstrInfo.td:281
355 ADDC_F_I_LO = 340, // LanaiInstrInfo.td:277
356 ADDC_F_R = 341, // LanaiInstrInfo.td:293
357 ADDC_I_HI = 342, // LanaiInstrInfo.td:281
358 ADDC_I_LO = 343, // LanaiInstrInfo.td:277
359 ADDC_R = 344, // LanaiInstrInfo.td:293
360 ADD_F_I_HI = 345, // LanaiInstrInfo.td:281
361 ADD_F_I_LO = 346, // LanaiInstrInfo.td:277
362 ADD_F_R = 347, // LanaiInstrInfo.td:293
363 ADD_I_HI = 348, // LanaiInstrInfo.td:281
364 ADD_I_LO = 349, // LanaiInstrInfo.td:277
365 ADD_R = 350, // LanaiInstrInfo.td:293
366 AND_F_I_HI = 351, // LanaiInstrInfo.td:281
367 AND_F_I_LO = 352, // LanaiInstrInfo.td:277
368 AND_F_R = 353, // LanaiInstrInfo.td:306
369 AND_I_HI = 354, // LanaiInstrInfo.td:281
370 AND_I_LO = 355, // LanaiInstrInfo.td:277
371 AND_R = 356, // LanaiInstrInfo.td:306
372 BRCC = 357, // LanaiInstrInfo.td:686
373 BRIND_CC = 358, // LanaiInstrInfo.td:789
374 BRIND_CCA = 359, // LanaiInstrInfo.td:797
375 BRR = 360, // LanaiInstrInfo.td:809
376 BT = 361, // LanaiInstrInfo.td:679
377 JR = 362, // LanaiInstrInfo.td:691
378 LDADDR = 363, // LanaiInstrInfo.td:542
379 LDBs_RI = 364, // LanaiInstrInfo.td:580
380 LDBs_RR = 365, // LanaiInstrInfo.td:539
381 LDBz_RI = 366, // LanaiInstrInfo.td:577
382 LDBz_RR = 367, // LanaiInstrInfo.td:532
383 LDHs_RI = 368, // LanaiInstrInfo.td:574
384 LDHs_RR = 369, // LanaiInstrInfo.td:537
385 LDHz_RI = 370, // LanaiInstrInfo.td:571
386 LDHz_RR = 371, // LanaiInstrInfo.td:530
387 LDW_RI = 372, // LanaiInstrInfo.td:515
388 LDW_RR = 373, // LanaiInstrInfo.td:516
389 LDWz_RR = 374, // LanaiInstrInfo.td:524
390 LEADZ = 375, // LanaiInstrInfo.td:819
391 LOG0 = 376, // LanaiInstrInfo.td:249
392 LOG1 = 377, // LanaiInstrInfo.td:251
393 LOG2 = 378, // LanaiInstrInfo.td:253
394 LOG3 = 379, // LanaiInstrInfo.td:255
395 LOG4 = 380, // LanaiInstrInfo.td:257
396 MOVHI = 381, // LanaiInstrInfo.td:408
397 NOP = 382, // LanaiInstrInfo.td:245
398 OR_F_I_HI = 383, // LanaiInstrInfo.td:281
399 OR_F_I_LO = 384, // LanaiInstrInfo.td:277
400 OR_F_R = 385, // LanaiInstrInfo.td:306
401 OR_I_HI = 386, // LanaiInstrInfo.td:281
402 OR_I_LO = 387, // LanaiInstrInfo.td:277
403 OR_R = 388, // LanaiInstrInfo.td:306
404 POPC = 389, // LanaiInstrInfo.td:814
405 RET = 390, // LanaiInstrInfo.td:734
406 SA_F_I = 391, // LanaiInstrInfo.td:439
407 SA_I = 392, // LanaiInstrInfo.td:430
408 SCC = 393, // LanaiInstrInfo.td:769
409 SELECT = 394, // LanaiInstrInfo.td:776
410 SFSUB_F_RI_HI = 395, // LanaiInstrInfo.td:717
411 SFSUB_F_RI_LO = 396, // LanaiInstrInfo.td:713
412 SFSUB_F_RR = 397, // LanaiInstrInfo.td:709
413 SHL_F_R = 398, // LanaiInstrInfo.td:460
414 SHL_R = 399, // LanaiInstrInfo.td:448
415 SLI = 400, // LanaiInstrInfo.td:582
416 SL_F_I = 401, // LanaiInstrInfo.td:437
417 SL_I = 402, // LanaiInstrInfo.td:428
418 SRA_F_R = 403, // LanaiInstrInfo.td:466
419 SRA_R = 404, // LanaiInstrInfo.td:455
420 SRL_F_R = 405, // LanaiInstrInfo.td:463
421 SRL_R = 406, // LanaiInstrInfo.td:452
422 STADDR = 407, // LanaiInstrInfo.td:641
423 STB_RI = 408, // LanaiInstrInfo.td:672
424 STB_RR = 409, // LanaiInstrInfo.td:638
425 STH_RI = 410, // LanaiInstrInfo.td:669
426 STH_RR = 411, // LanaiInstrInfo.td:636
427 SUBB_F_I_HI = 412, // LanaiInstrInfo.td:281
428 SUBB_F_I_LO = 413, // LanaiInstrInfo.td:277
429 SUBB_F_R = 414, // LanaiInstrInfo.td:293
430 SUBB_I_HI = 415, // LanaiInstrInfo.td:281
431 SUBB_I_LO = 416, // LanaiInstrInfo.td:277
432 SUBB_R = 417, // LanaiInstrInfo.td:293
433 SUB_F_I_HI = 418, // LanaiInstrInfo.td:281
434 SUB_F_I_LO = 419, // LanaiInstrInfo.td:277
435 SUB_F_R = 420, // LanaiInstrInfo.td:293
436 SUB_I_HI = 421, // LanaiInstrInfo.td:281
437 SUB_I_LO = 422, // LanaiInstrInfo.td:277
438 SUB_R = 423, // LanaiInstrInfo.td:293
439 SW_RI = 424, // LanaiInstrInfo.td:631
440 SW_RR = 425, // LanaiInstrInfo.td:630
441 TRAILZ = 426, // LanaiInstrInfo.td:823
442 XOR_F_I_HI = 427, // LanaiInstrInfo.td:281
443 XOR_F_I_LO = 428, // LanaiInstrInfo.td:277
444 XOR_F_R = 429, // LanaiInstrInfo.td:306
445 XOR_I_HI = 430, // LanaiInstrInfo.td:281
446 XOR_I_LO = 431, // LanaiInstrInfo.td:277
447 XOR_R = 432, // LanaiInstrInfo.td:306
448 INSTRUCTION_LIST_END = 433
449 };
450
451} // namespace llvm::Lanai
452
453#endif // GET_INSTRINFO_ENUM
454
455#ifdef GET_INSTRINFO_SCHED_ENUM
456#undef GET_INSTRINFO_SCHED_ENUM
457
458namespace llvm::Lanai::Sched {
459
460 enum {
461 NoInstrModel = 0,
462 IIC_ALU_WriteALU = 1,
463 IIC_ALU = 2,
464 IIC_LD_WriteLD = 3,
465 IIC_LDSW_WriteLDSW = 4,
466 WriteLD = 5,
467 IIC_ST_WriteST = 6,
468 IIC_STSW_WriteSTSW = 7,
469 SCHED_LIST_END = 8
470 };
471
472} // namespace llvm::Lanai::Sched
473
474#endif // GET_INSTRINFO_SCHED_ENUM
475
476#if defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
477
478namespace llvm {
479
480struct LanaiInstrTable {
481 MCInstrDesc Insts[433];
482 static_assert(alignof(MCInstrDesc) >= alignof(MCPhysReg), "Unwanted padding between Insts and ImplicitOps");
483 MCPhysReg ImplicitOps[8];
484 char Padding[sizeof(MCOperandInfo) - sizeof ImplicitOps % sizeof(MCOperandInfo)];
485 static_assert(alignof(MCInstrDesc) >= alignof(MCOperandInfo), "Unwanted padding between Insts and OperandInfo");
486 MCOperandInfo OperandInfo[174];
487};
488} // namespace llvm
489
490#endif // defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
491
492#ifdef GET_INSTRINFO_MC_DESC
493#undef GET_INSTRINFO_MC_DESC
494
495namespace llvm {
496
497static_assert((sizeof LanaiInstrTable::ImplicitOps + sizeof LanaiInstrTable::Padding) % sizeof(MCOperandInfo) == 0);
498static constexpr unsigned LanaiOpInfoBase = (sizeof LanaiInstrTable::ImplicitOps + sizeof LanaiInstrTable::Padding) / sizeof(MCOperandInfo);
499
500extern const LanaiInstrTable LanaiDescs = {
501 {
502 { 432, 4, 1, 4, 1, 0, 0, LanaiOpInfoBase + 156, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR_R
503 { 431, 3, 1, 4, 1, 0, 0, LanaiOpInfoBase + 153, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR_I_LO
504 { 430, 3, 1, 4, 1, 0, 0, LanaiOpInfoBase + 153, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR_I_HI
505 { 429, 4, 1, 4, 1, 0, 1, LanaiOpInfoBase + 156, 6, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR_F_R
506 { 428, 3, 1, 4, 1, 0, 1, LanaiOpInfoBase + 153, 6, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR_F_I_LO
507 { 427, 3, 1, 4, 1, 0, 1, LanaiOpInfoBase + 153, 6, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR_F_I_HI
508 { 426, 2, 1, 4, 1, 0, 0, LanaiOpInfoBase + 151, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TRAILZ
509 { 425, 4, 0, 4, 6, 0, 0, LanaiOpInfoBase + 166, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SW_RR
510 { 424, 4, 0, 4, 6, 0, 0, LanaiOpInfoBase + 162, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SW_RI
511 { 423, 4, 1, 4, 1, 0, 0, LanaiOpInfoBase + 156, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_R
512 { 422, 3, 1, 4, 1, 0, 0, LanaiOpInfoBase + 153, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_I_LO
513 { 421, 3, 1, 4, 1, 0, 0, LanaiOpInfoBase + 153, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_I_HI
514 { 420, 4, 1, 4, 1, 0, 1, LanaiOpInfoBase + 156, 6, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_F_R
515 { 419, 3, 1, 4, 1, 0, 1, LanaiOpInfoBase + 153, 6, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_F_I_LO
516 { 418, 3, 1, 4, 1, 0, 1, LanaiOpInfoBase + 153, 6, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_F_I_HI
517 { 417, 4, 1, 4, 1, 1, 0, LanaiOpInfoBase + 156, 6, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBB_R
518 { 416, 3, 1, 4, 1, 1, 0, LanaiOpInfoBase + 153, 6, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBB_I_LO
519 { 415, 3, 1, 4, 1, 1, 0, LanaiOpInfoBase + 153, 6, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBB_I_HI
520 { 414, 4, 1, 4, 1, 1, 1, LanaiOpInfoBase + 156, 4, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBB_F_R
521 { 413, 3, 1, 4, 1, 1, 1, LanaiOpInfoBase + 153, 4, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBB_F_I_LO
522 { 412, 3, 1, 4, 1, 1, 1, LanaiOpInfoBase + 153, 4, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBB_F_I_HI
523 { 411, 4, 0, 4, 6, 0, 0, LanaiOpInfoBase + 166, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STH_RR
524 { 410, 4, 0, 4, 7, 0, 0, LanaiOpInfoBase + 162, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STH_RI
525 { 409, 4, 0, 4, 6, 0, 0, LanaiOpInfoBase + 166, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STB_RR
526 { 408, 4, 0, 4, 7, 0, 0, LanaiOpInfoBase + 162, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STB_RI
527 { 407, 2, 0, 4, 6, 0, 0, LanaiOpInfoBase + 34, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STADDR
528 { 406, 4, 1, 4, 1, 0, 0, LanaiOpInfoBase + 156, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SRL_R
529 { 405, 4, 1, 4, 1, 0, 1, LanaiOpInfoBase + 156, 6, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SRL_F_R
530 { 404, 4, 1, 4, 1, 0, 0, LanaiOpInfoBase + 156, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SRA_R
531 { 403, 4, 1, 4, 1, 0, 1, LanaiOpInfoBase + 156, 6, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SRA_F_R
532 { 402, 3, 1, 4, 1, 0, 0, LanaiOpInfoBase + 153, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SL_I
533 { 401, 3, 1, 4, 1, 0, 1, LanaiOpInfoBase + 153, 6, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SL_F_I
534 { 400, 2, 1, 4, 0, 0, 0, LanaiOpInfoBase + 34, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SLI
535 { 399, 4, 1, 4, 1, 0, 0, LanaiOpInfoBase + 156, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHL_R
536 { 398, 4, 1, 4, 1, 0, 1, LanaiOpInfoBase + 156, 6, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHL_F_R
537 { 397, 2, 0, 4, 1, 0, 1, LanaiOpInfoBase + 151, 6, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SFSUB_F_RR
538 { 396, 2, 0, 4, 1, 0, 1, LanaiOpInfoBase + 34, 6, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SFSUB_F_RI_LO
539 { 395, 2, 0, 4, 1, 0, 1, LanaiOpInfoBase + 34, 6, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SFSUB_F_RI_HI
540 { 394, 4, 1, 4, 1, 1, 0, LanaiOpInfoBase + 170, 6, 0|(1ULL<<MCID::Select)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SELECT
541 { 393, 2, 1, 4, 2, 1, 0, LanaiOpInfoBase + 34, 6, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SCC
542 { 392, 3, 1, 4, 1, 0, 0, LanaiOpInfoBase + 153, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SA_I
543 { 391, 3, 1, 4, 1, 0, 1, LanaiOpInfoBase + 153, 6, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SA_F_I
544 { 390, 0, 0, 4, 0, 1, 0, LanaiOpInfoBase + 1, 7, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RET
545 { 389, 2, 1, 4, 1, 0, 0, LanaiOpInfoBase + 151, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // POPC
546 { 388, 4, 1, 4, 1, 0, 0, LanaiOpInfoBase + 156, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OR_R
547 { 387, 3, 1, 4, 1, 0, 0, LanaiOpInfoBase + 153, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OR_I_LO
548 { 386, 3, 1, 4, 1, 0, 0, LanaiOpInfoBase + 153, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OR_I_HI
549 { 385, 4, 1, 4, 1, 0, 1, LanaiOpInfoBase + 156, 6, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OR_F_R
550 { 384, 3, 1, 4, 1, 0, 1, LanaiOpInfoBase + 153, 6, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OR_F_I_LO
551 { 383, 3, 1, 4, 1, 0, 1, LanaiOpInfoBase + 153, 6, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OR_F_I_HI
552 { 382, 0, 0, 4, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NOP
553 { 381, 2, 1, 4, 1, 0, 0, LanaiOpInfoBase + 34, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOVHI
554 { 380, 0, 0, 4, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOG4
555 { 379, 0, 0, 4, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOG3
556 { 378, 0, 0, 4, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOG2
557 { 377, 0, 0, 4, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOG1
558 { 376, 0, 0, 4, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOG0
559 { 375, 2, 1, 4, 1, 0, 0, LanaiOpInfoBase + 151, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LEADZ
560 { 374, 4, 1, 4, 5, 0, 0, LanaiOpInfoBase + 166, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDWz_RR
561 { 373, 4, 1, 4, 5, 0, 0, LanaiOpInfoBase + 166, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDW_RR
562 { 372, 4, 1, 4, 3, 0, 0, LanaiOpInfoBase + 162, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDW_RI
563 { 371, 4, 1, 4, 5, 0, 0, LanaiOpInfoBase + 166, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDHz_RR
564 { 370, 4, 1, 4, 4, 0, 0, LanaiOpInfoBase + 162, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDHz_RI
565 { 369, 4, 1, 4, 5, 0, 0, LanaiOpInfoBase + 166, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDHs_RR
566 { 368, 4, 1, 4, 4, 0, 0, LanaiOpInfoBase + 162, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDHs_RI
567 { 367, 4, 1, 4, 5, 0, 0, LanaiOpInfoBase + 166, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDBz_RR
568 { 366, 4, 1, 4, 4, 0, 0, LanaiOpInfoBase + 162, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDBz_RI
569 { 365, 4, 1, 4, 5, 0, 0, LanaiOpInfoBase + 166, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDBs_RR
570 { 364, 4, 1, 4, 4, 0, 0, LanaiOpInfoBase + 162, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDBs_RI
571 { 363, 2, 1, 4, 3, 0, 0, LanaiOpInfoBase + 34, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDADDR
572 { 362, 1, 0, 4, 1, 0, 0, LanaiOpInfoBase + 28, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JR
573 { 361, 1, 0, 4, 2, 0, 0, LanaiOpInfoBase + 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BT
574 { 360, 2, 0, 4, 0, 1, 0, LanaiOpInfoBase + 160, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BRR
575 { 359, 3, 0, 4, 1, 1, 0, LanaiOpInfoBase + 153, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BRIND_CCA
576 { 358, 2, 0, 4, 1, 1, 0, LanaiOpInfoBase + 34, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BRIND_CC
577 { 357, 2, 0, 4, 2, 1, 0, LanaiOpInfoBase + 9, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BRCC
578 { 356, 4, 1, 4, 1, 0, 0, LanaiOpInfoBase + 156, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND_R
579 { 355, 3, 1, 4, 1, 0, 0, LanaiOpInfoBase + 153, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND_I_LO
580 { 354, 3, 1, 4, 1, 0, 0, LanaiOpInfoBase + 153, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND_I_HI
581 { 353, 4, 1, 4, 1, 0, 1, LanaiOpInfoBase + 156, 6, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND_F_R
582 { 352, 3, 1, 4, 1, 0, 1, LanaiOpInfoBase + 153, 6, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND_F_I_LO
583 { 351, 3, 1, 4, 1, 0, 1, LanaiOpInfoBase + 153, 6, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND_F_I_HI
584 { 350, 4, 1, 4, 1, 0, 0, LanaiOpInfoBase + 156, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_R
585 { 349, 3, 1, 4, 1, 0, 0, LanaiOpInfoBase + 153, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_I_LO
586 { 348, 3, 1, 4, 1, 0, 0, LanaiOpInfoBase + 153, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_I_HI
587 { 347, 4, 1, 4, 1, 0, 1, LanaiOpInfoBase + 156, 6, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_F_R
588 { 346, 3, 1, 4, 1, 0, 1, LanaiOpInfoBase + 153, 6, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_F_I_LO
589 { 345, 3, 1, 4, 1, 0, 1, LanaiOpInfoBase + 153, 6, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_F_I_HI
590 { 344, 4, 1, 4, 1, 1, 0, LanaiOpInfoBase + 156, 6, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC_R
591 { 343, 3, 1, 4, 1, 1, 0, LanaiOpInfoBase + 153, 6, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC_I_LO
592 { 342, 3, 1, 4, 1, 1, 0, LanaiOpInfoBase + 153, 6, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC_I_HI
593 { 341, 4, 1, 4, 1, 1, 1, LanaiOpInfoBase + 156, 4, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC_F_R
594 { 340, 3, 1, 4, 1, 1, 1, LanaiOpInfoBase + 153, 4, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC_F_I_LO
595 { 339, 3, 1, 4, 1, 1, 1, LanaiOpInfoBase + 153, 4, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC_F_I_HI
596 { 338, 1, 0, 4, 0, 1, 1, LanaiOpInfoBase + 28, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CALLR
597 { 337, 1, 0, 4, 0, 1, 1, LanaiOpInfoBase + 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CALL
598 { 336, 2, 1, 4, 0, 1, 1, LanaiOpInfoBase + 151, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADJDYNALLOC
599 { 335, 2, 0, 4, 0, 1, 1, LanaiOpInfoBase + 20, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADJCALLSTACKUP
600 { 334, 2, 0, 4, 0, 1, 1, LanaiOpInfoBase + 20, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADJCALLSTACKDOWN
601 { 333, 4, 1, 0, 0, 0, 0, LanaiOpInfoBase + 147, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UBFX
602 { 332, 4, 1, 0, 0, 0, 0, LanaiOpInfoBase + 147, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SBFX
603 { 331, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_UMIN
604 { 330, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_UMAX
605 { 329, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SMIN
606 { 328, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SMAX
607 { 327, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_XOR
608 { 326, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_OR
609 { 325, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_AND
610 { 324, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_MUL
611 { 323, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_ADD
612 { 322, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMINIMUMNUM
613 { 321, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMAXIMUMNUM
614 { 320, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMINIMUM
615 { 319, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMAXIMUM
616 { 318, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMIN
617 { 317, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMAX
618 { 316, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMUL
619 { 315, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FADD
620 { 314, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SEQ_FMUL
621 { 313, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SEQ_FADD
622 { 312, 1, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UBSANTRAP
623 { 311, 0, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_DEBUGTRAP
624 { 310, 0, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRAP
625 { 309, 3, 0, 0, 0, 0, 0, LanaiOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMSET_INLINE
626 { 308, 3, 0, 0, 0, 0, 0, LanaiOpInfoBase + 57, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BZERO
627 { 307, 4, 0, 0, 0, 0, 0, LanaiOpInfoBase + 143, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMSET
628 { 306, 4, 0, 0, 0, 0, 0, LanaiOpInfoBase + 143, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMMOVE
629 { 305, 3, 0, 0, 0, 0, 0, LanaiOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMCPY_INLINE
630 { 304, 4, 0, 0, 0, 0, 0, LanaiOpInfoBase + 143, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMCPY
631 { 303, 2, 0, 0, 0, 0, 0, LanaiOpInfoBase + 141, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_WRITE_REGISTER
632 { 302, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_READ_REGISTER
633 { 301, 4, 1, 0, 0, 0, 0, LanaiOpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FCMPS
634 { 300, 4, 1, 0, 0, 0, 0, LanaiOpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FCMP
635 { 299, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FLDEXP
636 { 298, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FSQRT
637 { 297, 4, 1, 0, 0, 0, 0, LanaiOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FMA
638 { 296, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FREM
639 { 295, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FDIV
640 { 294, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FMUL
641 { 293, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FSUB
642 { 292, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FADD
643 { 291, 1, 0, 0, 0, 0, 0, LanaiOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STACKRESTORE
644 { 290, 1, 1, 0, 0, 0, 0, LanaiOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STACKSAVE
645 { 289, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 68, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_DYN_STACKALLOC
646 { 288, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_JUMP_TABLE
647 { 287, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BLOCK_ADDR
648 { 286, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ADDRSPACE_CAST
649 { 285, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FNEARBYINT
650 { 284, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FRINT
651 { 283, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FFLOOR
652 { 282, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSQRT
653 { 281, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FTANH
654 { 280, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSINH
655 { 279, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCOSH
656 { 278, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FATAN2
657 { 277, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FATAN
658 { 276, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FASIN
659 { 275, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FACOS
660 { 274, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FTAN
661 { 273, 3, 2, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSINCOS
662 { 272, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSIN
663 { 271, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCOS
664 { 270, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCEIL
665 { 269, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CLMULH
666 { 268, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CLMUL
667 { 267, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BITREVERSE
668 { 266, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BSWAP
669 { 265, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTPOP
670 { 264, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTLS
671 { 263, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTLZ_ZERO_POISON
672 { 262, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTLZ
673 { 261, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTTZ_ZERO_POISON
674 { 260, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTTZ
675 { 259, 4, 1, 0, 0, 0, 0, LanaiOpInfoBase + 137, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECTOR_COMPRESS
676 { 258, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STEP_VECTOR
677 { 257, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SPLAT_VECTOR
678 { 256, 4, 1, 0, 0, 0, 0, LanaiOpInfoBase + 133, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SHUFFLE_VECTOR
679 { 255, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_EXTRACT_VECTOR_ELT
680 { 254, 4, 1, 0, 0, 0, 0, LanaiOpInfoBase + 126, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INSERT_VECTOR_ELT
681 { 253, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 57, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_EXTRACT_SUBVECTOR
682 { 252, 4, 1, 0, 0, 0, 0, LanaiOpInfoBase + 62, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INSERT_SUBVECTOR
683 { 251, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VSCALE
684 { 250, 3, 0, 0, 0, 0, 0, LanaiOpInfoBase + 123, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BRJT
685 { 249, 1, 0, 0, 0, 0, 0, LanaiOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BR
686 { 248, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LLROUND
687 { 247, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LROUND
688 { 246, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ABS
689 { 245, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMAX
690 { 244, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMIN
691 { 243, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMAX
692 { 242, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMIN
693 { 241, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTRMASK
694 { 240, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTR_ADD
695 { 239, 1, 0, 0, 0, 0, 0, LanaiOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SET_ROUNDING
696 { 238, 1, 1, 0, 0, 0, 0, LanaiOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GET_ROUNDING
697 { 237, 0, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_RESET_FPMODE
698 { 236, 1, 0, 0, 0, 0, 0, LanaiOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SET_FPMODE
699 { 235, 1, 1, 0, 0, 0, 0, LanaiOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GET_FPMODE
700 { 234, 0, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_RESET_FPENV
701 { 233, 1, 0, 0, 0, 0, 0, LanaiOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SET_FPENV
702 { 232, 1, 1, 0, 0, 0, 0, LanaiOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GET_FPENV
703 { 231, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXIMUMNUM
704 { 230, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINIMUMNUM
705 { 229, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXIMUM
706 { 228, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINIMUM
707 { 227, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXNUM_IEEE
708 { 226, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINNUM_IEEE
709 { 225, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXNUM
710 { 224, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINNUM
711 { 223, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCANONICALIZE
712 { 222, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 97, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_IS_FPCLASS
713 { 221, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCOPYSIGN
714 { 220, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FABS
715 { 219, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOUI_SAT
716 { 218, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOSI_SAT
717 { 217, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UITOFP
718 { 216, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SITOFP
719 { 215, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOUI
720 { 214, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOSI
721 { 213, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTRUNC
722 { 212, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPEXT
723 { 211, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FNEG
724 { 210, 3, 2, 0, 0, 0, 0, LanaiOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FFREXP
725 { 209, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLDEXP
726 { 208, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLOG10
727 { 207, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLOG2
728 { 206, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLOG
729 { 205, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FEXP10
730 { 204, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FEXP2
731 { 203, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FEXP
732 { 202, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPOWI
733 { 201, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPOW
734 { 200, 3, 2, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMODF
735 { 199, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FREM
736 { 198, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FDIV
737 { 197, 4, 1, 0, 0, 0, 0, LanaiOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAD
738 { 196, 4, 1, 0, 0, 0, 0, LanaiOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMA
739 { 195, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMUL
740 { 194, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSUB
741 { 193, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FADD
742 { 192, 4, 1, 0, 0, 0, 0, LanaiOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIVFIXSAT
743 { 191, 4, 1, 0, 0, 0, 0, LanaiOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIVFIXSAT
744 { 190, 4, 1, 0, 0, 0, 0, LanaiOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIVFIX
745 { 189, 4, 1, 0, 0, 0, 0, LanaiOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIVFIX
746 { 188, 4, 1, 0, 0, 0, 0, LanaiOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULFIXSAT
747 { 187, 4, 1, 0, 0, 0, 0, LanaiOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULFIXSAT
748 { 186, 4, 1, 0, 0, 0, 0, LanaiOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULFIX
749 { 185, 4, 1, 0, 0, 0, 0, LanaiOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULFIX
750 { 184, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSHLSAT
751 { 183, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USHLSAT
752 { 182, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSUBSAT
753 { 181, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USUBSAT
754 { 180, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SADDSAT
755 { 179, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UADDSAT
756 { 178, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULH
757 { 177, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULH
758 { 176, 4, 2, 0, 0, 0, 0, LanaiOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULO
759 { 175, 4, 2, 0, 0, 0, 0, LanaiOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULO
760 { 174, 5, 2, 0, 0, 0, 0, LanaiOpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSUBE
761 { 173, 4, 2, 0, 0, 0, 0, LanaiOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSUBO
762 { 172, 5, 2, 0, 0, 0, 0, LanaiOpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SADDE
763 { 171, 4, 2, 0, 0, 0, 0, LanaiOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SADDO
764 { 170, 5, 2, 0, 0, 0, 0, LanaiOpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USUBE
765 { 169, 4, 2, 0, 0, 0, 0, LanaiOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USUBO
766 { 168, 5, 2, 0, 0, 0, 0, LanaiOpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UADDE
767 { 167, 4, 2, 0, 0, 0, 0, LanaiOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UADDO
768 { 166, 4, 1, 0, 0, 0, 0, LanaiOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SELECT
769 { 165, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 111, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UCMP
770 { 164, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 111, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SCMP
771 { 163, 4, 1, 0, 0, 0, 0, LanaiOpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCMP
772 { 162, 4, 1, 0, 0, 0, 0, LanaiOpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ICMP
773 { 161, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ROTL
774 { 160, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ROTR
775 { 159, 4, 1, 0, 0, 0, 0, LanaiOpInfoBase + 103, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSHR
776 { 158, 4, 1, 0, 0, 0, 0, LanaiOpInfoBase + 103, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSHL
777 { 157, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASHR
778 { 156, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LSHR
779 { 155, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SHL
780 { 154, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ZEXT
781 { 153, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SEXT_INREG
782 { 152, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SEXT
783 { 151, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 97, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VAARG
784 { 150, 1, 0, 0, 0, 0, 0, LanaiOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VASTART
785 { 149, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCONSTANT
786 { 148, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONSTANT
787 { 147, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC_USAT_U
788 { 146, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC_SSAT_U
789 { 145, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC_SSAT_S
790 { 144, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC
791 { 143, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ANYEXT
792 { 142, 1, 0, 0, 0, 0, 0, LanaiOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
793 { 141, 1, 0, 0, 0, 0, 0, LanaiOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_INTRINSIC_CONVERGENT
794 { 140, 1, 0, 0, 0, 0, 0, LanaiOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_W_SIDE_EFFECTS
795 { 139, 1, 0, 0, 0, 0, 0, LanaiOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC
796 { 138, 0, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INVOKE_REGION_START
797 { 137, 1, 0, 0, 0, 0, 0, LanaiOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BRINDIRECT
798 { 136, 2, 0, 0, 0, 0, 0, LanaiOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BRCOND
799 { 135, 4, 0, 0, 0, 0, 0, LanaiOpInfoBase + 93, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PREFETCH
800 { 134, 2, 0, 0, 0, 0, 0, LanaiOpInfoBase + 20, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FENCE
801 { 133, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_USUB_SAT
802 { 132, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_USUB_COND
803 { 131, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UDEC_WRAP
804 { 130, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UINC_WRAP
805 { 129, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMINIMUMNUM
806 { 128, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMAXIMUMNUM
807 { 127, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMINIMUM
808 { 126, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMAXIMUM
809 { 125, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMIN
810 { 124, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMAX
811 { 123, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FSUB
812 { 122, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FADD
813 { 121, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UMIN
814 { 120, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UMAX
815 { 119, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_MIN
816 { 118, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_MAX
817 { 117, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_XOR
818 { 116, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_OR
819 { 115, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_NAND
820 { 114, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_AND
821 { 113, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_SUB
822 { 112, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_ADD
823 { 111, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_XCHG
824 { 110, 4, 1, 0, 0, 0, 0, LanaiOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMIC_CMPXCHG
825 { 109, 5, 2, 0, 0, 0, 0, LanaiOpInfoBase + 81, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
826 { 108, 5, 1, 0, 0, 0, 0, LanaiOpInfoBase + 76, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_STORE
827 { 107, 2, 0, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTRUNCSTORE
828 { 106, 2, 0, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STORE
829 { 105, 5, 2, 0, 0, 0, 0, LanaiOpInfoBase + 71, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_ZEXTLOAD
830 { 104, 5, 2, 0, 0, 0, 0, LanaiOpInfoBase + 71, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_SEXTLOAD
831 { 103, 5, 2, 0, 0, 0, 0, LanaiOpInfoBase + 71, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_LOAD
832 { 102, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPEXTLOAD
833 { 101, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ZEXTLOAD
834 { 100, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SEXTLOAD
835 { 99, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LOAD
836 { 98, 1, 1, 0, 0, 0, 0, LanaiOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_READSTEADYCOUNTER
837 { 97, 1, 1, 0, 0, 0, 0, LanaiOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_READCYCLECOUNTER
838 { 96, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_ROUNDEVEN
839 { 95, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_LLRINT
840 { 94, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_LRINT
841 { 93, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_ROUND
842 { 92, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_TRUNC
843 { 91, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 68, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_FPTRUNC_ROUND
844 { 90, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONSTANT_FOLD_BARRIER
845 { 89, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FREEZE
846 { 88, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BITCAST
847 { 87, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTTOPTR
848 { 86, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTRTOINT
849 { 85, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONCAT_VECTORS
850 { 84, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BUILD_VECTOR_TRUNC
851 { 83, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BUILD_VECTOR
852 { 82, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MERGE_VALUES
853 { 81, 4, 1, 0, 0, 0, 0, LanaiOpInfoBase + 62, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INSERT
854 { 80, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UNMERGE_VALUES
855 { 79, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 57, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_EXTRACT
856 { 78, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONSTANT_POOL
857 { 77, 5, 1, 0, 0, 0, 0, LanaiOpInfoBase + 52, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTRAUTH_GLOBAL_VALUE
858 { 76, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GLOBAL_VALUE
859 { 75, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FRAME_INDEX
860 { 74, 1, 1, 0, 0, 0, 0, LanaiOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PHI
861 { 73, 1, 1, 0, 0, 0, 0, LanaiOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_IMPLICIT_DEF
862 { 72, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SAVGCEIL
863 { 71, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SAVGFLOOR
864 { 70, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UAVGCEIL
865 { 69, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UAVGFLOOR
866 { 68, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ABDU
867 { 67, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ABDS
868 { 66, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_XOR
869 { 65, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_OR
870 { 64, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_AND
871 { 63, 4, 2, 0, 0, 0, 0, LanaiOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIVREM
872 { 62, 4, 2, 0, 0, 0, 0, LanaiOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIVREM
873 { 61, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UREM
874 { 60, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SREM
875 { 59, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIV
876 { 58, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIV
877 { 57, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MUL
878 { 56, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SUB
879 { 55, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ADD
880 { 54, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASSERT_ALIGN
881 { 53, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASSERT_ZEXT
882 { 52, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASSERT_SEXT
883 { 51, 1, 0, 0, 0, 0, 0, LanaiOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_GLUE
884 { 50, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_LOOP
885 { 49, 1, 1, 0, 0, 0, 0, LanaiOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_ANCHOR
886 { 48, 1, 1, 0, 0, 0, 0, LanaiOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_ENTRY
887 { 47, 1, 0, 0, 0, 0, 0, LanaiOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RELOC_NONE
888 { 46, 1, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JUMP_TABLE_DEBUG_INFO
889 { 45, 0, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMBARRIER
890 { 44, 0, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FAKE_USE
891 { 43, 0, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ICALL_BRANCH_FUNNEL
892 { 42, 3, 0, 0, 0, 0, 0, LanaiOpInfoBase + 36, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_14715
893 { 41, 2, 0, 0, 0, 0, 0, LanaiOpInfoBase + 34, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_14714
894 { 40, 0, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_TAIL_CALL
895 { 39, 0, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_FUNCTION_EXIT
896 { 38, 0, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_RET
897 { 37, 0, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_FUNCTION_ENTER
898 { 36, 0, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_OP
899 { 35, 1, 1, 0, 0, 0, 0, LanaiOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FAULTING_OP
900 { 34, 2, 0, 0, 0, 0, 0, LanaiOpInfoBase + 32, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_ESCAPE
901 { 33, 0, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STATEPOINT
902 { 32, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 29, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_14713
903 { 31, 1, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PREALLOCATED_SETUP
904 { 30, 1, 1, 0, 0, 0, 0, LanaiOpInfoBase + 28, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_14348
905 { 29, 6, 1, 0, 0, 0, 0, LanaiOpInfoBase + 22, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHPOINT
906 { 28, 0, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FENTRY_CALL
907 { 27, 2, 0, 0, 0, 0, 0, LanaiOpInfoBase + 20, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STACKMAP
908 { 26, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 18, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARITH_FENCE
909 { 25, 4, 0, 0, 0, 0, 0, LanaiOpInfoBase + 14, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PSEUDO_PROBE
910 { 24, 1, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LIFETIME_END
911 { 23, 1, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LIFETIME_START
912 { 22, 0, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BUNDLE
913 { 21, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 11, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_LANEMASK
914 { 20, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY
915 { 19, 2, 1, 0, 0, 0, 0, LanaiOpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REG_SEQUENCE
916 { 18, 1, 0, 0, 0, 0, 0, LanaiOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_LABEL
917 { 17, 0, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_PHI
918 { 16, 0, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_INSTR_REF
919 { 15, 0, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_VALUE_LIST
920 { 14, 0, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_VALUE
921 { 13, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_TO_REGCLASS
922 { 12, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBREG_TO_REG
923 { 11, 1, 1, 0, 0, 0, 0, LanaiOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INIT_UNDEF
924 { 10, 1, 1, 0, 0, 0, 0, LanaiOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // IMPLICIT_DEF
925 { 9, 4, 1, 0, 0, 0, 0, LanaiOpInfoBase + 5, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INSERT_SUBREG
926 { 8, 3, 1, 0, 0, 0, 0, LanaiOpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTRACT_SUBREG
927 { 7, 0, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // KILL
928 { 6, 1, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ANNOTATION_LABEL
929 { 5, 1, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GC_LABEL
930 { 4, 1, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EH_LABEL
931 { 3, 1, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CFI_INSTRUCTION
932 { 2, 0, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INLINEASM_BR
933 { 1, 0, 0, 0, 0, 0, 0, LanaiOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INLINEASM
934 { 0, 1, 1, 0, 0, 0, 0, LanaiOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PHI
935 }, {
936 /* 0 */
937 /* 0 */ Lanai::SP, Lanai::SP,
938 /* 2 */ Lanai::SP, Lanai::RCA,
939 /* 4 */ Lanai::SR, Lanai::SR,
940 /* 6 */ Lanai::SR,
941 /* 7 */ Lanai::RCA,
942 }, {
943 0
944 }, {
945 /* 0 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
946 /* 1 */
947 /* 1 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
948 /* 2 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
949 /* 5 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
950 /* 9 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
951 /* 11 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
952 /* 14 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
953 /* 18 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) },
954 /* 20 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
955 /* 22 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
956 /* 28 */ { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
957 /* 29 */ { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
958 /* 32 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
959 /* 34 */ { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
960 /* 36 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
961 /* 39 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
962 /* 42 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
963 /* 45 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
964 /* 49 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
965 /* 50 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
966 /* 52 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
967 /* 57 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
968 /* 60 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
969 /* 62 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
970 /* 66 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
971 /* 68 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
972 /* 71 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
973 /* 76 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
974 /* 81 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
975 /* 86 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
976 /* 90 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
977 /* 93 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_2, 0 },
978 /* 97 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
979 /* 100 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
980 /* 103 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
981 /* 107 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
982 /* 111 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
983 /* 114 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
984 /* 119 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
985 /* 123 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
986 /* 126 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
987 /* 130 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
988 /* 133 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
989 /* 137 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
990 /* 141 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
991 /* 143 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
992 /* 147 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
993 /* 151 */ { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
994 /* 153 */ { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
995 /* 156 */ { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 },
996 /* 160 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
997 /* 162 */ { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
998 /* 166 */ { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
999 /* 170 */ { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1000 }
1001};
1002
1003
1004#ifdef __GNUC__
1005#pragma GCC diagnostic push
1006#pragma GCC diagnostic ignored "-Woverlength-strings"
1007#endif
1008extern const char LanaiInstrNameData[] = {
1009 /* 0 */ "G_FLOG10\000"
1010 /* 9 */ "G_FEXP10\000"
1011 /* 18 */ "LOG0\000"
1012 /* 23 */ "LOG1\000"
1013 /* 28 */ "G_FLOG2\000"
1014 /* 36 */ "G_FATAN2\000"
1015 /* 45 */ "G_FEXP2\000"
1016 /* 53 */ "LOG3\000"
1017 /* 58 */ "LOG4\000"
1018 /* 63 */ "BRIND_CCA\000"
1019 /* 73 */ "G_FMA\000"
1020 /* 79 */ "G_STRICT_FMA\000"
1021 /* 92 */ "G_FSUB\000"
1022 /* 99 */ "G_STRICT_FSUB\000"
1023 /* 113 */ "G_ATOMICRMW_FSUB\000"
1024 /* 130 */ "G_SUB\000"
1025 /* 136 */ "G_ATOMICRMW_SUB\000"
1026 /* 152 */ "BRCC\000"
1027 /* 157 */ "SCC\000"
1028 /* 161 */ "BRIND_CC\000"
1029 /* 170 */ "G_INTRINSIC\000"
1030 /* 182 */ "G_FPTRUNC\000"
1031 /* 192 */ "G_INTRINSIC_TRUNC\000"
1032 /* 210 */ "G_TRUNC\000"
1033 /* 218 */ "G_BUILD_VECTOR_TRUNC\000"
1034 /* 239 */ "G_DYN_STACKALLOC\000"
1035 /* 256 */ "ADJDYNALLOC\000"
1036 /* 268 */ "POPC\000"
1037 /* 273 */ "G_FMAD\000"
1038 /* 280 */ "G_FPEXTLOAD\000"
1039 /* 292 */ "G_INDEXED_SEXTLOAD\000"
1040 /* 311 */ "G_SEXTLOAD\000"
1041 /* 322 */ "G_INDEXED_ZEXTLOAD\000"
1042 /* 341 */ "G_ZEXTLOAD\000"
1043 /* 352 */ "G_INDEXED_LOAD\000"
1044 /* 367 */ "G_LOAD\000"
1045 /* 374 */ "G_VECREDUCE_FADD\000"
1046 /* 391 */ "G_FADD\000"
1047 /* 398 */ "G_VECREDUCE_SEQ_FADD\000"
1048 /* 419 */ "G_STRICT_FADD\000"
1049 /* 433 */ "G_ATOMICRMW_FADD\000"
1050 /* 450 */ "G_VECREDUCE_ADD\000"
1051 /* 466 */ "G_ADD\000"
1052 /* 472 */ "G_PTR_ADD\000"
1053 /* 482 */ "G_ATOMICRMW_ADD\000"
1054 /* 498 */ "G_ATOMICRMW_NAND\000"
1055 /* 515 */ "G_VECREDUCE_AND\000"
1056 /* 531 */ "G_AND\000"
1057 /* 537 */ "G_ATOMICRMW_AND\000"
1058 /* 553 */ "LIFETIME_END\000"
1059 /* 566 */ "G_BRCOND\000"
1060 /* 575 */ "G_ATOMICRMW_USUB_COND\000"
1061 /* 597 */ "G_LLROUND\000"
1062 /* 607 */ "G_LROUND\000"
1063 /* 616 */ "G_INTRINSIC_ROUND\000"
1064 /* 634 */ "G_INTRINSIC_FPTRUNC_ROUND\000"
1065 /* 660 */ "LOAD_STACK_GUARD\000"
1066 /* 677 */ "PSEUDO_PROBE\000"
1067 /* 690 */ "G_SSUBE\000"
1068 /* 698 */ "G_USUBE\000"
1069 /* 706 */ "G_FENCE\000"
1070 /* 714 */ "ARITH_FENCE\000"
1071 /* 726 */ "REG_SEQUENCE\000"
1072 /* 739 */ "G_SADDE\000"
1073 /* 747 */ "G_UADDE\000"
1074 /* 755 */ "G_GET_FPMODE\000"
1075 /* 768 */ "G_RESET_FPMODE\000"
1076 /* 783 */ "G_SET_FPMODE\000"
1077 /* 796 */ "G_FMINNUM_IEEE\000"
1078 /* 811 */ "G_FMAXNUM_IEEE\000"
1079 /* 826 */ "G_VSCALE\000"
1080 /* 835 */ "G_JUMP_TABLE\000"
1081 /* 848 */ "BUNDLE\000"
1082 /* 855 */ "G_MEMSET_INLINE\000"
1083 /* 871 */ "G_MEMCPY_INLINE\000"
1084 /* 887 */ "RELOC_NONE\000"
1085 /* 898 */ "LOCAL_ESCAPE\000"
1086 /* 911 */ "G_FPTRUNCSTORE\000"
1087 /* 926 */ "G_STACKRESTORE\000"
1088 /* 941 */ "G_INDEXED_STORE\000"
1089 /* 957 */ "G_STORE\000"
1090 /* 965 */ "G_BITREVERSE\000"
1091 /* 978 */ "FAKE_USE\000"
1092 /* 987 */ "DBG_VALUE\000"
1093 /* 997 */ "G_GLOBAL_VALUE\000"
1094 /* 1012 */ "G_PTRAUTH_GLOBAL_VALUE\000"
1095 /* 1035 */ "CONVERGENCECTRL_GLUE\000"
1096 /* 1056 */ "G_STACKSAVE\000"
1097 /* 1068 */ "G_MEMMOVE\000"
1098 /* 1078 */ "G_FREEZE\000"
1099 /* 1087 */ "G_FCANONICALIZE\000"
1100 /* 1103 */ "G_FMODF\000"
1101 /* 1111 */ "INIT_UNDEF\000"
1102 /* 1122 */ "G_IMPLICIT_DEF\000"
1103 /* 1137 */ "DBG_INSTR_REF\000"
1104 /* 1151 */ "G_FNEG\000"
1105 /* 1158 */ "EXTRACT_SUBREG\000"
1106 /* 1173 */ "INSERT_SUBREG\000"
1107 /* 1187 */ "G_SEXT_INREG\000"
1108 /* 1200 */ "SUBREG_TO_REG\000"
1109 /* 1214 */ "G_ATOMIC_CMPXCHG\000"
1110 /* 1231 */ "G_ATOMICRMW_XCHG\000"
1111 /* 1248 */ "G_GET_ROUNDING\000"
1112 /* 1263 */ "G_SET_ROUNDING\000"
1113 /* 1278 */ "G_FLOG\000"
1114 /* 1285 */ "G_VAARG\000"
1115 /* 1293 */ "PREALLOCATED_ARG\000"
1116 /* 1310 */ "G_PREFETCH\000"
1117 /* 1321 */ "G_CLMULH\000"
1118 /* 1330 */ "G_SMULH\000"
1119 /* 1338 */ "G_UMULH\000"
1120 /* 1346 */ "G_FTANH\000"
1121 /* 1354 */ "G_FSINH\000"
1122 /* 1362 */ "G_FCOSH\000"
1123 /* 1370 */ "DBG_PHI\000"
1124 /* 1378 */ "MOVHI\000"
1125 /* 1384 */ "SFSUB_F_RI_HI\000"
1126 /* 1398 */ "SUBB_I_HI\000"
1127 /* 1408 */ "SUB_I_HI\000"
1128 /* 1417 */ "ADDC_I_HI\000"
1129 /* 1427 */ "ADD_I_HI\000"
1130 /* 1436 */ "AND_I_HI\000"
1131 /* 1445 */ "SUBB_F_I_HI\000"
1132 /* 1457 */ "SUB_F_I_HI\000"
1133 /* 1468 */ "ADDC_F_I_HI\000"
1134 /* 1480 */ "ADD_F_I_HI\000"
1135 /* 1491 */ "AND_F_I_HI\000"
1136 /* 1502 */ "XOR_F_I_HI\000"
1137 /* 1513 */ "XOR_I_HI\000"
1138 /* 1522 */ "SLI\000"
1139 /* 1526 */ "STB_RI\000"
1140 /* 1533 */ "STH_RI\000"
1141 /* 1540 */ "LDW_RI\000"
1142 /* 1547 */ "SW_RI\000"
1143 /* 1553 */ "LDBs_RI\000"
1144 /* 1561 */ "LDHs_RI\000"
1145 /* 1569 */ "LDBz_RI\000"
1146 /* 1577 */ "LDHz_RI\000"
1147 /* 1585 */ "G_FPTOSI\000"
1148 /* 1594 */ "G_FPTOUI\000"
1149 /* 1603 */ "G_FPOWI\000"
1150 /* 1611 */ "SA_I\000"
1151 /* 1616 */ "SA_F_I\000"
1152 /* 1623 */ "SL_F_I\000"
1153 /* 1630 */ "SL_I\000"
1154 /* 1635 */ "COPY_LANEMASK\000"
1155 /* 1649 */ "G_PTRMASK\000"
1156 /* 1659 */ "GC_LABEL\000"
1157 /* 1668 */ "DBG_LABEL\000"
1158 /* 1678 */ "EH_LABEL\000"
1159 /* 1687 */ "ANNOTATION_LABEL\000"
1160 /* 1704 */ "ICALL_BRANCH_FUNNEL\000"
1161 /* 1724 */ "G_FSHL\000"
1162 /* 1731 */ "G_SHL\000"
1163 /* 1737 */ "G_FCEIL\000"
1164 /* 1745 */ "G_SAVGCEIL\000"
1165 /* 1756 */ "G_UAVGCEIL\000"
1166 /* 1767 */ "PATCHABLE_TAIL_CALL\000"
1167 /* 1787 */ "PATCHABLE_TYPED_EVENT_CALL\000"
1168 /* 1814 */ "PATCHABLE_EVENT_CALL\000"
1169 /* 1835 */ "FENTRY_CALL\000"
1170 /* 1847 */ "KILL\000"
1171 /* 1852 */ "G_CONSTANT_POOL\000"
1172 /* 1868 */ "G_ROTL\000"
1173 /* 1875 */ "G_VECREDUCE_FMUL\000"
1174 /* 1892 */ "G_FMUL\000"
1175 /* 1899 */ "G_VECREDUCE_SEQ_FMUL\000"
1176 /* 1920 */ "G_STRICT_FMUL\000"
1177 /* 1934 */ "G_CLMUL\000"
1178 /* 1942 */ "G_VECREDUCE_MUL\000"
1179 /* 1958 */ "G_MUL\000"
1180 /* 1964 */ "G_FREM\000"
1181 /* 1971 */ "G_STRICT_FREM\000"
1182 /* 1985 */ "G_SREM\000"
1183 /* 1992 */ "G_UREM\000"
1184 /* 1999 */ "G_SDIVREM\000"
1185 /* 2009 */ "G_UDIVREM\000"
1186 /* 2019 */ "INLINEASM\000"
1187 /* 2029 */ "G_VECREDUCE_FMINIMUM\000"
1188 /* 2050 */ "G_FMINIMUM\000"
1189 /* 2061 */ "G_ATOMICRMW_FMINIMUM\000"
1190 /* 2082 */ "G_VECREDUCE_FMAXIMUM\000"
1191 /* 2103 */ "G_FMAXIMUM\000"
1192 /* 2114 */ "G_ATOMICRMW_FMAXIMUM\000"
1193 /* 2135 */ "G_VECREDUCE_FMINIMUMNUM\000"
1194 /* 2159 */ "G_FMINIMUMNUM\000"
1195 /* 2173 */ "G_ATOMICRMW_FMINIMUMNUM\000"
1196 /* 2197 */ "G_VECREDUCE_FMAXIMUMNUM\000"
1197 /* 2221 */ "G_FMAXIMUMNUM\000"
1198 /* 2235 */ "G_ATOMICRMW_FMAXIMUMNUM\000"
1199 /* 2259 */ "G_FMINNUM\000"
1200 /* 2269 */ "G_FMAXNUM\000"
1201 /* 2279 */ "G_FATAN\000"
1202 /* 2287 */ "G_FTAN\000"
1203 /* 2294 */ "G_INTRINSIC_ROUNDEVEN\000"
1204 /* 2316 */ "G_ASSERT_ALIGN\000"
1205 /* 2331 */ "G_FCOPYSIGN\000"
1206 /* 2343 */ "G_VECREDUCE_FMIN\000"
1207 /* 2360 */ "G_ATOMICRMW_FMIN\000"
1208 /* 2377 */ "G_VECREDUCE_SMIN\000"
1209 /* 2394 */ "G_SMIN\000"
1210 /* 2401 */ "G_VECREDUCE_UMIN\000"
1211 /* 2418 */ "G_UMIN\000"
1212 /* 2425 */ "G_ATOMICRMW_UMIN\000"
1213 /* 2442 */ "G_ATOMICRMW_MIN\000"
1214 /* 2458 */ "G_FASIN\000"
1215 /* 2466 */ "G_FSIN\000"
1216 /* 2473 */ "CFI_INSTRUCTION\000"
1217 /* 2489 */ "G_CTLZ_ZERO_POISON\000"
1218 /* 2508 */ "G_CTTZ_ZERO_POISON\000"
1219 /* 2527 */ "ADJCALLSTACKDOWN\000"
1220 /* 2544 */ "G_SSUBO\000"
1221 /* 2552 */ "G_USUBO\000"
1222 /* 2560 */ "G_SADDO\000"
1223 /* 2568 */ "G_UADDO\000"
1224 /* 2576 */ "JUMP_TABLE_DEBUG_INFO\000"
1225 /* 2598 */ "G_SMULO\000"
1226 /* 2606 */ "G_UMULO\000"
1227 /* 2614 */ "SFSUB_F_RI_LO\000"
1228 /* 2628 */ "SUBB_I_LO\000"
1229 /* 2638 */ "SUB_I_LO\000"
1230 /* 2647 */ "ADDC_I_LO\000"
1231 /* 2657 */ "ADD_I_LO\000"
1232 /* 2666 */ "AND_I_LO\000"
1233 /* 2675 */ "SUBB_F_I_LO\000"
1234 /* 2687 */ "SUB_F_I_LO\000"
1235 /* 2698 */ "ADDC_F_I_LO\000"
1236 /* 2710 */ "ADD_F_I_LO\000"
1237 /* 2721 */ "AND_F_I_LO\000"
1238 /* 2732 */ "XOR_F_I_LO\000"
1239 /* 2743 */ "XOR_I_LO\000"
1240 /* 2752 */ "G_BZERO\000"
1241 /* 2760 */ "STACKMAP\000"
1242 /* 2769 */ "G_DEBUGTRAP\000"
1243 /* 2781 */ "G_UBSANTRAP\000"
1244 /* 2793 */ "G_TRAP\000"
1245 /* 2800 */ "G_ATOMICRMW_UDEC_WRAP\000"
1246 /* 2822 */ "G_ATOMICRMW_UINC_WRAP\000"
1247 /* 2844 */ "G_BSWAP\000"
1248 /* 2852 */ "G_SITOFP\000"
1249 /* 2861 */ "G_UITOFP\000"
1250 /* 2870 */ "G_FCMP\000"
1251 /* 2877 */ "G_STRICT_FCMP\000"
1252 /* 2891 */ "G_ICMP\000"
1253 /* 2898 */ "G_SCMP\000"
1254 /* 2905 */ "G_UCMP\000"
1255 /* 2912 */ "NOP\000"
1256 /* 2916 */ "CONVERGENCECTRL_LOOP\000"
1257 /* 2937 */ "G_CTPOP\000"
1258 /* 2945 */ "PATCHABLE_OP\000"
1259 /* 2958 */ "FAULTING_OP\000"
1260 /* 2970 */ "ADJCALLSTACKUP\000"
1261 /* 2985 */ "PREALLOCATED_SETUP\000"
1262 /* 3004 */ "G_FLDEXP\000"
1263 /* 3013 */ "G_STRICT_FLDEXP\000"
1264 /* 3029 */ "G_FEXP\000"
1265 /* 3036 */ "G_FFREXP\000"
1266 /* 3045 */ "G_BR\000"
1267 /* 3050 */ "INLINEASM_BR\000"
1268 /* 3063 */ "LDADDR\000"
1269 /* 3070 */ "STADDR\000"
1270 /* 3077 */ "G_BLOCK_ADDR\000"
1271 /* 3090 */ "MEMBARRIER\000"
1272 /* 3101 */ "G_CONSTANT_FOLD_BARRIER\000"
1273 /* 3125 */ "PATCHABLE_FUNCTION_ENTER\000"
1274 /* 3150 */ "G_READCYCLECOUNTER\000"
1275 /* 3169 */ "G_READSTEADYCOUNTER\000"
1276 /* 3189 */ "G_READ_REGISTER\000"
1277 /* 3205 */ "G_WRITE_REGISTER\000"
1278 /* 3222 */ "G_ASHR\000"
1279 /* 3229 */ "G_FSHR\000"
1280 /* 3236 */ "G_LSHR\000"
1281 /* 3243 */ "JR\000"
1282 /* 3246 */ "CALLR\000"
1283 /* 3252 */ "CONVERGENCECTRL_ANCHOR\000"
1284 /* 3275 */ "G_FFLOOR\000"
1285 /* 3284 */ "G_SAVGFLOOR\000"
1286 /* 3296 */ "G_UAVGFLOOR\000"
1287 /* 3308 */ "G_EXTRACT_SUBVECTOR\000"
1288 /* 3328 */ "G_INSERT_SUBVECTOR\000"
1289 /* 3347 */ "G_BUILD_VECTOR\000"
1290 /* 3362 */ "G_SHUFFLE_VECTOR\000"
1291 /* 3379 */ "G_STEP_VECTOR\000"
1292 /* 3393 */ "G_SPLAT_VECTOR\000"
1293 /* 3408 */ "G_VECREDUCE_XOR\000"
1294 /* 3424 */ "G_XOR\000"
1295 /* 3430 */ "G_ATOMICRMW_XOR\000"
1296 /* 3446 */ "G_VECREDUCE_OR\000"
1297 /* 3461 */ "G_OR\000"
1298 /* 3466 */ "G_ATOMICRMW_OR\000"
1299 /* 3481 */ "BRR\000"
1300 /* 3485 */ "STB_RR\000"
1301 /* 3492 */ "SFSUB_F_RR\000"
1302 /* 3503 */ "STH_RR\000"
1303 /* 3510 */ "LDW_RR\000"
1304 /* 3517 */ "SW_RR\000"
1305 /* 3523 */ "LDBs_RR\000"
1306 /* 3531 */ "LDHs_RR\000"
1307 /* 3539 */ "LDBz_RR\000"
1308 /* 3547 */ "LDHz_RR\000"
1309 /* 3555 */ "LDWz_RR\000"
1310 /* 3563 */ "G_ROTR\000"
1311 /* 3570 */ "G_INTTOPTR\000"
1312 /* 3581 */ "SRA_R\000"
1313 /* 3587 */ "SUBB_R\000"
1314 /* 3594 */ "SUB_R\000"
1315 /* 3600 */ "ADDC_R\000"
1316 /* 3607 */ "ADD_R\000"
1317 /* 3613 */ "AND_R\000"
1318 /* 3619 */ "SRA_F_R\000"
1319 /* 3627 */ "SUBB_F_R\000"
1320 /* 3636 */ "SUB_F_R\000"
1321 /* 3644 */ "ADDC_F_R\000"
1322 /* 3653 */ "ADD_F_R\000"
1323 /* 3661 */ "AND_F_R\000"
1324 /* 3669 */ "SHL_F_R\000"
1325 /* 3677 */ "SRL_F_R\000"
1326 /* 3685 */ "XOR_F_R\000"
1327 /* 3693 */ "SHL_R\000"
1328 /* 3699 */ "SRL_R\000"
1329 /* 3705 */ "XOR_R\000"
1330 /* 3711 */ "G_FABS\000"
1331 /* 3718 */ "G_ABS\000"
1332 /* 3724 */ "G_ABDS\000"
1333 /* 3731 */ "G_UNMERGE_VALUES\000"
1334 /* 3748 */ "G_MERGE_VALUES\000"
1335 /* 3763 */ "G_CTLS\000"
1336 /* 3770 */ "G_FACOS\000"
1337 /* 3778 */ "G_FCOS\000"
1338 /* 3785 */ "G_FSINCOS\000"
1339 /* 3795 */ "G_STRICT_FCMPS\000"
1340 /* 3810 */ "G_CONCAT_VECTORS\000"
1341 /* 3827 */ "COPY_TO_REGCLASS\000"
1342 /* 3844 */ "G_IS_FPCLASS\000"
1343 /* 3857 */ "G_ATOMIC_CMPXCHG_WITH_SUCCESS\000"
1344 /* 3887 */ "G_VECTOR_COMPRESS\000"
1345 /* 3905 */ "G_INTRINSIC_W_SIDE_EFFECTS\000"
1346 /* 3932 */ "G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS\000"
1347 /* 3970 */ "G_TRUNC_SSAT_S\000"
1348 /* 3985 */ "G_SSUBSAT\000"
1349 /* 3995 */ "G_USUBSAT\000"
1350 /* 4005 */ "G_SADDSAT\000"
1351 /* 4015 */ "G_UADDSAT\000"
1352 /* 4025 */ "G_SSHLSAT\000"
1353 /* 4035 */ "G_USHLSAT\000"
1354 /* 4045 */ "G_SMULFIXSAT\000"
1355 /* 4058 */ "G_UMULFIXSAT\000"
1356 /* 4071 */ "G_SDIVFIXSAT\000"
1357 /* 4084 */ "G_UDIVFIXSAT\000"
1358 /* 4097 */ "G_ATOMICRMW_USUB_SAT\000"
1359 /* 4118 */ "G_FPTOSI_SAT\000"
1360 /* 4131 */ "G_FPTOUI_SAT\000"
1361 /* 4144 */ "BT\000"
1362 /* 4147 */ "G_EXTRACT\000"
1363 /* 4157 */ "G_SELECT\000"
1364 /* 4166 */ "G_BRINDIRECT\000"
1365 /* 4179 */ "PATCHABLE_RET\000"
1366 /* 4193 */ "G_MEMSET\000"
1367 /* 4202 */ "PATCHABLE_FUNCTION_EXIT\000"
1368 /* 4226 */ "G_BRJT\000"
1369 /* 4233 */ "G_EXTRACT_VECTOR_ELT\000"
1370 /* 4254 */ "G_INSERT_VECTOR_ELT\000"
1371 /* 4274 */ "G_FCONSTANT\000"
1372 /* 4286 */ "G_CONSTANT\000"
1373 /* 4297 */ "G_INTRINSIC_CONVERGENT\000"
1374 /* 4320 */ "STATEPOINT\000"
1375 /* 4331 */ "PATCHPOINT\000"
1376 /* 4342 */ "G_PTRTOINT\000"
1377 /* 4353 */ "G_FRINT\000"
1378 /* 4361 */ "G_INTRINSIC_LLRINT\000"
1379 /* 4380 */ "G_INTRINSIC_LRINT\000"
1380 /* 4398 */ "G_FNEARBYINT\000"
1381 /* 4411 */ "G_VASTART\000"
1382 /* 4421 */ "LIFETIME_START\000"
1383 /* 4436 */ "G_INVOKE_REGION_START\000"
1384 /* 4458 */ "G_INSERT\000"
1385 /* 4467 */ "G_FSQRT\000"
1386 /* 4475 */ "G_STRICT_FSQRT\000"
1387 /* 4490 */ "G_BITCAST\000"
1388 /* 4500 */ "G_ADDRSPACE_CAST\000"
1389 /* 4517 */ "DBG_VALUE_LIST\000"
1390 /* 4532 */ "G_FPEXT\000"
1391 /* 4540 */ "G_SEXT\000"
1392 /* 4547 */ "G_ASSERT_SEXT\000"
1393 /* 4561 */ "G_ANYEXT\000"
1394 /* 4570 */ "G_ZEXT\000"
1395 /* 4577 */ "G_ASSERT_ZEXT\000"
1396 /* 4591 */ "G_ABDU\000"
1397 /* 4598 */ "G_TRUNC_SSAT_U\000"
1398 /* 4613 */ "G_TRUNC_USAT_U\000"
1399 /* 4628 */ "G_FDIV\000"
1400 /* 4635 */ "G_STRICT_FDIV\000"
1401 /* 4649 */ "G_SDIV\000"
1402 /* 4656 */ "G_UDIV\000"
1403 /* 4663 */ "G_GET_FPENV\000"
1404 /* 4675 */ "G_RESET_FPENV\000"
1405 /* 4689 */ "G_SET_FPENV\000"
1406 /* 4701 */ "G_FPOW\000"
1407 /* 4708 */ "G_VECREDUCE_FMAX\000"
1408 /* 4725 */ "G_ATOMICRMW_FMAX\000"
1409 /* 4742 */ "G_VECREDUCE_SMAX\000"
1410 /* 4759 */ "G_SMAX\000"
1411 /* 4766 */ "G_VECREDUCE_UMAX\000"
1412 /* 4783 */ "G_UMAX\000"
1413 /* 4790 */ "G_ATOMICRMW_UMAX\000"
1414 /* 4807 */ "G_ATOMICRMW_MAX\000"
1415 /* 4823 */ "G_FRAME_INDEX\000"
1416 /* 4837 */ "G_SBFX\000"
1417 /* 4844 */ "G_UBFX\000"
1418 /* 4851 */ "G_SMULFIX\000"
1419 /* 4861 */ "G_UMULFIX\000"
1420 /* 4871 */ "G_SDIVFIX\000"
1421 /* 4881 */ "G_UDIVFIX\000"
1422 /* 4891 */ "G_MEMCPY\000"
1423 /* 4900 */ "COPY\000"
1424 /* 4905 */ "CONVERGENCECTRL_ENTRY\000"
1425 /* 4927 */ "LEADZ\000"
1426 /* 4933 */ "TRAILZ\000"
1427 /* 4940 */ "G_CTLZ\000"
1428 /* 4947 */ "G_CTTZ\000"
1429};
1430#ifdef __GNUC__
1431#pragma GCC diagnostic pop
1432#endif
1433
1434extern const unsigned LanaiInstrNameIndices[] = {
1435 1374U, 2019U, 3050U, 2473U, 1678U, 1659U, 1687U, 1847U,
1436 1158U, 1173U, 1124U, 1111U, 1200U, 3827U, 987U, 4517U,
1437 1137U, 1370U, 1668U, 726U, 4900U, 1635U, 848U, 4421U,
1438 553U, 677U, 714U, 2760U, 1835U, 4331U, 660U, 2985U,
1439 1293U, 4320U, 898U, 2958U, 2945U, 3125U, 4179U, 4202U,
1440 1767U, 1814U, 1787U, 1704U, 978U, 3090U, 2576U, 887U,
1441 4905U, 3252U, 2916U, 1035U, 4547U, 4577U, 2316U, 466U,
1442 130U, 1958U, 4649U, 4656U, 1985U, 1992U, 1999U, 2009U,
1443 531U, 3461U, 3424U, 3724U, 4591U, 3296U, 1756U, 3284U,
1444 1745U, 1122U, 1372U, 4823U, 997U, 1012U, 1852U, 4147U,
1445 3731U, 4458U, 3748U, 3347U, 218U, 3810U, 4342U, 3570U,
1446 4490U, 1078U, 3101U, 634U, 192U, 616U, 4380U, 4361U,
1447 2294U, 3150U, 3169U, 367U, 311U, 341U, 280U, 352U,
1448 292U, 322U, 957U, 911U, 941U, 3857U, 1214U, 1231U,
1449 482U, 136U, 537U, 498U, 3466U, 3430U, 4807U, 2442U,
1450 4790U, 2425U, 433U, 113U, 4725U, 2360U, 2114U, 2061U,
1451 2235U, 2173U, 2822U, 2800U, 575U, 4097U, 706U, 1310U,
1452 566U, 4166U, 4436U, 170U, 3905U, 4297U, 3932U, 4561U,
1453 210U, 3970U, 4598U, 4613U, 4286U, 4274U, 4411U, 1285U,
1454 4540U, 1187U, 4570U, 1731U, 3236U, 3222U, 1724U, 3229U,
1455 3563U, 1868U, 2891U, 2870U, 2898U, 2905U, 4157U, 2568U,
1456 747U, 2552U, 698U, 2560U, 739U, 2544U, 690U, 2606U,
1457 2598U, 1338U, 1330U, 4015U, 4005U, 3995U, 3985U, 4035U,
1458 4025U, 4851U, 4861U, 4045U, 4058U, 4871U, 4881U, 4071U,
1459 4084U, 391U, 92U, 1892U, 73U, 273U, 4628U, 1964U,
1460 1103U, 4701U, 1603U, 3029U, 45U, 9U, 1278U, 28U,
1461 0U, 3004U, 3036U, 1151U, 4532U, 182U, 1585U, 1594U,
1462 2852U, 2861U, 4118U, 4131U, 3711U, 2331U, 3844U, 1087U,
1463 2259U, 2269U, 796U, 811U, 2050U, 2103U, 2159U, 2221U,
1464 4663U, 4689U, 4675U, 755U, 783U, 768U, 1248U, 1263U,
1465 472U, 1649U, 2394U, 4759U, 2418U, 4783U, 3718U, 607U,
1466 597U, 3045U, 4226U, 826U, 3328U, 3308U, 4254U, 4233U,
1467 3362U, 3393U, 3379U, 3887U, 4947U, 2508U, 4940U, 2489U,
1468 3763U, 2937U, 2844U, 965U, 1934U, 1321U, 1737U, 3778U,
1469 2466U, 3785U, 2287U, 3770U, 2458U, 2279U, 36U, 1362U,
1470 1354U, 1346U, 4467U, 3275U, 4353U, 4398U, 4500U, 3077U,
1471 835U, 239U, 1056U, 926U, 419U, 99U, 1920U, 4635U,
1472 1971U, 79U, 4475U, 3013U, 2877U, 3795U, 3189U, 3205U,
1473 4891U, 871U, 1068U, 4193U, 2752U, 855U, 2793U, 2769U,
1474 2781U, 398U, 1899U, 374U, 1875U, 4708U, 2343U, 2082U,
1475 2029U, 2197U, 2135U, 450U, 1942U, 515U, 3446U, 3408U,
1476 4742U, 2377U, 4766U, 2401U, 4837U, 4844U, 2527U, 2970U,
1477 256U, 1782U, 3246U, 1468U, 2698U, 3644U, 1417U, 2647U,
1478 3600U, 1480U, 2710U, 3653U, 1427U, 2657U, 3607U, 1491U,
1479 2721U, 3661U, 1436U, 2666U, 3613U, 152U, 161U, 63U,
1480 3481U, 4144U, 3243U, 3063U, 1553U, 3523U, 1569U, 3539U,
1481 1561U, 3531U, 1577U, 3547U, 1540U, 3510U, 3555U, 4927U,
1482 18U, 23U, 31U, 53U, 58U, 1378U, 2912U, 1503U,
1483 2733U, 3686U, 1514U, 2744U, 3706U, 268U, 4189U, 1616U,
1484 1611U, 157U, 4159U, 1384U, 2614U, 3492U, 3669U, 3693U,
1485 1522U, 1623U, 1630U, 3619U, 3581U, 3677U, 3699U, 3070U,
1486 1526U, 3485U, 1533U, 3503U, 1445U, 2675U, 3627U, 1398U,
1487 2628U, 3587U, 1457U, 2687U, 3636U, 1408U, 2638U, 3594U,
1488 1547U, 3517U, 4933U, 1502U, 2732U, 3685U, 1513U, 2743U,
1489 3705U,
1490};
1491
1492static inline void InitLanaiMCInstrInfo(MCInstrInfo *II) {
1493 II->InitMCInstrInfo(LanaiDescs.Insts, LanaiInstrNameIndices, LanaiInstrNameData, nullptr, nullptr, 433, nullptr, 0);
1494}
1495
1496
1497} // namespace llvm
1498
1499#endif // GET_INSTRINFO_MC_DESC
1500
1501#ifdef GET_INSTRINFO_HEADER
1502#undef GET_INSTRINFO_HEADER
1503
1504namespace llvm {
1505
1506struct LanaiGenInstrInfo : public TargetInstrInfo {
1507 explicit LanaiGenInstrInfo(const TargetSubtargetInfo &STI, const TargetRegisterInfo &TRI, unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u, unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u);
1508 ~LanaiGenInstrInfo() override = default;
1509};
1510
1511} // namespace llvm
1512
1513namespace llvm::Lanai {
1514
1515constexpr unsigned SUBOP_MEMri_base = 0;
1516constexpr unsigned SUBOP_MEMri_offset = 1;
1517constexpr unsigned SUBOP_MEMri_Opcode = 2;
1518constexpr unsigned SUBOP_MEMrr_Op1 = 0;
1519constexpr unsigned SUBOP_MEMrr_Op2 = 1;
1520constexpr unsigned SUBOP_MEMrr_Opcode = 2;
1521constexpr unsigned SUBOP_MEMspls_base = 0;
1522constexpr unsigned SUBOP_MEMspls_offset = 1;
1523constexpr unsigned SUBOP_MEMspls_Opcode = 2;
1524
1525} // namespace llvm::Lanai
1526
1527#endif // GET_INSTRINFO_HEADER
1528
1529#ifdef GET_INSTRINFO_HELPER_DECLS
1530#undef GET_INSTRINFO_HELPER_DECLS
1531
1532
1533#endif // GET_INSTRINFO_HELPER_DECLS
1534
1535#ifdef GET_INSTRINFO_HELPERS
1536#undef GET_INSTRINFO_HELPERS
1537
1538
1539#endif // GET_INSTRINFO_HELPERS
1540
1541#ifdef GET_INSTRINFO_CTOR_DTOR
1542#undef GET_INSTRINFO_CTOR_DTOR
1543
1544namespace llvm {
1545
1546extern const LanaiInstrTable LanaiDescs;
1547extern const unsigned LanaiInstrNameIndices[];
1548extern const char LanaiInstrNameData[];
1549LanaiGenInstrInfo::LanaiGenInstrInfo(const TargetSubtargetInfo &STI, const TargetRegisterInfo &TRI, unsigned CFSetupOpcode, unsigned CFDestroyOpcode, unsigned CatchRetOpcode, unsigned ReturnOpcode)
1550 : TargetInstrInfo(TRI, CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) {
1551 InitMCInstrInfo(LanaiDescs.Insts, LanaiInstrNameIndices, LanaiInstrNameData, nullptr, nullptr, 433);
1552}
1553
1554} // namespace llvm
1555
1556#endif // GET_INSTRINFO_CTOR_DTOR
1557
1558#ifdef GET_INSTRINFO_MC_HELPER_DECLS
1559#undef GET_INSTRINFO_MC_HELPER_DECLS
1560
1561namespace llvm {
1562
1563class MCInst;
1564class FeatureBitset;
1565
1566namespace Lanai_MC {
1567
1568void verifyInstructionPredicates(unsigned Opcode, const FeatureBitset &Features);
1569
1570} // namespace Lanai_MC
1571
1572} // namespace llvm
1573
1574#endif // GET_INSTRINFO_MC_HELPER_DECLS
1575
1576#ifdef GET_INSTRINFO_MC_HELPERS
1577#undef GET_INSTRINFO_MC_HELPERS
1578
1579namespace llvm::Lanai_MC {
1580
1581
1582} // namespace llvm::Lanai_MC
1583
1584#endif // GET_INSTRINFO_MC_HELPERS
1585
1586#if (defined(ENABLE_INSTR_PREDICATE_VERIFIER) && !defined(NDEBUG)) ||\
1587 defined(GET_AVAILABLE_OPCODE_CHECKER)
1588#define GET_COMPUTE_FEATURES
1589#endif
1590#ifdef GET_COMPUTE_FEATURES
1591#undef GET_COMPUTE_FEATURES
1592
1593namespace llvm::Lanai_MC {
1594
1595// Bits for subtarget features that participate in instruction matching.
1596enum SubtargetFeatureBits : uint8_t {
1597};
1598
1599inline FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) {
1600 FeatureBitset Features;
1601 return Features;
1602}
1603
1604inline FeatureBitset computeRequiredFeatures(unsigned Opcode) {
1605 enum : uint8_t {
1606 CEFBS_None,
1607 };
1608
1609 static constexpr FeatureBitset FeatureBitsets[] = {
1610 {}, // CEFBS_None
1611 };
1612 static constexpr uint8_t RequiredFeaturesRefs[] = {
1613 CEFBS_None, // PHI
1614 CEFBS_None, // INLINEASM
1615 CEFBS_None, // INLINEASM_BR
1616 CEFBS_None, // CFI_INSTRUCTION
1617 CEFBS_None, // EH_LABEL
1618 CEFBS_None, // GC_LABEL
1619 CEFBS_None, // ANNOTATION_LABEL
1620 CEFBS_None, // KILL
1621 CEFBS_None, // EXTRACT_SUBREG
1622 CEFBS_None, // INSERT_SUBREG
1623 CEFBS_None, // IMPLICIT_DEF
1624 CEFBS_None, // INIT_UNDEF
1625 CEFBS_None, // SUBREG_TO_REG
1626 CEFBS_None, // COPY_TO_REGCLASS
1627 CEFBS_None, // DBG_VALUE
1628 CEFBS_None, // DBG_VALUE_LIST
1629 CEFBS_None, // DBG_INSTR_REF
1630 CEFBS_None, // DBG_PHI
1631 CEFBS_None, // DBG_LABEL
1632 CEFBS_None, // REG_SEQUENCE
1633 CEFBS_None, // COPY
1634 CEFBS_None, // COPY_LANEMASK
1635 CEFBS_None, // BUNDLE
1636 CEFBS_None, // LIFETIME_START
1637 CEFBS_None, // LIFETIME_END
1638 CEFBS_None, // PSEUDO_PROBE
1639 CEFBS_None, // ARITH_FENCE
1640 CEFBS_None, // STACKMAP
1641 CEFBS_None, // FENTRY_CALL
1642 CEFBS_None, // PATCHPOINT
1643 CEFBS_None, // LOAD_STACK_GUARD
1644 CEFBS_None, // PREALLOCATED_SETUP
1645 CEFBS_None, // PREALLOCATED_ARG
1646 CEFBS_None, // STATEPOINT
1647 CEFBS_None, // LOCAL_ESCAPE
1648 CEFBS_None, // FAULTING_OP
1649 CEFBS_None, // PATCHABLE_OP
1650 CEFBS_None, // PATCHABLE_FUNCTION_ENTER
1651 CEFBS_None, // PATCHABLE_RET
1652 CEFBS_None, // PATCHABLE_FUNCTION_EXIT
1653 CEFBS_None, // PATCHABLE_TAIL_CALL
1654 CEFBS_None, // PATCHABLE_EVENT_CALL
1655 CEFBS_None, // PATCHABLE_TYPED_EVENT_CALL
1656 CEFBS_None, // ICALL_BRANCH_FUNNEL
1657 CEFBS_None, // FAKE_USE
1658 CEFBS_None, // MEMBARRIER
1659 CEFBS_None, // JUMP_TABLE_DEBUG_INFO
1660 CEFBS_None, // RELOC_NONE
1661 CEFBS_None, // CONVERGENCECTRL_ENTRY
1662 CEFBS_None, // CONVERGENCECTRL_ANCHOR
1663 CEFBS_None, // CONVERGENCECTRL_LOOP
1664 CEFBS_None, // CONVERGENCECTRL_GLUE
1665 CEFBS_None, // G_ASSERT_SEXT
1666 CEFBS_None, // G_ASSERT_ZEXT
1667 CEFBS_None, // G_ASSERT_ALIGN
1668 CEFBS_None, // G_ADD
1669 CEFBS_None, // G_SUB
1670 CEFBS_None, // G_MUL
1671 CEFBS_None, // G_SDIV
1672 CEFBS_None, // G_UDIV
1673 CEFBS_None, // G_SREM
1674 CEFBS_None, // G_UREM
1675 CEFBS_None, // G_SDIVREM
1676 CEFBS_None, // G_UDIVREM
1677 CEFBS_None, // G_AND
1678 CEFBS_None, // G_OR
1679 CEFBS_None, // G_XOR
1680 CEFBS_None, // G_ABDS
1681 CEFBS_None, // G_ABDU
1682 CEFBS_None, // G_UAVGFLOOR
1683 CEFBS_None, // G_UAVGCEIL
1684 CEFBS_None, // G_SAVGFLOOR
1685 CEFBS_None, // G_SAVGCEIL
1686 CEFBS_None, // G_IMPLICIT_DEF
1687 CEFBS_None, // G_PHI
1688 CEFBS_None, // G_FRAME_INDEX
1689 CEFBS_None, // G_GLOBAL_VALUE
1690 CEFBS_None, // G_PTRAUTH_GLOBAL_VALUE
1691 CEFBS_None, // G_CONSTANT_POOL
1692 CEFBS_None, // G_EXTRACT
1693 CEFBS_None, // G_UNMERGE_VALUES
1694 CEFBS_None, // G_INSERT
1695 CEFBS_None, // G_MERGE_VALUES
1696 CEFBS_None, // G_BUILD_VECTOR
1697 CEFBS_None, // G_BUILD_VECTOR_TRUNC
1698 CEFBS_None, // G_CONCAT_VECTORS
1699 CEFBS_None, // G_PTRTOINT
1700 CEFBS_None, // G_INTTOPTR
1701 CEFBS_None, // G_BITCAST
1702 CEFBS_None, // G_FREEZE
1703 CEFBS_None, // G_CONSTANT_FOLD_BARRIER
1704 CEFBS_None, // G_INTRINSIC_FPTRUNC_ROUND
1705 CEFBS_None, // G_INTRINSIC_TRUNC
1706 CEFBS_None, // G_INTRINSIC_ROUND
1707 CEFBS_None, // G_INTRINSIC_LRINT
1708 CEFBS_None, // G_INTRINSIC_LLRINT
1709 CEFBS_None, // G_INTRINSIC_ROUNDEVEN
1710 CEFBS_None, // G_READCYCLECOUNTER
1711 CEFBS_None, // G_READSTEADYCOUNTER
1712 CEFBS_None, // G_LOAD
1713 CEFBS_None, // G_SEXTLOAD
1714 CEFBS_None, // G_ZEXTLOAD
1715 CEFBS_None, // G_FPEXTLOAD
1716 CEFBS_None, // G_INDEXED_LOAD
1717 CEFBS_None, // G_INDEXED_SEXTLOAD
1718 CEFBS_None, // G_INDEXED_ZEXTLOAD
1719 CEFBS_None, // G_STORE
1720 CEFBS_None, // G_FPTRUNCSTORE
1721 CEFBS_None, // G_INDEXED_STORE
1722 CEFBS_None, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
1723 CEFBS_None, // G_ATOMIC_CMPXCHG
1724 CEFBS_None, // G_ATOMICRMW_XCHG
1725 CEFBS_None, // G_ATOMICRMW_ADD
1726 CEFBS_None, // G_ATOMICRMW_SUB
1727 CEFBS_None, // G_ATOMICRMW_AND
1728 CEFBS_None, // G_ATOMICRMW_NAND
1729 CEFBS_None, // G_ATOMICRMW_OR
1730 CEFBS_None, // G_ATOMICRMW_XOR
1731 CEFBS_None, // G_ATOMICRMW_MAX
1732 CEFBS_None, // G_ATOMICRMW_MIN
1733 CEFBS_None, // G_ATOMICRMW_UMAX
1734 CEFBS_None, // G_ATOMICRMW_UMIN
1735 CEFBS_None, // G_ATOMICRMW_FADD
1736 CEFBS_None, // G_ATOMICRMW_FSUB
1737 CEFBS_None, // G_ATOMICRMW_FMAX
1738 CEFBS_None, // G_ATOMICRMW_FMIN
1739 CEFBS_None, // G_ATOMICRMW_FMAXIMUM
1740 CEFBS_None, // G_ATOMICRMW_FMINIMUM
1741 CEFBS_None, // G_ATOMICRMW_FMAXIMUMNUM
1742 CEFBS_None, // G_ATOMICRMW_FMINIMUMNUM
1743 CEFBS_None, // G_ATOMICRMW_UINC_WRAP
1744 CEFBS_None, // G_ATOMICRMW_UDEC_WRAP
1745 CEFBS_None, // G_ATOMICRMW_USUB_COND
1746 CEFBS_None, // G_ATOMICRMW_USUB_SAT
1747 CEFBS_None, // G_FENCE
1748 CEFBS_None, // G_PREFETCH
1749 CEFBS_None, // G_BRCOND
1750 CEFBS_None, // G_BRINDIRECT
1751 CEFBS_None, // G_INVOKE_REGION_START
1752 CEFBS_None, // G_INTRINSIC
1753 CEFBS_None, // G_INTRINSIC_W_SIDE_EFFECTS
1754 CEFBS_None, // G_INTRINSIC_CONVERGENT
1755 CEFBS_None, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
1756 CEFBS_None, // G_ANYEXT
1757 CEFBS_None, // G_TRUNC
1758 CEFBS_None, // G_TRUNC_SSAT_S
1759 CEFBS_None, // G_TRUNC_SSAT_U
1760 CEFBS_None, // G_TRUNC_USAT_U
1761 CEFBS_None, // G_CONSTANT
1762 CEFBS_None, // G_FCONSTANT
1763 CEFBS_None, // G_VASTART
1764 CEFBS_None, // G_VAARG
1765 CEFBS_None, // G_SEXT
1766 CEFBS_None, // G_SEXT_INREG
1767 CEFBS_None, // G_ZEXT
1768 CEFBS_None, // G_SHL
1769 CEFBS_None, // G_LSHR
1770 CEFBS_None, // G_ASHR
1771 CEFBS_None, // G_FSHL
1772 CEFBS_None, // G_FSHR
1773 CEFBS_None, // G_ROTR
1774 CEFBS_None, // G_ROTL
1775 CEFBS_None, // G_ICMP
1776 CEFBS_None, // G_FCMP
1777 CEFBS_None, // G_SCMP
1778 CEFBS_None, // G_UCMP
1779 CEFBS_None, // G_SELECT
1780 CEFBS_None, // G_UADDO
1781 CEFBS_None, // G_UADDE
1782 CEFBS_None, // G_USUBO
1783 CEFBS_None, // G_USUBE
1784 CEFBS_None, // G_SADDO
1785 CEFBS_None, // G_SADDE
1786 CEFBS_None, // G_SSUBO
1787 CEFBS_None, // G_SSUBE
1788 CEFBS_None, // G_UMULO
1789 CEFBS_None, // G_SMULO
1790 CEFBS_None, // G_UMULH
1791 CEFBS_None, // G_SMULH
1792 CEFBS_None, // G_UADDSAT
1793 CEFBS_None, // G_SADDSAT
1794 CEFBS_None, // G_USUBSAT
1795 CEFBS_None, // G_SSUBSAT
1796 CEFBS_None, // G_USHLSAT
1797 CEFBS_None, // G_SSHLSAT
1798 CEFBS_None, // G_SMULFIX
1799 CEFBS_None, // G_UMULFIX
1800 CEFBS_None, // G_SMULFIXSAT
1801 CEFBS_None, // G_UMULFIXSAT
1802 CEFBS_None, // G_SDIVFIX
1803 CEFBS_None, // G_UDIVFIX
1804 CEFBS_None, // G_SDIVFIXSAT
1805 CEFBS_None, // G_UDIVFIXSAT
1806 CEFBS_None, // G_FADD
1807 CEFBS_None, // G_FSUB
1808 CEFBS_None, // G_FMUL
1809 CEFBS_None, // G_FMA
1810 CEFBS_None, // G_FMAD
1811 CEFBS_None, // G_FDIV
1812 CEFBS_None, // G_FREM
1813 CEFBS_None, // G_FMODF
1814 CEFBS_None, // G_FPOW
1815 CEFBS_None, // G_FPOWI
1816 CEFBS_None, // G_FEXP
1817 CEFBS_None, // G_FEXP2
1818 CEFBS_None, // G_FEXP10
1819 CEFBS_None, // G_FLOG
1820 CEFBS_None, // G_FLOG2
1821 CEFBS_None, // G_FLOG10
1822 CEFBS_None, // G_FLDEXP
1823 CEFBS_None, // G_FFREXP
1824 CEFBS_None, // G_FNEG
1825 CEFBS_None, // G_FPEXT
1826 CEFBS_None, // G_FPTRUNC
1827 CEFBS_None, // G_FPTOSI
1828 CEFBS_None, // G_FPTOUI
1829 CEFBS_None, // G_SITOFP
1830 CEFBS_None, // G_UITOFP
1831 CEFBS_None, // G_FPTOSI_SAT
1832 CEFBS_None, // G_FPTOUI_SAT
1833 CEFBS_None, // G_FABS
1834 CEFBS_None, // G_FCOPYSIGN
1835 CEFBS_None, // G_IS_FPCLASS
1836 CEFBS_None, // G_FCANONICALIZE
1837 CEFBS_None, // G_FMINNUM
1838 CEFBS_None, // G_FMAXNUM
1839 CEFBS_None, // G_FMINNUM_IEEE
1840 CEFBS_None, // G_FMAXNUM_IEEE
1841 CEFBS_None, // G_FMINIMUM
1842 CEFBS_None, // G_FMAXIMUM
1843 CEFBS_None, // G_FMINIMUMNUM
1844 CEFBS_None, // G_FMAXIMUMNUM
1845 CEFBS_None, // G_GET_FPENV
1846 CEFBS_None, // G_SET_FPENV
1847 CEFBS_None, // G_RESET_FPENV
1848 CEFBS_None, // G_GET_FPMODE
1849 CEFBS_None, // G_SET_FPMODE
1850 CEFBS_None, // G_RESET_FPMODE
1851 CEFBS_None, // G_GET_ROUNDING
1852 CEFBS_None, // G_SET_ROUNDING
1853 CEFBS_None, // G_PTR_ADD
1854 CEFBS_None, // G_PTRMASK
1855 CEFBS_None, // G_SMIN
1856 CEFBS_None, // G_SMAX
1857 CEFBS_None, // G_UMIN
1858 CEFBS_None, // G_UMAX
1859 CEFBS_None, // G_ABS
1860 CEFBS_None, // G_LROUND
1861 CEFBS_None, // G_LLROUND
1862 CEFBS_None, // G_BR
1863 CEFBS_None, // G_BRJT
1864 CEFBS_None, // G_VSCALE
1865 CEFBS_None, // G_INSERT_SUBVECTOR
1866 CEFBS_None, // G_EXTRACT_SUBVECTOR
1867 CEFBS_None, // G_INSERT_VECTOR_ELT
1868 CEFBS_None, // G_EXTRACT_VECTOR_ELT
1869 CEFBS_None, // G_SHUFFLE_VECTOR
1870 CEFBS_None, // G_SPLAT_VECTOR
1871 CEFBS_None, // G_STEP_VECTOR
1872 CEFBS_None, // G_VECTOR_COMPRESS
1873 CEFBS_None, // G_CTTZ
1874 CEFBS_None, // G_CTTZ_ZERO_POISON
1875 CEFBS_None, // G_CTLZ
1876 CEFBS_None, // G_CTLZ_ZERO_POISON
1877 CEFBS_None, // G_CTLS
1878 CEFBS_None, // G_CTPOP
1879 CEFBS_None, // G_BSWAP
1880 CEFBS_None, // G_BITREVERSE
1881 CEFBS_None, // G_CLMUL
1882 CEFBS_None, // G_CLMULH
1883 CEFBS_None, // G_FCEIL
1884 CEFBS_None, // G_FCOS
1885 CEFBS_None, // G_FSIN
1886 CEFBS_None, // G_FSINCOS
1887 CEFBS_None, // G_FTAN
1888 CEFBS_None, // G_FACOS
1889 CEFBS_None, // G_FASIN
1890 CEFBS_None, // G_FATAN
1891 CEFBS_None, // G_FATAN2
1892 CEFBS_None, // G_FCOSH
1893 CEFBS_None, // G_FSINH
1894 CEFBS_None, // G_FTANH
1895 CEFBS_None, // G_FSQRT
1896 CEFBS_None, // G_FFLOOR
1897 CEFBS_None, // G_FRINT
1898 CEFBS_None, // G_FNEARBYINT
1899 CEFBS_None, // G_ADDRSPACE_CAST
1900 CEFBS_None, // G_BLOCK_ADDR
1901 CEFBS_None, // G_JUMP_TABLE
1902 CEFBS_None, // G_DYN_STACKALLOC
1903 CEFBS_None, // G_STACKSAVE
1904 CEFBS_None, // G_STACKRESTORE
1905 CEFBS_None, // G_STRICT_FADD
1906 CEFBS_None, // G_STRICT_FSUB
1907 CEFBS_None, // G_STRICT_FMUL
1908 CEFBS_None, // G_STRICT_FDIV
1909 CEFBS_None, // G_STRICT_FREM
1910 CEFBS_None, // G_STRICT_FMA
1911 CEFBS_None, // G_STRICT_FSQRT
1912 CEFBS_None, // G_STRICT_FLDEXP
1913 CEFBS_None, // G_STRICT_FCMP
1914 CEFBS_None, // G_STRICT_FCMPS
1915 CEFBS_None, // G_READ_REGISTER
1916 CEFBS_None, // G_WRITE_REGISTER
1917 CEFBS_None, // G_MEMCPY
1918 CEFBS_None, // G_MEMCPY_INLINE
1919 CEFBS_None, // G_MEMMOVE
1920 CEFBS_None, // G_MEMSET
1921 CEFBS_None, // G_BZERO
1922 CEFBS_None, // G_MEMSET_INLINE
1923 CEFBS_None, // G_TRAP
1924 CEFBS_None, // G_DEBUGTRAP
1925 CEFBS_None, // G_UBSANTRAP
1926 CEFBS_None, // G_VECREDUCE_SEQ_FADD
1927 CEFBS_None, // G_VECREDUCE_SEQ_FMUL
1928 CEFBS_None, // G_VECREDUCE_FADD
1929 CEFBS_None, // G_VECREDUCE_FMUL
1930 CEFBS_None, // G_VECREDUCE_FMAX
1931 CEFBS_None, // G_VECREDUCE_FMIN
1932 CEFBS_None, // G_VECREDUCE_FMAXIMUM
1933 CEFBS_None, // G_VECREDUCE_FMINIMUM
1934 CEFBS_None, // G_VECREDUCE_FMAXIMUMNUM
1935 CEFBS_None, // G_VECREDUCE_FMINIMUMNUM
1936 CEFBS_None, // G_VECREDUCE_ADD
1937 CEFBS_None, // G_VECREDUCE_MUL
1938 CEFBS_None, // G_VECREDUCE_AND
1939 CEFBS_None, // G_VECREDUCE_OR
1940 CEFBS_None, // G_VECREDUCE_XOR
1941 CEFBS_None, // G_VECREDUCE_SMAX
1942 CEFBS_None, // G_VECREDUCE_SMIN
1943 CEFBS_None, // G_VECREDUCE_UMAX
1944 CEFBS_None, // G_VECREDUCE_UMIN
1945 CEFBS_None, // G_SBFX
1946 CEFBS_None, // G_UBFX
1947 CEFBS_None, // ADJCALLSTACKDOWN
1948 CEFBS_None, // ADJCALLSTACKUP
1949 CEFBS_None, // ADJDYNALLOC
1950 CEFBS_None, // CALL
1951 CEFBS_None, // CALLR
1952 CEFBS_None, // ADDC_F_I_HI
1953 CEFBS_None, // ADDC_F_I_LO
1954 CEFBS_None, // ADDC_F_R
1955 CEFBS_None, // ADDC_I_HI
1956 CEFBS_None, // ADDC_I_LO
1957 CEFBS_None, // ADDC_R
1958 CEFBS_None, // ADD_F_I_HI
1959 CEFBS_None, // ADD_F_I_LO
1960 CEFBS_None, // ADD_F_R
1961 CEFBS_None, // ADD_I_HI
1962 CEFBS_None, // ADD_I_LO
1963 CEFBS_None, // ADD_R
1964 CEFBS_None, // AND_F_I_HI
1965 CEFBS_None, // AND_F_I_LO
1966 CEFBS_None, // AND_F_R
1967 CEFBS_None, // AND_I_HI
1968 CEFBS_None, // AND_I_LO
1969 CEFBS_None, // AND_R
1970 CEFBS_None, // BRCC
1971 CEFBS_None, // BRIND_CC
1972 CEFBS_None, // BRIND_CCA
1973 CEFBS_None, // BRR
1974 CEFBS_None, // BT
1975 CEFBS_None, // JR
1976 CEFBS_None, // LDADDR
1977 CEFBS_None, // LDBs_RI
1978 CEFBS_None, // LDBs_RR
1979 CEFBS_None, // LDBz_RI
1980 CEFBS_None, // LDBz_RR
1981 CEFBS_None, // LDHs_RI
1982 CEFBS_None, // LDHs_RR
1983 CEFBS_None, // LDHz_RI
1984 CEFBS_None, // LDHz_RR
1985 CEFBS_None, // LDW_RI
1986 CEFBS_None, // LDW_RR
1987 CEFBS_None, // LDWz_RR
1988 CEFBS_None, // LEADZ
1989 CEFBS_None, // LOG0
1990 CEFBS_None, // LOG1
1991 CEFBS_None, // LOG2
1992 CEFBS_None, // LOG3
1993 CEFBS_None, // LOG4
1994 CEFBS_None, // MOVHI
1995 CEFBS_None, // NOP
1996 CEFBS_None, // OR_F_I_HI
1997 CEFBS_None, // OR_F_I_LO
1998 CEFBS_None, // OR_F_R
1999 CEFBS_None, // OR_I_HI
2000 CEFBS_None, // OR_I_LO
2001 CEFBS_None, // OR_R
2002 CEFBS_None, // POPC
2003 CEFBS_None, // RET
2004 CEFBS_None, // SA_F_I
2005 CEFBS_None, // SA_I
2006 CEFBS_None, // SCC
2007 CEFBS_None, // SELECT
2008 CEFBS_None, // SFSUB_F_RI_HI
2009 CEFBS_None, // SFSUB_F_RI_LO
2010 CEFBS_None, // SFSUB_F_RR
2011 CEFBS_None, // SHL_F_R
2012 CEFBS_None, // SHL_R
2013 CEFBS_None, // SLI
2014 CEFBS_None, // SL_F_I
2015 CEFBS_None, // SL_I
2016 CEFBS_None, // SRA_F_R
2017 CEFBS_None, // SRA_R
2018 CEFBS_None, // SRL_F_R
2019 CEFBS_None, // SRL_R
2020 CEFBS_None, // STADDR
2021 CEFBS_None, // STB_RI
2022 CEFBS_None, // STB_RR
2023 CEFBS_None, // STH_RI
2024 CEFBS_None, // STH_RR
2025 CEFBS_None, // SUBB_F_I_HI
2026 CEFBS_None, // SUBB_F_I_LO
2027 CEFBS_None, // SUBB_F_R
2028 CEFBS_None, // SUBB_I_HI
2029 CEFBS_None, // SUBB_I_LO
2030 CEFBS_None, // SUBB_R
2031 CEFBS_None, // SUB_F_I_HI
2032 CEFBS_None, // SUB_F_I_LO
2033 CEFBS_None, // SUB_F_R
2034 CEFBS_None, // SUB_I_HI
2035 CEFBS_None, // SUB_I_LO
2036 CEFBS_None, // SUB_R
2037 CEFBS_None, // SW_RI
2038 CEFBS_None, // SW_RR
2039 CEFBS_None, // TRAILZ
2040 CEFBS_None, // XOR_F_I_HI
2041 CEFBS_None, // XOR_F_I_LO
2042 CEFBS_None, // XOR_F_R
2043 CEFBS_None, // XOR_I_HI
2044 CEFBS_None, // XOR_I_LO
2045 CEFBS_None, // XOR_R
2046 };
2047
2048 assert(Opcode < 433);
2049 return FeatureBitsets[RequiredFeaturesRefs[Opcode]];
2050}
2051
2052
2053} // namespace llvm::Lanai_MC
2054
2055#endif // GET_COMPUTE_FEATURES
2056
2057#ifdef GET_AVAILABLE_OPCODE_CHECKER
2058#undef GET_AVAILABLE_OPCODE_CHECKER
2059
2060namespace llvm::Lanai_MC {
2061
2062bool isOpcodeAvailable(unsigned Opcode, const FeatureBitset &Features) {
2063 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
2064 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
2065 FeatureBitset MissingFeatures =
2066 (AvailableFeatures & RequiredFeatures) ^
2067 RequiredFeatures;
2068 return !MissingFeatures.any();
2069}
2070
2071} // namespace llvm::Lanai_MC
2072
2073#endif // GET_AVAILABLE_OPCODE_CHECKER
2074
2075#ifdef ENABLE_INSTR_PREDICATE_VERIFIER
2076#undef ENABLE_INSTR_PREDICATE_VERIFIER
2077
2078#include <sstream>
2079
2080namespace llvm::Lanai_MC {
2081
2082#ifndef NDEBUG
2083static const char *SubtargetFeatureNames[] = {
2084 nullptr
2085};
2086
2087#endif // NDEBUG
2088
2089void verifyInstructionPredicates(
2090 unsigned Opcode, const FeatureBitset &Features) {
2091#ifndef NDEBUG
2092 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
2093 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
2094 FeatureBitset MissingFeatures =
2095 (AvailableFeatures & RequiredFeatures) ^
2096 RequiredFeatures;
2097 if (MissingFeatures.any()) {
2098 std::ostringstream Msg;
2099 Msg << "Attempting to emit " << &LanaiInstrNameData[LanaiInstrNameIndices[Opcode]]
2100 << " instruction but the ";
2101 for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i)
2102 if (MissingFeatures.test(i))
2103 Msg << SubtargetFeatureNames[i] << " ";
2104 Msg << "predicate(s) are not met";
2105 report_fatal_error(Msg.str().c_str());
2106 }
2107#endif // NDEBUG
2108}
2109
2110} // namespace llvm::Lanai_MC
2111
2112#endif // ENABLE_INSTR_PREDICATE_VERIFIER
2113
2114#ifdef GET_INSTRMAP_INFO
2115#undef GET_INSTRMAP_INFO
2116
2117namespace llvm::Lanai {
2118
2119enum PostEncoderMethod {
2120 PostEncoderMethod_adjustPqBitsSpls
2121};
2122
2123// splsIdempotent
2124LLVM_READONLY
2125int32_t splsIdempotent(uint32_t Opcode) {
2126 using namespace Lanai;
2127 static constexpr uint32_t Table[][2] = {
2128 { LDBs_RI, LDBs_RI },
2129 { LDBz_RI, LDBz_RI },
2130 { LDHs_RI, LDHs_RI },
2131 { LDHz_RI, LDHz_RI },
2132 { STB_RI, STB_RI },
2133 { STH_RI, STH_RI },
2134 }; // End of Table
2135
2136 unsigned mid;
2137 unsigned start = 0;
2138 unsigned end = 6;
2139 while (start < end) {
2140 mid = start + (end - start) / 2;
2141 if (Opcode == Table[mid][0])
2142 break;
2143 if (Opcode < Table[mid][0])
2144 end = mid;
2145 else
2146 start = mid + 1;
2147 }
2148 if (start == end)
2149 return -1; // Instruction doesn't exist in this table.
2150
2151 return Table[mid][1];
2152}
2153
2154
2155} // namespace llvm::Lanai
2156
2157#endif // GET_INSTRMAP_INFO
2158
2159