1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Register Enum Values *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9namespace llvm {
10
11class MCRegisterClass;
12const MCRegisterClass &getLanaiMCRegisterClass(unsigned RC);
13namespace Lanai {
14
15enum : unsigned {
16 NoRegister,
17 FP = 1,
18 PC = 2,
19 RCA = 3,
20 RV = 4,
21 SP = 5,
22 SR = 6,
23 R0 = 7,
24 R1 = 8,
25 R2 = 9,
26 R3 = 10,
27 R4 = 11,
28 R5 = 12,
29 R6 = 13,
30 R7 = 14,
31 R8 = 15,
32 R9 = 16,
33 R10 = 17,
34 R11 = 18,
35 R12 = 19,
36 R13 = 20,
37 R14 = 21,
38 R15 = 22,
39 R16 = 23,
40 R17 = 24,
41 R18 = 25,
42 R19 = 26,
43 R20 = 27,
44 R21 = 28,
45 R22 = 29,
46 R23 = 30,
47 R24 = 31,
48 R25 = 32,
49 R26 = 33,
50 R27 = 34,
51 R28 = 35,
52 R29 = 36,
53 R30 = 37,
54 R31 = 38,
55 RR1 = 39,
56 RR2 = 40,
57 NUM_TARGET_REGS // 41
58};
59
60} // namespace Lanai
61
62// Register classes
63
64namespace Lanai {
65
66enum {
67 GPRRegClassID = 0,
68 GPR_with_sub_32RegClassID = 1,
69 CCRRegClassID = 2,
70
71};
72
73} // namespace Lanai
74
75// Subregister indices
76
77namespace Lanai {
78
79enum : uint16_t {
80 NoSubRegister,
81 sub_32, // 1
82 NUM_TARGET_SUBREGS
83};
84
85} // namespace Lanai
86// Register pressure sets enum.
87namespace Lanai {
88
89enum RegisterPressureSets {
90 GPR_with_sub_32 = 0,
91 GPR = 1,
92};
93
94} // namespace Lanai
95
96} // namespace llvm
97