1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Subtarget Enumeration Source Fragment *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_SUBTARGETINFO_ENUM
10#undef GET_SUBTARGETINFO_ENUM
11
12namespace llvm {
13
14
15} // namespace llvm
16
17#endif // GET_SUBTARGETINFO_ENUM
18
19#ifdef GET_SUBTARGETINFO_MACRO
20
21
22#undef GET_SUBTARGETINFO_MACRO
23#endif // GET_SUBTARGETINFO_MACRO
24
25#ifdef GET_SUBTARGETINFO_MC_DESC
26#undef GET_SUBTARGETINFO_MC_DESC
27
28namespace llvm {
29
30
31#ifdef DBGFIELD
32#error "<target>GenSubtargetInfo.inc requires a DBGFIELD macro"
33#endif
34#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
35#define DBGFIELD(x) x,
36#define DBGVAL_OR_NULLPTR(x) x
37#else
38#define DBGFIELD(x)
39#define DBGVAL_OR_NULLPTR(x) nullptr
40#endif
41
42// Functional units for "LanaiItinerary"
43namespace LanaiItineraryFU {
44
45 const InstrStage::FuncUnits ALU_FU = 1ULL << 0;
46 const InstrStage::FuncUnits LDST_FU = 1ULL << 1;
47
48} // namespace LanaiItineraryFU
49
50extern const llvm::InstrStage LanaiStages[] = {
51 { 0, 0, 0, llvm::InstrStage::Required }, // No itinerary
52 { 1, LanaiItineraryFU::ALU_FU, -1, (llvm::InstrStage::ReservationKinds)0 }, // 1
53 { 1, LanaiItineraryFU::LDST_FU, -1, (llvm::InstrStage::ReservationKinds)0 }, // 2
54 { 2, LanaiItineraryFU::LDST_FU, -1, (llvm::InstrStage::ReservationKinds)0 }, // 3
55 { 0, 0, 0, llvm::InstrStage::Required } // End stages
56};
57extern const unsigned LanaiOperandCycles[] = {
58 0, // No itinerary
59 0 // End operand cycles
60};
61extern const unsigned LanaiForwardingPaths[] = {
62 0, // No itinerary
63 0 // End bypass tables
64};
65
66static constexpr llvm::InstrItinerary LanaiItinerary[] = {
67 { 0, 0, 0, 0, 0 }, // 0 NoInstrModel
68 { 1, 1, 2, 0, 0 }, // 1 IIC_ALU_WriteALU
69 { 1, 1, 2, 0, 0 }, // 2 IIC_ALU
70 { 1, 2, 3, 0, 0 }, // 3 IIC_LD_WriteLD
71 { 1, 3, 4, 0, 0 }, // 4 IIC_LDSW_WriteLDSW
72 { 0, 0, 0, 0, 0 }, // 5 WriteLD
73 { 1, 2, 3, 0, 0 }, // 6 IIC_ST_WriteST
74 { 1, 3, 4, 0, 0 }, // 7 IIC_STSW_WriteSTSW
75 { 0, uint16_t(~0U), uint16_t(~0U), uint16_t(~0U), uint16_t(~0U) }// end marker
76};
77
78// ===============================================================
79// Data tables for the new per-operand machine model.
80
81static_assert(1 <= UINT8_MAX, "NumWriteProcResEntries does not fit in uint8_t");
82static_assert(1 <= UINT8_MAX, "NumWriteLatencyEntries does not fit in uint8_t");
83
84// {ProcResourceIdx, ReleaseAtCycle, AcquireAtCycle}
85extern const llvm::MCWriteProcResEntry LanaiWriteProcResTable[] = {
86 { 0, 0, 0 }, // Invalid
87 { 1, 1, 0}, // #1
88 { 2, 1, 0} // #2
89}; // LanaiWriteProcResTable
90
91// {Cycles, WriteResourceID}
92extern const llvm::MCWriteLatencyEntry LanaiWriteLatencyTable[] = {
93 { 0, 0}, // Invalid
94 { 1, 0}, // #1 WriteALU
95 { 2, 0}, // #2 WriteLD_WriteLDSW_WriteST
96 { 4, 0} // #3 WriteSTSW
97}; // LanaiWriteLatencyTable
98
99// {UseIdx, WriteResourceID, Cycles}
100extern const llvm::MCReadAdvanceEntry LanaiReadAdvanceTable[] = {
101 {0, 0, 0}, // Invalid
102}; // LanaiReadAdvanceTable
103
104// {Name, NumMicroOps, BeginGroup, EndGroup, RetireOOO, ReadAdvanceIdx, WriteProcResIdx, WriteLatencyIdx, NumReadAdvanceEntries, NumWriteProcResEntries, NumWriteLatencyEntries}
105static const llvm::MCSchedClassDesc LanaiSchedModelSchedClasses[] = {
106 {DBGFIELD(1) 8191, false, false, false, 0, 0, 0, 0, 0, 0},
107 {DBGFIELD(/*IIC_ALU_WriteALU*/ 19) 1, false, false, false, 0, 1, 1, 0, 1, 1}, // #1
108 {DBGFIELD(/*IIC_ALU*/ 36) 8191, false, false, false, 0, 0, 0, 0, 0, 0}, // #2
109 {DBGFIELD(/*IIC_LD_WriteLD*/ 44) 1, false, false, false, 0, 2, 2, 0, 1, 1}, // #3
110 {DBGFIELD(/*IIC_LDSW_WriteLDSW*/ 59) 1, false, false, false, 0, 2, 2, 0, 1, 1}, // #4
111 {DBGFIELD(/*WriteLD*/ 78) 1, false, false, false, 0, 2, 2, 0, 1, 1}, // #5
112 {DBGFIELD(/*IIC_ST_WriteST*/ 86) 1, false, false, false, 0, 2, 2, 0, 1, 1}, // #6
113 {DBGFIELD(/*IIC_STSW_WriteSTSW*/ 101) 1, false, false, false, 0, 2, 3, 0, 1, 1}, // #7
114}; // LanaiSchedModelSchedClasses
115
116#ifdef __GNUC__
117#pragma GCC diagnostic push
118#pragma GCC diagnostic ignored "-Woverlength-strings"
119#endif
120static constexpr char LanaiSchedClassNamesStorage[] =
121 "\0"
122 "InvalidSchedClass\0"
123 "IIC_ALU_WriteALU\0"
124 "IIC_ALU\0"
125 "IIC_LD_WriteLD\0"
126 "IIC_LDSW_WriteLDSW\0"
127 "WriteLD\0"
128 "IIC_ST_WriteST\0"
129 "IIC_STSW_WriteSTSW\0"
130 ;
131#ifdef __GNUC__
132#pragma GCC diagnostic pop
133#endif
134
135static constexpr llvm::StringTable
136LanaiSchedClassNames = LanaiSchedClassNamesStorage;
137
138static const unsigned LanaiSchedModelProcResourceSubUnits[] = {
139 0, // Invalid
140};
141
142// {Name, NumUnits, SuperIdx, BufferSize, SubUnitsIdxBegin}
143static const llvm::MCProcResourceDesc LanaiSchedModelProcResources[] = {
144 {"InvalidUnit", 0, 0, 0, 0},
145 {"ALU", 1, 0, 0, nullptr}, // #1
146 {"LdSt", 1, 0, 0, nullptr}, // #2
147};
148
149extern const llvm::MCSchedModel LanaiSchedModels[] = {
150{ // NoSchedModel
151 MCSchedModel::DefaultIssueWidth,
152 MCSchedModel::DefaultMicroOpBufferSize,
153 MCSchedModel::DefaultLoopMicroOpBufferSize,
154 MCSchedModel::DefaultLoadLatency,
155 MCSchedModel::DefaultHighLatency,
156 MCSchedModel::DefaultMispredictPenalty,
157 false, // PostRAScheduler
158 false, // CompleteModel
159 false, // EnableIntervals
160 0, // Processor ID
161 nullptr, nullptr, 0, 0, // No instruction-level machine model.
162 DBGVAL_OR_NULLPTR(&LanaiSchedClassNames), // SchedClassNames
163 nullptr, // No Itinerary
164 nullptr // No extra processor descriptor
165 },
166{ // LanaiSchedModel
167 1, // IssueWidth
168 0, // MicroOpBufferSize
169 0, // LoopMicroOpBufferSize
170 2, // LoadLatency
171 MCSchedModel::DefaultHighLatency,
172 10, // MispredictPenalty
173 false, // PostRAScheduler
174 false, // CompleteModel
175 false, // EnableIntervals
176 1, // Processor ID
177 LanaiSchedModelProcResources,
178 LanaiSchedModelSchedClasses,
179 3,
180 8,
181 DBGVAL_OR_NULLPTR(&LanaiSchedClassNames), // SchedClassNames
182 LanaiItinerary,
183 nullptr // No extra processor descriptor
184 },
185};
186
187#undef DBGFIELD
188
189#undef DBGVAL_OR_NULLPTR
190
191// Sorted (by key) array of values for CPU subtype.
192extern const llvm::SubtargetSubTypeKVStorage< 2, 14> LanaiSubTypeKVStorage = {
193 {
194 { sizeof(SubtargetSubTypeKV) * 2 + 1, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 1 },
195 { sizeof(SubtargetSubTypeKV) * 1 + 9, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 1 },
196 },
197 "\000generic\000v11\000"};
198
199namespace Lanai_MC {
200
201unsigned resolveVariantSchedClassImpl(unsigned SchedClass,
202 const MCInst *MI, const MCInstrInfo *MCII, const MCSubtargetInfo &STI, unsigned CPUID) {
203 // Don't know how to resolve this scheduling class.
204 return 0;
205}
206
207} // namespace Lanai_MC
208struct LanaiGenMCSubtargetInfo : public MCSubtargetInfo {
209 LanaiGenMCSubtargetInfo(const Triple &TT,
210 StringRef CPU, StringRef TuneCPU, StringRef FS,
211 StringTable PN,
212 ArrayRef<SubtargetFeatureKV> PF,
213 ArrayRef<SubtargetSubTypeKV> PD,
214 const MCSchedModel *PSM,
215 const MCWriteProcResEntry *WPR,
216 const MCWriteLatencyEntry *WL,
217 const MCReadAdvanceEntry *RA, const InstrStage *IS,
218 const unsigned *OC, const unsigned *FP) :
219 MCSubtargetInfo(TT, CPU, TuneCPU, FS, PN, PF, PD, PSM,
220 WPR, WL, RA, IS, OC, FP) { }
221
222 unsigned resolveVariantSchedClass(unsigned SchedClass,
223 const MCInst *MI, const MCInstrInfo *MCII,
224 unsigned CPUID) const final {
225 return Lanai_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, *this, CPUID);
226 }
227};
228
229static inline MCSubtargetInfo *createLanaiMCSubtargetInfoImpl(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS) {
230 return new LanaiGenMCSubtargetInfo(TT, CPU, TuneCPU, FS, StringTable(LanaiSubTypeKVStorage.Strings), {}, LanaiSubTypeKVStorage.SubTypes, LanaiSchedModels,
231 LanaiWriteProcResTable, LanaiWriteLatencyTable, LanaiReadAdvanceTable,
232 LanaiStages, LanaiOperandCycles, LanaiForwardingPaths);
233}
234
235
236} // namespace llvm
237
238#endif // GET_SUBTARGETINFO_MC_DESC
239
240#ifdef GET_SUBTARGETINFO_TARGET_DESC
241#undef GET_SUBTARGETINFO_TARGET_DESC
242
243#include "llvm/ADT/BitmaskEnum.h"
244#include "llvm/Support/Debug.h"
245#include "llvm/Support/raw_ostream.h"
246
247// ParseSubtargetFeatures - Parses features string setting specified
248// subtarget options.
249void llvm::LanaiSubtarget::ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS) {
250 LLVM_DEBUG(dbgs() << "\nFeatures:" << FS);
251 LLVM_DEBUG(dbgs() << "\nCPU:" << CPU);
252 LLVM_DEBUG(dbgs() << "\nTuneCPU:" << TuneCPU << "\n\n");
253}
254
255#endif // GET_SUBTARGETINFO_TARGET_DESC
256
257#ifdef GET_SUBTARGETINFO_HEADER
258#undef GET_SUBTARGETINFO_HEADER
259
260namespace llvm {
261
262class DFAPacketizer;
263namespace Lanai_MC {
264
265unsigned resolveVariantSchedClassImpl(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, const MCSubtargetInfo &STI, unsigned CPUID);
266
267} // namespace Lanai_MC
268struct LanaiGenSubtargetInfo : public TargetSubtargetInfo {
269 explicit LanaiGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS);
270public:
271 unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const final;
272 unsigned resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const final;
273 DFAPacketizer *createDFAPacketizer(const InstrItineraryData *IID) const;
274 const FeatureBitset &getInlineIgnoreFeatures() const override;
275 const FeatureBitset &getInlineInverseFeatures() const override;
276 const FeatureBitset &getInlineMustMatchFeatures() const override;
277};
278
279} // namespace llvm
280
281#endif // GET_SUBTARGETINFO_HEADER
282
283#ifdef GET_SUBTARGETINFO_CTOR
284#undef GET_SUBTARGETINFO_CTOR
285
286#include "llvm/CodeGen/TargetSchedule.h"
287
288namespace llvm {
289
290extern const llvm::StringRef LanaiNames[];
291extern const llvm::SubtargetSubTypeKVStorage<2, 14> LanaiSubTypeKVStorage;
292extern const llvm::MCSchedModel LanaiSchedModels[];
293extern const llvm::MCWriteProcResEntry LanaiWriteProcResTable[];
294extern const llvm::MCWriteLatencyEntry LanaiWriteLatencyTable[];
295extern const llvm::MCReadAdvanceEntry LanaiReadAdvanceTable[];
296extern const llvm::InstrStage LanaiStages[];
297extern const unsigned LanaiOperandCycles[];
298extern const unsigned LanaiForwardingPaths[];
299LanaiGenSubtargetInfo::LanaiGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS)
300 : TargetSubtargetInfo(TT, CPU, TuneCPU, FS, StringTable(LanaiSubTypeKVStorage.Strings), {}, ArrayRef(LanaiSubTypeKVStorage.SubTypes), LanaiSchedModels,
301 LanaiWriteProcResTable, LanaiWriteLatencyTable, LanaiReadAdvanceTable,
302 LanaiStages, LanaiOperandCycles, LanaiForwardingPaths) {}
303
304unsigned LanaiGenSubtargetInfo
305::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const {
306 report_fatal_error("Expected a variant SchedClass");
307} // LanaiGenSubtargetInfo::resolveSchedClass
308
309unsigned LanaiGenSubtargetInfo
310::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const {
311 return Lanai_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, *this, CPUID);
312} // LanaiGenSubtargetInfo::resolveVariantSchedClass
313
314const FeatureBitset &LanaiGenSubtargetInfo::getInlineIgnoreFeatures() const {
315 static constexpr FeatureBitset Features = {
316 };
317 return Features;
318}
319
320const FeatureBitset &LanaiGenSubtargetInfo::getInlineInverseFeatures() const {
321 static constexpr FeatureBitset Features = {
322 };
323 return Features;
324}
325
326const FeatureBitset &LanaiGenSubtargetInfo::getInlineMustMatchFeatures() const {
327 static constexpr FeatureBitset Features = {
328 };
329 return Features;
330}
331
332
333} // namespace llvm
334
335#endif // GET_SUBTARGETINFO_CTOR
336
337#ifdef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
338#undef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
339
340
341#endif // GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
342
343#ifdef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
344#undef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
345
346
347#endif // GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
348
349