1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Subtarget Enumeration Source Fragment *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_SUBTARGETINFO_ENUM
10#undef GET_SUBTARGETINFO_ENUM
11
12namespace llvm {
13
14
15} // namespace llvm
16
17#endif // GET_SUBTARGETINFO_ENUM
18
19#ifdef GET_SUBTARGETINFO_MACRO
20
21
22#undef GET_SUBTARGETINFO_MACRO
23#endif // GET_SUBTARGETINFO_MACRO
24
25#ifdef GET_SUBTARGETINFO_MC_DESC
26#undef GET_SUBTARGETINFO_MC_DESC
27
28namespace llvm {
29
30
31#ifdef DBGFIELD
32#error "<target>GenSubtargetInfo.inc requires a DBGFIELD macro"
33#endif
34#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
35#define DBGFIELD(x) x,
36#define DBGVAL_OR_NULLPTR(x) x
37#else
38#define DBGFIELD(x)
39#define DBGVAL_OR_NULLPTR(x) nullptr
40#endif
41
42// Functional units for "LanaiItinerary"
43namespace LanaiItineraryFU {
44
45 const InstrStage::FuncUnits ALU_FU = 1ULL << 0;
46 const InstrStage::FuncUnits LDST_FU = 1ULL << 1;
47
48} // namespace LanaiItineraryFU
49
50extern const llvm::InstrStage LanaiStages[] = {
51 { 0, 0, 0, llvm::InstrStage::Required }, // No itinerary
52 { 1, LanaiItineraryFU::ALU_FU, -1, (llvm::InstrStage::ReservationKinds)0 }, // 1
53 { 1, LanaiItineraryFU::LDST_FU, -1, (llvm::InstrStage::ReservationKinds)0 }, // 2
54 { 2, LanaiItineraryFU::LDST_FU, -1, (llvm::InstrStage::ReservationKinds)0 }, // 3
55 { 0, 0, 0, llvm::InstrStage::Required } // End stages
56};
57extern const unsigned LanaiOperandCycles[] = {
58 0, // No itinerary
59 0 // End operand cycles
60};
61extern const unsigned LanaiForwardingPaths[] = {
62 0, // No itinerary
63 0 // End bypass tables
64};
65
66static constexpr llvm::InstrItinerary LanaiItinerary[] = {
67 { 0, 0, 0, 0, 0 }, // 0 NoInstrModel
68 { 1, 1, 2, 0, 0 }, // 1 IIC_ALU_WriteALU
69 { 1, 1, 2, 0, 0 }, // 2 IIC_ALU
70 { 1, 2, 3, 0, 0 }, // 3 IIC_LD_WriteLD
71 { 1, 3, 4, 0, 0 }, // 4 IIC_LDSW_WriteLDSW
72 { 0, 0, 0, 0, 0 }, // 5 WriteLD
73 { 1, 2, 3, 0, 0 }, // 6 IIC_ST_WriteST
74 { 1, 3, 4, 0, 0 }, // 7 IIC_STSW_WriteSTSW
75 { 0, uint16_t(~0U), uint16_t(~0U), uint16_t(~0U), uint16_t(~0U) }// end marker
76};
77
78// ===============================================================
79// Data tables for the new per-operand machine model.
80
81// {ProcResourceIdx, ReleaseAtCycle, AcquireAtCycle}
82extern const llvm::MCWriteProcResEntry LanaiWriteProcResTable[] = {
83 { 0, 0, 0 }, // Invalid
84 { 1, 1, 0}, // #1
85 { 2, 1, 0} // #2
86}; // LanaiWriteProcResTable
87
88// {Cycles, WriteResourceID}
89extern const llvm::MCWriteLatencyEntry LanaiWriteLatencyTable[] = {
90 { 0, 0}, // Invalid
91 { 1, 0}, // #1 WriteALU
92 { 2, 0}, // #2 WriteLD_WriteLDSW_WriteST
93 { 4, 0} // #3 WriteSTSW
94}; // LanaiWriteLatencyTable
95
96// {UseIdx, WriteResourceID, Cycles}
97extern const llvm::MCReadAdvanceEntry LanaiReadAdvanceTable[] = {
98 {0, 0, 0}, // Invalid
99}; // LanaiReadAdvanceTable
100
101// {Name, NumMicroOps, BeginGroup, EndGroup, RetireOOO, WriteProcResIdx,#, WriteLatencyIdx,#, ReadAdvanceIdx,#}
102static const llvm::MCSchedClassDesc LanaiSchedModelSchedClasses[] = {
103 {DBGFIELD(1) 8191, false, false, false, 0, 0, 0, 0, 0, 0},
104 {DBGFIELD(/*IIC_ALU_WriteALU*/ 19) 1, false, false, false, 1, 1, 1, 1, 0, 0}, // #1
105 {DBGFIELD(/*IIC_ALU*/ 36) 8191, false, false, false, 0, 0, 0, 0, 0, 0}, // #2
106 {DBGFIELD(/*IIC_LD_WriteLD*/ 44) 1, false, false, false, 2, 1, 2, 1, 0, 0}, // #3
107 {DBGFIELD(/*IIC_LDSW_WriteLDSW*/ 59) 1, false, false, false, 2, 1, 2, 1, 0, 0}, // #4
108 {DBGFIELD(/*WriteLD*/ 78) 1, false, false, false, 2, 1, 2, 1, 0, 0}, // #5
109 {DBGFIELD(/*IIC_ST_WriteST*/ 86) 1, false, false, false, 2, 1, 2, 1, 0, 0}, // #6
110 {DBGFIELD(/*IIC_STSW_WriteSTSW*/ 101) 1, false, false, false, 2, 1, 3, 1, 0, 0}, // #7
111}; // LanaiSchedModelSchedClasses
112
113#ifdef __GNUC__
114#pragma GCC diagnostic push
115#pragma GCC diagnostic ignored "-Woverlength-strings"
116#endif
117static constexpr char LanaiSchedClassNamesStorage[] =
118 "\0"
119 "InvalidSchedClass\0"
120 "IIC_ALU_WriteALU\0"
121 "IIC_ALU\0"
122 "IIC_LD_WriteLD\0"
123 "IIC_LDSW_WriteLDSW\0"
124 "WriteLD\0"
125 "IIC_ST_WriteST\0"
126 "IIC_STSW_WriteSTSW\0"
127 ;
128#ifdef __GNUC__
129#pragma GCC diagnostic pop
130#endif
131
132static constexpr llvm::StringTable
133LanaiSchedClassNames = LanaiSchedClassNamesStorage;
134
135static const llvm::MCSchedModel NoSchedModel = {
136 MCSchedModel::DefaultIssueWidth,
137 MCSchedModel::DefaultMicroOpBufferSize,
138 MCSchedModel::DefaultLoopMicroOpBufferSize,
139 MCSchedModel::DefaultLoadLatency,
140 MCSchedModel::DefaultHighLatency,
141 MCSchedModel::DefaultMispredictPenalty,
142 false, // PostRAScheduler
143 false, // CompleteModel
144 false, // EnableIntervals
145 0, // Processor ID
146 nullptr, nullptr, 0, 0, // No instruction-level machine model.
147 DBGVAL_OR_NULLPTR(&LanaiSchedClassNames), // SchedClassNames
148 nullptr, // No Itinerary
149 nullptr // No extra processor descriptor
150};
151
152static const unsigned LanaiSchedModelProcResourceSubUnits[] = {
153 0, // Invalid
154};
155
156// {Name, NumUnits, SuperIdx, BufferSize, SubUnitsIdxBegin}
157static const llvm::MCProcResourceDesc LanaiSchedModelProcResources[] = {
158 {"InvalidUnit", 0, 0, 0, 0},
159 {"ALU", 1, 0, 0, nullptr}, // #1
160 {"LdSt", 1, 0, 0, nullptr}, // #2
161};
162
163static const llvm::MCSchedModel LanaiSchedModel = {
164 1, // IssueWidth
165 0, // MicroOpBufferSize
166 0, // LoopMicroOpBufferSize
167 2, // LoadLatency
168 MCSchedModel::DefaultHighLatency,
169 10, // MispredictPenalty
170 false, // PostRAScheduler
171 false, // CompleteModel
172 false, // EnableIntervals
173 1, // Processor ID
174 LanaiSchedModelProcResources,
175 LanaiSchedModelSchedClasses,
176 3,
177 8,
178 DBGVAL_OR_NULLPTR(&LanaiSchedClassNames), // SchedClassNames
179 LanaiItinerary,
180 nullptr // No extra processor descriptor
181};
182
183#undef DBGFIELD
184
185#undef DBGVAL_OR_NULLPTR
186
187// Sorted (by key) array of values for CPU subtype.
188extern const llvm::SubtargetSubTypeKV LanaiSubTypeKV[] = {
189 { "generic", { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &LanaiSchedModel },
190 { "v11", { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &LanaiSchedModel },
191};
192
193// Sorted array of names of CPU subtypes, including aliases.
194extern const llvm::StringRef LanaiNames[] = {
195"generic",
196"v11"};
197
198namespace Lanai_MC {
199
200unsigned resolveVariantSchedClassImpl(unsigned SchedClass,
201 const MCInst *MI, const MCInstrInfo *MCII, const MCSubtargetInfo &STI, unsigned CPUID) {
202 // Don't know how to resolve this scheduling class.
203 return 0;
204}
205
206} // namespace Lanai_MC
207struct LanaiGenMCSubtargetInfo : public MCSubtargetInfo {
208 LanaiGenMCSubtargetInfo(const Triple &TT,
209 StringRef CPU, StringRef TuneCPU, StringRef FS,
210 ArrayRef<StringRef> PN,
211 ArrayRef<SubtargetFeatureKV> PF,
212 ArrayRef<SubtargetSubTypeKV> PD,
213 const MCWriteProcResEntry *WPR,
214 const MCWriteLatencyEntry *WL,
215 const MCReadAdvanceEntry *RA, const InstrStage *IS,
216 const unsigned *OC, const unsigned *FP) :
217 MCSubtargetInfo(TT, CPU, TuneCPU, FS, PN, PF, PD,
218 WPR, WL, RA, IS, OC, FP) { }
219
220 unsigned resolveVariantSchedClass(unsigned SchedClass,
221 const MCInst *MI, const MCInstrInfo *MCII,
222 unsigned CPUID) const final {
223 return Lanai_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, *this, CPUID);
224 }
225};
226
227static inline MCSubtargetInfo *createLanaiMCSubtargetInfoImpl(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS) {
228 return new LanaiGenMCSubtargetInfo(TT, CPU, TuneCPU, FS, LanaiNames, {}, LanaiSubTypeKV,
229 LanaiWriteProcResTable, LanaiWriteLatencyTable, LanaiReadAdvanceTable,
230 LanaiStages, LanaiOperandCycles, LanaiForwardingPaths);
231}
232
233
234} // namespace llvm
235
236#endif // GET_SUBTARGETINFO_MC_DESC
237
238#ifdef GET_SUBTARGETINFO_TARGET_DESC
239#undef GET_SUBTARGETINFO_TARGET_DESC
240
241#include "llvm/ADT/BitmaskEnum.h"
242#include "llvm/Support/Debug.h"
243#include "llvm/Support/raw_ostream.h"
244
245// ParseSubtargetFeatures - Parses features string setting specified
246// subtarget options.
247void llvm::LanaiSubtarget::ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS) {
248 LLVM_DEBUG(dbgs() << "\nFeatures:" << FS);
249 LLVM_DEBUG(dbgs() << "\nCPU:" << CPU);
250 LLVM_DEBUG(dbgs() << "\nTuneCPU:" << TuneCPU << "\n\n");
251}
252
253#endif // GET_SUBTARGETINFO_TARGET_DESC
254
255#ifdef GET_SUBTARGETINFO_HEADER
256#undef GET_SUBTARGETINFO_HEADER
257
258namespace llvm {
259
260class DFAPacketizer;
261namespace Lanai_MC {
262
263unsigned resolveVariantSchedClassImpl(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, const MCSubtargetInfo &STI, unsigned CPUID);
264
265} // namespace Lanai_MC
266struct LanaiGenSubtargetInfo : public TargetSubtargetInfo {
267 explicit LanaiGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS);
268public:
269 unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const final;
270 unsigned resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const final;
271 DFAPacketizer *createDFAPacketizer(const InstrItineraryData *IID) const;
272};
273
274} // namespace llvm
275
276#endif // GET_SUBTARGETINFO_HEADER
277
278#ifdef GET_SUBTARGETINFO_CTOR
279#undef GET_SUBTARGETINFO_CTOR
280
281#include "llvm/CodeGen/TargetSchedule.h"
282
283namespace llvm {
284
285extern const llvm::StringRef LanaiNames[];
286extern const llvm::SubtargetFeatureKV LanaiFeatureKV[];
287extern const llvm::SubtargetSubTypeKV LanaiSubTypeKV[];
288extern const llvm::MCWriteProcResEntry LanaiWriteProcResTable[];
289extern const llvm::MCWriteLatencyEntry LanaiWriteLatencyTable[];
290extern const llvm::MCReadAdvanceEntry LanaiReadAdvanceTable[];
291extern const llvm::InstrStage LanaiStages[];
292extern const unsigned LanaiOperandCycles[];
293extern const unsigned LanaiForwardingPaths[];
294LanaiGenSubtargetInfo::LanaiGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS)
295 : TargetSubtargetInfo(TT, CPU, TuneCPU, FS, ArrayRef(LanaiNames, 2), {}, ArrayRef(LanaiSubTypeKV, 2),
296 LanaiWriteProcResTable, LanaiWriteLatencyTable, LanaiReadAdvanceTable,
297 LanaiStages, LanaiOperandCycles, LanaiForwardingPaths) {}
298
299unsigned LanaiGenSubtargetInfo
300::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const {
301 report_fatal_error("Expected a variant SchedClass");
302} // LanaiGenSubtargetInfo::resolveSchedClass
303
304unsigned LanaiGenSubtargetInfo
305::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const {
306 return Lanai_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, *this, CPUID);
307} // LanaiGenSubtargetInfo::resolveVariantSchedClass
308
309
310} // namespace llvm
311
312#endif // GET_SUBTARGETINFO_CTOR
313
314#ifdef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
315#undef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
316
317
318#endif // GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
319
320#ifdef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
321#undef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
322
323
324#endif // GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
325
326