| 1 | /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
| 2 | |* *| |
| 3 | |* Target Register Enum Values *| |
| 4 | |* *| |
| 5 | |* Automatically generated file, do not edit! *| |
| 6 | |* *| |
| 7 | \*===----------------------------------------------------------------------===*/ |
| 8 | |
| 9 | namespace llvm { |
| 10 | |
| 11 | class MCRegisterClass; |
| 12 | extern const MCRegisterClass LoongArchMCRegisterClasses[]; |
| 13 | |
| 14 | namespace LoongArch { |
| 15 | enum : unsigned { |
| 16 | NoRegister, |
| 17 | F0 = 1, |
| 18 | F1 = 2, |
| 19 | F2 = 3, |
| 20 | F3 = 4, |
| 21 | F4 = 5, |
| 22 | F5 = 6, |
| 23 | F6 = 7, |
| 24 | F7 = 8, |
| 25 | F8 = 9, |
| 26 | F9 = 10, |
| 27 | F10 = 11, |
| 28 | F11 = 12, |
| 29 | F12 = 13, |
| 30 | F13 = 14, |
| 31 | F14 = 15, |
| 32 | F15 = 16, |
| 33 | F16 = 17, |
| 34 | F17 = 18, |
| 35 | F18 = 19, |
| 36 | F19 = 20, |
| 37 | F20 = 21, |
| 38 | F21 = 22, |
| 39 | F22 = 23, |
| 40 | F23 = 24, |
| 41 | F24 = 25, |
| 42 | F25 = 26, |
| 43 | F26 = 27, |
| 44 | F27 = 28, |
| 45 | F28 = 29, |
| 46 | F29 = 30, |
| 47 | F30 = 31, |
| 48 | F31 = 32, |
| 49 | FCC0 = 33, |
| 50 | FCC1 = 34, |
| 51 | FCC2 = 35, |
| 52 | FCC3 = 36, |
| 53 | FCC4 = 37, |
| 54 | FCC5 = 38, |
| 55 | FCC6 = 39, |
| 56 | FCC7 = 40, |
| 57 | FCSR0 = 41, |
| 58 | FCSR1 = 42, |
| 59 | FCSR2 = 43, |
| 60 | FCSR3 = 44, |
| 61 | R0 = 45, |
| 62 | R1 = 46, |
| 63 | R2 = 47, |
| 64 | R3 = 48, |
| 65 | R4 = 49, |
| 66 | R5 = 50, |
| 67 | R6 = 51, |
| 68 | R7 = 52, |
| 69 | R8 = 53, |
| 70 | R9 = 54, |
| 71 | R10 = 55, |
| 72 | R11 = 56, |
| 73 | R12 = 57, |
| 74 | R13 = 58, |
| 75 | R14 = 59, |
| 76 | R15 = 60, |
| 77 | R16 = 61, |
| 78 | R17 = 62, |
| 79 | R18 = 63, |
| 80 | R19 = 64, |
| 81 | R20 = 65, |
| 82 | R21 = 66, |
| 83 | R22 = 67, |
| 84 | R23 = 68, |
| 85 | R24 = 69, |
| 86 | R25 = 70, |
| 87 | R26 = 71, |
| 88 | R27 = 72, |
| 89 | R28 = 73, |
| 90 | R29 = 74, |
| 91 | R30 = 75, |
| 92 | R31 = 76, |
| 93 | SCR0 = 77, |
| 94 | SCR1 = 78, |
| 95 | SCR2 = 79, |
| 96 | SCR3 = 80, |
| 97 | VR0 = 81, |
| 98 | VR1 = 82, |
| 99 | VR2 = 83, |
| 100 | VR3 = 84, |
| 101 | VR4 = 85, |
| 102 | VR5 = 86, |
| 103 | VR6 = 87, |
| 104 | VR7 = 88, |
| 105 | VR8 = 89, |
| 106 | VR9 = 90, |
| 107 | VR10 = 91, |
| 108 | VR11 = 92, |
| 109 | VR12 = 93, |
| 110 | VR13 = 94, |
| 111 | VR14 = 95, |
| 112 | VR15 = 96, |
| 113 | VR16 = 97, |
| 114 | VR17 = 98, |
| 115 | VR18 = 99, |
| 116 | VR19 = 100, |
| 117 | VR20 = 101, |
| 118 | VR21 = 102, |
| 119 | VR22 = 103, |
| 120 | VR23 = 104, |
| 121 | VR24 = 105, |
| 122 | VR25 = 106, |
| 123 | VR26 = 107, |
| 124 | VR27 = 108, |
| 125 | VR28 = 109, |
| 126 | VR29 = 110, |
| 127 | VR30 = 111, |
| 128 | VR31 = 112, |
| 129 | XR0 = 113, |
| 130 | XR1 = 114, |
| 131 | XR2 = 115, |
| 132 | XR3 = 116, |
| 133 | XR4 = 117, |
| 134 | XR5 = 118, |
| 135 | XR6 = 119, |
| 136 | XR7 = 120, |
| 137 | XR8 = 121, |
| 138 | XR9 = 122, |
| 139 | XR10 = 123, |
| 140 | XR11 = 124, |
| 141 | XR12 = 125, |
| 142 | XR13 = 126, |
| 143 | XR14 = 127, |
| 144 | XR15 = 128, |
| 145 | XR16 = 129, |
| 146 | XR17 = 130, |
| 147 | XR18 = 131, |
| 148 | XR19 = 132, |
| 149 | XR20 = 133, |
| 150 | XR21 = 134, |
| 151 | XR22 = 135, |
| 152 | XR23 = 136, |
| 153 | XR24 = 137, |
| 154 | XR25 = 138, |
| 155 | XR26 = 139, |
| 156 | XR27 = 140, |
| 157 | XR28 = 141, |
| 158 | XR29 = 142, |
| 159 | XR30 = 143, |
| 160 | XR31 = 144, |
| 161 | F0_64 = 145, |
| 162 | F1_64 = 146, |
| 163 | F2_64 = 147, |
| 164 | F3_64 = 148, |
| 165 | F4_64 = 149, |
| 166 | F5_64 = 150, |
| 167 | F6_64 = 151, |
| 168 | F7_64 = 152, |
| 169 | F8_64 = 153, |
| 170 | F9_64 = 154, |
| 171 | F10_64 = 155, |
| 172 | F11_64 = 156, |
| 173 | F12_64 = 157, |
| 174 | F13_64 = 158, |
| 175 | F14_64 = 159, |
| 176 | F15_64 = 160, |
| 177 | F16_64 = 161, |
| 178 | F17_64 = 162, |
| 179 | F18_64 = 163, |
| 180 | F19_64 = 164, |
| 181 | F20_64 = 165, |
| 182 | F21_64 = 166, |
| 183 | F22_64 = 167, |
| 184 | F23_64 = 168, |
| 185 | F24_64 = 169, |
| 186 | F25_64 = 170, |
| 187 | F26_64 = 171, |
| 188 | F27_64 = 172, |
| 189 | F28_64 = 173, |
| 190 | F29_64 = 174, |
| 191 | F30_64 = 175, |
| 192 | F31_64 = 176, |
| 193 | NUM_TARGET_REGS // 177 |
| 194 | }; |
| 195 | } // end namespace LoongArch |
| 196 | |
| 197 | // Register classes |
| 198 | |
| 199 | namespace LoongArch { |
| 200 | enum { |
| 201 | FPR32RegClassID = 0, |
| 202 | GPRRegClassID = 1, |
| 203 | GPRJRRegClassID = 2, |
| 204 | GPRNoR0R1RegClassID = 3, |
| 205 | GPRTRegClassID = 4, |
| 206 | CFRRegClassID = 5, |
| 207 | FCSRRegClassID = 6, |
| 208 | SCRRegClassID = 7, |
| 209 | FPR64RegClassID = 8, |
| 210 | LSX128RegClassID = 9, |
| 211 | LASX256RegClassID = 10, |
| 212 | |
| 213 | }; |
| 214 | } // end namespace LoongArch |
| 215 | |
| 216 | |
| 217 | // Register alternate name indices |
| 218 | |
| 219 | namespace LoongArch { |
| 220 | enum { |
| 221 | NoRegAltName, // 0 |
| 222 | RegAliasName, // 1 |
| 223 | NUM_TARGET_REG_ALT_NAMES = 2 |
| 224 | }; |
| 225 | } // end namespace LoongArch |
| 226 | |
| 227 | |
| 228 | // Subregister indices |
| 229 | |
| 230 | namespace LoongArch { |
| 231 | enum : uint16_t { |
| 232 | NoSubRegister, |
| 233 | sub_32, // 1 |
| 234 | sub_64, // 2 |
| 235 | sub_128, // 3 |
| 236 | NUM_TARGET_SUBREGS |
| 237 | }; |
| 238 | } // end namespace LoongArch |
| 239 | |
| 240 | // Register pressure sets enum. |
| 241 | namespace LoongArch { |
| 242 | enum RegisterPressureSets { |
| 243 | CFR = 0, |
| 244 | GPRT = 1, |
| 245 | FPR32 = 2, |
| 246 | GPR = 3, |
| 247 | }; |
| 248 | } // end namespace LoongArch |
| 249 | |
| 250 | } // end namespace llvm |
| 251 | |
| 252 | |