1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Subtarget Enumeration Source Fragment *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_SUBTARGETINFO_ENUM
10#undef GET_SUBTARGETINFO_ENUM
11
12namespace llvm {
13
14namespace LoongArch {
15
16enum {
17 Feature32Bit = 0,
18 Feature32S = 1,
19 Feature64Bit = 2,
20 FeatureBasicD = 3,
21 FeatureBasicF = 4,
22 FeatureDiv32 = 5,
23 FeatureExtLASX = 6,
24 FeatureExtLBT = 7,
25 FeatureExtLSX = 8,
26 FeatureExtLVZ = 9,
27 FeatureFrecipe = 10,
28 FeatureLAMCAS = 11,
29 FeatureLAM_BH = 12,
30 FeatureLD_SEQ_SA = 13,
31 FeatureRelax = 14,
32 FeatureSCQ = 15,
33 FeatureUAL = 16,
34 LaGlobalWithAbs = 17,
35 LaGlobalWithPcrel = 18,
36 LaLocalWithAbs = 19,
37 TunePreferWInst = 20,
38 NumSubtargetFeatures = 21
39};
40
41} // namespace LoongArch
42
43} // namespace llvm
44
45#endif // GET_SUBTARGETINFO_ENUM
46
47#ifdef GET_SUBTARGETINFO_MACRO
48
49GET_SUBTARGETINFO_MACRO(Has32S, false, has32S)
50GET_SUBTARGETINFO_MACRO(HasBasicD, false, hasBasicD)
51GET_SUBTARGETINFO_MACRO(HasBasicF, false, hasBasicF)
52GET_SUBTARGETINFO_MACRO(HasDiv32, false, hasDiv32)
53GET_SUBTARGETINFO_MACRO(HasExtLASX, false, hasExtLASX)
54GET_SUBTARGETINFO_MACRO(HasExtLBT, false, hasExtLBT)
55GET_SUBTARGETINFO_MACRO(HasExtLSX, false, hasExtLSX)
56GET_SUBTARGETINFO_MACRO(HasExtLVZ, false, hasExtLVZ)
57GET_SUBTARGETINFO_MACRO(HasFrecipe, false, hasFrecipe)
58GET_SUBTARGETINFO_MACRO(HasLA32, false, hasLA32)
59GET_SUBTARGETINFO_MACRO(HasLA64, false, hasLA64)
60GET_SUBTARGETINFO_MACRO(HasLAMCAS, false, hasLAMCAS)
61GET_SUBTARGETINFO_MACRO(HasLAM_BH, false, hasLAM_BH)
62GET_SUBTARGETINFO_MACRO(HasLD_SEQ_SA, false, hasLD_SEQ_SA)
63GET_SUBTARGETINFO_MACRO(HasLaGlobalWithAbs, false, hasLaGlobalWithAbs)
64GET_SUBTARGETINFO_MACRO(HasLaGlobalWithPcrel, false, hasLaGlobalWithPcrel)
65GET_SUBTARGETINFO_MACRO(HasLaLocalWithAbs, false, hasLaLocalWithAbs)
66GET_SUBTARGETINFO_MACRO(HasLinkerRelax, false, hasLinkerRelax)
67GET_SUBTARGETINFO_MACRO(HasSCQ, false, hasSCQ)
68GET_SUBTARGETINFO_MACRO(HasUAL, false, hasUAL)
69GET_SUBTARGETINFO_MACRO(PreferWInst, false, preferWInst)
70
71#undef GET_SUBTARGETINFO_MACRO
72#endif // GET_SUBTARGETINFO_MACRO
73
74#ifdef GET_SUBTARGETINFO_MC_DESC
75#undef GET_SUBTARGETINFO_MC_DESC
76
77namespace llvm {
78
79// Sorted (by key) array of values for CPU features.
80extern const llvm::SubtargetFeatureKVStorage< 21, 1017> LoongArchFeatureKVStorage = {
81 {
82 { sizeof(SubtargetFeatureKV) * 21 + 1, sizeof(SubtargetFeatureKV) * 21 + 7, LoongArch::Feature32Bit, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
83 { sizeof(SubtargetFeatureKV) * 20 + 56, sizeof(SubtargetFeatureKV) * 20 + 60, LoongArch::Feature32S, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
84 { sizeof(SubtargetFeatureKV) * 19 + 102, sizeof(SubtargetFeatureKV) * 19 + 108, LoongArch::Feature64Bit, { { { 0x2ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
85 { sizeof(SubtargetFeatureKV) * 18 + 157, sizeof(SubtargetFeatureKV) * 18 + 159, LoongArch::FeatureBasicD, { { { 0x10ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
86 { sizeof(SubtargetFeatureKV) * 17 + 197, sizeof(SubtargetFeatureKV) * 17 + 203, LoongArch::FeatureDiv32, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
87 { sizeof(SubtargetFeatureKV) * 16 + 277, sizeof(SubtargetFeatureKV) * 16 + 279, LoongArch::FeatureBasicF, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
88 { sizeof(SubtargetFeatureKV) * 15 + 317, sizeof(SubtargetFeatureKV) * 15 + 325, LoongArch::FeatureFrecipe, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
89 { sizeof(SubtargetFeatureKV) * 14 + 378, sizeof(SubtargetFeatureKV) * 14 + 397, LoongArch::LaGlobalWithAbs, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
90 { sizeof(SubtargetFeatureKV) * 13 + 424, sizeof(SubtargetFeatureKV) * 13 + 445, LoongArch::LaGlobalWithPcrel, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
91 { sizeof(SubtargetFeatureKV) * 12 + 474, sizeof(SubtargetFeatureKV) * 12 + 492, LoongArch::LaLocalWithAbs, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
92 { sizeof(SubtargetFeatureKV) * 11 + 518, sizeof(SubtargetFeatureKV) * 11 + 525, LoongArch::FeatureLAM_BH, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
93 { sizeof(SubtargetFeatureKV) * 10 + 585, sizeof(SubtargetFeatureKV) * 10 + 592, LoongArch::FeatureLAMCAS, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
94 { sizeof(SubtargetFeatureKV) * 9 + 621, sizeof(SubtargetFeatureKV) * 9 + 626, LoongArch::FeatureExtLASX, { { { 0x100ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
95 { sizeof(SubtargetFeatureKV) * 8 + 668, sizeof(SubtargetFeatureKV) * 8 + 672, LoongArch::FeatureExtLBT, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
96 { sizeof(SubtargetFeatureKV) * 7 + 718, sizeof(SubtargetFeatureKV) * 7 + 728, LoongArch::FeatureLD_SEQ_SA, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
97 { sizeof(SubtargetFeatureKV) * 6 + 784, sizeof(SubtargetFeatureKV) * 6 + 788, LoongArch::FeatureExtLSX, { { { 0x8ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
98 { sizeof(SubtargetFeatureKV) * 5 + 820, sizeof(SubtargetFeatureKV) * 5 + 824, LoongArch::FeatureExtLVZ, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
99 { sizeof(SubtargetFeatureKV) * 4 + 866, sizeof(SubtargetFeatureKV) * 4 + 880, LoongArch::TunePreferWInst, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
100 { sizeof(SubtargetFeatureKV) * 3 + 914, sizeof(SubtargetFeatureKV) * 3 + 920, LoongArch::FeatureRelax, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
101 { sizeof(SubtargetFeatureKV) * 2 + 945, sizeof(SubtargetFeatureKV) * 2 + 949, LoongArch::FeatureSCQ, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
102 { sizeof(SubtargetFeatureKV) * 1 + 974, sizeof(SubtargetFeatureKV) * 1 + 978, LoongArch::FeatureUAL, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
103 },
104 "\000" "32bit\000LA32 Basic Integer and Privilege Instruction Set\000" ""
105 "32s\000LA32 Standard Basic Instruction Extension\000" "64bit\000LA64 Ba"
106 "sic Integer and Privilege Instruction Set\000d\000'D' (Double-Precision"
107 " Floating-Point)\000div32\000Assume div.w[u] and mod.w[u] can handle in"
108 "puts that are not sign-extended\000f\000'F' (Single-Precision Floating-"
109 "Point)\000frecipe\000Support frecipe.{s/d} and frsqrte.{s/d} instructio"
110 "ns\000la-global-with-abs\000Expand la.global as la.abs\000la-global-wit"
111 "h-pcrel\000Expand la.global as la.pcrel\000la-local-with-abs\000Expand "
112 "la.local as la.abs\000lam-bh\000Support amswap[_db].{b/h} and amadd[_db"
113 "].{b/h} instructions\000lamcas\000Support amcas[_db].{b/h/w/d}\000lasx\000"
114 "'LASX' (Loongson Advanced SIMD Extension)\000lbt\000'LBT' (Loongson Bin"
115 "ary Translation Extension)\000ld-seq-sa\000Don't use a same-address loa"
116 "d-load barrier (dbar 0x700)\000lsx\000'LSX' (Loongson SIMD Extension)\000"
117 "lvz\000'LVZ' (Loongson Virtualization Extension)\000prefer-w-inst\000Pr"
118 "efer instructions with W suffix\000relax\000Enable Linker relaxation\000"
119 "scq\000Support sc.q instruction\000ual\000Allow memory accesses to be u"
120 "naligned\000"};
121
122#ifdef DBGFIELD
123#error "<target>GenSubtargetInfo.inc requires a DBGFIELD macro"
124#endif
125#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
126#define DBGFIELD(x) x,
127#define DBGVAL_OR_NULLPTR(x) x
128#else
129#define DBGFIELD(x)
130#define DBGVAL_OR_NULLPTR(x) nullptr
131#endif
132
133// ===============================================================
134// Data tables for the new per-operand machine model.
135
136static_assert(0 <= UINT8_MAX, "NumWriteProcResEntries does not fit in uint8_t");
137static_assert(0 <= UINT8_MAX, "NumWriteLatencyEntries does not fit in uint8_t");
138
139// {ProcResourceIdx, ReleaseAtCycle, AcquireAtCycle}
140extern const llvm::MCWriteProcResEntry LoongArchWriteProcResTable[] = {
141 { 0, 0, 0 }, // Invalid
142}; // LoongArchWriteProcResTable
143
144// {Cycles, WriteResourceID}
145extern const llvm::MCWriteLatencyEntry LoongArchWriteLatencyTable[] = {
146 { 0, 0}, // Invalid
147}; // LoongArchWriteLatencyTable
148
149// {UseIdx, WriteResourceID, Cycles}
150extern const llvm::MCReadAdvanceEntry LoongArchReadAdvanceTable[] = {
151 {0, 0, 0}, // Invalid
152}; // LoongArchReadAdvanceTable
153
154#ifdef __GNUC__
155#pragma GCC diagnostic push
156#pragma GCC diagnostic ignored "-Woverlength-strings"
157#endif
158static constexpr char LoongArchSchedClassNamesStorage[] =
159 "\0"
160 "InvalidSchedClass\0"
161 ;
162#ifdef __GNUC__
163#pragma GCC diagnostic pop
164#endif
165
166static constexpr llvm::StringTable
167LoongArchSchedClassNames = LoongArchSchedClassNamesStorage;
168
169extern const llvm::MCSchedModel LoongArchSchedModels[] = {
170{ // NoSchedModel
171 MCSchedModel::DefaultIssueWidth,
172 MCSchedModel::DefaultMicroOpBufferSize,
173 MCSchedModel::DefaultLoopMicroOpBufferSize,
174 MCSchedModel::DefaultLoadLatency,
175 MCSchedModel::DefaultHighLatency,
176 MCSchedModel::DefaultMispredictPenalty,
177 false, // PostRAScheduler
178 false, // CompleteModel
179 false, // EnableIntervals
180 0, // Processor ID
181 nullptr, nullptr, 0, 0, // No instruction-level machine model.
182 DBGVAL_OR_NULLPTR(&LoongArchSchedClassNames), // SchedClassNames
183 nullptr, // No Itinerary
184 nullptr // No extra processor descriptor
185 },
186};
187
188#undef DBGFIELD
189
190#undef DBGVAL_OR_NULLPTR
191
192static constexpr size_t LoongArchCPUAliasArraySize = sizeof(std::array<SubtargetSubTypeAliasKV, 0>);
193// Sorted (by key) array of values for CPU subtype.
194extern const llvm::SubtargetSubTypeKVStorage< 7, 0, 72> LoongArchSubTypeKVStorage = {
195 {
196 { sizeof(SubtargetSubTypeKV) * 7 + LoongArchCPUAliasArraySize + 1, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
197 { sizeof(SubtargetSubTypeKV) * 6 + LoongArchCPUAliasArraySize + 9, { { { 0x1ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
198 { sizeof(SubtargetSubTypeKV) * 5 + LoongArchCPUAliasArraySize + 22, { { { 0x10104ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
199 { sizeof(SubtargetSubTypeKV) * 4 + LoongArchCPUAliasArraySize + 35, { { { 0x102c4ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
200 { sizeof(SubtargetSubTypeKV) * 3 + LoongArchCPUAliasArraySize + 41, { { { 0x1bee4ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
201 { sizeof(SubtargetSubTypeKV) * 2 + LoongArchCPUAliasArraySize + 47, { { { 0x1ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
202 { sizeof(SubtargetSubTypeKV) * 1 + LoongArchCPUAliasArraySize + 59, { { { 0x1000cULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
203 },
204 { {
205 } },
206 "\000generic\000generic-la32\000generic-la64\000la464\000la664\000loonga"
207 "rch32\000loongarch64\000"};
208
209namespace LoongArch_MC {
210
211unsigned resolveVariantSchedClassImpl(unsigned SchedClass,
212 const MCInst *MI, const MCInstrInfo *MCII, const MCSubtargetInfo &STI, unsigned CPUID) {
213 // Don't know how to resolve this scheduling class.
214 return 0;
215}
216
217} // namespace LoongArch_MC
218struct LoongArchGenMCSubtargetInfo : public MCSubtargetInfo {
219 LoongArchGenMCSubtargetInfo(const Triple &TT,
220 StringRef CPU, StringRef TuneCPU, StringRef FS,
221 StringTable PN,
222 ArrayRef<SubtargetFeatureKV> PF,
223 ArrayRef<SubtargetSubTypeKV> PD,
224 ArrayRef<SubtargetSubTypeAliasKV> PA,
225 const MCSchedModel *PSM,
226 const MCWriteProcResEntry *WPR,
227 const MCWriteLatencyEntry *WL,
228 const MCReadAdvanceEntry *RA, const InstrStage *IS,
229 const unsigned *OC, const unsigned *FP) :
230 MCSubtargetInfo(TT, CPU, TuneCPU, FS, PN, PF, PD, PA, PSM,
231 WPR, WL, RA, IS, OC, FP) { }
232
233 unsigned resolveVariantSchedClass(unsigned SchedClass,
234 const MCInst *MI, const MCInstrInfo *MCII,
235 unsigned CPUID) const final {
236 return LoongArch_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, *this, CPUID);
237 }
238 unsigned getHwModeSet() const final;
239 unsigned getHwMode(enum HwModeType type = HwMode_Default) const final;
240};
241unsigned LoongArchGenMCSubtargetInfo::getHwModeSet() const {
242 [[maybe_unused]] const FeatureBitset &FB = getFeatureBits();
243 // Collect HwModes and store them as a bit set.
244 unsigned Modes = 0;
245 if (FB[LoongArch::Feature64Bit]) Modes |= (1 << 0);
246 return Modes;
247}
248unsigned LoongArchGenMCSubtargetInfo::getHwMode(enum HwModeType type) const {
249 unsigned Modes = getHwModeSet();
250
251 if (!Modes)
252 return Modes;
253
254 switch (type) {
255 case HwMode_Default:
256 return llvm::countr_zero(Modes) + 1;
257 case HwMode_ValueType:
258 Modes &= 1;
259 if (!Modes)
260 return Modes;
261 if (!llvm::has_single_bit<unsigned>(Modes))
262 llvm_unreachable("Two or more HwModes for ValueType were found!");
263 return llvm::countr_zero(Modes) + 1;
264 case HwMode_RegInfo:
265 Modes &= 1;
266 if (!Modes)
267 return Modes;
268 if (!llvm::has_single_bit<unsigned>(Modes))
269 llvm_unreachable("Two or more HwModes for RegInfo were found!");
270 return llvm::countr_zero(Modes) + 1;
271 case HwMode_EncodingInfo:
272 // No HwMode for EncodingInfo.
273 return 0;
274 }
275 llvm_unreachable("unexpected HwModeType");
276 return 0; // should not get here
277}
278
279static inline MCSubtargetInfo *createLoongArchMCSubtargetInfoImpl(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS) {
280 return new LoongArchGenMCSubtargetInfo(TT, CPU, TuneCPU, FS, StringTable(LoongArchSubTypeKVStorage.Strings), LoongArchFeatureKVStorage.Features, LoongArchSubTypeKVStorage.SubTypes, ArrayRef(LoongArchSubTypeKVStorage.Aliases).take_front(0), LoongArchSchedModels,
281 LoongArchWriteProcResTable, LoongArchWriteLatencyTable, LoongArchReadAdvanceTable,
282 nullptr, nullptr, nullptr);
283}
284
285
286} // namespace llvm
287
288#endif // GET_SUBTARGETINFO_MC_DESC
289
290#ifdef GET_SUBTARGETINFO_TARGET_DESC
291#undef GET_SUBTARGETINFO_TARGET_DESC
292
293#include "llvm/ADT/BitmaskEnum.h"
294#include "llvm/Support/Debug.h"
295#include "llvm/Support/raw_ostream.h"
296
297// ParseSubtargetFeatures - Parses features string setting specified
298// subtarget options.
299void llvm::LoongArchSubtarget::ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS) {
300 LLVM_DEBUG(dbgs() << "\nFeatures:" << FS);
301 LLVM_DEBUG(dbgs() << "\nCPU:" << CPU);
302 LLVM_DEBUG(dbgs() << "\nTuneCPU:" << TuneCPU << "\n\n");
303 InitMCProcessorInfo(CPU, TuneCPU, FS);
304 const FeatureBitset &Bits = getFeatureBits();
305 if (Bits[LoongArch::Feature32Bit]) HasLA32 = true;
306 if (Bits[LoongArch::Feature32S]) Has32S = true;
307 if (Bits[LoongArch::Feature64Bit]) HasLA64 = true;
308 if (Bits[LoongArch::FeatureBasicD]) HasBasicD = true;
309 if (Bits[LoongArch::FeatureBasicF]) HasBasicF = true;
310 if (Bits[LoongArch::FeatureDiv32]) HasDiv32 = true;
311 if (Bits[LoongArch::FeatureExtLASX]) HasExtLASX = true;
312 if (Bits[LoongArch::FeatureExtLBT]) HasExtLBT = true;
313 if (Bits[LoongArch::FeatureExtLSX]) HasExtLSX = true;
314 if (Bits[LoongArch::FeatureExtLVZ]) HasExtLVZ = true;
315 if (Bits[LoongArch::FeatureFrecipe]) HasFrecipe = true;
316 if (Bits[LoongArch::FeatureLAMCAS]) HasLAMCAS = true;
317 if (Bits[LoongArch::FeatureLAM_BH]) HasLAM_BH = true;
318 if (Bits[LoongArch::FeatureLD_SEQ_SA]) HasLD_SEQ_SA = true;
319 if (Bits[LoongArch::FeatureRelax]) HasLinkerRelax = true;
320 if (Bits[LoongArch::FeatureSCQ]) HasSCQ = true;
321 if (Bits[LoongArch::FeatureUAL]) HasUAL = true;
322 if (Bits[LoongArch::LaGlobalWithAbs]) HasLaGlobalWithAbs = true;
323 if (Bits[LoongArch::LaGlobalWithPcrel]) HasLaGlobalWithPcrel = true;
324 if (Bits[LoongArch::LaLocalWithAbs]) HasLaLocalWithAbs = true;
325 if (Bits[LoongArch::TunePreferWInst]) PreferWInst = true;
326}
327
328#endif // GET_SUBTARGETINFO_TARGET_DESC
329
330#ifdef GET_SUBTARGETINFO_HEADER
331#undef GET_SUBTARGETINFO_HEADER
332
333namespace llvm {
334
335class DFAPacketizer;
336namespace LoongArch_MC {
337
338unsigned resolveVariantSchedClassImpl(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, const MCSubtargetInfo &STI, unsigned CPUID);
339
340} // namespace LoongArch_MC
341struct LoongArchGenSubtargetInfo : public TargetSubtargetInfo {
342 explicit LoongArchGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS);
343public:
344 unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const final;
345 unsigned resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const final;
346 DFAPacketizer *createDFAPacketizer(const InstrItineraryData *IID) const;
347 enum class LoongArchHwModeBits : unsigned {
348 DefaultMode = 0,
349 LA64 = (1 << 0),
350
351 LLVM_MARK_AS_BITMASK_ENUM(/*LargestValue=*/LA64),
352 };
353 unsigned getHwModeSet() const final;
354 unsigned getHwMode(enum HwModeType type = HwMode_Default) const final;
355 const FeatureBitset &getInlineIgnoreFeatures() const override;
356 const FeatureBitset &getInlineInverseFeatures() const override;
357 const FeatureBitset &getInlineMustMatchFeatures() const override;
358};
359
360} // namespace llvm
361
362#endif // GET_SUBTARGETINFO_HEADER
363
364#ifdef GET_SUBTARGETINFO_CTOR
365#undef GET_SUBTARGETINFO_CTOR
366
367#include "llvm/CodeGen/TargetSchedule.h"
368
369namespace llvm {
370
371extern const llvm::StringRef LoongArchNames[];
372extern const llvm::SubtargetFeatureKVStorage<21, 1017> LoongArchFeatureKVStorage;
373extern const llvm::SubtargetSubTypeKVStorage<7, 0, 72> LoongArchSubTypeKVStorage;
374extern const llvm::MCSchedModel LoongArchSchedModels[];
375extern const llvm::MCWriteProcResEntry LoongArchWriteProcResTable[];
376extern const llvm::MCWriteLatencyEntry LoongArchWriteLatencyTable[];
377extern const llvm::MCReadAdvanceEntry LoongArchReadAdvanceTable[];
378LoongArchGenSubtargetInfo::LoongArchGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS)
379 : TargetSubtargetInfo(TT, CPU, TuneCPU, FS, StringTable(LoongArchSubTypeKVStorage.Strings), ArrayRef(LoongArchFeatureKVStorage.Features), ArrayRef(LoongArchSubTypeKVStorage.SubTypes), ArrayRef(LoongArchSubTypeKVStorage.Aliases).take_front(0), LoongArchSchedModels,
380 LoongArchWriteProcResTable, LoongArchWriteLatencyTable, LoongArchReadAdvanceTable,
381 nullptr, nullptr, nullptr) {}
382
383unsigned LoongArchGenSubtargetInfo
384::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const {
385 report_fatal_error("Expected a variant SchedClass");
386} // LoongArchGenSubtargetInfo::resolveSchedClass
387
388unsigned LoongArchGenSubtargetInfo
389::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const {
390 return LoongArch_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, *this, CPUID);
391} // LoongArchGenSubtargetInfo::resolveVariantSchedClass
392
393unsigned LoongArchGenSubtargetInfo::getHwModeSet() const {
394 [[maybe_unused]] const auto *Subtarget =
395 static_cast<const LoongArchSubtarget *>(this);
396 // Collect HwModes and store them as a bit set.
397 unsigned Modes = 0;
398 if ((Subtarget->is64Bit())) Modes |= (1 << 0);
399 return Modes;
400}
401unsigned LoongArchGenSubtargetInfo::getHwMode(enum HwModeType type) const {
402 unsigned Modes = getHwModeSet();
403
404 if (!Modes)
405 return Modes;
406
407 switch (type) {
408 case HwMode_Default:
409 return llvm::countr_zero(Modes) + 1;
410 case HwMode_ValueType:
411 Modes &= 1;
412 if (!Modes)
413 return Modes;
414 if (!llvm::has_single_bit<unsigned>(Modes))
415 llvm_unreachable("Two or more HwModes for ValueType were found!");
416 return llvm::countr_zero(Modes) + 1;
417 case HwMode_RegInfo:
418 Modes &= 1;
419 if (!Modes)
420 return Modes;
421 if (!llvm::has_single_bit<unsigned>(Modes))
422 llvm_unreachable("Two or more HwModes for RegInfo were found!");
423 return llvm::countr_zero(Modes) + 1;
424 case HwMode_EncodingInfo:
425 // No HwMode for EncodingInfo.
426 return 0;
427 }
428 llvm_unreachable("unexpected HwModeType");
429 return 0; // should not get here
430}
431const FeatureBitset &LoongArchGenSubtargetInfo::getInlineIgnoreFeatures() const {
432 static constexpr FeatureBitset Features = {
433 };
434 return Features;
435}
436
437const FeatureBitset &LoongArchGenSubtargetInfo::getInlineInverseFeatures() const {
438 static constexpr FeatureBitset Features = {
439 };
440 return Features;
441}
442
443const FeatureBitset &LoongArchGenSubtargetInfo::getInlineMustMatchFeatures() const {
444 static constexpr FeatureBitset Features = {
445 };
446 return Features;
447}
448
449
450} // namespace llvm
451
452#endif // GET_SUBTARGETINFO_CTOR
453
454#ifdef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
455#undef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
456
457
458#endif // GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
459
460#ifdef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
461#undef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
462
463
464#endif // GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
465
466