1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Subtarget Enumeration Source Fragment *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_SUBTARGETINFO_ENUM
10#undef GET_SUBTARGETINFO_ENUM
11
12namespace llvm {
13
14namespace LoongArch {
15
16enum {
17 Feature32Bit = 0,
18 Feature32S = 1,
19 Feature64Bit = 2,
20 FeatureBasicD = 3,
21 FeatureBasicF = 4,
22 FeatureDiv32 = 5,
23 FeatureExtLASX = 6,
24 FeatureExtLBT = 7,
25 FeatureExtLSX = 8,
26 FeatureExtLVZ = 9,
27 FeatureFrecipe = 10,
28 FeatureLAMCAS = 11,
29 FeatureLAM_BH = 12,
30 FeatureLD_SEQ_SA = 13,
31 FeatureRelax = 14,
32 FeatureSCQ = 15,
33 FeatureUAL = 16,
34 LaGlobalWithAbs = 17,
35 LaGlobalWithPcrel = 18,
36 LaLocalWithAbs = 19,
37 TunePreferWInst = 20,
38 NumSubtargetFeatures = 21
39};
40
41} // namespace LoongArch
42
43} // namespace llvm
44
45#endif // GET_SUBTARGETINFO_ENUM
46
47#ifdef GET_SUBTARGETINFO_MACRO
48
49GET_SUBTARGETINFO_MACRO(Has32S, false, has32S)
50GET_SUBTARGETINFO_MACRO(HasBasicD, false, hasBasicD)
51GET_SUBTARGETINFO_MACRO(HasBasicF, false, hasBasicF)
52GET_SUBTARGETINFO_MACRO(HasDiv32, false, hasDiv32)
53GET_SUBTARGETINFO_MACRO(HasExtLASX, false, hasExtLASX)
54GET_SUBTARGETINFO_MACRO(HasExtLBT, false, hasExtLBT)
55GET_SUBTARGETINFO_MACRO(HasExtLSX, false, hasExtLSX)
56GET_SUBTARGETINFO_MACRO(HasExtLVZ, false, hasExtLVZ)
57GET_SUBTARGETINFO_MACRO(HasFrecipe, false, hasFrecipe)
58GET_SUBTARGETINFO_MACRO(HasLA32, false, hasLA32)
59GET_SUBTARGETINFO_MACRO(HasLA64, false, hasLA64)
60GET_SUBTARGETINFO_MACRO(HasLAMCAS, false, hasLAMCAS)
61GET_SUBTARGETINFO_MACRO(HasLAM_BH, false, hasLAM_BH)
62GET_SUBTARGETINFO_MACRO(HasLD_SEQ_SA, false, hasLD_SEQ_SA)
63GET_SUBTARGETINFO_MACRO(HasLaGlobalWithAbs, false, hasLaGlobalWithAbs)
64GET_SUBTARGETINFO_MACRO(HasLaGlobalWithPcrel, false, hasLaGlobalWithPcrel)
65GET_SUBTARGETINFO_MACRO(HasLaLocalWithAbs, false, hasLaLocalWithAbs)
66GET_SUBTARGETINFO_MACRO(HasLinkerRelax, false, hasLinkerRelax)
67GET_SUBTARGETINFO_MACRO(HasSCQ, false, hasSCQ)
68GET_SUBTARGETINFO_MACRO(HasUAL, false, hasUAL)
69GET_SUBTARGETINFO_MACRO(PreferWInst, false, preferWInst)
70
71#undef GET_SUBTARGETINFO_MACRO
72#endif // GET_SUBTARGETINFO_MACRO
73
74#ifdef GET_SUBTARGETINFO_MC_DESC
75#undef GET_SUBTARGETINFO_MC_DESC
76
77namespace llvm {
78
79// Sorted (by key) array of values for CPU features.
80extern const llvm::SubtargetFeatureKV LoongArchFeatureKV[] = {
81 { "32bit", "LA32 Basic Integer and Privilege Instruction Set", LoongArch::Feature32Bit, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
82 { "32s", "LA32 Standard Basic Instruction Extension", LoongArch::Feature32S, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
83 { "64bit", "LA64 Basic Integer and Privilege Instruction Set", LoongArch::Feature64Bit, { { { 0x2ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
84 { "d", "'D' (Double-Precision Floating-Point)", LoongArch::FeatureBasicD, { { { 0x10ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
85 { "div32", "Assume div.w[u] and mod.w[u] can handle inputs that are not sign-extended", LoongArch::FeatureDiv32, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
86 { "f", "'F' (Single-Precision Floating-Point)", LoongArch::FeatureBasicF, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
87 { "frecipe", "Support frecipe.{s/d} and frsqrte.{s/d} instructions", LoongArch::FeatureFrecipe, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
88 { "la-global-with-abs", "Expand la.global as la.abs", LoongArch::LaGlobalWithAbs, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
89 { "la-global-with-pcrel", "Expand la.global as la.pcrel", LoongArch::LaGlobalWithPcrel, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
90 { "la-local-with-abs", "Expand la.local as la.abs", LoongArch::LaLocalWithAbs, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
91 { "lam-bh", "Support amswap[_db].{b/h} and amadd[_db].{b/h} instructions", LoongArch::FeatureLAM_BH, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
92 { "lamcas", "Support amcas[_db].{b/h/w/d}", LoongArch::FeatureLAMCAS, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
93 { "lasx", "'LASX' (Loongson Advanced SIMD Extension)", LoongArch::FeatureExtLASX, { { { 0x100ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
94 { "lbt", "'LBT' (Loongson Binary Translation Extension)", LoongArch::FeatureExtLBT, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
95 { "ld-seq-sa", "Don't use a same-address load-load barrier (dbar 0x700)", LoongArch::FeatureLD_SEQ_SA, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
96 { "lsx", "'LSX' (Loongson SIMD Extension)", LoongArch::FeatureExtLSX, { { { 0x8ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
97 { "lvz", "'LVZ' (Loongson Virtualization Extension)", LoongArch::FeatureExtLVZ, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
98 { "prefer-w-inst", "Prefer instructions with W suffix", LoongArch::TunePreferWInst, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
99 { "relax", "Enable Linker relaxation", LoongArch::FeatureRelax, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
100 { "scq", "Support sc.q instruction", LoongArch::FeatureSCQ, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
101 { "ual", "Allow memory accesses to be unaligned", LoongArch::FeatureUAL, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
102};
103
104#ifdef DBGFIELD
105#error "<target>GenSubtargetInfo.inc requires a DBGFIELD macro"
106#endif
107#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
108#define DBGFIELD(x) x,
109#define DBGVAL_OR_NULLPTR(x) x
110#else
111#define DBGFIELD(x)
112#define DBGVAL_OR_NULLPTR(x) nullptr
113#endif
114
115// ===============================================================
116// Data tables for the new per-operand machine model.
117
118// {ProcResourceIdx, ReleaseAtCycle, AcquireAtCycle}
119extern const llvm::MCWriteProcResEntry LoongArchWriteProcResTable[] = {
120 { 0, 0, 0 }, // Invalid
121}; // LoongArchWriteProcResTable
122
123// {Cycles, WriteResourceID}
124extern const llvm::MCWriteLatencyEntry LoongArchWriteLatencyTable[] = {
125 { 0, 0}, // Invalid
126}; // LoongArchWriteLatencyTable
127
128// {UseIdx, WriteResourceID, Cycles}
129extern const llvm::MCReadAdvanceEntry LoongArchReadAdvanceTable[] = {
130 {0, 0, 0}, // Invalid
131}; // LoongArchReadAdvanceTable
132
133#ifdef __GNUC__
134#pragma GCC diagnostic push
135#pragma GCC diagnostic ignored "-Woverlength-strings"
136#endif
137static constexpr char LoongArchSchedClassNamesStorage[] =
138 "\0"
139 "InvalidSchedClass\0"
140 ;
141#ifdef __GNUC__
142#pragma GCC diagnostic pop
143#endif
144
145static constexpr llvm::StringTable
146LoongArchSchedClassNames = LoongArchSchedClassNamesStorage;
147
148static const llvm::MCSchedModel NoSchedModel = {
149 MCSchedModel::DefaultIssueWidth,
150 MCSchedModel::DefaultMicroOpBufferSize,
151 MCSchedModel::DefaultLoopMicroOpBufferSize,
152 MCSchedModel::DefaultLoadLatency,
153 MCSchedModel::DefaultHighLatency,
154 MCSchedModel::DefaultMispredictPenalty,
155 false, // PostRAScheduler
156 false, // CompleteModel
157 false, // EnableIntervals
158 0, // Processor ID
159 nullptr, nullptr, 0, 0, // No instruction-level machine model.
160 DBGVAL_OR_NULLPTR(&LoongArchSchedClassNames), // SchedClassNames
161 nullptr, // No Itinerary
162 nullptr // No extra processor descriptor
163};
164
165#undef DBGFIELD
166
167#undef DBGVAL_OR_NULLPTR
168
169// Sorted (by key) array of values for CPU subtype.
170extern const llvm::SubtargetSubTypeKV LoongArchSubTypeKV[] = {
171 { "generic", { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
172 { "generic-la32", { { { 0x1ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
173 { "generic-la64", { { { 0x10104ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
174 { "la464", { { { 0x102c4ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
175 { "la664", { { { 0x1bee4ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
176 { "loongarch32", { { { 0x1ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
177 { "loongarch64", { { { 0x1000cULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
178};
179
180// Sorted array of names of CPU subtypes, including aliases.
181extern const llvm::StringRef LoongArchNames[] = {
182"generic",
183"generic-la32",
184"generic-la64",
185"la464",
186"la664",
187"loongarch32",
188"loongarch64"};
189
190namespace LoongArch_MC {
191
192unsigned resolveVariantSchedClassImpl(unsigned SchedClass,
193 const MCInst *MI, const MCInstrInfo *MCII, const MCSubtargetInfo &STI, unsigned CPUID) {
194 // Don't know how to resolve this scheduling class.
195 return 0;
196}
197
198} // namespace LoongArch_MC
199struct LoongArchGenMCSubtargetInfo : public MCSubtargetInfo {
200 LoongArchGenMCSubtargetInfo(const Triple &TT,
201 StringRef CPU, StringRef TuneCPU, StringRef FS,
202 ArrayRef<StringRef> PN,
203 ArrayRef<SubtargetFeatureKV> PF,
204 ArrayRef<SubtargetSubTypeKV> PD,
205 const MCWriteProcResEntry *WPR,
206 const MCWriteLatencyEntry *WL,
207 const MCReadAdvanceEntry *RA, const InstrStage *IS,
208 const unsigned *OC, const unsigned *FP) :
209 MCSubtargetInfo(TT, CPU, TuneCPU, FS, PN, PF, PD,
210 WPR, WL, RA, IS, OC, FP) { }
211
212 unsigned resolveVariantSchedClass(unsigned SchedClass,
213 const MCInst *MI, const MCInstrInfo *MCII,
214 unsigned CPUID) const final {
215 return LoongArch_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, *this, CPUID);
216 }
217 unsigned getHwModeSet() const final;
218 unsigned getHwMode(enum HwModeType type = HwMode_Default) const final;
219};
220unsigned LoongArchGenMCSubtargetInfo::getHwModeSet() const {
221 [[maybe_unused]] const FeatureBitset &FB = getFeatureBits();
222 // Collect HwModes and store them as a bit set.
223 unsigned Modes = 0;
224 if (FB[LoongArch::Feature64Bit]) Modes |= (1 << 0);
225 return Modes;
226}
227unsigned LoongArchGenMCSubtargetInfo::getHwMode(enum HwModeType type) const {
228 unsigned Modes = getHwModeSet();
229
230 if (!Modes)
231 return Modes;
232
233 switch (type) {
234 case HwMode_Default:
235 return llvm::countr_zero(Modes) + 1;
236 case HwMode_ValueType:
237 Modes &= 1;
238 if (!Modes)
239 return Modes;
240 if (!llvm::has_single_bit<unsigned>(Modes))
241 llvm_unreachable("Two or more HwModes for ValueType were found!");
242 return llvm::countr_zero(Modes) + 1;
243 case HwMode_RegInfo:
244 Modes &= 1;
245 if (!Modes)
246 return Modes;
247 if (!llvm::has_single_bit<unsigned>(Modes))
248 llvm_unreachable("Two or more HwModes for RegInfo were found!");
249 return llvm::countr_zero(Modes) + 1;
250 case HwMode_EncodingInfo:
251 Modes &= 0;
252 if (!Modes)
253 return Modes;
254 if (!llvm::has_single_bit<unsigned>(Modes))
255 llvm_unreachable("Two or more HwModes for EncodingInfo were found!");
256 return llvm::countr_zero(Modes) + 1;
257 }
258 llvm_unreachable("unexpected HwModeType");
259 return 0; // should not get here
260}
261
262static inline MCSubtargetInfo *createLoongArchMCSubtargetInfoImpl(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS) {
263 return new LoongArchGenMCSubtargetInfo(TT, CPU, TuneCPU, FS, LoongArchNames, LoongArchFeatureKV, LoongArchSubTypeKV,
264 LoongArchWriteProcResTable, LoongArchWriteLatencyTable, LoongArchReadAdvanceTable,
265 nullptr, nullptr, nullptr);
266}
267
268
269} // namespace llvm
270
271#endif // GET_SUBTARGETINFO_MC_DESC
272
273#ifdef GET_SUBTARGETINFO_TARGET_DESC
274#undef GET_SUBTARGETINFO_TARGET_DESC
275
276#include "llvm/ADT/BitmaskEnum.h"
277#include "llvm/Support/Debug.h"
278#include "llvm/Support/raw_ostream.h"
279
280// ParseSubtargetFeatures - Parses features string setting specified
281// subtarget options.
282void llvm::LoongArchSubtarget::ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS) {
283 LLVM_DEBUG(dbgs() << "\nFeatures:" << FS);
284 LLVM_DEBUG(dbgs() << "\nCPU:" << CPU);
285 LLVM_DEBUG(dbgs() << "\nTuneCPU:" << TuneCPU << "\n\n");
286 InitMCProcessorInfo(CPU, TuneCPU, FS);
287 const FeatureBitset &Bits = getFeatureBits();
288 if (Bits[LoongArch::Feature32Bit]) HasLA32 = true;
289 if (Bits[LoongArch::Feature32S]) Has32S = true;
290 if (Bits[LoongArch::Feature64Bit]) HasLA64 = true;
291 if (Bits[LoongArch::FeatureBasicD]) HasBasicD = true;
292 if (Bits[LoongArch::FeatureBasicF]) HasBasicF = true;
293 if (Bits[LoongArch::FeatureDiv32]) HasDiv32 = true;
294 if (Bits[LoongArch::FeatureExtLASX]) HasExtLASX = true;
295 if (Bits[LoongArch::FeatureExtLBT]) HasExtLBT = true;
296 if (Bits[LoongArch::FeatureExtLSX]) HasExtLSX = true;
297 if (Bits[LoongArch::FeatureExtLVZ]) HasExtLVZ = true;
298 if (Bits[LoongArch::FeatureFrecipe]) HasFrecipe = true;
299 if (Bits[LoongArch::FeatureLAMCAS]) HasLAMCAS = true;
300 if (Bits[LoongArch::FeatureLAM_BH]) HasLAM_BH = true;
301 if (Bits[LoongArch::FeatureLD_SEQ_SA]) HasLD_SEQ_SA = true;
302 if (Bits[LoongArch::FeatureRelax]) HasLinkerRelax = true;
303 if (Bits[LoongArch::FeatureSCQ]) HasSCQ = true;
304 if (Bits[LoongArch::FeatureUAL]) HasUAL = true;
305 if (Bits[LoongArch::LaGlobalWithAbs]) HasLaGlobalWithAbs = true;
306 if (Bits[LoongArch::LaGlobalWithPcrel]) HasLaGlobalWithPcrel = true;
307 if (Bits[LoongArch::LaLocalWithAbs]) HasLaLocalWithAbs = true;
308 if (Bits[LoongArch::TunePreferWInst]) PreferWInst = true;
309}
310
311#endif // GET_SUBTARGETINFO_TARGET_DESC
312
313#ifdef GET_SUBTARGETINFO_HEADER
314#undef GET_SUBTARGETINFO_HEADER
315
316namespace llvm {
317
318class DFAPacketizer;
319namespace LoongArch_MC {
320
321unsigned resolveVariantSchedClassImpl(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, const MCSubtargetInfo &STI, unsigned CPUID);
322
323} // namespace LoongArch_MC
324struct LoongArchGenSubtargetInfo : public TargetSubtargetInfo {
325 explicit LoongArchGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS);
326public:
327 unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const final;
328 unsigned resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const final;
329 DFAPacketizer *createDFAPacketizer(const InstrItineraryData *IID) const;
330 enum class LoongArchHwModeBits : unsigned {
331 DefaultMode = 0,
332 LA64 = (1 << 0),
333
334 LLVM_MARK_AS_BITMASK_ENUM(/*LargestValue=*/LA64),
335 };
336 unsigned getHwModeSet() const final;
337 unsigned getHwMode(enum HwModeType type = HwMode_Default) const final;
338};
339
340} // namespace llvm
341
342#endif // GET_SUBTARGETINFO_HEADER
343
344#ifdef GET_SUBTARGETINFO_CTOR
345#undef GET_SUBTARGETINFO_CTOR
346
347#include "llvm/CodeGen/TargetSchedule.h"
348
349namespace llvm {
350
351extern const llvm::StringRef LoongArchNames[];
352extern const llvm::SubtargetFeatureKV LoongArchFeatureKV[];
353extern const llvm::SubtargetSubTypeKV LoongArchSubTypeKV[];
354extern const llvm::MCWriteProcResEntry LoongArchWriteProcResTable[];
355extern const llvm::MCWriteLatencyEntry LoongArchWriteLatencyTable[];
356extern const llvm::MCReadAdvanceEntry LoongArchReadAdvanceTable[];
357LoongArchGenSubtargetInfo::LoongArchGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS)
358 : TargetSubtargetInfo(TT, CPU, TuneCPU, FS, ArrayRef(LoongArchNames, 7), ArrayRef(LoongArchFeatureKV, 21), ArrayRef(LoongArchSubTypeKV, 7),
359 LoongArchWriteProcResTable, LoongArchWriteLatencyTable, LoongArchReadAdvanceTable,
360 nullptr, nullptr, nullptr) {}
361
362unsigned LoongArchGenSubtargetInfo
363::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const {
364 report_fatal_error("Expected a variant SchedClass");
365} // LoongArchGenSubtargetInfo::resolveSchedClass
366
367unsigned LoongArchGenSubtargetInfo
368::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const {
369 return LoongArch_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, *this, CPUID);
370} // LoongArchGenSubtargetInfo::resolveVariantSchedClass
371
372unsigned LoongArchGenSubtargetInfo::getHwModeSet() const {
373 [[maybe_unused]] const auto *Subtarget =
374 static_cast<const LoongArchSubtarget *>(this);
375 // Collect HwModes and store them as a bit set.
376 unsigned Modes = 0;
377 if ((Subtarget->is64Bit())) Modes |= (1 << 0);
378 return Modes;
379}
380unsigned LoongArchGenSubtargetInfo::getHwMode(enum HwModeType type) const {
381 unsigned Modes = getHwModeSet();
382
383 if (!Modes)
384 return Modes;
385
386 switch (type) {
387 case HwMode_Default:
388 return llvm::countr_zero(Modes) + 1;
389 case HwMode_ValueType:
390 Modes &= 1;
391 if (!Modes)
392 return Modes;
393 if (!llvm::has_single_bit<unsigned>(Modes))
394 llvm_unreachable("Two or more HwModes for ValueType were found!");
395 return llvm::countr_zero(Modes) + 1;
396 case HwMode_RegInfo:
397 Modes &= 1;
398 if (!Modes)
399 return Modes;
400 if (!llvm::has_single_bit<unsigned>(Modes))
401 llvm_unreachable("Two or more HwModes for RegInfo were found!");
402 return llvm::countr_zero(Modes) + 1;
403 case HwMode_EncodingInfo:
404 Modes &= 0;
405 if (!Modes)
406 return Modes;
407 if (!llvm::has_single_bit<unsigned>(Modes))
408 llvm_unreachable("Two or more HwModes for EncodingInfo were found!");
409 return llvm::countr_zero(Modes) + 1;
410 }
411 llvm_unreachable("unexpected HwModeType");
412 return 0; // should not get here
413}
414
415} // namespace llvm
416
417#endif // GET_SUBTARGETINFO_CTOR
418
419#ifdef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
420#undef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
421
422
423#endif // GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
424
425#ifdef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
426#undef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
427
428
429#endif // GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
430
431