| 1 | /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
| 2 | |* *| |
| 3 | |* * MSP430 Disassembler *| |
| 4 | |* *| |
| 5 | |* Automatically generated file, do not edit! *| |
| 6 | |* *| |
| 7 | \*===----------------------------------------------------------------------===*/ |
| 8 | |
| 9 | |
| 10 | #include "llvm/MC/MCInst.h" |
| 11 | #include "llvm/MC/MCSubtargetInfo.h" |
| 12 | #include "llvm/Support/DataTypes.h" |
| 13 | #include "llvm/Support/Debug.h" |
| 14 | #include "llvm/Support/LEB128.h" |
| 15 | #include "llvm/Support/raw_ostream.h" |
| 16 | #include "llvm/TargetParser/SubtargetFeature.h" |
| 17 | #include <assert.h> |
| 18 | |
| 19 | namespace { |
| 20 | |
| 21 | // InsnBitWidth is essentially a type trait used by the decoder emitter to query |
| 22 | // the supported bitwidth for a given type. But default, the value is 0, making |
| 23 | // it an invalid type for use as `InsnType` when instantiating the decoder. |
| 24 | // Individual targets are expected to provide specializations for these based |
| 25 | // on their usage. |
| 26 | template <typename T> constexpr uint32_t InsnBitWidth = 0; |
| 27 | |
| 28 | static const uint8_t DecoderTable16[222] = { |
| 29 | OPC_SwitchField, 13, 3, // 0: switch Inst[15:13] { |
| 30 | 0, 200, 1, // 3: case 0x0: { |
| 31 | OPC_SwitchField, 6, 7, // 6: switch Inst[12:6] { |
| 32 | 64, 21, // 9: case 0x40: { |
| 33 | OPC_SwitchField, 4, 2, // 11: switch Inst[5:4] { |
| 34 | 0, 4, // 14: case 0x0: { |
| 35 | OPC_Decode, 186, 4, 0, // 16: decode to RRC16r using decoder 0 |
| 36 | // 16: } |
| 37 | 2, 4, // 20: case 0x2: { |
| 38 | OPC_Decode, 184, 4, 1, // 22: decode to RRC16n using decoder 1 |
| 39 | // 22: } |
| 40 | 3, 0, // 26: case 0x3: { |
| 41 | OPC_Decode, 185, 4, 1, // 28: decode to RRC16p using decoder 1 |
| 42 | // 28: } |
| 43 | // 28: } // switch Inst[5:4] |
| 44 | // 28: } |
| 45 | 65, 21, // 32: case 0x41: { |
| 46 | OPC_SwitchField, 4, 2, // 34: switch Inst[5:4] { |
| 47 | 0, 4, // 37: case 0x0: { |
| 48 | OPC_Decode, 190, 4, 2, // 39: decode to RRC8r using decoder 2 |
| 49 | // 39: } |
| 50 | 2, 4, // 43: case 0x2: { |
| 51 | OPC_Decode, 188, 4, 1, // 45: decode to RRC8n using decoder 1 |
| 52 | // 45: } |
| 53 | 3, 0, // 49: case 0x3: { |
| 54 | OPC_Decode, 189, 4, 1, // 51: decode to RRC8p using decoder 1 |
| 55 | // 51: } |
| 56 | // 51: } // switch Inst[5:4] |
| 57 | // 51: } |
| 58 | 66, 21, // 55: case 0x42: { |
| 59 | OPC_SwitchField, 4, 2, // 57: switch Inst[5:4] { |
| 60 | 0, 4, // 60: case 0x0: { |
| 61 | OPC_Decode, 248, 4, 0, // 62: decode to SWPB16r using decoder 0 |
| 62 | // 62: } |
| 63 | 2, 4, // 66: case 0x2: { |
| 64 | OPC_Decode, 246, 4, 1, // 68: decode to SWPB16n using decoder 1 |
| 65 | // 68: } |
| 66 | 3, 0, // 72: case 0x3: { |
| 67 | OPC_Decode, 247, 4, 1, // 74: decode to SWPB16p using decoder 1 |
| 68 | // 74: } |
| 69 | // 74: } // switch Inst[5:4] |
| 70 | // 74: } |
| 71 | 68, 21, // 78: case 0x44: { |
| 72 | OPC_SwitchField, 4, 2, // 80: switch Inst[5:4] { |
| 73 | 0, 4, // 83: case 0x0: { |
| 74 | OPC_Decode, 178, 4, 0, // 85: decode to RRA16r using decoder 0 |
| 75 | // 85: } |
| 76 | 2, 4, // 89: case 0x2: { |
| 77 | OPC_Decode, 176, 4, 1, // 91: decode to RRA16n using decoder 1 |
| 78 | // 91: } |
| 79 | 3, 0, // 95: case 0x3: { |
| 80 | OPC_Decode, 177, 4, 1, // 97: decode to RRA16p using decoder 1 |
| 81 | // 97: } |
| 82 | // 97: } // switch Inst[5:4] |
| 83 | // 97: } |
| 84 | 69, 21, // 101: case 0x45: { |
| 85 | OPC_SwitchField, 4, 2, // 103: switch Inst[5:4] { |
| 86 | 0, 4, // 106: case 0x0: { |
| 87 | OPC_Decode, 182, 4, 2, // 108: decode to RRA8r using decoder 2 |
| 88 | // 108: } |
| 89 | 2, 4, // 112: case 0x2: { |
| 90 | OPC_Decode, 180, 4, 1, // 114: decode to RRA8n using decoder 1 |
| 91 | // 114: } |
| 92 | 3, 0, // 118: case 0x3: { |
| 93 | OPC_Decode, 181, 4, 1, // 120: decode to RRA8p using decoder 1 |
| 94 | // 120: } |
| 95 | // 120: } // switch Inst[5:4] |
| 96 | // 120: } |
| 97 | 70, 21, // 124: case 0x46: { |
| 98 | OPC_SwitchField, 4, 2, // 126: switch Inst[5:4] { |
| 99 | 0, 4, // 129: case 0x0: { |
| 100 | OPC_Decode, 196, 4, 0, // 131: decode to SEXT16r using decoder 0 |
| 101 | // 131: } |
| 102 | 2, 4, // 135: case 0x2: { |
| 103 | OPC_Decode, 194, 4, 1, // 137: decode to SEXT16n using decoder 1 |
| 104 | // 137: } |
| 105 | 3, 0, // 141: case 0x3: { |
| 106 | OPC_Decode, 195, 4, 1, // 143: decode to SEXT16p using decoder 1 |
| 107 | // 143: } |
| 108 | // 143: } // switch Inst[5:4] |
| 109 | // 143: } |
| 110 | 72, 14, // 147: case 0x48: { |
| 111 | OPC_Scope, 8, // 149: try { |
| 112 | OPC_CheckField, 4, 2, 0, // 151: check Inst[5:4] == 0x0 |
| 113 | OPC_Decode, 171, 4, 1, // 155: decode to PUSH16r using decoder 1 |
| 114 | // 155: } else try { |
| 115 | OPC_Decode, 169, 4, 3, // 159: decode to PUSH16c using decoder 3 |
| 116 | // 159: } |
| 117 | // 159: } |
| 118 | 73, 8, // 163: case 0x49: { |
| 119 | OPC_CheckField, 4, 2, 0, // 165: check Inst[5:4] == 0x0 |
| 120 | OPC_Decode, 172, 4, 4, // 169: decode to PUSH8r using decoder 4 |
| 121 | // 169: } |
| 122 | 74, 21, // 173: case 0x4a: { |
| 123 | OPC_SwitchField, 4, 2, // 175: switch Inst[5:4] { |
| 124 | 0, 4, // 178: case 0x0: { |
| 125 | OPC_Decode, 221, 3, 1, // 180: decode to CALLr using decoder 1 |
| 126 | // 180: } |
| 127 | 2, 4, // 184: case 0x2: { |
| 128 | OPC_Decode, 219, 3, 1, // 186: decode to CALLn using decoder 1 |
| 129 | // 186: } |
| 130 | 3, 0, // 190: case 0x3: { |
| 131 | OPC_Decode, 220, 3, 1, // 192: decode to CALLp using decoder 1 |
| 132 | // 192: } |
| 133 | // 192: } // switch Inst[5:4] |
| 134 | // 192: } |
| 135 | 76, 0, // 196: case 0x4c: { |
| 136 | OPC_CheckField, 0, 6, 0, // 198: check Inst[5:0] == 0x0 |
| 137 | OPC_Decode, 174, 4, 5, // 202: decode to RETI using decoder 5 |
| 138 | // 202: } |
| 139 | // 202: } // switch Inst[12:6] |
| 140 | // 202: } |
| 141 | 1, 0, // 206: case 0x1: { |
| 142 | OPC_Scope, 8, // 208: try { |
| 143 | OPC_CheckField, 10, 3, 7, // 210: check Inst[12:10] == 0x7 |
| 144 | OPC_Decode, 143, 4, 6, // 214: decode to JMP using decoder 6 |
| 145 | // 214: } else try { |
| 146 | OPC_Decode, 142, 4, 7, // 218: decode to JCC using decoder 7 |
| 147 | // 218: } |
| 148 | // 218: } |
| 149 | // 218: } // switch Inst[15:13] |
| 150 | }; |
| 151 | static const uint8_t DecoderTableAlpha16[217] = { |
| 152 | OPC_SwitchField, 12, 4, // 0: switch Inst[15:12] { |
| 153 | 4, 25, // 3: case 0x4: { |
| 154 | OPC_SwitchField, 4, 4, // 5: switch Inst[7:4] { |
| 155 | 0, 14, // 8: case 0x0: { |
| 156 | OPC_Scope, 8, // 10: try { |
| 157 | OPC_CheckField, 0, 4, 0, // 12: check Inst[3:0] == 0x0 |
| 158 | OPC_Decode, 216, 3, 8, // 16: decode to Br using decoder 8 |
| 159 | // 16: } else try { |
| 160 | OPC_Decode, 154, 4, 9, // 20: decode to MOV16rr using decoder 9 |
| 161 | // 20: } |
| 162 | // 20: } |
| 163 | 4, 0, // 24: case 0x4: { |
| 164 | OPC_Decode, 165, 4, 10, // 26: decode to MOV8rr using decoder 10 |
| 165 | // 26: } |
| 166 | // 26: } // switch Inst[7:4] |
| 167 | // 26: } |
| 168 | 5, 15, // 30: case 0x5: { |
| 169 | OPC_SwitchField, 4, 4, // 32: switch Inst[7:4] { |
| 170 | 0, 4, // 35: case 0x0: { |
| 171 | OPC_Decode, 206, 2, 11, // 37: decode to ADD16rr using decoder 11 |
| 172 | // 37: } |
| 173 | 4, 0, // 41: case 0x4: { |
| 174 | OPC_Decode, 218, 2, 12, // 43: decode to ADD8rr using decoder 12 |
| 175 | // 43: } |
| 176 | // 43: } // switch Inst[7:4] |
| 177 | // 43: } |
| 178 | 6, 15, // 47: case 0x6: { |
| 179 | OPC_SwitchField, 4, 4, // 49: switch Inst[7:4] { |
| 180 | 0, 4, // 52: case 0x0: { |
| 181 | OPC_Decode, 230, 2, 11, // 54: decode to ADDC16rr using decoder 11 |
| 182 | // 54: } |
| 183 | 4, 0, // 58: case 0x4: { |
| 184 | OPC_Decode, 242, 2, 12, // 60: decode to ADDC8rr using decoder 12 |
| 185 | // 60: } |
| 186 | // 60: } // switch Inst[7:4] |
| 187 | // 60: } |
| 188 | 7, 15, // 64: case 0x7: { |
| 189 | OPC_SwitchField, 4, 4, // 66: switch Inst[7:4] { |
| 190 | 0, 4, // 69: case 0x0: { |
| 191 | OPC_Decode, 232, 4, 11, // 71: decode to SUBC16rr using decoder 11 |
| 192 | // 71: } |
| 193 | 4, 0, // 75: case 0x4: { |
| 194 | OPC_Decode, 244, 4, 12, // 77: decode to SUBC8rr using decoder 12 |
| 195 | // 77: } |
| 196 | // 77: } // switch Inst[7:4] |
| 197 | // 77: } |
| 198 | 8, 15, // 81: case 0x8: { |
| 199 | OPC_SwitchField, 4, 4, // 83: switch Inst[7:4] { |
| 200 | 0, 4, // 86: case 0x0: { |
| 201 | OPC_Decode, 208, 4, 11, // 88: decode to SUB16rr using decoder 11 |
| 202 | // 88: } |
| 203 | 4, 0, // 92: case 0x4: { |
| 204 | OPC_Decode, 220, 4, 12, // 94: decode to SUB8rr using decoder 12 |
| 205 | // 94: } |
| 206 | // 94: } // switch Inst[7:4] |
| 207 | // 94: } |
| 208 | 9, 15, // 98: case 0x9: { |
| 209 | OPC_SwitchField, 4, 4, // 100: switch Inst[7:4] { |
| 210 | 0, 4, // 103: case 0x0: { |
| 211 | OPC_Decode, 233, 3, 9, // 105: decode to CMP16rr using decoder 9 |
| 212 | // 105: } |
| 213 | 4, 0, // 109: case 0x4: { |
| 214 | OPC_Decode, 245, 3, 10, // 111: decode to CMP8rr using decoder 10 |
| 215 | // 111: } |
| 216 | // 111: } // switch Inst[7:4] |
| 217 | // 111: } |
| 218 | 10, 15, // 115: case 0xa: { |
| 219 | OPC_SwitchField, 4, 4, // 117: switch Inst[7:4] { |
| 220 | 0, 4, // 120: case 0x0: { |
| 221 | OPC_Decode, 129, 4, 11, // 122: decode to DADD16rr using decoder 11 |
| 222 | // 122: } |
| 223 | 4, 0, // 126: case 0x4: { |
| 224 | OPC_Decode, 141, 4, 12, // 128: decode to DADD8rr using decoder 12 |
| 225 | // 128: } |
| 226 | // 128: } // switch Inst[7:4] |
| 227 | // 128: } |
| 228 | 11, 15, // 132: case 0xb: { |
| 229 | OPC_SwitchField, 4, 4, // 134: switch Inst[7:4] { |
| 230 | 0, 4, // 137: case 0x0: { |
| 231 | OPC_Decode, 201, 3, 9, // 139: decode to BIT16rr using decoder 9 |
| 232 | // 139: } |
| 233 | 4, 0, // 143: case 0x4: { |
| 234 | OPC_Decode, 213, 3, 10, // 145: decode to BIT8rr using decoder 10 |
| 235 | // 145: } |
| 236 | // 145: } // switch Inst[7:4] |
| 237 | // 145: } |
| 238 | 12, 15, // 149: case 0xc: { |
| 239 | OPC_SwitchField, 4, 4, // 151: switch Inst[7:4] { |
| 240 | 0, 4, // 154: case 0x0: { |
| 241 | OPC_Decode, 153, 3, 11, // 156: decode to BIC16rr using decoder 11 |
| 242 | // 156: } |
| 243 | 4, 0, // 160: case 0x4: { |
| 244 | OPC_Decode, 165, 3, 12, // 162: decode to BIC8rr using decoder 12 |
| 245 | // 162: } |
| 246 | // 162: } // switch Inst[7:4] |
| 247 | // 162: } |
| 248 | 13, 15, // 166: case 0xd: { |
| 249 | OPC_SwitchField, 4, 4, // 168: switch Inst[7:4] { |
| 250 | 0, 4, // 171: case 0x0: { |
| 251 | OPC_Decode, 177, 3, 11, // 173: decode to BIS16rr using decoder 11 |
| 252 | // 173: } |
| 253 | 4, 0, // 177: case 0x4: { |
| 254 | OPC_Decode, 189, 3, 12, // 179: decode to BIS8rr using decoder 12 |
| 255 | // 179: } |
| 256 | // 179: } // switch Inst[7:4] |
| 257 | // 179: } |
| 258 | 14, 15, // 183: case 0xe: { |
| 259 | OPC_SwitchField, 4, 4, // 185: switch Inst[7:4] { |
| 260 | 0, 4, // 188: case 0x0: { |
| 261 | OPC_Decode, 140, 5, 11, // 190: decode to XOR16rr using decoder 11 |
| 262 | // 190: } |
| 263 | 4, 0, // 194: case 0x4: { |
| 264 | OPC_Decode, 152, 5, 12, // 196: decode to XOR8rr using decoder 12 |
| 265 | // 196: } |
| 266 | // 196: } // switch Inst[7:4] |
| 267 | // 196: } |
| 268 | 15, 0, // 200: case 0xf: { |
| 269 | OPC_SwitchField, 4, 4, // 202: switch Inst[7:4] { |
| 270 | 0, 4, // 205: case 0x0: { |
| 271 | OPC_Decode, 129, 3, 11, // 207: decode to AND16rr using decoder 11 |
| 272 | // 207: } |
| 273 | 4, 0, // 211: case 0x4: { |
| 274 | OPC_Decode, 141, 3, 12, // 213: decode to AND8rr using decoder 12 |
| 275 | // 213: } |
| 276 | // 213: } // switch Inst[7:4] |
| 277 | // 213: } |
| 278 | // 213: } // switch Inst[15:12] |
| 279 | }; |
| 280 | static const uint8_t DecoderTableBeta16[207] = { |
| 281 | OPC_SwitchField, 12, 4, // 0: switch Inst[15:12] { |
| 282 | 4, 15, // 3: case 0x4: { |
| 283 | OPC_SwitchField, 6, 2, // 5: switch Inst[7:6] { |
| 284 | 0, 4, // 8: case 0x0: { |
| 285 | OPC_Decode, 149, 4, 13, // 10: decode to MOV16rc using decoder 13 |
| 286 | // 10: } |
| 287 | 1, 0, // 14: case 0x1: { |
| 288 | OPC_Decode, 160, 4, 14, // 16: decode to MOV8rc using decoder 14 |
| 289 | // 16: } |
| 290 | // 16: } // switch Inst[7:6] |
| 291 | // 16: } |
| 292 | 5, 15, // 20: case 0x5: { |
| 293 | OPC_SwitchField, 6, 2, // 22: switch Inst[7:6] { |
| 294 | 0, 4, // 25: case 0x0: { |
| 295 | OPC_Decode, 201, 2, 15, // 27: decode to ADD16rc using decoder 15 |
| 296 | // 27: } |
| 297 | 1, 0, // 31: case 0x1: { |
| 298 | OPC_Decode, 213, 2, 16, // 33: decode to ADD8rc using decoder 16 |
| 299 | // 33: } |
| 300 | // 33: } // switch Inst[7:6] |
| 301 | // 33: } |
| 302 | 6, 15, // 37: case 0x6: { |
| 303 | OPC_SwitchField, 6, 2, // 39: switch Inst[7:6] { |
| 304 | 0, 4, // 42: case 0x0: { |
| 305 | OPC_Decode, 225, 2, 15, // 44: decode to ADDC16rc using decoder 15 |
| 306 | // 44: } |
| 307 | 1, 0, // 48: case 0x1: { |
| 308 | OPC_Decode, 237, 2, 16, // 50: decode to ADDC8rc using decoder 16 |
| 309 | // 50: } |
| 310 | // 50: } // switch Inst[7:6] |
| 311 | // 50: } |
| 312 | 7, 15, // 54: case 0x7: { |
| 313 | OPC_SwitchField, 6, 2, // 56: switch Inst[7:6] { |
| 314 | 0, 4, // 59: case 0x0: { |
| 315 | OPC_Decode, 227, 4, 15, // 61: decode to SUBC16rc using decoder 15 |
| 316 | // 61: } |
| 317 | 1, 0, // 65: case 0x1: { |
| 318 | OPC_Decode, 239, 4, 16, // 67: decode to SUBC8rc using decoder 16 |
| 319 | // 67: } |
| 320 | // 67: } // switch Inst[7:6] |
| 321 | // 67: } |
| 322 | 8, 15, // 71: case 0x8: { |
| 323 | OPC_SwitchField, 6, 2, // 73: switch Inst[7:6] { |
| 324 | 0, 4, // 76: case 0x0: { |
| 325 | OPC_Decode, 203, 4, 15, // 78: decode to SUB16rc using decoder 15 |
| 326 | // 78: } |
| 327 | 1, 0, // 82: case 0x1: { |
| 328 | OPC_Decode, 215, 4, 16, // 84: decode to SUB8rc using decoder 16 |
| 329 | // 84: } |
| 330 | // 84: } // switch Inst[7:6] |
| 331 | // 84: } |
| 332 | 9, 15, // 88: case 0x9: { |
| 333 | OPC_SwitchField, 6, 2, // 90: switch Inst[7:6] { |
| 334 | 0, 4, // 93: case 0x0: { |
| 335 | OPC_Decode, 228, 3, 13, // 95: decode to CMP16rc using decoder 13 |
| 336 | // 95: } |
| 337 | 1, 0, // 99: case 0x1: { |
| 338 | OPC_Decode, 240, 3, 14, // 101: decode to CMP8rc using decoder 14 |
| 339 | // 101: } |
| 340 | // 101: } // switch Inst[7:6] |
| 341 | // 101: } |
| 342 | 10, 15, // 105: case 0xa: { |
| 343 | OPC_SwitchField, 6, 2, // 107: switch Inst[7:6] { |
| 344 | 0, 4, // 110: case 0x0: { |
| 345 | OPC_Decode, 252, 3, 15, // 112: decode to DADD16rc using decoder 15 |
| 346 | // 112: } |
| 347 | 1, 0, // 116: case 0x1: { |
| 348 | OPC_Decode, 136, 4, 16, // 118: decode to DADD8rc using decoder 16 |
| 349 | // 118: } |
| 350 | // 118: } // switch Inst[7:6] |
| 351 | // 118: } |
| 352 | 11, 15, // 122: case 0xb: { |
| 353 | OPC_SwitchField, 6, 2, // 124: switch Inst[7:6] { |
| 354 | 0, 4, // 127: case 0x0: { |
| 355 | OPC_Decode, 196, 3, 13, // 129: decode to BIT16rc using decoder 13 |
| 356 | // 129: } |
| 357 | 1, 0, // 133: case 0x1: { |
| 358 | OPC_Decode, 208, 3, 14, // 135: decode to BIT8rc using decoder 14 |
| 359 | // 135: } |
| 360 | // 135: } // switch Inst[7:6] |
| 361 | // 135: } |
| 362 | 12, 15, // 139: case 0xc: { |
| 363 | OPC_SwitchField, 6, 2, // 141: switch Inst[7:6] { |
| 364 | 0, 4, // 144: case 0x0: { |
| 365 | OPC_Decode, 148, 3, 15, // 146: decode to BIC16rc using decoder 15 |
| 366 | // 146: } |
| 367 | 1, 0, // 150: case 0x1: { |
| 368 | OPC_Decode, 160, 3, 16, // 152: decode to BIC8rc using decoder 16 |
| 369 | // 152: } |
| 370 | // 152: } // switch Inst[7:6] |
| 371 | // 152: } |
| 372 | 13, 15, // 156: case 0xd: { |
| 373 | OPC_SwitchField, 6, 2, // 158: switch Inst[7:6] { |
| 374 | 0, 4, // 161: case 0x0: { |
| 375 | OPC_Decode, 172, 3, 15, // 163: decode to BIS16rc using decoder 15 |
| 376 | // 163: } |
| 377 | 1, 0, // 167: case 0x1: { |
| 378 | OPC_Decode, 184, 3, 16, // 169: decode to BIS8rc using decoder 16 |
| 379 | // 169: } |
| 380 | // 169: } // switch Inst[7:6] |
| 381 | // 169: } |
| 382 | 14, 15, // 173: case 0xe: { |
| 383 | OPC_SwitchField, 6, 2, // 175: switch Inst[7:6] { |
| 384 | 0, 4, // 178: case 0x0: { |
| 385 | OPC_Decode, 135, 5, 15, // 180: decode to XOR16rc using decoder 15 |
| 386 | // 180: } |
| 387 | 1, 0, // 184: case 0x1: { |
| 388 | OPC_Decode, 147, 5, 16, // 186: decode to XOR8rc using decoder 16 |
| 389 | // 186: } |
| 390 | // 186: } // switch Inst[7:6] |
| 391 | // 186: } |
| 392 | 15, 0, // 190: case 0xf: { |
| 393 | OPC_SwitchField, 6, 2, // 192: switch Inst[7:6] { |
| 394 | 0, 4, // 195: case 0x0: { |
| 395 | OPC_Decode, 252, 2, 15, // 197: decode to AND16rc using decoder 15 |
| 396 | // 197: } |
| 397 | 1, 0, // 201: case 0x1: { |
| 398 | OPC_Decode, 136, 3, 16, // 203: decode to AND8rc using decoder 16 |
| 399 | // 203: } |
| 400 | // 203: } // switch Inst[7:6] |
| 401 | // 203: } |
| 402 | // 203: } // switch Inst[15:12] |
| 403 | }; |
| 404 | static const uint8_t DecoderTableDelta16[375] = { |
| 405 | OPC_SwitchField, 12, 4, // 0: switch Inst[15:12] { |
| 406 | 4, 51, // 3: case 0x4: { |
| 407 | OPC_SwitchField, 4, 4, // 5: switch Inst[7:4] { |
| 408 | 2, 4, // 8: case 0x2: { |
| 409 | OPC_Decode, 152, 4, 9, // 10: decode to MOV16rn using decoder 9 |
| 410 | // 10: } |
| 411 | 3, 28, // 14: case 0x3: { |
| 412 | OPC_Scope, 12, // 16: try { |
| 413 | OPC_CheckField, 0, 4, 0, // 18: check Inst[3:0] == 0x0 |
| 414 | OPC_CheckField, 8, 4, 1, // 22: check Inst[11:8] == 0x1 |
| 415 | OPC_Decode, 173, 4, 5, // 26: decode to RET using decoder 5 |
| 416 | OPC_Scope, 8, // 30: } else try { |
| 417 | OPC_CheckField, 8, 4, 1, // 32: check Inst[11:8] == 0x1 |
| 418 | OPC_Decode, 168, 4, 1, // 36: decode to POP16r using decoder 1 |
| 419 | // 36: } else try { |
| 420 | OPC_Decode, 153, 4, 17, // 40: decode to MOV16rp using decoder 17 |
| 421 | // 40: } |
| 422 | // 40: } |
| 423 | 6, 4, // 44: case 0x6: { |
| 424 | OPC_Decode, 163, 4, 18, // 46: decode to MOV8rn using decoder 18 |
| 425 | // 46: } |
| 426 | 7, 0, // 50: case 0x7: { |
| 427 | OPC_Decode, 164, 4, 19, // 52: decode to MOV8rp using decoder 19 |
| 428 | // 52: } |
| 429 | // 52: } // switch Inst[7:4] |
| 430 | // 52: } |
| 431 | 5, 27, // 56: case 0x5: { |
| 432 | OPC_SwitchField, 4, 4, // 58: switch Inst[7:4] { |
| 433 | 2, 4, // 61: case 0x2: { |
| 434 | OPC_Decode, 204, 2, 11, // 63: decode to ADD16rn using decoder 11 |
| 435 | // 63: } |
| 436 | 3, 4, // 67: case 0x3: { |
| 437 | OPC_Decode, 205, 2, 20, // 69: decode to ADD16rp using decoder 20 |
| 438 | // 69: } |
| 439 | 6, 4, // 73: case 0x6: { |
| 440 | OPC_Decode, 216, 2, 21, // 75: decode to ADD8rn using decoder 21 |
| 441 | // 75: } |
| 442 | 7, 0, // 79: case 0x7: { |
| 443 | OPC_Decode, 217, 2, 22, // 81: decode to ADD8rp using decoder 22 |
| 444 | // 81: } |
| 445 | // 81: } // switch Inst[7:4] |
| 446 | // 81: } |
| 447 | 6, 27, // 85: case 0x6: { |
| 448 | OPC_SwitchField, 4, 4, // 87: switch Inst[7:4] { |
| 449 | 2, 4, // 90: case 0x2: { |
| 450 | OPC_Decode, 228, 2, 11, // 92: decode to ADDC16rn using decoder 11 |
| 451 | // 92: } |
| 452 | 3, 4, // 96: case 0x3: { |
| 453 | OPC_Decode, 229, 2, 20, // 98: decode to ADDC16rp using decoder 20 |
| 454 | // 98: } |
| 455 | 6, 4, // 102: case 0x6: { |
| 456 | OPC_Decode, 240, 2, 21, // 104: decode to ADDC8rn using decoder 21 |
| 457 | // 104: } |
| 458 | 7, 0, // 108: case 0x7: { |
| 459 | OPC_Decode, 241, 2, 22, // 110: decode to ADDC8rp using decoder 22 |
| 460 | // 110: } |
| 461 | // 110: } // switch Inst[7:4] |
| 462 | // 110: } |
| 463 | 7, 27, // 114: case 0x7: { |
| 464 | OPC_SwitchField, 4, 4, // 116: switch Inst[7:4] { |
| 465 | 2, 4, // 119: case 0x2: { |
| 466 | OPC_Decode, 230, 4, 11, // 121: decode to SUBC16rn using decoder 11 |
| 467 | // 121: } |
| 468 | 3, 4, // 125: case 0x3: { |
| 469 | OPC_Decode, 231, 4, 20, // 127: decode to SUBC16rp using decoder 20 |
| 470 | // 127: } |
| 471 | 6, 4, // 131: case 0x6: { |
| 472 | OPC_Decode, 242, 4, 21, // 133: decode to SUBC8rn using decoder 21 |
| 473 | // 133: } |
| 474 | 7, 0, // 137: case 0x7: { |
| 475 | OPC_Decode, 243, 4, 22, // 139: decode to SUBC8rp using decoder 22 |
| 476 | // 139: } |
| 477 | // 139: } // switch Inst[7:4] |
| 478 | // 139: } |
| 479 | 8, 27, // 143: case 0x8: { |
| 480 | OPC_SwitchField, 4, 4, // 145: switch Inst[7:4] { |
| 481 | 2, 4, // 148: case 0x2: { |
| 482 | OPC_Decode, 206, 4, 11, // 150: decode to SUB16rn using decoder 11 |
| 483 | // 150: } |
| 484 | 3, 4, // 154: case 0x3: { |
| 485 | OPC_Decode, 207, 4, 20, // 156: decode to SUB16rp using decoder 20 |
| 486 | // 156: } |
| 487 | 6, 4, // 160: case 0x6: { |
| 488 | OPC_Decode, 218, 4, 21, // 162: decode to SUB8rn using decoder 21 |
| 489 | // 162: } |
| 490 | 7, 0, // 166: case 0x7: { |
| 491 | OPC_Decode, 219, 4, 22, // 168: decode to SUB8rp using decoder 22 |
| 492 | // 168: } |
| 493 | // 168: } // switch Inst[7:4] |
| 494 | // 168: } |
| 495 | 9, 27, // 172: case 0x9: { |
| 496 | OPC_SwitchField, 4, 4, // 174: switch Inst[7:4] { |
| 497 | 2, 4, // 177: case 0x2: { |
| 498 | OPC_Decode, 231, 3, 9, // 179: decode to CMP16rn using decoder 9 |
| 499 | // 179: } |
| 500 | 3, 4, // 183: case 0x3: { |
| 501 | OPC_Decode, 232, 3, 9, // 185: decode to CMP16rp using decoder 9 |
| 502 | // 185: } |
| 503 | 6, 4, // 189: case 0x6: { |
| 504 | OPC_Decode, 243, 3, 18, // 191: decode to CMP8rn using decoder 18 |
| 505 | // 191: } |
| 506 | 7, 0, // 195: case 0x7: { |
| 507 | OPC_Decode, 244, 3, 18, // 197: decode to CMP8rp using decoder 18 |
| 508 | // 197: } |
| 509 | // 197: } // switch Inst[7:4] |
| 510 | // 197: } |
| 511 | 10, 27, // 201: case 0xa: { |
| 512 | OPC_SwitchField, 4, 4, // 203: switch Inst[7:4] { |
| 513 | 2, 4, // 206: case 0x2: { |
| 514 | OPC_Decode, 255, 3, 11, // 208: decode to DADD16rn using decoder 11 |
| 515 | // 208: } |
| 516 | 3, 4, // 212: case 0x3: { |
| 517 | OPC_Decode, 128, 4, 20, // 214: decode to DADD16rp using decoder 20 |
| 518 | // 214: } |
| 519 | 6, 4, // 218: case 0x6: { |
| 520 | OPC_Decode, 139, 4, 21, // 220: decode to DADD8rn using decoder 21 |
| 521 | // 220: } |
| 522 | 7, 0, // 224: case 0x7: { |
| 523 | OPC_Decode, 140, 4, 22, // 226: decode to DADD8rp using decoder 22 |
| 524 | // 226: } |
| 525 | // 226: } // switch Inst[7:4] |
| 526 | // 226: } |
| 527 | 11, 27, // 230: case 0xb: { |
| 528 | OPC_SwitchField, 4, 4, // 232: switch Inst[7:4] { |
| 529 | 2, 4, // 235: case 0x2: { |
| 530 | OPC_Decode, 199, 3, 9, // 237: decode to BIT16rn using decoder 9 |
| 531 | // 237: } |
| 532 | 3, 4, // 241: case 0x3: { |
| 533 | OPC_Decode, 200, 3, 9, // 243: decode to BIT16rp using decoder 9 |
| 534 | // 243: } |
| 535 | 6, 4, // 247: case 0x6: { |
| 536 | OPC_Decode, 211, 3, 18, // 249: decode to BIT8rn using decoder 18 |
| 537 | // 249: } |
| 538 | 7, 0, // 253: case 0x7: { |
| 539 | OPC_Decode, 212, 3, 18, // 255: decode to BIT8rp using decoder 18 |
| 540 | // 255: } |
| 541 | // 255: } // switch Inst[7:4] |
| 542 | // 255: } |
| 543 | 12, 27, // 259: case 0xc: { |
| 544 | OPC_SwitchField, 4, 4, // 261: switch Inst[7:4] { |
| 545 | 2, 4, // 264: case 0x2: { |
| 546 | OPC_Decode, 151, 3, 11, // 266: decode to BIC16rn using decoder 11 |
| 547 | // 266: } |
| 548 | 3, 4, // 270: case 0x3: { |
| 549 | OPC_Decode, 152, 3, 20, // 272: decode to BIC16rp using decoder 20 |
| 550 | // 272: } |
| 551 | 6, 4, // 276: case 0x6: { |
| 552 | OPC_Decode, 163, 3, 21, // 278: decode to BIC8rn using decoder 21 |
| 553 | // 278: } |
| 554 | 7, 0, // 282: case 0x7: { |
| 555 | OPC_Decode, 164, 3, 22, // 284: decode to BIC8rp using decoder 22 |
| 556 | // 284: } |
| 557 | // 284: } // switch Inst[7:4] |
| 558 | // 284: } |
| 559 | 13, 27, // 288: case 0xd: { |
| 560 | OPC_SwitchField, 4, 4, // 290: switch Inst[7:4] { |
| 561 | 2, 4, // 293: case 0x2: { |
| 562 | OPC_Decode, 175, 3, 11, // 295: decode to BIS16rn using decoder 11 |
| 563 | // 295: } |
| 564 | 3, 4, // 299: case 0x3: { |
| 565 | OPC_Decode, 176, 3, 20, // 301: decode to BIS16rp using decoder 20 |
| 566 | // 301: } |
| 567 | 6, 4, // 305: case 0x6: { |
| 568 | OPC_Decode, 187, 3, 21, // 307: decode to BIS8rn using decoder 21 |
| 569 | // 307: } |
| 570 | 7, 0, // 311: case 0x7: { |
| 571 | OPC_Decode, 188, 3, 22, // 313: decode to BIS8rp using decoder 22 |
| 572 | // 313: } |
| 573 | // 313: } // switch Inst[7:4] |
| 574 | // 313: } |
| 575 | 14, 27, // 317: case 0xe: { |
| 576 | OPC_SwitchField, 4, 4, // 319: switch Inst[7:4] { |
| 577 | 2, 4, // 322: case 0x2: { |
| 578 | OPC_Decode, 138, 5, 11, // 324: decode to XOR16rn using decoder 11 |
| 579 | // 324: } |
| 580 | 3, 4, // 328: case 0x3: { |
| 581 | OPC_Decode, 139, 5, 20, // 330: decode to XOR16rp using decoder 20 |
| 582 | // 330: } |
| 583 | 6, 4, // 334: case 0x6: { |
| 584 | OPC_Decode, 150, 5, 21, // 336: decode to XOR8rn using decoder 21 |
| 585 | // 336: } |
| 586 | 7, 0, // 340: case 0x7: { |
| 587 | OPC_Decode, 151, 5, 22, // 342: decode to XOR8rp using decoder 22 |
| 588 | // 342: } |
| 589 | // 342: } // switch Inst[7:4] |
| 590 | // 342: } |
| 591 | 15, 0, // 346: case 0xf: { |
| 592 | OPC_SwitchField, 4, 4, // 348: switch Inst[7:4] { |
| 593 | 2, 4, // 351: case 0x2: { |
| 594 | OPC_Decode, 255, 2, 11, // 353: decode to AND16rn using decoder 11 |
| 595 | // 353: } |
| 596 | 3, 4, // 357: case 0x3: { |
| 597 | OPC_Decode, 128, 3, 20, // 359: decode to AND16rp using decoder 20 |
| 598 | // 359: } |
| 599 | 6, 4, // 363: case 0x6: { |
| 600 | OPC_Decode, 139, 3, 21, // 365: decode to AND8rn using decoder 21 |
| 601 | // 365: } |
| 602 | 7, 0, // 369: case 0x7: { |
| 603 | OPC_Decode, 140, 3, 22, // 371: decode to AND8rp using decoder 22 |
| 604 | // 371: } |
| 605 | // 371: } // switch Inst[7:4] |
| 606 | // 371: } |
| 607 | // 371: } // switch Inst[15:12] |
| 608 | }; |
| 609 | static const uint8_t DecoderTable32[74] = { |
| 610 | OPC_SwitchField, 4, 12, // 0: switch Inst[15:4] { |
| 611 | 129, 2, 4, // 3: case 0x101: { |
| 612 | OPC_Decode, 183, 4, 23, // 6: decode to RRC16m using decoder 23 |
| 613 | // 6: } |
| 614 | 133, 2, 4, // 10: case 0x105: { |
| 615 | OPC_Decode, 187, 4, 23, // 13: decode to RRC8m using decoder 23 |
| 616 | // 13: } |
| 617 | 137, 2, 4, // 17: case 0x109: { |
| 618 | OPC_Decode, 245, 4, 23, // 20: decode to SWPB16m using decoder 23 |
| 619 | // 20: } |
| 620 | 145, 2, 4, // 24: case 0x111: { |
| 621 | OPC_Decode, 175, 4, 23, // 27: decode to RRA16m using decoder 23 |
| 622 | // 27: } |
| 623 | 149, 2, 4, // 31: case 0x115: { |
| 624 | OPC_Decode, 179, 4, 23, // 34: decode to RRA8m using decoder 23 |
| 625 | // 34: } |
| 626 | 153, 2, 4, // 38: case 0x119: { |
| 627 | OPC_Decode, 193, 4, 23, // 41: decode to SEXT16m using decoder 23 |
| 628 | // 41: } |
| 629 | 163, 2, 8, // 45: case 0x123: { |
| 630 | OPC_CheckField, 0, 4, 0, // 48: check Inst[3:0] == 0x0 |
| 631 | OPC_Decode, 170, 4, 24, // 52: decode to PUSH16i using decoder 24 |
| 632 | // 52: } |
| 633 | 169, 2, 4, // 56: case 0x129: { |
| 634 | OPC_Decode, 218, 3, 23, // 59: decode to CALLm using decoder 23 |
| 635 | // 59: } |
| 636 | 171, 2, 0, // 63: case 0x12b: { |
| 637 | OPC_CheckField, 0, 4, 0, // 66: check Inst[3:0] == 0x0 |
| 638 | OPC_Decode, 217, 3, 24, // 70: decode to CALLi using decoder 24 |
| 639 | // 70: } |
| 640 | // 70: } // switch Inst[15:4] |
| 641 | }; |
| 642 | static const uint8_t DecoderTableAlpha32[207] = { |
| 643 | OPC_SwitchField, 12, 4, // 0: switch Inst[15:12] { |
| 644 | 4, 15, // 3: case 0x4: { |
| 645 | OPC_SwitchField, 4, 4, // 5: switch Inst[7:4] { |
| 646 | 8, 4, // 8: case 0x8: { |
| 647 | OPC_Decode, 148, 4, 25, // 10: decode to MOV16mr using decoder 25 |
| 648 | // 10: } |
| 649 | 12, 0, // 14: case 0xc: { |
| 650 | OPC_Decode, 159, 4, 26, // 16: decode to MOV8mr using decoder 26 |
| 651 | // 16: } |
| 652 | // 16: } // switch Inst[7:4] |
| 653 | // 16: } |
| 654 | 5, 15, // 20: case 0x5: { |
| 655 | OPC_SwitchField, 4, 4, // 22: switch Inst[7:4] { |
| 656 | 8, 4, // 25: case 0x8: { |
| 657 | OPC_Decode, 200, 2, 25, // 27: decode to ADD16mr using decoder 25 |
| 658 | // 27: } |
| 659 | 12, 0, // 31: case 0xc: { |
| 660 | OPC_Decode, 212, 2, 26, // 33: decode to ADD8mr using decoder 26 |
| 661 | // 33: } |
| 662 | // 33: } // switch Inst[7:4] |
| 663 | // 33: } |
| 664 | 6, 15, // 37: case 0x6: { |
| 665 | OPC_SwitchField, 4, 4, // 39: switch Inst[7:4] { |
| 666 | 8, 4, // 42: case 0x8: { |
| 667 | OPC_Decode, 224, 2, 25, // 44: decode to ADDC16mr using decoder 25 |
| 668 | // 44: } |
| 669 | 12, 0, // 48: case 0xc: { |
| 670 | OPC_Decode, 236, 2, 26, // 50: decode to ADDC8mr using decoder 26 |
| 671 | // 50: } |
| 672 | // 50: } // switch Inst[7:4] |
| 673 | // 50: } |
| 674 | 7, 15, // 54: case 0x7: { |
| 675 | OPC_SwitchField, 4, 4, // 56: switch Inst[7:4] { |
| 676 | 8, 4, // 59: case 0x8: { |
| 677 | OPC_Decode, 226, 4, 25, // 61: decode to SUBC16mr using decoder 25 |
| 678 | // 61: } |
| 679 | 12, 0, // 65: case 0xc: { |
| 680 | OPC_Decode, 238, 4, 26, // 67: decode to SUBC8mr using decoder 26 |
| 681 | // 67: } |
| 682 | // 67: } // switch Inst[7:4] |
| 683 | // 67: } |
| 684 | 8, 15, // 71: case 0x8: { |
| 685 | OPC_SwitchField, 4, 4, // 73: switch Inst[7:4] { |
| 686 | 8, 4, // 76: case 0x8: { |
| 687 | OPC_Decode, 202, 4, 25, // 78: decode to SUB16mr using decoder 25 |
| 688 | // 78: } |
| 689 | 12, 0, // 82: case 0xc: { |
| 690 | OPC_Decode, 214, 4, 26, // 84: decode to SUB8mr using decoder 26 |
| 691 | // 84: } |
| 692 | // 84: } // switch Inst[7:4] |
| 693 | // 84: } |
| 694 | 9, 15, // 88: case 0x9: { |
| 695 | OPC_SwitchField, 4, 4, // 90: switch Inst[7:4] { |
| 696 | 8, 4, // 93: case 0x8: { |
| 697 | OPC_Decode, 227, 3, 25, // 95: decode to CMP16mr using decoder 25 |
| 698 | // 95: } |
| 699 | 12, 0, // 99: case 0xc: { |
| 700 | OPC_Decode, 239, 3, 26, // 101: decode to CMP8mr using decoder 26 |
| 701 | // 101: } |
| 702 | // 101: } // switch Inst[7:4] |
| 703 | // 101: } |
| 704 | 10, 15, // 105: case 0xa: { |
| 705 | OPC_SwitchField, 4, 4, // 107: switch Inst[7:4] { |
| 706 | 8, 4, // 110: case 0x8: { |
| 707 | OPC_Decode, 251, 3, 25, // 112: decode to DADD16mr using decoder 25 |
| 708 | // 112: } |
| 709 | 12, 0, // 116: case 0xc: { |
| 710 | OPC_Decode, 135, 4, 26, // 118: decode to DADD8mr using decoder 26 |
| 711 | // 118: } |
| 712 | // 118: } // switch Inst[7:4] |
| 713 | // 118: } |
| 714 | 11, 15, // 122: case 0xb: { |
| 715 | OPC_SwitchField, 4, 4, // 124: switch Inst[7:4] { |
| 716 | 8, 4, // 127: case 0x8: { |
| 717 | OPC_Decode, 195, 3, 25, // 129: decode to BIT16mr using decoder 25 |
| 718 | // 129: } |
| 719 | 12, 0, // 133: case 0xc: { |
| 720 | OPC_Decode, 207, 3, 26, // 135: decode to BIT8mr using decoder 26 |
| 721 | // 135: } |
| 722 | // 135: } // switch Inst[7:4] |
| 723 | // 135: } |
| 724 | 12, 15, // 139: case 0xc: { |
| 725 | OPC_SwitchField, 4, 4, // 141: switch Inst[7:4] { |
| 726 | 8, 4, // 144: case 0x8: { |
| 727 | OPC_Decode, 147, 3, 25, // 146: decode to BIC16mr using decoder 25 |
| 728 | // 146: } |
| 729 | 12, 0, // 150: case 0xc: { |
| 730 | OPC_Decode, 159, 3, 26, // 152: decode to BIC8mr using decoder 26 |
| 731 | // 152: } |
| 732 | // 152: } // switch Inst[7:4] |
| 733 | // 152: } |
| 734 | 13, 15, // 156: case 0xd: { |
| 735 | OPC_SwitchField, 4, 4, // 158: switch Inst[7:4] { |
| 736 | 8, 4, // 161: case 0x8: { |
| 737 | OPC_Decode, 171, 3, 25, // 163: decode to BIS16mr using decoder 25 |
| 738 | // 163: } |
| 739 | 12, 0, // 167: case 0xc: { |
| 740 | OPC_Decode, 183, 3, 26, // 169: decode to BIS8mr using decoder 26 |
| 741 | // 169: } |
| 742 | // 169: } // switch Inst[7:4] |
| 743 | // 169: } |
| 744 | 14, 15, // 173: case 0xe: { |
| 745 | OPC_SwitchField, 4, 4, // 175: switch Inst[7:4] { |
| 746 | 8, 4, // 178: case 0x8: { |
| 747 | OPC_Decode, 134, 5, 25, // 180: decode to XOR16mr using decoder 25 |
| 748 | // 180: } |
| 749 | 12, 0, // 184: case 0xc: { |
| 750 | OPC_Decode, 146, 5, 26, // 186: decode to XOR8mr using decoder 26 |
| 751 | // 186: } |
| 752 | // 186: } // switch Inst[7:4] |
| 753 | // 186: } |
| 754 | 15, 0, // 190: case 0xf: { |
| 755 | OPC_SwitchField, 4, 4, // 192: switch Inst[7:4] { |
| 756 | 8, 4, // 195: case 0x8: { |
| 757 | OPC_Decode, 251, 2, 25, // 197: decode to AND16mr using decoder 25 |
| 758 | // 197: } |
| 759 | 12, 0, // 201: case 0xc: { |
| 760 | OPC_Decode, 135, 3, 26, // 203: decode to AND8mr using decoder 26 |
| 761 | // 203: } |
| 762 | // 203: } // switch Inst[7:4] |
| 763 | // 203: } |
| 764 | // 203: } // switch Inst[15:12] |
| 765 | }; |
| 766 | static const uint8_t DecoderTableBeta32[207] = { |
| 767 | OPC_SwitchField, 12, 4, // 0: switch Inst[15:12] { |
| 768 | 4, 15, // 3: case 0x4: { |
| 769 | OPC_SwitchField, 6, 2, // 5: switch Inst[7:6] { |
| 770 | 2, 4, // 8: case 0x2: { |
| 771 | OPC_Decode, 144, 4, 27, // 10: decode to MOV16mc using decoder 27 |
| 772 | // 10: } |
| 773 | 3, 0, // 14: case 0x3: { |
| 774 | OPC_Decode, 155, 4, 27, // 16: decode to MOV8mc using decoder 27 |
| 775 | // 16: } |
| 776 | // 16: } // switch Inst[7:6] |
| 777 | // 16: } |
| 778 | 5, 15, // 20: case 0x5: { |
| 779 | OPC_SwitchField, 6, 2, // 22: switch Inst[7:6] { |
| 780 | 2, 4, // 25: case 0x2: { |
| 781 | OPC_Decode, 195, 2, 27, // 27: decode to ADD16mc using decoder 27 |
| 782 | // 27: } |
| 783 | 3, 0, // 31: case 0x3: { |
| 784 | OPC_Decode, 207, 2, 27, // 33: decode to ADD8mc using decoder 27 |
| 785 | // 33: } |
| 786 | // 33: } // switch Inst[7:6] |
| 787 | // 33: } |
| 788 | 6, 15, // 37: case 0x6: { |
| 789 | OPC_SwitchField, 6, 2, // 39: switch Inst[7:6] { |
| 790 | 2, 4, // 42: case 0x2: { |
| 791 | OPC_Decode, 219, 2, 27, // 44: decode to ADDC16mc using decoder 27 |
| 792 | // 44: } |
| 793 | 3, 0, // 48: case 0x3: { |
| 794 | OPC_Decode, 231, 2, 27, // 50: decode to ADDC8mc using decoder 27 |
| 795 | // 50: } |
| 796 | // 50: } // switch Inst[7:6] |
| 797 | // 50: } |
| 798 | 7, 15, // 54: case 0x7: { |
| 799 | OPC_SwitchField, 6, 2, // 56: switch Inst[7:6] { |
| 800 | 2, 4, // 59: case 0x2: { |
| 801 | OPC_Decode, 221, 4, 27, // 61: decode to SUBC16mc using decoder 27 |
| 802 | // 61: } |
| 803 | 3, 0, // 65: case 0x3: { |
| 804 | OPC_Decode, 233, 4, 27, // 67: decode to SUBC8mc using decoder 27 |
| 805 | // 67: } |
| 806 | // 67: } // switch Inst[7:6] |
| 807 | // 67: } |
| 808 | 8, 15, // 71: case 0x8: { |
| 809 | OPC_SwitchField, 6, 2, // 73: switch Inst[7:6] { |
| 810 | 2, 4, // 76: case 0x2: { |
| 811 | OPC_Decode, 197, 4, 27, // 78: decode to SUB16mc using decoder 27 |
| 812 | // 78: } |
| 813 | 3, 0, // 82: case 0x3: { |
| 814 | OPC_Decode, 209, 4, 27, // 84: decode to SUB8mc using decoder 27 |
| 815 | // 84: } |
| 816 | // 84: } // switch Inst[7:6] |
| 817 | // 84: } |
| 818 | 9, 15, // 88: case 0x9: { |
| 819 | OPC_SwitchField, 6, 2, // 90: switch Inst[7:6] { |
| 820 | 2, 4, // 93: case 0x2: { |
| 821 | OPC_Decode, 222, 3, 27, // 95: decode to CMP16mc using decoder 27 |
| 822 | // 95: } |
| 823 | 3, 0, // 99: case 0x3: { |
| 824 | OPC_Decode, 234, 3, 27, // 101: decode to CMP8mc using decoder 27 |
| 825 | // 101: } |
| 826 | // 101: } // switch Inst[7:6] |
| 827 | // 101: } |
| 828 | 10, 15, // 105: case 0xa: { |
| 829 | OPC_SwitchField, 6, 2, // 107: switch Inst[7:6] { |
| 830 | 2, 4, // 110: case 0x2: { |
| 831 | OPC_Decode, 246, 3, 27, // 112: decode to DADD16mc using decoder 27 |
| 832 | // 112: } |
| 833 | 3, 0, // 116: case 0x3: { |
| 834 | OPC_Decode, 130, 4, 27, // 118: decode to DADD8mc using decoder 27 |
| 835 | // 118: } |
| 836 | // 118: } // switch Inst[7:6] |
| 837 | // 118: } |
| 838 | 11, 15, // 122: case 0xb: { |
| 839 | OPC_SwitchField, 6, 2, // 124: switch Inst[7:6] { |
| 840 | 2, 4, // 127: case 0x2: { |
| 841 | OPC_Decode, 190, 3, 27, // 129: decode to BIT16mc using decoder 27 |
| 842 | // 129: } |
| 843 | 3, 0, // 133: case 0x3: { |
| 844 | OPC_Decode, 202, 3, 27, // 135: decode to BIT8mc using decoder 27 |
| 845 | // 135: } |
| 846 | // 135: } // switch Inst[7:6] |
| 847 | // 135: } |
| 848 | 12, 15, // 139: case 0xc: { |
| 849 | OPC_SwitchField, 6, 2, // 141: switch Inst[7:6] { |
| 850 | 2, 4, // 144: case 0x2: { |
| 851 | OPC_Decode, 142, 3, 27, // 146: decode to BIC16mc using decoder 27 |
| 852 | // 146: } |
| 853 | 3, 0, // 150: case 0x3: { |
| 854 | OPC_Decode, 154, 3, 27, // 152: decode to BIC8mc using decoder 27 |
| 855 | // 152: } |
| 856 | // 152: } // switch Inst[7:6] |
| 857 | // 152: } |
| 858 | 13, 15, // 156: case 0xd: { |
| 859 | OPC_SwitchField, 6, 2, // 158: switch Inst[7:6] { |
| 860 | 2, 4, // 161: case 0x2: { |
| 861 | OPC_Decode, 166, 3, 27, // 163: decode to BIS16mc using decoder 27 |
| 862 | // 163: } |
| 863 | 3, 0, // 167: case 0x3: { |
| 864 | OPC_Decode, 178, 3, 27, // 169: decode to BIS8mc using decoder 27 |
| 865 | // 169: } |
| 866 | // 169: } // switch Inst[7:6] |
| 867 | // 169: } |
| 868 | 14, 15, // 173: case 0xe: { |
| 869 | OPC_SwitchField, 6, 2, // 175: switch Inst[7:6] { |
| 870 | 2, 4, // 178: case 0x2: { |
| 871 | OPC_Decode, 129, 5, 27, // 180: decode to XOR16mc using decoder 27 |
| 872 | // 180: } |
| 873 | 3, 0, // 184: case 0x3: { |
| 874 | OPC_Decode, 141, 5, 27, // 186: decode to XOR8mc using decoder 27 |
| 875 | // 186: } |
| 876 | // 186: } // switch Inst[7:6] |
| 877 | // 186: } |
| 878 | 15, 0, // 190: case 0xf: { |
| 879 | OPC_SwitchField, 6, 2, // 192: switch Inst[7:6] { |
| 880 | 2, 4, // 195: case 0x2: { |
| 881 | OPC_Decode, 246, 2, 27, // 197: decode to AND16mc using decoder 27 |
| 882 | // 197: } |
| 883 | 3, 0, // 201: case 0x3: { |
| 884 | OPC_Decode, 130, 3, 27, // 203: decode to AND8mc using decoder 27 |
| 885 | // 203: } |
| 886 | // 203: } // switch Inst[7:6] |
| 887 | // 203: } |
| 888 | // 203: } // switch Inst[15:12] |
| 889 | }; |
| 890 | static const uint8_t DecoderTableDelta32[339] = { |
| 891 | OPC_SwitchField, 12, 4, // 0: switch Inst[15:12] { |
| 892 | 4, 15, // 3: case 0x4: { |
| 893 | OPC_SwitchField, 4, 4, // 5: switch Inst[7:4] { |
| 894 | 10, 4, // 8: case 0xa: { |
| 895 | OPC_Decode, 147, 4, 25, // 10: decode to MOV16mn using decoder 25 |
| 896 | // 10: } |
| 897 | 14, 0, // 14: case 0xe: { |
| 898 | OPC_Decode, 158, 4, 25, // 16: decode to MOV8mn using decoder 25 |
| 899 | // 16: } |
| 900 | // 16: } // switch Inst[7:4] |
| 901 | // 16: } |
| 902 | 5, 27, // 20: case 0x5: { |
| 903 | OPC_SwitchField, 4, 4, // 22: switch Inst[7:4] { |
| 904 | 10, 4, // 25: case 0xa: { |
| 905 | OPC_Decode, 198, 2, 25, // 27: decode to ADD16mn using decoder 25 |
| 906 | // 27: } |
| 907 | 11, 4, // 31: case 0xb: { |
| 908 | OPC_Decode, 199, 2, 25, // 33: decode to ADD16mp using decoder 25 |
| 909 | // 33: } |
| 910 | 14, 4, // 37: case 0xe: { |
| 911 | OPC_Decode, 210, 2, 25, // 39: decode to ADD8mn using decoder 25 |
| 912 | // 39: } |
| 913 | 15, 0, // 43: case 0xf: { |
| 914 | OPC_Decode, 211, 2, 25, // 45: decode to ADD8mp using decoder 25 |
| 915 | // 45: } |
| 916 | // 45: } // switch Inst[7:4] |
| 917 | // 45: } |
| 918 | 6, 27, // 49: case 0x6: { |
| 919 | OPC_SwitchField, 4, 4, // 51: switch Inst[7:4] { |
| 920 | 10, 4, // 54: case 0xa: { |
| 921 | OPC_Decode, 222, 2, 25, // 56: decode to ADDC16mn using decoder 25 |
| 922 | // 56: } |
| 923 | 11, 4, // 60: case 0xb: { |
| 924 | OPC_Decode, 223, 2, 25, // 62: decode to ADDC16mp using decoder 25 |
| 925 | // 62: } |
| 926 | 14, 4, // 66: case 0xe: { |
| 927 | OPC_Decode, 234, 2, 25, // 68: decode to ADDC8mn using decoder 25 |
| 928 | // 68: } |
| 929 | 15, 0, // 72: case 0xf: { |
| 930 | OPC_Decode, 235, 2, 25, // 74: decode to ADDC8mp using decoder 25 |
| 931 | // 74: } |
| 932 | // 74: } // switch Inst[7:4] |
| 933 | // 74: } |
| 934 | 7, 27, // 78: case 0x7: { |
| 935 | OPC_SwitchField, 4, 4, // 80: switch Inst[7:4] { |
| 936 | 10, 4, // 83: case 0xa: { |
| 937 | OPC_Decode, 224, 4, 25, // 85: decode to SUBC16mn using decoder 25 |
| 938 | // 85: } |
| 939 | 11, 4, // 89: case 0xb: { |
| 940 | OPC_Decode, 225, 4, 25, // 91: decode to SUBC16mp using decoder 25 |
| 941 | // 91: } |
| 942 | 14, 4, // 95: case 0xe: { |
| 943 | OPC_Decode, 236, 4, 25, // 97: decode to SUBC8mn using decoder 25 |
| 944 | // 97: } |
| 945 | 15, 0, // 101: case 0xf: { |
| 946 | OPC_Decode, 237, 4, 25, // 103: decode to SUBC8mp using decoder 25 |
| 947 | // 103: } |
| 948 | // 103: } // switch Inst[7:4] |
| 949 | // 103: } |
| 950 | 8, 27, // 107: case 0x8: { |
| 951 | OPC_SwitchField, 4, 4, // 109: switch Inst[7:4] { |
| 952 | 10, 4, // 112: case 0xa: { |
| 953 | OPC_Decode, 200, 4, 25, // 114: decode to SUB16mn using decoder 25 |
| 954 | // 114: } |
| 955 | 11, 4, // 118: case 0xb: { |
| 956 | OPC_Decode, 201, 4, 25, // 120: decode to SUB16mp using decoder 25 |
| 957 | // 120: } |
| 958 | 14, 4, // 124: case 0xe: { |
| 959 | OPC_Decode, 212, 4, 25, // 126: decode to SUB8mn using decoder 25 |
| 960 | // 126: } |
| 961 | 15, 0, // 130: case 0xf: { |
| 962 | OPC_Decode, 213, 4, 25, // 132: decode to SUB8mp using decoder 25 |
| 963 | // 132: } |
| 964 | // 132: } // switch Inst[7:4] |
| 965 | // 132: } |
| 966 | 9, 27, // 136: case 0x9: { |
| 967 | OPC_SwitchField, 4, 4, // 138: switch Inst[7:4] { |
| 968 | 10, 4, // 141: case 0xa: { |
| 969 | OPC_Decode, 225, 3, 25, // 143: decode to CMP16mn using decoder 25 |
| 970 | // 143: } |
| 971 | 11, 4, // 147: case 0xb: { |
| 972 | OPC_Decode, 226, 3, 25, // 149: decode to CMP16mp using decoder 25 |
| 973 | // 149: } |
| 974 | 14, 4, // 153: case 0xe: { |
| 975 | OPC_Decode, 237, 3, 25, // 155: decode to CMP8mn using decoder 25 |
| 976 | // 155: } |
| 977 | 15, 0, // 159: case 0xf: { |
| 978 | OPC_Decode, 238, 3, 25, // 161: decode to CMP8mp using decoder 25 |
| 979 | // 161: } |
| 980 | // 161: } // switch Inst[7:4] |
| 981 | // 161: } |
| 982 | 10, 27, // 165: case 0xa: { |
| 983 | OPC_SwitchField, 4, 4, // 167: switch Inst[7:4] { |
| 984 | 10, 4, // 170: case 0xa: { |
| 985 | OPC_Decode, 249, 3, 25, // 172: decode to DADD16mn using decoder 25 |
| 986 | // 172: } |
| 987 | 11, 4, // 176: case 0xb: { |
| 988 | OPC_Decode, 250, 3, 25, // 178: decode to DADD16mp using decoder 25 |
| 989 | // 178: } |
| 990 | 14, 4, // 182: case 0xe: { |
| 991 | OPC_Decode, 133, 4, 25, // 184: decode to DADD8mn using decoder 25 |
| 992 | // 184: } |
| 993 | 15, 0, // 188: case 0xf: { |
| 994 | OPC_Decode, 134, 4, 25, // 190: decode to DADD8mp using decoder 25 |
| 995 | // 190: } |
| 996 | // 190: } // switch Inst[7:4] |
| 997 | // 190: } |
| 998 | 11, 27, // 194: case 0xb: { |
| 999 | OPC_SwitchField, 4, 4, // 196: switch Inst[7:4] { |
| 1000 | 10, 4, // 199: case 0xa: { |
| 1001 | OPC_Decode, 193, 3, 25, // 201: decode to BIT16mn using decoder 25 |
| 1002 | // 201: } |
| 1003 | 11, 4, // 205: case 0xb: { |
| 1004 | OPC_Decode, 194, 3, 25, // 207: decode to BIT16mp using decoder 25 |
| 1005 | // 207: } |
| 1006 | 14, 4, // 211: case 0xe: { |
| 1007 | OPC_Decode, 205, 3, 25, // 213: decode to BIT8mn using decoder 25 |
| 1008 | // 213: } |
| 1009 | 15, 0, // 217: case 0xf: { |
| 1010 | OPC_Decode, 206, 3, 25, // 219: decode to BIT8mp using decoder 25 |
| 1011 | // 219: } |
| 1012 | // 219: } // switch Inst[7:4] |
| 1013 | // 219: } |
| 1014 | 12, 27, // 223: case 0xc: { |
| 1015 | OPC_SwitchField, 4, 4, // 225: switch Inst[7:4] { |
| 1016 | 10, 4, // 228: case 0xa: { |
| 1017 | OPC_Decode, 145, 3, 25, // 230: decode to BIC16mn using decoder 25 |
| 1018 | // 230: } |
| 1019 | 11, 4, // 234: case 0xb: { |
| 1020 | OPC_Decode, 146, 3, 25, // 236: decode to BIC16mp using decoder 25 |
| 1021 | // 236: } |
| 1022 | 14, 4, // 240: case 0xe: { |
| 1023 | OPC_Decode, 157, 3, 25, // 242: decode to BIC8mn using decoder 25 |
| 1024 | // 242: } |
| 1025 | 15, 0, // 246: case 0xf: { |
| 1026 | OPC_Decode, 158, 3, 25, // 248: decode to BIC8mp using decoder 25 |
| 1027 | // 248: } |
| 1028 | // 248: } // switch Inst[7:4] |
| 1029 | // 248: } |
| 1030 | 13, 27, // 252: case 0xd: { |
| 1031 | OPC_SwitchField, 4, 4, // 254: switch Inst[7:4] { |
| 1032 | 10, 4, // 257: case 0xa: { |
| 1033 | OPC_Decode, 169, 3, 25, // 259: decode to BIS16mn using decoder 25 |
| 1034 | // 259: } |
| 1035 | 11, 4, // 263: case 0xb: { |
| 1036 | OPC_Decode, 170, 3, 25, // 265: decode to BIS16mp using decoder 25 |
| 1037 | // 265: } |
| 1038 | 14, 4, // 269: case 0xe: { |
| 1039 | OPC_Decode, 181, 3, 25, // 271: decode to BIS8mn using decoder 25 |
| 1040 | // 271: } |
| 1041 | 15, 0, // 275: case 0xf: { |
| 1042 | OPC_Decode, 182, 3, 25, // 277: decode to BIS8mp using decoder 25 |
| 1043 | // 277: } |
| 1044 | // 277: } // switch Inst[7:4] |
| 1045 | // 277: } |
| 1046 | 14, 27, // 281: case 0xe: { |
| 1047 | OPC_SwitchField, 4, 4, // 283: switch Inst[7:4] { |
| 1048 | 10, 4, // 286: case 0xa: { |
| 1049 | OPC_Decode, 132, 5, 25, // 288: decode to XOR16mn using decoder 25 |
| 1050 | // 288: } |
| 1051 | 11, 4, // 292: case 0xb: { |
| 1052 | OPC_Decode, 133, 5, 25, // 294: decode to XOR16mp using decoder 25 |
| 1053 | // 294: } |
| 1054 | 14, 4, // 298: case 0xe: { |
| 1055 | OPC_Decode, 144, 5, 25, // 300: decode to XOR8mn using decoder 25 |
| 1056 | // 300: } |
| 1057 | 15, 0, // 304: case 0xf: { |
| 1058 | OPC_Decode, 145, 5, 25, // 306: decode to XOR8mp using decoder 25 |
| 1059 | // 306: } |
| 1060 | // 306: } // switch Inst[7:4] |
| 1061 | // 306: } |
| 1062 | 15, 0, // 310: case 0xf: { |
| 1063 | OPC_SwitchField, 4, 4, // 312: switch Inst[7:4] { |
| 1064 | 10, 4, // 315: case 0xa: { |
| 1065 | OPC_Decode, 249, 2, 25, // 317: decode to AND16mn using decoder 25 |
| 1066 | // 317: } |
| 1067 | 11, 4, // 321: case 0xb: { |
| 1068 | OPC_Decode, 250, 2, 25, // 323: decode to AND16mp using decoder 25 |
| 1069 | // 323: } |
| 1070 | 14, 4, // 327: case 0xe: { |
| 1071 | OPC_Decode, 133, 3, 25, // 329: decode to AND8mn using decoder 25 |
| 1072 | // 329: } |
| 1073 | 15, 0, // 333: case 0xf: { |
| 1074 | OPC_Decode, 134, 3, 25, // 335: decode to AND8mp using decoder 25 |
| 1075 | // 335: } |
| 1076 | // 335: } // switch Inst[7:4] |
| 1077 | // 335: } |
| 1078 | // 335: } // switch Inst[15:12] |
| 1079 | }; |
| 1080 | static const uint8_t DecoderTableGamma32[467] = { |
| 1081 | OPC_SwitchField, 12, 4, // 0: switch Inst[15:12] { |
| 1082 | 4, 55, // 3: case 0x4: { |
| 1083 | OPC_SwitchField, 4, 4, // 5: switch Inst[7:4] { |
| 1084 | 1, 14, // 8: case 0x1: { |
| 1085 | OPC_Scope, 8, // 10: try { |
| 1086 | OPC_CheckField, 0, 4, 0, // 12: check Inst[3:0] == 0x0 |
| 1087 | OPC_Decode, 215, 3, 28, // 16: decode to Bm using decoder 28 |
| 1088 | // 16: } else try { |
| 1089 | OPC_Decode, 151, 4, 29, // 20: decode to MOV16rm using decoder 29 |
| 1090 | // 20: } |
| 1091 | // 20: } |
| 1092 | 3, 18, // 24: case 0x3: { |
| 1093 | OPC_CheckField, 8, 4, 0, // 26: check Inst[11:8] == 0x0 |
| 1094 | OPC_Scope, 8, // 30: try { |
| 1095 | OPC_CheckField, 0, 4, 0, // 32: check Inst[3:0] == 0x0 |
| 1096 | OPC_Decode, 214, 3, 24, // 36: decode to Bi using decoder 24 |
| 1097 | // 36: } else try { |
| 1098 | OPC_Decode, 150, 4, 30, // 40: decode to MOV16ri using decoder 30 |
| 1099 | // 40: } |
| 1100 | // 40: } |
| 1101 | 5, 4, // 44: case 0x5: { |
| 1102 | OPC_Decode, 162, 4, 31, // 46: decode to MOV8rm using decoder 31 |
| 1103 | // 46: } |
| 1104 | 7, 0, // 50: case 0x7: { |
| 1105 | OPC_CheckField, 8, 4, 0, // 52: check Inst[11:8] == 0x0 |
| 1106 | OPC_Decode, 161, 4, 32, // 56: decode to MOV8ri using decoder 32 |
| 1107 | // 56: } |
| 1108 | // 56: } // switch Inst[7:4] |
| 1109 | // 56: } |
| 1110 | 5, 35, // 60: case 0x5: { |
| 1111 | OPC_SwitchField, 4, 4, // 62: switch Inst[7:4] { |
| 1112 | 1, 4, // 65: case 0x1: { |
| 1113 | OPC_Decode, 203, 2, 33, // 67: decode to ADD16rm using decoder 33 |
| 1114 | // 67: } |
| 1115 | 3, 8, // 71: case 0x3: { |
| 1116 | OPC_CheckField, 8, 4, 0, // 73: check Inst[11:8] == 0x0 |
| 1117 | OPC_Decode, 202, 2, 34, // 77: decode to ADD16ri using decoder 34 |
| 1118 | // 77: } |
| 1119 | 5, 4, // 81: case 0x5: { |
| 1120 | OPC_Decode, 215, 2, 35, // 83: decode to ADD8rm using decoder 35 |
| 1121 | // 83: } |
| 1122 | 7, 0, // 87: case 0x7: { |
| 1123 | OPC_CheckField, 8, 4, 0, // 89: check Inst[11:8] == 0x0 |
| 1124 | OPC_Decode, 214, 2, 36, // 93: decode to ADD8ri using decoder 36 |
| 1125 | // 93: } |
| 1126 | // 93: } // switch Inst[7:4] |
| 1127 | // 93: } |
| 1128 | 6, 35, // 97: case 0x6: { |
| 1129 | OPC_SwitchField, 4, 4, // 99: switch Inst[7:4] { |
| 1130 | 1, 4, // 102: case 0x1: { |
| 1131 | OPC_Decode, 227, 2, 33, // 104: decode to ADDC16rm using decoder 33 |
| 1132 | // 104: } |
| 1133 | 3, 8, // 108: case 0x3: { |
| 1134 | OPC_CheckField, 8, 4, 0, // 110: check Inst[11:8] == 0x0 |
| 1135 | OPC_Decode, 226, 2, 34, // 114: decode to ADDC16ri using decoder 34 |
| 1136 | // 114: } |
| 1137 | 5, 4, // 118: case 0x5: { |
| 1138 | OPC_Decode, 239, 2, 35, // 120: decode to ADDC8rm using decoder 35 |
| 1139 | // 120: } |
| 1140 | 7, 0, // 124: case 0x7: { |
| 1141 | OPC_CheckField, 8, 4, 0, // 126: check Inst[11:8] == 0x0 |
| 1142 | OPC_Decode, 238, 2, 36, // 130: decode to ADDC8ri using decoder 36 |
| 1143 | // 130: } |
| 1144 | // 130: } // switch Inst[7:4] |
| 1145 | // 130: } |
| 1146 | 7, 35, // 134: case 0x7: { |
| 1147 | OPC_SwitchField, 4, 4, // 136: switch Inst[7:4] { |
| 1148 | 1, 4, // 139: case 0x1: { |
| 1149 | OPC_Decode, 229, 4, 33, // 141: decode to SUBC16rm using decoder 33 |
| 1150 | // 141: } |
| 1151 | 3, 8, // 145: case 0x3: { |
| 1152 | OPC_CheckField, 8, 4, 0, // 147: check Inst[11:8] == 0x0 |
| 1153 | OPC_Decode, 228, 4, 34, // 151: decode to SUBC16ri using decoder 34 |
| 1154 | // 151: } |
| 1155 | 5, 4, // 155: case 0x5: { |
| 1156 | OPC_Decode, 241, 4, 35, // 157: decode to SUBC8rm using decoder 35 |
| 1157 | // 157: } |
| 1158 | 7, 0, // 161: case 0x7: { |
| 1159 | OPC_CheckField, 8, 4, 0, // 163: check Inst[11:8] == 0x0 |
| 1160 | OPC_Decode, 240, 4, 36, // 167: decode to SUBC8ri using decoder 36 |
| 1161 | // 167: } |
| 1162 | // 167: } // switch Inst[7:4] |
| 1163 | // 167: } |
| 1164 | 8, 35, // 171: case 0x8: { |
| 1165 | OPC_SwitchField, 4, 4, // 173: switch Inst[7:4] { |
| 1166 | 1, 4, // 176: case 0x1: { |
| 1167 | OPC_Decode, 205, 4, 33, // 178: decode to SUB16rm using decoder 33 |
| 1168 | // 178: } |
| 1169 | 3, 8, // 182: case 0x3: { |
| 1170 | OPC_CheckField, 8, 4, 0, // 184: check Inst[11:8] == 0x0 |
| 1171 | OPC_Decode, 204, 4, 34, // 188: decode to SUB16ri using decoder 34 |
| 1172 | // 188: } |
| 1173 | 5, 4, // 192: case 0x5: { |
| 1174 | OPC_Decode, 217, 4, 35, // 194: decode to SUB8rm using decoder 35 |
| 1175 | // 194: } |
| 1176 | 7, 0, // 198: case 0x7: { |
| 1177 | OPC_CheckField, 8, 4, 0, // 200: check Inst[11:8] == 0x0 |
| 1178 | OPC_Decode, 216, 4, 36, // 204: decode to SUB8ri using decoder 36 |
| 1179 | // 204: } |
| 1180 | // 204: } // switch Inst[7:4] |
| 1181 | // 204: } |
| 1182 | 9, 35, // 208: case 0x9: { |
| 1183 | OPC_SwitchField, 4, 4, // 210: switch Inst[7:4] { |
| 1184 | 1, 4, // 213: case 0x1: { |
| 1185 | OPC_Decode, 230, 3, 29, // 215: decode to CMP16rm using decoder 29 |
| 1186 | // 215: } |
| 1187 | 3, 8, // 219: case 0x3: { |
| 1188 | OPC_CheckField, 8, 4, 0, // 221: check Inst[11:8] == 0x0 |
| 1189 | OPC_Decode, 229, 3, 30, // 225: decode to CMP16ri using decoder 30 |
| 1190 | // 225: } |
| 1191 | 5, 4, // 229: case 0x5: { |
| 1192 | OPC_Decode, 242, 3, 31, // 231: decode to CMP8rm using decoder 31 |
| 1193 | // 231: } |
| 1194 | 7, 0, // 235: case 0x7: { |
| 1195 | OPC_CheckField, 8, 4, 0, // 237: check Inst[11:8] == 0x0 |
| 1196 | OPC_Decode, 241, 3, 32, // 241: decode to CMP8ri using decoder 32 |
| 1197 | // 241: } |
| 1198 | // 241: } // switch Inst[7:4] |
| 1199 | // 241: } |
| 1200 | 10, 35, // 245: case 0xa: { |
| 1201 | OPC_SwitchField, 4, 4, // 247: switch Inst[7:4] { |
| 1202 | 1, 4, // 250: case 0x1: { |
| 1203 | OPC_Decode, 254, 3, 33, // 252: decode to DADD16rm using decoder 33 |
| 1204 | // 252: } |
| 1205 | 3, 8, // 256: case 0x3: { |
| 1206 | OPC_CheckField, 8, 4, 0, // 258: check Inst[11:8] == 0x0 |
| 1207 | OPC_Decode, 253, 3, 34, // 262: decode to DADD16ri using decoder 34 |
| 1208 | // 262: } |
| 1209 | 5, 4, // 266: case 0x5: { |
| 1210 | OPC_Decode, 138, 4, 35, // 268: decode to DADD8rm using decoder 35 |
| 1211 | // 268: } |
| 1212 | 7, 0, // 272: case 0x7: { |
| 1213 | OPC_CheckField, 8, 4, 0, // 274: check Inst[11:8] == 0x0 |
| 1214 | OPC_Decode, 137, 4, 36, // 278: decode to DADD8ri using decoder 36 |
| 1215 | // 278: } |
| 1216 | // 278: } // switch Inst[7:4] |
| 1217 | // 278: } |
| 1218 | 11, 35, // 282: case 0xb: { |
| 1219 | OPC_SwitchField, 4, 4, // 284: switch Inst[7:4] { |
| 1220 | 1, 4, // 287: case 0x1: { |
| 1221 | OPC_Decode, 198, 3, 29, // 289: decode to BIT16rm using decoder 29 |
| 1222 | // 289: } |
| 1223 | 3, 8, // 293: case 0x3: { |
| 1224 | OPC_CheckField, 8, 4, 0, // 295: check Inst[11:8] == 0x0 |
| 1225 | OPC_Decode, 197, 3, 30, // 299: decode to BIT16ri using decoder 30 |
| 1226 | // 299: } |
| 1227 | 5, 4, // 303: case 0x5: { |
| 1228 | OPC_Decode, 210, 3, 31, // 305: decode to BIT8rm using decoder 31 |
| 1229 | // 305: } |
| 1230 | 7, 0, // 309: case 0x7: { |
| 1231 | OPC_CheckField, 8, 4, 0, // 311: check Inst[11:8] == 0x0 |
| 1232 | OPC_Decode, 209, 3, 32, // 315: decode to BIT8ri using decoder 32 |
| 1233 | // 315: } |
| 1234 | // 315: } // switch Inst[7:4] |
| 1235 | // 315: } |
| 1236 | 12, 35, // 319: case 0xc: { |
| 1237 | OPC_SwitchField, 4, 4, // 321: switch Inst[7:4] { |
| 1238 | 1, 4, // 324: case 0x1: { |
| 1239 | OPC_Decode, 150, 3, 33, // 326: decode to BIC16rm using decoder 33 |
| 1240 | // 326: } |
| 1241 | 3, 8, // 330: case 0x3: { |
| 1242 | OPC_CheckField, 8, 4, 0, // 332: check Inst[11:8] == 0x0 |
| 1243 | OPC_Decode, 149, 3, 34, // 336: decode to BIC16ri using decoder 34 |
| 1244 | // 336: } |
| 1245 | 5, 4, // 340: case 0x5: { |
| 1246 | OPC_Decode, 162, 3, 35, // 342: decode to BIC8rm using decoder 35 |
| 1247 | // 342: } |
| 1248 | 7, 0, // 346: case 0x7: { |
| 1249 | OPC_CheckField, 8, 4, 0, // 348: check Inst[11:8] == 0x0 |
| 1250 | OPC_Decode, 161, 3, 36, // 352: decode to BIC8ri using decoder 36 |
| 1251 | // 352: } |
| 1252 | // 352: } // switch Inst[7:4] |
| 1253 | // 352: } |
| 1254 | 13, 35, // 356: case 0xd: { |
| 1255 | OPC_SwitchField, 4, 4, // 358: switch Inst[7:4] { |
| 1256 | 1, 4, // 361: case 0x1: { |
| 1257 | OPC_Decode, 174, 3, 33, // 363: decode to BIS16rm using decoder 33 |
| 1258 | // 363: } |
| 1259 | 3, 8, // 367: case 0x3: { |
| 1260 | OPC_CheckField, 8, 4, 0, // 369: check Inst[11:8] == 0x0 |
| 1261 | OPC_Decode, 173, 3, 34, // 373: decode to BIS16ri using decoder 34 |
| 1262 | // 373: } |
| 1263 | 5, 4, // 377: case 0x5: { |
| 1264 | OPC_Decode, 186, 3, 35, // 379: decode to BIS8rm using decoder 35 |
| 1265 | // 379: } |
| 1266 | 7, 0, // 383: case 0x7: { |
| 1267 | OPC_CheckField, 8, 4, 0, // 385: check Inst[11:8] == 0x0 |
| 1268 | OPC_Decode, 185, 3, 36, // 389: decode to BIS8ri using decoder 36 |
| 1269 | // 389: } |
| 1270 | // 389: } // switch Inst[7:4] |
| 1271 | // 389: } |
| 1272 | 14, 35, // 393: case 0xe: { |
| 1273 | OPC_SwitchField, 4, 4, // 395: switch Inst[7:4] { |
| 1274 | 1, 4, // 398: case 0x1: { |
| 1275 | OPC_Decode, 137, 5, 33, // 400: decode to XOR16rm using decoder 33 |
| 1276 | // 400: } |
| 1277 | 3, 8, // 404: case 0x3: { |
| 1278 | OPC_CheckField, 8, 4, 0, // 406: check Inst[11:8] == 0x0 |
| 1279 | OPC_Decode, 136, 5, 34, // 410: decode to XOR16ri using decoder 34 |
| 1280 | // 410: } |
| 1281 | 5, 4, // 414: case 0x5: { |
| 1282 | OPC_Decode, 149, 5, 35, // 416: decode to XOR8rm using decoder 35 |
| 1283 | // 416: } |
| 1284 | 7, 0, // 420: case 0x7: { |
| 1285 | OPC_CheckField, 8, 4, 0, // 422: check Inst[11:8] == 0x0 |
| 1286 | OPC_Decode, 148, 5, 36, // 426: decode to XOR8ri using decoder 36 |
| 1287 | // 426: } |
| 1288 | // 426: } // switch Inst[7:4] |
| 1289 | // 426: } |
| 1290 | 15, 0, // 430: case 0xf: { |
| 1291 | OPC_SwitchField, 4, 4, // 432: switch Inst[7:4] { |
| 1292 | 1, 4, // 435: case 0x1: { |
| 1293 | OPC_Decode, 254, 2, 33, // 437: decode to AND16rm using decoder 33 |
| 1294 | // 437: } |
| 1295 | 3, 8, // 441: case 0x3: { |
| 1296 | OPC_CheckField, 8, 4, 0, // 443: check Inst[11:8] == 0x0 |
| 1297 | OPC_Decode, 253, 2, 34, // 447: decode to AND16ri using decoder 34 |
| 1298 | // 447: } |
| 1299 | 5, 4, // 451: case 0x5: { |
| 1300 | OPC_Decode, 138, 3, 35, // 453: decode to AND8rm using decoder 35 |
| 1301 | // 453: } |
| 1302 | 7, 0, // 457: case 0x7: { |
| 1303 | OPC_CheckField, 8, 4, 0, // 459: check Inst[11:8] == 0x0 |
| 1304 | OPC_Decode, 137, 3, 36, // 463: decode to AND8ri using decoder 36 |
| 1305 | // 463: } |
| 1306 | // 463: } // switch Inst[7:4] |
| 1307 | // 463: } |
| 1308 | // 463: } // switch Inst[15:12] |
| 1309 | }; |
| 1310 | static const uint8_t DecoderTableGamma48[447] = { |
| 1311 | OPC_SwitchField, 12, 4, // 0: switch Inst[15:12] { |
| 1312 | 4, 35, // 3: case 0x4: { |
| 1313 | OPC_SwitchField, 4, 4, // 5: switch Inst[7:4] { |
| 1314 | 9, 4, // 8: case 0x9: { |
| 1315 | OPC_Decode, 146, 4, 37, // 10: decode to MOV16mm using decoder 37 |
| 1316 | // 10: } |
| 1317 | 11, 8, // 14: case 0xb: { |
| 1318 | OPC_CheckField, 8, 4, 0, // 16: check Inst[11:8] == 0x0 |
| 1319 | OPC_Decode, 145, 4, 38, // 20: decode to MOV16mi using decoder 38 |
| 1320 | // 20: } |
| 1321 | 13, 4, // 24: case 0xd: { |
| 1322 | OPC_Decode, 157, 4, 37, // 26: decode to MOV8mm using decoder 37 |
| 1323 | // 26: } |
| 1324 | 15, 0, // 30: case 0xf: { |
| 1325 | OPC_CheckField, 8, 4, 0, // 32: check Inst[11:8] == 0x0 |
| 1326 | OPC_Decode, 156, 4, 38, // 36: decode to MOV8mi using decoder 38 |
| 1327 | // 36: } |
| 1328 | // 36: } // switch Inst[7:4] |
| 1329 | // 36: } |
| 1330 | 5, 35, // 40: case 0x5: { |
| 1331 | OPC_SwitchField, 4, 4, // 42: switch Inst[7:4] { |
| 1332 | 9, 4, // 45: case 0x9: { |
| 1333 | OPC_Decode, 197, 2, 37, // 47: decode to ADD16mm using decoder 37 |
| 1334 | // 47: } |
| 1335 | 11, 8, // 51: case 0xb: { |
| 1336 | OPC_CheckField, 8, 4, 0, // 53: check Inst[11:8] == 0x0 |
| 1337 | OPC_Decode, 196, 2, 38, // 57: decode to ADD16mi using decoder 38 |
| 1338 | // 57: } |
| 1339 | 13, 4, // 61: case 0xd: { |
| 1340 | OPC_Decode, 209, 2, 37, // 63: decode to ADD8mm using decoder 37 |
| 1341 | // 63: } |
| 1342 | 15, 0, // 67: case 0xf: { |
| 1343 | OPC_CheckField, 8, 4, 0, // 69: check Inst[11:8] == 0x0 |
| 1344 | OPC_Decode, 208, 2, 38, // 73: decode to ADD8mi using decoder 38 |
| 1345 | // 73: } |
| 1346 | // 73: } // switch Inst[7:4] |
| 1347 | // 73: } |
| 1348 | 6, 35, // 77: case 0x6: { |
| 1349 | OPC_SwitchField, 4, 4, // 79: switch Inst[7:4] { |
| 1350 | 9, 4, // 82: case 0x9: { |
| 1351 | OPC_Decode, 221, 2, 37, // 84: decode to ADDC16mm using decoder 37 |
| 1352 | // 84: } |
| 1353 | 11, 8, // 88: case 0xb: { |
| 1354 | OPC_CheckField, 8, 4, 0, // 90: check Inst[11:8] == 0x0 |
| 1355 | OPC_Decode, 220, 2, 38, // 94: decode to ADDC16mi using decoder 38 |
| 1356 | // 94: } |
| 1357 | 13, 4, // 98: case 0xd: { |
| 1358 | OPC_Decode, 233, 2, 37, // 100: decode to ADDC8mm using decoder 37 |
| 1359 | // 100: } |
| 1360 | 15, 0, // 104: case 0xf: { |
| 1361 | OPC_CheckField, 8, 4, 0, // 106: check Inst[11:8] == 0x0 |
| 1362 | OPC_Decode, 232, 2, 38, // 110: decode to ADDC8mi using decoder 38 |
| 1363 | // 110: } |
| 1364 | // 110: } // switch Inst[7:4] |
| 1365 | // 110: } |
| 1366 | 7, 35, // 114: case 0x7: { |
| 1367 | OPC_SwitchField, 4, 4, // 116: switch Inst[7:4] { |
| 1368 | 9, 4, // 119: case 0x9: { |
| 1369 | OPC_Decode, 223, 4, 37, // 121: decode to SUBC16mm using decoder 37 |
| 1370 | // 121: } |
| 1371 | 11, 8, // 125: case 0xb: { |
| 1372 | OPC_CheckField, 8, 4, 0, // 127: check Inst[11:8] == 0x0 |
| 1373 | OPC_Decode, 222, 4, 38, // 131: decode to SUBC16mi using decoder 38 |
| 1374 | // 131: } |
| 1375 | 13, 4, // 135: case 0xd: { |
| 1376 | OPC_Decode, 235, 4, 37, // 137: decode to SUBC8mm using decoder 37 |
| 1377 | // 137: } |
| 1378 | 15, 0, // 141: case 0xf: { |
| 1379 | OPC_CheckField, 8, 4, 0, // 143: check Inst[11:8] == 0x0 |
| 1380 | OPC_Decode, 234, 4, 38, // 147: decode to SUBC8mi using decoder 38 |
| 1381 | // 147: } |
| 1382 | // 147: } // switch Inst[7:4] |
| 1383 | // 147: } |
| 1384 | 8, 35, // 151: case 0x8: { |
| 1385 | OPC_SwitchField, 4, 4, // 153: switch Inst[7:4] { |
| 1386 | 9, 4, // 156: case 0x9: { |
| 1387 | OPC_Decode, 199, 4, 37, // 158: decode to SUB16mm using decoder 37 |
| 1388 | // 158: } |
| 1389 | 11, 8, // 162: case 0xb: { |
| 1390 | OPC_CheckField, 8, 4, 0, // 164: check Inst[11:8] == 0x0 |
| 1391 | OPC_Decode, 198, 4, 38, // 168: decode to SUB16mi using decoder 38 |
| 1392 | // 168: } |
| 1393 | 13, 4, // 172: case 0xd: { |
| 1394 | OPC_Decode, 211, 4, 37, // 174: decode to SUB8mm using decoder 37 |
| 1395 | // 174: } |
| 1396 | 15, 0, // 178: case 0xf: { |
| 1397 | OPC_CheckField, 8, 4, 0, // 180: check Inst[11:8] == 0x0 |
| 1398 | OPC_Decode, 210, 4, 38, // 184: decode to SUB8mi using decoder 38 |
| 1399 | // 184: } |
| 1400 | // 184: } // switch Inst[7:4] |
| 1401 | // 184: } |
| 1402 | 9, 35, // 188: case 0x9: { |
| 1403 | OPC_SwitchField, 4, 4, // 190: switch Inst[7:4] { |
| 1404 | 9, 4, // 193: case 0x9: { |
| 1405 | OPC_Decode, 224, 3, 37, // 195: decode to CMP16mm using decoder 37 |
| 1406 | // 195: } |
| 1407 | 11, 8, // 199: case 0xb: { |
| 1408 | OPC_CheckField, 8, 4, 0, // 201: check Inst[11:8] == 0x0 |
| 1409 | OPC_Decode, 223, 3, 38, // 205: decode to CMP16mi using decoder 38 |
| 1410 | // 205: } |
| 1411 | 13, 4, // 209: case 0xd: { |
| 1412 | OPC_Decode, 236, 3, 37, // 211: decode to CMP8mm using decoder 37 |
| 1413 | // 211: } |
| 1414 | 15, 0, // 215: case 0xf: { |
| 1415 | OPC_CheckField, 8, 4, 0, // 217: check Inst[11:8] == 0x0 |
| 1416 | OPC_Decode, 235, 3, 38, // 221: decode to CMP8mi using decoder 38 |
| 1417 | // 221: } |
| 1418 | // 221: } // switch Inst[7:4] |
| 1419 | // 221: } |
| 1420 | 10, 35, // 225: case 0xa: { |
| 1421 | OPC_SwitchField, 4, 4, // 227: switch Inst[7:4] { |
| 1422 | 9, 4, // 230: case 0x9: { |
| 1423 | OPC_Decode, 248, 3, 37, // 232: decode to DADD16mm using decoder 37 |
| 1424 | // 232: } |
| 1425 | 11, 8, // 236: case 0xb: { |
| 1426 | OPC_CheckField, 8, 4, 0, // 238: check Inst[11:8] == 0x0 |
| 1427 | OPC_Decode, 247, 3, 38, // 242: decode to DADD16mi using decoder 38 |
| 1428 | // 242: } |
| 1429 | 13, 4, // 246: case 0xd: { |
| 1430 | OPC_Decode, 132, 4, 37, // 248: decode to DADD8mm using decoder 37 |
| 1431 | // 248: } |
| 1432 | 15, 0, // 252: case 0xf: { |
| 1433 | OPC_CheckField, 8, 4, 0, // 254: check Inst[11:8] == 0x0 |
| 1434 | OPC_Decode, 131, 4, 38, // 258: decode to DADD8mi using decoder 38 |
| 1435 | // 258: } |
| 1436 | // 258: } // switch Inst[7:4] |
| 1437 | // 258: } |
| 1438 | 11, 35, // 262: case 0xb: { |
| 1439 | OPC_SwitchField, 4, 4, // 264: switch Inst[7:4] { |
| 1440 | 9, 4, // 267: case 0x9: { |
| 1441 | OPC_Decode, 192, 3, 37, // 269: decode to BIT16mm using decoder 37 |
| 1442 | // 269: } |
| 1443 | 11, 8, // 273: case 0xb: { |
| 1444 | OPC_CheckField, 8, 4, 0, // 275: check Inst[11:8] == 0x0 |
| 1445 | OPC_Decode, 191, 3, 38, // 279: decode to BIT16mi using decoder 38 |
| 1446 | // 279: } |
| 1447 | 13, 4, // 283: case 0xd: { |
| 1448 | OPC_Decode, 204, 3, 37, // 285: decode to BIT8mm using decoder 37 |
| 1449 | // 285: } |
| 1450 | 15, 0, // 289: case 0xf: { |
| 1451 | OPC_CheckField, 8, 4, 0, // 291: check Inst[11:8] == 0x0 |
| 1452 | OPC_Decode, 203, 3, 38, // 295: decode to BIT8mi using decoder 38 |
| 1453 | // 295: } |
| 1454 | // 295: } // switch Inst[7:4] |
| 1455 | // 295: } |
| 1456 | 12, 35, // 299: case 0xc: { |
| 1457 | OPC_SwitchField, 4, 4, // 301: switch Inst[7:4] { |
| 1458 | 9, 4, // 304: case 0x9: { |
| 1459 | OPC_Decode, 144, 3, 37, // 306: decode to BIC16mm using decoder 37 |
| 1460 | // 306: } |
| 1461 | 11, 8, // 310: case 0xb: { |
| 1462 | OPC_CheckField, 8, 4, 0, // 312: check Inst[11:8] == 0x0 |
| 1463 | OPC_Decode, 143, 3, 38, // 316: decode to BIC16mi using decoder 38 |
| 1464 | // 316: } |
| 1465 | 13, 4, // 320: case 0xd: { |
| 1466 | OPC_Decode, 156, 3, 37, // 322: decode to BIC8mm using decoder 37 |
| 1467 | // 322: } |
| 1468 | 15, 0, // 326: case 0xf: { |
| 1469 | OPC_CheckField, 8, 4, 0, // 328: check Inst[11:8] == 0x0 |
| 1470 | OPC_Decode, 155, 3, 38, // 332: decode to BIC8mi using decoder 38 |
| 1471 | // 332: } |
| 1472 | // 332: } // switch Inst[7:4] |
| 1473 | // 332: } |
| 1474 | 13, 35, // 336: case 0xd: { |
| 1475 | OPC_SwitchField, 4, 4, // 338: switch Inst[7:4] { |
| 1476 | 9, 4, // 341: case 0x9: { |
| 1477 | OPC_Decode, 168, 3, 37, // 343: decode to BIS16mm using decoder 37 |
| 1478 | // 343: } |
| 1479 | 11, 8, // 347: case 0xb: { |
| 1480 | OPC_CheckField, 8, 4, 0, // 349: check Inst[11:8] == 0x0 |
| 1481 | OPC_Decode, 167, 3, 38, // 353: decode to BIS16mi using decoder 38 |
| 1482 | // 353: } |
| 1483 | 13, 4, // 357: case 0xd: { |
| 1484 | OPC_Decode, 180, 3, 37, // 359: decode to BIS8mm using decoder 37 |
| 1485 | // 359: } |
| 1486 | 15, 0, // 363: case 0xf: { |
| 1487 | OPC_CheckField, 8, 4, 0, // 365: check Inst[11:8] == 0x0 |
| 1488 | OPC_Decode, 179, 3, 38, // 369: decode to BIS8mi using decoder 38 |
| 1489 | // 369: } |
| 1490 | // 369: } // switch Inst[7:4] |
| 1491 | // 369: } |
| 1492 | 14, 35, // 373: case 0xe: { |
| 1493 | OPC_SwitchField, 4, 4, // 375: switch Inst[7:4] { |
| 1494 | 9, 4, // 378: case 0x9: { |
| 1495 | OPC_Decode, 131, 5, 37, // 380: decode to XOR16mm using decoder 37 |
| 1496 | // 380: } |
| 1497 | 11, 8, // 384: case 0xb: { |
| 1498 | OPC_CheckField, 8, 4, 0, // 386: check Inst[11:8] == 0x0 |
| 1499 | OPC_Decode, 130, 5, 38, // 390: decode to XOR16mi using decoder 38 |
| 1500 | // 390: } |
| 1501 | 13, 4, // 394: case 0xd: { |
| 1502 | OPC_Decode, 143, 5, 37, // 396: decode to XOR8mm using decoder 37 |
| 1503 | // 396: } |
| 1504 | 15, 0, // 400: case 0xf: { |
| 1505 | OPC_CheckField, 8, 4, 0, // 402: check Inst[11:8] == 0x0 |
| 1506 | OPC_Decode, 142, 5, 38, // 406: decode to XOR8mi using decoder 38 |
| 1507 | // 406: } |
| 1508 | // 406: } // switch Inst[7:4] |
| 1509 | // 406: } |
| 1510 | 15, 0, // 410: case 0xf: { |
| 1511 | OPC_SwitchField, 4, 4, // 412: switch Inst[7:4] { |
| 1512 | 9, 4, // 415: case 0x9: { |
| 1513 | OPC_Decode, 248, 2, 37, // 417: decode to AND16mm using decoder 37 |
| 1514 | // 417: } |
| 1515 | 11, 8, // 421: case 0xb: { |
| 1516 | OPC_CheckField, 8, 4, 0, // 423: check Inst[11:8] == 0x0 |
| 1517 | OPC_Decode, 247, 2, 38, // 427: decode to AND16mi using decoder 38 |
| 1518 | // 427: } |
| 1519 | 13, 4, // 431: case 0xd: { |
| 1520 | OPC_Decode, 132, 3, 37, // 433: decode to AND8mm using decoder 37 |
| 1521 | // 433: } |
| 1522 | 15, 0, // 437: case 0xf: { |
| 1523 | OPC_CheckField, 8, 4, 0, // 439: check Inst[11:8] == 0x0 |
| 1524 | OPC_Decode, 131, 3, 38, // 443: decode to AND8mi using decoder 38 |
| 1525 | // 443: } |
| 1526 | // 443: } // switch Inst[7:4] |
| 1527 | // 443: } |
| 1528 | // 443: } // switch Inst[15:12] |
| 1529 | }; |
| 1530 | // Handling 39 cases. |
| 1531 | template <typename InsnType> |
| 1532 | static DecodeStatus decodeToMCInst(unsigned Idx, DecodeStatus S, InsnType insn, MCInst &MI, uint64_t Address, const MCDisassembler *Decoder, bool &DecodeComplete) { |
| 1533 | DecodeComplete = true; |
| 1534 | using TmpType = std::conditional_t<std::is_integral<InsnType>::value, InsnType, uint64_t>; |
| 1535 | TmpType tmp; |
| 1536 | switch (Idx) { |
| 1537 | default: llvm_unreachable("Invalid decoder index!" ); |
| 1538 | case 0: |
| 1539 | tmp = fieldFromInstruction(insn, 0, 4); |
| 1540 | if (!Check(S, DecodeGR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 1541 | tmp = fieldFromInstruction(insn, 0, 4); |
| 1542 | if (!Check(S, DecodeGR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 1543 | return S; |
| 1544 | case 1: |
| 1545 | tmp = fieldFromInstruction(insn, 0, 4); |
| 1546 | if (!Check(S, DecodeGR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 1547 | return S; |
| 1548 | case 2: |
| 1549 | tmp = fieldFromInstruction(insn, 0, 4); |
| 1550 | if (!Check(S, DecodeGR8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 1551 | tmp = fieldFromInstruction(insn, 0, 4); |
| 1552 | if (!Check(S, DecodeGR8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 1553 | return S; |
| 1554 | case 3: |
| 1555 | tmp = fieldFromInstruction(insn, 0, 6); |
| 1556 | if (!Check(S, DecodeCGImm(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 1557 | return S; |
| 1558 | case 4: |
| 1559 | tmp = fieldFromInstruction(insn, 0, 4); |
| 1560 | if (!Check(S, DecodeGR8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 1561 | return S; |
| 1562 | case 5: |
| 1563 | return S; |
| 1564 | case 6: |
| 1565 | tmp = fieldFromInstruction(insn, 0, 10); |
| 1566 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 1567 | return S; |
| 1568 | case 7: |
| 1569 | tmp = fieldFromInstruction(insn, 0, 10); |
| 1570 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 1571 | tmp = fieldFromInstruction(insn, 10, 3); |
| 1572 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 1573 | return S; |
| 1574 | case 8: |
| 1575 | tmp = fieldFromInstruction(insn, 8, 4); |
| 1576 | if (!Check(S, DecodeGR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 1577 | return S; |
| 1578 | case 9: |
| 1579 | tmp = fieldFromInstruction(insn, 0, 4); |
| 1580 | if (!Check(S, DecodeGR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 1581 | tmp = fieldFromInstruction(insn, 8, 4); |
| 1582 | if (!Check(S, DecodeGR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 1583 | return S; |
| 1584 | case 10: |
| 1585 | tmp = fieldFromInstruction(insn, 0, 4); |
| 1586 | if (!Check(S, DecodeGR8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 1587 | tmp = fieldFromInstruction(insn, 8, 4); |
| 1588 | if (!Check(S, DecodeGR8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 1589 | return S; |
| 1590 | case 11: |
| 1591 | tmp = fieldFromInstruction(insn, 0, 4); |
| 1592 | if (!Check(S, DecodeGR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 1593 | tmp = fieldFromInstruction(insn, 0, 4); |
| 1594 | if (!Check(S, DecodeGR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 1595 | tmp = fieldFromInstruction(insn, 8, 4); |
| 1596 | if (!Check(S, DecodeGR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 1597 | return S; |
| 1598 | case 12: |
| 1599 | tmp = fieldFromInstruction(insn, 0, 4); |
| 1600 | if (!Check(S, DecodeGR8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 1601 | tmp = fieldFromInstruction(insn, 0, 4); |
| 1602 | if (!Check(S, DecodeGR8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 1603 | tmp = fieldFromInstruction(insn, 8, 4); |
| 1604 | if (!Check(S, DecodeGR8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 1605 | return S; |
| 1606 | case 13: |
| 1607 | tmp = fieldFromInstruction(insn, 0, 4); |
| 1608 | if (!Check(S, DecodeGR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 1609 | tmp = 0x0; |
| 1610 | tmp |= fieldFromInstruction(insn, 4, 2) << 4; |
| 1611 | tmp |= fieldFromInstruction(insn, 8, 4); |
| 1612 | if (!Check(S, DecodeCGImm(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 1613 | return S; |
| 1614 | case 14: |
| 1615 | tmp = fieldFromInstruction(insn, 0, 4); |
| 1616 | if (!Check(S, DecodeGR8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 1617 | tmp = 0x0; |
| 1618 | tmp |= fieldFromInstruction(insn, 4, 2) << 4; |
| 1619 | tmp |= fieldFromInstruction(insn, 8, 4); |
| 1620 | if (!Check(S, DecodeCGImm(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 1621 | return S; |
| 1622 | case 15: |
| 1623 | tmp = fieldFromInstruction(insn, 0, 4); |
| 1624 | if (!Check(S, DecodeGR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 1625 | tmp = fieldFromInstruction(insn, 0, 4); |
| 1626 | if (!Check(S, DecodeGR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 1627 | tmp = 0x0; |
| 1628 | tmp |= fieldFromInstruction(insn, 4, 2) << 4; |
| 1629 | tmp |= fieldFromInstruction(insn, 8, 4); |
| 1630 | if (!Check(S, DecodeCGImm(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 1631 | return S; |
| 1632 | case 16: |
| 1633 | tmp = fieldFromInstruction(insn, 0, 4); |
| 1634 | if (!Check(S, DecodeGR8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 1635 | tmp = fieldFromInstruction(insn, 0, 4); |
| 1636 | if (!Check(S, DecodeGR8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 1637 | tmp = 0x0; |
| 1638 | tmp |= fieldFromInstruction(insn, 4, 2) << 4; |
| 1639 | tmp |= fieldFromInstruction(insn, 8, 4); |
| 1640 | if (!Check(S, DecodeCGImm(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 1641 | return S; |
| 1642 | case 17: |
| 1643 | tmp = fieldFromInstruction(insn, 0, 4); |
| 1644 | if (!Check(S, DecodeGR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 1645 | tmp = fieldFromInstruction(insn, 8, 4); |
| 1646 | if (!Check(S, DecodeGR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 1647 | tmp = fieldFromInstruction(insn, 8, 4); |
| 1648 | if (!Check(S, DecodeGR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 1649 | return S; |
| 1650 | case 18: |
| 1651 | tmp = fieldFromInstruction(insn, 0, 4); |
| 1652 | if (!Check(S, DecodeGR8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 1653 | tmp = fieldFromInstruction(insn, 8, 4); |
| 1654 | if (!Check(S, DecodeGR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 1655 | return S; |
| 1656 | case 19: |
| 1657 | tmp = fieldFromInstruction(insn, 0, 4); |
| 1658 | if (!Check(S, DecodeGR8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 1659 | tmp = fieldFromInstruction(insn, 8, 4); |
| 1660 | if (!Check(S, DecodeGR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 1661 | tmp = fieldFromInstruction(insn, 8, 4); |
| 1662 | if (!Check(S, DecodeGR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 1663 | return S; |
| 1664 | case 20: |
| 1665 | tmp = fieldFromInstruction(insn, 0, 4); |
| 1666 | if (!Check(S, DecodeGR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 1667 | tmp = fieldFromInstruction(insn, 8, 4); |
| 1668 | if (!Check(S, DecodeGR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 1669 | tmp = fieldFromInstruction(insn, 0, 4); |
| 1670 | if (!Check(S, DecodeGR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 1671 | tmp = fieldFromInstruction(insn, 8, 4); |
| 1672 | if (!Check(S, DecodeGR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 1673 | return S; |
| 1674 | case 21: |
| 1675 | tmp = fieldFromInstruction(insn, 0, 4); |
| 1676 | if (!Check(S, DecodeGR8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 1677 | tmp = fieldFromInstruction(insn, 0, 4); |
| 1678 | if (!Check(S, DecodeGR8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 1679 | tmp = fieldFromInstruction(insn, 8, 4); |
| 1680 | if (!Check(S, DecodeGR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 1681 | return S; |
| 1682 | case 22: |
| 1683 | tmp = fieldFromInstruction(insn, 0, 4); |
| 1684 | if (!Check(S, DecodeGR8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 1685 | tmp = fieldFromInstruction(insn, 8, 4); |
| 1686 | if (!Check(S, DecodeGR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 1687 | tmp = fieldFromInstruction(insn, 0, 4); |
| 1688 | if (!Check(S, DecodeGR8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 1689 | tmp = fieldFromInstruction(insn, 8, 4); |
| 1690 | if (!Check(S, DecodeGR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 1691 | return S; |
| 1692 | case 23: |
| 1693 | tmp = 0x0; |
| 1694 | tmp |= fieldFromInstruction(insn, 0, 4); |
| 1695 | tmp |= fieldFromInstruction(insn, 16, 16) << 4; |
| 1696 | if (!Check(S, DecodeMemOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 1697 | return S; |
| 1698 | case 24: |
| 1699 | tmp = fieldFromInstruction(insn, 16, 16); |
| 1700 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 1701 | return S; |
| 1702 | case 25: |
| 1703 | tmp = 0x0; |
| 1704 | tmp |= fieldFromInstruction(insn, 0, 4); |
| 1705 | tmp |= fieldFromInstruction(insn, 16, 16) << 4; |
| 1706 | if (!Check(S, DecodeMemOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 1707 | tmp = fieldFromInstruction(insn, 8, 4); |
| 1708 | if (!Check(S, DecodeGR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 1709 | return S; |
| 1710 | case 26: |
| 1711 | tmp = 0x0; |
| 1712 | tmp |= fieldFromInstruction(insn, 0, 4); |
| 1713 | tmp |= fieldFromInstruction(insn, 16, 16) << 4; |
| 1714 | if (!Check(S, DecodeMemOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 1715 | tmp = fieldFromInstruction(insn, 8, 4); |
| 1716 | if (!Check(S, DecodeGR8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 1717 | return S; |
| 1718 | case 27: |
| 1719 | tmp = 0x0; |
| 1720 | tmp |= fieldFromInstruction(insn, 0, 4); |
| 1721 | tmp |= fieldFromInstruction(insn, 16, 16) << 4; |
| 1722 | if (!Check(S, DecodeMemOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 1723 | tmp = 0x0; |
| 1724 | tmp |= fieldFromInstruction(insn, 4, 2) << 4; |
| 1725 | tmp |= fieldFromInstruction(insn, 8, 4); |
| 1726 | if (!Check(S, DecodeCGImm(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 1727 | return S; |
| 1728 | case 28: |
| 1729 | tmp = 0x0; |
| 1730 | tmp |= fieldFromInstruction(insn, 8, 4); |
| 1731 | tmp |= fieldFromInstruction(insn, 16, 16) << 4; |
| 1732 | if (!Check(S, DecodeMemOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 1733 | return S; |
| 1734 | case 29: |
| 1735 | tmp = fieldFromInstruction(insn, 0, 4); |
| 1736 | if (!Check(S, DecodeGR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 1737 | tmp = 0x0; |
| 1738 | tmp |= fieldFromInstruction(insn, 8, 4); |
| 1739 | tmp |= fieldFromInstruction(insn, 16, 16) << 4; |
| 1740 | if (!Check(S, DecodeMemOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 1741 | return S; |
| 1742 | case 30: |
| 1743 | tmp = fieldFromInstruction(insn, 0, 4); |
| 1744 | if (!Check(S, DecodeGR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 1745 | tmp = fieldFromInstruction(insn, 16, 16); |
| 1746 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 1747 | return S; |
| 1748 | case 31: |
| 1749 | tmp = fieldFromInstruction(insn, 0, 4); |
| 1750 | if (!Check(S, DecodeGR8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 1751 | tmp = 0x0; |
| 1752 | tmp |= fieldFromInstruction(insn, 8, 4); |
| 1753 | tmp |= fieldFromInstruction(insn, 16, 16) << 4; |
| 1754 | if (!Check(S, DecodeMemOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 1755 | return S; |
| 1756 | case 32: |
| 1757 | tmp = fieldFromInstruction(insn, 0, 4); |
| 1758 | if (!Check(S, DecodeGR8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 1759 | tmp = fieldFromInstruction(insn, 16, 16); |
| 1760 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 1761 | return S; |
| 1762 | case 33: |
| 1763 | tmp = fieldFromInstruction(insn, 0, 4); |
| 1764 | if (!Check(S, DecodeGR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 1765 | tmp = fieldFromInstruction(insn, 0, 4); |
| 1766 | if (!Check(S, DecodeGR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 1767 | tmp = 0x0; |
| 1768 | tmp |= fieldFromInstruction(insn, 8, 4); |
| 1769 | tmp |= fieldFromInstruction(insn, 16, 16) << 4; |
| 1770 | if (!Check(S, DecodeMemOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 1771 | return S; |
| 1772 | case 34: |
| 1773 | tmp = fieldFromInstruction(insn, 0, 4); |
| 1774 | if (!Check(S, DecodeGR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 1775 | tmp = fieldFromInstruction(insn, 0, 4); |
| 1776 | if (!Check(S, DecodeGR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 1777 | tmp = fieldFromInstruction(insn, 16, 16); |
| 1778 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 1779 | return S; |
| 1780 | case 35: |
| 1781 | tmp = fieldFromInstruction(insn, 0, 4); |
| 1782 | if (!Check(S, DecodeGR8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 1783 | tmp = fieldFromInstruction(insn, 0, 4); |
| 1784 | if (!Check(S, DecodeGR8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 1785 | tmp = 0x0; |
| 1786 | tmp |= fieldFromInstruction(insn, 8, 4); |
| 1787 | tmp |= fieldFromInstruction(insn, 16, 16) << 4; |
| 1788 | if (!Check(S, DecodeMemOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 1789 | return S; |
| 1790 | case 36: |
| 1791 | tmp = fieldFromInstruction(insn, 0, 4); |
| 1792 | if (!Check(S, DecodeGR8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 1793 | tmp = fieldFromInstruction(insn, 0, 4); |
| 1794 | if (!Check(S, DecodeGR8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 1795 | tmp = fieldFromInstruction(insn, 16, 16); |
| 1796 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 1797 | return S; |
| 1798 | case 37: |
| 1799 | tmp = 0x0; |
| 1800 | tmp |= fieldFromInstruction(insn, 0, 4); |
| 1801 | tmp |= fieldFromInstruction(insn, 32, 16) << 4; |
| 1802 | if (!Check(S, DecodeMemOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 1803 | tmp = 0x0; |
| 1804 | tmp |= fieldFromInstruction(insn, 8, 4); |
| 1805 | tmp |= fieldFromInstruction(insn, 16, 16) << 4; |
| 1806 | if (!Check(S, DecodeMemOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 1807 | return S; |
| 1808 | case 38: |
| 1809 | tmp = 0x0; |
| 1810 | tmp |= fieldFromInstruction(insn, 0, 4); |
| 1811 | tmp |= fieldFromInstruction(insn, 32, 16) << 4; |
| 1812 | if (!Check(S, DecodeMemOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 1813 | tmp = fieldFromInstruction(insn, 16, 16); |
| 1814 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 1815 | return S; |
| 1816 | } |
| 1817 | } |
| 1818 | |
| 1819 | template <typename InsnType> |
| 1820 | static DecodeStatus decodeInstruction(const uint8_t DecodeTable[], MCInst &MI, |
| 1821 | InsnType insn, uint64_t Address, |
| 1822 | const MCDisassembler *DisAsm, |
| 1823 | const MCSubtargetInfo &STI) { |
| 1824 | const uint8_t *Ptr = DecodeTable; |
| 1825 | |
| 1826 | SmallVector<const uint8_t *, 8> ScopeStack; |
| 1827 | DecodeStatus S = MCDisassembler::Success; |
| 1828 | while (true) { |
| 1829 | ptrdiff_t Loc = Ptr - DecodeTable; |
| 1830 | const uint8_t DecoderOp = *Ptr++; |
| 1831 | switch (DecoderOp) { |
| 1832 | default: |
| 1833 | errs() << Loc << ": Unexpected decode table opcode: " |
| 1834 | << (int)DecoderOp << '\n'; |
| 1835 | return MCDisassembler::Fail; |
| 1836 | case OPC_Scope: { |
| 1837 | unsigned NumToSkip = decodeULEB128AndIncUnsafe(p&: Ptr); |
| 1838 | const uint8_t *SkipTo = Ptr + NumToSkip; |
| 1839 | ScopeStack.push_back(Elt: SkipTo); |
| 1840 | LLVM_DEBUG(dbgs() << Loc << ": OPC_Scope(" << SkipTo - DecodeTable |
| 1841 | << ")\n" ); |
| 1842 | continue; |
| 1843 | } |
| 1844 | case OPC_SwitchField: { |
| 1845 | // Decode the start value. |
| 1846 | unsigned Start = decodeULEB128AndIncUnsafe(p&: Ptr); |
| 1847 | unsigned Len = *Ptr++; |
| 1848 | uint64_t FieldValue = fieldFromInstruction(insn, Start, Len); |
| 1849 | uint64_t CaseValue; |
| 1850 | unsigned CaseSize; |
| 1851 | while (true) { |
| 1852 | CaseValue = decodeULEB128AndIncUnsafe(p&: Ptr); |
| 1853 | CaseSize = decodeULEB128AndIncUnsafe(p&: Ptr); |
| 1854 | if (FieldValue == CaseValue || !CaseSize) |
| 1855 | break; |
| 1856 | Ptr += CaseSize; |
| 1857 | } |
| 1858 | if (FieldValue == CaseValue) { |
| 1859 | LLVM_DEBUG(dbgs() << Loc << ": OPC_SwitchField(" << Start << ", " << Len |
| 1860 | << "): " << FieldValue << '\n'); |
| 1861 | continue; |
| 1862 | } |
| 1863 | break; |
| 1864 | } |
| 1865 | case OPC_CheckField: { |
| 1866 | // Decode the start value. |
| 1867 | unsigned Start = decodeULEB128AndIncUnsafe(p&: Ptr); |
| 1868 | unsigned Len = *Ptr; |
| 1869 | uint64_t FieldValue = fieldFromInstruction(insn, Start, Len); |
| 1870 | // Decode the field value. |
| 1871 | unsigned PtrLen = 0; |
| 1872 | uint64_t ExpectedValue = decodeULEB128(p: ++Ptr, n: &PtrLen); |
| 1873 | Ptr += PtrLen; |
| 1874 | bool Failed = ExpectedValue != FieldValue; |
| 1875 | |
| 1876 | LLVM_DEBUG(dbgs() << Loc << ": OPC_CheckField(" << Start << ", " << Len |
| 1877 | << ", " << ExpectedValue << "): FieldValue = " |
| 1878 | << FieldValue << ", ExpectedValue = " << ExpectedValue |
| 1879 | << ": " << (Failed ? "FAIL, " : "PASS\n" );); |
| 1880 | if (!Failed) |
| 1881 | continue; |
| 1882 | break; |
| 1883 | } |
| 1884 | case OPC_Decode: { |
| 1885 | // Decode the Opcode value. |
| 1886 | unsigned Opc = decodeULEB128AndIncUnsafe(p&: Ptr); |
| 1887 | unsigned DecodeIdx = decodeULEB128AndIncUnsafe(p&: Ptr); |
| 1888 | |
| 1889 | MI.clear(); |
| 1890 | MI.setOpcode(Opc); |
| 1891 | bool DecodeComplete; |
| 1892 | S = decodeToMCInst(DecodeIdx, S, insn, MI, Address, DisAsm, |
| 1893 | DecodeComplete); |
| 1894 | LLVM_DEBUG(dbgs() << Loc << ": OPC_Decode: opcode " << Opc |
| 1895 | << ", using decoder " << DecodeIdx << ": " |
| 1896 | << (S ? "PASS, " : "FAIL, " )); |
| 1897 | |
| 1898 | if (DecodeComplete) { |
| 1899 | LLVM_DEBUG(dbgs() << "decoding complete\n" ); |
| 1900 | return S; |
| 1901 | } |
| 1902 | assert(S == MCDisassembler::Fail); |
| 1903 | // Reset decode status. This also drops a SoftFail status that could be |
| 1904 | // set before the decode attempt. |
| 1905 | S = MCDisassembler::Success; |
| 1906 | break; |
| 1907 | } |
| 1908 | } |
| 1909 | if (ScopeStack.empty()) { |
| 1910 | LLVM_DEBUG(dbgs() << "returning Fail\n" ); |
| 1911 | return MCDisassembler::Fail; |
| 1912 | } |
| 1913 | Ptr = ScopeStack.pop_back_val(); |
| 1914 | LLVM_DEBUG(dbgs() << "continuing at " << Ptr - DecodeTable << '\n'); |
| 1915 | } |
| 1916 | llvm_unreachable("bogosity detected in disassembler state machine!" ); |
| 1917 | } |
| 1918 | |
| 1919 | |
| 1920 | } // namespace |
| 1921 | |