1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Instruction Enum Values and Descriptors *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_INSTRINFO_ENUM
10#undef GET_INSTRINFO_ENUM
11
12namespace llvm::MSP430 {
13
14 enum {
15 PHI = 0, // Target.td:1324
16 INLINEASM = 1, // Target.td:1330
17 INLINEASM_BR = 2, // Target.td:1336
18 CFI_INSTRUCTION = 3, // Target.td:1345
19 EH_LABEL = 4, // Target.td:1354
20 GC_LABEL = 5, // Target.td:1363
21 ANNOTATION_LABEL = 6, // Target.td:1372
22 KILL = 7, // Target.td:1380
23 EXTRACT_SUBREG = 8, // Target.td:1387
24 INSERT_SUBREG = 9, // Target.td:1393
25 IMPLICIT_DEF = 10, // Target.td:1400
26 INIT_UNDEF = 11, // Target.td:1409
27 SUBREG_TO_REG = 12, // Target.td:1416
28 COPY_TO_REGCLASS = 13, // Target.td:1422
29 DBG_VALUE = 14, // Target.td:1429
30 DBG_VALUE_LIST = 15, // Target.td:1436
31 DBG_INSTR_REF = 16, // Target.td:1443
32 DBG_PHI = 17, // Target.td:1450
33 DBG_LABEL = 18, // Target.td:1457
34 REG_SEQUENCE = 19, // Target.td:1464
35 COPY = 20, // Target.td:1471
36 COPY_LANEMASK = 21, // Target.td:1479
37 BUNDLE = 22, // Target.td:1486
38 LIFETIME_START = 23, // Target.td:1492
39 LIFETIME_END = 24, // Target.td:1499
40 PSEUDO_PROBE = 25, // Target.td:1506
41 ARITH_FENCE = 26, // Target.td:1513
42 STACKMAP = 27, // Target.td:1522
43 FENTRY_CALL = 28, // Target.td:1657
44 PATCHPOINT = 29, // Target.td:1530
45 LOAD_STACK_GUARD = 30, // Target.td:1548
46 PREALLOCATED_SETUP = 31, // Target.td:1556
47 PREALLOCATED_ARG = 32, // Target.td:1562
48 STATEPOINT = 33, // Target.td:1539
49 LOCAL_ESCAPE = 34, // Target.td:1568
50 FAULTING_OP = 35, // Target.td:1577
51 PATCHABLE_OP = 36, // Target.td:1597
52 PATCHABLE_FUNCTION_ENTER = 37, // Target.td:1605
53 PATCHABLE_RET = 38, // Target.td:1612
54 PATCHABLE_FUNCTION_EXIT = 39, // Target.td:1621
55 PATCHABLE_TAIL_CALL = 40, // Target.td:1629
56 PATCHABLE_EVENT_CALL = 41, // Target.td:1637
57 PATCHABLE_TYPED_EVENT_CALL = 42, // Target.td:1647
58 ICALL_BRANCH_FUNNEL = 43, // Target.td:1667
59 FAKE_USE = 44, // Target.td:1587
60 MEMBARRIER = 45, // Target.td:1673
61 JUMP_TABLE_DEBUG_INFO = 46, // Target.td:1681
62 RELOC_NONE = 47, // Target.td:1689
63 CONVERGENCECTRL_ENTRY = 48, // Target.td:1701
64 CONVERGENCECTRL_ANCHOR = 49, // Target.td:1697
65 CONVERGENCECTRL_LOOP = 50, // Target.td:1705
66 CONVERGENCECTRL_GLUE = 51, // Target.td:1709
67 G_ASSERT_SEXT = 52, // GenericOpcodes.td:1929
68 G_ASSERT_ZEXT = 53, // GenericOpcodes.td:1921
69 G_ASSERT_ALIGN = 54, // GenericOpcodes.td:1936
70 G_ADD = 55, // GenericOpcodes.td:308
71 G_SUB = 56, // GenericOpcodes.td:316
72 G_MUL = 57, // GenericOpcodes.td:324
73 G_SDIV = 58, // GenericOpcodes.td:332
74 G_UDIV = 59, // GenericOpcodes.td:340
75 G_SREM = 60, // GenericOpcodes.td:348
76 G_UREM = 61, // GenericOpcodes.td:356
77 G_SDIVREM = 62, // GenericOpcodes.td:364
78 G_UDIVREM = 63, // GenericOpcodes.td:372
79 G_AND = 64, // GenericOpcodes.td:380
80 G_OR = 65, // GenericOpcodes.td:388
81 G_XOR = 66, // GenericOpcodes.td:396
82 G_ABDS = 67, // GenericOpcodes.td:425
83 G_ABDU = 68, // GenericOpcodes.td:433
84 G_UAVGFLOOR = 69, // GenericOpcodes.td:441
85 G_UAVGCEIL = 70, // GenericOpcodes.td:448
86 G_SAVGFLOOR = 71, // GenericOpcodes.td:455
87 G_SAVGCEIL = 72, // GenericOpcodes.td:462
88 G_IMPLICIT_DEF = 73, // GenericOpcodes.td:111
89 G_PHI = 74, // GenericOpcodes.td:118
90 G_FRAME_INDEX = 75, // GenericOpcodes.td:125
91 G_GLOBAL_VALUE = 76, // GenericOpcodes.td:131
92 G_PTRAUTH_GLOBAL_VALUE = 77, // GenericOpcodes.td:137
93 G_CONSTANT_POOL = 78, // GenericOpcodes.td:143
94 G_EXTRACT = 79, // GenericOpcodes.td:1516
95 G_UNMERGE_VALUES = 80, // GenericOpcodes.td:1529
96 G_INSERT = 81, // GenericOpcodes.td:1538
97 G_MERGE_VALUES = 82, // GenericOpcodes.td:1548
98 G_BUILD_VECTOR = 83, // GenericOpcodes.td:1568
99 G_BUILD_VECTOR_TRUNC = 84, // GenericOpcodes.td:1578
100 G_CONCAT_VECTORS = 85, // GenericOpcodes.td:1585
101 G_PTRTOINT = 86, // GenericOpcodes.td:155
102 G_INTTOPTR = 87, // GenericOpcodes.td:149
103 G_BITCAST = 88, // GenericOpcodes.td:161
104 G_FREEZE = 89, // GenericOpcodes.td:284
105 G_CONSTANT_FOLD_BARRIER = 90, // GenericOpcodes.td:1943
106 G_INTRINSIC_FPTRUNC_ROUND = 91, // GenericOpcodes.td:1280
107 G_INTRINSIC_TRUNC = 92, // GenericOpcodes.td:1286
108 G_INTRINSIC_ROUND = 93, // GenericOpcodes.td:1292
109 G_INTRINSIC_LRINT = 94, // GenericOpcodes.td:1298
110 G_INTRINSIC_LLRINT = 95, // GenericOpcodes.td:1304
111 G_INTRINSIC_ROUNDEVEN = 96, // GenericOpcodes.td:1310
112 G_READCYCLECOUNTER = 97, // GenericOpcodes.td:1316
113 G_READSTEADYCOUNTER = 98, // GenericOpcodes.td:1322
114 G_LOAD = 99, // GenericOpcodes.td:1349
115 G_SEXTLOAD = 100, // GenericOpcodes.td:1358
116 G_ZEXTLOAD = 101, // GenericOpcodes.td:1366
117 G_FPEXTLOAD = 102, // GenericOpcodes.td:1375
118 G_INDEXED_LOAD = 103, // GenericOpcodes.td:1385
119 G_INDEXED_SEXTLOAD = 104, // GenericOpcodes.td:1394
120 G_INDEXED_ZEXTLOAD = 105, // GenericOpcodes.td:1402
121 G_STORE = 106, // GenericOpcodes.td:1410
122 G_FPTRUNCSTORE = 107, // GenericOpcodes.td:1420
123 G_INDEXED_STORE = 108, // GenericOpcodes.td:1428
124 G_ATOMIC_CMPXCHG_WITH_SUCCESS = 109, // GenericOpcodes.td:1439
125 G_ATOMIC_CMPXCHG = 110, // GenericOpcodes.td:1450
126 G_ATOMICRMW_XCHG = 111, // GenericOpcodes.td:1470
127 G_ATOMICRMW_ADD = 112, // GenericOpcodes.td:1471
128 G_ATOMICRMW_SUB = 113, // GenericOpcodes.td:1472
129 G_ATOMICRMW_AND = 114, // GenericOpcodes.td:1473
130 G_ATOMICRMW_NAND = 115, // GenericOpcodes.td:1474
131 G_ATOMICRMW_OR = 116, // GenericOpcodes.td:1475
132 G_ATOMICRMW_XOR = 117, // GenericOpcodes.td:1476
133 G_ATOMICRMW_MAX = 118, // GenericOpcodes.td:1477
134 G_ATOMICRMW_MIN = 119, // GenericOpcodes.td:1478
135 G_ATOMICRMW_UMAX = 120, // GenericOpcodes.td:1479
136 G_ATOMICRMW_UMIN = 121, // GenericOpcodes.td:1480
137 G_ATOMICRMW_FADD = 122, // GenericOpcodes.td:1481
138 G_ATOMICRMW_FSUB = 123, // GenericOpcodes.td:1482
139 G_ATOMICRMW_FMAX = 124, // GenericOpcodes.td:1483
140 G_ATOMICRMW_FMIN = 125, // GenericOpcodes.td:1484
141 G_ATOMICRMW_FMAXIMUM = 126, // GenericOpcodes.td:1485
142 G_ATOMICRMW_FMINIMUM = 127, // GenericOpcodes.td:1486
143 G_ATOMICRMW_FMAXIMUMNUM = 128, // GenericOpcodes.td:1487
144 G_ATOMICRMW_FMINIMUMNUM = 129, // GenericOpcodes.td:1488
145 G_ATOMICRMW_UINC_WRAP = 130, // GenericOpcodes.td:1489
146 G_ATOMICRMW_UDEC_WRAP = 131, // GenericOpcodes.td:1490
147 G_ATOMICRMW_USUB_COND = 132, // GenericOpcodes.td:1491
148 G_ATOMICRMW_USUB_SAT = 133, // GenericOpcodes.td:1492
149 G_FENCE = 134, // GenericOpcodes.td:1494
150 G_PREFETCH = 135, // GenericOpcodes.td:1501
151 G_BRCOND = 136, // GenericOpcodes.td:1641
152 G_BRINDIRECT = 137, // GenericOpcodes.td:1650
153 G_INVOKE_REGION_START = 138, // GenericOpcodes.td:1673
154 G_INTRINSIC = 139, // GenericOpcodes.td:1593
155 G_INTRINSIC_W_SIDE_EFFECTS = 140, // GenericOpcodes.td:1600
156 G_INTRINSIC_CONVERGENT = 141, // GenericOpcodes.td:1609
157 G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 142, // GenericOpcodes.td:1617
158 G_ANYEXT = 143, // GenericOpcodes.td:44
159 G_TRUNC = 144, // GenericOpcodes.td:83
160 G_TRUNC_SSAT_S = 145, // GenericOpcodes.td:91
161 G_TRUNC_SSAT_U = 146, // GenericOpcodes.td:98
162 G_TRUNC_USAT_U = 147, // GenericOpcodes.td:105
163 G_CONSTANT = 148, // GenericOpcodes.td:169
164 G_FCONSTANT = 149, // GenericOpcodes.td:177
165 G_VASTART = 150, // GenericOpcodes.td:184
166 G_VAARG = 151, // GenericOpcodes.td:191
167 G_SEXT = 152, // GenericOpcodes.td:52
168 G_SEXT_INREG = 153, // GenericOpcodes.td:66
169 G_ZEXT = 154, // GenericOpcodes.td:74
170 G_SHL = 155, // GenericOpcodes.td:404
171 G_LSHR = 156, // GenericOpcodes.td:411
172 G_ASHR = 157, // GenericOpcodes.td:418
173 G_FSHL = 158, // GenericOpcodes.td:470
174 G_FSHR = 159, // GenericOpcodes.td:478
175 G_ROTR = 160, // GenericOpcodes.td:485
176 G_ROTL = 161, // GenericOpcodes.td:492
177 G_ICMP = 162, // GenericOpcodes.td:499
178 G_FCMP = 163, // GenericOpcodes.td:506
179 G_SCMP = 164, // GenericOpcodes.td:513
180 G_UCMP = 165, // GenericOpcodes.td:520
181 G_SELECT = 166, // GenericOpcodes.td:527
182 G_UADDO = 167, // GenericOpcodes.td:601
183 G_UADDE = 168, // GenericOpcodes.td:609
184 G_USUBO = 169, // GenericOpcodes.td:631
185 G_USUBE = 170, // GenericOpcodes.td:637
186 G_SADDO = 171, // GenericOpcodes.td:616
187 G_SADDE = 172, // GenericOpcodes.td:624
188 G_SSUBO = 173, // GenericOpcodes.td:644
189 G_SSUBE = 174, // GenericOpcodes.td:651
190 G_UMULO = 175, // GenericOpcodes.td:658
191 G_SMULO = 176, // GenericOpcodes.td:666
192 G_UMULH = 177, // GenericOpcodes.td:675
193 G_SMULH = 178, // GenericOpcodes.td:684
194 G_UADDSAT = 179, // GenericOpcodes.td:696
195 G_SADDSAT = 180, // GenericOpcodes.td:704
196 G_USUBSAT = 181, // GenericOpcodes.td:712
197 G_SSUBSAT = 182, // GenericOpcodes.td:720
198 G_USHLSAT = 183, // GenericOpcodes.td:728
199 G_SSHLSAT = 184, // GenericOpcodes.td:736
200 G_SMULFIX = 185, // GenericOpcodes.td:748
201 G_UMULFIX = 186, // GenericOpcodes.td:755
202 G_SMULFIXSAT = 187, // GenericOpcodes.td:765
203 G_UMULFIXSAT = 188, // GenericOpcodes.td:772
204 G_SDIVFIX = 189, // GenericOpcodes.td:783
205 G_UDIVFIX = 190, // GenericOpcodes.td:790
206 G_SDIVFIXSAT = 191, // GenericOpcodes.td:800
207 G_UDIVFIXSAT = 192, // GenericOpcodes.td:807
208 G_FADD = 193, // GenericOpcodes.td:980
209 G_FSUB = 194, // GenericOpcodes.td:988
210 G_FMUL = 195, // GenericOpcodes.td:996
211 G_FMA = 196, // GenericOpcodes.td:1005
212 G_FMAD = 197, // GenericOpcodes.td:1014
213 G_FDIV = 198, // GenericOpcodes.td:1022
214 G_FREM = 199, // GenericOpcodes.td:1029
215 G_FMODF = 200, // GenericOpcodes.td:1036
216 G_FPOW = 201, // GenericOpcodes.td:1043
217 G_FPOWI = 202, // GenericOpcodes.td:1050
218 G_FEXP = 203, // GenericOpcodes.td:1057
219 G_FEXP2 = 204, // GenericOpcodes.td:1064
220 G_FEXP10 = 205, // GenericOpcodes.td:1071
221 G_FLOG = 206, // GenericOpcodes.td:1078
222 G_FLOG2 = 207, // GenericOpcodes.td:1085
223 G_FLOG10 = 208, // GenericOpcodes.td:1092
224 G_FLDEXP = 209, // GenericOpcodes.td:1099
225 G_FFREXP = 210, // GenericOpcodes.td:1106
226 G_FNEG = 211, // GenericOpcodes.td:818
227 G_FPEXT = 212, // GenericOpcodes.td:824
228 G_FPTRUNC = 213, // GenericOpcodes.td:830
229 G_FPTOSI = 214, // GenericOpcodes.td:836
230 G_FPTOUI = 215, // GenericOpcodes.td:842
231 G_SITOFP = 216, // GenericOpcodes.td:848
232 G_UITOFP = 217, // GenericOpcodes.td:854
233 G_FPTOSI_SAT = 218, // GenericOpcodes.td:860
234 G_FPTOUI_SAT = 219, // GenericOpcodes.td:866
235 G_FABS = 220, // GenericOpcodes.td:872
236 G_FCOPYSIGN = 221, // GenericOpcodes.td:878
237 G_IS_FPCLASS = 222, // GenericOpcodes.td:891
238 G_FCANONICALIZE = 223, // GenericOpcodes.td:884
239 G_FMINNUM = 224, // GenericOpcodes.td:904
240 G_FMAXNUM = 225, // GenericOpcodes.td:911
241 G_FMINNUM_IEEE = 226, // GenericOpcodes.td:929
242 G_FMAXNUM_IEEE = 227, // GenericOpcodes.td:936
243 G_FMINIMUM = 228, // GenericOpcodes.td:946
244 G_FMAXIMUM = 229, // GenericOpcodes.td:953
245 G_FMINIMUMNUM = 230, // GenericOpcodes.td:961
246 G_FMAXIMUMNUM = 231, // GenericOpcodes.td:968
247 G_GET_FPENV = 232, // GenericOpcodes.td:1236
248 G_SET_FPENV = 233, // GenericOpcodes.td:1243
249 G_RESET_FPENV = 234, // GenericOpcodes.td:1250
250 G_GET_FPMODE = 235, // GenericOpcodes.td:1257
251 G_SET_FPMODE = 236, // GenericOpcodes.td:1264
252 G_RESET_FPMODE = 237, // GenericOpcodes.td:1271
253 G_GET_ROUNDING = 238, // GenericOpcodes.td:1328
254 G_SET_ROUNDING = 239, // GenericOpcodes.td:1334
255 G_PTR_ADD = 240, // GenericOpcodes.td:534
256 G_PTRMASK = 241, // GenericOpcodes.td:542
257 G_SMIN = 242, // GenericOpcodes.td:549
258 G_SMAX = 243, // GenericOpcodes.td:557
259 G_UMIN = 244, // GenericOpcodes.td:565
260 G_UMAX = 245, // GenericOpcodes.td:573
261 G_ABS = 246, // GenericOpcodes.td:581
262 G_LROUND = 247, // GenericOpcodes.td:291
263 G_LLROUND = 248, // GenericOpcodes.td:297
264 G_BR = 249, // GenericOpcodes.td:1631
265 G_BRJT = 250, // GenericOpcodes.td:1661
266 G_VSCALE = 251, // GenericOpcodes.td:1559
267 G_INSERT_SUBVECTOR = 252, // GenericOpcodes.td:1705
268 G_EXTRACT_SUBVECTOR = 253, // GenericOpcodes.td:1713
269 G_INSERT_VECTOR_ELT = 254, // GenericOpcodes.td:1721
270 G_EXTRACT_VECTOR_ELT = 255, // GenericOpcodes.td:1729
271 G_SHUFFLE_VECTOR = 256, // GenericOpcodes.td:1740
272 G_SPLAT_VECTOR = 257, // GenericOpcodes.td:1748
273 G_STEP_VECTOR = 258, // GenericOpcodes.td:1756
274 G_VECTOR_COMPRESS = 259, // GenericOpcodes.td:1763
275 G_CTTZ = 260, // GenericOpcodes.td:211
276 G_CTTZ_ZERO_POISON = 261, // GenericOpcodes.td:217
277 G_CTLZ = 262, // GenericOpcodes.td:199
278 G_CTLZ_ZERO_POISON = 263, // GenericOpcodes.td:205
279 G_CTLS = 264, // GenericOpcodes.td:223
280 G_CTPOP = 265, // GenericOpcodes.td:229
281 G_BSWAP = 266, // GenericOpcodes.td:235
282 G_BITREVERSE = 267, // GenericOpcodes.td:242
283 G_CLMUL = 268, // GenericOpcodes.td:588
284 G_FCEIL = 269, // GenericOpcodes.td:1113
285 G_FCOS = 270, // GenericOpcodes.td:1120
286 G_FSIN = 271, // GenericOpcodes.td:1127
287 G_FSINCOS = 272, // GenericOpcodes.td:1134
288 G_FTAN = 273, // GenericOpcodes.td:1141
289 G_FACOS = 274, // GenericOpcodes.td:1148
290 G_FASIN = 275, // GenericOpcodes.td:1155
291 G_FATAN = 276, // GenericOpcodes.td:1162
292 G_FATAN2 = 277, // GenericOpcodes.td:1169
293 G_FCOSH = 278, // GenericOpcodes.td:1176
294 G_FSINH = 279, // GenericOpcodes.td:1183
295 G_FTANH = 280, // GenericOpcodes.td:1190
296 G_FSQRT = 281, // GenericOpcodes.td:1200
297 G_FFLOOR = 282, // GenericOpcodes.td:1207
298 G_FRINT = 283, // GenericOpcodes.td:1214
299 G_FNEARBYINT = 284, // GenericOpcodes.td:1221
300 G_ADDRSPACE_CAST = 285, // GenericOpcodes.td:248
301 G_BLOCK_ADDR = 286, // GenericOpcodes.td:254
302 G_JUMP_TABLE = 287, // GenericOpcodes.td:260
303 G_DYN_STACKALLOC = 288, // GenericOpcodes.td:266
304 G_STACKSAVE = 289, // GenericOpcodes.td:272
305 G_STACKRESTORE = 290, // GenericOpcodes.td:278
306 G_STRICT_FADD = 291, // GenericOpcodes.td:1813
307 G_STRICT_FSUB = 292, // GenericOpcodes.td:1814
308 G_STRICT_FMUL = 293, // GenericOpcodes.td:1815
309 G_STRICT_FDIV = 294, // GenericOpcodes.td:1816
310 G_STRICT_FREM = 295, // GenericOpcodes.td:1817
311 G_STRICT_FMA = 296, // GenericOpcodes.td:1818
312 G_STRICT_FSQRT = 297, // GenericOpcodes.td:1819
313 G_STRICT_FLDEXP = 298, // GenericOpcodes.td:1820
314 G_STRICT_FCMP = 299, // GenericOpcodes.td:1821
315 G_STRICT_FCMPS = 300, // GenericOpcodes.td:1822
316 G_READ_REGISTER = 301, // GenericOpcodes.td:1680
317 G_WRITE_REGISTER = 302, // GenericOpcodes.td:1690
318 G_MEMCPY = 303, // GenericOpcodes.td:1828
319 G_MEMCPY_INLINE = 304, // GenericOpcodes.td:1836
320 G_MEMMOVE = 305, // GenericOpcodes.td:1844
321 G_MEMSET = 306, // GenericOpcodes.td:1852
322 G_BZERO = 307, // GenericOpcodes.td:1859
323 G_MEMSET_INLINE = 308, // GenericOpcodes.td:1866
324 G_TRAP = 309, // GenericOpcodes.td:1876
325 G_DEBUGTRAP = 310, // GenericOpcodes.td:1883
326 G_UBSANTRAP = 311, // GenericOpcodes.td:1889
327 G_VECREDUCE_SEQ_FADD = 312, // GenericOpcodes.td:1779
328 G_VECREDUCE_SEQ_FMUL = 313, // GenericOpcodes.td:1785
329 G_VECREDUCE_FADD = 314, // GenericOpcodes.td:1791
330 G_VECREDUCE_FMUL = 315, // GenericOpcodes.td:1792
331 G_VECREDUCE_FMAX = 316, // GenericOpcodes.td:1794
332 G_VECREDUCE_FMIN = 317, // GenericOpcodes.td:1795
333 G_VECREDUCE_FMAXIMUM = 318, // GenericOpcodes.td:1796
334 G_VECREDUCE_FMINIMUM = 319, // GenericOpcodes.td:1797
335 G_VECREDUCE_ADD = 320, // GenericOpcodes.td:1799
336 G_VECREDUCE_MUL = 321, // GenericOpcodes.td:1800
337 G_VECREDUCE_AND = 322, // GenericOpcodes.td:1801
338 G_VECREDUCE_OR = 323, // GenericOpcodes.td:1802
339 G_VECREDUCE_XOR = 324, // GenericOpcodes.td:1803
340 G_VECREDUCE_SMAX = 325, // GenericOpcodes.td:1804
341 G_VECREDUCE_SMIN = 326, // GenericOpcodes.td:1805
342 G_VECREDUCE_UMAX = 327, // GenericOpcodes.td:1806
343 G_VECREDUCE_UMIN = 328, // GenericOpcodes.td:1807
344 G_SBFX = 329, // GenericOpcodes.td:1901
345 G_UBFX = 330, // GenericOpcodes.td:1909
346 ADD16mc = 331, // MSP430InstrInfo.td:499
347 ADD16mi = 332, // MSP430InstrInfo.td:505
348 ADD16mm = 333, // MSP430InstrInfo.td:512
349 ADD16mn = 334, // MSP430InstrInfo.td:518
350 ADD16mp = 335, // MSP430InstrInfo.td:522
351 ADD16mr = 336, // MSP430InstrInfo.td:493
352 ADD16rc = 337, // MSP430InstrInfo.td:480
353 ADD16ri = 338, // MSP430InstrInfo.td:486
354 ADD16rm = 339, // MSP430InstrInfo.td:462
355 ADD16rn = 340, // MSP430InstrInfo.td:467
356 ADD16rp = 341, // MSP430InstrInfo.td:474
357 ADD16rr = 342, // MSP430InstrInfo.td:455
358 ADD8mc = 343, // MSP430InstrInfo.td:496
359 ADD8mi = 344, // MSP430InstrInfo.td:502
360 ADD8mm = 345, // MSP430InstrInfo.td:508
361 ADD8mn = 346, // MSP430InstrInfo.td:516
362 ADD8mp = 347, // MSP430InstrInfo.td:520
363 ADD8mr = 348, // MSP430InstrInfo.td:490
364 ADD8rc = 349, // MSP430InstrInfo.td:477
365 ADD8ri = 350, // MSP430InstrInfo.td:483
366 ADD8rm = 351, // MSP430InstrInfo.td:459
367 ADD8rn = 352, // MSP430InstrInfo.td:465
368 ADD8rp = 353, // MSP430InstrInfo.td:472
369 ADD8rr = 354, // MSP430InstrInfo.td:452
370 ADDC16mc = 355, // MSP430InstrInfo.td:499
371 ADDC16mi = 356, // MSP430InstrInfo.td:505
372 ADDC16mm = 357, // MSP430InstrInfo.td:512
373 ADDC16mn = 358, // MSP430InstrInfo.td:518
374 ADDC16mp = 359, // MSP430InstrInfo.td:522
375 ADDC16mr = 360, // MSP430InstrInfo.td:493
376 ADDC16rc = 361, // MSP430InstrInfo.td:480
377 ADDC16ri = 362, // MSP430InstrInfo.td:486
378 ADDC16rm = 363, // MSP430InstrInfo.td:462
379 ADDC16rn = 364, // MSP430InstrInfo.td:467
380 ADDC16rp = 365, // MSP430InstrInfo.td:474
381 ADDC16rr = 366, // MSP430InstrInfo.td:455
382 ADDC8mc = 367, // MSP430InstrInfo.td:496
383 ADDC8mi = 368, // MSP430InstrInfo.td:502
384 ADDC8mm = 369, // MSP430InstrInfo.td:508
385 ADDC8mn = 370, // MSP430InstrInfo.td:516
386 ADDC8mp = 371, // MSP430InstrInfo.td:520
387 ADDC8mr = 372, // MSP430InstrInfo.td:490
388 ADDC8rc = 373, // MSP430InstrInfo.td:477
389 ADDC8ri = 374, // MSP430InstrInfo.td:483
390 ADDC8rm = 375, // MSP430InstrInfo.td:459
391 ADDC8rn = 376, // MSP430InstrInfo.td:465
392 ADDC8rp = 377, // MSP430InstrInfo.td:472
393 ADDC8rr = 378, // MSP430InstrInfo.td:452
394 ADDframe = 379, // MSP430InstrInfo.td:183
395 ADJCALLSTACKDOWN = 380, // MSP430InstrInfo.td:174
396 ADJCALLSTACKUP = 381, // MSP430InstrInfo.td:177
397 AND16mc = 382, // MSP430InstrInfo.td:499
398 AND16mi = 383, // MSP430InstrInfo.td:505
399 AND16mm = 384, // MSP430InstrInfo.td:512
400 AND16mn = 385, // MSP430InstrInfo.td:518
401 AND16mp = 386, // MSP430InstrInfo.td:522
402 AND16mr = 387, // MSP430InstrInfo.td:493
403 AND16rc = 388, // MSP430InstrInfo.td:480
404 AND16ri = 389, // MSP430InstrInfo.td:486
405 AND16rm = 390, // MSP430InstrInfo.td:462
406 AND16rn = 391, // MSP430InstrInfo.td:467
407 AND16rp = 392, // MSP430InstrInfo.td:474
408 AND16rr = 393, // MSP430InstrInfo.td:455
409 AND8mc = 394, // MSP430InstrInfo.td:496
410 AND8mi = 395, // MSP430InstrInfo.td:502
411 AND8mm = 396, // MSP430InstrInfo.td:508
412 AND8mn = 397, // MSP430InstrInfo.td:516
413 AND8mp = 398, // MSP430InstrInfo.td:520
414 AND8mr = 399, // MSP430InstrInfo.td:490
415 AND8rc = 400, // MSP430InstrInfo.td:477
416 AND8ri = 401, // MSP430InstrInfo.td:483
417 AND8rm = 402, // MSP430InstrInfo.td:459
418 AND8rn = 403, // MSP430InstrInfo.td:465
419 AND8rp = 404, // MSP430InstrInfo.td:472
420 AND8rr = 405, // MSP430InstrInfo.td:452
421 BIC16mc = 406, // MSP430InstrInfo.td:499
422 BIC16mi = 407, // MSP430InstrInfo.td:505
423 BIC16mm = 408, // MSP430InstrInfo.td:512
424 BIC16mn = 409, // MSP430InstrInfo.td:518
425 BIC16mp = 410, // MSP430InstrInfo.td:522
426 BIC16mr = 411, // MSP430InstrInfo.td:493
427 BIC16rc = 412, // MSP430InstrInfo.td:480
428 BIC16ri = 413, // MSP430InstrInfo.td:486
429 BIC16rm = 414, // MSP430InstrInfo.td:462
430 BIC16rn = 415, // MSP430InstrInfo.td:467
431 BIC16rp = 416, // MSP430InstrInfo.td:474
432 BIC16rr = 417, // MSP430InstrInfo.td:455
433 BIC8mc = 418, // MSP430InstrInfo.td:496
434 BIC8mi = 419, // MSP430InstrInfo.td:502
435 BIC8mm = 420, // MSP430InstrInfo.td:508
436 BIC8mn = 421, // MSP430InstrInfo.td:516
437 BIC8mp = 422, // MSP430InstrInfo.td:520
438 BIC8mr = 423, // MSP430InstrInfo.td:490
439 BIC8rc = 424, // MSP430InstrInfo.td:477
440 BIC8ri = 425, // MSP430InstrInfo.td:483
441 BIC8rm = 426, // MSP430InstrInfo.td:459
442 BIC8rn = 427, // MSP430InstrInfo.td:465
443 BIC8rp = 428, // MSP430InstrInfo.td:472
444 BIC8rr = 429, // MSP430InstrInfo.td:452
445 BIS16mc = 430, // MSP430InstrInfo.td:499
446 BIS16mi = 431, // MSP430InstrInfo.td:505
447 BIS16mm = 432, // MSP430InstrInfo.td:512
448 BIS16mn = 433, // MSP430InstrInfo.td:518
449 BIS16mp = 434, // MSP430InstrInfo.td:522
450 BIS16mr = 435, // MSP430InstrInfo.td:493
451 BIS16rc = 436, // MSP430InstrInfo.td:480
452 BIS16ri = 437, // MSP430InstrInfo.td:486
453 BIS16rm = 438, // MSP430InstrInfo.td:462
454 BIS16rn = 439, // MSP430InstrInfo.td:467
455 BIS16rp = 440, // MSP430InstrInfo.td:474
456 BIS16rr = 441, // MSP430InstrInfo.td:455
457 BIS8mc = 442, // MSP430InstrInfo.td:496
458 BIS8mi = 443, // MSP430InstrInfo.td:502
459 BIS8mm = 444, // MSP430InstrInfo.td:508
460 BIS8mn = 445, // MSP430InstrInfo.td:516
461 BIS8mp = 446, // MSP430InstrInfo.td:520
462 BIS8mr = 447, // MSP430InstrInfo.td:490
463 BIS8rc = 448, // MSP430InstrInfo.td:477
464 BIS8ri = 449, // MSP430InstrInfo.td:483
465 BIS8rm = 450, // MSP430InstrInfo.td:459
466 BIS8rn = 451, // MSP430InstrInfo.td:465
467 BIS8rp = 452, // MSP430InstrInfo.td:472
468 BIS8rr = 453, // MSP430InstrInfo.td:452
469 BIT16mc = 454, // MSP430InstrInfo.td:861
470 BIT16mi = 455, // MSP430InstrInfo.td:870
471 BIT16mm = 456, // MSP430InstrInfo.td:881
472 BIT16mn = 457, // MSP430InstrInfo.td:889
473 BIT16mp = 458, // MSP430InstrInfo.td:894
474 BIT16mr = 459, // MSP430InstrInfo.td:852
475 BIT16rc = 460, // MSP430InstrInfo.td:815
476 BIT16ri = 461, // MSP430InstrInfo.td:824
477 BIT16rm = 462, // MSP430InstrInfo.td:833
478 BIT16rn = 463, // MSP430InstrInfo.td:840
479 BIT16rp = 464, // MSP430InstrInfo.td:845
480 BIT16rr = 465, // MSP430InstrInfo.td:806
481 BIT8mc = 466, // MSP430InstrInfo.td:857
482 BIT8mi = 467, // MSP430InstrInfo.td:866
483 BIT8mm = 468, // MSP430InstrInfo.td:875
484 BIT8mn = 469, // MSP430InstrInfo.td:887
485 BIT8mp = 470, // MSP430InstrInfo.td:892
486 BIT8mr = 471, // MSP430InstrInfo.td:848
487 BIT8rc = 472, // MSP430InstrInfo.td:811
488 BIT8ri = 473, // MSP430InstrInfo.td:820
489 BIT8rm = 474, // MSP430InstrInfo.td:829
490 BIT8rn = 475, // MSP430InstrInfo.td:838
491 BIT8rp = 476, // MSP430InstrInfo.td:843
492 BIT8rr = 477, // MSP430InstrInfo.td:802
493 Bi = 478, // MSP430InstrInfo.td:255
494 Bm = 479, // MSP430InstrInfo.td:261
495 Br = 480, // MSP430InstrInfo.td:258
496 CALLi = 481, // MSP430InstrInfo.td:284
497 CALLm = 482, // MSP430InstrInfo.td:290
498 CALLn = 483, // MSP430InstrInfo.td:293
499 CALLp = 484, // MSP430InstrInfo.td:294
500 CALLr = 485, // MSP430InstrInfo.td:287
501 CMP16mc = 486, // MSP430InstrInfo.td:738
502 CMP16mi = 487, // MSP430InstrInfo.td:748
503 CMP16mm = 488, // MSP430InstrInfo.td:785
504 CMP16mn = 489, // MSP430InstrInfo.td:791
505 CMP16mp = 490, // MSP430InstrInfo.td:796
506 CMP16mr = 491, // MSP430InstrInfo.td:777
507 CMP16rc = 492, // MSP430InstrInfo.td:720
508 CMP16ri = 493, // MSP430InstrInfo.td:729
509 CMP16rm = 494, // MSP430InstrInfo.td:758
510 CMP16rn = 495, // MSP430InstrInfo.td:765
511 CMP16rp = 496, // MSP430InstrInfo.td:770
512 CMP16rr = 497, // MSP430InstrInfo.td:711
513 CMP8mc = 498, // MSP430InstrInfo.td:734
514 CMP8mi = 499, // MSP430InstrInfo.td:743
515 CMP8mm = 500, // MSP430InstrInfo.td:781
516 CMP8mn = 501, // MSP430InstrInfo.td:789
517 CMP8mp = 502, // MSP430InstrInfo.td:794
518 CMP8mr = 503, // MSP430InstrInfo.td:773
519 CMP8rc = 504, // MSP430InstrInfo.td:716
520 CMP8ri = 505, // MSP430InstrInfo.td:725
521 CMP8rm = 506, // MSP430InstrInfo.td:754
522 CMP8rn = 507, // MSP430InstrInfo.td:763
523 CMP8rp = 508, // MSP430InstrInfo.td:768
524 CMP8rr = 509, // MSP430InstrInfo.td:707
525 DADD16mc = 510, // MSP430InstrInfo.td:499
526 DADD16mi = 511, // MSP430InstrInfo.td:505
527 DADD16mm = 512, // MSP430InstrInfo.td:512
528 DADD16mn = 513, // MSP430InstrInfo.td:518
529 DADD16mp = 514, // MSP430InstrInfo.td:522
530 DADD16mr = 515, // MSP430InstrInfo.td:493
531 DADD16rc = 516, // MSP430InstrInfo.td:480
532 DADD16ri = 517, // MSP430InstrInfo.td:486
533 DADD16rm = 518, // MSP430InstrInfo.td:462
534 DADD16rn = 519, // MSP430InstrInfo.td:467
535 DADD16rp = 520, // MSP430InstrInfo.td:474
536 DADD16rr = 521, // MSP430InstrInfo.td:455
537 DADD8mc = 522, // MSP430InstrInfo.td:496
538 DADD8mi = 523, // MSP430InstrInfo.td:502
539 DADD8mm = 524, // MSP430InstrInfo.td:508
540 DADD8mn = 525, // MSP430InstrInfo.td:516
541 DADD8mp = 526, // MSP430InstrInfo.td:520
542 DADD8mr = 527, // MSP430InstrInfo.td:490
543 DADD8rc = 528, // MSP430InstrInfo.td:477
544 DADD8ri = 529, // MSP430InstrInfo.td:483
545 DADD8rm = 530, // MSP430InstrInfo.td:459
546 DADD8rn = 531, // MSP430InstrInfo.td:465
547 DADD8rp = 532, // MSP430InstrInfo.td:472
548 DADD8rr = 533, // MSP430InstrInfo.td:452
549 JCC = 534, // MSP430InstrInfo.td:269
550 JMP = 535, // MSP430InstrInfo.td:248
551 MOV16mc = 536, // MSP430InstrInfo.td:407
552 MOV16mi = 537, // MSP430InstrInfo.td:416
553 MOV16mm = 538, // MSP430InstrInfo.td:434
554 MOV16mn = 539, // MSP430InstrInfo.td:441
555 MOV16mr = 540, // MSP430InstrInfo.td:425
556 MOV16rc = 541, // MSP430InstrInfo.td:335
557 MOV16ri = 542, // MSP430InstrInfo.td:343
558 MOV16rm = 543, // MSP430InstrInfo.td:354
559 MOV16rn = 544, // MSP430InstrInfo.td:362
560 MOV16rp = 545, // MSP430InstrInfo.td:383
561 MOV16rr = 546, // MSP430InstrInfo.td:324
562 MOV8mc = 547, // MSP430InstrInfo.td:403
563 MOV8mi = 548, // MSP430InstrInfo.td:412
564 MOV8mm = 549, // MSP430InstrInfo.td:430
565 MOV8mn = 550, // MSP430InstrInfo.td:439
566 MOV8mr = 551, // MSP430InstrInfo.td:421
567 MOV8rc = 552, // MSP430InstrInfo.td:331
568 MOV8ri = 553, // MSP430InstrInfo.td:339
569 MOV8rm = 554, // MSP430InstrInfo.td:350
570 MOV8rn = 555, // MSP430InstrInfo.td:358
571 MOV8rp = 556, // MSP430InstrInfo.td:380
572 MOV8rr = 557, // MSP430InstrInfo.td:320
573 MOVZX16rm8 = 558, // MSP430InstrInfo.td:373
574 MOVZX16rr8 = 559, // MSP430InstrInfo.td:369
575 POP16r = 560, // MSP430InstrInfo.td:302
576 PUSH16c = 561, // MSP430InstrInfo.td:311
577 PUSH16i = 562, // MSP430InstrInfo.td:312
578 PUSH16r = 563, // MSP430InstrInfo.td:310
579 PUSH8r = 564, // MSP430InstrInfo.td:309
580 RET = 565, // MSP430InstrInfo.td:229
581 RETI = 566, // MSP430InstrInfo.td:235
582 RRA16m = 567, // MSP430InstrInfo.td:661
583 RRA16n = 568, // MSP430InstrInfo.td:667
584 RRA16p = 569, // MSP430InstrInfo.td:669
585 RRA16r = 570, // MSP430InstrInfo.td:619
586 RRA8m = 571, // MSP430InstrInfo.td:657
587 RRA8n = 572, // MSP430InstrInfo.td:666
588 RRA8p = 573, // MSP430InstrInfo.td:668
589 RRA8r = 574, // MSP430InstrInfo.td:615
590 RRC16m = 575, // MSP430InstrInfo.td:676
591 RRC16n = 576, // MSP430InstrInfo.td:682
592 RRC16p = 577, // MSP430InstrInfo.td:684
593 RRC16r = 578, // MSP430InstrInfo.td:629
594 RRC8m = 579, // MSP430InstrInfo.td:672
595 RRC8n = 580, // MSP430InstrInfo.td:681
596 RRC8p = 581, // MSP430InstrInfo.td:683
597 RRC8r = 582, // MSP430InstrInfo.td:625
598 Rrcl16 = 583, // MSP430InstrInfo.td:219
599 Rrcl8 = 584, // MSP430InstrInfo.td:217
600 SEXT16m = 585, // MSP430InstrInfo.td:688
601 SEXT16n = 586, // MSP430InstrInfo.td:693
602 SEXT16p = 587, // MSP430InstrInfo.td:694
603 SEXT16r = 588, // MSP430InstrInfo.td:635
604 SUB16mc = 589, // MSP430InstrInfo.td:499
605 SUB16mi = 590, // MSP430InstrInfo.td:505
606 SUB16mm = 591, // MSP430InstrInfo.td:512
607 SUB16mn = 592, // MSP430InstrInfo.td:518
608 SUB16mp = 593, // MSP430InstrInfo.td:522
609 SUB16mr = 594, // MSP430InstrInfo.td:493
610 SUB16rc = 595, // MSP430InstrInfo.td:480
611 SUB16ri = 596, // MSP430InstrInfo.td:486
612 SUB16rm = 597, // MSP430InstrInfo.td:462
613 SUB16rn = 598, // MSP430InstrInfo.td:467
614 SUB16rp = 599, // MSP430InstrInfo.td:474
615 SUB16rr = 600, // MSP430InstrInfo.td:455
616 SUB8mc = 601, // MSP430InstrInfo.td:496
617 SUB8mi = 602, // MSP430InstrInfo.td:502
618 SUB8mm = 603, // MSP430InstrInfo.td:508
619 SUB8mn = 604, // MSP430InstrInfo.td:516
620 SUB8mp = 605, // MSP430InstrInfo.td:520
621 SUB8mr = 606, // MSP430InstrInfo.td:490
622 SUB8rc = 607, // MSP430InstrInfo.td:477
623 SUB8ri = 608, // MSP430InstrInfo.td:483
624 SUB8rm = 609, // MSP430InstrInfo.td:459
625 SUB8rn = 610, // MSP430InstrInfo.td:465
626 SUB8rp = 611, // MSP430InstrInfo.td:472
627 SUB8rr = 612, // MSP430InstrInfo.td:452
628 SUBC16mc = 613, // MSP430InstrInfo.td:499
629 SUBC16mi = 614, // MSP430InstrInfo.td:505
630 SUBC16mm = 615, // MSP430InstrInfo.td:512
631 SUBC16mn = 616, // MSP430InstrInfo.td:518
632 SUBC16mp = 617, // MSP430InstrInfo.td:522
633 SUBC16mr = 618, // MSP430InstrInfo.td:493
634 SUBC16rc = 619, // MSP430InstrInfo.td:480
635 SUBC16ri = 620, // MSP430InstrInfo.td:486
636 SUBC16rm = 621, // MSP430InstrInfo.td:462
637 SUBC16rn = 622, // MSP430InstrInfo.td:467
638 SUBC16rp = 623, // MSP430InstrInfo.td:474
639 SUBC16rr = 624, // MSP430InstrInfo.td:455
640 SUBC8mc = 625, // MSP430InstrInfo.td:496
641 SUBC8mi = 626, // MSP430InstrInfo.td:502
642 SUBC8mm = 627, // MSP430InstrInfo.td:508
643 SUBC8mn = 628, // MSP430InstrInfo.td:516
644 SUBC8mp = 629, // MSP430InstrInfo.td:520
645 SUBC8mr = 630, // MSP430InstrInfo.td:490
646 SUBC8rc = 631, // MSP430InstrInfo.td:477
647 SUBC8ri = 632, // MSP430InstrInfo.td:483
648 SUBC8rm = 633, // MSP430InstrInfo.td:459
649 SUBC8rn = 634, // MSP430InstrInfo.td:465
650 SUBC8rp = 635, // MSP430InstrInfo.td:472
651 SUBC8rr = 636, // MSP430InstrInfo.td:452
652 SWPB16m = 637, // MSP430InstrInfo.td:698
653 SWPB16n = 638, // MSP430InstrInfo.td:702
654 SWPB16p = 639, // MSP430InstrInfo.td:703
655 SWPB16r = 640, // MSP430InstrInfo.td:648
656 Select16 = 641, // MSP430InstrInfo.td:193
657 Select8 = 642, // MSP430InstrInfo.td:189
658 Shl16 = 643, // MSP430InstrInfo.td:202
659 Shl8 = 644, // MSP430InstrInfo.td:199
660 Sra16 = 645, // MSP430InstrInfo.td:208
661 Sra8 = 646, // MSP430InstrInfo.td:205
662 Srl16 = 647, // MSP430InstrInfo.td:214
663 Srl8 = 648, // MSP430InstrInfo.td:211
664 XOR16mc = 649, // MSP430InstrInfo.td:499
665 XOR16mi = 650, // MSP430InstrInfo.td:505
666 XOR16mm = 651, // MSP430InstrInfo.td:512
667 XOR16mn = 652, // MSP430InstrInfo.td:518
668 XOR16mp = 653, // MSP430InstrInfo.td:522
669 XOR16mr = 654, // MSP430InstrInfo.td:493
670 XOR16rc = 655, // MSP430InstrInfo.td:480
671 XOR16ri = 656, // MSP430InstrInfo.td:486
672 XOR16rm = 657, // MSP430InstrInfo.td:462
673 XOR16rn = 658, // MSP430InstrInfo.td:467
674 XOR16rp = 659, // MSP430InstrInfo.td:474
675 XOR16rr = 660, // MSP430InstrInfo.td:455
676 XOR8mc = 661, // MSP430InstrInfo.td:496
677 XOR8mi = 662, // MSP430InstrInfo.td:502
678 XOR8mm = 663, // MSP430InstrInfo.td:508
679 XOR8mn = 664, // MSP430InstrInfo.td:516
680 XOR8mp = 665, // MSP430InstrInfo.td:520
681 XOR8mr = 666, // MSP430InstrInfo.td:490
682 XOR8rc = 667, // MSP430InstrInfo.td:477
683 XOR8ri = 668, // MSP430InstrInfo.td:483
684 XOR8rm = 669, // MSP430InstrInfo.td:459
685 XOR8rn = 670, // MSP430InstrInfo.td:465
686 XOR8rp = 671, // MSP430InstrInfo.td:472
687 XOR8rr = 672, // MSP430InstrInfo.td:452
688 ZEXT16r = 673, // MSP430InstrInfo.td:643
689 INSTRUCTION_LIST_END = 674
690 };
691
692} // namespace llvm::MSP430
693
694#endif // GET_INSTRINFO_ENUM
695
696#ifdef GET_INSTRINFO_SCHED_ENUM
697#undef GET_INSTRINFO_SCHED_ENUM
698
699namespace llvm::MSP430::Sched {
700
701 enum {
702 NoInstrModel = 0,
703 SCHED_LIST_END = 1
704 };
705
706} // namespace llvm::MSP430::Sched
707
708#endif // GET_INSTRINFO_SCHED_ENUM
709
710#if defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
711
712namespace llvm {
713
714struct MSP430InstrTable {
715 MCInstrDesc Insts[674];
716 static_assert(alignof(MCInstrDesc) >= alignof(MCPhysReg), "Unwanted padding between Insts and ImplicitOps");
717 MCPhysReg ImplicitOps[17];
718 char Padding[sizeof(MCOperandInfo) - sizeof ImplicitOps % sizeof(MCOperandInfo)];
719 static_assert(alignof(MCInstrDesc) >= alignof(MCOperandInfo), "Unwanted padding between Insts and OperandInfo");
720 MCOperandInfo OperandInfo[260];
721};
722} // namespace llvm
723
724#endif // defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
725
726#ifdef GET_INSTRINFO_MC_DESC
727#undef GET_INSTRINFO_MC_DESC
728
729namespace llvm {
730
731static_assert((sizeof MSP430InstrTable::ImplicitOps + sizeof MSP430InstrTable::Padding) % sizeof(MCOperandInfo) == 0);
732static constexpr unsigned MSP430OpInfoBase = (sizeof MSP430InstrTable::ImplicitOps + sizeof MSP430InstrTable::Padding) / sizeof(MCOperandInfo);
733
734extern const MSP430InstrTable MSP430Descs = {
735 {
736 { 673, 2, 1, 2, 0, 0, 0, MSP430OpInfoBase + 242, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ZEXT16r
737 { 672, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 207, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR8rr
738 { 671, 4, 2, 2, 0, 0, 1, MSP430OpInfoBase + 203, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR8rp
739 { 670, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR8rn
740 { 669, 4, 1, 4, 0, 0, 1, MSP430OpInfoBase + 196, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR8rm
741 { 668, 3, 1, 4, 0, 0, 1, MSP430OpInfoBase + 193, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR8ri
742 { 667, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 190, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR8rc
743 { 666, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 187, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR8mr
744 { 665, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR8mp
745 { 664, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR8mn
746 { 663, 4, 0, 6, 0, 0, 1, MSP430OpInfoBase + 157, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR8mm
747 { 662, 3, 0, 6, 0, 0, 1, MSP430OpInfoBase + 154, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR8mi
748 { 661, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 151, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR8mc
749 { 660, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 184, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR16rr
750 { 659, 4, 2, 2, 0, 0, 1, MSP430OpInfoBase + 180, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR16rp
751 { 658, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 177, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR16rn
752 { 657, 4, 1, 4, 0, 0, 1, MSP430OpInfoBase + 173, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR16rm
753 { 656, 3, 1, 4, 0, 0, 1, MSP430OpInfoBase + 170, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR16ri
754 { 655, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 167, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR16rc
755 { 654, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 164, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR16mr
756 { 653, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR16mp
757 { 652, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR16mn
758 { 651, 4, 0, 6, 0, 0, 1, MSP430OpInfoBase + 157, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR16mm
759 { 650, 3, 0, 6, 0, 0, 1, MSP430OpInfoBase + 154, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR16mi
760 { 649, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 151, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR16mc
761 { 648, 3, 1, 0, 0, 0, 1, MSP430OpInfoBase + 257, 0, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Srl8
762 { 647, 3, 1, 0, 0, 0, 1, MSP430OpInfoBase + 254, 0, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Srl16
763 { 646, 3, 1, 0, 0, 0, 1, MSP430OpInfoBase + 257, 0, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Sra8
764 { 645, 3, 1, 0, 0, 0, 1, MSP430OpInfoBase + 254, 0, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Sra16
765 { 644, 3, 1, 0, 0, 0, 1, MSP430OpInfoBase + 257, 0, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Shl8
766 { 643, 3, 1, 0, 0, 0, 1, MSP430OpInfoBase + 254, 0, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Shl16
767 { 642, 4, 1, 0, 0, 1, 0, MSP430OpInfoBase + 250, 0, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Select8
768 { 641, 4, 1, 0, 0, 1, 0, MSP430OpInfoBase + 246, 0, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Select16
769 { 640, 2, 1, 2, 0, 0, 0, MSP430OpInfoBase + 242, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SWPB16r
770 { 639, 1, 0, 2, 0, 0, 0, MSP430OpInfoBase + 232, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SWPB16p
771 { 638, 1, 0, 2, 0, 0, 0, MSP430OpInfoBase + 232, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SWPB16n
772 { 637, 2, 0, 4, 0, 0, 0, MSP430OpInfoBase + 230, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SWPB16m
773 { 636, 3, 1, 2, 0, 1, 1, MSP430OpInfoBase + 207, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC8rr
774 { 635, 4, 2, 2, 0, 1, 1, MSP430OpInfoBase + 203, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC8rp
775 { 634, 3, 1, 2, 0, 1, 1, MSP430OpInfoBase + 200, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC8rn
776 { 633, 4, 1, 4, 0, 1, 1, MSP430OpInfoBase + 196, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC8rm
777 { 632, 3, 1, 4, 0, 1, 1, MSP430OpInfoBase + 193, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC8ri
778 { 631, 3, 1, 2, 0, 1, 1, MSP430OpInfoBase + 190, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC8rc
779 { 630, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 187, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC8mr
780 { 629, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 161, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC8mp
781 { 628, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 161, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC8mn
782 { 627, 4, 0, 6, 0, 1, 1, MSP430OpInfoBase + 157, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC8mm
783 { 626, 3, 0, 6, 0, 1, 1, MSP430OpInfoBase + 154, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC8mi
784 { 625, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 151, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC8mc
785 { 624, 3, 1, 2, 0, 1, 1, MSP430OpInfoBase + 184, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC16rr
786 { 623, 4, 2, 2, 0, 1, 1, MSP430OpInfoBase + 180, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC16rp
787 { 622, 3, 1, 2, 0, 1, 1, MSP430OpInfoBase + 177, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC16rn
788 { 621, 4, 1, 4, 0, 1, 1, MSP430OpInfoBase + 173, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC16rm
789 { 620, 3, 1, 4, 0, 1, 1, MSP430OpInfoBase + 170, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC16ri
790 { 619, 3, 1, 2, 0, 1, 1, MSP430OpInfoBase + 167, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC16rc
791 { 618, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 164, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC16mr
792 { 617, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 161, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC16mp
793 { 616, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 161, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC16mn
794 { 615, 4, 0, 6, 0, 1, 1, MSP430OpInfoBase + 157, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC16mm
795 { 614, 3, 0, 6, 0, 1, 1, MSP430OpInfoBase + 154, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC16mi
796 { 613, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 151, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC16mc
797 { 612, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 207, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB8rr
798 { 611, 4, 2, 2, 0, 0, 1, MSP430OpInfoBase + 203, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB8rp
799 { 610, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB8rn
800 { 609, 4, 1, 4, 0, 0, 1, MSP430OpInfoBase + 196, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB8rm
801 { 608, 3, 1, 4, 0, 0, 1, MSP430OpInfoBase + 193, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB8ri
802 { 607, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 190, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB8rc
803 { 606, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 187, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB8mr
804 { 605, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB8mp
805 { 604, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB8mn
806 { 603, 4, 0, 6, 0, 0, 1, MSP430OpInfoBase + 157, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB8mm
807 { 602, 3, 0, 6, 0, 0, 1, MSP430OpInfoBase + 154, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB8mi
808 { 601, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 151, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB8mc
809 { 600, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 184, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB16rr
810 { 599, 4, 2, 2, 0, 0, 1, MSP430OpInfoBase + 180, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB16rp
811 { 598, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 177, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB16rn
812 { 597, 4, 1, 4, 0, 0, 1, MSP430OpInfoBase + 173, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB16rm
813 { 596, 3, 1, 4, 0, 0, 1, MSP430OpInfoBase + 170, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB16ri
814 { 595, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 167, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB16rc
815 { 594, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 164, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB16mr
816 { 593, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB16mp
817 { 592, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB16mn
818 { 591, 4, 0, 6, 0, 0, 1, MSP430OpInfoBase + 157, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB16mm
819 { 590, 3, 0, 6, 0, 0, 1, MSP430OpInfoBase + 154, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB16mi
820 { 589, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 151, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB16mc
821 { 588, 2, 1, 2, 0, 0, 1, MSP430OpInfoBase + 242, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SEXT16r
822 { 587, 1, 0, 2, 0, 0, 1, MSP430OpInfoBase + 232, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SEXT16p
823 { 586, 1, 0, 2, 0, 0, 1, MSP430OpInfoBase + 232, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SEXT16n
824 { 585, 2, 0, 4, 0, 0, 1, MSP430OpInfoBase + 230, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SEXT16m
825 { 584, 2, 1, 0, 0, 0, 1, MSP430OpInfoBase + 228, 0, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Rrcl8
826 { 583, 2, 1, 0, 0, 0, 1, MSP430OpInfoBase + 217, 0, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Rrcl16
827 { 582, 2, 1, 2, 0, 1, 1, MSP430OpInfoBase + 244, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RRC8r
828 { 581, 1, 0, 2, 0, 1, 1, MSP430OpInfoBase + 232, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RRC8p
829 { 580, 1, 0, 2, 0, 1, 1, MSP430OpInfoBase + 232, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RRC8n
830 { 579, 2, 0, 4, 0, 1, 1, MSP430OpInfoBase + 230, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RRC8m
831 { 578, 2, 1, 2, 0, 1, 1, MSP430OpInfoBase + 242, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RRC16r
832 { 577, 1, 0, 2, 0, 1, 1, MSP430OpInfoBase + 232, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RRC16p
833 { 576, 1, 0, 2, 0, 1, 1, MSP430OpInfoBase + 232, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RRC16n
834 { 575, 2, 0, 4, 0, 1, 1, MSP430OpInfoBase + 230, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RRC16m
835 { 574, 2, 1, 2, 0, 0, 1, MSP430OpInfoBase + 244, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RRA8r
836 { 573, 1, 0, 2, 0, 0, 1, MSP430OpInfoBase + 232, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RRA8p
837 { 572, 1, 0, 2, 0, 0, 1, MSP430OpInfoBase + 232, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RRA8n
838 { 571, 2, 0, 4, 0, 0, 1, MSP430OpInfoBase + 230, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RRA8m
839 { 570, 2, 1, 2, 0, 0, 1, MSP430OpInfoBase + 242, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RRA16r
840 { 569, 1, 0, 2, 0, 0, 1, MSP430OpInfoBase + 232, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RRA16p
841 { 568, 1, 0, 2, 0, 0, 1, MSP430OpInfoBase + 232, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RRA16n
842 { 567, 2, 0, 4, 0, 0, 1, MSP430OpInfoBase + 230, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RRA16m
843 { 566, 0, 0, 2, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RETI
844 { 565, 0, 0, 2, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RET
845 { 564, 1, 0, 2, 0, 1, 1, MSP430OpInfoBase + 241, 15, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PUSH8r
846 { 563, 1, 0, 2, 0, 1, 1, MSP430OpInfoBase + 28, 15, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PUSH16r
847 { 562, 1, 0, 4, 0, 1, 1, MSP430OpInfoBase + 1, 15, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PUSH16i
848 { 561, 1, 0, 2, 0, 1, 1, MSP430OpInfoBase + 0, 15, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PUSH16c
849 { 560, 1, 1, 2, 0, 1, 1, MSP430OpInfoBase + 28, 15, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // POP16r
850 { 559, 2, 1, 2, 0, 0, 0, MSP430OpInfoBase + 239, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOVZX16rr8
851 { 558, 3, 1, 4, 0, 0, 0, MSP430OpInfoBase + 212, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOVZX16rm8
852 { 557, 2, 1, 2, 0, 0, 0, MSP430OpInfoBase + 228, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV8rr
853 { 556, 3, 2, 2, 0, 0, 0, MSP430OpInfoBase + 236, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV8rp
854 { 555, 2, 1, 2, 0, 0, 0, MSP430OpInfoBase + 226, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV8rn
855 { 554, 3, 1, 4, 0, 0, 0, MSP430OpInfoBase + 223, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV8rm
856 { 553, 2, 1, 4, 0, 0, 0, MSP430OpInfoBase + 221, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV8ri
857 { 552, 2, 1, 2, 0, 0, 0, MSP430OpInfoBase + 219, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV8rc
858 { 551, 3, 0, 4, 0, 0, 0, MSP430OpInfoBase + 187, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV8mr
859 { 550, 3, 0, 4, 0, 0, 0, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV8mn
860 { 549, 4, 0, 6, 0, 0, 0, MSP430OpInfoBase + 157, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV8mm
861 { 548, 3, 0, 6, 0, 0, 0, MSP430OpInfoBase + 154, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV8mi
862 { 547, 3, 0, 4, 0, 0, 0, MSP430OpInfoBase + 151, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV8mc
863 { 546, 2, 1, 2, 0, 0, 0, MSP430OpInfoBase + 217, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV16rr
864 { 545, 3, 2, 2, 0, 0, 0, MSP430OpInfoBase + 233, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV16rp
865 { 544, 2, 1, 2, 0, 0, 0, MSP430OpInfoBase + 215, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV16rn
866 { 543, 3, 1, 4, 0, 0, 0, MSP430OpInfoBase + 212, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV16rm
867 { 542, 2, 1, 4, 0, 0, 0, MSP430OpInfoBase + 210, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV16ri
868 { 541, 2, 1, 2, 0, 0, 0, MSP430OpInfoBase + 34, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV16rc
869 { 540, 3, 0, 4, 0, 0, 0, MSP430OpInfoBase + 164, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV16mr
870 { 539, 3, 0, 4, 0, 0, 0, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV16mn
871 { 538, 4, 0, 6, 0, 0, 0, MSP430OpInfoBase + 157, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV16mm
872 { 537, 3, 0, 6, 0, 0, 0, MSP430OpInfoBase + 154, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV16mi
873 { 536, 3, 0, 4, 0, 0, 0, MSP430OpInfoBase + 151, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV16mc
874 { 535, 1, 0, 2, 0, 0, 0, MSP430OpInfoBase + 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JMP
875 { 534, 2, 0, 2, 0, 1, 0, MSP430OpInfoBase + 9, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JCC
876 { 533, 3, 1, 2, 0, 1, 1, MSP430OpInfoBase + 207, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD8rr
877 { 532, 4, 2, 2, 0, 1, 1, MSP430OpInfoBase + 203, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD8rp
878 { 531, 3, 1, 2, 0, 1, 1, MSP430OpInfoBase + 200, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD8rn
879 { 530, 4, 1, 4, 0, 1, 1, MSP430OpInfoBase + 196, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD8rm
880 { 529, 3, 1, 4, 0, 1, 1, MSP430OpInfoBase + 193, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD8ri
881 { 528, 3, 1, 2, 0, 1, 1, MSP430OpInfoBase + 190, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD8rc
882 { 527, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 187, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD8mr
883 { 526, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 161, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD8mp
884 { 525, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 161, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD8mn
885 { 524, 4, 0, 6, 0, 1, 1, MSP430OpInfoBase + 157, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD8mm
886 { 523, 3, 0, 6, 0, 1, 1, MSP430OpInfoBase + 154, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD8mi
887 { 522, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 151, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD8mc
888 { 521, 3, 1, 2, 0, 1, 1, MSP430OpInfoBase + 184, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD16rr
889 { 520, 4, 2, 2, 0, 1, 1, MSP430OpInfoBase + 180, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD16rp
890 { 519, 3, 1, 2, 0, 1, 1, MSP430OpInfoBase + 177, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD16rn
891 { 518, 4, 1, 4, 0, 1, 1, MSP430OpInfoBase + 173, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD16rm
892 { 517, 3, 1, 4, 0, 1, 1, MSP430OpInfoBase + 170, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD16ri
893 { 516, 3, 1, 2, 0, 1, 1, MSP430OpInfoBase + 167, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD16rc
894 { 515, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 164, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD16mr
895 { 514, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 161, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD16mp
896 { 513, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 161, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD16mn
897 { 512, 4, 0, 6, 0, 1, 1, MSP430OpInfoBase + 157, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD16mm
898 { 511, 3, 0, 6, 0, 1, 1, MSP430OpInfoBase + 154, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD16mi
899 { 510, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 151, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD16mc
900 { 509, 2, 0, 2, 0, 0, 1, MSP430OpInfoBase + 228, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP8rr
901 { 508, 2, 0, 2, 0, 0, 1, MSP430OpInfoBase + 226, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP8rp
902 { 507, 2, 0, 2, 0, 0, 1, MSP430OpInfoBase + 226, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP8rn
903 { 506, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 223, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP8rm
904 { 505, 2, 0, 4, 0, 0, 1, MSP430OpInfoBase + 221, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP8ri
905 { 504, 2, 0, 2, 0, 0, 1, MSP430OpInfoBase + 219, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP8rc
906 { 503, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 187, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP8mr
907 { 502, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP8mp
908 { 501, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP8mn
909 { 500, 4, 0, 6, 0, 0, 1, MSP430OpInfoBase + 157, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP8mm
910 { 499, 3, 0, 6, 0, 0, 1, MSP430OpInfoBase + 154, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP8mi
911 { 498, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 151, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP8mc
912 { 497, 2, 0, 2, 0, 0, 1, MSP430OpInfoBase + 217, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP16rr
913 { 496, 2, 0, 2, 0, 0, 1, MSP430OpInfoBase + 215, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP16rp
914 { 495, 2, 0, 2, 0, 0, 1, MSP430OpInfoBase + 215, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP16rn
915 { 494, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 212, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP16rm
916 { 493, 2, 0, 4, 0, 0, 1, MSP430OpInfoBase + 210, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP16ri
917 { 492, 2, 0, 2, 0, 0, 1, MSP430OpInfoBase + 34, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP16rc
918 { 491, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 164, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP16mr
919 { 490, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP16mp
920 { 489, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP16mn
921 { 488, 4, 0, 6, 0, 0, 1, MSP430OpInfoBase + 157, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP16mm
922 { 487, 3, 0, 6, 0, 0, 1, MSP430OpInfoBase + 154, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP16mi
923 { 486, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 151, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP16mc
924 { 485, 1, 0, 2, 0, 1, 6, MSP430OpInfoBase + 28, 8, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CALLr
925 { 484, 1, 0, 2, 0, 1, 6, MSP430OpInfoBase + 232, 8, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CALLp
926 { 483, 1, 0, 2, 0, 1, 6, MSP430OpInfoBase + 232, 8, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CALLn
927 { 482, 2, 0, 4, 0, 1, 6, MSP430OpInfoBase + 230, 8, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CALLm
928 { 481, 1, 0, 4, 0, 1, 6, MSP430OpInfoBase + 1, 8, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CALLi
929 { 480, 1, 0, 2, 0, 0, 0, MSP430OpInfoBase + 28, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Br
930 { 479, 2, 0, 4, 0, 0, 0, MSP430OpInfoBase + 230, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Bm
931 { 478, 1, 0, 4, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Bi
932 { 477, 2, 0, 2, 0, 0, 1, MSP430OpInfoBase + 228, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT8rr
933 { 476, 2, 0, 2, 0, 0, 1, MSP430OpInfoBase + 226, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT8rp
934 { 475, 2, 0, 2, 0, 0, 1, MSP430OpInfoBase + 226, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT8rn
935 { 474, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 223, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT8rm
936 { 473, 2, 0, 4, 0, 0, 1, MSP430OpInfoBase + 221, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT8ri
937 { 472, 2, 0, 2, 0, 0, 1, MSP430OpInfoBase + 219, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT8rc
938 { 471, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 187, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT8mr
939 { 470, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT8mp
940 { 469, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT8mn
941 { 468, 4, 0, 6, 0, 0, 1, MSP430OpInfoBase + 157, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT8mm
942 { 467, 3, 0, 6, 0, 0, 1, MSP430OpInfoBase + 154, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT8mi
943 { 466, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 151, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT8mc
944 { 465, 2, 0, 2, 0, 0, 1, MSP430OpInfoBase + 217, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT16rr
945 { 464, 2, 0, 2, 0, 0, 1, MSP430OpInfoBase + 215, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT16rp
946 { 463, 2, 0, 2, 0, 0, 1, MSP430OpInfoBase + 215, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT16rn
947 { 462, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 212, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT16rm
948 { 461, 2, 0, 4, 0, 0, 1, MSP430OpInfoBase + 210, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT16ri
949 { 460, 2, 0, 2, 0, 0, 1, MSP430OpInfoBase + 34, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT16rc
950 { 459, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 164, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT16mr
951 { 458, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT16mp
952 { 457, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT16mn
953 { 456, 4, 0, 6, 0, 0, 1, MSP430OpInfoBase + 157, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT16mm
954 { 455, 3, 0, 6, 0, 0, 1, MSP430OpInfoBase + 154, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT16mi
955 { 454, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 151, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT16mc
956 { 453, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 207, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS8rr
957 { 452, 4, 2, 2, 0, 0, 1, MSP430OpInfoBase + 203, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS8rp
958 { 451, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS8rn
959 { 450, 4, 1, 4, 0, 0, 1, MSP430OpInfoBase + 196, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS8rm
960 { 449, 3, 1, 4, 0, 0, 1, MSP430OpInfoBase + 193, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS8ri
961 { 448, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 190, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS8rc
962 { 447, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 187, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS8mr
963 { 446, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS8mp
964 { 445, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS8mn
965 { 444, 4, 0, 6, 0, 0, 1, MSP430OpInfoBase + 157, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS8mm
966 { 443, 3, 0, 6, 0, 0, 1, MSP430OpInfoBase + 154, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS8mi
967 { 442, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 151, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS8mc
968 { 441, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 184, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS16rr
969 { 440, 4, 2, 2, 0, 0, 1, MSP430OpInfoBase + 180, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS16rp
970 { 439, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 177, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS16rn
971 { 438, 4, 1, 4, 0, 0, 1, MSP430OpInfoBase + 173, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS16rm
972 { 437, 3, 1, 4, 0, 0, 1, MSP430OpInfoBase + 170, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS16ri
973 { 436, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 167, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS16rc
974 { 435, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 164, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS16mr
975 { 434, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS16mp
976 { 433, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS16mn
977 { 432, 4, 0, 6, 0, 0, 1, MSP430OpInfoBase + 157, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS16mm
978 { 431, 3, 0, 6, 0, 0, 1, MSP430OpInfoBase + 154, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS16mi
979 { 430, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 151, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS16mc
980 { 429, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 207, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC8rr
981 { 428, 4, 2, 2, 0, 0, 1, MSP430OpInfoBase + 203, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC8rp
982 { 427, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC8rn
983 { 426, 4, 1, 4, 0, 0, 1, MSP430OpInfoBase + 196, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC8rm
984 { 425, 3, 1, 4, 0, 0, 1, MSP430OpInfoBase + 193, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC8ri
985 { 424, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 190, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC8rc
986 { 423, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 187, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC8mr
987 { 422, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC8mp
988 { 421, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC8mn
989 { 420, 4, 0, 6, 0, 0, 1, MSP430OpInfoBase + 157, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC8mm
990 { 419, 3, 0, 6, 0, 0, 1, MSP430OpInfoBase + 154, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC8mi
991 { 418, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 151, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC8mc
992 { 417, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 184, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC16rr
993 { 416, 4, 2, 2, 0, 0, 1, MSP430OpInfoBase + 180, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC16rp
994 { 415, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 177, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC16rn
995 { 414, 4, 1, 4, 0, 0, 1, MSP430OpInfoBase + 173, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC16rm
996 { 413, 3, 1, 4, 0, 0, 1, MSP430OpInfoBase + 170, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC16ri
997 { 412, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 167, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC16rc
998 { 411, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 164, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC16mr
999 { 410, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC16mp
1000 { 409, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC16mn
1001 { 408, 4, 0, 6, 0, 0, 1, MSP430OpInfoBase + 157, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC16mm
1002 { 407, 3, 0, 6, 0, 0, 1, MSP430OpInfoBase + 154, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC16mi
1003 { 406, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 151, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC16mc
1004 { 405, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 207, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND8rr
1005 { 404, 4, 2, 2, 0, 0, 1, MSP430OpInfoBase + 203, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND8rp
1006 { 403, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND8rn
1007 { 402, 4, 1, 4, 0, 0, 1, MSP430OpInfoBase + 196, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND8rm
1008 { 401, 3, 1, 4, 0, 0, 1, MSP430OpInfoBase + 193, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND8ri
1009 { 400, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 190, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND8rc
1010 { 399, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 187, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND8mr
1011 { 398, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND8mp
1012 { 397, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND8mn
1013 { 396, 4, 0, 6, 0, 0, 1, MSP430OpInfoBase + 157, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND8mm
1014 { 395, 3, 0, 6, 0, 0, 1, MSP430OpInfoBase + 154, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND8mi
1015 { 394, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 151, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND8mc
1016 { 393, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 184, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND16rr
1017 { 392, 4, 2, 2, 0, 0, 1, MSP430OpInfoBase + 180, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND16rp
1018 { 391, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 177, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND16rn
1019 { 390, 4, 1, 4, 0, 0, 1, MSP430OpInfoBase + 173, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND16rm
1020 { 389, 3, 1, 4, 0, 0, 1, MSP430OpInfoBase + 170, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND16ri
1021 { 388, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 167, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND16rc
1022 { 387, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 164, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND16mr
1023 { 386, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND16mp
1024 { 385, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND16mn
1025 { 384, 4, 0, 6, 0, 0, 1, MSP430OpInfoBase + 157, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND16mm
1026 { 383, 3, 0, 6, 0, 0, 1, MSP430OpInfoBase + 154, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND16mi
1027 { 382, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 151, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND16mc
1028 { 381, 2, 0, 0, 0, 1, 2, MSP430OpInfoBase + 20, 5, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADJCALLSTACKUP
1029 { 380, 2, 0, 0, 0, 1, 2, MSP430OpInfoBase + 20, 5, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADJCALLSTACKDOWN
1030 { 379, 3, 1, 0, 0, 1, 1, MSP430OpInfoBase + 29, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDframe
1031 { 378, 3, 1, 2, 0, 1, 1, MSP430OpInfoBase + 207, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC8rr
1032 { 377, 4, 2, 2, 0, 1, 1, MSP430OpInfoBase + 203, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC8rp
1033 { 376, 3, 1, 2, 0, 1, 1, MSP430OpInfoBase + 200, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC8rn
1034 { 375, 4, 1, 4, 0, 1, 1, MSP430OpInfoBase + 196, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC8rm
1035 { 374, 3, 1, 4, 0, 1, 1, MSP430OpInfoBase + 193, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC8ri
1036 { 373, 3, 1, 2, 0, 1, 1, MSP430OpInfoBase + 190, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC8rc
1037 { 372, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 187, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC8mr
1038 { 371, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 161, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC8mp
1039 { 370, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 161, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC8mn
1040 { 369, 4, 0, 6, 0, 1, 1, MSP430OpInfoBase + 157, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC8mm
1041 { 368, 3, 0, 6, 0, 1, 1, MSP430OpInfoBase + 154, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC8mi
1042 { 367, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 151, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC8mc
1043 { 366, 3, 1, 2, 0, 1, 1, MSP430OpInfoBase + 184, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC16rr
1044 { 365, 4, 2, 2, 0, 1, 1, MSP430OpInfoBase + 180, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC16rp
1045 { 364, 3, 1, 2, 0, 1, 1, MSP430OpInfoBase + 177, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC16rn
1046 { 363, 4, 1, 4, 0, 1, 1, MSP430OpInfoBase + 173, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC16rm
1047 { 362, 3, 1, 4, 0, 1, 1, MSP430OpInfoBase + 170, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC16ri
1048 { 361, 3, 1, 2, 0, 1, 1, MSP430OpInfoBase + 167, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC16rc
1049 { 360, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 164, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC16mr
1050 { 359, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 161, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC16mp
1051 { 358, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 161, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC16mn
1052 { 357, 4, 0, 6, 0, 1, 1, MSP430OpInfoBase + 157, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC16mm
1053 { 356, 3, 0, 6, 0, 1, 1, MSP430OpInfoBase + 154, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC16mi
1054 { 355, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 151, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC16mc
1055 { 354, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 207, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD8rr
1056 { 353, 4, 2, 2, 0, 0, 1, MSP430OpInfoBase + 203, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD8rp
1057 { 352, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD8rn
1058 { 351, 4, 1, 4, 0, 0, 1, MSP430OpInfoBase + 196, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD8rm
1059 { 350, 3, 1, 4, 0, 0, 1, MSP430OpInfoBase + 193, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD8ri
1060 { 349, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 190, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD8rc
1061 { 348, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 187, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD8mr
1062 { 347, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD8mp
1063 { 346, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD8mn
1064 { 345, 4, 0, 6, 0, 0, 1, MSP430OpInfoBase + 157, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD8mm
1065 { 344, 3, 0, 6, 0, 0, 1, MSP430OpInfoBase + 154, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD8mi
1066 { 343, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 151, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD8mc
1067 { 342, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 184, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD16rr
1068 { 341, 4, 2, 2, 0, 0, 1, MSP430OpInfoBase + 180, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD16rp
1069 { 340, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 177, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD16rn
1070 { 339, 4, 1, 4, 0, 0, 1, MSP430OpInfoBase + 173, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD16rm
1071 { 338, 3, 1, 4, 0, 0, 1, MSP430OpInfoBase + 170, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD16ri
1072 { 337, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 167, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD16rc
1073 { 336, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 164, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD16mr
1074 { 335, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD16mp
1075 { 334, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD16mn
1076 { 333, 4, 0, 6, 0, 0, 1, MSP430OpInfoBase + 157, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD16mm
1077 { 332, 3, 0, 6, 0, 0, 1, MSP430OpInfoBase + 154, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD16mi
1078 { 331, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 151, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD16mc
1079 { 330, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 147, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UBFX
1080 { 329, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 147, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SBFX
1081 { 328, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_UMIN
1082 { 327, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_UMAX
1083 { 326, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SMIN
1084 { 325, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SMAX
1085 { 324, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_XOR
1086 { 323, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_OR
1087 { 322, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_AND
1088 { 321, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_MUL
1089 { 320, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_ADD
1090 { 319, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMINIMUM
1091 { 318, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMAXIMUM
1092 { 317, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMIN
1093 { 316, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMAX
1094 { 315, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMUL
1095 { 314, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FADD
1096 { 313, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SEQ_FMUL
1097 { 312, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SEQ_FADD
1098 { 311, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UBSANTRAP
1099 { 310, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_DEBUGTRAP
1100 { 309, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRAP
1101 { 308, 3, 0, 0, 0, 0, 0, MSP430OpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMSET_INLINE
1102 { 307, 3, 0, 0, 0, 0, 0, MSP430OpInfoBase + 57, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BZERO
1103 { 306, 4, 0, 0, 0, 0, 0, MSP430OpInfoBase + 143, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMSET
1104 { 305, 4, 0, 0, 0, 0, 0, MSP430OpInfoBase + 143, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMMOVE
1105 { 304, 3, 0, 0, 0, 0, 0, MSP430OpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMCPY_INLINE
1106 { 303, 4, 0, 0, 0, 0, 0, MSP430OpInfoBase + 143, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMCPY
1107 { 302, 2, 0, 0, 0, 0, 0, MSP430OpInfoBase + 141, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_WRITE_REGISTER
1108 { 301, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_READ_REGISTER
1109 { 300, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FCMPS
1110 { 299, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FCMP
1111 { 298, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FLDEXP
1112 { 297, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FSQRT
1113 { 296, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FMA
1114 { 295, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FREM
1115 { 294, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FDIV
1116 { 293, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FMUL
1117 { 292, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FSUB
1118 { 291, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FADD
1119 { 290, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STACKRESTORE
1120 { 289, 1, 1, 0, 0, 0, 0, MSP430OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STACKSAVE
1121 { 288, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 68, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_DYN_STACKALLOC
1122 { 287, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_JUMP_TABLE
1123 { 286, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BLOCK_ADDR
1124 { 285, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ADDRSPACE_CAST
1125 { 284, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FNEARBYINT
1126 { 283, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FRINT
1127 { 282, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FFLOOR
1128 { 281, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSQRT
1129 { 280, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FTANH
1130 { 279, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSINH
1131 { 278, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCOSH
1132 { 277, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FATAN2
1133 { 276, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FATAN
1134 { 275, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FASIN
1135 { 274, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FACOS
1136 { 273, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FTAN
1137 { 272, 3, 2, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSINCOS
1138 { 271, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSIN
1139 { 270, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCOS
1140 { 269, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCEIL
1141 { 268, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CLMUL
1142 { 267, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BITREVERSE
1143 { 266, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BSWAP
1144 { 265, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTPOP
1145 { 264, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTLS
1146 { 263, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTLZ_ZERO_POISON
1147 { 262, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTLZ
1148 { 261, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTTZ_ZERO_POISON
1149 { 260, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTTZ
1150 { 259, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 137, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECTOR_COMPRESS
1151 { 258, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STEP_VECTOR
1152 { 257, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SPLAT_VECTOR
1153 { 256, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 133, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SHUFFLE_VECTOR
1154 { 255, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_EXTRACT_VECTOR_ELT
1155 { 254, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 126, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INSERT_VECTOR_ELT
1156 { 253, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 57, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_EXTRACT_SUBVECTOR
1157 { 252, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 62, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INSERT_SUBVECTOR
1158 { 251, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VSCALE
1159 { 250, 3, 0, 0, 0, 0, 0, MSP430OpInfoBase + 123, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BRJT
1160 { 249, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BR
1161 { 248, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LLROUND
1162 { 247, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LROUND
1163 { 246, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ABS
1164 { 245, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMAX
1165 { 244, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMIN
1166 { 243, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMAX
1167 { 242, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMIN
1168 { 241, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTRMASK
1169 { 240, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTR_ADD
1170 { 239, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SET_ROUNDING
1171 { 238, 1, 1, 0, 0, 0, 0, MSP430OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GET_ROUNDING
1172 { 237, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_RESET_FPMODE
1173 { 236, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SET_FPMODE
1174 { 235, 1, 1, 0, 0, 0, 0, MSP430OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GET_FPMODE
1175 { 234, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_RESET_FPENV
1176 { 233, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SET_FPENV
1177 { 232, 1, 1, 0, 0, 0, 0, MSP430OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GET_FPENV
1178 { 231, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXIMUMNUM
1179 { 230, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINIMUMNUM
1180 { 229, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXIMUM
1181 { 228, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINIMUM
1182 { 227, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXNUM_IEEE
1183 { 226, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINNUM_IEEE
1184 { 225, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXNUM
1185 { 224, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINNUM
1186 { 223, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCANONICALIZE
1187 { 222, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 97, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_IS_FPCLASS
1188 { 221, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCOPYSIGN
1189 { 220, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FABS
1190 { 219, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOUI_SAT
1191 { 218, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOSI_SAT
1192 { 217, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UITOFP
1193 { 216, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SITOFP
1194 { 215, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOUI
1195 { 214, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOSI
1196 { 213, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTRUNC
1197 { 212, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPEXT
1198 { 211, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FNEG
1199 { 210, 3, 2, 0, 0, 0, 0, MSP430OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FFREXP
1200 { 209, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLDEXP
1201 { 208, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLOG10
1202 { 207, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLOG2
1203 { 206, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLOG
1204 { 205, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FEXP10
1205 { 204, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FEXP2
1206 { 203, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FEXP
1207 { 202, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPOWI
1208 { 201, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPOW
1209 { 200, 3, 2, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMODF
1210 { 199, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FREM
1211 { 198, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FDIV
1212 { 197, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAD
1213 { 196, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMA
1214 { 195, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMUL
1215 { 194, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSUB
1216 { 193, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FADD
1217 { 192, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIVFIXSAT
1218 { 191, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIVFIXSAT
1219 { 190, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIVFIX
1220 { 189, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIVFIX
1221 { 188, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULFIXSAT
1222 { 187, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULFIXSAT
1223 { 186, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULFIX
1224 { 185, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULFIX
1225 { 184, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSHLSAT
1226 { 183, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USHLSAT
1227 { 182, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSUBSAT
1228 { 181, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USUBSAT
1229 { 180, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SADDSAT
1230 { 179, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UADDSAT
1231 { 178, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULH
1232 { 177, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULH
1233 { 176, 4, 2, 0, 0, 0, 0, MSP430OpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULO
1234 { 175, 4, 2, 0, 0, 0, 0, MSP430OpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULO
1235 { 174, 5, 2, 0, 0, 0, 0, MSP430OpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSUBE
1236 { 173, 4, 2, 0, 0, 0, 0, MSP430OpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSUBO
1237 { 172, 5, 2, 0, 0, 0, 0, MSP430OpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SADDE
1238 { 171, 4, 2, 0, 0, 0, 0, MSP430OpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SADDO
1239 { 170, 5, 2, 0, 0, 0, 0, MSP430OpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USUBE
1240 { 169, 4, 2, 0, 0, 0, 0, MSP430OpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USUBO
1241 { 168, 5, 2, 0, 0, 0, 0, MSP430OpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UADDE
1242 { 167, 4, 2, 0, 0, 0, 0, MSP430OpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UADDO
1243 { 166, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SELECT
1244 { 165, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 111, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UCMP
1245 { 164, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 111, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SCMP
1246 { 163, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCMP
1247 { 162, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ICMP
1248 { 161, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ROTL
1249 { 160, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ROTR
1250 { 159, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 103, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSHR
1251 { 158, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 103, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSHL
1252 { 157, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASHR
1253 { 156, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LSHR
1254 { 155, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SHL
1255 { 154, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ZEXT
1256 { 153, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SEXT_INREG
1257 { 152, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SEXT
1258 { 151, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 97, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VAARG
1259 { 150, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VASTART
1260 { 149, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCONSTANT
1261 { 148, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONSTANT
1262 { 147, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC_USAT_U
1263 { 146, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC_SSAT_U
1264 { 145, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC_SSAT_S
1265 { 144, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC
1266 { 143, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ANYEXT
1267 { 142, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
1268 { 141, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_INTRINSIC_CONVERGENT
1269 { 140, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_W_SIDE_EFFECTS
1270 { 139, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC
1271 { 138, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INVOKE_REGION_START
1272 { 137, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BRINDIRECT
1273 { 136, 2, 0, 0, 0, 0, 0, MSP430OpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BRCOND
1274 { 135, 4, 0, 0, 0, 0, 0, MSP430OpInfoBase + 93, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PREFETCH
1275 { 134, 2, 0, 0, 0, 0, 0, MSP430OpInfoBase + 20, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FENCE
1276 { 133, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_USUB_SAT
1277 { 132, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_USUB_COND
1278 { 131, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UDEC_WRAP
1279 { 130, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UINC_WRAP
1280 { 129, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMINIMUMNUM
1281 { 128, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMAXIMUMNUM
1282 { 127, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMINIMUM
1283 { 126, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMAXIMUM
1284 { 125, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMIN
1285 { 124, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMAX
1286 { 123, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FSUB
1287 { 122, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FADD
1288 { 121, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UMIN
1289 { 120, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UMAX
1290 { 119, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_MIN
1291 { 118, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_MAX
1292 { 117, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_XOR
1293 { 116, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_OR
1294 { 115, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_NAND
1295 { 114, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_AND
1296 { 113, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_SUB
1297 { 112, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_ADD
1298 { 111, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_XCHG
1299 { 110, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMIC_CMPXCHG
1300 { 109, 5, 2, 0, 0, 0, 0, MSP430OpInfoBase + 81, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
1301 { 108, 5, 1, 0, 0, 0, 0, MSP430OpInfoBase + 76, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_STORE
1302 { 107, 2, 0, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTRUNCSTORE
1303 { 106, 2, 0, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STORE
1304 { 105, 5, 2, 0, 0, 0, 0, MSP430OpInfoBase + 71, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_ZEXTLOAD
1305 { 104, 5, 2, 0, 0, 0, 0, MSP430OpInfoBase + 71, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_SEXTLOAD
1306 { 103, 5, 2, 0, 0, 0, 0, MSP430OpInfoBase + 71, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_LOAD
1307 { 102, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPEXTLOAD
1308 { 101, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ZEXTLOAD
1309 { 100, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SEXTLOAD
1310 { 99, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LOAD
1311 { 98, 1, 1, 0, 0, 0, 0, MSP430OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_READSTEADYCOUNTER
1312 { 97, 1, 1, 0, 0, 0, 0, MSP430OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_READCYCLECOUNTER
1313 { 96, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_ROUNDEVEN
1314 { 95, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_LLRINT
1315 { 94, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_LRINT
1316 { 93, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_ROUND
1317 { 92, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_TRUNC
1318 { 91, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 68, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_FPTRUNC_ROUND
1319 { 90, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONSTANT_FOLD_BARRIER
1320 { 89, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FREEZE
1321 { 88, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BITCAST
1322 { 87, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTTOPTR
1323 { 86, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTRTOINT
1324 { 85, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONCAT_VECTORS
1325 { 84, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BUILD_VECTOR_TRUNC
1326 { 83, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BUILD_VECTOR
1327 { 82, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MERGE_VALUES
1328 { 81, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 62, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INSERT
1329 { 80, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UNMERGE_VALUES
1330 { 79, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 57, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_EXTRACT
1331 { 78, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONSTANT_POOL
1332 { 77, 5, 1, 0, 0, 0, 0, MSP430OpInfoBase + 52, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTRAUTH_GLOBAL_VALUE
1333 { 76, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GLOBAL_VALUE
1334 { 75, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FRAME_INDEX
1335 { 74, 1, 1, 0, 0, 0, 0, MSP430OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PHI
1336 { 73, 1, 1, 0, 0, 0, 0, MSP430OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_IMPLICIT_DEF
1337 { 72, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SAVGCEIL
1338 { 71, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SAVGFLOOR
1339 { 70, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UAVGCEIL
1340 { 69, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UAVGFLOOR
1341 { 68, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ABDU
1342 { 67, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ABDS
1343 { 66, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_XOR
1344 { 65, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_OR
1345 { 64, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_AND
1346 { 63, 4, 2, 0, 0, 0, 0, MSP430OpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIVREM
1347 { 62, 4, 2, 0, 0, 0, 0, MSP430OpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIVREM
1348 { 61, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UREM
1349 { 60, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SREM
1350 { 59, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIV
1351 { 58, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIV
1352 { 57, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MUL
1353 { 56, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SUB
1354 { 55, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ADD
1355 { 54, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASSERT_ALIGN
1356 { 53, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASSERT_ZEXT
1357 { 52, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASSERT_SEXT
1358 { 51, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_GLUE
1359 { 50, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_LOOP
1360 { 49, 1, 1, 0, 0, 0, 0, MSP430OpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_ANCHOR
1361 { 48, 1, 1, 0, 0, 0, 0, MSP430OpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_ENTRY
1362 { 47, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RELOC_NONE
1363 { 46, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JUMP_TABLE_DEBUG_INFO
1364 { 45, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMBARRIER
1365 { 44, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FAKE_USE
1366 { 43, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ICALL_BRANCH_FUNNEL
1367 { 42, 3, 0, 0, 0, 0, 0, MSP430OpInfoBase + 36, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_13888
1368 { 41, 2, 0, 0, 0, 0, 0, MSP430OpInfoBase + 34, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_13887
1369 { 40, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_TAIL_CALL
1370 { 39, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_FUNCTION_EXIT
1371 { 38, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_RET
1372 { 37, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_FUNCTION_ENTER
1373 { 36, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_OP
1374 { 35, 1, 1, 0, 0, 0, 0, MSP430OpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FAULTING_OP
1375 { 34, 2, 0, 0, 0, 0, 0, MSP430OpInfoBase + 32, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_ESCAPE
1376 { 33, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STATEPOINT
1377 { 32, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 29, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_13886
1378 { 31, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PREALLOCATED_SETUP
1379 { 30, 1, 1, 0, 0, 0, 0, MSP430OpInfoBase + 28, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_13555
1380 { 29, 6, 1, 0, 0, 0, 0, MSP430OpInfoBase + 22, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHPOINT
1381 { 28, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FENTRY_CALL
1382 { 27, 2, 0, 0, 0, 0, 0, MSP430OpInfoBase + 20, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STACKMAP
1383 { 26, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 18, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARITH_FENCE
1384 { 25, 4, 0, 0, 0, 0, 0, MSP430OpInfoBase + 14, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PSEUDO_PROBE
1385 { 24, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LIFETIME_END
1386 { 23, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LIFETIME_START
1387 { 22, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BUNDLE
1388 { 21, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 11, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_LANEMASK
1389 { 20, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY
1390 { 19, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REG_SEQUENCE
1391 { 18, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_LABEL
1392 { 17, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_PHI
1393 { 16, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_INSTR_REF
1394 { 15, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_VALUE_LIST
1395 { 14, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_VALUE
1396 { 13, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_TO_REGCLASS
1397 { 12, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBREG_TO_REG
1398 { 11, 1, 1, 0, 0, 0, 0, MSP430OpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INIT_UNDEF
1399 { 10, 1, 1, 0, 0, 0, 0, MSP430OpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // IMPLICIT_DEF
1400 { 9, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 5, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INSERT_SUBREG
1401 { 8, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTRACT_SUBREG
1402 { 7, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // KILL
1403 { 6, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ANNOTATION_LABEL
1404 { 5, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GC_LABEL
1405 { 4, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EH_LABEL
1406 { 3, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CFI_INSTRUCTION
1407 { 2, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INLINEASM_BR
1408 { 1, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INLINEASM
1409 { 0, 1, 1, 0, 0, 0, 0, MSP430OpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PHI
1410 }, {
1411 /* 0 */
1412 /* 0 */ MSP430::SR,
1413 /* 1 */ MSP430::SR, MSP430::SR,
1414 /* 3 */ MSP430::SP, MSP430::SR,
1415 /* 5 */ MSP430::SP, MSP430::SP, MSP430::SR,
1416 /* 8 */ MSP430::SP, MSP430::R11, MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15, MSP430::SR,
1417 /* 15 */ MSP430::SP, MSP430::SP,
1418 }, {
1419 0
1420 }, {
1421 /* 0 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1422 /* 1 */
1423 /* 1 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1424 /* 2 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1425 /* 5 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1426 /* 9 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1427 /* 11 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1428 /* 14 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1429 /* 18 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) },
1430 /* 20 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1431 /* 22 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1432 /* 28 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1433 /* 29 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1434 /* 32 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1435 /* 34 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1436 /* 36 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1437 /* 39 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1438 /* 42 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1439 /* 45 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1440 /* 49 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1441 /* 50 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1442 /* 52 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1443 /* 57 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1444 /* 60 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1445 /* 62 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1446 /* 66 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1447 /* 68 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1448 /* 71 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1449 /* 76 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1450 /* 81 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1451 /* 86 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1452 /* 90 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1453 /* 93 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1454 /* 97 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1455 /* 100 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1456 /* 103 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1457 /* 107 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1458 /* 111 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1459 /* 114 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1460 /* 119 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1461 /* 123 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1462 /* 126 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
1463 /* 130 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
1464 /* 133 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1465 /* 137 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1466 /* 141 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1467 /* 143 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1468 /* 147 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1469 /* 151 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1470 /* 154 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1471 /* 157 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1472 /* 161 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 },
1473 /* 164 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1474 /* 167 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1475 /* 170 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1476 /* 173 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1477 /* 177 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 },
1478 /* 180 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(1) },
1479 /* 184 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1480 /* 187 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1481 /* 190 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1482 /* 193 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1483 /* 196 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1484 /* 200 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 },
1485 /* 203 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(1) },
1486 /* 207 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1487 /* 210 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1488 /* 212 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1489 /* 215 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 },
1490 /* 217 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1491 /* 219 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1492 /* 221 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1493 /* 223 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1494 /* 226 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 },
1495 /* 228 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1496 /* 230 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1497 /* 232 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 },
1498 /* 233 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(1) },
1499 /* 236 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(1) },
1500 /* 239 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1501 /* 241 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1502 /* 242 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
1503 /* 244 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
1504 /* 246 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1505 /* 250 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1506 /* 254 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1507 /* 257 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1508 }
1509};
1510
1511
1512#ifdef __GNUC__
1513#pragma GCC diagnostic push
1514#pragma GCC diagnostic ignored "-Woverlength-strings"
1515#endif
1516extern const char MSP430InstrNameData[] = {
1517 /* 0 */ "G_FLOG10\000"
1518 /* 9 */ "G_FEXP10\000"
1519 /* 18 */ "G_FLOG2\000"
1520 /* 26 */ "G_FATAN2\000"
1521 /* 35 */ "G_FEXP2\000"
1522 /* 43 */ "Sra16\000"
1523 /* 49 */ "Rrcl16\000"
1524 /* 56 */ "Shl16\000"
1525 /* 62 */ "Srl16\000"
1526 /* 68 */ "Select16\000"
1527 /* 77 */ "Sra8\000"
1528 /* 82 */ "Rrcl8\000"
1529 /* 88 */ "Shl8\000"
1530 /* 93 */ "Srl8\000"
1531 /* 98 */ "MOVZX16rm8\000"
1532 /* 109 */ "MOVZX16rr8\000"
1533 /* 120 */ "Select8\000"
1534 /* 128 */ "G_FMA\000"
1535 /* 134 */ "G_STRICT_FMA\000"
1536 /* 147 */ "G_FSUB\000"
1537 /* 154 */ "G_STRICT_FSUB\000"
1538 /* 168 */ "G_ATOMICRMW_FSUB\000"
1539 /* 185 */ "G_SUB\000"
1540 /* 191 */ "G_ATOMICRMW_SUB\000"
1541 /* 207 */ "JCC\000"
1542 /* 211 */ "G_INTRINSIC\000"
1543 /* 223 */ "G_FPTRUNC\000"
1544 /* 233 */ "G_INTRINSIC_TRUNC\000"
1545 /* 251 */ "G_TRUNC\000"
1546 /* 259 */ "G_BUILD_VECTOR_TRUNC\000"
1547 /* 280 */ "G_DYN_STACKALLOC\000"
1548 /* 297 */ "G_FMAD\000"
1549 /* 304 */ "G_FPEXTLOAD\000"
1550 /* 316 */ "G_INDEXED_SEXTLOAD\000"
1551 /* 335 */ "G_SEXTLOAD\000"
1552 /* 346 */ "G_INDEXED_ZEXTLOAD\000"
1553 /* 365 */ "G_ZEXTLOAD\000"
1554 /* 376 */ "G_INDEXED_LOAD\000"
1555 /* 391 */ "G_LOAD\000"
1556 /* 398 */ "G_VECREDUCE_FADD\000"
1557 /* 415 */ "G_FADD\000"
1558 /* 422 */ "G_VECREDUCE_SEQ_FADD\000"
1559 /* 443 */ "G_STRICT_FADD\000"
1560 /* 457 */ "G_ATOMICRMW_FADD\000"
1561 /* 474 */ "G_VECREDUCE_ADD\000"
1562 /* 490 */ "G_ADD\000"
1563 /* 496 */ "G_PTR_ADD\000"
1564 /* 506 */ "G_ATOMICRMW_ADD\000"
1565 /* 522 */ "G_ATOMICRMW_NAND\000"
1566 /* 539 */ "G_VECREDUCE_AND\000"
1567 /* 555 */ "G_AND\000"
1568 /* 561 */ "G_ATOMICRMW_AND\000"
1569 /* 577 */ "LIFETIME_END\000"
1570 /* 590 */ "G_BRCOND\000"
1571 /* 599 */ "G_ATOMICRMW_USUB_COND\000"
1572 /* 621 */ "G_LLROUND\000"
1573 /* 631 */ "G_LROUND\000"
1574 /* 640 */ "G_INTRINSIC_ROUND\000"
1575 /* 658 */ "G_INTRINSIC_FPTRUNC_ROUND\000"
1576 /* 684 */ "LOAD_STACK_GUARD\000"
1577 /* 701 */ "PSEUDO_PROBE\000"
1578 /* 714 */ "G_SSUBE\000"
1579 /* 722 */ "G_USUBE\000"
1580 /* 730 */ "G_FENCE\000"
1581 /* 738 */ "ARITH_FENCE\000"
1582 /* 750 */ "REG_SEQUENCE\000"
1583 /* 763 */ "G_SADDE\000"
1584 /* 771 */ "G_UADDE\000"
1585 /* 779 */ "G_GET_FPMODE\000"
1586 /* 792 */ "G_RESET_FPMODE\000"
1587 /* 807 */ "G_SET_FPMODE\000"
1588 /* 820 */ "G_FMINNUM_IEEE\000"
1589 /* 835 */ "G_FMAXNUM_IEEE\000"
1590 /* 850 */ "G_VSCALE\000"
1591 /* 859 */ "G_JUMP_TABLE\000"
1592 /* 872 */ "BUNDLE\000"
1593 /* 879 */ "G_MEMSET_INLINE\000"
1594 /* 895 */ "G_MEMCPY_INLINE\000"
1595 /* 911 */ "RELOC_NONE\000"
1596 /* 922 */ "LOCAL_ESCAPE\000"
1597 /* 935 */ "G_FPTRUNCSTORE\000"
1598 /* 950 */ "G_STACKRESTORE\000"
1599 /* 965 */ "G_INDEXED_STORE\000"
1600 /* 981 */ "G_STORE\000"
1601 /* 989 */ "G_BITREVERSE\000"
1602 /* 1002 */ "FAKE_USE\000"
1603 /* 1011 */ "DBG_VALUE\000"
1604 /* 1021 */ "G_GLOBAL_VALUE\000"
1605 /* 1036 */ "G_PTRAUTH_GLOBAL_VALUE\000"
1606 /* 1059 */ "CONVERGENCECTRL_GLUE\000"
1607 /* 1080 */ "G_STACKSAVE\000"
1608 /* 1092 */ "G_MEMMOVE\000"
1609 /* 1102 */ "G_FREEZE\000"
1610 /* 1111 */ "G_FCANONICALIZE\000"
1611 /* 1127 */ "G_FMODF\000"
1612 /* 1135 */ "INIT_UNDEF\000"
1613 /* 1146 */ "G_IMPLICIT_DEF\000"
1614 /* 1161 */ "DBG_INSTR_REF\000"
1615 /* 1175 */ "G_FNEG\000"
1616 /* 1182 */ "EXTRACT_SUBREG\000"
1617 /* 1197 */ "INSERT_SUBREG\000"
1618 /* 1211 */ "G_SEXT_INREG\000"
1619 /* 1224 */ "SUBREG_TO_REG\000"
1620 /* 1238 */ "G_ATOMIC_CMPXCHG\000"
1621 /* 1255 */ "G_ATOMICRMW_XCHG\000"
1622 /* 1272 */ "G_GET_ROUNDING\000"
1623 /* 1287 */ "G_SET_ROUNDING\000"
1624 /* 1302 */ "G_FLOG\000"
1625 /* 1309 */ "G_VAARG\000"
1626 /* 1317 */ "PREALLOCATED_ARG\000"
1627 /* 1334 */ "G_PREFETCH\000"
1628 /* 1345 */ "G_SMULH\000"
1629 /* 1353 */ "G_UMULH\000"
1630 /* 1361 */ "G_FTANH\000"
1631 /* 1369 */ "G_FSINH\000"
1632 /* 1377 */ "G_FCOSH\000"
1633 /* 1385 */ "DBG_PHI\000"
1634 /* 1393 */ "G_FPTOSI\000"
1635 /* 1402 */ "RETI\000"
1636 /* 1407 */ "G_FPTOUI\000"
1637 /* 1416 */ "G_FPOWI\000"
1638 /* 1424 */ "COPY_LANEMASK\000"
1639 /* 1438 */ "G_PTRMASK\000"
1640 /* 1448 */ "GC_LABEL\000"
1641 /* 1457 */ "DBG_LABEL\000"
1642 /* 1467 */ "EH_LABEL\000"
1643 /* 1476 */ "ANNOTATION_LABEL\000"
1644 /* 1493 */ "ICALL_BRANCH_FUNNEL\000"
1645 /* 1513 */ "G_FSHL\000"
1646 /* 1520 */ "G_SHL\000"
1647 /* 1526 */ "G_FCEIL\000"
1648 /* 1534 */ "G_SAVGCEIL\000"
1649 /* 1545 */ "G_UAVGCEIL\000"
1650 /* 1556 */ "PATCHABLE_TAIL_CALL\000"
1651 /* 1576 */ "PATCHABLE_TYPED_EVENT_CALL\000"
1652 /* 1603 */ "PATCHABLE_EVENT_CALL\000"
1653 /* 1624 */ "FENTRY_CALL\000"
1654 /* 1636 */ "KILL\000"
1655 /* 1641 */ "G_CONSTANT_POOL\000"
1656 /* 1657 */ "G_ROTL\000"
1657 /* 1664 */ "G_VECREDUCE_FMUL\000"
1658 /* 1681 */ "G_FMUL\000"
1659 /* 1688 */ "G_VECREDUCE_SEQ_FMUL\000"
1660 /* 1709 */ "G_STRICT_FMUL\000"
1661 /* 1723 */ "G_CLMUL\000"
1662 /* 1731 */ "G_VECREDUCE_MUL\000"
1663 /* 1747 */ "G_MUL\000"
1664 /* 1753 */ "G_FREM\000"
1665 /* 1760 */ "G_STRICT_FREM\000"
1666 /* 1774 */ "G_SREM\000"
1667 /* 1781 */ "G_UREM\000"
1668 /* 1788 */ "G_SDIVREM\000"
1669 /* 1798 */ "G_UDIVREM\000"
1670 /* 1808 */ "INLINEASM\000"
1671 /* 1818 */ "G_VECREDUCE_FMINIMUM\000"
1672 /* 1839 */ "G_FMINIMUM\000"
1673 /* 1850 */ "G_ATOMICRMW_FMINIMUM\000"
1674 /* 1871 */ "G_VECREDUCE_FMAXIMUM\000"
1675 /* 1892 */ "G_FMAXIMUM\000"
1676 /* 1903 */ "G_ATOMICRMW_FMAXIMUM\000"
1677 /* 1924 */ "G_FMINIMUMNUM\000"
1678 /* 1938 */ "G_ATOMICRMW_FMINIMUMNUM\000"
1679 /* 1962 */ "G_FMAXIMUMNUM\000"
1680 /* 1976 */ "G_ATOMICRMW_FMAXIMUMNUM\000"
1681 /* 2000 */ "G_FMINNUM\000"
1682 /* 2010 */ "G_FMAXNUM\000"
1683 /* 2020 */ "G_FATAN\000"
1684 /* 2028 */ "G_FTAN\000"
1685 /* 2035 */ "G_INTRINSIC_ROUNDEVEN\000"
1686 /* 2057 */ "G_ASSERT_ALIGN\000"
1687 /* 2072 */ "G_FCOPYSIGN\000"
1688 /* 2084 */ "G_VECREDUCE_FMIN\000"
1689 /* 2101 */ "G_ATOMICRMW_FMIN\000"
1690 /* 2118 */ "G_VECREDUCE_SMIN\000"
1691 /* 2135 */ "G_SMIN\000"
1692 /* 2142 */ "G_VECREDUCE_UMIN\000"
1693 /* 2159 */ "G_UMIN\000"
1694 /* 2166 */ "G_ATOMICRMW_UMIN\000"
1695 /* 2183 */ "G_ATOMICRMW_MIN\000"
1696 /* 2199 */ "G_FASIN\000"
1697 /* 2207 */ "G_FSIN\000"
1698 /* 2214 */ "CFI_INSTRUCTION\000"
1699 /* 2230 */ "G_CTLZ_ZERO_POISON\000"
1700 /* 2249 */ "G_CTTZ_ZERO_POISON\000"
1701 /* 2268 */ "ADJCALLSTACKDOWN\000"
1702 /* 2285 */ "G_SSUBO\000"
1703 /* 2293 */ "G_USUBO\000"
1704 /* 2301 */ "G_SADDO\000"
1705 /* 2309 */ "G_UADDO\000"
1706 /* 2317 */ "JUMP_TABLE_DEBUG_INFO\000"
1707 /* 2339 */ "G_SMULO\000"
1708 /* 2347 */ "G_UMULO\000"
1709 /* 2355 */ "G_BZERO\000"
1710 /* 2363 */ "STACKMAP\000"
1711 /* 2372 */ "G_DEBUGTRAP\000"
1712 /* 2384 */ "G_UBSANTRAP\000"
1713 /* 2396 */ "G_TRAP\000"
1714 /* 2403 */ "G_ATOMICRMW_UDEC_WRAP\000"
1715 /* 2425 */ "G_ATOMICRMW_UINC_WRAP\000"
1716 /* 2447 */ "G_BSWAP\000"
1717 /* 2455 */ "G_SITOFP\000"
1718 /* 2464 */ "G_UITOFP\000"
1719 /* 2473 */ "G_FCMP\000"
1720 /* 2480 */ "G_STRICT_FCMP\000"
1721 /* 2494 */ "G_ICMP\000"
1722 /* 2501 */ "G_SCMP\000"
1723 /* 2508 */ "G_UCMP\000"
1724 /* 2515 */ "JMP\000"
1725 /* 2519 */ "CONVERGENCECTRL_LOOP\000"
1726 /* 2540 */ "G_CTPOP\000"
1727 /* 2548 */ "PATCHABLE_OP\000"
1728 /* 2561 */ "FAULTING_OP\000"
1729 /* 2573 */ "ADJCALLSTACKUP\000"
1730 /* 2588 */ "PREALLOCATED_SETUP\000"
1731 /* 2607 */ "G_FLDEXP\000"
1732 /* 2616 */ "G_STRICT_FLDEXP\000"
1733 /* 2632 */ "G_FEXP\000"
1734 /* 2639 */ "G_FFREXP\000"
1735 /* 2648 */ "G_BR\000"
1736 /* 2653 */ "INLINEASM_BR\000"
1737 /* 2666 */ "G_BLOCK_ADDR\000"
1738 /* 2679 */ "MEMBARRIER\000"
1739 /* 2690 */ "G_CONSTANT_FOLD_BARRIER\000"
1740 /* 2714 */ "PATCHABLE_FUNCTION_ENTER\000"
1741 /* 2739 */ "G_READCYCLECOUNTER\000"
1742 /* 2758 */ "G_READSTEADYCOUNTER\000"
1743 /* 2778 */ "G_READ_REGISTER\000"
1744 /* 2794 */ "G_WRITE_REGISTER\000"
1745 /* 2811 */ "G_ASHR\000"
1746 /* 2818 */ "G_FSHR\000"
1747 /* 2825 */ "G_LSHR\000"
1748 /* 2832 */ "CONVERGENCECTRL_ANCHOR\000"
1749 /* 2855 */ "G_FFLOOR\000"
1750 /* 2864 */ "G_SAVGFLOOR\000"
1751 /* 2876 */ "G_UAVGFLOOR\000"
1752 /* 2888 */ "G_EXTRACT_SUBVECTOR\000"
1753 /* 2908 */ "G_INSERT_SUBVECTOR\000"
1754 /* 2927 */ "G_BUILD_VECTOR\000"
1755 /* 2942 */ "G_SHUFFLE_VECTOR\000"
1756 /* 2959 */ "G_STEP_VECTOR\000"
1757 /* 2973 */ "G_SPLAT_VECTOR\000"
1758 /* 2988 */ "G_VECREDUCE_XOR\000"
1759 /* 3004 */ "G_XOR\000"
1760 /* 3010 */ "G_ATOMICRMW_XOR\000"
1761 /* 3026 */ "G_VECREDUCE_OR\000"
1762 /* 3041 */ "G_OR\000"
1763 /* 3046 */ "G_ATOMICRMW_OR\000"
1764 /* 3061 */ "G_ROTR\000"
1765 /* 3068 */ "G_INTTOPTR\000"
1766 /* 3079 */ "G_FABS\000"
1767 /* 3086 */ "G_ABS\000"
1768 /* 3092 */ "G_ABDS\000"
1769 /* 3099 */ "G_UNMERGE_VALUES\000"
1770 /* 3116 */ "G_MERGE_VALUES\000"
1771 /* 3131 */ "G_CTLS\000"
1772 /* 3138 */ "G_FACOS\000"
1773 /* 3146 */ "G_FCOS\000"
1774 /* 3153 */ "G_FSINCOS\000"
1775 /* 3163 */ "G_STRICT_FCMPS\000"
1776 /* 3178 */ "G_CONCAT_VECTORS\000"
1777 /* 3195 */ "COPY_TO_REGCLASS\000"
1778 /* 3212 */ "G_IS_FPCLASS\000"
1779 /* 3225 */ "G_ATOMIC_CMPXCHG_WITH_SUCCESS\000"
1780 /* 3255 */ "G_VECTOR_COMPRESS\000"
1781 /* 3273 */ "G_INTRINSIC_W_SIDE_EFFECTS\000"
1782 /* 3300 */ "G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS\000"
1783 /* 3338 */ "G_TRUNC_SSAT_S\000"
1784 /* 3353 */ "G_SSUBSAT\000"
1785 /* 3363 */ "G_USUBSAT\000"
1786 /* 3373 */ "G_SADDSAT\000"
1787 /* 3383 */ "G_UADDSAT\000"
1788 /* 3393 */ "G_SSHLSAT\000"
1789 /* 3403 */ "G_USHLSAT\000"
1790 /* 3413 */ "G_SMULFIXSAT\000"
1791 /* 3426 */ "G_UMULFIXSAT\000"
1792 /* 3439 */ "G_SDIVFIXSAT\000"
1793 /* 3452 */ "G_UDIVFIXSAT\000"
1794 /* 3465 */ "G_ATOMICRMW_USUB_SAT\000"
1795 /* 3486 */ "G_FPTOSI_SAT\000"
1796 /* 3499 */ "G_FPTOUI_SAT\000"
1797 /* 3512 */ "G_EXTRACT\000"
1798 /* 3522 */ "G_SELECT\000"
1799 /* 3531 */ "G_BRINDIRECT\000"
1800 /* 3544 */ "PATCHABLE_RET\000"
1801 /* 3558 */ "G_MEMSET\000"
1802 /* 3567 */ "PATCHABLE_FUNCTION_EXIT\000"
1803 /* 3591 */ "G_BRJT\000"
1804 /* 3598 */ "G_EXTRACT_VECTOR_ELT\000"
1805 /* 3619 */ "G_INSERT_VECTOR_ELT\000"
1806 /* 3639 */ "G_FCONSTANT\000"
1807 /* 3651 */ "G_CONSTANT\000"
1808 /* 3662 */ "G_INTRINSIC_CONVERGENT\000"
1809 /* 3685 */ "STATEPOINT\000"
1810 /* 3696 */ "PATCHPOINT\000"
1811 /* 3707 */ "G_PTRTOINT\000"
1812 /* 3718 */ "G_FRINT\000"
1813 /* 3726 */ "G_INTRINSIC_LLRINT\000"
1814 /* 3745 */ "G_INTRINSIC_LRINT\000"
1815 /* 3763 */ "G_FNEARBYINT\000"
1816 /* 3776 */ "G_VASTART\000"
1817 /* 3786 */ "LIFETIME_START\000"
1818 /* 3801 */ "G_INVOKE_REGION_START\000"
1819 /* 3823 */ "G_INSERT\000"
1820 /* 3832 */ "G_FSQRT\000"
1821 /* 3840 */ "G_STRICT_FSQRT\000"
1822 /* 3855 */ "G_BITCAST\000"
1823 /* 3865 */ "G_ADDRSPACE_CAST\000"
1824 /* 3882 */ "DBG_VALUE_LIST\000"
1825 /* 3897 */ "G_FPEXT\000"
1826 /* 3905 */ "G_SEXT\000"
1827 /* 3912 */ "G_ASSERT_SEXT\000"
1828 /* 3926 */ "G_ANYEXT\000"
1829 /* 3935 */ "G_ZEXT\000"
1830 /* 3942 */ "G_ASSERT_ZEXT\000"
1831 /* 3956 */ "G_ABDU\000"
1832 /* 3963 */ "G_TRUNC_SSAT_U\000"
1833 /* 3978 */ "G_TRUNC_USAT_U\000"
1834 /* 3993 */ "G_FDIV\000"
1835 /* 4000 */ "G_STRICT_FDIV\000"
1836 /* 4014 */ "G_SDIV\000"
1837 /* 4021 */ "G_UDIV\000"
1838 /* 4028 */ "G_GET_FPENV\000"
1839 /* 4040 */ "G_RESET_FPENV\000"
1840 /* 4054 */ "G_SET_FPENV\000"
1841 /* 4066 */ "G_FPOW\000"
1842 /* 4073 */ "G_VECREDUCE_FMAX\000"
1843 /* 4090 */ "G_ATOMICRMW_FMAX\000"
1844 /* 4107 */ "G_VECREDUCE_SMAX\000"
1845 /* 4124 */ "G_SMAX\000"
1846 /* 4131 */ "G_VECREDUCE_UMAX\000"
1847 /* 4148 */ "G_UMAX\000"
1848 /* 4155 */ "G_ATOMICRMW_UMAX\000"
1849 /* 4172 */ "G_ATOMICRMW_MAX\000"
1850 /* 4188 */ "G_FRAME_INDEX\000"
1851 /* 4202 */ "G_SBFX\000"
1852 /* 4209 */ "G_UBFX\000"
1853 /* 4216 */ "G_SMULFIX\000"
1854 /* 4226 */ "G_UMULFIX\000"
1855 /* 4236 */ "G_SDIVFIX\000"
1856 /* 4246 */ "G_UDIVFIX\000"
1857 /* 4256 */ "G_MEMCPY\000"
1858 /* 4265 */ "COPY\000"
1859 /* 4270 */ "CONVERGENCECTRL_ENTRY\000"
1860 /* 4292 */ "G_CTLZ\000"
1861 /* 4299 */ "G_CTTZ\000"
1862 /* 4306 */ "PUSH16c\000"
1863 /* 4314 */ "SUB16mc\000"
1864 /* 4322 */ "SUBC16mc\000"
1865 /* 4331 */ "ADDC16mc\000"
1866 /* 4340 */ "BIC16mc\000"
1867 /* 4348 */ "DADD16mc\000"
1868 /* 4357 */ "AND16mc\000"
1869 /* 4365 */ "CMP16mc\000"
1870 /* 4373 */ "XOR16mc\000"
1871 /* 4381 */ "BIS16mc\000"
1872 /* 4389 */ "BIT16mc\000"
1873 /* 4397 */ "MOV16mc\000"
1874 /* 4405 */ "SUB8mc\000"
1875 /* 4412 */ "SUBC8mc\000"
1876 /* 4420 */ "ADDC8mc\000"
1877 /* 4428 */ "BIC8mc\000"
1878 /* 4435 */ "DADD8mc\000"
1879 /* 4443 */ "AND8mc\000"
1880 /* 4450 */ "CMP8mc\000"
1881 /* 4457 */ "XOR8mc\000"
1882 /* 4464 */ "BIS8mc\000"
1883 /* 4471 */ "BIT8mc\000"
1884 /* 4478 */ "MOV8mc\000"
1885 /* 4485 */ "SUB16rc\000"
1886 /* 4493 */ "SUBC16rc\000"
1887 /* 4502 */ "ADDC16rc\000"
1888 /* 4511 */ "BIC16rc\000"
1889 /* 4519 */ "DADD16rc\000"
1890 /* 4528 */ "AND16rc\000"
1891 /* 4536 */ "CMP16rc\000"
1892 /* 4544 */ "XOR16rc\000"
1893 /* 4552 */ "BIS16rc\000"
1894 /* 4560 */ "BIT16rc\000"
1895 /* 4568 */ "MOV16rc\000"
1896 /* 4576 */ "SUB8rc\000"
1897 /* 4583 */ "SUBC8rc\000"
1898 /* 4591 */ "ADDC8rc\000"
1899 /* 4599 */ "BIC8rc\000"
1900 /* 4606 */ "DADD8rc\000"
1901 /* 4614 */ "AND8rc\000"
1902 /* 4621 */ "CMP8rc\000"
1903 /* 4628 */ "XOR8rc\000"
1904 /* 4635 */ "BIS8rc\000"
1905 /* 4642 */ "BIT8rc\000"
1906 /* 4649 */ "MOV8rc\000"
1907 /* 4656 */ "ADDframe\000"
1908 /* 4665 */ "PUSH16i\000"
1909 /* 4673 */ "Bi\000"
1910 /* 4676 */ "CALLi\000"
1911 /* 4682 */ "SUB16mi\000"
1912 /* 4690 */ "SUBC16mi\000"
1913 /* 4699 */ "ADDC16mi\000"
1914 /* 4708 */ "BIC16mi\000"
1915 /* 4716 */ "DADD16mi\000"
1916 /* 4725 */ "AND16mi\000"
1917 /* 4733 */ "CMP16mi\000"
1918 /* 4741 */ "XOR16mi\000"
1919 /* 4749 */ "BIS16mi\000"
1920 /* 4757 */ "BIT16mi\000"
1921 /* 4765 */ "MOV16mi\000"
1922 /* 4773 */ "SUB8mi\000"
1923 /* 4780 */ "SUBC8mi\000"
1924 /* 4788 */ "ADDC8mi\000"
1925 /* 4796 */ "BIC8mi\000"
1926 /* 4803 */ "DADD8mi\000"
1927 /* 4811 */ "AND8mi\000"
1928 /* 4818 */ "CMP8mi\000"
1929 /* 4825 */ "XOR8mi\000"
1930 /* 4832 */ "BIS8mi\000"
1931 /* 4839 */ "BIT8mi\000"
1932 /* 4846 */ "MOV8mi\000"
1933 /* 4853 */ "SUB16ri\000"
1934 /* 4861 */ "SUBC16ri\000"
1935 /* 4870 */ "ADDC16ri\000"
1936 /* 4879 */ "BIC16ri\000"
1937 /* 4887 */ "DADD16ri\000"
1938 /* 4896 */ "AND16ri\000"
1939 /* 4904 */ "CMP16ri\000"
1940 /* 4912 */ "XOR16ri\000"
1941 /* 4920 */ "BIS16ri\000"
1942 /* 4928 */ "BIT16ri\000"
1943 /* 4936 */ "MOV16ri\000"
1944 /* 4944 */ "SUB8ri\000"
1945 /* 4951 */ "SUBC8ri\000"
1946 /* 4959 */ "ADDC8ri\000"
1947 /* 4967 */ "BIC8ri\000"
1948 /* 4974 */ "DADD8ri\000"
1949 /* 4982 */ "AND8ri\000"
1950 /* 4989 */ "CMP8ri\000"
1951 /* 4996 */ "XOR8ri\000"
1952 /* 5003 */ "BIS8ri\000"
1953 /* 5010 */ "BIT8ri\000"
1954 /* 5017 */ "MOV8ri\000"
1955 /* 5024 */ "RRA16m\000"
1956 /* 5031 */ "SWPB16m\000"
1957 /* 5039 */ "RRC16m\000"
1958 /* 5046 */ "SEXT16m\000"
1959 /* 5054 */ "RRA8m\000"
1960 /* 5060 */ "RRC8m\000"
1961 /* 5066 */ "Bm\000"
1962 /* 5069 */ "CALLm\000"
1963 /* 5075 */ "SUB16mm\000"
1964 /* 5083 */ "SUBC16mm\000"
1965 /* 5092 */ "ADDC16mm\000"
1966 /* 5101 */ "BIC16mm\000"
1967 /* 5109 */ "DADD16mm\000"
1968 /* 5118 */ "AND16mm\000"
1969 /* 5126 */ "CMP16mm\000"
1970 /* 5134 */ "XOR16mm\000"
1971 /* 5142 */ "BIS16mm\000"
1972 /* 5150 */ "BIT16mm\000"
1973 /* 5158 */ "MOV16mm\000"
1974 /* 5166 */ "SUB8mm\000"
1975 /* 5173 */ "SUBC8mm\000"
1976 /* 5181 */ "ADDC8mm\000"
1977 /* 5189 */ "BIC8mm\000"
1978 /* 5196 */ "DADD8mm\000"
1979 /* 5204 */ "AND8mm\000"
1980 /* 5211 */ "CMP8mm\000"
1981 /* 5218 */ "XOR8mm\000"
1982 /* 5225 */ "BIS8mm\000"
1983 /* 5232 */ "BIT8mm\000"
1984 /* 5239 */ "MOV8mm\000"
1985 /* 5246 */ "SUB16rm\000"
1986 /* 5254 */ "SUBC16rm\000"
1987 /* 5263 */ "ADDC16rm\000"
1988 /* 5272 */ "BIC16rm\000"
1989 /* 5280 */ "DADD16rm\000"
1990 /* 5289 */ "AND16rm\000"
1991 /* 5297 */ "CMP16rm\000"
1992 /* 5305 */ "XOR16rm\000"
1993 /* 5313 */ "BIS16rm\000"
1994 /* 5321 */ "BIT16rm\000"
1995 /* 5329 */ "MOV16rm\000"
1996 /* 5337 */ "SUB8rm\000"
1997 /* 5344 */ "SUBC8rm\000"
1998 /* 5352 */ "ADDC8rm\000"
1999 /* 5360 */ "BIC8rm\000"
2000 /* 5367 */ "DADD8rm\000"
2001 /* 5375 */ "AND8rm\000"
2002 /* 5382 */ "CMP8rm\000"
2003 /* 5389 */ "XOR8rm\000"
2004 /* 5396 */ "BIS8rm\000"
2005 /* 5403 */ "BIT8rm\000"
2006 /* 5410 */ "MOV8rm\000"
2007 /* 5417 */ "RRA16n\000"
2008 /* 5424 */ "SWPB16n\000"
2009 /* 5432 */ "RRC16n\000"
2010 /* 5439 */ "SEXT16n\000"
2011 /* 5447 */ "RRA8n\000"
2012 /* 5453 */ "RRC8n\000"
2013 /* 5459 */ "CALLn\000"
2014 /* 5465 */ "SUB16mn\000"
2015 /* 5473 */ "SUBC16mn\000"
2016 /* 5482 */ "ADDC16mn\000"
2017 /* 5491 */ "BIC16mn\000"
2018 /* 5499 */ "DADD16mn\000"
2019 /* 5508 */ "AND16mn\000"
2020 /* 5516 */ "CMP16mn\000"
2021 /* 5524 */ "XOR16mn\000"
2022 /* 5532 */ "BIS16mn\000"
2023 /* 5540 */ "BIT16mn\000"
2024 /* 5548 */ "MOV16mn\000"
2025 /* 5556 */ "SUB8mn\000"
2026 /* 5563 */ "SUBC8mn\000"
2027 /* 5571 */ "ADDC8mn\000"
2028 /* 5579 */ "BIC8mn\000"
2029 /* 5586 */ "DADD8mn\000"
2030 /* 5594 */ "AND8mn\000"
2031 /* 5601 */ "CMP8mn\000"
2032 /* 5608 */ "XOR8mn\000"
2033 /* 5615 */ "BIS8mn\000"
2034 /* 5622 */ "BIT8mn\000"
2035 /* 5629 */ "MOV8mn\000"
2036 /* 5636 */ "SUB16rn\000"
2037 /* 5644 */ "SUBC16rn\000"
2038 /* 5653 */ "ADDC16rn\000"
2039 /* 5662 */ "BIC16rn\000"
2040 /* 5670 */ "DADD16rn\000"
2041 /* 5679 */ "AND16rn\000"
2042 /* 5687 */ "CMP16rn\000"
2043 /* 5695 */ "XOR16rn\000"
2044 /* 5703 */ "BIS16rn\000"
2045 /* 5711 */ "BIT16rn\000"
2046 /* 5719 */ "MOV16rn\000"
2047 /* 5727 */ "SUB8rn\000"
2048 /* 5734 */ "SUBC8rn\000"
2049 /* 5742 */ "ADDC8rn\000"
2050 /* 5750 */ "BIC8rn\000"
2051 /* 5757 */ "DADD8rn\000"
2052 /* 5765 */ "AND8rn\000"
2053 /* 5772 */ "CMP8rn\000"
2054 /* 5779 */ "XOR8rn\000"
2055 /* 5786 */ "BIS8rn\000"
2056 /* 5793 */ "BIT8rn\000"
2057 /* 5800 */ "MOV8rn\000"
2058 /* 5807 */ "RRA16p\000"
2059 /* 5814 */ "SWPB16p\000"
2060 /* 5822 */ "RRC16p\000"
2061 /* 5829 */ "SEXT16p\000"
2062 /* 5837 */ "RRA8p\000"
2063 /* 5843 */ "RRC8p\000"
2064 /* 5849 */ "CALLp\000"
2065 /* 5855 */ "SUB16mp\000"
2066 /* 5863 */ "SUBC16mp\000"
2067 /* 5872 */ "ADDC16mp\000"
2068 /* 5881 */ "BIC16mp\000"
2069 /* 5889 */ "DADD16mp\000"
2070 /* 5898 */ "AND16mp\000"
2071 /* 5906 */ "CMP16mp\000"
2072 /* 5914 */ "XOR16mp\000"
2073 /* 5922 */ "BIS16mp\000"
2074 /* 5930 */ "BIT16mp\000"
2075 /* 5938 */ "SUB8mp\000"
2076 /* 5945 */ "SUBC8mp\000"
2077 /* 5953 */ "ADDC8mp\000"
2078 /* 5961 */ "BIC8mp\000"
2079 /* 5968 */ "DADD8mp\000"
2080 /* 5976 */ "AND8mp\000"
2081 /* 5983 */ "CMP8mp\000"
2082 /* 5990 */ "XOR8mp\000"
2083 /* 5997 */ "BIS8mp\000"
2084 /* 6004 */ "BIT8mp\000"
2085 /* 6011 */ "SUB16rp\000"
2086 /* 6019 */ "SUBC16rp\000"
2087 /* 6028 */ "ADDC16rp\000"
2088 /* 6037 */ "BIC16rp\000"
2089 /* 6045 */ "DADD16rp\000"
2090 /* 6054 */ "AND16rp\000"
2091 /* 6062 */ "CMP16rp\000"
2092 /* 6070 */ "XOR16rp\000"
2093 /* 6078 */ "BIS16rp\000"
2094 /* 6086 */ "BIT16rp\000"
2095 /* 6094 */ "MOV16rp\000"
2096 /* 6102 */ "SUB8rp\000"
2097 /* 6109 */ "SUBC8rp\000"
2098 /* 6117 */ "ADDC8rp\000"
2099 /* 6125 */ "BIC8rp\000"
2100 /* 6132 */ "DADD8rp\000"
2101 /* 6140 */ "AND8rp\000"
2102 /* 6147 */ "CMP8rp\000"
2103 /* 6154 */ "XOR8rp\000"
2104 /* 6161 */ "BIS8rp\000"
2105 /* 6168 */ "BIT8rp\000"
2106 /* 6175 */ "MOV8rp\000"
2107 /* 6182 */ "RRA16r\000"
2108 /* 6189 */ "SWPB16r\000"
2109 /* 6197 */ "RRC16r\000"
2110 /* 6204 */ "PUSH16r\000"
2111 /* 6212 */ "POP16r\000"
2112 /* 6219 */ "SEXT16r\000"
2113 /* 6227 */ "ZEXT16r\000"
2114 /* 6235 */ "RRA8r\000"
2115 /* 6241 */ "RRC8r\000"
2116 /* 6247 */ "PUSH8r\000"
2117 /* 6254 */ "Br\000"
2118 /* 6257 */ "CALLr\000"
2119 /* 6263 */ "SUB16mr\000"
2120 /* 6271 */ "SUBC16mr\000"
2121 /* 6280 */ "ADDC16mr\000"
2122 /* 6289 */ "BIC16mr\000"
2123 /* 6297 */ "DADD16mr\000"
2124 /* 6306 */ "AND16mr\000"
2125 /* 6314 */ "CMP16mr\000"
2126 /* 6322 */ "XOR16mr\000"
2127 /* 6330 */ "BIS16mr\000"
2128 /* 6338 */ "BIT16mr\000"
2129 /* 6346 */ "MOV16mr\000"
2130 /* 6354 */ "SUB8mr\000"
2131 /* 6361 */ "SUBC8mr\000"
2132 /* 6369 */ "ADDC8mr\000"
2133 /* 6377 */ "BIC8mr\000"
2134 /* 6384 */ "DADD8mr\000"
2135 /* 6392 */ "AND8mr\000"
2136 /* 6399 */ "CMP8mr\000"
2137 /* 6406 */ "XOR8mr\000"
2138 /* 6413 */ "BIS8mr\000"
2139 /* 6420 */ "BIT8mr\000"
2140 /* 6427 */ "MOV8mr\000"
2141 /* 6434 */ "SUB16rr\000"
2142 /* 6442 */ "SUBC16rr\000"
2143 /* 6451 */ "ADDC16rr\000"
2144 /* 6460 */ "BIC16rr\000"
2145 /* 6468 */ "DADD16rr\000"
2146 /* 6477 */ "AND16rr\000"
2147 /* 6485 */ "CMP16rr\000"
2148 /* 6493 */ "XOR16rr\000"
2149 /* 6501 */ "BIS16rr\000"
2150 /* 6509 */ "BIT16rr\000"
2151 /* 6517 */ "MOV16rr\000"
2152 /* 6525 */ "SUB8rr\000"
2153 /* 6532 */ "SUBC8rr\000"
2154 /* 6540 */ "ADDC8rr\000"
2155 /* 6548 */ "BIC8rr\000"
2156 /* 6555 */ "DADD8rr\000"
2157 /* 6563 */ "AND8rr\000"
2158 /* 6570 */ "CMP8rr\000"
2159 /* 6577 */ "XOR8rr\000"
2160 /* 6584 */ "BIS8rr\000"
2161 /* 6591 */ "BIT8rr\000"
2162 /* 6598 */ "MOV8rr\000"
2163};
2164#ifdef __GNUC__
2165#pragma GCC diagnostic pop
2166#endif
2167
2168extern const unsigned MSP430InstrNameIndices[] = {
2169 1389U, 1808U, 2653U, 2214U, 1467U, 1448U, 1476U, 1636U,
2170 1182U, 1197U, 1148U, 1135U, 1224U, 3195U, 1011U, 3882U,
2171 1161U, 1385U, 1457U, 750U, 4265U, 1424U, 872U, 3786U,
2172 577U, 701U, 738U, 2363U, 1624U, 3696U, 684U, 2588U,
2173 1317U, 3685U, 922U, 2561U, 2548U, 2714U, 3544U, 3567U,
2174 1556U, 1603U, 1576U, 1493U, 1002U, 2679U, 2317U, 911U,
2175 4270U, 2832U, 2519U, 1059U, 3912U, 3942U, 2057U, 490U,
2176 185U, 1747U, 4014U, 4021U, 1774U, 1781U, 1788U, 1798U,
2177 555U, 3041U, 3004U, 3092U, 3956U, 2876U, 1545U, 2864U,
2178 1534U, 1146U, 1387U, 4188U, 1021U, 1036U, 1641U, 3512U,
2179 3099U, 3823U, 3116U, 2927U, 259U, 3178U, 3707U, 3068U,
2180 3855U, 1102U, 2690U, 658U, 233U, 640U, 3745U, 3726U,
2181 2035U, 2739U, 2758U, 391U, 335U, 365U, 304U, 376U,
2182 316U, 346U, 981U, 935U, 965U, 3225U, 1238U, 1255U,
2183 506U, 191U, 561U, 522U, 3046U, 3010U, 4172U, 2183U,
2184 4155U, 2166U, 457U, 168U, 4090U, 2101U, 1903U, 1850U,
2185 1976U, 1938U, 2425U, 2403U, 599U, 3465U, 730U, 1334U,
2186 590U, 3531U, 3801U, 211U, 3273U, 3662U, 3300U, 3926U,
2187 251U, 3338U, 3963U, 3978U, 3651U, 3639U, 3776U, 1309U,
2188 3905U, 1211U, 3935U, 1520U, 2825U, 2811U, 1513U, 2818U,
2189 3061U, 1657U, 2494U, 2473U, 2501U, 2508U, 3522U, 2309U,
2190 771U, 2293U, 722U, 2301U, 763U, 2285U, 714U, 2347U,
2191 2339U, 1353U, 1345U, 3383U, 3373U, 3363U, 3353U, 3403U,
2192 3393U, 4216U, 4226U, 3413U, 3426U, 4236U, 4246U, 3439U,
2193 3452U, 415U, 147U, 1681U, 128U, 297U, 3993U, 1753U,
2194 1127U, 4066U, 1416U, 2632U, 35U, 9U, 1302U, 18U,
2195 0U, 2607U, 2639U, 1175U, 3897U, 223U, 1393U, 1407U,
2196 2455U, 2464U, 3486U, 3499U, 3079U, 2072U, 3212U, 1111U,
2197 2000U, 2010U, 820U, 835U, 1839U, 1892U, 1924U, 1962U,
2198 4028U, 4054U, 4040U, 779U, 807U, 792U, 1272U, 1287U,
2199 496U, 1438U, 2135U, 4124U, 2159U, 4148U, 3086U, 631U,
2200 621U, 2648U, 3591U, 850U, 2908U, 2888U, 3619U, 3598U,
2201 2942U, 2973U, 2959U, 3255U, 4299U, 2249U, 4292U, 2230U,
2202 3131U, 2540U, 2447U, 989U, 1723U, 1526U, 3146U, 2207U,
2203 3153U, 2028U, 3138U, 2199U, 2020U, 26U, 1377U, 1369U,
2204 1361U, 3832U, 2855U, 3718U, 3763U, 3865U, 2666U, 859U,
2205 280U, 1080U, 950U, 443U, 154U, 1709U, 4000U, 1760U,
2206 134U, 3840U, 2616U, 2480U, 3163U, 2778U, 2794U, 4256U,
2207 895U, 1092U, 3558U, 2355U, 879U, 2396U, 2372U, 2384U,
2208 422U, 1688U, 398U, 1664U, 4073U, 2084U, 1871U, 1818U,
2209 474U, 1731U, 539U, 3026U, 2988U, 4107U, 2118U, 4131U,
2210 2142U, 4202U, 4209U, 4349U, 4717U, 5110U, 5500U, 5890U,
2211 6298U, 4520U, 4888U, 5281U, 5671U, 6046U, 6469U, 4436U,
2212 4804U, 5197U, 5587U, 5969U, 6385U, 4607U, 4975U, 5368U,
2213 5758U, 6133U, 6556U, 4331U, 4699U, 5092U, 5482U, 5872U,
2214 6280U, 4502U, 4870U, 5263U, 5653U, 6028U, 6451U, 4420U,
2215 4788U, 5181U, 5571U, 5953U, 6369U, 4591U, 4959U, 5352U,
2216 5742U, 6117U, 6540U, 4656U, 2268U, 2573U, 4357U, 4725U,
2217 5118U, 5508U, 5898U, 6306U, 4528U, 4896U, 5289U, 5679U,
2218 6054U, 6477U, 4443U, 4811U, 5204U, 5594U, 5976U, 6392U,
2219 4614U, 4982U, 5375U, 5765U, 6140U, 6563U, 4340U, 4708U,
2220 5101U, 5491U, 5881U, 6289U, 4511U, 4879U, 5272U, 5662U,
2221 6037U, 6460U, 4428U, 4796U, 5189U, 5579U, 5961U, 6377U,
2222 4599U, 4967U, 5360U, 5750U, 6125U, 6548U, 4381U, 4749U,
2223 5142U, 5532U, 5922U, 6330U, 4552U, 4920U, 5313U, 5703U,
2224 6078U, 6501U, 4464U, 4832U, 5225U, 5615U, 5997U, 6413U,
2225 4635U, 5003U, 5396U, 5786U, 6161U, 6584U, 4389U, 4757U,
2226 5150U, 5540U, 5930U, 6338U, 4560U, 4928U, 5321U, 5711U,
2227 6086U, 6509U, 4471U, 4839U, 5232U, 5622U, 6004U, 6420U,
2228 4642U, 5010U, 5403U, 5793U, 6168U, 6591U, 4673U, 5066U,
2229 6254U, 4676U, 5069U, 5459U, 5849U, 6257U, 4365U, 4733U,
2230 5126U, 5516U, 5906U, 6314U, 4536U, 4904U, 5297U, 5687U,
2231 6062U, 6485U, 4450U, 4818U, 5211U, 5601U, 5983U, 6399U,
2232 4621U, 4989U, 5382U, 5772U, 6147U, 6570U, 4348U, 4716U,
2233 5109U, 5499U, 5889U, 6297U, 4519U, 4887U, 5280U, 5670U,
2234 6045U, 6468U, 4435U, 4803U, 5196U, 5586U, 5968U, 6384U,
2235 4606U, 4974U, 5367U, 5757U, 6132U, 6555U, 207U, 2515U,
2236 4397U, 4765U, 5158U, 5548U, 6346U, 4568U, 4936U, 5329U,
2237 5719U, 6094U, 6517U, 4478U, 4846U, 5239U, 5629U, 6427U,
2238 4649U, 5017U, 5410U, 5800U, 6175U, 6598U, 98U, 109U,
2239 6212U, 4306U, 4665U, 6204U, 6247U, 3554U, 1402U, 5024U,
2240 5417U, 5807U, 6182U, 5054U, 5447U, 5837U, 6235U, 5039U,
2241 5432U, 5822U, 6197U, 5060U, 5453U, 5843U, 6241U, 49U,
2242 82U, 5046U, 5439U, 5829U, 6219U, 4314U, 4682U, 5075U,
2243 5465U, 5855U, 6263U, 4485U, 4853U, 5246U, 5636U, 6011U,
2244 6434U, 4405U, 4773U, 5166U, 5556U, 5938U, 6354U, 4576U,
2245 4944U, 5337U, 5727U, 6102U, 6525U, 4322U, 4690U, 5083U,
2246 5473U, 5863U, 6271U, 4493U, 4861U, 5254U, 5644U, 6019U,
2247 6442U, 4412U, 4780U, 5173U, 5563U, 5945U, 6361U, 4583U,
2248 4951U, 5344U, 5734U, 6109U, 6532U, 5031U, 5424U, 5814U,
2249 6189U, 68U, 120U, 56U, 88U, 43U, 77U, 62U,
2250 93U, 4373U, 4741U, 5134U, 5524U, 5914U, 6322U, 4544U,
2251 4912U, 5305U, 5695U, 6070U, 6493U, 4457U, 4825U, 5218U,
2252 5608U, 5990U, 6406U, 4628U, 4996U, 5389U, 5779U, 6154U,
2253 6577U, 6227U,
2254};
2255
2256static inline void InitMSP430MCInstrInfo(MCInstrInfo *II) {
2257 II->InitMCInstrInfo(MSP430Descs.Insts, MSP430InstrNameIndices, MSP430InstrNameData, nullptr, nullptr, 674, nullptr, 0);
2258}
2259
2260
2261} // namespace llvm
2262
2263#endif // GET_INSTRINFO_MC_DESC
2264
2265#ifdef GET_INSTRINFO_HEADER
2266#undef GET_INSTRINFO_HEADER
2267
2268namespace llvm {
2269
2270struct MSP430GenInstrInfo : public TargetInstrInfo {
2271 explicit MSP430GenInstrInfo(const TargetSubtargetInfo &STI, const TargetRegisterInfo &TRI, unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u, unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u);
2272 ~MSP430GenInstrInfo() override = default;
2273};
2274
2275} // namespace llvm
2276
2277namespace llvm::MSP430 {
2278
2279
2280} // namespace llvm::MSP430
2281
2282#endif // GET_INSTRINFO_HEADER
2283
2284#ifdef GET_INSTRINFO_HELPER_DECLS
2285#undef GET_INSTRINFO_HELPER_DECLS
2286
2287
2288#endif // GET_INSTRINFO_HELPER_DECLS
2289
2290#ifdef GET_INSTRINFO_HELPERS
2291#undef GET_INSTRINFO_HELPERS
2292
2293
2294#endif // GET_INSTRINFO_HELPERS
2295
2296#ifdef GET_INSTRINFO_CTOR_DTOR
2297#undef GET_INSTRINFO_CTOR_DTOR
2298
2299namespace llvm {
2300
2301extern const MSP430InstrTable MSP430Descs;
2302extern const unsigned MSP430InstrNameIndices[];
2303extern const char MSP430InstrNameData[];
2304MSP430GenInstrInfo::MSP430GenInstrInfo(const TargetSubtargetInfo &STI, const TargetRegisterInfo &TRI, unsigned CFSetupOpcode, unsigned CFDestroyOpcode, unsigned CatchRetOpcode, unsigned ReturnOpcode)
2305 : TargetInstrInfo(TRI, CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) {
2306 InitMCInstrInfo(MSP430Descs.Insts, MSP430InstrNameIndices, MSP430InstrNameData, nullptr, nullptr, 674);
2307}
2308
2309} // namespace llvm
2310
2311#endif // GET_INSTRINFO_CTOR_DTOR
2312
2313#ifdef GET_INSTRINFO_MC_HELPER_DECLS
2314#undef GET_INSTRINFO_MC_HELPER_DECLS
2315
2316namespace llvm {
2317
2318class MCInst;
2319class FeatureBitset;
2320
2321namespace MSP430_MC {
2322
2323void verifyInstructionPredicates(unsigned Opcode, const FeatureBitset &Features);
2324
2325} // namespace MSP430_MC
2326
2327} // namespace llvm
2328
2329#endif // GET_INSTRINFO_MC_HELPER_DECLS
2330
2331#ifdef GET_INSTRINFO_MC_HELPERS
2332#undef GET_INSTRINFO_MC_HELPERS
2333
2334namespace llvm::MSP430_MC {
2335
2336
2337} // namespace llvm::MSP430_MC
2338
2339#endif // GET_INSTRINFO_MC_HELPERS
2340
2341#if (defined(ENABLE_INSTR_PREDICATE_VERIFIER) && !defined(NDEBUG)) ||\
2342 defined(GET_AVAILABLE_OPCODE_CHECKER)
2343#define GET_COMPUTE_FEATURES
2344#endif
2345#ifdef GET_COMPUTE_FEATURES
2346#undef GET_COMPUTE_FEATURES
2347
2348namespace llvm::MSP430_MC {
2349
2350// Bits for subtarget features that participate in instruction matching.
2351enum SubtargetFeatureBits : uint8_t {
2352};
2353
2354inline FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) {
2355 FeatureBitset Features;
2356 return Features;
2357}
2358
2359inline FeatureBitset computeRequiredFeatures(unsigned Opcode) {
2360 enum : uint8_t {
2361 CEFBS_None,
2362 };
2363
2364 static constexpr FeatureBitset FeatureBitsets[] = {
2365 {}, // CEFBS_None
2366 };
2367 static constexpr uint8_t RequiredFeaturesRefs[] = {
2368 CEFBS_None, // PHI
2369 CEFBS_None, // INLINEASM
2370 CEFBS_None, // INLINEASM_BR
2371 CEFBS_None, // CFI_INSTRUCTION
2372 CEFBS_None, // EH_LABEL
2373 CEFBS_None, // GC_LABEL
2374 CEFBS_None, // ANNOTATION_LABEL
2375 CEFBS_None, // KILL
2376 CEFBS_None, // EXTRACT_SUBREG
2377 CEFBS_None, // INSERT_SUBREG
2378 CEFBS_None, // IMPLICIT_DEF
2379 CEFBS_None, // INIT_UNDEF
2380 CEFBS_None, // SUBREG_TO_REG
2381 CEFBS_None, // COPY_TO_REGCLASS
2382 CEFBS_None, // DBG_VALUE
2383 CEFBS_None, // DBG_VALUE_LIST
2384 CEFBS_None, // DBG_INSTR_REF
2385 CEFBS_None, // DBG_PHI
2386 CEFBS_None, // DBG_LABEL
2387 CEFBS_None, // REG_SEQUENCE
2388 CEFBS_None, // COPY
2389 CEFBS_None, // COPY_LANEMASK
2390 CEFBS_None, // BUNDLE
2391 CEFBS_None, // LIFETIME_START
2392 CEFBS_None, // LIFETIME_END
2393 CEFBS_None, // PSEUDO_PROBE
2394 CEFBS_None, // ARITH_FENCE
2395 CEFBS_None, // STACKMAP
2396 CEFBS_None, // FENTRY_CALL
2397 CEFBS_None, // PATCHPOINT
2398 CEFBS_None, // LOAD_STACK_GUARD
2399 CEFBS_None, // PREALLOCATED_SETUP
2400 CEFBS_None, // PREALLOCATED_ARG
2401 CEFBS_None, // STATEPOINT
2402 CEFBS_None, // LOCAL_ESCAPE
2403 CEFBS_None, // FAULTING_OP
2404 CEFBS_None, // PATCHABLE_OP
2405 CEFBS_None, // PATCHABLE_FUNCTION_ENTER
2406 CEFBS_None, // PATCHABLE_RET
2407 CEFBS_None, // PATCHABLE_FUNCTION_EXIT
2408 CEFBS_None, // PATCHABLE_TAIL_CALL
2409 CEFBS_None, // PATCHABLE_EVENT_CALL
2410 CEFBS_None, // PATCHABLE_TYPED_EVENT_CALL
2411 CEFBS_None, // ICALL_BRANCH_FUNNEL
2412 CEFBS_None, // FAKE_USE
2413 CEFBS_None, // MEMBARRIER
2414 CEFBS_None, // JUMP_TABLE_DEBUG_INFO
2415 CEFBS_None, // RELOC_NONE
2416 CEFBS_None, // CONVERGENCECTRL_ENTRY
2417 CEFBS_None, // CONVERGENCECTRL_ANCHOR
2418 CEFBS_None, // CONVERGENCECTRL_LOOP
2419 CEFBS_None, // CONVERGENCECTRL_GLUE
2420 CEFBS_None, // G_ASSERT_SEXT
2421 CEFBS_None, // G_ASSERT_ZEXT
2422 CEFBS_None, // G_ASSERT_ALIGN
2423 CEFBS_None, // G_ADD
2424 CEFBS_None, // G_SUB
2425 CEFBS_None, // G_MUL
2426 CEFBS_None, // G_SDIV
2427 CEFBS_None, // G_UDIV
2428 CEFBS_None, // G_SREM
2429 CEFBS_None, // G_UREM
2430 CEFBS_None, // G_SDIVREM
2431 CEFBS_None, // G_UDIVREM
2432 CEFBS_None, // G_AND
2433 CEFBS_None, // G_OR
2434 CEFBS_None, // G_XOR
2435 CEFBS_None, // G_ABDS
2436 CEFBS_None, // G_ABDU
2437 CEFBS_None, // G_UAVGFLOOR
2438 CEFBS_None, // G_UAVGCEIL
2439 CEFBS_None, // G_SAVGFLOOR
2440 CEFBS_None, // G_SAVGCEIL
2441 CEFBS_None, // G_IMPLICIT_DEF
2442 CEFBS_None, // G_PHI
2443 CEFBS_None, // G_FRAME_INDEX
2444 CEFBS_None, // G_GLOBAL_VALUE
2445 CEFBS_None, // G_PTRAUTH_GLOBAL_VALUE
2446 CEFBS_None, // G_CONSTANT_POOL
2447 CEFBS_None, // G_EXTRACT
2448 CEFBS_None, // G_UNMERGE_VALUES
2449 CEFBS_None, // G_INSERT
2450 CEFBS_None, // G_MERGE_VALUES
2451 CEFBS_None, // G_BUILD_VECTOR
2452 CEFBS_None, // G_BUILD_VECTOR_TRUNC
2453 CEFBS_None, // G_CONCAT_VECTORS
2454 CEFBS_None, // G_PTRTOINT
2455 CEFBS_None, // G_INTTOPTR
2456 CEFBS_None, // G_BITCAST
2457 CEFBS_None, // G_FREEZE
2458 CEFBS_None, // G_CONSTANT_FOLD_BARRIER
2459 CEFBS_None, // G_INTRINSIC_FPTRUNC_ROUND
2460 CEFBS_None, // G_INTRINSIC_TRUNC
2461 CEFBS_None, // G_INTRINSIC_ROUND
2462 CEFBS_None, // G_INTRINSIC_LRINT
2463 CEFBS_None, // G_INTRINSIC_LLRINT
2464 CEFBS_None, // G_INTRINSIC_ROUNDEVEN
2465 CEFBS_None, // G_READCYCLECOUNTER
2466 CEFBS_None, // G_READSTEADYCOUNTER
2467 CEFBS_None, // G_LOAD
2468 CEFBS_None, // G_SEXTLOAD
2469 CEFBS_None, // G_ZEXTLOAD
2470 CEFBS_None, // G_FPEXTLOAD
2471 CEFBS_None, // G_INDEXED_LOAD
2472 CEFBS_None, // G_INDEXED_SEXTLOAD
2473 CEFBS_None, // G_INDEXED_ZEXTLOAD
2474 CEFBS_None, // G_STORE
2475 CEFBS_None, // G_FPTRUNCSTORE
2476 CEFBS_None, // G_INDEXED_STORE
2477 CEFBS_None, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
2478 CEFBS_None, // G_ATOMIC_CMPXCHG
2479 CEFBS_None, // G_ATOMICRMW_XCHG
2480 CEFBS_None, // G_ATOMICRMW_ADD
2481 CEFBS_None, // G_ATOMICRMW_SUB
2482 CEFBS_None, // G_ATOMICRMW_AND
2483 CEFBS_None, // G_ATOMICRMW_NAND
2484 CEFBS_None, // G_ATOMICRMW_OR
2485 CEFBS_None, // G_ATOMICRMW_XOR
2486 CEFBS_None, // G_ATOMICRMW_MAX
2487 CEFBS_None, // G_ATOMICRMW_MIN
2488 CEFBS_None, // G_ATOMICRMW_UMAX
2489 CEFBS_None, // G_ATOMICRMW_UMIN
2490 CEFBS_None, // G_ATOMICRMW_FADD
2491 CEFBS_None, // G_ATOMICRMW_FSUB
2492 CEFBS_None, // G_ATOMICRMW_FMAX
2493 CEFBS_None, // G_ATOMICRMW_FMIN
2494 CEFBS_None, // G_ATOMICRMW_FMAXIMUM
2495 CEFBS_None, // G_ATOMICRMW_FMINIMUM
2496 CEFBS_None, // G_ATOMICRMW_FMAXIMUMNUM
2497 CEFBS_None, // G_ATOMICRMW_FMINIMUMNUM
2498 CEFBS_None, // G_ATOMICRMW_UINC_WRAP
2499 CEFBS_None, // G_ATOMICRMW_UDEC_WRAP
2500 CEFBS_None, // G_ATOMICRMW_USUB_COND
2501 CEFBS_None, // G_ATOMICRMW_USUB_SAT
2502 CEFBS_None, // G_FENCE
2503 CEFBS_None, // G_PREFETCH
2504 CEFBS_None, // G_BRCOND
2505 CEFBS_None, // G_BRINDIRECT
2506 CEFBS_None, // G_INVOKE_REGION_START
2507 CEFBS_None, // G_INTRINSIC
2508 CEFBS_None, // G_INTRINSIC_W_SIDE_EFFECTS
2509 CEFBS_None, // G_INTRINSIC_CONVERGENT
2510 CEFBS_None, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
2511 CEFBS_None, // G_ANYEXT
2512 CEFBS_None, // G_TRUNC
2513 CEFBS_None, // G_TRUNC_SSAT_S
2514 CEFBS_None, // G_TRUNC_SSAT_U
2515 CEFBS_None, // G_TRUNC_USAT_U
2516 CEFBS_None, // G_CONSTANT
2517 CEFBS_None, // G_FCONSTANT
2518 CEFBS_None, // G_VASTART
2519 CEFBS_None, // G_VAARG
2520 CEFBS_None, // G_SEXT
2521 CEFBS_None, // G_SEXT_INREG
2522 CEFBS_None, // G_ZEXT
2523 CEFBS_None, // G_SHL
2524 CEFBS_None, // G_LSHR
2525 CEFBS_None, // G_ASHR
2526 CEFBS_None, // G_FSHL
2527 CEFBS_None, // G_FSHR
2528 CEFBS_None, // G_ROTR
2529 CEFBS_None, // G_ROTL
2530 CEFBS_None, // G_ICMP
2531 CEFBS_None, // G_FCMP
2532 CEFBS_None, // G_SCMP
2533 CEFBS_None, // G_UCMP
2534 CEFBS_None, // G_SELECT
2535 CEFBS_None, // G_UADDO
2536 CEFBS_None, // G_UADDE
2537 CEFBS_None, // G_USUBO
2538 CEFBS_None, // G_USUBE
2539 CEFBS_None, // G_SADDO
2540 CEFBS_None, // G_SADDE
2541 CEFBS_None, // G_SSUBO
2542 CEFBS_None, // G_SSUBE
2543 CEFBS_None, // G_UMULO
2544 CEFBS_None, // G_SMULO
2545 CEFBS_None, // G_UMULH
2546 CEFBS_None, // G_SMULH
2547 CEFBS_None, // G_UADDSAT
2548 CEFBS_None, // G_SADDSAT
2549 CEFBS_None, // G_USUBSAT
2550 CEFBS_None, // G_SSUBSAT
2551 CEFBS_None, // G_USHLSAT
2552 CEFBS_None, // G_SSHLSAT
2553 CEFBS_None, // G_SMULFIX
2554 CEFBS_None, // G_UMULFIX
2555 CEFBS_None, // G_SMULFIXSAT
2556 CEFBS_None, // G_UMULFIXSAT
2557 CEFBS_None, // G_SDIVFIX
2558 CEFBS_None, // G_UDIVFIX
2559 CEFBS_None, // G_SDIVFIXSAT
2560 CEFBS_None, // G_UDIVFIXSAT
2561 CEFBS_None, // G_FADD
2562 CEFBS_None, // G_FSUB
2563 CEFBS_None, // G_FMUL
2564 CEFBS_None, // G_FMA
2565 CEFBS_None, // G_FMAD
2566 CEFBS_None, // G_FDIV
2567 CEFBS_None, // G_FREM
2568 CEFBS_None, // G_FMODF
2569 CEFBS_None, // G_FPOW
2570 CEFBS_None, // G_FPOWI
2571 CEFBS_None, // G_FEXP
2572 CEFBS_None, // G_FEXP2
2573 CEFBS_None, // G_FEXP10
2574 CEFBS_None, // G_FLOG
2575 CEFBS_None, // G_FLOG2
2576 CEFBS_None, // G_FLOG10
2577 CEFBS_None, // G_FLDEXP
2578 CEFBS_None, // G_FFREXP
2579 CEFBS_None, // G_FNEG
2580 CEFBS_None, // G_FPEXT
2581 CEFBS_None, // G_FPTRUNC
2582 CEFBS_None, // G_FPTOSI
2583 CEFBS_None, // G_FPTOUI
2584 CEFBS_None, // G_SITOFP
2585 CEFBS_None, // G_UITOFP
2586 CEFBS_None, // G_FPTOSI_SAT
2587 CEFBS_None, // G_FPTOUI_SAT
2588 CEFBS_None, // G_FABS
2589 CEFBS_None, // G_FCOPYSIGN
2590 CEFBS_None, // G_IS_FPCLASS
2591 CEFBS_None, // G_FCANONICALIZE
2592 CEFBS_None, // G_FMINNUM
2593 CEFBS_None, // G_FMAXNUM
2594 CEFBS_None, // G_FMINNUM_IEEE
2595 CEFBS_None, // G_FMAXNUM_IEEE
2596 CEFBS_None, // G_FMINIMUM
2597 CEFBS_None, // G_FMAXIMUM
2598 CEFBS_None, // G_FMINIMUMNUM
2599 CEFBS_None, // G_FMAXIMUMNUM
2600 CEFBS_None, // G_GET_FPENV
2601 CEFBS_None, // G_SET_FPENV
2602 CEFBS_None, // G_RESET_FPENV
2603 CEFBS_None, // G_GET_FPMODE
2604 CEFBS_None, // G_SET_FPMODE
2605 CEFBS_None, // G_RESET_FPMODE
2606 CEFBS_None, // G_GET_ROUNDING
2607 CEFBS_None, // G_SET_ROUNDING
2608 CEFBS_None, // G_PTR_ADD
2609 CEFBS_None, // G_PTRMASK
2610 CEFBS_None, // G_SMIN
2611 CEFBS_None, // G_SMAX
2612 CEFBS_None, // G_UMIN
2613 CEFBS_None, // G_UMAX
2614 CEFBS_None, // G_ABS
2615 CEFBS_None, // G_LROUND
2616 CEFBS_None, // G_LLROUND
2617 CEFBS_None, // G_BR
2618 CEFBS_None, // G_BRJT
2619 CEFBS_None, // G_VSCALE
2620 CEFBS_None, // G_INSERT_SUBVECTOR
2621 CEFBS_None, // G_EXTRACT_SUBVECTOR
2622 CEFBS_None, // G_INSERT_VECTOR_ELT
2623 CEFBS_None, // G_EXTRACT_VECTOR_ELT
2624 CEFBS_None, // G_SHUFFLE_VECTOR
2625 CEFBS_None, // G_SPLAT_VECTOR
2626 CEFBS_None, // G_STEP_VECTOR
2627 CEFBS_None, // G_VECTOR_COMPRESS
2628 CEFBS_None, // G_CTTZ
2629 CEFBS_None, // G_CTTZ_ZERO_POISON
2630 CEFBS_None, // G_CTLZ
2631 CEFBS_None, // G_CTLZ_ZERO_POISON
2632 CEFBS_None, // G_CTLS
2633 CEFBS_None, // G_CTPOP
2634 CEFBS_None, // G_BSWAP
2635 CEFBS_None, // G_BITREVERSE
2636 CEFBS_None, // G_CLMUL
2637 CEFBS_None, // G_FCEIL
2638 CEFBS_None, // G_FCOS
2639 CEFBS_None, // G_FSIN
2640 CEFBS_None, // G_FSINCOS
2641 CEFBS_None, // G_FTAN
2642 CEFBS_None, // G_FACOS
2643 CEFBS_None, // G_FASIN
2644 CEFBS_None, // G_FATAN
2645 CEFBS_None, // G_FATAN2
2646 CEFBS_None, // G_FCOSH
2647 CEFBS_None, // G_FSINH
2648 CEFBS_None, // G_FTANH
2649 CEFBS_None, // G_FSQRT
2650 CEFBS_None, // G_FFLOOR
2651 CEFBS_None, // G_FRINT
2652 CEFBS_None, // G_FNEARBYINT
2653 CEFBS_None, // G_ADDRSPACE_CAST
2654 CEFBS_None, // G_BLOCK_ADDR
2655 CEFBS_None, // G_JUMP_TABLE
2656 CEFBS_None, // G_DYN_STACKALLOC
2657 CEFBS_None, // G_STACKSAVE
2658 CEFBS_None, // G_STACKRESTORE
2659 CEFBS_None, // G_STRICT_FADD
2660 CEFBS_None, // G_STRICT_FSUB
2661 CEFBS_None, // G_STRICT_FMUL
2662 CEFBS_None, // G_STRICT_FDIV
2663 CEFBS_None, // G_STRICT_FREM
2664 CEFBS_None, // G_STRICT_FMA
2665 CEFBS_None, // G_STRICT_FSQRT
2666 CEFBS_None, // G_STRICT_FLDEXP
2667 CEFBS_None, // G_STRICT_FCMP
2668 CEFBS_None, // G_STRICT_FCMPS
2669 CEFBS_None, // G_READ_REGISTER
2670 CEFBS_None, // G_WRITE_REGISTER
2671 CEFBS_None, // G_MEMCPY
2672 CEFBS_None, // G_MEMCPY_INLINE
2673 CEFBS_None, // G_MEMMOVE
2674 CEFBS_None, // G_MEMSET
2675 CEFBS_None, // G_BZERO
2676 CEFBS_None, // G_MEMSET_INLINE
2677 CEFBS_None, // G_TRAP
2678 CEFBS_None, // G_DEBUGTRAP
2679 CEFBS_None, // G_UBSANTRAP
2680 CEFBS_None, // G_VECREDUCE_SEQ_FADD
2681 CEFBS_None, // G_VECREDUCE_SEQ_FMUL
2682 CEFBS_None, // G_VECREDUCE_FADD
2683 CEFBS_None, // G_VECREDUCE_FMUL
2684 CEFBS_None, // G_VECREDUCE_FMAX
2685 CEFBS_None, // G_VECREDUCE_FMIN
2686 CEFBS_None, // G_VECREDUCE_FMAXIMUM
2687 CEFBS_None, // G_VECREDUCE_FMINIMUM
2688 CEFBS_None, // G_VECREDUCE_ADD
2689 CEFBS_None, // G_VECREDUCE_MUL
2690 CEFBS_None, // G_VECREDUCE_AND
2691 CEFBS_None, // G_VECREDUCE_OR
2692 CEFBS_None, // G_VECREDUCE_XOR
2693 CEFBS_None, // G_VECREDUCE_SMAX
2694 CEFBS_None, // G_VECREDUCE_SMIN
2695 CEFBS_None, // G_VECREDUCE_UMAX
2696 CEFBS_None, // G_VECREDUCE_UMIN
2697 CEFBS_None, // G_SBFX
2698 CEFBS_None, // G_UBFX
2699 CEFBS_None, // ADD16mc
2700 CEFBS_None, // ADD16mi
2701 CEFBS_None, // ADD16mm
2702 CEFBS_None, // ADD16mn
2703 CEFBS_None, // ADD16mp
2704 CEFBS_None, // ADD16mr
2705 CEFBS_None, // ADD16rc
2706 CEFBS_None, // ADD16ri
2707 CEFBS_None, // ADD16rm
2708 CEFBS_None, // ADD16rn
2709 CEFBS_None, // ADD16rp
2710 CEFBS_None, // ADD16rr
2711 CEFBS_None, // ADD8mc
2712 CEFBS_None, // ADD8mi
2713 CEFBS_None, // ADD8mm
2714 CEFBS_None, // ADD8mn
2715 CEFBS_None, // ADD8mp
2716 CEFBS_None, // ADD8mr
2717 CEFBS_None, // ADD8rc
2718 CEFBS_None, // ADD8ri
2719 CEFBS_None, // ADD8rm
2720 CEFBS_None, // ADD8rn
2721 CEFBS_None, // ADD8rp
2722 CEFBS_None, // ADD8rr
2723 CEFBS_None, // ADDC16mc
2724 CEFBS_None, // ADDC16mi
2725 CEFBS_None, // ADDC16mm
2726 CEFBS_None, // ADDC16mn
2727 CEFBS_None, // ADDC16mp
2728 CEFBS_None, // ADDC16mr
2729 CEFBS_None, // ADDC16rc
2730 CEFBS_None, // ADDC16ri
2731 CEFBS_None, // ADDC16rm
2732 CEFBS_None, // ADDC16rn
2733 CEFBS_None, // ADDC16rp
2734 CEFBS_None, // ADDC16rr
2735 CEFBS_None, // ADDC8mc
2736 CEFBS_None, // ADDC8mi
2737 CEFBS_None, // ADDC8mm
2738 CEFBS_None, // ADDC8mn
2739 CEFBS_None, // ADDC8mp
2740 CEFBS_None, // ADDC8mr
2741 CEFBS_None, // ADDC8rc
2742 CEFBS_None, // ADDC8ri
2743 CEFBS_None, // ADDC8rm
2744 CEFBS_None, // ADDC8rn
2745 CEFBS_None, // ADDC8rp
2746 CEFBS_None, // ADDC8rr
2747 CEFBS_None, // ADDframe
2748 CEFBS_None, // ADJCALLSTACKDOWN
2749 CEFBS_None, // ADJCALLSTACKUP
2750 CEFBS_None, // AND16mc
2751 CEFBS_None, // AND16mi
2752 CEFBS_None, // AND16mm
2753 CEFBS_None, // AND16mn
2754 CEFBS_None, // AND16mp
2755 CEFBS_None, // AND16mr
2756 CEFBS_None, // AND16rc
2757 CEFBS_None, // AND16ri
2758 CEFBS_None, // AND16rm
2759 CEFBS_None, // AND16rn
2760 CEFBS_None, // AND16rp
2761 CEFBS_None, // AND16rr
2762 CEFBS_None, // AND8mc
2763 CEFBS_None, // AND8mi
2764 CEFBS_None, // AND8mm
2765 CEFBS_None, // AND8mn
2766 CEFBS_None, // AND8mp
2767 CEFBS_None, // AND8mr
2768 CEFBS_None, // AND8rc
2769 CEFBS_None, // AND8ri
2770 CEFBS_None, // AND8rm
2771 CEFBS_None, // AND8rn
2772 CEFBS_None, // AND8rp
2773 CEFBS_None, // AND8rr
2774 CEFBS_None, // BIC16mc
2775 CEFBS_None, // BIC16mi
2776 CEFBS_None, // BIC16mm
2777 CEFBS_None, // BIC16mn
2778 CEFBS_None, // BIC16mp
2779 CEFBS_None, // BIC16mr
2780 CEFBS_None, // BIC16rc
2781 CEFBS_None, // BIC16ri
2782 CEFBS_None, // BIC16rm
2783 CEFBS_None, // BIC16rn
2784 CEFBS_None, // BIC16rp
2785 CEFBS_None, // BIC16rr
2786 CEFBS_None, // BIC8mc
2787 CEFBS_None, // BIC8mi
2788 CEFBS_None, // BIC8mm
2789 CEFBS_None, // BIC8mn
2790 CEFBS_None, // BIC8mp
2791 CEFBS_None, // BIC8mr
2792 CEFBS_None, // BIC8rc
2793 CEFBS_None, // BIC8ri
2794 CEFBS_None, // BIC8rm
2795 CEFBS_None, // BIC8rn
2796 CEFBS_None, // BIC8rp
2797 CEFBS_None, // BIC8rr
2798 CEFBS_None, // BIS16mc
2799 CEFBS_None, // BIS16mi
2800 CEFBS_None, // BIS16mm
2801 CEFBS_None, // BIS16mn
2802 CEFBS_None, // BIS16mp
2803 CEFBS_None, // BIS16mr
2804 CEFBS_None, // BIS16rc
2805 CEFBS_None, // BIS16ri
2806 CEFBS_None, // BIS16rm
2807 CEFBS_None, // BIS16rn
2808 CEFBS_None, // BIS16rp
2809 CEFBS_None, // BIS16rr
2810 CEFBS_None, // BIS8mc
2811 CEFBS_None, // BIS8mi
2812 CEFBS_None, // BIS8mm
2813 CEFBS_None, // BIS8mn
2814 CEFBS_None, // BIS8mp
2815 CEFBS_None, // BIS8mr
2816 CEFBS_None, // BIS8rc
2817 CEFBS_None, // BIS8ri
2818 CEFBS_None, // BIS8rm
2819 CEFBS_None, // BIS8rn
2820 CEFBS_None, // BIS8rp
2821 CEFBS_None, // BIS8rr
2822 CEFBS_None, // BIT16mc
2823 CEFBS_None, // BIT16mi
2824 CEFBS_None, // BIT16mm
2825 CEFBS_None, // BIT16mn
2826 CEFBS_None, // BIT16mp
2827 CEFBS_None, // BIT16mr
2828 CEFBS_None, // BIT16rc
2829 CEFBS_None, // BIT16ri
2830 CEFBS_None, // BIT16rm
2831 CEFBS_None, // BIT16rn
2832 CEFBS_None, // BIT16rp
2833 CEFBS_None, // BIT16rr
2834 CEFBS_None, // BIT8mc
2835 CEFBS_None, // BIT8mi
2836 CEFBS_None, // BIT8mm
2837 CEFBS_None, // BIT8mn
2838 CEFBS_None, // BIT8mp
2839 CEFBS_None, // BIT8mr
2840 CEFBS_None, // BIT8rc
2841 CEFBS_None, // BIT8ri
2842 CEFBS_None, // BIT8rm
2843 CEFBS_None, // BIT8rn
2844 CEFBS_None, // BIT8rp
2845 CEFBS_None, // BIT8rr
2846 CEFBS_None, // Bi
2847 CEFBS_None, // Bm
2848 CEFBS_None, // Br
2849 CEFBS_None, // CALLi
2850 CEFBS_None, // CALLm
2851 CEFBS_None, // CALLn
2852 CEFBS_None, // CALLp
2853 CEFBS_None, // CALLr
2854 CEFBS_None, // CMP16mc
2855 CEFBS_None, // CMP16mi
2856 CEFBS_None, // CMP16mm
2857 CEFBS_None, // CMP16mn
2858 CEFBS_None, // CMP16mp
2859 CEFBS_None, // CMP16mr
2860 CEFBS_None, // CMP16rc
2861 CEFBS_None, // CMP16ri
2862 CEFBS_None, // CMP16rm
2863 CEFBS_None, // CMP16rn
2864 CEFBS_None, // CMP16rp
2865 CEFBS_None, // CMP16rr
2866 CEFBS_None, // CMP8mc
2867 CEFBS_None, // CMP8mi
2868 CEFBS_None, // CMP8mm
2869 CEFBS_None, // CMP8mn
2870 CEFBS_None, // CMP8mp
2871 CEFBS_None, // CMP8mr
2872 CEFBS_None, // CMP8rc
2873 CEFBS_None, // CMP8ri
2874 CEFBS_None, // CMP8rm
2875 CEFBS_None, // CMP8rn
2876 CEFBS_None, // CMP8rp
2877 CEFBS_None, // CMP8rr
2878 CEFBS_None, // DADD16mc
2879 CEFBS_None, // DADD16mi
2880 CEFBS_None, // DADD16mm
2881 CEFBS_None, // DADD16mn
2882 CEFBS_None, // DADD16mp
2883 CEFBS_None, // DADD16mr
2884 CEFBS_None, // DADD16rc
2885 CEFBS_None, // DADD16ri
2886 CEFBS_None, // DADD16rm
2887 CEFBS_None, // DADD16rn
2888 CEFBS_None, // DADD16rp
2889 CEFBS_None, // DADD16rr
2890 CEFBS_None, // DADD8mc
2891 CEFBS_None, // DADD8mi
2892 CEFBS_None, // DADD8mm
2893 CEFBS_None, // DADD8mn
2894 CEFBS_None, // DADD8mp
2895 CEFBS_None, // DADD8mr
2896 CEFBS_None, // DADD8rc
2897 CEFBS_None, // DADD8ri
2898 CEFBS_None, // DADD8rm
2899 CEFBS_None, // DADD8rn
2900 CEFBS_None, // DADD8rp
2901 CEFBS_None, // DADD8rr
2902 CEFBS_None, // JCC
2903 CEFBS_None, // JMP
2904 CEFBS_None, // MOV16mc
2905 CEFBS_None, // MOV16mi
2906 CEFBS_None, // MOV16mm
2907 CEFBS_None, // MOV16mn
2908 CEFBS_None, // MOV16mr
2909 CEFBS_None, // MOV16rc
2910 CEFBS_None, // MOV16ri
2911 CEFBS_None, // MOV16rm
2912 CEFBS_None, // MOV16rn
2913 CEFBS_None, // MOV16rp
2914 CEFBS_None, // MOV16rr
2915 CEFBS_None, // MOV8mc
2916 CEFBS_None, // MOV8mi
2917 CEFBS_None, // MOV8mm
2918 CEFBS_None, // MOV8mn
2919 CEFBS_None, // MOV8mr
2920 CEFBS_None, // MOV8rc
2921 CEFBS_None, // MOV8ri
2922 CEFBS_None, // MOV8rm
2923 CEFBS_None, // MOV8rn
2924 CEFBS_None, // MOV8rp
2925 CEFBS_None, // MOV8rr
2926 CEFBS_None, // MOVZX16rm8
2927 CEFBS_None, // MOVZX16rr8
2928 CEFBS_None, // POP16r
2929 CEFBS_None, // PUSH16c
2930 CEFBS_None, // PUSH16i
2931 CEFBS_None, // PUSH16r
2932 CEFBS_None, // PUSH8r
2933 CEFBS_None, // RET
2934 CEFBS_None, // RETI
2935 CEFBS_None, // RRA16m
2936 CEFBS_None, // RRA16n
2937 CEFBS_None, // RRA16p
2938 CEFBS_None, // RRA16r
2939 CEFBS_None, // RRA8m
2940 CEFBS_None, // RRA8n
2941 CEFBS_None, // RRA8p
2942 CEFBS_None, // RRA8r
2943 CEFBS_None, // RRC16m
2944 CEFBS_None, // RRC16n
2945 CEFBS_None, // RRC16p
2946 CEFBS_None, // RRC16r
2947 CEFBS_None, // RRC8m
2948 CEFBS_None, // RRC8n
2949 CEFBS_None, // RRC8p
2950 CEFBS_None, // RRC8r
2951 CEFBS_None, // Rrcl16
2952 CEFBS_None, // Rrcl8
2953 CEFBS_None, // SEXT16m
2954 CEFBS_None, // SEXT16n
2955 CEFBS_None, // SEXT16p
2956 CEFBS_None, // SEXT16r
2957 CEFBS_None, // SUB16mc
2958 CEFBS_None, // SUB16mi
2959 CEFBS_None, // SUB16mm
2960 CEFBS_None, // SUB16mn
2961 CEFBS_None, // SUB16mp
2962 CEFBS_None, // SUB16mr
2963 CEFBS_None, // SUB16rc
2964 CEFBS_None, // SUB16ri
2965 CEFBS_None, // SUB16rm
2966 CEFBS_None, // SUB16rn
2967 CEFBS_None, // SUB16rp
2968 CEFBS_None, // SUB16rr
2969 CEFBS_None, // SUB8mc
2970 CEFBS_None, // SUB8mi
2971 CEFBS_None, // SUB8mm
2972 CEFBS_None, // SUB8mn
2973 CEFBS_None, // SUB8mp
2974 CEFBS_None, // SUB8mr
2975 CEFBS_None, // SUB8rc
2976 CEFBS_None, // SUB8ri
2977 CEFBS_None, // SUB8rm
2978 CEFBS_None, // SUB8rn
2979 CEFBS_None, // SUB8rp
2980 CEFBS_None, // SUB8rr
2981 CEFBS_None, // SUBC16mc
2982 CEFBS_None, // SUBC16mi
2983 CEFBS_None, // SUBC16mm
2984 CEFBS_None, // SUBC16mn
2985 CEFBS_None, // SUBC16mp
2986 CEFBS_None, // SUBC16mr
2987 CEFBS_None, // SUBC16rc
2988 CEFBS_None, // SUBC16ri
2989 CEFBS_None, // SUBC16rm
2990 CEFBS_None, // SUBC16rn
2991 CEFBS_None, // SUBC16rp
2992 CEFBS_None, // SUBC16rr
2993 CEFBS_None, // SUBC8mc
2994 CEFBS_None, // SUBC8mi
2995 CEFBS_None, // SUBC8mm
2996 CEFBS_None, // SUBC8mn
2997 CEFBS_None, // SUBC8mp
2998 CEFBS_None, // SUBC8mr
2999 CEFBS_None, // SUBC8rc
3000 CEFBS_None, // SUBC8ri
3001 CEFBS_None, // SUBC8rm
3002 CEFBS_None, // SUBC8rn
3003 CEFBS_None, // SUBC8rp
3004 CEFBS_None, // SUBC8rr
3005 CEFBS_None, // SWPB16m
3006 CEFBS_None, // SWPB16n
3007 CEFBS_None, // SWPB16p
3008 CEFBS_None, // SWPB16r
3009 CEFBS_None, // Select16
3010 CEFBS_None, // Select8
3011 CEFBS_None, // Shl16
3012 CEFBS_None, // Shl8
3013 CEFBS_None, // Sra16
3014 CEFBS_None, // Sra8
3015 CEFBS_None, // Srl16
3016 CEFBS_None, // Srl8
3017 CEFBS_None, // XOR16mc
3018 CEFBS_None, // XOR16mi
3019 CEFBS_None, // XOR16mm
3020 CEFBS_None, // XOR16mn
3021 CEFBS_None, // XOR16mp
3022 CEFBS_None, // XOR16mr
3023 CEFBS_None, // XOR16rc
3024 CEFBS_None, // XOR16ri
3025 CEFBS_None, // XOR16rm
3026 CEFBS_None, // XOR16rn
3027 CEFBS_None, // XOR16rp
3028 CEFBS_None, // XOR16rr
3029 CEFBS_None, // XOR8mc
3030 CEFBS_None, // XOR8mi
3031 CEFBS_None, // XOR8mm
3032 CEFBS_None, // XOR8mn
3033 CEFBS_None, // XOR8mp
3034 CEFBS_None, // XOR8mr
3035 CEFBS_None, // XOR8rc
3036 CEFBS_None, // XOR8ri
3037 CEFBS_None, // XOR8rm
3038 CEFBS_None, // XOR8rn
3039 CEFBS_None, // XOR8rp
3040 CEFBS_None, // XOR8rr
3041 CEFBS_None, // ZEXT16r
3042 };
3043
3044 assert(Opcode < 674);
3045 return FeatureBitsets[RequiredFeaturesRefs[Opcode]];
3046}
3047
3048
3049} // namespace llvm::MSP430_MC
3050
3051#endif // GET_COMPUTE_FEATURES
3052
3053#ifdef GET_AVAILABLE_OPCODE_CHECKER
3054#undef GET_AVAILABLE_OPCODE_CHECKER
3055
3056namespace llvm::MSP430_MC {
3057
3058bool isOpcodeAvailable(unsigned Opcode, const FeatureBitset &Features) {
3059 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
3060 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
3061 FeatureBitset MissingFeatures =
3062 (AvailableFeatures & RequiredFeatures) ^
3063 RequiredFeatures;
3064 return !MissingFeatures.any();
3065}
3066
3067} // namespace llvm::MSP430_MC
3068
3069#endif // GET_AVAILABLE_OPCODE_CHECKER
3070
3071#ifdef ENABLE_INSTR_PREDICATE_VERIFIER
3072#undef ENABLE_INSTR_PREDICATE_VERIFIER
3073
3074#include <sstream>
3075
3076namespace llvm::MSP430_MC {
3077
3078#ifndef NDEBUG
3079static const char *SubtargetFeatureNames[] = {
3080 nullptr
3081};
3082
3083#endif // NDEBUG
3084
3085void verifyInstructionPredicates(
3086 unsigned Opcode, const FeatureBitset &Features) {
3087#ifndef NDEBUG
3088 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
3089 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
3090 FeatureBitset MissingFeatures =
3091 (AvailableFeatures & RequiredFeatures) ^
3092 RequiredFeatures;
3093 if (MissingFeatures.any()) {
3094 std::ostringstream Msg;
3095 Msg << "Attempting to emit " << &MSP430InstrNameData[MSP430InstrNameIndices[Opcode]]
3096 << " instruction but the ";
3097 for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i)
3098 if (MissingFeatures.test(i))
3099 Msg << SubtargetFeatureNames[i] << " ";
3100 Msg << "predicate(s) are not met";
3101 report_fatal_error(Msg.str().c_str());
3102 }
3103#endif // NDEBUG
3104}
3105
3106} // namespace llvm::MSP430_MC
3107
3108#endif // ENABLE_INSTR_PREDICATE_VERIFIER
3109
3110