1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Instruction Enum Values and Descriptors *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_INSTRINFO_ENUM
10#undef GET_INSTRINFO_ENUM
11
12namespace llvm::MSP430 {
13
14 enum {
15 PHI = 0, // Target.td:1301
16 INLINEASM = 1, // Target.td:1307
17 INLINEASM_BR = 2, // Target.td:1313
18 CFI_INSTRUCTION = 3, // Target.td:1322
19 EH_LABEL = 4, // Target.td:1331
20 GC_LABEL = 5, // Target.td:1340
21 ANNOTATION_LABEL = 6, // Target.td:1349
22 KILL = 7, // Target.td:1357
23 EXTRACT_SUBREG = 8, // Target.td:1364
24 INSERT_SUBREG = 9, // Target.td:1370
25 IMPLICIT_DEF = 10, // Target.td:1377
26 INIT_UNDEF = 11, // Target.td:1386
27 SUBREG_TO_REG = 12, // Target.td:1393
28 COPY_TO_REGCLASS = 13, // Target.td:1399
29 DBG_VALUE = 14, // Target.td:1406
30 DBG_VALUE_LIST = 15, // Target.td:1413
31 DBG_INSTR_REF = 16, // Target.td:1420
32 DBG_PHI = 17, // Target.td:1427
33 DBG_LABEL = 18, // Target.td:1434
34 REG_SEQUENCE = 19, // Target.td:1441
35 COPY = 20, // Target.td:1448
36 COPY_LANEMASK = 21, // Target.td:1456
37 BUNDLE = 22, // Target.td:1463
38 LIFETIME_START = 23, // Target.td:1469
39 LIFETIME_END = 24, // Target.td:1476
40 PSEUDO_PROBE = 25, // Target.td:1483
41 ARITH_FENCE = 26, // Target.td:1490
42 STACKMAP = 27, // Target.td:1499
43 FENTRY_CALL = 28, // Target.td:1634
44 PATCHPOINT = 29, // Target.td:1507
45 LOAD_STACK_GUARD = 30, // Target.td:1525
46 PREALLOCATED_SETUP = 31, // Target.td:1533
47 PREALLOCATED_ARG = 32, // Target.td:1539
48 STATEPOINT = 33, // Target.td:1516
49 LOCAL_ESCAPE = 34, // Target.td:1545
50 FAULTING_OP = 35, // Target.td:1554
51 PATCHABLE_OP = 36, // Target.td:1574
52 PATCHABLE_FUNCTION_ENTER = 37, // Target.td:1582
53 PATCHABLE_RET = 38, // Target.td:1589
54 PATCHABLE_FUNCTION_EXIT = 39, // Target.td:1598
55 PATCHABLE_TAIL_CALL = 40, // Target.td:1606
56 PATCHABLE_EVENT_CALL = 41, // Target.td:1614
57 PATCHABLE_TYPED_EVENT_CALL = 42, // Target.td:1624
58 ICALL_BRANCH_FUNNEL = 43, // Target.td:1644
59 FAKE_USE = 44, // Target.td:1564
60 MEMBARRIER = 45, // Target.td:1650
61 JUMP_TABLE_DEBUG_INFO = 46, // Target.td:1658
62 RELOC_NONE = 47, // Target.td:1666
63 CONVERGENCECTRL_ENTRY = 48, // Target.td:1678
64 CONVERGENCECTRL_ANCHOR = 49, // Target.td:1674
65 CONVERGENCECTRL_LOOP = 50, // Target.td:1682
66 CONVERGENCECTRL_GLUE = 51, // Target.td:1686
67 G_ASSERT_SEXT = 52, // GenericOpcodes.td:1867
68 G_ASSERT_ZEXT = 53, // GenericOpcodes.td:1859
69 G_ASSERT_ALIGN = 54, // GenericOpcodes.td:1874
70 G_ADD = 55, // GenericOpcodes.td:300
71 G_SUB = 56, // GenericOpcodes.td:308
72 G_MUL = 57, // GenericOpcodes.td:316
73 G_SDIV = 58, // GenericOpcodes.td:324
74 G_UDIV = 59, // GenericOpcodes.td:332
75 G_SREM = 60, // GenericOpcodes.td:340
76 G_UREM = 61, // GenericOpcodes.td:348
77 G_SDIVREM = 62, // GenericOpcodes.td:356
78 G_UDIVREM = 63, // GenericOpcodes.td:364
79 G_AND = 64, // GenericOpcodes.td:372
80 G_OR = 65, // GenericOpcodes.td:380
81 G_XOR = 66, // GenericOpcodes.td:388
82 G_ABDS = 67, // GenericOpcodes.td:417
83 G_ABDU = 68, // GenericOpcodes.td:425
84 G_UAVGFLOOR = 69, // GenericOpcodes.td:433
85 G_UAVGCEIL = 70, // GenericOpcodes.td:440
86 G_SAVGFLOOR = 71, // GenericOpcodes.td:447
87 G_SAVGCEIL = 72, // GenericOpcodes.td:454
88 G_IMPLICIT_DEF = 73, // GenericOpcodes.td:110
89 G_PHI = 74, // GenericOpcodes.td:116
90 G_FRAME_INDEX = 75, // GenericOpcodes.td:122
91 G_GLOBAL_VALUE = 76, // GenericOpcodes.td:128
92 G_PTRAUTH_GLOBAL_VALUE = 77, // GenericOpcodes.td:134
93 G_CONSTANT_POOL = 78, // GenericOpcodes.td:140
94 G_EXTRACT = 79, // GenericOpcodes.td:1474
95 G_UNMERGE_VALUES = 80, // GenericOpcodes.td:1486
96 G_INSERT = 81, // GenericOpcodes.td:1494
97 G_MERGE_VALUES = 82, // GenericOpcodes.td:1504
98 G_BUILD_VECTOR = 83, // GenericOpcodes.td:1523
99 G_BUILD_VECTOR_TRUNC = 84, // GenericOpcodes.td:1532
100 G_CONCAT_VECTORS = 85, // GenericOpcodes.td:1539
101 G_PTRTOINT = 86, // GenericOpcodes.td:152
102 G_INTTOPTR = 87, // GenericOpcodes.td:146
103 G_BITCAST = 88, // GenericOpcodes.td:158
104 G_FREEZE = 89, // GenericOpcodes.td:277
105 G_CONSTANT_FOLD_BARRIER = 90, // GenericOpcodes.td:1881
106 G_INTRINSIC_FPTRUNC_ROUND = 91, // GenericOpcodes.td:1263
107 G_INTRINSIC_TRUNC = 92, // GenericOpcodes.td:1269
108 G_INTRINSIC_ROUND = 93, // GenericOpcodes.td:1275
109 G_INTRINSIC_LRINT = 94, // GenericOpcodes.td:1281
110 G_INTRINSIC_LLRINT = 95, // GenericOpcodes.td:1287
111 G_INTRINSIC_ROUNDEVEN = 96, // GenericOpcodes.td:1293
112 G_READCYCLECOUNTER = 97, // GenericOpcodes.td:1299
113 G_READSTEADYCOUNTER = 98, // GenericOpcodes.td:1305
114 G_LOAD = 99, // GenericOpcodes.td:1332
115 G_SEXTLOAD = 100, // GenericOpcodes.td:1340
116 G_ZEXTLOAD = 101, // GenericOpcodes.td:1348
117 G_INDEXED_LOAD = 102, // GenericOpcodes.td:1358
118 G_INDEXED_SEXTLOAD = 103, // GenericOpcodes.td:1366
119 G_INDEXED_ZEXTLOAD = 104, // GenericOpcodes.td:1374
120 G_STORE = 105, // GenericOpcodes.td:1382
121 G_INDEXED_STORE = 106, // GenericOpcodes.td:1390
122 G_ATOMIC_CMPXCHG_WITH_SUCCESS = 107, // GenericOpcodes.td:1400
123 G_ATOMIC_CMPXCHG = 108, // GenericOpcodes.td:1410
124 G_ATOMICRMW_XCHG = 109, // GenericOpcodes.td:1428
125 G_ATOMICRMW_ADD = 110, // GenericOpcodes.td:1429
126 G_ATOMICRMW_SUB = 111, // GenericOpcodes.td:1430
127 G_ATOMICRMW_AND = 112, // GenericOpcodes.td:1431
128 G_ATOMICRMW_NAND = 113, // GenericOpcodes.td:1432
129 G_ATOMICRMW_OR = 114, // GenericOpcodes.td:1433
130 G_ATOMICRMW_XOR = 115, // GenericOpcodes.td:1434
131 G_ATOMICRMW_MAX = 116, // GenericOpcodes.td:1435
132 G_ATOMICRMW_MIN = 117, // GenericOpcodes.td:1436
133 G_ATOMICRMW_UMAX = 118, // GenericOpcodes.td:1437
134 G_ATOMICRMW_UMIN = 119, // GenericOpcodes.td:1438
135 G_ATOMICRMW_FADD = 120, // GenericOpcodes.td:1439
136 G_ATOMICRMW_FSUB = 121, // GenericOpcodes.td:1440
137 G_ATOMICRMW_FMAX = 122, // GenericOpcodes.td:1441
138 G_ATOMICRMW_FMIN = 123, // GenericOpcodes.td:1442
139 G_ATOMICRMW_FMAXIMUM = 124, // GenericOpcodes.td:1443
140 G_ATOMICRMW_FMINIMUM = 125, // GenericOpcodes.td:1444
141 G_ATOMICRMW_FMAXIMUMNUM = 126, // GenericOpcodes.td:1445
142 G_ATOMICRMW_FMINIMUMNUM = 127, // GenericOpcodes.td:1446
143 G_ATOMICRMW_UINC_WRAP = 128, // GenericOpcodes.td:1447
144 G_ATOMICRMW_UDEC_WRAP = 129, // GenericOpcodes.td:1448
145 G_ATOMICRMW_USUB_COND = 130, // GenericOpcodes.td:1449
146 G_ATOMICRMW_USUB_SAT = 131, // GenericOpcodes.td:1450
147 G_FENCE = 132, // GenericOpcodes.td:1452
148 G_PREFETCH = 133, // GenericOpcodes.td:1459
149 G_BRCOND = 134, // GenericOpcodes.td:1594
150 G_BRINDIRECT = 135, // GenericOpcodes.td:1603
151 G_INVOKE_REGION_START = 136, // GenericOpcodes.td:1626
152 G_INTRINSIC = 137, // GenericOpcodes.td:1546
153 G_INTRINSIC_W_SIDE_EFFECTS = 138, // GenericOpcodes.td:1553
154 G_INTRINSIC_CONVERGENT = 139, // GenericOpcodes.td:1562
155 G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 140, // GenericOpcodes.td:1570
156 G_ANYEXT = 141, // GenericOpcodes.td:44
157 G_TRUNC = 142, // GenericOpcodes.td:83
158 G_TRUNC_SSAT_S = 143, // GenericOpcodes.td:90
159 G_TRUNC_SSAT_U = 144, // GenericOpcodes.td:97
160 G_TRUNC_USAT_U = 145, // GenericOpcodes.td:104
161 G_CONSTANT = 146, // GenericOpcodes.td:165
162 G_FCONSTANT = 147, // GenericOpcodes.td:172
163 G_VASTART = 148, // GenericOpcodes.td:178
164 G_VAARG = 149, // GenericOpcodes.td:185
165 G_SEXT = 150, // GenericOpcodes.td:52
166 G_SEXT_INREG = 151, // GenericOpcodes.td:66
167 G_ZEXT = 152, // GenericOpcodes.td:74
168 G_SHL = 153, // GenericOpcodes.td:396
169 G_LSHR = 154, // GenericOpcodes.td:403
170 G_ASHR = 155, // GenericOpcodes.td:410
171 G_FSHL = 156, // GenericOpcodes.td:462
172 G_FSHR = 157, // GenericOpcodes.td:470
173 G_ROTR = 158, // GenericOpcodes.td:477
174 G_ROTL = 159, // GenericOpcodes.td:484
175 G_ICMP = 160, // GenericOpcodes.td:491
176 G_FCMP = 161, // GenericOpcodes.td:498
177 G_SCMP = 162, // GenericOpcodes.td:505
178 G_UCMP = 163, // GenericOpcodes.td:512
179 G_SELECT = 164, // GenericOpcodes.td:519
180 G_UADDO = 165, // GenericOpcodes.td:584
181 G_UADDE = 166, // GenericOpcodes.td:592
182 G_USUBO = 167, // GenericOpcodes.td:614
183 G_USUBE = 168, // GenericOpcodes.td:620
184 G_SADDO = 169, // GenericOpcodes.td:599
185 G_SADDE = 170, // GenericOpcodes.td:607
186 G_SSUBO = 171, // GenericOpcodes.td:627
187 G_SSUBE = 172, // GenericOpcodes.td:634
188 G_UMULO = 173, // GenericOpcodes.td:641
189 G_SMULO = 174, // GenericOpcodes.td:649
190 G_UMULH = 175, // GenericOpcodes.td:658
191 G_SMULH = 176, // GenericOpcodes.td:667
192 G_UADDSAT = 177, // GenericOpcodes.td:679
193 G_SADDSAT = 178, // GenericOpcodes.td:687
194 G_USUBSAT = 179, // GenericOpcodes.td:695
195 G_SSUBSAT = 180, // GenericOpcodes.td:703
196 G_USHLSAT = 181, // GenericOpcodes.td:711
197 G_SSHLSAT = 182, // GenericOpcodes.td:719
198 G_SMULFIX = 183, // GenericOpcodes.td:731
199 G_UMULFIX = 184, // GenericOpcodes.td:738
200 G_SMULFIXSAT = 185, // GenericOpcodes.td:748
201 G_UMULFIXSAT = 186, // GenericOpcodes.td:755
202 G_SDIVFIX = 187, // GenericOpcodes.td:766
203 G_UDIVFIX = 188, // GenericOpcodes.td:773
204 G_SDIVFIXSAT = 189, // GenericOpcodes.td:783
205 G_UDIVFIXSAT = 190, // GenericOpcodes.td:790
206 G_FADD = 191, // GenericOpcodes.td:963
207 G_FSUB = 192, // GenericOpcodes.td:971
208 G_FMUL = 193, // GenericOpcodes.td:979
209 G_FMA = 194, // GenericOpcodes.td:988
210 G_FMAD = 195, // GenericOpcodes.td:997
211 G_FDIV = 196, // GenericOpcodes.td:1005
212 G_FREM = 197, // GenericOpcodes.td:1012
213 G_FMODF = 198, // GenericOpcodes.td:1019
214 G_FPOW = 199, // GenericOpcodes.td:1026
215 G_FPOWI = 200, // GenericOpcodes.td:1033
216 G_FEXP = 201, // GenericOpcodes.td:1040
217 G_FEXP2 = 202, // GenericOpcodes.td:1047
218 G_FEXP10 = 203, // GenericOpcodes.td:1054
219 G_FLOG = 204, // GenericOpcodes.td:1061
220 G_FLOG2 = 205, // GenericOpcodes.td:1068
221 G_FLOG10 = 206, // GenericOpcodes.td:1075
222 G_FLDEXP = 207, // GenericOpcodes.td:1082
223 G_FFREXP = 208, // GenericOpcodes.td:1089
224 G_FNEG = 209, // GenericOpcodes.td:801
225 G_FPEXT = 210, // GenericOpcodes.td:807
226 G_FPTRUNC = 211, // GenericOpcodes.td:813
227 G_FPTOSI = 212, // GenericOpcodes.td:819
228 G_FPTOUI = 213, // GenericOpcodes.td:825
229 G_SITOFP = 214, // GenericOpcodes.td:831
230 G_UITOFP = 215, // GenericOpcodes.td:837
231 G_FPTOSI_SAT = 216, // GenericOpcodes.td:843
232 G_FPTOUI_SAT = 217, // GenericOpcodes.td:849
233 G_FABS = 218, // GenericOpcodes.td:855
234 G_FCOPYSIGN = 219, // GenericOpcodes.td:861
235 G_IS_FPCLASS = 220, // GenericOpcodes.td:874
236 G_FCANONICALIZE = 221, // GenericOpcodes.td:867
237 G_FMINNUM = 222, // GenericOpcodes.td:887
238 G_FMAXNUM = 223, // GenericOpcodes.td:894
239 G_FMINNUM_IEEE = 224, // GenericOpcodes.td:912
240 G_FMAXNUM_IEEE = 225, // GenericOpcodes.td:919
241 G_FMINIMUM = 226, // GenericOpcodes.td:929
242 G_FMAXIMUM = 227, // GenericOpcodes.td:936
243 G_FMINIMUMNUM = 228, // GenericOpcodes.td:944
244 G_FMAXIMUMNUM = 229, // GenericOpcodes.td:951
245 G_GET_FPENV = 230, // GenericOpcodes.td:1219
246 G_SET_FPENV = 231, // GenericOpcodes.td:1226
247 G_RESET_FPENV = 232, // GenericOpcodes.td:1233
248 G_GET_FPMODE = 233, // GenericOpcodes.td:1240
249 G_SET_FPMODE = 234, // GenericOpcodes.td:1247
250 G_RESET_FPMODE = 235, // GenericOpcodes.td:1254
251 G_GET_ROUNDING = 236, // GenericOpcodes.td:1311
252 G_SET_ROUNDING = 237, // GenericOpcodes.td:1317
253 G_PTR_ADD = 238, // GenericOpcodes.td:526
254 G_PTRMASK = 239, // GenericOpcodes.td:534
255 G_SMIN = 240, // GenericOpcodes.td:541
256 G_SMAX = 241, // GenericOpcodes.td:549
257 G_UMIN = 242, // GenericOpcodes.td:557
258 G_UMAX = 243, // GenericOpcodes.td:565
259 G_ABS = 244, // GenericOpcodes.td:573
260 G_LROUND = 245, // GenericOpcodes.td:283
261 G_LLROUND = 246, // GenericOpcodes.td:289
262 G_BR = 247, // GenericOpcodes.td:1584
263 G_BRJT = 248, // GenericOpcodes.td:1614
264 G_VSCALE = 249, // GenericOpcodes.td:1514
265 G_INSERT_SUBVECTOR = 250, // GenericOpcodes.td:1658
266 G_EXTRACT_SUBVECTOR = 251, // GenericOpcodes.td:1665
267 G_INSERT_VECTOR_ELT = 252, // GenericOpcodes.td:1672
268 G_EXTRACT_VECTOR_ELT = 253, // GenericOpcodes.td:1679
269 G_SHUFFLE_VECTOR = 254, // GenericOpcodes.td:1689
270 G_SPLAT_VECTOR = 255, // GenericOpcodes.td:1696
271 G_STEP_VECTOR = 256, // GenericOpcodes.td:1703
272 G_VECTOR_COMPRESS = 257, // GenericOpcodes.td:1710
273 G_CTTZ = 258, // GenericOpcodes.td:205
274 G_CTTZ_ZERO_UNDEF = 259, // GenericOpcodes.td:211
275 G_CTLZ = 260, // GenericOpcodes.td:193
276 G_CTLZ_ZERO_UNDEF = 261, // GenericOpcodes.td:199
277 G_CTLS = 262, // GenericOpcodes.td:217
278 G_CTPOP = 263, // GenericOpcodes.td:223
279 G_BSWAP = 264, // GenericOpcodes.td:229
280 G_BITREVERSE = 265, // GenericOpcodes.td:235
281 G_FCEIL = 266, // GenericOpcodes.td:1096
282 G_FCOS = 267, // GenericOpcodes.td:1103
283 G_FSIN = 268, // GenericOpcodes.td:1110
284 G_FSINCOS = 269, // GenericOpcodes.td:1117
285 G_FTAN = 270, // GenericOpcodes.td:1124
286 G_FACOS = 271, // GenericOpcodes.td:1131
287 G_FASIN = 272, // GenericOpcodes.td:1138
288 G_FATAN = 273, // GenericOpcodes.td:1145
289 G_FATAN2 = 274, // GenericOpcodes.td:1152
290 G_FCOSH = 275, // GenericOpcodes.td:1159
291 G_FSINH = 276, // GenericOpcodes.td:1166
292 G_FTANH = 277, // GenericOpcodes.td:1173
293 G_FSQRT = 278, // GenericOpcodes.td:1183
294 G_FFLOOR = 279, // GenericOpcodes.td:1190
295 G_FRINT = 280, // GenericOpcodes.td:1197
296 G_FNEARBYINT = 281, // GenericOpcodes.td:1204
297 G_ADDRSPACE_CAST = 282, // GenericOpcodes.td:241
298 G_BLOCK_ADDR = 283, // GenericOpcodes.td:247
299 G_JUMP_TABLE = 284, // GenericOpcodes.td:253
300 G_DYN_STACKALLOC = 285, // GenericOpcodes.td:259
301 G_STACKSAVE = 286, // GenericOpcodes.td:265
302 G_STACKRESTORE = 287, // GenericOpcodes.td:271
303 G_STRICT_FADD = 288, // GenericOpcodes.td:1760
304 G_STRICT_FSUB = 289, // GenericOpcodes.td:1761
305 G_STRICT_FMUL = 290, // GenericOpcodes.td:1762
306 G_STRICT_FDIV = 291, // GenericOpcodes.td:1763
307 G_STRICT_FREM = 292, // GenericOpcodes.td:1764
308 G_STRICT_FMA = 293, // GenericOpcodes.td:1765
309 G_STRICT_FSQRT = 294, // GenericOpcodes.td:1766
310 G_STRICT_FLDEXP = 295, // GenericOpcodes.td:1767
311 G_READ_REGISTER = 296, // GenericOpcodes.td:1633
312 G_WRITE_REGISTER = 297, // GenericOpcodes.td:1643
313 G_MEMCPY = 298, // GenericOpcodes.td:1773
314 G_MEMCPY_INLINE = 299, // GenericOpcodes.td:1781
315 G_MEMMOVE = 300, // GenericOpcodes.td:1789
316 G_MEMSET = 301, // GenericOpcodes.td:1797
317 G_BZERO = 302, // GenericOpcodes.td:1804
318 G_TRAP = 303, // GenericOpcodes.td:1814
319 G_DEBUGTRAP = 304, // GenericOpcodes.td:1821
320 G_UBSANTRAP = 305, // GenericOpcodes.td:1827
321 G_VECREDUCE_SEQ_FADD = 306, // GenericOpcodes.td:1726
322 G_VECREDUCE_SEQ_FMUL = 307, // GenericOpcodes.td:1732
323 G_VECREDUCE_FADD = 308, // GenericOpcodes.td:1738
324 G_VECREDUCE_FMUL = 309, // GenericOpcodes.td:1739
325 G_VECREDUCE_FMAX = 310, // GenericOpcodes.td:1741
326 G_VECREDUCE_FMIN = 311, // GenericOpcodes.td:1742
327 G_VECREDUCE_FMAXIMUM = 312, // GenericOpcodes.td:1743
328 G_VECREDUCE_FMINIMUM = 313, // GenericOpcodes.td:1744
329 G_VECREDUCE_ADD = 314, // GenericOpcodes.td:1746
330 G_VECREDUCE_MUL = 315, // GenericOpcodes.td:1747
331 G_VECREDUCE_AND = 316, // GenericOpcodes.td:1748
332 G_VECREDUCE_OR = 317, // GenericOpcodes.td:1749
333 G_VECREDUCE_XOR = 318, // GenericOpcodes.td:1750
334 G_VECREDUCE_SMAX = 319, // GenericOpcodes.td:1751
335 G_VECREDUCE_SMIN = 320, // GenericOpcodes.td:1752
336 G_VECREDUCE_UMAX = 321, // GenericOpcodes.td:1753
337 G_VECREDUCE_UMIN = 322, // GenericOpcodes.td:1754
338 G_SBFX = 323, // GenericOpcodes.td:1839
339 G_UBFX = 324, // GenericOpcodes.td:1847
340 ADD16mc = 325, // MSP430InstrInfo.td:499
341 ADD16mi = 326, // MSP430InstrInfo.td:505
342 ADD16mm = 327, // MSP430InstrInfo.td:512
343 ADD16mn = 328, // MSP430InstrInfo.td:518
344 ADD16mp = 329, // MSP430InstrInfo.td:522
345 ADD16mr = 330, // MSP430InstrInfo.td:493
346 ADD16rc = 331, // MSP430InstrInfo.td:480
347 ADD16ri = 332, // MSP430InstrInfo.td:486
348 ADD16rm = 333, // MSP430InstrInfo.td:462
349 ADD16rn = 334, // MSP430InstrInfo.td:467
350 ADD16rp = 335, // MSP430InstrInfo.td:474
351 ADD16rr = 336, // MSP430InstrInfo.td:455
352 ADD8mc = 337, // MSP430InstrInfo.td:496
353 ADD8mi = 338, // MSP430InstrInfo.td:502
354 ADD8mm = 339, // MSP430InstrInfo.td:508
355 ADD8mn = 340, // MSP430InstrInfo.td:516
356 ADD8mp = 341, // MSP430InstrInfo.td:520
357 ADD8mr = 342, // MSP430InstrInfo.td:490
358 ADD8rc = 343, // MSP430InstrInfo.td:477
359 ADD8ri = 344, // MSP430InstrInfo.td:483
360 ADD8rm = 345, // MSP430InstrInfo.td:459
361 ADD8rn = 346, // MSP430InstrInfo.td:465
362 ADD8rp = 347, // MSP430InstrInfo.td:472
363 ADD8rr = 348, // MSP430InstrInfo.td:452
364 ADDC16mc = 349, // MSP430InstrInfo.td:499
365 ADDC16mi = 350, // MSP430InstrInfo.td:505
366 ADDC16mm = 351, // MSP430InstrInfo.td:512
367 ADDC16mn = 352, // MSP430InstrInfo.td:518
368 ADDC16mp = 353, // MSP430InstrInfo.td:522
369 ADDC16mr = 354, // MSP430InstrInfo.td:493
370 ADDC16rc = 355, // MSP430InstrInfo.td:480
371 ADDC16ri = 356, // MSP430InstrInfo.td:486
372 ADDC16rm = 357, // MSP430InstrInfo.td:462
373 ADDC16rn = 358, // MSP430InstrInfo.td:467
374 ADDC16rp = 359, // MSP430InstrInfo.td:474
375 ADDC16rr = 360, // MSP430InstrInfo.td:455
376 ADDC8mc = 361, // MSP430InstrInfo.td:496
377 ADDC8mi = 362, // MSP430InstrInfo.td:502
378 ADDC8mm = 363, // MSP430InstrInfo.td:508
379 ADDC8mn = 364, // MSP430InstrInfo.td:516
380 ADDC8mp = 365, // MSP430InstrInfo.td:520
381 ADDC8mr = 366, // MSP430InstrInfo.td:490
382 ADDC8rc = 367, // MSP430InstrInfo.td:477
383 ADDC8ri = 368, // MSP430InstrInfo.td:483
384 ADDC8rm = 369, // MSP430InstrInfo.td:459
385 ADDC8rn = 370, // MSP430InstrInfo.td:465
386 ADDC8rp = 371, // MSP430InstrInfo.td:472
387 ADDC8rr = 372, // MSP430InstrInfo.td:452
388 ADDframe = 373, // MSP430InstrInfo.td:183
389 ADJCALLSTACKDOWN = 374, // MSP430InstrInfo.td:174
390 ADJCALLSTACKUP = 375, // MSP430InstrInfo.td:177
391 AND16mc = 376, // MSP430InstrInfo.td:499
392 AND16mi = 377, // MSP430InstrInfo.td:505
393 AND16mm = 378, // MSP430InstrInfo.td:512
394 AND16mn = 379, // MSP430InstrInfo.td:518
395 AND16mp = 380, // MSP430InstrInfo.td:522
396 AND16mr = 381, // MSP430InstrInfo.td:493
397 AND16rc = 382, // MSP430InstrInfo.td:480
398 AND16ri = 383, // MSP430InstrInfo.td:486
399 AND16rm = 384, // MSP430InstrInfo.td:462
400 AND16rn = 385, // MSP430InstrInfo.td:467
401 AND16rp = 386, // MSP430InstrInfo.td:474
402 AND16rr = 387, // MSP430InstrInfo.td:455
403 AND8mc = 388, // MSP430InstrInfo.td:496
404 AND8mi = 389, // MSP430InstrInfo.td:502
405 AND8mm = 390, // MSP430InstrInfo.td:508
406 AND8mn = 391, // MSP430InstrInfo.td:516
407 AND8mp = 392, // MSP430InstrInfo.td:520
408 AND8mr = 393, // MSP430InstrInfo.td:490
409 AND8rc = 394, // MSP430InstrInfo.td:477
410 AND8ri = 395, // MSP430InstrInfo.td:483
411 AND8rm = 396, // MSP430InstrInfo.td:459
412 AND8rn = 397, // MSP430InstrInfo.td:465
413 AND8rp = 398, // MSP430InstrInfo.td:472
414 AND8rr = 399, // MSP430InstrInfo.td:452
415 BIC16mc = 400, // MSP430InstrInfo.td:499
416 BIC16mi = 401, // MSP430InstrInfo.td:505
417 BIC16mm = 402, // MSP430InstrInfo.td:512
418 BIC16mn = 403, // MSP430InstrInfo.td:518
419 BIC16mp = 404, // MSP430InstrInfo.td:522
420 BIC16mr = 405, // MSP430InstrInfo.td:493
421 BIC16rc = 406, // MSP430InstrInfo.td:480
422 BIC16ri = 407, // MSP430InstrInfo.td:486
423 BIC16rm = 408, // MSP430InstrInfo.td:462
424 BIC16rn = 409, // MSP430InstrInfo.td:467
425 BIC16rp = 410, // MSP430InstrInfo.td:474
426 BIC16rr = 411, // MSP430InstrInfo.td:455
427 BIC8mc = 412, // MSP430InstrInfo.td:496
428 BIC8mi = 413, // MSP430InstrInfo.td:502
429 BIC8mm = 414, // MSP430InstrInfo.td:508
430 BIC8mn = 415, // MSP430InstrInfo.td:516
431 BIC8mp = 416, // MSP430InstrInfo.td:520
432 BIC8mr = 417, // MSP430InstrInfo.td:490
433 BIC8rc = 418, // MSP430InstrInfo.td:477
434 BIC8ri = 419, // MSP430InstrInfo.td:483
435 BIC8rm = 420, // MSP430InstrInfo.td:459
436 BIC8rn = 421, // MSP430InstrInfo.td:465
437 BIC8rp = 422, // MSP430InstrInfo.td:472
438 BIC8rr = 423, // MSP430InstrInfo.td:452
439 BIS16mc = 424, // MSP430InstrInfo.td:499
440 BIS16mi = 425, // MSP430InstrInfo.td:505
441 BIS16mm = 426, // MSP430InstrInfo.td:512
442 BIS16mn = 427, // MSP430InstrInfo.td:518
443 BIS16mp = 428, // MSP430InstrInfo.td:522
444 BIS16mr = 429, // MSP430InstrInfo.td:493
445 BIS16rc = 430, // MSP430InstrInfo.td:480
446 BIS16ri = 431, // MSP430InstrInfo.td:486
447 BIS16rm = 432, // MSP430InstrInfo.td:462
448 BIS16rn = 433, // MSP430InstrInfo.td:467
449 BIS16rp = 434, // MSP430InstrInfo.td:474
450 BIS16rr = 435, // MSP430InstrInfo.td:455
451 BIS8mc = 436, // MSP430InstrInfo.td:496
452 BIS8mi = 437, // MSP430InstrInfo.td:502
453 BIS8mm = 438, // MSP430InstrInfo.td:508
454 BIS8mn = 439, // MSP430InstrInfo.td:516
455 BIS8mp = 440, // MSP430InstrInfo.td:520
456 BIS8mr = 441, // MSP430InstrInfo.td:490
457 BIS8rc = 442, // MSP430InstrInfo.td:477
458 BIS8ri = 443, // MSP430InstrInfo.td:483
459 BIS8rm = 444, // MSP430InstrInfo.td:459
460 BIS8rn = 445, // MSP430InstrInfo.td:465
461 BIS8rp = 446, // MSP430InstrInfo.td:472
462 BIS8rr = 447, // MSP430InstrInfo.td:452
463 BIT16mc = 448, // MSP430InstrInfo.td:861
464 BIT16mi = 449, // MSP430InstrInfo.td:870
465 BIT16mm = 450, // MSP430InstrInfo.td:881
466 BIT16mn = 451, // MSP430InstrInfo.td:889
467 BIT16mp = 452, // MSP430InstrInfo.td:894
468 BIT16mr = 453, // MSP430InstrInfo.td:852
469 BIT16rc = 454, // MSP430InstrInfo.td:815
470 BIT16ri = 455, // MSP430InstrInfo.td:824
471 BIT16rm = 456, // MSP430InstrInfo.td:833
472 BIT16rn = 457, // MSP430InstrInfo.td:840
473 BIT16rp = 458, // MSP430InstrInfo.td:845
474 BIT16rr = 459, // MSP430InstrInfo.td:806
475 BIT8mc = 460, // MSP430InstrInfo.td:857
476 BIT8mi = 461, // MSP430InstrInfo.td:866
477 BIT8mm = 462, // MSP430InstrInfo.td:875
478 BIT8mn = 463, // MSP430InstrInfo.td:887
479 BIT8mp = 464, // MSP430InstrInfo.td:892
480 BIT8mr = 465, // MSP430InstrInfo.td:848
481 BIT8rc = 466, // MSP430InstrInfo.td:811
482 BIT8ri = 467, // MSP430InstrInfo.td:820
483 BIT8rm = 468, // MSP430InstrInfo.td:829
484 BIT8rn = 469, // MSP430InstrInfo.td:838
485 BIT8rp = 470, // MSP430InstrInfo.td:843
486 BIT8rr = 471, // MSP430InstrInfo.td:802
487 Bi = 472, // MSP430InstrInfo.td:255
488 Bm = 473, // MSP430InstrInfo.td:261
489 Br = 474, // MSP430InstrInfo.td:258
490 CALLi = 475, // MSP430InstrInfo.td:284
491 CALLm = 476, // MSP430InstrInfo.td:290
492 CALLn = 477, // MSP430InstrInfo.td:293
493 CALLp = 478, // MSP430InstrInfo.td:294
494 CALLr = 479, // MSP430InstrInfo.td:287
495 CMP16mc = 480, // MSP430InstrInfo.td:738
496 CMP16mi = 481, // MSP430InstrInfo.td:748
497 CMP16mm = 482, // MSP430InstrInfo.td:785
498 CMP16mn = 483, // MSP430InstrInfo.td:791
499 CMP16mp = 484, // MSP430InstrInfo.td:796
500 CMP16mr = 485, // MSP430InstrInfo.td:777
501 CMP16rc = 486, // MSP430InstrInfo.td:720
502 CMP16ri = 487, // MSP430InstrInfo.td:729
503 CMP16rm = 488, // MSP430InstrInfo.td:758
504 CMP16rn = 489, // MSP430InstrInfo.td:765
505 CMP16rp = 490, // MSP430InstrInfo.td:770
506 CMP16rr = 491, // MSP430InstrInfo.td:711
507 CMP8mc = 492, // MSP430InstrInfo.td:734
508 CMP8mi = 493, // MSP430InstrInfo.td:743
509 CMP8mm = 494, // MSP430InstrInfo.td:781
510 CMP8mn = 495, // MSP430InstrInfo.td:789
511 CMP8mp = 496, // MSP430InstrInfo.td:794
512 CMP8mr = 497, // MSP430InstrInfo.td:773
513 CMP8rc = 498, // MSP430InstrInfo.td:716
514 CMP8ri = 499, // MSP430InstrInfo.td:725
515 CMP8rm = 500, // MSP430InstrInfo.td:754
516 CMP8rn = 501, // MSP430InstrInfo.td:763
517 CMP8rp = 502, // MSP430InstrInfo.td:768
518 CMP8rr = 503, // MSP430InstrInfo.td:707
519 DADD16mc = 504, // MSP430InstrInfo.td:499
520 DADD16mi = 505, // MSP430InstrInfo.td:505
521 DADD16mm = 506, // MSP430InstrInfo.td:512
522 DADD16mn = 507, // MSP430InstrInfo.td:518
523 DADD16mp = 508, // MSP430InstrInfo.td:522
524 DADD16mr = 509, // MSP430InstrInfo.td:493
525 DADD16rc = 510, // MSP430InstrInfo.td:480
526 DADD16ri = 511, // MSP430InstrInfo.td:486
527 DADD16rm = 512, // MSP430InstrInfo.td:462
528 DADD16rn = 513, // MSP430InstrInfo.td:467
529 DADD16rp = 514, // MSP430InstrInfo.td:474
530 DADD16rr = 515, // MSP430InstrInfo.td:455
531 DADD8mc = 516, // MSP430InstrInfo.td:496
532 DADD8mi = 517, // MSP430InstrInfo.td:502
533 DADD8mm = 518, // MSP430InstrInfo.td:508
534 DADD8mn = 519, // MSP430InstrInfo.td:516
535 DADD8mp = 520, // MSP430InstrInfo.td:520
536 DADD8mr = 521, // MSP430InstrInfo.td:490
537 DADD8rc = 522, // MSP430InstrInfo.td:477
538 DADD8ri = 523, // MSP430InstrInfo.td:483
539 DADD8rm = 524, // MSP430InstrInfo.td:459
540 DADD8rn = 525, // MSP430InstrInfo.td:465
541 DADD8rp = 526, // MSP430InstrInfo.td:472
542 DADD8rr = 527, // MSP430InstrInfo.td:452
543 JCC = 528, // MSP430InstrInfo.td:269
544 JMP = 529, // MSP430InstrInfo.td:248
545 MOV16mc = 530, // MSP430InstrInfo.td:407
546 MOV16mi = 531, // MSP430InstrInfo.td:416
547 MOV16mm = 532, // MSP430InstrInfo.td:434
548 MOV16mn = 533, // MSP430InstrInfo.td:441
549 MOV16mr = 534, // MSP430InstrInfo.td:425
550 MOV16rc = 535, // MSP430InstrInfo.td:335
551 MOV16ri = 536, // MSP430InstrInfo.td:343
552 MOV16rm = 537, // MSP430InstrInfo.td:354
553 MOV16rn = 538, // MSP430InstrInfo.td:362
554 MOV16rp = 539, // MSP430InstrInfo.td:383
555 MOV16rr = 540, // MSP430InstrInfo.td:324
556 MOV8mc = 541, // MSP430InstrInfo.td:403
557 MOV8mi = 542, // MSP430InstrInfo.td:412
558 MOV8mm = 543, // MSP430InstrInfo.td:430
559 MOV8mn = 544, // MSP430InstrInfo.td:439
560 MOV8mr = 545, // MSP430InstrInfo.td:421
561 MOV8rc = 546, // MSP430InstrInfo.td:331
562 MOV8ri = 547, // MSP430InstrInfo.td:339
563 MOV8rm = 548, // MSP430InstrInfo.td:350
564 MOV8rn = 549, // MSP430InstrInfo.td:358
565 MOV8rp = 550, // MSP430InstrInfo.td:380
566 MOV8rr = 551, // MSP430InstrInfo.td:320
567 MOVZX16rm8 = 552, // MSP430InstrInfo.td:373
568 MOVZX16rr8 = 553, // MSP430InstrInfo.td:369
569 POP16r = 554, // MSP430InstrInfo.td:302
570 PUSH16c = 555, // MSP430InstrInfo.td:311
571 PUSH16i = 556, // MSP430InstrInfo.td:312
572 PUSH16r = 557, // MSP430InstrInfo.td:310
573 PUSH8r = 558, // MSP430InstrInfo.td:309
574 RET = 559, // MSP430InstrInfo.td:229
575 RETI = 560, // MSP430InstrInfo.td:235
576 RRA16m = 561, // MSP430InstrInfo.td:661
577 RRA16n = 562, // MSP430InstrInfo.td:667
578 RRA16p = 563, // MSP430InstrInfo.td:669
579 RRA16r = 564, // MSP430InstrInfo.td:619
580 RRA8m = 565, // MSP430InstrInfo.td:657
581 RRA8n = 566, // MSP430InstrInfo.td:666
582 RRA8p = 567, // MSP430InstrInfo.td:668
583 RRA8r = 568, // MSP430InstrInfo.td:615
584 RRC16m = 569, // MSP430InstrInfo.td:676
585 RRC16n = 570, // MSP430InstrInfo.td:682
586 RRC16p = 571, // MSP430InstrInfo.td:684
587 RRC16r = 572, // MSP430InstrInfo.td:629
588 RRC8m = 573, // MSP430InstrInfo.td:672
589 RRC8n = 574, // MSP430InstrInfo.td:681
590 RRC8p = 575, // MSP430InstrInfo.td:683
591 RRC8r = 576, // MSP430InstrInfo.td:625
592 Rrcl16 = 577, // MSP430InstrInfo.td:219
593 Rrcl8 = 578, // MSP430InstrInfo.td:217
594 SEXT16m = 579, // MSP430InstrInfo.td:688
595 SEXT16n = 580, // MSP430InstrInfo.td:693
596 SEXT16p = 581, // MSP430InstrInfo.td:694
597 SEXT16r = 582, // MSP430InstrInfo.td:635
598 SUB16mc = 583, // MSP430InstrInfo.td:499
599 SUB16mi = 584, // MSP430InstrInfo.td:505
600 SUB16mm = 585, // MSP430InstrInfo.td:512
601 SUB16mn = 586, // MSP430InstrInfo.td:518
602 SUB16mp = 587, // MSP430InstrInfo.td:522
603 SUB16mr = 588, // MSP430InstrInfo.td:493
604 SUB16rc = 589, // MSP430InstrInfo.td:480
605 SUB16ri = 590, // MSP430InstrInfo.td:486
606 SUB16rm = 591, // MSP430InstrInfo.td:462
607 SUB16rn = 592, // MSP430InstrInfo.td:467
608 SUB16rp = 593, // MSP430InstrInfo.td:474
609 SUB16rr = 594, // MSP430InstrInfo.td:455
610 SUB8mc = 595, // MSP430InstrInfo.td:496
611 SUB8mi = 596, // MSP430InstrInfo.td:502
612 SUB8mm = 597, // MSP430InstrInfo.td:508
613 SUB8mn = 598, // MSP430InstrInfo.td:516
614 SUB8mp = 599, // MSP430InstrInfo.td:520
615 SUB8mr = 600, // MSP430InstrInfo.td:490
616 SUB8rc = 601, // MSP430InstrInfo.td:477
617 SUB8ri = 602, // MSP430InstrInfo.td:483
618 SUB8rm = 603, // MSP430InstrInfo.td:459
619 SUB8rn = 604, // MSP430InstrInfo.td:465
620 SUB8rp = 605, // MSP430InstrInfo.td:472
621 SUB8rr = 606, // MSP430InstrInfo.td:452
622 SUBC16mc = 607, // MSP430InstrInfo.td:499
623 SUBC16mi = 608, // MSP430InstrInfo.td:505
624 SUBC16mm = 609, // MSP430InstrInfo.td:512
625 SUBC16mn = 610, // MSP430InstrInfo.td:518
626 SUBC16mp = 611, // MSP430InstrInfo.td:522
627 SUBC16mr = 612, // MSP430InstrInfo.td:493
628 SUBC16rc = 613, // MSP430InstrInfo.td:480
629 SUBC16ri = 614, // MSP430InstrInfo.td:486
630 SUBC16rm = 615, // MSP430InstrInfo.td:462
631 SUBC16rn = 616, // MSP430InstrInfo.td:467
632 SUBC16rp = 617, // MSP430InstrInfo.td:474
633 SUBC16rr = 618, // MSP430InstrInfo.td:455
634 SUBC8mc = 619, // MSP430InstrInfo.td:496
635 SUBC8mi = 620, // MSP430InstrInfo.td:502
636 SUBC8mm = 621, // MSP430InstrInfo.td:508
637 SUBC8mn = 622, // MSP430InstrInfo.td:516
638 SUBC8mp = 623, // MSP430InstrInfo.td:520
639 SUBC8mr = 624, // MSP430InstrInfo.td:490
640 SUBC8rc = 625, // MSP430InstrInfo.td:477
641 SUBC8ri = 626, // MSP430InstrInfo.td:483
642 SUBC8rm = 627, // MSP430InstrInfo.td:459
643 SUBC8rn = 628, // MSP430InstrInfo.td:465
644 SUBC8rp = 629, // MSP430InstrInfo.td:472
645 SUBC8rr = 630, // MSP430InstrInfo.td:452
646 SWPB16m = 631, // MSP430InstrInfo.td:698
647 SWPB16n = 632, // MSP430InstrInfo.td:702
648 SWPB16p = 633, // MSP430InstrInfo.td:703
649 SWPB16r = 634, // MSP430InstrInfo.td:648
650 Select16 = 635, // MSP430InstrInfo.td:193
651 Select8 = 636, // MSP430InstrInfo.td:189
652 Shl16 = 637, // MSP430InstrInfo.td:202
653 Shl8 = 638, // MSP430InstrInfo.td:199
654 Sra16 = 639, // MSP430InstrInfo.td:208
655 Sra8 = 640, // MSP430InstrInfo.td:205
656 Srl16 = 641, // MSP430InstrInfo.td:214
657 Srl8 = 642, // MSP430InstrInfo.td:211
658 XOR16mc = 643, // MSP430InstrInfo.td:499
659 XOR16mi = 644, // MSP430InstrInfo.td:505
660 XOR16mm = 645, // MSP430InstrInfo.td:512
661 XOR16mn = 646, // MSP430InstrInfo.td:518
662 XOR16mp = 647, // MSP430InstrInfo.td:522
663 XOR16mr = 648, // MSP430InstrInfo.td:493
664 XOR16rc = 649, // MSP430InstrInfo.td:480
665 XOR16ri = 650, // MSP430InstrInfo.td:486
666 XOR16rm = 651, // MSP430InstrInfo.td:462
667 XOR16rn = 652, // MSP430InstrInfo.td:467
668 XOR16rp = 653, // MSP430InstrInfo.td:474
669 XOR16rr = 654, // MSP430InstrInfo.td:455
670 XOR8mc = 655, // MSP430InstrInfo.td:496
671 XOR8mi = 656, // MSP430InstrInfo.td:502
672 XOR8mm = 657, // MSP430InstrInfo.td:508
673 XOR8mn = 658, // MSP430InstrInfo.td:516
674 XOR8mp = 659, // MSP430InstrInfo.td:520
675 XOR8mr = 660, // MSP430InstrInfo.td:490
676 XOR8rc = 661, // MSP430InstrInfo.td:477
677 XOR8ri = 662, // MSP430InstrInfo.td:483
678 XOR8rm = 663, // MSP430InstrInfo.td:459
679 XOR8rn = 664, // MSP430InstrInfo.td:465
680 XOR8rp = 665, // MSP430InstrInfo.td:472
681 XOR8rr = 666, // MSP430InstrInfo.td:452
682 ZEXT16r = 667, // MSP430InstrInfo.td:643
683 INSTRUCTION_LIST_END = 668
684 };
685
686} // namespace llvm::MSP430
687
688#endif // GET_INSTRINFO_ENUM
689
690#ifdef GET_INSTRINFO_SCHED_ENUM
691#undef GET_INSTRINFO_SCHED_ENUM
692
693namespace llvm::MSP430::Sched {
694
695 enum {
696 NoInstrModel = 0,
697 SCHED_LIST_END = 1
698 };
699
700} // namespace llvm::MSP430::Sched
701
702#endif // GET_INSTRINFO_SCHED_ENUM
703
704#if defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
705
706namespace llvm {
707
708struct MSP430InstrTable {
709 MCInstrDesc Insts[668];
710 static_assert(alignof(MCInstrDesc) >= alignof(MCPhysReg), "Unwanted padding between Insts and ImplicitOps");
711 MCPhysReg ImplicitOps[17];
712 char Padding[sizeof(MCOperandInfo) - sizeof ImplicitOps % sizeof(MCOperandInfo)];
713 static_assert(alignof(MCInstrDesc) >= alignof(MCOperandInfo), "Unwanted padding between Insts and OperandInfo");
714 MCOperandInfo OperandInfo[260];
715};
716} // namespace llvm
717
718#endif // defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
719
720#ifdef GET_INSTRINFO_MC_DESC
721#undef GET_INSTRINFO_MC_DESC
722
723namespace llvm {
724
725static_assert((sizeof MSP430InstrTable::ImplicitOps + sizeof MSP430InstrTable::Padding) % sizeof(MCOperandInfo) == 0);
726static constexpr unsigned MSP430OpInfoBase = (sizeof MSP430InstrTable::ImplicitOps + sizeof MSP430InstrTable::Padding) / sizeof(MCOperandInfo);
727
728extern const MSP430InstrTable MSP430Descs = {
729 {
730 { 667, 2, 1, 2, 0, 0, 0, MSP430OpInfoBase + 242, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ZEXT16r
731 { 666, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 207, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR8rr
732 { 665, 4, 2, 2, 0, 0, 1, MSP430OpInfoBase + 203, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR8rp
733 { 664, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR8rn
734 { 663, 4, 1, 4, 0, 0, 1, MSP430OpInfoBase + 196, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR8rm
735 { 662, 3, 1, 4, 0, 0, 1, MSP430OpInfoBase + 193, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR8ri
736 { 661, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 190, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR8rc
737 { 660, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 187, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR8mr
738 { 659, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR8mp
739 { 658, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR8mn
740 { 657, 4, 0, 6, 0, 0, 1, MSP430OpInfoBase + 157, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR8mm
741 { 656, 3, 0, 6, 0, 0, 1, MSP430OpInfoBase + 154, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR8mi
742 { 655, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 151, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR8mc
743 { 654, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 184, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR16rr
744 { 653, 4, 2, 2, 0, 0, 1, MSP430OpInfoBase + 180, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR16rp
745 { 652, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 177, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR16rn
746 { 651, 4, 1, 4, 0, 0, 1, MSP430OpInfoBase + 173, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR16rm
747 { 650, 3, 1, 4, 0, 0, 1, MSP430OpInfoBase + 170, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR16ri
748 { 649, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 167, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR16rc
749 { 648, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 164, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR16mr
750 { 647, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR16mp
751 { 646, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR16mn
752 { 645, 4, 0, 6, 0, 0, 1, MSP430OpInfoBase + 157, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR16mm
753 { 644, 3, 0, 6, 0, 0, 1, MSP430OpInfoBase + 154, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR16mi
754 { 643, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 151, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR16mc
755 { 642, 3, 1, 0, 0, 0, 1, MSP430OpInfoBase + 257, 0, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Srl8
756 { 641, 3, 1, 0, 0, 0, 1, MSP430OpInfoBase + 254, 0, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Srl16
757 { 640, 3, 1, 0, 0, 0, 1, MSP430OpInfoBase + 257, 0, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Sra8
758 { 639, 3, 1, 0, 0, 0, 1, MSP430OpInfoBase + 254, 0, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Sra16
759 { 638, 3, 1, 0, 0, 0, 1, MSP430OpInfoBase + 257, 0, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Shl8
760 { 637, 3, 1, 0, 0, 0, 1, MSP430OpInfoBase + 254, 0, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Shl16
761 { 636, 4, 1, 0, 0, 1, 0, MSP430OpInfoBase + 250, 0, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Select8
762 { 635, 4, 1, 0, 0, 1, 0, MSP430OpInfoBase + 246, 0, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Select16
763 { 634, 2, 1, 2, 0, 0, 0, MSP430OpInfoBase + 242, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SWPB16r
764 { 633, 1, 0, 2, 0, 0, 0, MSP430OpInfoBase + 232, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SWPB16p
765 { 632, 1, 0, 2, 0, 0, 0, MSP430OpInfoBase + 232, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SWPB16n
766 { 631, 2, 0, 4, 0, 0, 0, MSP430OpInfoBase + 230, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SWPB16m
767 { 630, 3, 1, 2, 0, 1, 1, MSP430OpInfoBase + 207, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC8rr
768 { 629, 4, 2, 2, 0, 1, 1, MSP430OpInfoBase + 203, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC8rp
769 { 628, 3, 1, 2, 0, 1, 1, MSP430OpInfoBase + 200, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC8rn
770 { 627, 4, 1, 4, 0, 1, 1, MSP430OpInfoBase + 196, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC8rm
771 { 626, 3, 1, 4, 0, 1, 1, MSP430OpInfoBase + 193, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC8ri
772 { 625, 3, 1, 2, 0, 1, 1, MSP430OpInfoBase + 190, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC8rc
773 { 624, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 187, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC8mr
774 { 623, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 161, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC8mp
775 { 622, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 161, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC8mn
776 { 621, 4, 0, 6, 0, 1, 1, MSP430OpInfoBase + 157, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC8mm
777 { 620, 3, 0, 6, 0, 1, 1, MSP430OpInfoBase + 154, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC8mi
778 { 619, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 151, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC8mc
779 { 618, 3, 1, 2, 0, 1, 1, MSP430OpInfoBase + 184, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC16rr
780 { 617, 4, 2, 2, 0, 1, 1, MSP430OpInfoBase + 180, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC16rp
781 { 616, 3, 1, 2, 0, 1, 1, MSP430OpInfoBase + 177, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC16rn
782 { 615, 4, 1, 4, 0, 1, 1, MSP430OpInfoBase + 173, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC16rm
783 { 614, 3, 1, 4, 0, 1, 1, MSP430OpInfoBase + 170, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC16ri
784 { 613, 3, 1, 2, 0, 1, 1, MSP430OpInfoBase + 167, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC16rc
785 { 612, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 164, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC16mr
786 { 611, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 161, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC16mp
787 { 610, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 161, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC16mn
788 { 609, 4, 0, 6, 0, 1, 1, MSP430OpInfoBase + 157, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC16mm
789 { 608, 3, 0, 6, 0, 1, 1, MSP430OpInfoBase + 154, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC16mi
790 { 607, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 151, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC16mc
791 { 606, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 207, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB8rr
792 { 605, 4, 2, 2, 0, 0, 1, MSP430OpInfoBase + 203, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB8rp
793 { 604, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB8rn
794 { 603, 4, 1, 4, 0, 0, 1, MSP430OpInfoBase + 196, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB8rm
795 { 602, 3, 1, 4, 0, 0, 1, MSP430OpInfoBase + 193, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB8ri
796 { 601, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 190, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB8rc
797 { 600, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 187, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB8mr
798 { 599, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB8mp
799 { 598, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB8mn
800 { 597, 4, 0, 6, 0, 0, 1, MSP430OpInfoBase + 157, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB8mm
801 { 596, 3, 0, 6, 0, 0, 1, MSP430OpInfoBase + 154, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB8mi
802 { 595, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 151, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB8mc
803 { 594, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 184, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB16rr
804 { 593, 4, 2, 2, 0, 0, 1, MSP430OpInfoBase + 180, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB16rp
805 { 592, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 177, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB16rn
806 { 591, 4, 1, 4, 0, 0, 1, MSP430OpInfoBase + 173, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB16rm
807 { 590, 3, 1, 4, 0, 0, 1, MSP430OpInfoBase + 170, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB16ri
808 { 589, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 167, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB16rc
809 { 588, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 164, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB16mr
810 { 587, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB16mp
811 { 586, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB16mn
812 { 585, 4, 0, 6, 0, 0, 1, MSP430OpInfoBase + 157, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB16mm
813 { 584, 3, 0, 6, 0, 0, 1, MSP430OpInfoBase + 154, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB16mi
814 { 583, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 151, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB16mc
815 { 582, 2, 1, 2, 0, 0, 1, MSP430OpInfoBase + 242, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SEXT16r
816 { 581, 1, 0, 2, 0, 0, 1, MSP430OpInfoBase + 232, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SEXT16p
817 { 580, 1, 0, 2, 0, 0, 1, MSP430OpInfoBase + 232, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SEXT16n
818 { 579, 2, 0, 4, 0, 0, 1, MSP430OpInfoBase + 230, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SEXT16m
819 { 578, 2, 1, 0, 0, 0, 1, MSP430OpInfoBase + 228, 0, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Rrcl8
820 { 577, 2, 1, 0, 0, 0, 1, MSP430OpInfoBase + 217, 0, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Rrcl16
821 { 576, 2, 1, 2, 0, 1, 1, MSP430OpInfoBase + 244, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RRC8r
822 { 575, 1, 0, 2, 0, 1, 1, MSP430OpInfoBase + 232, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RRC8p
823 { 574, 1, 0, 2, 0, 1, 1, MSP430OpInfoBase + 232, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RRC8n
824 { 573, 2, 0, 4, 0, 1, 1, MSP430OpInfoBase + 230, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RRC8m
825 { 572, 2, 1, 2, 0, 1, 1, MSP430OpInfoBase + 242, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RRC16r
826 { 571, 1, 0, 2, 0, 1, 1, MSP430OpInfoBase + 232, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RRC16p
827 { 570, 1, 0, 2, 0, 1, 1, MSP430OpInfoBase + 232, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RRC16n
828 { 569, 2, 0, 4, 0, 1, 1, MSP430OpInfoBase + 230, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RRC16m
829 { 568, 2, 1, 2, 0, 0, 1, MSP430OpInfoBase + 244, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RRA8r
830 { 567, 1, 0, 2, 0, 0, 1, MSP430OpInfoBase + 232, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RRA8p
831 { 566, 1, 0, 2, 0, 0, 1, MSP430OpInfoBase + 232, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RRA8n
832 { 565, 2, 0, 4, 0, 0, 1, MSP430OpInfoBase + 230, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RRA8m
833 { 564, 2, 1, 2, 0, 0, 1, MSP430OpInfoBase + 242, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RRA16r
834 { 563, 1, 0, 2, 0, 0, 1, MSP430OpInfoBase + 232, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RRA16p
835 { 562, 1, 0, 2, 0, 0, 1, MSP430OpInfoBase + 232, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RRA16n
836 { 561, 2, 0, 4, 0, 0, 1, MSP430OpInfoBase + 230, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RRA16m
837 { 560, 0, 0, 2, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RETI
838 { 559, 0, 0, 2, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RET
839 { 558, 1, 0, 2, 0, 1, 1, MSP430OpInfoBase + 241, 15, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PUSH8r
840 { 557, 1, 0, 2, 0, 1, 1, MSP430OpInfoBase + 28, 15, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PUSH16r
841 { 556, 1, 0, 4, 0, 1, 1, MSP430OpInfoBase + 1, 15, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PUSH16i
842 { 555, 1, 0, 2, 0, 1, 1, MSP430OpInfoBase + 0, 15, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PUSH16c
843 { 554, 1, 1, 2, 0, 1, 1, MSP430OpInfoBase + 28, 15, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // POP16r
844 { 553, 2, 1, 2, 0, 0, 0, MSP430OpInfoBase + 239, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOVZX16rr8
845 { 552, 3, 1, 4, 0, 0, 0, MSP430OpInfoBase + 212, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOVZX16rm8
846 { 551, 2, 1, 2, 0, 0, 0, MSP430OpInfoBase + 228, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV8rr
847 { 550, 3, 2, 2, 0, 0, 0, MSP430OpInfoBase + 236, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV8rp
848 { 549, 2, 1, 2, 0, 0, 0, MSP430OpInfoBase + 226, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV8rn
849 { 548, 3, 1, 4, 0, 0, 0, MSP430OpInfoBase + 223, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV8rm
850 { 547, 2, 1, 4, 0, 0, 0, MSP430OpInfoBase + 221, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV8ri
851 { 546, 2, 1, 2, 0, 0, 0, MSP430OpInfoBase + 219, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV8rc
852 { 545, 3, 0, 4, 0, 0, 0, MSP430OpInfoBase + 187, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV8mr
853 { 544, 3, 0, 4, 0, 0, 0, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV8mn
854 { 543, 4, 0, 6, 0, 0, 0, MSP430OpInfoBase + 157, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV8mm
855 { 542, 3, 0, 6, 0, 0, 0, MSP430OpInfoBase + 154, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV8mi
856 { 541, 3, 0, 4, 0, 0, 0, MSP430OpInfoBase + 151, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV8mc
857 { 540, 2, 1, 2, 0, 0, 0, MSP430OpInfoBase + 217, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV16rr
858 { 539, 3, 2, 2, 0, 0, 0, MSP430OpInfoBase + 233, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV16rp
859 { 538, 2, 1, 2, 0, 0, 0, MSP430OpInfoBase + 215, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV16rn
860 { 537, 3, 1, 4, 0, 0, 0, MSP430OpInfoBase + 212, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV16rm
861 { 536, 2, 1, 4, 0, 0, 0, MSP430OpInfoBase + 210, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV16ri
862 { 535, 2, 1, 2, 0, 0, 0, MSP430OpInfoBase + 34, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV16rc
863 { 534, 3, 0, 4, 0, 0, 0, MSP430OpInfoBase + 164, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV16mr
864 { 533, 3, 0, 4, 0, 0, 0, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV16mn
865 { 532, 4, 0, 6, 0, 0, 0, MSP430OpInfoBase + 157, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV16mm
866 { 531, 3, 0, 6, 0, 0, 0, MSP430OpInfoBase + 154, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV16mi
867 { 530, 3, 0, 4, 0, 0, 0, MSP430OpInfoBase + 151, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV16mc
868 { 529, 1, 0, 2, 0, 0, 0, MSP430OpInfoBase + 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JMP
869 { 528, 2, 0, 2, 0, 1, 0, MSP430OpInfoBase + 9, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JCC
870 { 527, 3, 1, 2, 0, 1, 1, MSP430OpInfoBase + 207, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD8rr
871 { 526, 4, 2, 2, 0, 1, 1, MSP430OpInfoBase + 203, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD8rp
872 { 525, 3, 1, 2, 0, 1, 1, MSP430OpInfoBase + 200, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD8rn
873 { 524, 4, 1, 4, 0, 1, 1, MSP430OpInfoBase + 196, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD8rm
874 { 523, 3, 1, 4, 0, 1, 1, MSP430OpInfoBase + 193, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD8ri
875 { 522, 3, 1, 2, 0, 1, 1, MSP430OpInfoBase + 190, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD8rc
876 { 521, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 187, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD8mr
877 { 520, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 161, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD8mp
878 { 519, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 161, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD8mn
879 { 518, 4, 0, 6, 0, 1, 1, MSP430OpInfoBase + 157, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD8mm
880 { 517, 3, 0, 6, 0, 1, 1, MSP430OpInfoBase + 154, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD8mi
881 { 516, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 151, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD8mc
882 { 515, 3, 1, 2, 0, 1, 1, MSP430OpInfoBase + 184, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD16rr
883 { 514, 4, 2, 2, 0, 1, 1, MSP430OpInfoBase + 180, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD16rp
884 { 513, 3, 1, 2, 0, 1, 1, MSP430OpInfoBase + 177, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD16rn
885 { 512, 4, 1, 4, 0, 1, 1, MSP430OpInfoBase + 173, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD16rm
886 { 511, 3, 1, 4, 0, 1, 1, MSP430OpInfoBase + 170, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD16ri
887 { 510, 3, 1, 2, 0, 1, 1, MSP430OpInfoBase + 167, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD16rc
888 { 509, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 164, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD16mr
889 { 508, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 161, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD16mp
890 { 507, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 161, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD16mn
891 { 506, 4, 0, 6, 0, 1, 1, MSP430OpInfoBase + 157, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD16mm
892 { 505, 3, 0, 6, 0, 1, 1, MSP430OpInfoBase + 154, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD16mi
893 { 504, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 151, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD16mc
894 { 503, 2, 0, 2, 0, 0, 1, MSP430OpInfoBase + 228, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP8rr
895 { 502, 2, 0, 2, 0, 0, 1, MSP430OpInfoBase + 226, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP8rp
896 { 501, 2, 0, 2, 0, 0, 1, MSP430OpInfoBase + 226, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP8rn
897 { 500, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 223, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP8rm
898 { 499, 2, 0, 4, 0, 0, 1, MSP430OpInfoBase + 221, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP8ri
899 { 498, 2, 0, 2, 0, 0, 1, MSP430OpInfoBase + 219, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP8rc
900 { 497, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 187, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP8mr
901 { 496, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP8mp
902 { 495, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP8mn
903 { 494, 4, 0, 6, 0, 0, 1, MSP430OpInfoBase + 157, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP8mm
904 { 493, 3, 0, 6, 0, 0, 1, MSP430OpInfoBase + 154, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP8mi
905 { 492, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 151, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP8mc
906 { 491, 2, 0, 2, 0, 0, 1, MSP430OpInfoBase + 217, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP16rr
907 { 490, 2, 0, 2, 0, 0, 1, MSP430OpInfoBase + 215, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP16rp
908 { 489, 2, 0, 2, 0, 0, 1, MSP430OpInfoBase + 215, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP16rn
909 { 488, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 212, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP16rm
910 { 487, 2, 0, 4, 0, 0, 1, MSP430OpInfoBase + 210, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP16ri
911 { 486, 2, 0, 2, 0, 0, 1, MSP430OpInfoBase + 34, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP16rc
912 { 485, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 164, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP16mr
913 { 484, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP16mp
914 { 483, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP16mn
915 { 482, 4, 0, 6, 0, 0, 1, MSP430OpInfoBase + 157, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP16mm
916 { 481, 3, 0, 6, 0, 0, 1, MSP430OpInfoBase + 154, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP16mi
917 { 480, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 151, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP16mc
918 { 479, 1, 0, 2, 0, 1, 6, MSP430OpInfoBase + 28, 8, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CALLr
919 { 478, 1, 0, 2, 0, 1, 6, MSP430OpInfoBase + 232, 8, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CALLp
920 { 477, 1, 0, 2, 0, 1, 6, MSP430OpInfoBase + 232, 8, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CALLn
921 { 476, 2, 0, 4, 0, 1, 6, MSP430OpInfoBase + 230, 8, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CALLm
922 { 475, 1, 0, 4, 0, 1, 6, MSP430OpInfoBase + 1, 8, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CALLi
923 { 474, 1, 0, 2, 0, 0, 0, MSP430OpInfoBase + 28, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Br
924 { 473, 2, 0, 4, 0, 0, 0, MSP430OpInfoBase + 230, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Bm
925 { 472, 1, 0, 4, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Bi
926 { 471, 2, 0, 2, 0, 0, 1, MSP430OpInfoBase + 228, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT8rr
927 { 470, 2, 0, 2, 0, 0, 1, MSP430OpInfoBase + 226, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT8rp
928 { 469, 2, 0, 2, 0, 0, 1, MSP430OpInfoBase + 226, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT8rn
929 { 468, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 223, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT8rm
930 { 467, 2, 0, 4, 0, 0, 1, MSP430OpInfoBase + 221, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT8ri
931 { 466, 2, 0, 2, 0, 0, 1, MSP430OpInfoBase + 219, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT8rc
932 { 465, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 187, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT8mr
933 { 464, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT8mp
934 { 463, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT8mn
935 { 462, 4, 0, 6, 0, 0, 1, MSP430OpInfoBase + 157, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT8mm
936 { 461, 3, 0, 6, 0, 0, 1, MSP430OpInfoBase + 154, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT8mi
937 { 460, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 151, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT8mc
938 { 459, 2, 0, 2, 0, 0, 1, MSP430OpInfoBase + 217, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT16rr
939 { 458, 2, 0, 2, 0, 0, 1, MSP430OpInfoBase + 215, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT16rp
940 { 457, 2, 0, 2, 0, 0, 1, MSP430OpInfoBase + 215, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT16rn
941 { 456, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 212, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT16rm
942 { 455, 2, 0, 4, 0, 0, 1, MSP430OpInfoBase + 210, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT16ri
943 { 454, 2, 0, 2, 0, 0, 1, MSP430OpInfoBase + 34, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT16rc
944 { 453, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 164, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT16mr
945 { 452, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT16mp
946 { 451, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT16mn
947 { 450, 4, 0, 6, 0, 0, 1, MSP430OpInfoBase + 157, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT16mm
948 { 449, 3, 0, 6, 0, 0, 1, MSP430OpInfoBase + 154, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT16mi
949 { 448, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 151, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT16mc
950 { 447, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 207, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS8rr
951 { 446, 4, 2, 2, 0, 0, 1, MSP430OpInfoBase + 203, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS8rp
952 { 445, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS8rn
953 { 444, 4, 1, 4, 0, 0, 1, MSP430OpInfoBase + 196, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS8rm
954 { 443, 3, 1, 4, 0, 0, 1, MSP430OpInfoBase + 193, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS8ri
955 { 442, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 190, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS8rc
956 { 441, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 187, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS8mr
957 { 440, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS8mp
958 { 439, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS8mn
959 { 438, 4, 0, 6, 0, 0, 1, MSP430OpInfoBase + 157, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS8mm
960 { 437, 3, 0, 6, 0, 0, 1, MSP430OpInfoBase + 154, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS8mi
961 { 436, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 151, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS8mc
962 { 435, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 184, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS16rr
963 { 434, 4, 2, 2, 0, 0, 1, MSP430OpInfoBase + 180, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS16rp
964 { 433, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 177, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS16rn
965 { 432, 4, 1, 4, 0, 0, 1, MSP430OpInfoBase + 173, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS16rm
966 { 431, 3, 1, 4, 0, 0, 1, MSP430OpInfoBase + 170, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS16ri
967 { 430, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 167, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS16rc
968 { 429, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 164, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS16mr
969 { 428, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS16mp
970 { 427, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS16mn
971 { 426, 4, 0, 6, 0, 0, 1, MSP430OpInfoBase + 157, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS16mm
972 { 425, 3, 0, 6, 0, 0, 1, MSP430OpInfoBase + 154, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS16mi
973 { 424, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 151, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS16mc
974 { 423, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 207, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC8rr
975 { 422, 4, 2, 2, 0, 0, 1, MSP430OpInfoBase + 203, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC8rp
976 { 421, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC8rn
977 { 420, 4, 1, 4, 0, 0, 1, MSP430OpInfoBase + 196, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC8rm
978 { 419, 3, 1, 4, 0, 0, 1, MSP430OpInfoBase + 193, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC8ri
979 { 418, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 190, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC8rc
980 { 417, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 187, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC8mr
981 { 416, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC8mp
982 { 415, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC8mn
983 { 414, 4, 0, 6, 0, 0, 1, MSP430OpInfoBase + 157, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC8mm
984 { 413, 3, 0, 6, 0, 0, 1, MSP430OpInfoBase + 154, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC8mi
985 { 412, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 151, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC8mc
986 { 411, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 184, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC16rr
987 { 410, 4, 2, 2, 0, 0, 1, MSP430OpInfoBase + 180, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC16rp
988 { 409, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 177, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC16rn
989 { 408, 4, 1, 4, 0, 0, 1, MSP430OpInfoBase + 173, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC16rm
990 { 407, 3, 1, 4, 0, 0, 1, MSP430OpInfoBase + 170, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC16ri
991 { 406, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 167, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC16rc
992 { 405, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 164, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC16mr
993 { 404, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC16mp
994 { 403, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC16mn
995 { 402, 4, 0, 6, 0, 0, 1, MSP430OpInfoBase + 157, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC16mm
996 { 401, 3, 0, 6, 0, 0, 1, MSP430OpInfoBase + 154, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC16mi
997 { 400, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 151, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC16mc
998 { 399, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 207, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND8rr
999 { 398, 4, 2, 2, 0, 0, 1, MSP430OpInfoBase + 203, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND8rp
1000 { 397, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND8rn
1001 { 396, 4, 1, 4, 0, 0, 1, MSP430OpInfoBase + 196, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND8rm
1002 { 395, 3, 1, 4, 0, 0, 1, MSP430OpInfoBase + 193, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND8ri
1003 { 394, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 190, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND8rc
1004 { 393, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 187, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND8mr
1005 { 392, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND8mp
1006 { 391, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND8mn
1007 { 390, 4, 0, 6, 0, 0, 1, MSP430OpInfoBase + 157, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND8mm
1008 { 389, 3, 0, 6, 0, 0, 1, MSP430OpInfoBase + 154, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND8mi
1009 { 388, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 151, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND8mc
1010 { 387, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 184, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND16rr
1011 { 386, 4, 2, 2, 0, 0, 1, MSP430OpInfoBase + 180, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND16rp
1012 { 385, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 177, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND16rn
1013 { 384, 4, 1, 4, 0, 0, 1, MSP430OpInfoBase + 173, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND16rm
1014 { 383, 3, 1, 4, 0, 0, 1, MSP430OpInfoBase + 170, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND16ri
1015 { 382, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 167, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND16rc
1016 { 381, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 164, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND16mr
1017 { 380, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND16mp
1018 { 379, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND16mn
1019 { 378, 4, 0, 6, 0, 0, 1, MSP430OpInfoBase + 157, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND16mm
1020 { 377, 3, 0, 6, 0, 0, 1, MSP430OpInfoBase + 154, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND16mi
1021 { 376, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 151, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND16mc
1022 { 375, 2, 0, 0, 0, 1, 2, MSP430OpInfoBase + 20, 5, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADJCALLSTACKUP
1023 { 374, 2, 0, 0, 0, 1, 2, MSP430OpInfoBase + 20, 5, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADJCALLSTACKDOWN
1024 { 373, 3, 1, 0, 0, 1, 1, MSP430OpInfoBase + 29, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDframe
1025 { 372, 3, 1, 2, 0, 1, 1, MSP430OpInfoBase + 207, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC8rr
1026 { 371, 4, 2, 2, 0, 1, 1, MSP430OpInfoBase + 203, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC8rp
1027 { 370, 3, 1, 2, 0, 1, 1, MSP430OpInfoBase + 200, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC8rn
1028 { 369, 4, 1, 4, 0, 1, 1, MSP430OpInfoBase + 196, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC8rm
1029 { 368, 3, 1, 4, 0, 1, 1, MSP430OpInfoBase + 193, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC8ri
1030 { 367, 3, 1, 2, 0, 1, 1, MSP430OpInfoBase + 190, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC8rc
1031 { 366, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 187, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC8mr
1032 { 365, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 161, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC8mp
1033 { 364, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 161, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC8mn
1034 { 363, 4, 0, 6, 0, 1, 1, MSP430OpInfoBase + 157, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC8mm
1035 { 362, 3, 0, 6, 0, 1, 1, MSP430OpInfoBase + 154, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC8mi
1036 { 361, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 151, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC8mc
1037 { 360, 3, 1, 2, 0, 1, 1, MSP430OpInfoBase + 184, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC16rr
1038 { 359, 4, 2, 2, 0, 1, 1, MSP430OpInfoBase + 180, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC16rp
1039 { 358, 3, 1, 2, 0, 1, 1, MSP430OpInfoBase + 177, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC16rn
1040 { 357, 4, 1, 4, 0, 1, 1, MSP430OpInfoBase + 173, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC16rm
1041 { 356, 3, 1, 4, 0, 1, 1, MSP430OpInfoBase + 170, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC16ri
1042 { 355, 3, 1, 2, 0, 1, 1, MSP430OpInfoBase + 167, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC16rc
1043 { 354, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 164, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC16mr
1044 { 353, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 161, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC16mp
1045 { 352, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 161, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC16mn
1046 { 351, 4, 0, 6, 0, 1, 1, MSP430OpInfoBase + 157, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC16mm
1047 { 350, 3, 0, 6, 0, 1, 1, MSP430OpInfoBase + 154, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC16mi
1048 { 349, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 151, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC16mc
1049 { 348, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 207, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD8rr
1050 { 347, 4, 2, 2, 0, 0, 1, MSP430OpInfoBase + 203, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD8rp
1051 { 346, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD8rn
1052 { 345, 4, 1, 4, 0, 0, 1, MSP430OpInfoBase + 196, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD8rm
1053 { 344, 3, 1, 4, 0, 0, 1, MSP430OpInfoBase + 193, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD8ri
1054 { 343, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 190, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD8rc
1055 { 342, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 187, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD8mr
1056 { 341, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD8mp
1057 { 340, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD8mn
1058 { 339, 4, 0, 6, 0, 0, 1, MSP430OpInfoBase + 157, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD8mm
1059 { 338, 3, 0, 6, 0, 0, 1, MSP430OpInfoBase + 154, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD8mi
1060 { 337, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 151, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD8mc
1061 { 336, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 184, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD16rr
1062 { 335, 4, 2, 2, 0, 0, 1, MSP430OpInfoBase + 180, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD16rp
1063 { 334, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 177, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD16rn
1064 { 333, 4, 1, 4, 0, 0, 1, MSP430OpInfoBase + 173, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD16rm
1065 { 332, 3, 1, 4, 0, 0, 1, MSP430OpInfoBase + 170, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD16ri
1066 { 331, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 167, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD16rc
1067 { 330, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 164, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD16mr
1068 { 329, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD16mp
1069 { 328, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD16mn
1070 { 327, 4, 0, 6, 0, 0, 1, MSP430OpInfoBase + 157, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD16mm
1071 { 326, 3, 0, 6, 0, 0, 1, MSP430OpInfoBase + 154, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD16mi
1072 { 325, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 151, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD16mc
1073 { 324, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 147, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UBFX
1074 { 323, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 147, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SBFX
1075 { 322, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_UMIN
1076 { 321, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_UMAX
1077 { 320, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SMIN
1078 { 319, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SMAX
1079 { 318, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_XOR
1080 { 317, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_OR
1081 { 316, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_AND
1082 { 315, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_MUL
1083 { 314, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_ADD
1084 { 313, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMINIMUM
1085 { 312, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMAXIMUM
1086 { 311, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMIN
1087 { 310, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMAX
1088 { 309, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMUL
1089 { 308, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FADD
1090 { 307, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SEQ_FMUL
1091 { 306, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SEQ_FADD
1092 { 305, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UBSANTRAP
1093 { 304, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_DEBUGTRAP
1094 { 303, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRAP
1095 { 302, 3, 0, 0, 0, 0, 0, MSP430OpInfoBase + 57, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BZERO
1096 { 301, 4, 0, 0, 0, 0, 0, MSP430OpInfoBase + 143, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMSET
1097 { 300, 4, 0, 0, 0, 0, 0, MSP430OpInfoBase + 143, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMMOVE
1098 { 299, 3, 0, 0, 0, 0, 0, MSP430OpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMCPY_INLINE
1099 { 298, 4, 0, 0, 0, 0, 0, MSP430OpInfoBase + 143, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMCPY
1100 { 297, 2, 0, 0, 0, 0, 0, MSP430OpInfoBase + 141, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_WRITE_REGISTER
1101 { 296, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_READ_REGISTER
1102 { 295, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FLDEXP
1103 { 294, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FSQRT
1104 { 293, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FMA
1105 { 292, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FREM
1106 { 291, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FDIV
1107 { 290, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FMUL
1108 { 289, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FSUB
1109 { 288, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FADD
1110 { 287, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STACKRESTORE
1111 { 286, 1, 1, 0, 0, 0, 0, MSP430OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STACKSAVE
1112 { 285, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 68, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_DYN_STACKALLOC
1113 { 284, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_JUMP_TABLE
1114 { 283, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BLOCK_ADDR
1115 { 282, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ADDRSPACE_CAST
1116 { 281, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FNEARBYINT
1117 { 280, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FRINT
1118 { 279, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FFLOOR
1119 { 278, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSQRT
1120 { 277, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FTANH
1121 { 276, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSINH
1122 { 275, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCOSH
1123 { 274, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FATAN2
1124 { 273, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FATAN
1125 { 272, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FASIN
1126 { 271, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FACOS
1127 { 270, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FTAN
1128 { 269, 3, 2, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSINCOS
1129 { 268, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSIN
1130 { 267, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCOS
1131 { 266, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCEIL
1132 { 265, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BITREVERSE
1133 { 264, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BSWAP
1134 { 263, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTPOP
1135 { 262, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTLS
1136 { 261, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTLZ_ZERO_UNDEF
1137 { 260, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTLZ
1138 { 259, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTTZ_ZERO_UNDEF
1139 { 258, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTTZ
1140 { 257, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 137, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECTOR_COMPRESS
1141 { 256, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STEP_VECTOR
1142 { 255, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SPLAT_VECTOR
1143 { 254, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 133, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SHUFFLE_VECTOR
1144 { 253, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_EXTRACT_VECTOR_ELT
1145 { 252, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 126, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INSERT_VECTOR_ELT
1146 { 251, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 57, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_EXTRACT_SUBVECTOR
1147 { 250, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 62, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INSERT_SUBVECTOR
1148 { 249, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VSCALE
1149 { 248, 3, 0, 0, 0, 0, 0, MSP430OpInfoBase + 123, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BRJT
1150 { 247, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BR
1151 { 246, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LLROUND
1152 { 245, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LROUND
1153 { 244, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ABS
1154 { 243, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMAX
1155 { 242, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMIN
1156 { 241, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMAX
1157 { 240, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMIN
1158 { 239, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTRMASK
1159 { 238, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTR_ADD
1160 { 237, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SET_ROUNDING
1161 { 236, 1, 1, 0, 0, 0, 0, MSP430OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GET_ROUNDING
1162 { 235, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_RESET_FPMODE
1163 { 234, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SET_FPMODE
1164 { 233, 1, 1, 0, 0, 0, 0, MSP430OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GET_FPMODE
1165 { 232, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_RESET_FPENV
1166 { 231, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SET_FPENV
1167 { 230, 1, 1, 0, 0, 0, 0, MSP430OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GET_FPENV
1168 { 229, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXIMUMNUM
1169 { 228, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINIMUMNUM
1170 { 227, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXIMUM
1171 { 226, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINIMUM
1172 { 225, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXNUM_IEEE
1173 { 224, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINNUM_IEEE
1174 { 223, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXNUM
1175 { 222, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINNUM
1176 { 221, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCANONICALIZE
1177 { 220, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 97, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_IS_FPCLASS
1178 { 219, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCOPYSIGN
1179 { 218, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FABS
1180 { 217, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOUI_SAT
1181 { 216, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOSI_SAT
1182 { 215, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UITOFP
1183 { 214, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SITOFP
1184 { 213, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOUI
1185 { 212, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOSI
1186 { 211, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTRUNC
1187 { 210, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPEXT
1188 { 209, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FNEG
1189 { 208, 3, 2, 0, 0, 0, 0, MSP430OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FFREXP
1190 { 207, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLDEXP
1191 { 206, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLOG10
1192 { 205, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLOG2
1193 { 204, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLOG
1194 { 203, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FEXP10
1195 { 202, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FEXP2
1196 { 201, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FEXP
1197 { 200, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPOWI
1198 { 199, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPOW
1199 { 198, 3, 2, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMODF
1200 { 197, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FREM
1201 { 196, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FDIV
1202 { 195, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAD
1203 { 194, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMA
1204 { 193, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMUL
1205 { 192, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSUB
1206 { 191, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FADD
1207 { 190, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIVFIXSAT
1208 { 189, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIVFIXSAT
1209 { 188, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIVFIX
1210 { 187, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIVFIX
1211 { 186, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULFIXSAT
1212 { 185, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULFIXSAT
1213 { 184, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULFIX
1214 { 183, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULFIX
1215 { 182, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSHLSAT
1216 { 181, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USHLSAT
1217 { 180, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSUBSAT
1218 { 179, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USUBSAT
1219 { 178, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SADDSAT
1220 { 177, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UADDSAT
1221 { 176, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULH
1222 { 175, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULH
1223 { 174, 4, 2, 0, 0, 0, 0, MSP430OpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULO
1224 { 173, 4, 2, 0, 0, 0, 0, MSP430OpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULO
1225 { 172, 5, 2, 0, 0, 0, 0, MSP430OpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSUBE
1226 { 171, 4, 2, 0, 0, 0, 0, MSP430OpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSUBO
1227 { 170, 5, 2, 0, 0, 0, 0, MSP430OpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SADDE
1228 { 169, 4, 2, 0, 0, 0, 0, MSP430OpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SADDO
1229 { 168, 5, 2, 0, 0, 0, 0, MSP430OpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USUBE
1230 { 167, 4, 2, 0, 0, 0, 0, MSP430OpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USUBO
1231 { 166, 5, 2, 0, 0, 0, 0, MSP430OpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UADDE
1232 { 165, 4, 2, 0, 0, 0, 0, MSP430OpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UADDO
1233 { 164, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SELECT
1234 { 163, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 111, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UCMP
1235 { 162, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 111, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SCMP
1236 { 161, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCMP
1237 { 160, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ICMP
1238 { 159, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ROTL
1239 { 158, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ROTR
1240 { 157, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 103, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSHR
1241 { 156, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 103, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSHL
1242 { 155, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASHR
1243 { 154, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LSHR
1244 { 153, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SHL
1245 { 152, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ZEXT
1246 { 151, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SEXT_INREG
1247 { 150, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SEXT
1248 { 149, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 97, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VAARG
1249 { 148, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VASTART
1250 { 147, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCONSTANT
1251 { 146, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONSTANT
1252 { 145, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC_USAT_U
1253 { 144, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC_SSAT_U
1254 { 143, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC_SSAT_S
1255 { 142, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC
1256 { 141, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ANYEXT
1257 { 140, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
1258 { 139, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_INTRINSIC_CONVERGENT
1259 { 138, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_W_SIDE_EFFECTS
1260 { 137, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC
1261 { 136, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INVOKE_REGION_START
1262 { 135, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BRINDIRECT
1263 { 134, 2, 0, 0, 0, 0, 0, MSP430OpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BRCOND
1264 { 133, 4, 0, 0, 0, 0, 0, MSP430OpInfoBase + 93, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PREFETCH
1265 { 132, 2, 0, 0, 0, 0, 0, MSP430OpInfoBase + 20, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FENCE
1266 { 131, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_USUB_SAT
1267 { 130, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_USUB_COND
1268 { 129, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UDEC_WRAP
1269 { 128, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UINC_WRAP
1270 { 127, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMINIMUMNUM
1271 { 126, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMAXIMUMNUM
1272 { 125, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMINIMUM
1273 { 124, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMAXIMUM
1274 { 123, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMIN
1275 { 122, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMAX
1276 { 121, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FSUB
1277 { 120, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FADD
1278 { 119, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UMIN
1279 { 118, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UMAX
1280 { 117, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_MIN
1281 { 116, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_MAX
1282 { 115, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_XOR
1283 { 114, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_OR
1284 { 113, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_NAND
1285 { 112, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_AND
1286 { 111, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_SUB
1287 { 110, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_ADD
1288 { 109, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_XCHG
1289 { 108, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMIC_CMPXCHG
1290 { 107, 5, 2, 0, 0, 0, 0, MSP430OpInfoBase + 81, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
1291 { 106, 5, 1, 0, 0, 0, 0, MSP430OpInfoBase + 76, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_STORE
1292 { 105, 2, 0, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STORE
1293 { 104, 5, 2, 0, 0, 0, 0, MSP430OpInfoBase + 71, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_ZEXTLOAD
1294 { 103, 5, 2, 0, 0, 0, 0, MSP430OpInfoBase + 71, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_SEXTLOAD
1295 { 102, 5, 2, 0, 0, 0, 0, MSP430OpInfoBase + 71, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_LOAD
1296 { 101, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ZEXTLOAD
1297 { 100, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SEXTLOAD
1298 { 99, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LOAD
1299 { 98, 1, 1, 0, 0, 0, 0, MSP430OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_READSTEADYCOUNTER
1300 { 97, 1, 1, 0, 0, 0, 0, MSP430OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_READCYCLECOUNTER
1301 { 96, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_ROUNDEVEN
1302 { 95, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_LLRINT
1303 { 94, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_LRINT
1304 { 93, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_ROUND
1305 { 92, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_TRUNC
1306 { 91, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 68, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_FPTRUNC_ROUND
1307 { 90, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONSTANT_FOLD_BARRIER
1308 { 89, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FREEZE
1309 { 88, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BITCAST
1310 { 87, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTTOPTR
1311 { 86, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTRTOINT
1312 { 85, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONCAT_VECTORS
1313 { 84, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BUILD_VECTOR_TRUNC
1314 { 83, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BUILD_VECTOR
1315 { 82, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MERGE_VALUES
1316 { 81, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 62, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INSERT
1317 { 80, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UNMERGE_VALUES
1318 { 79, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 57, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_EXTRACT
1319 { 78, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONSTANT_POOL
1320 { 77, 5, 1, 0, 0, 0, 0, MSP430OpInfoBase + 52, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTRAUTH_GLOBAL_VALUE
1321 { 76, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GLOBAL_VALUE
1322 { 75, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FRAME_INDEX
1323 { 74, 1, 1, 0, 0, 0, 0, MSP430OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PHI
1324 { 73, 1, 1, 0, 0, 0, 0, MSP430OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_IMPLICIT_DEF
1325 { 72, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SAVGCEIL
1326 { 71, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SAVGFLOOR
1327 { 70, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UAVGCEIL
1328 { 69, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UAVGFLOOR
1329 { 68, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ABDU
1330 { 67, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ABDS
1331 { 66, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_XOR
1332 { 65, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_OR
1333 { 64, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_AND
1334 { 63, 4, 2, 0, 0, 0, 0, MSP430OpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIVREM
1335 { 62, 4, 2, 0, 0, 0, 0, MSP430OpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIVREM
1336 { 61, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UREM
1337 { 60, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SREM
1338 { 59, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIV
1339 { 58, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIV
1340 { 57, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MUL
1341 { 56, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SUB
1342 { 55, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ADD
1343 { 54, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASSERT_ALIGN
1344 { 53, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASSERT_ZEXT
1345 { 52, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASSERT_SEXT
1346 { 51, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_GLUE
1347 { 50, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_LOOP
1348 { 49, 1, 1, 0, 0, 0, 0, MSP430OpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_ANCHOR
1349 { 48, 1, 1, 0, 0, 0, 0, MSP430OpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_ENTRY
1350 { 47, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RELOC_NONE
1351 { 46, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JUMP_TABLE_DEBUG_INFO
1352 { 45, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMBARRIER
1353 { 44, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FAKE_USE
1354 { 43, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ICALL_BRANCH_FUNNEL
1355 { 42, 3, 0, 0, 0, 0, 0, MSP430OpInfoBase + 36, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_13874
1356 { 41, 2, 0, 0, 0, 0, 0, MSP430OpInfoBase + 34, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_13873
1357 { 40, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_TAIL_CALL
1358 { 39, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_FUNCTION_EXIT
1359 { 38, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_RET
1360 { 37, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_FUNCTION_ENTER
1361 { 36, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_OP
1362 { 35, 1, 1, 0, 0, 0, 0, MSP430OpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FAULTING_OP
1363 { 34, 2, 0, 0, 0, 0, 0, MSP430OpInfoBase + 32, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_ESCAPE
1364 { 33, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STATEPOINT
1365 { 32, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 29, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_13872
1366 { 31, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PREALLOCATED_SETUP
1367 { 30, 1, 1, 0, 0, 0, 0, MSP430OpInfoBase + 28, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_13542
1368 { 29, 6, 1, 0, 0, 0, 0, MSP430OpInfoBase + 22, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHPOINT
1369 { 28, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FENTRY_CALL
1370 { 27, 2, 0, 0, 0, 0, 0, MSP430OpInfoBase + 20, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STACKMAP
1371 { 26, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 18, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARITH_FENCE
1372 { 25, 4, 0, 0, 0, 0, 0, MSP430OpInfoBase + 14, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PSEUDO_PROBE
1373 { 24, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LIFETIME_END
1374 { 23, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LIFETIME_START
1375 { 22, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BUNDLE
1376 { 21, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 11, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_LANEMASK
1377 { 20, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY
1378 { 19, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REG_SEQUENCE
1379 { 18, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_LABEL
1380 { 17, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_PHI
1381 { 16, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_INSTR_REF
1382 { 15, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_VALUE_LIST
1383 { 14, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_VALUE
1384 { 13, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_TO_REGCLASS
1385 { 12, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBREG_TO_REG
1386 { 11, 1, 1, 0, 0, 0, 0, MSP430OpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INIT_UNDEF
1387 { 10, 1, 1, 0, 0, 0, 0, MSP430OpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // IMPLICIT_DEF
1388 { 9, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 5, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INSERT_SUBREG
1389 { 8, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTRACT_SUBREG
1390 { 7, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // KILL
1391 { 6, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ANNOTATION_LABEL
1392 { 5, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GC_LABEL
1393 { 4, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EH_LABEL
1394 { 3, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CFI_INSTRUCTION
1395 { 2, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INLINEASM_BR
1396 { 1, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INLINEASM
1397 { 0, 1, 1, 0, 0, 0, 0, MSP430OpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PHI
1398 }, {
1399 /* 0 */
1400 /* 0 */ MSP430::SR,
1401 /* 1 */ MSP430::SR, MSP430::SR,
1402 /* 3 */ MSP430::SP, MSP430::SR,
1403 /* 5 */ MSP430::SP, MSP430::SP, MSP430::SR,
1404 /* 8 */ MSP430::SP, MSP430::R11, MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15, MSP430::SR,
1405 /* 15 */ MSP430::SP, MSP430::SP,
1406 }, {
1407 0
1408 }, {
1409 /* 0 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1410 /* 1 */
1411 /* 1 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1412 /* 2 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1413 /* 5 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1414 /* 9 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1415 /* 11 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1416 /* 14 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1417 /* 18 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) },
1418 /* 20 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1419 /* 22 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1420 /* 28 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1421 /* 29 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1422 /* 32 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1423 /* 34 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1424 /* 36 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1425 /* 39 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1426 /* 42 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1427 /* 45 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1428 /* 49 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1429 /* 50 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1430 /* 52 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1431 /* 57 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1432 /* 60 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1433 /* 62 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1434 /* 66 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1435 /* 68 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1436 /* 71 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1437 /* 76 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1438 /* 81 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1439 /* 86 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1440 /* 90 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1441 /* 93 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1442 /* 97 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1443 /* 100 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1444 /* 103 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1445 /* 107 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1446 /* 111 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1447 /* 114 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1448 /* 119 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1449 /* 123 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1450 /* 126 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
1451 /* 130 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
1452 /* 133 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1453 /* 137 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1454 /* 141 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1455 /* 143 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1456 /* 147 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1457 /* 151 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1458 /* 154 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1459 /* 157 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1460 /* 161 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 },
1461 /* 164 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1462 /* 167 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1463 /* 170 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1464 /* 173 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1465 /* 177 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 },
1466 /* 180 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(1) },
1467 /* 184 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1468 /* 187 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1469 /* 190 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1470 /* 193 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1471 /* 196 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1472 /* 200 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 },
1473 /* 203 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(1) },
1474 /* 207 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1475 /* 210 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1476 /* 212 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1477 /* 215 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 },
1478 /* 217 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1479 /* 219 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1480 /* 221 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1481 /* 223 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1482 /* 226 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 },
1483 /* 228 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1484 /* 230 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1485 /* 232 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 },
1486 /* 233 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(1) },
1487 /* 236 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(1) },
1488 /* 239 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1489 /* 241 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1490 /* 242 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
1491 /* 244 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
1492 /* 246 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1493 /* 250 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1494 /* 254 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1495 /* 257 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1496 }
1497};
1498
1499
1500#ifdef __GNUC__
1501#pragma GCC diagnostic push
1502#pragma GCC diagnostic ignored "-Woverlength-strings"
1503#endif
1504extern const char MSP430InstrNameData[] = {
1505 /* 0 */ "G_FLOG10\000"
1506 /* 9 */ "G_FEXP10\000"
1507 /* 18 */ "G_FLOG2\000"
1508 /* 26 */ "G_FATAN2\000"
1509 /* 35 */ "G_FEXP2\000"
1510 /* 43 */ "Sra16\000"
1511 /* 49 */ "Rrcl16\000"
1512 /* 56 */ "Shl16\000"
1513 /* 62 */ "Srl16\000"
1514 /* 68 */ "Select16\000"
1515 /* 77 */ "Sra8\000"
1516 /* 82 */ "Rrcl8\000"
1517 /* 88 */ "Shl8\000"
1518 /* 93 */ "Srl8\000"
1519 /* 98 */ "MOVZX16rm8\000"
1520 /* 109 */ "MOVZX16rr8\000"
1521 /* 120 */ "Select8\000"
1522 /* 128 */ "G_FMA\000"
1523 /* 134 */ "G_STRICT_FMA\000"
1524 /* 147 */ "G_FSUB\000"
1525 /* 154 */ "G_STRICT_FSUB\000"
1526 /* 168 */ "G_ATOMICRMW_FSUB\000"
1527 /* 185 */ "G_SUB\000"
1528 /* 191 */ "G_ATOMICRMW_SUB\000"
1529 /* 207 */ "JCC\000"
1530 /* 211 */ "G_INTRINSIC\000"
1531 /* 223 */ "G_FPTRUNC\000"
1532 /* 233 */ "G_INTRINSIC_TRUNC\000"
1533 /* 251 */ "G_TRUNC\000"
1534 /* 259 */ "G_BUILD_VECTOR_TRUNC\000"
1535 /* 280 */ "G_DYN_STACKALLOC\000"
1536 /* 297 */ "G_FMAD\000"
1537 /* 304 */ "G_INDEXED_SEXTLOAD\000"
1538 /* 323 */ "G_SEXTLOAD\000"
1539 /* 334 */ "G_INDEXED_ZEXTLOAD\000"
1540 /* 353 */ "G_ZEXTLOAD\000"
1541 /* 364 */ "G_INDEXED_LOAD\000"
1542 /* 379 */ "G_LOAD\000"
1543 /* 386 */ "G_VECREDUCE_FADD\000"
1544 /* 403 */ "G_FADD\000"
1545 /* 410 */ "G_VECREDUCE_SEQ_FADD\000"
1546 /* 431 */ "G_STRICT_FADD\000"
1547 /* 445 */ "G_ATOMICRMW_FADD\000"
1548 /* 462 */ "G_VECREDUCE_ADD\000"
1549 /* 478 */ "G_ADD\000"
1550 /* 484 */ "G_PTR_ADD\000"
1551 /* 494 */ "G_ATOMICRMW_ADD\000"
1552 /* 510 */ "G_ATOMICRMW_NAND\000"
1553 /* 527 */ "G_VECREDUCE_AND\000"
1554 /* 543 */ "G_AND\000"
1555 /* 549 */ "G_ATOMICRMW_AND\000"
1556 /* 565 */ "LIFETIME_END\000"
1557 /* 578 */ "G_BRCOND\000"
1558 /* 587 */ "G_ATOMICRMW_USUB_COND\000"
1559 /* 609 */ "G_LLROUND\000"
1560 /* 619 */ "G_LROUND\000"
1561 /* 628 */ "G_INTRINSIC_ROUND\000"
1562 /* 646 */ "G_INTRINSIC_FPTRUNC_ROUND\000"
1563 /* 672 */ "LOAD_STACK_GUARD\000"
1564 /* 689 */ "PSEUDO_PROBE\000"
1565 /* 702 */ "G_SSUBE\000"
1566 /* 710 */ "G_USUBE\000"
1567 /* 718 */ "G_FENCE\000"
1568 /* 726 */ "ARITH_FENCE\000"
1569 /* 738 */ "REG_SEQUENCE\000"
1570 /* 751 */ "G_SADDE\000"
1571 /* 759 */ "G_UADDE\000"
1572 /* 767 */ "G_GET_FPMODE\000"
1573 /* 780 */ "G_RESET_FPMODE\000"
1574 /* 795 */ "G_SET_FPMODE\000"
1575 /* 808 */ "G_FMINNUM_IEEE\000"
1576 /* 823 */ "G_FMAXNUM_IEEE\000"
1577 /* 838 */ "G_VSCALE\000"
1578 /* 847 */ "G_JUMP_TABLE\000"
1579 /* 860 */ "BUNDLE\000"
1580 /* 867 */ "G_MEMCPY_INLINE\000"
1581 /* 883 */ "RELOC_NONE\000"
1582 /* 894 */ "LOCAL_ESCAPE\000"
1583 /* 907 */ "G_STACKRESTORE\000"
1584 /* 922 */ "G_INDEXED_STORE\000"
1585 /* 938 */ "G_STORE\000"
1586 /* 946 */ "G_BITREVERSE\000"
1587 /* 959 */ "FAKE_USE\000"
1588 /* 968 */ "DBG_VALUE\000"
1589 /* 978 */ "G_GLOBAL_VALUE\000"
1590 /* 993 */ "G_PTRAUTH_GLOBAL_VALUE\000"
1591 /* 1016 */ "CONVERGENCECTRL_GLUE\000"
1592 /* 1037 */ "G_STACKSAVE\000"
1593 /* 1049 */ "G_MEMMOVE\000"
1594 /* 1059 */ "G_FREEZE\000"
1595 /* 1068 */ "G_FCANONICALIZE\000"
1596 /* 1084 */ "G_FMODF\000"
1597 /* 1092 */ "G_CTLZ_ZERO_UNDEF\000"
1598 /* 1110 */ "G_CTTZ_ZERO_UNDEF\000"
1599 /* 1128 */ "INIT_UNDEF\000"
1600 /* 1139 */ "G_IMPLICIT_DEF\000"
1601 /* 1154 */ "DBG_INSTR_REF\000"
1602 /* 1168 */ "G_FNEG\000"
1603 /* 1175 */ "EXTRACT_SUBREG\000"
1604 /* 1190 */ "INSERT_SUBREG\000"
1605 /* 1204 */ "G_SEXT_INREG\000"
1606 /* 1217 */ "SUBREG_TO_REG\000"
1607 /* 1231 */ "G_ATOMIC_CMPXCHG\000"
1608 /* 1248 */ "G_ATOMICRMW_XCHG\000"
1609 /* 1265 */ "G_GET_ROUNDING\000"
1610 /* 1280 */ "G_SET_ROUNDING\000"
1611 /* 1295 */ "G_FLOG\000"
1612 /* 1302 */ "G_VAARG\000"
1613 /* 1310 */ "PREALLOCATED_ARG\000"
1614 /* 1327 */ "G_PREFETCH\000"
1615 /* 1338 */ "G_SMULH\000"
1616 /* 1346 */ "G_UMULH\000"
1617 /* 1354 */ "G_FTANH\000"
1618 /* 1362 */ "G_FSINH\000"
1619 /* 1370 */ "G_FCOSH\000"
1620 /* 1378 */ "DBG_PHI\000"
1621 /* 1386 */ "G_FPTOSI\000"
1622 /* 1395 */ "RETI\000"
1623 /* 1400 */ "G_FPTOUI\000"
1624 /* 1409 */ "G_FPOWI\000"
1625 /* 1417 */ "COPY_LANEMASK\000"
1626 /* 1431 */ "G_PTRMASK\000"
1627 /* 1441 */ "GC_LABEL\000"
1628 /* 1450 */ "DBG_LABEL\000"
1629 /* 1460 */ "EH_LABEL\000"
1630 /* 1469 */ "ANNOTATION_LABEL\000"
1631 /* 1486 */ "ICALL_BRANCH_FUNNEL\000"
1632 /* 1506 */ "G_FSHL\000"
1633 /* 1513 */ "G_SHL\000"
1634 /* 1519 */ "G_FCEIL\000"
1635 /* 1527 */ "G_SAVGCEIL\000"
1636 /* 1538 */ "G_UAVGCEIL\000"
1637 /* 1549 */ "PATCHABLE_TAIL_CALL\000"
1638 /* 1569 */ "PATCHABLE_TYPED_EVENT_CALL\000"
1639 /* 1596 */ "PATCHABLE_EVENT_CALL\000"
1640 /* 1617 */ "FENTRY_CALL\000"
1641 /* 1629 */ "KILL\000"
1642 /* 1634 */ "G_CONSTANT_POOL\000"
1643 /* 1650 */ "G_ROTL\000"
1644 /* 1657 */ "G_VECREDUCE_FMUL\000"
1645 /* 1674 */ "G_FMUL\000"
1646 /* 1681 */ "G_VECREDUCE_SEQ_FMUL\000"
1647 /* 1702 */ "G_STRICT_FMUL\000"
1648 /* 1716 */ "G_VECREDUCE_MUL\000"
1649 /* 1732 */ "G_MUL\000"
1650 /* 1738 */ "G_FREM\000"
1651 /* 1745 */ "G_STRICT_FREM\000"
1652 /* 1759 */ "G_SREM\000"
1653 /* 1766 */ "G_UREM\000"
1654 /* 1773 */ "G_SDIVREM\000"
1655 /* 1783 */ "G_UDIVREM\000"
1656 /* 1793 */ "INLINEASM\000"
1657 /* 1803 */ "G_VECREDUCE_FMINIMUM\000"
1658 /* 1824 */ "G_FMINIMUM\000"
1659 /* 1835 */ "G_ATOMICRMW_FMINIMUM\000"
1660 /* 1856 */ "G_VECREDUCE_FMAXIMUM\000"
1661 /* 1877 */ "G_FMAXIMUM\000"
1662 /* 1888 */ "G_ATOMICRMW_FMAXIMUM\000"
1663 /* 1909 */ "G_FMINIMUMNUM\000"
1664 /* 1923 */ "G_ATOMICRMW_FMINIMUMNUM\000"
1665 /* 1947 */ "G_FMAXIMUMNUM\000"
1666 /* 1961 */ "G_ATOMICRMW_FMAXIMUMNUM\000"
1667 /* 1985 */ "G_FMINNUM\000"
1668 /* 1995 */ "G_FMAXNUM\000"
1669 /* 2005 */ "G_FATAN\000"
1670 /* 2013 */ "G_FTAN\000"
1671 /* 2020 */ "G_INTRINSIC_ROUNDEVEN\000"
1672 /* 2042 */ "G_ASSERT_ALIGN\000"
1673 /* 2057 */ "G_FCOPYSIGN\000"
1674 /* 2069 */ "G_VECREDUCE_FMIN\000"
1675 /* 2086 */ "G_ATOMICRMW_FMIN\000"
1676 /* 2103 */ "G_VECREDUCE_SMIN\000"
1677 /* 2120 */ "G_SMIN\000"
1678 /* 2127 */ "G_VECREDUCE_UMIN\000"
1679 /* 2144 */ "G_UMIN\000"
1680 /* 2151 */ "G_ATOMICRMW_UMIN\000"
1681 /* 2168 */ "G_ATOMICRMW_MIN\000"
1682 /* 2184 */ "G_FASIN\000"
1683 /* 2192 */ "G_FSIN\000"
1684 /* 2199 */ "CFI_INSTRUCTION\000"
1685 /* 2215 */ "ADJCALLSTACKDOWN\000"
1686 /* 2232 */ "G_SSUBO\000"
1687 /* 2240 */ "G_USUBO\000"
1688 /* 2248 */ "G_SADDO\000"
1689 /* 2256 */ "G_UADDO\000"
1690 /* 2264 */ "JUMP_TABLE_DEBUG_INFO\000"
1691 /* 2286 */ "G_SMULO\000"
1692 /* 2294 */ "G_UMULO\000"
1693 /* 2302 */ "G_BZERO\000"
1694 /* 2310 */ "STACKMAP\000"
1695 /* 2319 */ "G_DEBUGTRAP\000"
1696 /* 2331 */ "G_UBSANTRAP\000"
1697 /* 2343 */ "G_TRAP\000"
1698 /* 2350 */ "G_ATOMICRMW_UDEC_WRAP\000"
1699 /* 2372 */ "G_ATOMICRMW_UINC_WRAP\000"
1700 /* 2394 */ "G_BSWAP\000"
1701 /* 2402 */ "G_SITOFP\000"
1702 /* 2411 */ "G_UITOFP\000"
1703 /* 2420 */ "G_FCMP\000"
1704 /* 2427 */ "G_ICMP\000"
1705 /* 2434 */ "G_SCMP\000"
1706 /* 2441 */ "G_UCMP\000"
1707 /* 2448 */ "JMP\000"
1708 /* 2452 */ "CONVERGENCECTRL_LOOP\000"
1709 /* 2473 */ "G_CTPOP\000"
1710 /* 2481 */ "PATCHABLE_OP\000"
1711 /* 2494 */ "FAULTING_OP\000"
1712 /* 2506 */ "ADJCALLSTACKUP\000"
1713 /* 2521 */ "PREALLOCATED_SETUP\000"
1714 /* 2540 */ "G_FLDEXP\000"
1715 /* 2549 */ "G_STRICT_FLDEXP\000"
1716 /* 2565 */ "G_FEXP\000"
1717 /* 2572 */ "G_FFREXP\000"
1718 /* 2581 */ "G_BR\000"
1719 /* 2586 */ "INLINEASM_BR\000"
1720 /* 2599 */ "G_BLOCK_ADDR\000"
1721 /* 2612 */ "MEMBARRIER\000"
1722 /* 2623 */ "G_CONSTANT_FOLD_BARRIER\000"
1723 /* 2647 */ "PATCHABLE_FUNCTION_ENTER\000"
1724 /* 2672 */ "G_READCYCLECOUNTER\000"
1725 /* 2691 */ "G_READSTEADYCOUNTER\000"
1726 /* 2711 */ "G_READ_REGISTER\000"
1727 /* 2727 */ "G_WRITE_REGISTER\000"
1728 /* 2744 */ "G_ASHR\000"
1729 /* 2751 */ "G_FSHR\000"
1730 /* 2758 */ "G_LSHR\000"
1731 /* 2765 */ "CONVERGENCECTRL_ANCHOR\000"
1732 /* 2788 */ "G_FFLOOR\000"
1733 /* 2797 */ "G_SAVGFLOOR\000"
1734 /* 2809 */ "G_UAVGFLOOR\000"
1735 /* 2821 */ "G_EXTRACT_SUBVECTOR\000"
1736 /* 2841 */ "G_INSERT_SUBVECTOR\000"
1737 /* 2860 */ "G_BUILD_VECTOR\000"
1738 /* 2875 */ "G_SHUFFLE_VECTOR\000"
1739 /* 2892 */ "G_STEP_VECTOR\000"
1740 /* 2906 */ "G_SPLAT_VECTOR\000"
1741 /* 2921 */ "G_VECREDUCE_XOR\000"
1742 /* 2937 */ "G_XOR\000"
1743 /* 2943 */ "G_ATOMICRMW_XOR\000"
1744 /* 2959 */ "G_VECREDUCE_OR\000"
1745 /* 2974 */ "G_OR\000"
1746 /* 2979 */ "G_ATOMICRMW_OR\000"
1747 /* 2994 */ "G_ROTR\000"
1748 /* 3001 */ "G_INTTOPTR\000"
1749 /* 3012 */ "G_FABS\000"
1750 /* 3019 */ "G_ABS\000"
1751 /* 3025 */ "G_ABDS\000"
1752 /* 3032 */ "G_UNMERGE_VALUES\000"
1753 /* 3049 */ "G_MERGE_VALUES\000"
1754 /* 3064 */ "G_CTLS\000"
1755 /* 3071 */ "G_FACOS\000"
1756 /* 3079 */ "G_FCOS\000"
1757 /* 3086 */ "G_FSINCOS\000"
1758 /* 3096 */ "G_CONCAT_VECTORS\000"
1759 /* 3113 */ "COPY_TO_REGCLASS\000"
1760 /* 3130 */ "G_IS_FPCLASS\000"
1761 /* 3143 */ "G_ATOMIC_CMPXCHG_WITH_SUCCESS\000"
1762 /* 3173 */ "G_VECTOR_COMPRESS\000"
1763 /* 3191 */ "G_INTRINSIC_W_SIDE_EFFECTS\000"
1764 /* 3218 */ "G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS\000"
1765 /* 3256 */ "G_TRUNC_SSAT_S\000"
1766 /* 3271 */ "G_SSUBSAT\000"
1767 /* 3281 */ "G_USUBSAT\000"
1768 /* 3291 */ "G_SADDSAT\000"
1769 /* 3301 */ "G_UADDSAT\000"
1770 /* 3311 */ "G_SSHLSAT\000"
1771 /* 3321 */ "G_USHLSAT\000"
1772 /* 3331 */ "G_SMULFIXSAT\000"
1773 /* 3344 */ "G_UMULFIXSAT\000"
1774 /* 3357 */ "G_SDIVFIXSAT\000"
1775 /* 3370 */ "G_UDIVFIXSAT\000"
1776 /* 3383 */ "G_ATOMICRMW_USUB_SAT\000"
1777 /* 3404 */ "G_FPTOSI_SAT\000"
1778 /* 3417 */ "G_FPTOUI_SAT\000"
1779 /* 3430 */ "G_EXTRACT\000"
1780 /* 3440 */ "G_SELECT\000"
1781 /* 3449 */ "G_BRINDIRECT\000"
1782 /* 3462 */ "PATCHABLE_RET\000"
1783 /* 3476 */ "G_MEMSET\000"
1784 /* 3485 */ "PATCHABLE_FUNCTION_EXIT\000"
1785 /* 3509 */ "G_BRJT\000"
1786 /* 3516 */ "G_EXTRACT_VECTOR_ELT\000"
1787 /* 3537 */ "G_INSERT_VECTOR_ELT\000"
1788 /* 3557 */ "G_FCONSTANT\000"
1789 /* 3569 */ "G_CONSTANT\000"
1790 /* 3580 */ "G_INTRINSIC_CONVERGENT\000"
1791 /* 3603 */ "STATEPOINT\000"
1792 /* 3614 */ "PATCHPOINT\000"
1793 /* 3625 */ "G_PTRTOINT\000"
1794 /* 3636 */ "G_FRINT\000"
1795 /* 3644 */ "G_INTRINSIC_LLRINT\000"
1796 /* 3663 */ "G_INTRINSIC_LRINT\000"
1797 /* 3681 */ "G_FNEARBYINT\000"
1798 /* 3694 */ "G_VASTART\000"
1799 /* 3704 */ "LIFETIME_START\000"
1800 /* 3719 */ "G_INVOKE_REGION_START\000"
1801 /* 3741 */ "G_INSERT\000"
1802 /* 3750 */ "G_FSQRT\000"
1803 /* 3758 */ "G_STRICT_FSQRT\000"
1804 /* 3773 */ "G_BITCAST\000"
1805 /* 3783 */ "G_ADDRSPACE_CAST\000"
1806 /* 3800 */ "DBG_VALUE_LIST\000"
1807 /* 3815 */ "G_FPEXT\000"
1808 /* 3823 */ "G_SEXT\000"
1809 /* 3830 */ "G_ASSERT_SEXT\000"
1810 /* 3844 */ "G_ANYEXT\000"
1811 /* 3853 */ "G_ZEXT\000"
1812 /* 3860 */ "G_ASSERT_ZEXT\000"
1813 /* 3874 */ "G_ABDU\000"
1814 /* 3881 */ "G_TRUNC_SSAT_U\000"
1815 /* 3896 */ "G_TRUNC_USAT_U\000"
1816 /* 3911 */ "G_FDIV\000"
1817 /* 3918 */ "G_STRICT_FDIV\000"
1818 /* 3932 */ "G_SDIV\000"
1819 /* 3939 */ "G_UDIV\000"
1820 /* 3946 */ "G_GET_FPENV\000"
1821 /* 3958 */ "G_RESET_FPENV\000"
1822 /* 3972 */ "G_SET_FPENV\000"
1823 /* 3984 */ "G_FPOW\000"
1824 /* 3991 */ "G_VECREDUCE_FMAX\000"
1825 /* 4008 */ "G_ATOMICRMW_FMAX\000"
1826 /* 4025 */ "G_VECREDUCE_SMAX\000"
1827 /* 4042 */ "G_SMAX\000"
1828 /* 4049 */ "G_VECREDUCE_UMAX\000"
1829 /* 4066 */ "G_UMAX\000"
1830 /* 4073 */ "G_ATOMICRMW_UMAX\000"
1831 /* 4090 */ "G_ATOMICRMW_MAX\000"
1832 /* 4106 */ "G_FRAME_INDEX\000"
1833 /* 4120 */ "G_SBFX\000"
1834 /* 4127 */ "G_UBFX\000"
1835 /* 4134 */ "G_SMULFIX\000"
1836 /* 4144 */ "G_UMULFIX\000"
1837 /* 4154 */ "G_SDIVFIX\000"
1838 /* 4164 */ "G_UDIVFIX\000"
1839 /* 4174 */ "G_MEMCPY\000"
1840 /* 4183 */ "COPY\000"
1841 /* 4188 */ "CONVERGENCECTRL_ENTRY\000"
1842 /* 4210 */ "G_CTLZ\000"
1843 /* 4217 */ "G_CTTZ\000"
1844 /* 4224 */ "PUSH16c\000"
1845 /* 4232 */ "SUB16mc\000"
1846 /* 4240 */ "SUBC16mc\000"
1847 /* 4249 */ "ADDC16mc\000"
1848 /* 4258 */ "BIC16mc\000"
1849 /* 4266 */ "DADD16mc\000"
1850 /* 4275 */ "AND16mc\000"
1851 /* 4283 */ "CMP16mc\000"
1852 /* 4291 */ "XOR16mc\000"
1853 /* 4299 */ "BIS16mc\000"
1854 /* 4307 */ "BIT16mc\000"
1855 /* 4315 */ "MOV16mc\000"
1856 /* 4323 */ "SUB8mc\000"
1857 /* 4330 */ "SUBC8mc\000"
1858 /* 4338 */ "ADDC8mc\000"
1859 /* 4346 */ "BIC8mc\000"
1860 /* 4353 */ "DADD8mc\000"
1861 /* 4361 */ "AND8mc\000"
1862 /* 4368 */ "CMP8mc\000"
1863 /* 4375 */ "XOR8mc\000"
1864 /* 4382 */ "BIS8mc\000"
1865 /* 4389 */ "BIT8mc\000"
1866 /* 4396 */ "MOV8mc\000"
1867 /* 4403 */ "SUB16rc\000"
1868 /* 4411 */ "SUBC16rc\000"
1869 /* 4420 */ "ADDC16rc\000"
1870 /* 4429 */ "BIC16rc\000"
1871 /* 4437 */ "DADD16rc\000"
1872 /* 4446 */ "AND16rc\000"
1873 /* 4454 */ "CMP16rc\000"
1874 /* 4462 */ "XOR16rc\000"
1875 /* 4470 */ "BIS16rc\000"
1876 /* 4478 */ "BIT16rc\000"
1877 /* 4486 */ "MOV16rc\000"
1878 /* 4494 */ "SUB8rc\000"
1879 /* 4501 */ "SUBC8rc\000"
1880 /* 4509 */ "ADDC8rc\000"
1881 /* 4517 */ "BIC8rc\000"
1882 /* 4524 */ "DADD8rc\000"
1883 /* 4532 */ "AND8rc\000"
1884 /* 4539 */ "CMP8rc\000"
1885 /* 4546 */ "XOR8rc\000"
1886 /* 4553 */ "BIS8rc\000"
1887 /* 4560 */ "BIT8rc\000"
1888 /* 4567 */ "MOV8rc\000"
1889 /* 4574 */ "ADDframe\000"
1890 /* 4583 */ "PUSH16i\000"
1891 /* 4591 */ "Bi\000"
1892 /* 4594 */ "CALLi\000"
1893 /* 4600 */ "SUB16mi\000"
1894 /* 4608 */ "SUBC16mi\000"
1895 /* 4617 */ "ADDC16mi\000"
1896 /* 4626 */ "BIC16mi\000"
1897 /* 4634 */ "DADD16mi\000"
1898 /* 4643 */ "AND16mi\000"
1899 /* 4651 */ "CMP16mi\000"
1900 /* 4659 */ "XOR16mi\000"
1901 /* 4667 */ "BIS16mi\000"
1902 /* 4675 */ "BIT16mi\000"
1903 /* 4683 */ "MOV16mi\000"
1904 /* 4691 */ "SUB8mi\000"
1905 /* 4698 */ "SUBC8mi\000"
1906 /* 4706 */ "ADDC8mi\000"
1907 /* 4714 */ "BIC8mi\000"
1908 /* 4721 */ "DADD8mi\000"
1909 /* 4729 */ "AND8mi\000"
1910 /* 4736 */ "CMP8mi\000"
1911 /* 4743 */ "XOR8mi\000"
1912 /* 4750 */ "BIS8mi\000"
1913 /* 4757 */ "BIT8mi\000"
1914 /* 4764 */ "MOV8mi\000"
1915 /* 4771 */ "SUB16ri\000"
1916 /* 4779 */ "SUBC16ri\000"
1917 /* 4788 */ "ADDC16ri\000"
1918 /* 4797 */ "BIC16ri\000"
1919 /* 4805 */ "DADD16ri\000"
1920 /* 4814 */ "AND16ri\000"
1921 /* 4822 */ "CMP16ri\000"
1922 /* 4830 */ "XOR16ri\000"
1923 /* 4838 */ "BIS16ri\000"
1924 /* 4846 */ "BIT16ri\000"
1925 /* 4854 */ "MOV16ri\000"
1926 /* 4862 */ "SUB8ri\000"
1927 /* 4869 */ "SUBC8ri\000"
1928 /* 4877 */ "ADDC8ri\000"
1929 /* 4885 */ "BIC8ri\000"
1930 /* 4892 */ "DADD8ri\000"
1931 /* 4900 */ "AND8ri\000"
1932 /* 4907 */ "CMP8ri\000"
1933 /* 4914 */ "XOR8ri\000"
1934 /* 4921 */ "BIS8ri\000"
1935 /* 4928 */ "BIT8ri\000"
1936 /* 4935 */ "MOV8ri\000"
1937 /* 4942 */ "RRA16m\000"
1938 /* 4949 */ "SWPB16m\000"
1939 /* 4957 */ "RRC16m\000"
1940 /* 4964 */ "SEXT16m\000"
1941 /* 4972 */ "RRA8m\000"
1942 /* 4978 */ "RRC8m\000"
1943 /* 4984 */ "Bm\000"
1944 /* 4987 */ "CALLm\000"
1945 /* 4993 */ "SUB16mm\000"
1946 /* 5001 */ "SUBC16mm\000"
1947 /* 5010 */ "ADDC16mm\000"
1948 /* 5019 */ "BIC16mm\000"
1949 /* 5027 */ "DADD16mm\000"
1950 /* 5036 */ "AND16mm\000"
1951 /* 5044 */ "CMP16mm\000"
1952 /* 5052 */ "XOR16mm\000"
1953 /* 5060 */ "BIS16mm\000"
1954 /* 5068 */ "BIT16mm\000"
1955 /* 5076 */ "MOV16mm\000"
1956 /* 5084 */ "SUB8mm\000"
1957 /* 5091 */ "SUBC8mm\000"
1958 /* 5099 */ "ADDC8mm\000"
1959 /* 5107 */ "BIC8mm\000"
1960 /* 5114 */ "DADD8mm\000"
1961 /* 5122 */ "AND8mm\000"
1962 /* 5129 */ "CMP8mm\000"
1963 /* 5136 */ "XOR8mm\000"
1964 /* 5143 */ "BIS8mm\000"
1965 /* 5150 */ "BIT8mm\000"
1966 /* 5157 */ "MOV8mm\000"
1967 /* 5164 */ "SUB16rm\000"
1968 /* 5172 */ "SUBC16rm\000"
1969 /* 5181 */ "ADDC16rm\000"
1970 /* 5190 */ "BIC16rm\000"
1971 /* 5198 */ "DADD16rm\000"
1972 /* 5207 */ "AND16rm\000"
1973 /* 5215 */ "CMP16rm\000"
1974 /* 5223 */ "XOR16rm\000"
1975 /* 5231 */ "BIS16rm\000"
1976 /* 5239 */ "BIT16rm\000"
1977 /* 5247 */ "MOV16rm\000"
1978 /* 5255 */ "SUB8rm\000"
1979 /* 5262 */ "SUBC8rm\000"
1980 /* 5270 */ "ADDC8rm\000"
1981 /* 5278 */ "BIC8rm\000"
1982 /* 5285 */ "DADD8rm\000"
1983 /* 5293 */ "AND8rm\000"
1984 /* 5300 */ "CMP8rm\000"
1985 /* 5307 */ "XOR8rm\000"
1986 /* 5314 */ "BIS8rm\000"
1987 /* 5321 */ "BIT8rm\000"
1988 /* 5328 */ "MOV8rm\000"
1989 /* 5335 */ "RRA16n\000"
1990 /* 5342 */ "SWPB16n\000"
1991 /* 5350 */ "RRC16n\000"
1992 /* 5357 */ "SEXT16n\000"
1993 /* 5365 */ "RRA8n\000"
1994 /* 5371 */ "RRC8n\000"
1995 /* 5377 */ "CALLn\000"
1996 /* 5383 */ "SUB16mn\000"
1997 /* 5391 */ "SUBC16mn\000"
1998 /* 5400 */ "ADDC16mn\000"
1999 /* 5409 */ "BIC16mn\000"
2000 /* 5417 */ "DADD16mn\000"
2001 /* 5426 */ "AND16mn\000"
2002 /* 5434 */ "CMP16mn\000"
2003 /* 5442 */ "XOR16mn\000"
2004 /* 5450 */ "BIS16mn\000"
2005 /* 5458 */ "BIT16mn\000"
2006 /* 5466 */ "MOV16mn\000"
2007 /* 5474 */ "SUB8mn\000"
2008 /* 5481 */ "SUBC8mn\000"
2009 /* 5489 */ "ADDC8mn\000"
2010 /* 5497 */ "BIC8mn\000"
2011 /* 5504 */ "DADD8mn\000"
2012 /* 5512 */ "AND8mn\000"
2013 /* 5519 */ "CMP8mn\000"
2014 /* 5526 */ "XOR8mn\000"
2015 /* 5533 */ "BIS8mn\000"
2016 /* 5540 */ "BIT8mn\000"
2017 /* 5547 */ "MOV8mn\000"
2018 /* 5554 */ "SUB16rn\000"
2019 /* 5562 */ "SUBC16rn\000"
2020 /* 5571 */ "ADDC16rn\000"
2021 /* 5580 */ "BIC16rn\000"
2022 /* 5588 */ "DADD16rn\000"
2023 /* 5597 */ "AND16rn\000"
2024 /* 5605 */ "CMP16rn\000"
2025 /* 5613 */ "XOR16rn\000"
2026 /* 5621 */ "BIS16rn\000"
2027 /* 5629 */ "BIT16rn\000"
2028 /* 5637 */ "MOV16rn\000"
2029 /* 5645 */ "SUB8rn\000"
2030 /* 5652 */ "SUBC8rn\000"
2031 /* 5660 */ "ADDC8rn\000"
2032 /* 5668 */ "BIC8rn\000"
2033 /* 5675 */ "DADD8rn\000"
2034 /* 5683 */ "AND8rn\000"
2035 /* 5690 */ "CMP8rn\000"
2036 /* 5697 */ "XOR8rn\000"
2037 /* 5704 */ "BIS8rn\000"
2038 /* 5711 */ "BIT8rn\000"
2039 /* 5718 */ "MOV8rn\000"
2040 /* 5725 */ "RRA16p\000"
2041 /* 5732 */ "SWPB16p\000"
2042 /* 5740 */ "RRC16p\000"
2043 /* 5747 */ "SEXT16p\000"
2044 /* 5755 */ "RRA8p\000"
2045 /* 5761 */ "RRC8p\000"
2046 /* 5767 */ "CALLp\000"
2047 /* 5773 */ "SUB16mp\000"
2048 /* 5781 */ "SUBC16mp\000"
2049 /* 5790 */ "ADDC16mp\000"
2050 /* 5799 */ "BIC16mp\000"
2051 /* 5807 */ "DADD16mp\000"
2052 /* 5816 */ "AND16mp\000"
2053 /* 5824 */ "CMP16mp\000"
2054 /* 5832 */ "XOR16mp\000"
2055 /* 5840 */ "BIS16mp\000"
2056 /* 5848 */ "BIT16mp\000"
2057 /* 5856 */ "SUB8mp\000"
2058 /* 5863 */ "SUBC8mp\000"
2059 /* 5871 */ "ADDC8mp\000"
2060 /* 5879 */ "BIC8mp\000"
2061 /* 5886 */ "DADD8mp\000"
2062 /* 5894 */ "AND8mp\000"
2063 /* 5901 */ "CMP8mp\000"
2064 /* 5908 */ "XOR8mp\000"
2065 /* 5915 */ "BIS8mp\000"
2066 /* 5922 */ "BIT8mp\000"
2067 /* 5929 */ "SUB16rp\000"
2068 /* 5937 */ "SUBC16rp\000"
2069 /* 5946 */ "ADDC16rp\000"
2070 /* 5955 */ "BIC16rp\000"
2071 /* 5963 */ "DADD16rp\000"
2072 /* 5972 */ "AND16rp\000"
2073 /* 5980 */ "CMP16rp\000"
2074 /* 5988 */ "XOR16rp\000"
2075 /* 5996 */ "BIS16rp\000"
2076 /* 6004 */ "BIT16rp\000"
2077 /* 6012 */ "MOV16rp\000"
2078 /* 6020 */ "SUB8rp\000"
2079 /* 6027 */ "SUBC8rp\000"
2080 /* 6035 */ "ADDC8rp\000"
2081 /* 6043 */ "BIC8rp\000"
2082 /* 6050 */ "DADD8rp\000"
2083 /* 6058 */ "AND8rp\000"
2084 /* 6065 */ "CMP8rp\000"
2085 /* 6072 */ "XOR8rp\000"
2086 /* 6079 */ "BIS8rp\000"
2087 /* 6086 */ "BIT8rp\000"
2088 /* 6093 */ "MOV8rp\000"
2089 /* 6100 */ "RRA16r\000"
2090 /* 6107 */ "SWPB16r\000"
2091 /* 6115 */ "RRC16r\000"
2092 /* 6122 */ "PUSH16r\000"
2093 /* 6130 */ "POP16r\000"
2094 /* 6137 */ "SEXT16r\000"
2095 /* 6145 */ "ZEXT16r\000"
2096 /* 6153 */ "RRA8r\000"
2097 /* 6159 */ "RRC8r\000"
2098 /* 6165 */ "PUSH8r\000"
2099 /* 6172 */ "Br\000"
2100 /* 6175 */ "CALLr\000"
2101 /* 6181 */ "SUB16mr\000"
2102 /* 6189 */ "SUBC16mr\000"
2103 /* 6198 */ "ADDC16mr\000"
2104 /* 6207 */ "BIC16mr\000"
2105 /* 6215 */ "DADD16mr\000"
2106 /* 6224 */ "AND16mr\000"
2107 /* 6232 */ "CMP16mr\000"
2108 /* 6240 */ "XOR16mr\000"
2109 /* 6248 */ "BIS16mr\000"
2110 /* 6256 */ "BIT16mr\000"
2111 /* 6264 */ "MOV16mr\000"
2112 /* 6272 */ "SUB8mr\000"
2113 /* 6279 */ "SUBC8mr\000"
2114 /* 6287 */ "ADDC8mr\000"
2115 /* 6295 */ "BIC8mr\000"
2116 /* 6302 */ "DADD8mr\000"
2117 /* 6310 */ "AND8mr\000"
2118 /* 6317 */ "CMP8mr\000"
2119 /* 6324 */ "XOR8mr\000"
2120 /* 6331 */ "BIS8mr\000"
2121 /* 6338 */ "BIT8mr\000"
2122 /* 6345 */ "MOV8mr\000"
2123 /* 6352 */ "SUB16rr\000"
2124 /* 6360 */ "SUBC16rr\000"
2125 /* 6369 */ "ADDC16rr\000"
2126 /* 6378 */ "BIC16rr\000"
2127 /* 6386 */ "DADD16rr\000"
2128 /* 6395 */ "AND16rr\000"
2129 /* 6403 */ "CMP16rr\000"
2130 /* 6411 */ "XOR16rr\000"
2131 /* 6419 */ "BIS16rr\000"
2132 /* 6427 */ "BIT16rr\000"
2133 /* 6435 */ "MOV16rr\000"
2134 /* 6443 */ "SUB8rr\000"
2135 /* 6450 */ "SUBC8rr\000"
2136 /* 6458 */ "ADDC8rr\000"
2137 /* 6466 */ "BIC8rr\000"
2138 /* 6473 */ "DADD8rr\000"
2139 /* 6481 */ "AND8rr\000"
2140 /* 6488 */ "CMP8rr\000"
2141 /* 6495 */ "XOR8rr\000"
2142 /* 6502 */ "BIS8rr\000"
2143 /* 6509 */ "BIT8rr\000"
2144 /* 6516 */ "MOV8rr\000"
2145};
2146#ifdef __GNUC__
2147#pragma GCC diagnostic pop
2148#endif
2149
2150extern const unsigned MSP430InstrNameIndices[] = {
2151 1382U, 1793U, 2586U, 2199U, 1460U, 1441U, 1469U, 1629U,
2152 1175U, 1190U, 1141U, 1128U, 1217U, 3113U, 968U, 3800U,
2153 1154U, 1378U, 1450U, 738U, 4183U, 1417U, 860U, 3704U,
2154 565U, 689U, 726U, 2310U, 1617U, 3614U, 672U, 2521U,
2155 1310U, 3603U, 894U, 2494U, 2481U, 2647U, 3462U, 3485U,
2156 1549U, 1596U, 1569U, 1486U, 959U, 2612U, 2264U, 883U,
2157 4188U, 2765U, 2452U, 1016U, 3830U, 3860U, 2042U, 478U,
2158 185U, 1732U, 3932U, 3939U, 1759U, 1766U, 1773U, 1783U,
2159 543U, 2974U, 2937U, 3025U, 3874U, 2809U, 1538U, 2797U,
2160 1527U, 1139U, 1380U, 4106U, 978U, 993U, 1634U, 3430U,
2161 3032U, 3741U, 3049U, 2860U, 259U, 3096U, 3625U, 3001U,
2162 3773U, 1059U, 2623U, 646U, 233U, 628U, 3663U, 3644U,
2163 2020U, 2672U, 2691U, 379U, 323U, 353U, 364U, 304U,
2164 334U, 938U, 922U, 3143U, 1231U, 1248U, 494U, 191U,
2165 549U, 510U, 2979U, 2943U, 4090U, 2168U, 4073U, 2151U,
2166 445U, 168U, 4008U, 2086U, 1888U, 1835U, 1961U, 1923U,
2167 2372U, 2350U, 587U, 3383U, 718U, 1327U, 578U, 3449U,
2168 3719U, 211U, 3191U, 3580U, 3218U, 3844U, 251U, 3256U,
2169 3881U, 3896U, 3569U, 3557U, 3694U, 1302U, 3823U, 1204U,
2170 3853U, 1513U, 2758U, 2744U, 1506U, 2751U, 2994U, 1650U,
2171 2427U, 2420U, 2434U, 2441U, 3440U, 2256U, 759U, 2240U,
2172 710U, 2248U, 751U, 2232U, 702U, 2294U, 2286U, 1346U,
2173 1338U, 3301U, 3291U, 3281U, 3271U, 3321U, 3311U, 4134U,
2174 4144U, 3331U, 3344U, 4154U, 4164U, 3357U, 3370U, 403U,
2175 147U, 1674U, 128U, 297U, 3911U, 1738U, 1084U, 3984U,
2176 1409U, 2565U, 35U, 9U, 1295U, 18U, 0U, 2540U,
2177 2572U, 1168U, 3815U, 223U, 1386U, 1400U, 2402U, 2411U,
2178 3404U, 3417U, 3012U, 2057U, 3130U, 1068U, 1985U, 1995U,
2179 808U, 823U, 1824U, 1877U, 1909U, 1947U, 3946U, 3972U,
2180 3958U, 767U, 795U, 780U, 1265U, 1280U, 484U, 1431U,
2181 2120U, 4042U, 2144U, 4066U, 3019U, 619U, 609U, 2581U,
2182 3509U, 838U, 2841U, 2821U, 3537U, 3516U, 2875U, 2906U,
2183 2892U, 3173U, 4217U, 1110U, 4210U, 1092U, 3064U, 2473U,
2184 2394U, 946U, 1519U, 3079U, 2192U, 3086U, 2013U, 3071U,
2185 2184U, 2005U, 26U, 1370U, 1362U, 1354U, 3750U, 2788U,
2186 3636U, 3681U, 3783U, 2599U, 847U, 280U, 1037U, 907U,
2187 431U, 154U, 1702U, 3918U, 1745U, 134U, 3758U, 2549U,
2188 2711U, 2727U, 4174U, 867U, 1049U, 3476U, 2302U, 2343U,
2189 2319U, 2331U, 410U, 1681U, 386U, 1657U, 3991U, 2069U,
2190 1856U, 1803U, 462U, 1716U, 527U, 2959U, 2921U, 4025U,
2191 2103U, 4049U, 2127U, 4120U, 4127U, 4267U, 4635U, 5028U,
2192 5418U, 5808U, 6216U, 4438U, 4806U, 5199U, 5589U, 5964U,
2193 6387U, 4354U, 4722U, 5115U, 5505U, 5887U, 6303U, 4525U,
2194 4893U, 5286U, 5676U, 6051U, 6474U, 4249U, 4617U, 5010U,
2195 5400U, 5790U, 6198U, 4420U, 4788U, 5181U, 5571U, 5946U,
2196 6369U, 4338U, 4706U, 5099U, 5489U, 5871U, 6287U, 4509U,
2197 4877U, 5270U, 5660U, 6035U, 6458U, 4574U, 2215U, 2506U,
2198 4275U, 4643U, 5036U, 5426U, 5816U, 6224U, 4446U, 4814U,
2199 5207U, 5597U, 5972U, 6395U, 4361U, 4729U, 5122U, 5512U,
2200 5894U, 6310U, 4532U, 4900U, 5293U, 5683U, 6058U, 6481U,
2201 4258U, 4626U, 5019U, 5409U, 5799U, 6207U, 4429U, 4797U,
2202 5190U, 5580U, 5955U, 6378U, 4346U, 4714U, 5107U, 5497U,
2203 5879U, 6295U, 4517U, 4885U, 5278U, 5668U, 6043U, 6466U,
2204 4299U, 4667U, 5060U, 5450U, 5840U, 6248U, 4470U, 4838U,
2205 5231U, 5621U, 5996U, 6419U, 4382U, 4750U, 5143U, 5533U,
2206 5915U, 6331U, 4553U, 4921U, 5314U, 5704U, 6079U, 6502U,
2207 4307U, 4675U, 5068U, 5458U, 5848U, 6256U, 4478U, 4846U,
2208 5239U, 5629U, 6004U, 6427U, 4389U, 4757U, 5150U, 5540U,
2209 5922U, 6338U, 4560U, 4928U, 5321U, 5711U, 6086U, 6509U,
2210 4591U, 4984U, 6172U, 4594U, 4987U, 5377U, 5767U, 6175U,
2211 4283U, 4651U, 5044U, 5434U, 5824U, 6232U, 4454U, 4822U,
2212 5215U, 5605U, 5980U, 6403U, 4368U, 4736U, 5129U, 5519U,
2213 5901U, 6317U, 4539U, 4907U, 5300U, 5690U, 6065U, 6488U,
2214 4266U, 4634U, 5027U, 5417U, 5807U, 6215U, 4437U, 4805U,
2215 5198U, 5588U, 5963U, 6386U, 4353U, 4721U, 5114U, 5504U,
2216 5886U, 6302U, 4524U, 4892U, 5285U, 5675U, 6050U, 6473U,
2217 207U, 2448U, 4315U, 4683U, 5076U, 5466U, 6264U, 4486U,
2218 4854U, 5247U, 5637U, 6012U, 6435U, 4396U, 4764U, 5157U,
2219 5547U, 6345U, 4567U, 4935U, 5328U, 5718U, 6093U, 6516U,
2220 98U, 109U, 6130U, 4224U, 4583U, 6122U, 6165U, 3472U,
2221 1395U, 4942U, 5335U, 5725U, 6100U, 4972U, 5365U, 5755U,
2222 6153U, 4957U, 5350U, 5740U, 6115U, 4978U, 5371U, 5761U,
2223 6159U, 49U, 82U, 4964U, 5357U, 5747U, 6137U, 4232U,
2224 4600U, 4993U, 5383U, 5773U, 6181U, 4403U, 4771U, 5164U,
2225 5554U, 5929U, 6352U, 4323U, 4691U, 5084U, 5474U, 5856U,
2226 6272U, 4494U, 4862U, 5255U, 5645U, 6020U, 6443U, 4240U,
2227 4608U, 5001U, 5391U, 5781U, 6189U, 4411U, 4779U, 5172U,
2228 5562U, 5937U, 6360U, 4330U, 4698U, 5091U, 5481U, 5863U,
2229 6279U, 4501U, 4869U, 5262U, 5652U, 6027U, 6450U, 4949U,
2230 5342U, 5732U, 6107U, 68U, 120U, 56U, 88U, 43U,
2231 77U, 62U, 93U, 4291U, 4659U, 5052U, 5442U, 5832U,
2232 6240U, 4462U, 4830U, 5223U, 5613U, 5988U, 6411U, 4375U,
2233 4743U, 5136U, 5526U, 5908U, 6324U, 4546U, 4914U, 5307U,
2234 5697U, 6072U, 6495U, 6145U,
2235};
2236
2237static inline void InitMSP430MCInstrInfo(MCInstrInfo *II) {
2238 II->InitMCInstrInfo(MSP430Descs.Insts, MSP430InstrNameIndices, MSP430InstrNameData, nullptr, nullptr, 668, nullptr, 0);
2239}
2240
2241
2242} // namespace llvm
2243
2244#endif // GET_INSTRINFO_MC_DESC
2245
2246#ifdef GET_INSTRINFO_HEADER
2247#undef GET_INSTRINFO_HEADER
2248
2249namespace llvm {
2250
2251struct MSP430GenInstrInfo : public TargetInstrInfo {
2252 explicit MSP430GenInstrInfo(const TargetSubtargetInfo &STI, const TargetRegisterInfo &TRI, unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u, unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u);
2253 ~MSP430GenInstrInfo() override = default;
2254};
2255
2256} // namespace llvm
2257
2258namespace llvm::MSP430 {
2259
2260
2261} // namespace llvm::MSP430
2262
2263#endif // GET_INSTRINFO_HEADER
2264
2265#ifdef GET_INSTRINFO_HELPER_DECLS
2266#undef GET_INSTRINFO_HELPER_DECLS
2267
2268
2269#endif // GET_INSTRINFO_HELPER_DECLS
2270
2271#ifdef GET_INSTRINFO_HELPERS
2272#undef GET_INSTRINFO_HELPERS
2273
2274
2275#endif // GET_INSTRINFO_HELPERS
2276
2277#ifdef GET_INSTRINFO_CTOR_DTOR
2278#undef GET_INSTRINFO_CTOR_DTOR
2279
2280namespace llvm {
2281
2282extern const MSP430InstrTable MSP430Descs;
2283extern const unsigned MSP430InstrNameIndices[];
2284extern const char MSP430InstrNameData[];
2285MSP430GenInstrInfo::MSP430GenInstrInfo(const TargetSubtargetInfo &STI, const TargetRegisterInfo &TRI, unsigned CFSetupOpcode, unsigned CFDestroyOpcode, unsigned CatchRetOpcode, unsigned ReturnOpcode)
2286 : TargetInstrInfo(TRI, CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) {
2287 InitMCInstrInfo(MSP430Descs.Insts, MSP430InstrNameIndices, MSP430InstrNameData, nullptr, nullptr, 668);
2288}
2289
2290} // namespace llvm
2291
2292#endif // GET_INSTRINFO_CTOR_DTOR
2293
2294#ifdef GET_INSTRINFO_MC_HELPER_DECLS
2295#undef GET_INSTRINFO_MC_HELPER_DECLS
2296
2297namespace llvm {
2298
2299class MCInst;
2300class FeatureBitset;
2301
2302namespace MSP430_MC {
2303
2304void verifyInstructionPredicates(unsigned Opcode, const FeatureBitset &Features);
2305
2306} // namespace MSP430_MC
2307
2308} // namespace llvm
2309
2310#endif // GET_INSTRINFO_MC_HELPER_DECLS
2311
2312#ifdef GET_INSTRINFO_MC_HELPERS
2313#undef GET_INSTRINFO_MC_HELPERS
2314
2315namespace llvm::MSP430_MC {
2316
2317
2318} // namespace llvm::MSP430_MC
2319
2320#endif // GET_INSTRINFO_MC_HELPERS
2321
2322#if (defined(ENABLE_INSTR_PREDICATE_VERIFIER) && !defined(NDEBUG)) ||\
2323 defined(GET_AVAILABLE_OPCODE_CHECKER)
2324#define GET_COMPUTE_FEATURES
2325#endif
2326#ifdef GET_COMPUTE_FEATURES
2327#undef GET_COMPUTE_FEATURES
2328
2329namespace llvm::MSP430_MC {
2330
2331// Bits for subtarget features that participate in instruction matching.
2332enum SubtargetFeatureBits : uint8_t {
2333};
2334
2335inline FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) {
2336 FeatureBitset Features;
2337 return Features;
2338}
2339
2340inline FeatureBitset computeRequiredFeatures(unsigned Opcode) {
2341 enum : uint8_t {
2342 CEFBS_None,
2343 };
2344
2345 static constexpr FeatureBitset FeatureBitsets[] = {
2346 {}, // CEFBS_None
2347 };
2348 static constexpr uint8_t RequiredFeaturesRefs[] = {
2349 CEFBS_None, // PHI
2350 CEFBS_None, // INLINEASM
2351 CEFBS_None, // INLINEASM_BR
2352 CEFBS_None, // CFI_INSTRUCTION
2353 CEFBS_None, // EH_LABEL
2354 CEFBS_None, // GC_LABEL
2355 CEFBS_None, // ANNOTATION_LABEL
2356 CEFBS_None, // KILL
2357 CEFBS_None, // EXTRACT_SUBREG
2358 CEFBS_None, // INSERT_SUBREG
2359 CEFBS_None, // IMPLICIT_DEF
2360 CEFBS_None, // INIT_UNDEF
2361 CEFBS_None, // SUBREG_TO_REG
2362 CEFBS_None, // COPY_TO_REGCLASS
2363 CEFBS_None, // DBG_VALUE
2364 CEFBS_None, // DBG_VALUE_LIST
2365 CEFBS_None, // DBG_INSTR_REF
2366 CEFBS_None, // DBG_PHI
2367 CEFBS_None, // DBG_LABEL
2368 CEFBS_None, // REG_SEQUENCE
2369 CEFBS_None, // COPY
2370 CEFBS_None, // COPY_LANEMASK
2371 CEFBS_None, // BUNDLE
2372 CEFBS_None, // LIFETIME_START
2373 CEFBS_None, // LIFETIME_END
2374 CEFBS_None, // PSEUDO_PROBE
2375 CEFBS_None, // ARITH_FENCE
2376 CEFBS_None, // STACKMAP
2377 CEFBS_None, // FENTRY_CALL
2378 CEFBS_None, // PATCHPOINT
2379 CEFBS_None, // LOAD_STACK_GUARD
2380 CEFBS_None, // PREALLOCATED_SETUP
2381 CEFBS_None, // PREALLOCATED_ARG
2382 CEFBS_None, // STATEPOINT
2383 CEFBS_None, // LOCAL_ESCAPE
2384 CEFBS_None, // FAULTING_OP
2385 CEFBS_None, // PATCHABLE_OP
2386 CEFBS_None, // PATCHABLE_FUNCTION_ENTER
2387 CEFBS_None, // PATCHABLE_RET
2388 CEFBS_None, // PATCHABLE_FUNCTION_EXIT
2389 CEFBS_None, // PATCHABLE_TAIL_CALL
2390 CEFBS_None, // PATCHABLE_EVENT_CALL
2391 CEFBS_None, // PATCHABLE_TYPED_EVENT_CALL
2392 CEFBS_None, // ICALL_BRANCH_FUNNEL
2393 CEFBS_None, // FAKE_USE
2394 CEFBS_None, // MEMBARRIER
2395 CEFBS_None, // JUMP_TABLE_DEBUG_INFO
2396 CEFBS_None, // RELOC_NONE
2397 CEFBS_None, // CONVERGENCECTRL_ENTRY
2398 CEFBS_None, // CONVERGENCECTRL_ANCHOR
2399 CEFBS_None, // CONVERGENCECTRL_LOOP
2400 CEFBS_None, // CONVERGENCECTRL_GLUE
2401 CEFBS_None, // G_ASSERT_SEXT
2402 CEFBS_None, // G_ASSERT_ZEXT
2403 CEFBS_None, // G_ASSERT_ALIGN
2404 CEFBS_None, // G_ADD
2405 CEFBS_None, // G_SUB
2406 CEFBS_None, // G_MUL
2407 CEFBS_None, // G_SDIV
2408 CEFBS_None, // G_UDIV
2409 CEFBS_None, // G_SREM
2410 CEFBS_None, // G_UREM
2411 CEFBS_None, // G_SDIVREM
2412 CEFBS_None, // G_UDIVREM
2413 CEFBS_None, // G_AND
2414 CEFBS_None, // G_OR
2415 CEFBS_None, // G_XOR
2416 CEFBS_None, // G_ABDS
2417 CEFBS_None, // G_ABDU
2418 CEFBS_None, // G_UAVGFLOOR
2419 CEFBS_None, // G_UAVGCEIL
2420 CEFBS_None, // G_SAVGFLOOR
2421 CEFBS_None, // G_SAVGCEIL
2422 CEFBS_None, // G_IMPLICIT_DEF
2423 CEFBS_None, // G_PHI
2424 CEFBS_None, // G_FRAME_INDEX
2425 CEFBS_None, // G_GLOBAL_VALUE
2426 CEFBS_None, // G_PTRAUTH_GLOBAL_VALUE
2427 CEFBS_None, // G_CONSTANT_POOL
2428 CEFBS_None, // G_EXTRACT
2429 CEFBS_None, // G_UNMERGE_VALUES
2430 CEFBS_None, // G_INSERT
2431 CEFBS_None, // G_MERGE_VALUES
2432 CEFBS_None, // G_BUILD_VECTOR
2433 CEFBS_None, // G_BUILD_VECTOR_TRUNC
2434 CEFBS_None, // G_CONCAT_VECTORS
2435 CEFBS_None, // G_PTRTOINT
2436 CEFBS_None, // G_INTTOPTR
2437 CEFBS_None, // G_BITCAST
2438 CEFBS_None, // G_FREEZE
2439 CEFBS_None, // G_CONSTANT_FOLD_BARRIER
2440 CEFBS_None, // G_INTRINSIC_FPTRUNC_ROUND
2441 CEFBS_None, // G_INTRINSIC_TRUNC
2442 CEFBS_None, // G_INTRINSIC_ROUND
2443 CEFBS_None, // G_INTRINSIC_LRINT
2444 CEFBS_None, // G_INTRINSIC_LLRINT
2445 CEFBS_None, // G_INTRINSIC_ROUNDEVEN
2446 CEFBS_None, // G_READCYCLECOUNTER
2447 CEFBS_None, // G_READSTEADYCOUNTER
2448 CEFBS_None, // G_LOAD
2449 CEFBS_None, // G_SEXTLOAD
2450 CEFBS_None, // G_ZEXTLOAD
2451 CEFBS_None, // G_INDEXED_LOAD
2452 CEFBS_None, // G_INDEXED_SEXTLOAD
2453 CEFBS_None, // G_INDEXED_ZEXTLOAD
2454 CEFBS_None, // G_STORE
2455 CEFBS_None, // G_INDEXED_STORE
2456 CEFBS_None, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
2457 CEFBS_None, // G_ATOMIC_CMPXCHG
2458 CEFBS_None, // G_ATOMICRMW_XCHG
2459 CEFBS_None, // G_ATOMICRMW_ADD
2460 CEFBS_None, // G_ATOMICRMW_SUB
2461 CEFBS_None, // G_ATOMICRMW_AND
2462 CEFBS_None, // G_ATOMICRMW_NAND
2463 CEFBS_None, // G_ATOMICRMW_OR
2464 CEFBS_None, // G_ATOMICRMW_XOR
2465 CEFBS_None, // G_ATOMICRMW_MAX
2466 CEFBS_None, // G_ATOMICRMW_MIN
2467 CEFBS_None, // G_ATOMICRMW_UMAX
2468 CEFBS_None, // G_ATOMICRMW_UMIN
2469 CEFBS_None, // G_ATOMICRMW_FADD
2470 CEFBS_None, // G_ATOMICRMW_FSUB
2471 CEFBS_None, // G_ATOMICRMW_FMAX
2472 CEFBS_None, // G_ATOMICRMW_FMIN
2473 CEFBS_None, // G_ATOMICRMW_FMAXIMUM
2474 CEFBS_None, // G_ATOMICRMW_FMINIMUM
2475 CEFBS_None, // G_ATOMICRMW_FMAXIMUMNUM
2476 CEFBS_None, // G_ATOMICRMW_FMINIMUMNUM
2477 CEFBS_None, // G_ATOMICRMW_UINC_WRAP
2478 CEFBS_None, // G_ATOMICRMW_UDEC_WRAP
2479 CEFBS_None, // G_ATOMICRMW_USUB_COND
2480 CEFBS_None, // G_ATOMICRMW_USUB_SAT
2481 CEFBS_None, // G_FENCE
2482 CEFBS_None, // G_PREFETCH
2483 CEFBS_None, // G_BRCOND
2484 CEFBS_None, // G_BRINDIRECT
2485 CEFBS_None, // G_INVOKE_REGION_START
2486 CEFBS_None, // G_INTRINSIC
2487 CEFBS_None, // G_INTRINSIC_W_SIDE_EFFECTS
2488 CEFBS_None, // G_INTRINSIC_CONVERGENT
2489 CEFBS_None, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
2490 CEFBS_None, // G_ANYEXT
2491 CEFBS_None, // G_TRUNC
2492 CEFBS_None, // G_TRUNC_SSAT_S
2493 CEFBS_None, // G_TRUNC_SSAT_U
2494 CEFBS_None, // G_TRUNC_USAT_U
2495 CEFBS_None, // G_CONSTANT
2496 CEFBS_None, // G_FCONSTANT
2497 CEFBS_None, // G_VASTART
2498 CEFBS_None, // G_VAARG
2499 CEFBS_None, // G_SEXT
2500 CEFBS_None, // G_SEXT_INREG
2501 CEFBS_None, // G_ZEXT
2502 CEFBS_None, // G_SHL
2503 CEFBS_None, // G_LSHR
2504 CEFBS_None, // G_ASHR
2505 CEFBS_None, // G_FSHL
2506 CEFBS_None, // G_FSHR
2507 CEFBS_None, // G_ROTR
2508 CEFBS_None, // G_ROTL
2509 CEFBS_None, // G_ICMP
2510 CEFBS_None, // G_FCMP
2511 CEFBS_None, // G_SCMP
2512 CEFBS_None, // G_UCMP
2513 CEFBS_None, // G_SELECT
2514 CEFBS_None, // G_UADDO
2515 CEFBS_None, // G_UADDE
2516 CEFBS_None, // G_USUBO
2517 CEFBS_None, // G_USUBE
2518 CEFBS_None, // G_SADDO
2519 CEFBS_None, // G_SADDE
2520 CEFBS_None, // G_SSUBO
2521 CEFBS_None, // G_SSUBE
2522 CEFBS_None, // G_UMULO
2523 CEFBS_None, // G_SMULO
2524 CEFBS_None, // G_UMULH
2525 CEFBS_None, // G_SMULH
2526 CEFBS_None, // G_UADDSAT
2527 CEFBS_None, // G_SADDSAT
2528 CEFBS_None, // G_USUBSAT
2529 CEFBS_None, // G_SSUBSAT
2530 CEFBS_None, // G_USHLSAT
2531 CEFBS_None, // G_SSHLSAT
2532 CEFBS_None, // G_SMULFIX
2533 CEFBS_None, // G_UMULFIX
2534 CEFBS_None, // G_SMULFIXSAT
2535 CEFBS_None, // G_UMULFIXSAT
2536 CEFBS_None, // G_SDIVFIX
2537 CEFBS_None, // G_UDIVFIX
2538 CEFBS_None, // G_SDIVFIXSAT
2539 CEFBS_None, // G_UDIVFIXSAT
2540 CEFBS_None, // G_FADD
2541 CEFBS_None, // G_FSUB
2542 CEFBS_None, // G_FMUL
2543 CEFBS_None, // G_FMA
2544 CEFBS_None, // G_FMAD
2545 CEFBS_None, // G_FDIV
2546 CEFBS_None, // G_FREM
2547 CEFBS_None, // G_FMODF
2548 CEFBS_None, // G_FPOW
2549 CEFBS_None, // G_FPOWI
2550 CEFBS_None, // G_FEXP
2551 CEFBS_None, // G_FEXP2
2552 CEFBS_None, // G_FEXP10
2553 CEFBS_None, // G_FLOG
2554 CEFBS_None, // G_FLOG2
2555 CEFBS_None, // G_FLOG10
2556 CEFBS_None, // G_FLDEXP
2557 CEFBS_None, // G_FFREXP
2558 CEFBS_None, // G_FNEG
2559 CEFBS_None, // G_FPEXT
2560 CEFBS_None, // G_FPTRUNC
2561 CEFBS_None, // G_FPTOSI
2562 CEFBS_None, // G_FPTOUI
2563 CEFBS_None, // G_SITOFP
2564 CEFBS_None, // G_UITOFP
2565 CEFBS_None, // G_FPTOSI_SAT
2566 CEFBS_None, // G_FPTOUI_SAT
2567 CEFBS_None, // G_FABS
2568 CEFBS_None, // G_FCOPYSIGN
2569 CEFBS_None, // G_IS_FPCLASS
2570 CEFBS_None, // G_FCANONICALIZE
2571 CEFBS_None, // G_FMINNUM
2572 CEFBS_None, // G_FMAXNUM
2573 CEFBS_None, // G_FMINNUM_IEEE
2574 CEFBS_None, // G_FMAXNUM_IEEE
2575 CEFBS_None, // G_FMINIMUM
2576 CEFBS_None, // G_FMAXIMUM
2577 CEFBS_None, // G_FMINIMUMNUM
2578 CEFBS_None, // G_FMAXIMUMNUM
2579 CEFBS_None, // G_GET_FPENV
2580 CEFBS_None, // G_SET_FPENV
2581 CEFBS_None, // G_RESET_FPENV
2582 CEFBS_None, // G_GET_FPMODE
2583 CEFBS_None, // G_SET_FPMODE
2584 CEFBS_None, // G_RESET_FPMODE
2585 CEFBS_None, // G_GET_ROUNDING
2586 CEFBS_None, // G_SET_ROUNDING
2587 CEFBS_None, // G_PTR_ADD
2588 CEFBS_None, // G_PTRMASK
2589 CEFBS_None, // G_SMIN
2590 CEFBS_None, // G_SMAX
2591 CEFBS_None, // G_UMIN
2592 CEFBS_None, // G_UMAX
2593 CEFBS_None, // G_ABS
2594 CEFBS_None, // G_LROUND
2595 CEFBS_None, // G_LLROUND
2596 CEFBS_None, // G_BR
2597 CEFBS_None, // G_BRJT
2598 CEFBS_None, // G_VSCALE
2599 CEFBS_None, // G_INSERT_SUBVECTOR
2600 CEFBS_None, // G_EXTRACT_SUBVECTOR
2601 CEFBS_None, // G_INSERT_VECTOR_ELT
2602 CEFBS_None, // G_EXTRACT_VECTOR_ELT
2603 CEFBS_None, // G_SHUFFLE_VECTOR
2604 CEFBS_None, // G_SPLAT_VECTOR
2605 CEFBS_None, // G_STEP_VECTOR
2606 CEFBS_None, // G_VECTOR_COMPRESS
2607 CEFBS_None, // G_CTTZ
2608 CEFBS_None, // G_CTTZ_ZERO_UNDEF
2609 CEFBS_None, // G_CTLZ
2610 CEFBS_None, // G_CTLZ_ZERO_UNDEF
2611 CEFBS_None, // G_CTLS
2612 CEFBS_None, // G_CTPOP
2613 CEFBS_None, // G_BSWAP
2614 CEFBS_None, // G_BITREVERSE
2615 CEFBS_None, // G_FCEIL
2616 CEFBS_None, // G_FCOS
2617 CEFBS_None, // G_FSIN
2618 CEFBS_None, // G_FSINCOS
2619 CEFBS_None, // G_FTAN
2620 CEFBS_None, // G_FACOS
2621 CEFBS_None, // G_FASIN
2622 CEFBS_None, // G_FATAN
2623 CEFBS_None, // G_FATAN2
2624 CEFBS_None, // G_FCOSH
2625 CEFBS_None, // G_FSINH
2626 CEFBS_None, // G_FTANH
2627 CEFBS_None, // G_FSQRT
2628 CEFBS_None, // G_FFLOOR
2629 CEFBS_None, // G_FRINT
2630 CEFBS_None, // G_FNEARBYINT
2631 CEFBS_None, // G_ADDRSPACE_CAST
2632 CEFBS_None, // G_BLOCK_ADDR
2633 CEFBS_None, // G_JUMP_TABLE
2634 CEFBS_None, // G_DYN_STACKALLOC
2635 CEFBS_None, // G_STACKSAVE
2636 CEFBS_None, // G_STACKRESTORE
2637 CEFBS_None, // G_STRICT_FADD
2638 CEFBS_None, // G_STRICT_FSUB
2639 CEFBS_None, // G_STRICT_FMUL
2640 CEFBS_None, // G_STRICT_FDIV
2641 CEFBS_None, // G_STRICT_FREM
2642 CEFBS_None, // G_STRICT_FMA
2643 CEFBS_None, // G_STRICT_FSQRT
2644 CEFBS_None, // G_STRICT_FLDEXP
2645 CEFBS_None, // G_READ_REGISTER
2646 CEFBS_None, // G_WRITE_REGISTER
2647 CEFBS_None, // G_MEMCPY
2648 CEFBS_None, // G_MEMCPY_INLINE
2649 CEFBS_None, // G_MEMMOVE
2650 CEFBS_None, // G_MEMSET
2651 CEFBS_None, // G_BZERO
2652 CEFBS_None, // G_TRAP
2653 CEFBS_None, // G_DEBUGTRAP
2654 CEFBS_None, // G_UBSANTRAP
2655 CEFBS_None, // G_VECREDUCE_SEQ_FADD
2656 CEFBS_None, // G_VECREDUCE_SEQ_FMUL
2657 CEFBS_None, // G_VECREDUCE_FADD
2658 CEFBS_None, // G_VECREDUCE_FMUL
2659 CEFBS_None, // G_VECREDUCE_FMAX
2660 CEFBS_None, // G_VECREDUCE_FMIN
2661 CEFBS_None, // G_VECREDUCE_FMAXIMUM
2662 CEFBS_None, // G_VECREDUCE_FMINIMUM
2663 CEFBS_None, // G_VECREDUCE_ADD
2664 CEFBS_None, // G_VECREDUCE_MUL
2665 CEFBS_None, // G_VECREDUCE_AND
2666 CEFBS_None, // G_VECREDUCE_OR
2667 CEFBS_None, // G_VECREDUCE_XOR
2668 CEFBS_None, // G_VECREDUCE_SMAX
2669 CEFBS_None, // G_VECREDUCE_SMIN
2670 CEFBS_None, // G_VECREDUCE_UMAX
2671 CEFBS_None, // G_VECREDUCE_UMIN
2672 CEFBS_None, // G_SBFX
2673 CEFBS_None, // G_UBFX
2674 CEFBS_None, // ADD16mc
2675 CEFBS_None, // ADD16mi
2676 CEFBS_None, // ADD16mm
2677 CEFBS_None, // ADD16mn
2678 CEFBS_None, // ADD16mp
2679 CEFBS_None, // ADD16mr
2680 CEFBS_None, // ADD16rc
2681 CEFBS_None, // ADD16ri
2682 CEFBS_None, // ADD16rm
2683 CEFBS_None, // ADD16rn
2684 CEFBS_None, // ADD16rp
2685 CEFBS_None, // ADD16rr
2686 CEFBS_None, // ADD8mc
2687 CEFBS_None, // ADD8mi
2688 CEFBS_None, // ADD8mm
2689 CEFBS_None, // ADD8mn
2690 CEFBS_None, // ADD8mp
2691 CEFBS_None, // ADD8mr
2692 CEFBS_None, // ADD8rc
2693 CEFBS_None, // ADD8ri
2694 CEFBS_None, // ADD8rm
2695 CEFBS_None, // ADD8rn
2696 CEFBS_None, // ADD8rp
2697 CEFBS_None, // ADD8rr
2698 CEFBS_None, // ADDC16mc
2699 CEFBS_None, // ADDC16mi
2700 CEFBS_None, // ADDC16mm
2701 CEFBS_None, // ADDC16mn
2702 CEFBS_None, // ADDC16mp
2703 CEFBS_None, // ADDC16mr
2704 CEFBS_None, // ADDC16rc
2705 CEFBS_None, // ADDC16ri
2706 CEFBS_None, // ADDC16rm
2707 CEFBS_None, // ADDC16rn
2708 CEFBS_None, // ADDC16rp
2709 CEFBS_None, // ADDC16rr
2710 CEFBS_None, // ADDC8mc
2711 CEFBS_None, // ADDC8mi
2712 CEFBS_None, // ADDC8mm
2713 CEFBS_None, // ADDC8mn
2714 CEFBS_None, // ADDC8mp
2715 CEFBS_None, // ADDC8mr
2716 CEFBS_None, // ADDC8rc
2717 CEFBS_None, // ADDC8ri
2718 CEFBS_None, // ADDC8rm
2719 CEFBS_None, // ADDC8rn
2720 CEFBS_None, // ADDC8rp
2721 CEFBS_None, // ADDC8rr
2722 CEFBS_None, // ADDframe
2723 CEFBS_None, // ADJCALLSTACKDOWN
2724 CEFBS_None, // ADJCALLSTACKUP
2725 CEFBS_None, // AND16mc
2726 CEFBS_None, // AND16mi
2727 CEFBS_None, // AND16mm
2728 CEFBS_None, // AND16mn
2729 CEFBS_None, // AND16mp
2730 CEFBS_None, // AND16mr
2731 CEFBS_None, // AND16rc
2732 CEFBS_None, // AND16ri
2733 CEFBS_None, // AND16rm
2734 CEFBS_None, // AND16rn
2735 CEFBS_None, // AND16rp
2736 CEFBS_None, // AND16rr
2737 CEFBS_None, // AND8mc
2738 CEFBS_None, // AND8mi
2739 CEFBS_None, // AND8mm
2740 CEFBS_None, // AND8mn
2741 CEFBS_None, // AND8mp
2742 CEFBS_None, // AND8mr
2743 CEFBS_None, // AND8rc
2744 CEFBS_None, // AND8ri
2745 CEFBS_None, // AND8rm
2746 CEFBS_None, // AND8rn
2747 CEFBS_None, // AND8rp
2748 CEFBS_None, // AND8rr
2749 CEFBS_None, // BIC16mc
2750 CEFBS_None, // BIC16mi
2751 CEFBS_None, // BIC16mm
2752 CEFBS_None, // BIC16mn
2753 CEFBS_None, // BIC16mp
2754 CEFBS_None, // BIC16mr
2755 CEFBS_None, // BIC16rc
2756 CEFBS_None, // BIC16ri
2757 CEFBS_None, // BIC16rm
2758 CEFBS_None, // BIC16rn
2759 CEFBS_None, // BIC16rp
2760 CEFBS_None, // BIC16rr
2761 CEFBS_None, // BIC8mc
2762 CEFBS_None, // BIC8mi
2763 CEFBS_None, // BIC8mm
2764 CEFBS_None, // BIC8mn
2765 CEFBS_None, // BIC8mp
2766 CEFBS_None, // BIC8mr
2767 CEFBS_None, // BIC8rc
2768 CEFBS_None, // BIC8ri
2769 CEFBS_None, // BIC8rm
2770 CEFBS_None, // BIC8rn
2771 CEFBS_None, // BIC8rp
2772 CEFBS_None, // BIC8rr
2773 CEFBS_None, // BIS16mc
2774 CEFBS_None, // BIS16mi
2775 CEFBS_None, // BIS16mm
2776 CEFBS_None, // BIS16mn
2777 CEFBS_None, // BIS16mp
2778 CEFBS_None, // BIS16mr
2779 CEFBS_None, // BIS16rc
2780 CEFBS_None, // BIS16ri
2781 CEFBS_None, // BIS16rm
2782 CEFBS_None, // BIS16rn
2783 CEFBS_None, // BIS16rp
2784 CEFBS_None, // BIS16rr
2785 CEFBS_None, // BIS8mc
2786 CEFBS_None, // BIS8mi
2787 CEFBS_None, // BIS8mm
2788 CEFBS_None, // BIS8mn
2789 CEFBS_None, // BIS8mp
2790 CEFBS_None, // BIS8mr
2791 CEFBS_None, // BIS8rc
2792 CEFBS_None, // BIS8ri
2793 CEFBS_None, // BIS8rm
2794 CEFBS_None, // BIS8rn
2795 CEFBS_None, // BIS8rp
2796 CEFBS_None, // BIS8rr
2797 CEFBS_None, // BIT16mc
2798 CEFBS_None, // BIT16mi
2799 CEFBS_None, // BIT16mm
2800 CEFBS_None, // BIT16mn
2801 CEFBS_None, // BIT16mp
2802 CEFBS_None, // BIT16mr
2803 CEFBS_None, // BIT16rc
2804 CEFBS_None, // BIT16ri
2805 CEFBS_None, // BIT16rm
2806 CEFBS_None, // BIT16rn
2807 CEFBS_None, // BIT16rp
2808 CEFBS_None, // BIT16rr
2809 CEFBS_None, // BIT8mc
2810 CEFBS_None, // BIT8mi
2811 CEFBS_None, // BIT8mm
2812 CEFBS_None, // BIT8mn
2813 CEFBS_None, // BIT8mp
2814 CEFBS_None, // BIT8mr
2815 CEFBS_None, // BIT8rc
2816 CEFBS_None, // BIT8ri
2817 CEFBS_None, // BIT8rm
2818 CEFBS_None, // BIT8rn
2819 CEFBS_None, // BIT8rp
2820 CEFBS_None, // BIT8rr
2821 CEFBS_None, // Bi
2822 CEFBS_None, // Bm
2823 CEFBS_None, // Br
2824 CEFBS_None, // CALLi
2825 CEFBS_None, // CALLm
2826 CEFBS_None, // CALLn
2827 CEFBS_None, // CALLp
2828 CEFBS_None, // CALLr
2829 CEFBS_None, // CMP16mc
2830 CEFBS_None, // CMP16mi
2831 CEFBS_None, // CMP16mm
2832 CEFBS_None, // CMP16mn
2833 CEFBS_None, // CMP16mp
2834 CEFBS_None, // CMP16mr
2835 CEFBS_None, // CMP16rc
2836 CEFBS_None, // CMP16ri
2837 CEFBS_None, // CMP16rm
2838 CEFBS_None, // CMP16rn
2839 CEFBS_None, // CMP16rp
2840 CEFBS_None, // CMP16rr
2841 CEFBS_None, // CMP8mc
2842 CEFBS_None, // CMP8mi
2843 CEFBS_None, // CMP8mm
2844 CEFBS_None, // CMP8mn
2845 CEFBS_None, // CMP8mp
2846 CEFBS_None, // CMP8mr
2847 CEFBS_None, // CMP8rc
2848 CEFBS_None, // CMP8ri
2849 CEFBS_None, // CMP8rm
2850 CEFBS_None, // CMP8rn
2851 CEFBS_None, // CMP8rp
2852 CEFBS_None, // CMP8rr
2853 CEFBS_None, // DADD16mc
2854 CEFBS_None, // DADD16mi
2855 CEFBS_None, // DADD16mm
2856 CEFBS_None, // DADD16mn
2857 CEFBS_None, // DADD16mp
2858 CEFBS_None, // DADD16mr
2859 CEFBS_None, // DADD16rc
2860 CEFBS_None, // DADD16ri
2861 CEFBS_None, // DADD16rm
2862 CEFBS_None, // DADD16rn
2863 CEFBS_None, // DADD16rp
2864 CEFBS_None, // DADD16rr
2865 CEFBS_None, // DADD8mc
2866 CEFBS_None, // DADD8mi
2867 CEFBS_None, // DADD8mm
2868 CEFBS_None, // DADD8mn
2869 CEFBS_None, // DADD8mp
2870 CEFBS_None, // DADD8mr
2871 CEFBS_None, // DADD8rc
2872 CEFBS_None, // DADD8ri
2873 CEFBS_None, // DADD8rm
2874 CEFBS_None, // DADD8rn
2875 CEFBS_None, // DADD8rp
2876 CEFBS_None, // DADD8rr
2877 CEFBS_None, // JCC
2878 CEFBS_None, // JMP
2879 CEFBS_None, // MOV16mc
2880 CEFBS_None, // MOV16mi
2881 CEFBS_None, // MOV16mm
2882 CEFBS_None, // MOV16mn
2883 CEFBS_None, // MOV16mr
2884 CEFBS_None, // MOV16rc
2885 CEFBS_None, // MOV16ri
2886 CEFBS_None, // MOV16rm
2887 CEFBS_None, // MOV16rn
2888 CEFBS_None, // MOV16rp
2889 CEFBS_None, // MOV16rr
2890 CEFBS_None, // MOV8mc
2891 CEFBS_None, // MOV8mi
2892 CEFBS_None, // MOV8mm
2893 CEFBS_None, // MOV8mn
2894 CEFBS_None, // MOV8mr
2895 CEFBS_None, // MOV8rc
2896 CEFBS_None, // MOV8ri
2897 CEFBS_None, // MOV8rm
2898 CEFBS_None, // MOV8rn
2899 CEFBS_None, // MOV8rp
2900 CEFBS_None, // MOV8rr
2901 CEFBS_None, // MOVZX16rm8
2902 CEFBS_None, // MOVZX16rr8
2903 CEFBS_None, // POP16r
2904 CEFBS_None, // PUSH16c
2905 CEFBS_None, // PUSH16i
2906 CEFBS_None, // PUSH16r
2907 CEFBS_None, // PUSH8r
2908 CEFBS_None, // RET
2909 CEFBS_None, // RETI
2910 CEFBS_None, // RRA16m
2911 CEFBS_None, // RRA16n
2912 CEFBS_None, // RRA16p
2913 CEFBS_None, // RRA16r
2914 CEFBS_None, // RRA8m
2915 CEFBS_None, // RRA8n
2916 CEFBS_None, // RRA8p
2917 CEFBS_None, // RRA8r
2918 CEFBS_None, // RRC16m
2919 CEFBS_None, // RRC16n
2920 CEFBS_None, // RRC16p
2921 CEFBS_None, // RRC16r
2922 CEFBS_None, // RRC8m
2923 CEFBS_None, // RRC8n
2924 CEFBS_None, // RRC8p
2925 CEFBS_None, // RRC8r
2926 CEFBS_None, // Rrcl16
2927 CEFBS_None, // Rrcl8
2928 CEFBS_None, // SEXT16m
2929 CEFBS_None, // SEXT16n
2930 CEFBS_None, // SEXT16p
2931 CEFBS_None, // SEXT16r
2932 CEFBS_None, // SUB16mc
2933 CEFBS_None, // SUB16mi
2934 CEFBS_None, // SUB16mm
2935 CEFBS_None, // SUB16mn
2936 CEFBS_None, // SUB16mp
2937 CEFBS_None, // SUB16mr
2938 CEFBS_None, // SUB16rc
2939 CEFBS_None, // SUB16ri
2940 CEFBS_None, // SUB16rm
2941 CEFBS_None, // SUB16rn
2942 CEFBS_None, // SUB16rp
2943 CEFBS_None, // SUB16rr
2944 CEFBS_None, // SUB8mc
2945 CEFBS_None, // SUB8mi
2946 CEFBS_None, // SUB8mm
2947 CEFBS_None, // SUB8mn
2948 CEFBS_None, // SUB8mp
2949 CEFBS_None, // SUB8mr
2950 CEFBS_None, // SUB8rc
2951 CEFBS_None, // SUB8ri
2952 CEFBS_None, // SUB8rm
2953 CEFBS_None, // SUB8rn
2954 CEFBS_None, // SUB8rp
2955 CEFBS_None, // SUB8rr
2956 CEFBS_None, // SUBC16mc
2957 CEFBS_None, // SUBC16mi
2958 CEFBS_None, // SUBC16mm
2959 CEFBS_None, // SUBC16mn
2960 CEFBS_None, // SUBC16mp
2961 CEFBS_None, // SUBC16mr
2962 CEFBS_None, // SUBC16rc
2963 CEFBS_None, // SUBC16ri
2964 CEFBS_None, // SUBC16rm
2965 CEFBS_None, // SUBC16rn
2966 CEFBS_None, // SUBC16rp
2967 CEFBS_None, // SUBC16rr
2968 CEFBS_None, // SUBC8mc
2969 CEFBS_None, // SUBC8mi
2970 CEFBS_None, // SUBC8mm
2971 CEFBS_None, // SUBC8mn
2972 CEFBS_None, // SUBC8mp
2973 CEFBS_None, // SUBC8mr
2974 CEFBS_None, // SUBC8rc
2975 CEFBS_None, // SUBC8ri
2976 CEFBS_None, // SUBC8rm
2977 CEFBS_None, // SUBC8rn
2978 CEFBS_None, // SUBC8rp
2979 CEFBS_None, // SUBC8rr
2980 CEFBS_None, // SWPB16m
2981 CEFBS_None, // SWPB16n
2982 CEFBS_None, // SWPB16p
2983 CEFBS_None, // SWPB16r
2984 CEFBS_None, // Select16
2985 CEFBS_None, // Select8
2986 CEFBS_None, // Shl16
2987 CEFBS_None, // Shl8
2988 CEFBS_None, // Sra16
2989 CEFBS_None, // Sra8
2990 CEFBS_None, // Srl16
2991 CEFBS_None, // Srl8
2992 CEFBS_None, // XOR16mc
2993 CEFBS_None, // XOR16mi
2994 CEFBS_None, // XOR16mm
2995 CEFBS_None, // XOR16mn
2996 CEFBS_None, // XOR16mp
2997 CEFBS_None, // XOR16mr
2998 CEFBS_None, // XOR16rc
2999 CEFBS_None, // XOR16ri
3000 CEFBS_None, // XOR16rm
3001 CEFBS_None, // XOR16rn
3002 CEFBS_None, // XOR16rp
3003 CEFBS_None, // XOR16rr
3004 CEFBS_None, // XOR8mc
3005 CEFBS_None, // XOR8mi
3006 CEFBS_None, // XOR8mm
3007 CEFBS_None, // XOR8mn
3008 CEFBS_None, // XOR8mp
3009 CEFBS_None, // XOR8mr
3010 CEFBS_None, // XOR8rc
3011 CEFBS_None, // XOR8ri
3012 CEFBS_None, // XOR8rm
3013 CEFBS_None, // XOR8rn
3014 CEFBS_None, // XOR8rp
3015 CEFBS_None, // XOR8rr
3016 CEFBS_None, // ZEXT16r
3017 };
3018
3019 assert(Opcode < 668);
3020 return FeatureBitsets[RequiredFeaturesRefs[Opcode]];
3021}
3022
3023
3024} // namespace llvm::MSP430_MC
3025
3026#endif // GET_COMPUTE_FEATURES
3027
3028#ifdef GET_AVAILABLE_OPCODE_CHECKER
3029#undef GET_AVAILABLE_OPCODE_CHECKER
3030
3031namespace llvm::MSP430_MC {
3032
3033bool isOpcodeAvailable(unsigned Opcode, const FeatureBitset &Features) {
3034 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
3035 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
3036 FeatureBitset MissingFeatures =
3037 (AvailableFeatures & RequiredFeatures) ^
3038 RequiredFeatures;
3039 return !MissingFeatures.any();
3040}
3041
3042} // namespace llvm::MSP430_MC
3043
3044#endif // GET_AVAILABLE_OPCODE_CHECKER
3045
3046#ifdef ENABLE_INSTR_PREDICATE_VERIFIER
3047#undef ENABLE_INSTR_PREDICATE_VERIFIER
3048
3049#include <sstream>
3050
3051namespace llvm::MSP430_MC {
3052
3053#ifndef NDEBUG
3054static const char *SubtargetFeatureNames[] = {
3055 nullptr
3056};
3057
3058#endif // NDEBUG
3059
3060void verifyInstructionPredicates(
3061 unsigned Opcode, const FeatureBitset &Features) {
3062#ifndef NDEBUG
3063 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
3064 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
3065 FeatureBitset MissingFeatures =
3066 (AvailableFeatures & RequiredFeatures) ^
3067 RequiredFeatures;
3068 if (MissingFeatures.any()) {
3069 std::ostringstream Msg;
3070 Msg << "Attempting to emit " << &MSP430InstrNameData[MSP430InstrNameIndices[Opcode]]
3071 << " instruction but the ";
3072 for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i)
3073 if (MissingFeatures.test(i))
3074 Msg << SubtargetFeatureNames[i] << " ";
3075 Msg << "predicate(s) are not met";
3076 report_fatal_error(Msg.str().c_str());
3077 }
3078#endif // NDEBUG
3079}
3080
3081} // namespace llvm::MSP430_MC
3082
3083#endif // ENABLE_INSTR_PREDICATE_VERIFIER
3084
3085