1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Instruction Enum Values and Descriptors *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_INSTRINFO_ENUM
10#undef GET_INSTRINFO_ENUM
11
12namespace llvm::MSP430 {
13
14 enum {
15 PHI = 0, // Target.td:1314
16 INLINEASM = 1, // Target.td:1320
17 INLINEASM_BR = 2, // Target.td:1326
18 CFI_INSTRUCTION = 3, // Target.td:1335
19 EH_LABEL = 4, // Target.td:1344
20 GC_LABEL = 5, // Target.td:1353
21 ANNOTATION_LABEL = 6, // Target.td:1362
22 KILL = 7, // Target.td:1370
23 EXTRACT_SUBREG = 8, // Target.td:1377
24 INSERT_SUBREG = 9, // Target.td:1383
25 IMPLICIT_DEF = 10, // Target.td:1390
26 INIT_UNDEF = 11, // Target.td:1399
27 SUBREG_TO_REG = 12, // Target.td:1406
28 COPY_TO_REGCLASS = 13, // Target.td:1412
29 DBG_VALUE = 14, // Target.td:1419
30 DBG_VALUE_LIST = 15, // Target.td:1426
31 DBG_INSTR_REF = 16, // Target.td:1433
32 DBG_PHI = 17, // Target.td:1440
33 DBG_LABEL = 18, // Target.td:1447
34 REG_SEQUENCE = 19, // Target.td:1454
35 COPY = 20, // Target.td:1461
36 COPY_LANEMASK = 21, // Target.td:1469
37 BUNDLE = 22, // Target.td:1476
38 LIFETIME_START = 23, // Target.td:1482
39 LIFETIME_END = 24, // Target.td:1489
40 PSEUDO_PROBE = 25, // Target.td:1496
41 ARITH_FENCE = 26, // Target.td:1503
42 STACKMAP = 27, // Target.td:1512
43 FENTRY_CALL = 28, // Target.td:1647
44 PATCHPOINT = 29, // Target.td:1520
45 LOAD_STACK_GUARD = 30, // Target.td:1538
46 PREALLOCATED_SETUP = 31, // Target.td:1546
47 PREALLOCATED_ARG = 32, // Target.td:1552
48 STATEPOINT = 33, // Target.td:1529
49 LOCAL_ESCAPE = 34, // Target.td:1558
50 FAULTING_OP = 35, // Target.td:1567
51 PATCHABLE_OP = 36, // Target.td:1587
52 PATCHABLE_FUNCTION_ENTER = 37, // Target.td:1595
53 PATCHABLE_RET = 38, // Target.td:1602
54 PATCHABLE_FUNCTION_EXIT = 39, // Target.td:1611
55 PATCHABLE_TAIL_CALL = 40, // Target.td:1619
56 PATCHABLE_EVENT_CALL = 41, // Target.td:1627
57 PATCHABLE_TYPED_EVENT_CALL = 42, // Target.td:1637
58 ICALL_BRANCH_FUNNEL = 43, // Target.td:1657
59 FAKE_USE = 44, // Target.td:1577
60 MEMBARRIER = 45, // Target.td:1663
61 JUMP_TABLE_DEBUG_INFO = 46, // Target.td:1671
62 RELOC_NONE = 47, // Target.td:1679
63 CONVERGENCECTRL_ENTRY = 48, // Target.td:1691
64 CONVERGENCECTRL_ANCHOR = 49, // Target.td:1687
65 CONVERGENCECTRL_LOOP = 50, // Target.td:1695
66 CONVERGENCECTRL_GLUE = 51, // Target.td:1699
67 G_ASSERT_SEXT = 52, // GenericOpcodes.td:1955
68 G_ASSERT_ZEXT = 53, // GenericOpcodes.td:1947
69 G_ASSERT_ALIGN = 54, // GenericOpcodes.td:1962
70 G_ADD = 55, // GenericOpcodes.td:308
71 G_SUB = 56, // GenericOpcodes.td:316
72 G_MUL = 57, // GenericOpcodes.td:324
73 G_SDIV = 58, // GenericOpcodes.td:332
74 G_UDIV = 59, // GenericOpcodes.td:340
75 G_SREM = 60, // GenericOpcodes.td:348
76 G_UREM = 61, // GenericOpcodes.td:356
77 G_SDIVREM = 62, // GenericOpcodes.td:364
78 G_UDIVREM = 63, // GenericOpcodes.td:372
79 G_AND = 64, // GenericOpcodes.td:380
80 G_OR = 65, // GenericOpcodes.td:388
81 G_XOR = 66, // GenericOpcodes.td:396
82 G_ABDS = 67, // GenericOpcodes.td:425
83 G_ABDU = 68, // GenericOpcodes.td:433
84 G_UAVGFLOOR = 69, // GenericOpcodes.td:441
85 G_UAVGCEIL = 70, // GenericOpcodes.td:448
86 G_SAVGFLOOR = 71, // GenericOpcodes.td:455
87 G_SAVGCEIL = 72, // GenericOpcodes.td:462
88 G_IMPLICIT_DEF = 73, // GenericOpcodes.td:111
89 G_PHI = 74, // GenericOpcodes.td:118
90 G_FRAME_INDEX = 75, // GenericOpcodes.td:125
91 G_GLOBAL_VALUE = 76, // GenericOpcodes.td:131
92 G_PTRAUTH_GLOBAL_VALUE = 77, // GenericOpcodes.td:137
93 G_CONSTANT_POOL = 78, // GenericOpcodes.td:143
94 G_EXTRACT = 79, // GenericOpcodes.td:1540
95 G_UNMERGE_VALUES = 80, // GenericOpcodes.td:1553
96 G_INSERT = 81, // GenericOpcodes.td:1562
97 G_MERGE_VALUES = 82, // GenericOpcodes.td:1572
98 G_BUILD_VECTOR = 83, // GenericOpcodes.td:1592
99 G_BUILD_VECTOR_TRUNC = 84, // GenericOpcodes.td:1602
100 G_CONCAT_VECTORS = 85, // GenericOpcodes.td:1609
101 G_PTRTOINT = 86, // GenericOpcodes.td:155
102 G_INTTOPTR = 87, // GenericOpcodes.td:149
103 G_BITCAST = 88, // GenericOpcodes.td:161
104 G_FREEZE = 89, // GenericOpcodes.td:284
105 G_CONSTANT_FOLD_BARRIER = 90, // GenericOpcodes.td:1969
106 G_INTRINSIC_FPTRUNC_ROUND = 91, // GenericOpcodes.td:1298
107 G_INTRINSIC_TRUNC = 92, // GenericOpcodes.td:1304
108 G_INTRINSIC_ROUND = 93, // GenericOpcodes.td:1310
109 G_INTRINSIC_LRINT = 94, // GenericOpcodes.td:1316
110 G_INTRINSIC_LLRINT = 95, // GenericOpcodes.td:1322
111 G_INTRINSIC_ROUNDEVEN = 96, // GenericOpcodes.td:1328
112 G_READCYCLECOUNTER = 97, // GenericOpcodes.td:1334
113 G_READSTEADYCOUNTER = 98, // GenericOpcodes.td:1340
114 G_LOAD = 99, // GenericOpcodes.td:1367
115 G_SEXTLOAD = 100, // GenericOpcodes.td:1376
116 G_ZEXTLOAD = 101, // GenericOpcodes.td:1384
117 G_FPEXTLOAD = 102, // GenericOpcodes.td:1393
118 G_INDEXED_LOAD = 103, // GenericOpcodes.td:1403
119 G_INDEXED_SEXTLOAD = 104, // GenericOpcodes.td:1412
120 G_INDEXED_ZEXTLOAD = 105, // GenericOpcodes.td:1420
121 G_STORE = 106, // GenericOpcodes.td:1428
122 G_FPTRUNCSTORE = 107, // GenericOpcodes.td:1438
123 G_INDEXED_STORE = 108, // GenericOpcodes.td:1446
124 G_ATOMIC_CMPXCHG_WITH_SUCCESS = 109, // GenericOpcodes.td:1457
125 G_ATOMIC_CMPXCHG = 110, // GenericOpcodes.td:1468
126 G_ATOMICRMW_XCHG = 111, // GenericOpcodes.td:1488
127 G_ATOMICRMW_ADD = 112, // GenericOpcodes.td:1489
128 G_ATOMICRMW_SUB = 113, // GenericOpcodes.td:1490
129 G_ATOMICRMW_AND = 114, // GenericOpcodes.td:1491
130 G_ATOMICRMW_NAND = 115, // GenericOpcodes.td:1492
131 G_ATOMICRMW_OR = 116, // GenericOpcodes.td:1493
132 G_ATOMICRMW_XOR = 117, // GenericOpcodes.td:1494
133 G_ATOMICRMW_MAX = 118, // GenericOpcodes.td:1495
134 G_ATOMICRMW_MIN = 119, // GenericOpcodes.td:1496
135 G_ATOMICRMW_UMAX = 120, // GenericOpcodes.td:1497
136 G_ATOMICRMW_UMIN = 121, // GenericOpcodes.td:1498
137 G_ATOMICRMW_FADD = 122, // GenericOpcodes.td:1509
138 G_ATOMICRMW_FSUB = 123, // GenericOpcodes.td:1510
139 G_ATOMICRMW_FMAX = 124, // GenericOpcodes.td:1511
140 G_ATOMICRMW_FMIN = 125, // GenericOpcodes.td:1512
141 G_ATOMICRMW_FMAXIMUM = 126, // GenericOpcodes.td:1513
142 G_ATOMICRMW_FMINIMUM = 127, // GenericOpcodes.td:1514
143 G_ATOMICRMW_FMAXIMUMNUM = 128, // GenericOpcodes.td:1515
144 G_ATOMICRMW_FMINIMUMNUM = 129, // GenericOpcodes.td:1516
145 G_ATOMICRMW_UINC_WRAP = 130, // GenericOpcodes.td:1499
146 G_ATOMICRMW_UDEC_WRAP = 131, // GenericOpcodes.td:1500
147 G_ATOMICRMW_USUB_COND = 132, // GenericOpcodes.td:1501
148 G_ATOMICRMW_USUB_SAT = 133, // GenericOpcodes.td:1502
149 G_FENCE = 134, // GenericOpcodes.td:1518
150 G_PREFETCH = 135, // GenericOpcodes.td:1525
151 G_BRCOND = 136, // GenericOpcodes.td:1665
152 G_BRINDIRECT = 137, // GenericOpcodes.td:1674
153 G_INVOKE_REGION_START = 138, // GenericOpcodes.td:1697
154 G_INTRINSIC = 139, // GenericOpcodes.td:1617
155 G_INTRINSIC_W_SIDE_EFFECTS = 140, // GenericOpcodes.td:1624
156 G_INTRINSIC_CONVERGENT = 141, // GenericOpcodes.td:1633
157 G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 142, // GenericOpcodes.td:1641
158 G_ANYEXT = 143, // GenericOpcodes.td:44
159 G_TRUNC = 144, // GenericOpcodes.td:83
160 G_TRUNC_SSAT_S = 145, // GenericOpcodes.td:91
161 G_TRUNC_SSAT_U = 146, // GenericOpcodes.td:98
162 G_TRUNC_USAT_U = 147, // GenericOpcodes.td:105
163 G_CONSTANT = 148, // GenericOpcodes.td:169
164 G_FCONSTANT = 149, // GenericOpcodes.td:177
165 G_VASTART = 150, // GenericOpcodes.td:184
166 G_VAARG = 151, // GenericOpcodes.td:191
167 G_SEXT = 152, // GenericOpcodes.td:52
168 G_SEXT_INREG = 153, // GenericOpcodes.td:66
169 G_ZEXT = 154, // GenericOpcodes.td:74
170 G_SHL = 155, // GenericOpcodes.td:404
171 G_LSHR = 156, // GenericOpcodes.td:411
172 G_ASHR = 157, // GenericOpcodes.td:418
173 G_FSHL = 158, // GenericOpcodes.td:470
174 G_FSHR = 159, // GenericOpcodes.td:478
175 G_ROTR = 160, // GenericOpcodes.td:485
176 G_ROTL = 161, // GenericOpcodes.td:492
177 G_ICMP = 162, // GenericOpcodes.td:499
178 G_FCMP = 163, // GenericOpcodes.td:506
179 G_SCMP = 164, // GenericOpcodes.td:513
180 G_UCMP = 165, // GenericOpcodes.td:520
181 G_SELECT = 166, // GenericOpcodes.td:527
182 G_UADDO = 167, // GenericOpcodes.td:619
183 G_UADDE = 168, // GenericOpcodes.td:627
184 G_USUBO = 169, // GenericOpcodes.td:649
185 G_USUBE = 170, // GenericOpcodes.td:655
186 G_SADDO = 171, // GenericOpcodes.td:634
187 G_SADDE = 172, // GenericOpcodes.td:642
188 G_SSUBO = 173, // GenericOpcodes.td:662
189 G_SSUBE = 174, // GenericOpcodes.td:669
190 G_UMULO = 175, // GenericOpcodes.td:676
191 G_SMULO = 176, // GenericOpcodes.td:684
192 G_UMULH = 177, // GenericOpcodes.td:693
193 G_SMULH = 178, // GenericOpcodes.td:702
194 G_UADDSAT = 179, // GenericOpcodes.td:714
195 G_SADDSAT = 180, // GenericOpcodes.td:722
196 G_USUBSAT = 181, // GenericOpcodes.td:730
197 G_SSUBSAT = 182, // GenericOpcodes.td:738
198 G_USHLSAT = 183, // GenericOpcodes.td:746
199 G_SSHLSAT = 184, // GenericOpcodes.td:754
200 G_SMULFIX = 185, // GenericOpcodes.td:766
201 G_UMULFIX = 186, // GenericOpcodes.td:773
202 G_SMULFIXSAT = 187, // GenericOpcodes.td:783
203 G_UMULFIXSAT = 188, // GenericOpcodes.td:790
204 G_SDIVFIX = 189, // GenericOpcodes.td:801
205 G_UDIVFIX = 190, // GenericOpcodes.td:808
206 G_SDIVFIXSAT = 191, // GenericOpcodes.td:818
207 G_UDIVFIXSAT = 192, // GenericOpcodes.td:825
208 G_FADD = 193, // GenericOpcodes.td:998
209 G_FSUB = 194, // GenericOpcodes.td:1006
210 G_FMUL = 195, // GenericOpcodes.td:1014
211 G_FMA = 196, // GenericOpcodes.td:1023
212 G_FMAD = 197, // GenericOpcodes.td:1032
213 G_FDIV = 198, // GenericOpcodes.td:1040
214 G_FREM = 199, // GenericOpcodes.td:1047
215 G_FMODF = 200, // GenericOpcodes.td:1054
216 G_FPOW = 201, // GenericOpcodes.td:1061
217 G_FPOWI = 202, // GenericOpcodes.td:1068
218 G_FEXP = 203, // GenericOpcodes.td:1075
219 G_FEXP2 = 204, // GenericOpcodes.td:1082
220 G_FEXP10 = 205, // GenericOpcodes.td:1089
221 G_FLOG = 206, // GenericOpcodes.td:1096
222 G_FLOG2 = 207, // GenericOpcodes.td:1103
223 G_FLOG10 = 208, // GenericOpcodes.td:1110
224 G_FLDEXP = 209, // GenericOpcodes.td:1117
225 G_FFREXP = 210, // GenericOpcodes.td:1124
226 G_FNEG = 211, // GenericOpcodes.td:836
227 G_FPEXT = 212, // GenericOpcodes.td:842
228 G_FPTRUNC = 213, // GenericOpcodes.td:848
229 G_FPTOSI = 214, // GenericOpcodes.td:854
230 G_FPTOUI = 215, // GenericOpcodes.td:860
231 G_SITOFP = 216, // GenericOpcodes.td:866
232 G_UITOFP = 217, // GenericOpcodes.td:872
233 G_FPTOSI_SAT = 218, // GenericOpcodes.td:878
234 G_FPTOUI_SAT = 219, // GenericOpcodes.td:884
235 G_FABS = 220, // GenericOpcodes.td:890
236 G_FCOPYSIGN = 221, // GenericOpcodes.td:896
237 G_IS_FPCLASS = 222, // GenericOpcodes.td:909
238 G_FCANONICALIZE = 223, // GenericOpcodes.td:902
239 G_FMINNUM = 224, // GenericOpcodes.td:922
240 G_FMAXNUM = 225, // GenericOpcodes.td:929
241 G_FMINNUM_IEEE = 226, // GenericOpcodes.td:947
242 G_FMAXNUM_IEEE = 227, // GenericOpcodes.td:954
243 G_FMINIMUM = 228, // GenericOpcodes.td:964
244 G_FMAXIMUM = 229, // GenericOpcodes.td:971
245 G_FMINIMUMNUM = 230, // GenericOpcodes.td:979
246 G_FMAXIMUMNUM = 231, // GenericOpcodes.td:986
247 G_GET_FPENV = 232, // GenericOpcodes.td:1254
248 G_SET_FPENV = 233, // GenericOpcodes.td:1261
249 G_RESET_FPENV = 234, // GenericOpcodes.td:1268
250 G_GET_FPMODE = 235, // GenericOpcodes.td:1275
251 G_SET_FPMODE = 236, // GenericOpcodes.td:1282
252 G_RESET_FPMODE = 237, // GenericOpcodes.td:1289
253 G_GET_ROUNDING = 238, // GenericOpcodes.td:1346
254 G_SET_ROUNDING = 239, // GenericOpcodes.td:1352
255 G_PTR_ADD = 240, // GenericOpcodes.td:534
256 G_PTRMASK = 241, // GenericOpcodes.td:542
257 G_SMIN = 242, // GenericOpcodes.td:549
258 G_SMAX = 243, // GenericOpcodes.td:557
259 G_UMIN = 244, // GenericOpcodes.td:565
260 G_UMAX = 245, // GenericOpcodes.td:573
261 G_ABS = 246, // GenericOpcodes.td:581
262 G_LROUND = 247, // GenericOpcodes.td:291
263 G_LLROUND = 248, // GenericOpcodes.td:297
264 G_BR = 249, // GenericOpcodes.td:1655
265 G_BRJT = 250, // GenericOpcodes.td:1685
266 G_VSCALE = 251, // GenericOpcodes.td:1583
267 G_INSERT_SUBVECTOR = 252, // GenericOpcodes.td:1729
268 G_EXTRACT_SUBVECTOR = 253, // GenericOpcodes.td:1737
269 G_INSERT_VECTOR_ELT = 254, // GenericOpcodes.td:1745
270 G_EXTRACT_VECTOR_ELT = 255, // GenericOpcodes.td:1753
271 G_SHUFFLE_VECTOR = 256, // GenericOpcodes.td:1764
272 G_SPLAT_VECTOR = 257, // GenericOpcodes.td:1772
273 G_STEP_VECTOR = 258, // GenericOpcodes.td:1780
274 G_VECTOR_COMPRESS = 259, // GenericOpcodes.td:1787
275 G_CTTZ = 260, // GenericOpcodes.td:211
276 G_CTTZ_ZERO_POISON = 261, // GenericOpcodes.td:217
277 G_CTLZ = 262, // GenericOpcodes.td:199
278 G_CTLZ_ZERO_POISON = 263, // GenericOpcodes.td:205
279 G_CTLS = 264, // GenericOpcodes.td:223
280 G_CTPOP = 265, // GenericOpcodes.td:229
281 G_BSWAP = 266, // GenericOpcodes.td:235
282 G_BITREVERSE = 267, // GenericOpcodes.td:242
283 G_CLMUL = 268, // GenericOpcodes.td:588
284 G_CLMULH = 269, // GenericOpcodes.td:596
285 G_CLMULR = 270, // GenericOpcodes.td:606
286 G_FCEIL = 271, // GenericOpcodes.td:1131
287 G_FCOS = 272, // GenericOpcodes.td:1138
288 G_FSIN = 273, // GenericOpcodes.td:1145
289 G_FSINCOS = 274, // GenericOpcodes.td:1152
290 G_FTAN = 275, // GenericOpcodes.td:1159
291 G_FACOS = 276, // GenericOpcodes.td:1166
292 G_FASIN = 277, // GenericOpcodes.td:1173
293 G_FATAN = 278, // GenericOpcodes.td:1180
294 G_FATAN2 = 279, // GenericOpcodes.td:1187
295 G_FCOSH = 280, // GenericOpcodes.td:1194
296 G_FSINH = 281, // GenericOpcodes.td:1201
297 G_FTANH = 282, // GenericOpcodes.td:1208
298 G_FSQRT = 283, // GenericOpcodes.td:1218
299 G_FFLOOR = 284, // GenericOpcodes.td:1225
300 G_FRINT = 285, // GenericOpcodes.td:1232
301 G_FNEARBYINT = 286, // GenericOpcodes.td:1239
302 G_ADDRSPACE_CAST = 287, // GenericOpcodes.td:248
303 G_BLOCK_ADDR = 288, // GenericOpcodes.td:254
304 G_JUMP_TABLE = 289, // GenericOpcodes.td:260
305 G_DYN_STACKALLOC = 290, // GenericOpcodes.td:266
306 G_STACKSAVE = 291, // GenericOpcodes.td:272
307 G_STACKRESTORE = 292, // GenericOpcodes.td:278
308 G_STRICT_FADD = 293, // GenericOpcodes.td:1839
309 G_STRICT_FSUB = 294, // GenericOpcodes.td:1840
310 G_STRICT_FMUL = 295, // GenericOpcodes.td:1841
311 G_STRICT_FDIV = 296, // GenericOpcodes.td:1842
312 G_STRICT_FREM = 297, // GenericOpcodes.td:1843
313 G_STRICT_FMA = 298, // GenericOpcodes.td:1844
314 G_STRICT_FSQRT = 299, // GenericOpcodes.td:1845
315 G_STRICT_FLDEXP = 300, // GenericOpcodes.td:1846
316 G_STRICT_FCMP = 301, // GenericOpcodes.td:1847
317 G_STRICT_FCMPS = 302, // GenericOpcodes.td:1848
318 G_READ_REGISTER = 303, // GenericOpcodes.td:1704
319 G_WRITE_REGISTER = 304, // GenericOpcodes.td:1714
320 G_MEMCPY = 305, // GenericOpcodes.td:1854
321 G_MEMCPY_INLINE = 306, // GenericOpcodes.td:1862
322 G_MEMMOVE = 307, // GenericOpcodes.td:1870
323 G_MEMSET = 308, // GenericOpcodes.td:1878
324 G_BZERO = 309, // GenericOpcodes.td:1885
325 G_MEMSET_INLINE = 310, // GenericOpcodes.td:1892
326 G_TRAP = 311, // GenericOpcodes.td:1902
327 G_DEBUGTRAP = 312, // GenericOpcodes.td:1909
328 G_UBSANTRAP = 313, // GenericOpcodes.td:1915
329 G_VECREDUCE_SEQ_FADD = 314, // GenericOpcodes.td:1803
330 G_VECREDUCE_SEQ_FMUL = 315, // GenericOpcodes.td:1809
331 G_VECREDUCE_FADD = 316, // GenericOpcodes.td:1815
332 G_VECREDUCE_FMUL = 317, // GenericOpcodes.td:1816
333 G_VECREDUCE_FMAX = 318, // GenericOpcodes.td:1818
334 G_VECREDUCE_FMIN = 319, // GenericOpcodes.td:1819
335 G_VECREDUCE_FMAXIMUM = 320, // GenericOpcodes.td:1820
336 G_VECREDUCE_FMINIMUM = 321, // GenericOpcodes.td:1821
337 G_VECREDUCE_FMAXIMUMNUM = 322, // GenericOpcodes.td:1822
338 G_VECREDUCE_FMINIMUMNUM = 323, // GenericOpcodes.td:1823
339 G_VECREDUCE_ADD = 324, // GenericOpcodes.td:1825
340 G_VECREDUCE_MUL = 325, // GenericOpcodes.td:1826
341 G_VECREDUCE_AND = 326, // GenericOpcodes.td:1827
342 G_VECREDUCE_OR = 327, // GenericOpcodes.td:1828
343 G_VECREDUCE_XOR = 328, // GenericOpcodes.td:1829
344 G_VECREDUCE_SMAX = 329, // GenericOpcodes.td:1830
345 G_VECREDUCE_SMIN = 330, // GenericOpcodes.td:1831
346 G_VECREDUCE_UMAX = 331, // GenericOpcodes.td:1832
347 G_VECREDUCE_UMIN = 332, // GenericOpcodes.td:1833
348 G_SBFX = 333, // GenericOpcodes.td:1927
349 G_UBFX = 334, // GenericOpcodes.td:1935
350 ADD16mc = 335, // MSP430InstrInfo.td:499
351 ADD16mi = 336, // MSP430InstrInfo.td:505
352 ADD16mm = 337, // MSP430InstrInfo.td:512
353 ADD16mn = 338, // MSP430InstrInfo.td:518
354 ADD16mp = 339, // MSP430InstrInfo.td:522
355 ADD16mr = 340, // MSP430InstrInfo.td:493
356 ADD16rc = 341, // MSP430InstrInfo.td:480
357 ADD16ri = 342, // MSP430InstrInfo.td:486
358 ADD16rm = 343, // MSP430InstrInfo.td:462
359 ADD16rn = 344, // MSP430InstrInfo.td:467
360 ADD16rp = 345, // MSP430InstrInfo.td:474
361 ADD16rr = 346, // MSP430InstrInfo.td:455
362 ADD8mc = 347, // MSP430InstrInfo.td:496
363 ADD8mi = 348, // MSP430InstrInfo.td:502
364 ADD8mm = 349, // MSP430InstrInfo.td:508
365 ADD8mn = 350, // MSP430InstrInfo.td:516
366 ADD8mp = 351, // MSP430InstrInfo.td:520
367 ADD8mr = 352, // MSP430InstrInfo.td:490
368 ADD8rc = 353, // MSP430InstrInfo.td:477
369 ADD8ri = 354, // MSP430InstrInfo.td:483
370 ADD8rm = 355, // MSP430InstrInfo.td:459
371 ADD8rn = 356, // MSP430InstrInfo.td:465
372 ADD8rp = 357, // MSP430InstrInfo.td:472
373 ADD8rr = 358, // MSP430InstrInfo.td:452
374 ADDC16mc = 359, // MSP430InstrInfo.td:499
375 ADDC16mi = 360, // MSP430InstrInfo.td:505
376 ADDC16mm = 361, // MSP430InstrInfo.td:512
377 ADDC16mn = 362, // MSP430InstrInfo.td:518
378 ADDC16mp = 363, // MSP430InstrInfo.td:522
379 ADDC16mr = 364, // MSP430InstrInfo.td:493
380 ADDC16rc = 365, // MSP430InstrInfo.td:480
381 ADDC16ri = 366, // MSP430InstrInfo.td:486
382 ADDC16rm = 367, // MSP430InstrInfo.td:462
383 ADDC16rn = 368, // MSP430InstrInfo.td:467
384 ADDC16rp = 369, // MSP430InstrInfo.td:474
385 ADDC16rr = 370, // MSP430InstrInfo.td:455
386 ADDC8mc = 371, // MSP430InstrInfo.td:496
387 ADDC8mi = 372, // MSP430InstrInfo.td:502
388 ADDC8mm = 373, // MSP430InstrInfo.td:508
389 ADDC8mn = 374, // MSP430InstrInfo.td:516
390 ADDC8mp = 375, // MSP430InstrInfo.td:520
391 ADDC8mr = 376, // MSP430InstrInfo.td:490
392 ADDC8rc = 377, // MSP430InstrInfo.td:477
393 ADDC8ri = 378, // MSP430InstrInfo.td:483
394 ADDC8rm = 379, // MSP430InstrInfo.td:459
395 ADDC8rn = 380, // MSP430InstrInfo.td:465
396 ADDC8rp = 381, // MSP430InstrInfo.td:472
397 ADDC8rr = 382, // MSP430InstrInfo.td:452
398 ADDframe = 383, // MSP430InstrInfo.td:183
399 ADJCALLSTACKDOWN = 384, // MSP430InstrInfo.td:174
400 ADJCALLSTACKUP = 385, // MSP430InstrInfo.td:177
401 AND16mc = 386, // MSP430InstrInfo.td:499
402 AND16mi = 387, // MSP430InstrInfo.td:505
403 AND16mm = 388, // MSP430InstrInfo.td:512
404 AND16mn = 389, // MSP430InstrInfo.td:518
405 AND16mp = 390, // MSP430InstrInfo.td:522
406 AND16mr = 391, // MSP430InstrInfo.td:493
407 AND16rc = 392, // MSP430InstrInfo.td:480
408 AND16ri = 393, // MSP430InstrInfo.td:486
409 AND16rm = 394, // MSP430InstrInfo.td:462
410 AND16rn = 395, // MSP430InstrInfo.td:467
411 AND16rp = 396, // MSP430InstrInfo.td:474
412 AND16rr = 397, // MSP430InstrInfo.td:455
413 AND8mc = 398, // MSP430InstrInfo.td:496
414 AND8mi = 399, // MSP430InstrInfo.td:502
415 AND8mm = 400, // MSP430InstrInfo.td:508
416 AND8mn = 401, // MSP430InstrInfo.td:516
417 AND8mp = 402, // MSP430InstrInfo.td:520
418 AND8mr = 403, // MSP430InstrInfo.td:490
419 AND8rc = 404, // MSP430InstrInfo.td:477
420 AND8ri = 405, // MSP430InstrInfo.td:483
421 AND8rm = 406, // MSP430InstrInfo.td:459
422 AND8rn = 407, // MSP430InstrInfo.td:465
423 AND8rp = 408, // MSP430InstrInfo.td:472
424 AND8rr = 409, // MSP430InstrInfo.td:452
425 BIC16mc = 410, // MSP430InstrInfo.td:499
426 BIC16mi = 411, // MSP430InstrInfo.td:505
427 BIC16mm = 412, // MSP430InstrInfo.td:512
428 BIC16mn = 413, // MSP430InstrInfo.td:518
429 BIC16mp = 414, // MSP430InstrInfo.td:522
430 BIC16mr = 415, // MSP430InstrInfo.td:493
431 BIC16rc = 416, // MSP430InstrInfo.td:480
432 BIC16ri = 417, // MSP430InstrInfo.td:486
433 BIC16rm = 418, // MSP430InstrInfo.td:462
434 BIC16rn = 419, // MSP430InstrInfo.td:467
435 BIC16rp = 420, // MSP430InstrInfo.td:474
436 BIC16rr = 421, // MSP430InstrInfo.td:455
437 BIC8mc = 422, // MSP430InstrInfo.td:496
438 BIC8mi = 423, // MSP430InstrInfo.td:502
439 BIC8mm = 424, // MSP430InstrInfo.td:508
440 BIC8mn = 425, // MSP430InstrInfo.td:516
441 BIC8mp = 426, // MSP430InstrInfo.td:520
442 BIC8mr = 427, // MSP430InstrInfo.td:490
443 BIC8rc = 428, // MSP430InstrInfo.td:477
444 BIC8ri = 429, // MSP430InstrInfo.td:483
445 BIC8rm = 430, // MSP430InstrInfo.td:459
446 BIC8rn = 431, // MSP430InstrInfo.td:465
447 BIC8rp = 432, // MSP430InstrInfo.td:472
448 BIC8rr = 433, // MSP430InstrInfo.td:452
449 BIS16mc = 434, // MSP430InstrInfo.td:499
450 BIS16mi = 435, // MSP430InstrInfo.td:505
451 BIS16mm = 436, // MSP430InstrInfo.td:512
452 BIS16mn = 437, // MSP430InstrInfo.td:518
453 BIS16mp = 438, // MSP430InstrInfo.td:522
454 BIS16mr = 439, // MSP430InstrInfo.td:493
455 BIS16rc = 440, // MSP430InstrInfo.td:480
456 BIS16ri = 441, // MSP430InstrInfo.td:486
457 BIS16rm = 442, // MSP430InstrInfo.td:462
458 BIS16rn = 443, // MSP430InstrInfo.td:467
459 BIS16rp = 444, // MSP430InstrInfo.td:474
460 BIS16rr = 445, // MSP430InstrInfo.td:455
461 BIS8mc = 446, // MSP430InstrInfo.td:496
462 BIS8mi = 447, // MSP430InstrInfo.td:502
463 BIS8mm = 448, // MSP430InstrInfo.td:508
464 BIS8mn = 449, // MSP430InstrInfo.td:516
465 BIS8mp = 450, // MSP430InstrInfo.td:520
466 BIS8mr = 451, // MSP430InstrInfo.td:490
467 BIS8rc = 452, // MSP430InstrInfo.td:477
468 BIS8ri = 453, // MSP430InstrInfo.td:483
469 BIS8rm = 454, // MSP430InstrInfo.td:459
470 BIS8rn = 455, // MSP430InstrInfo.td:465
471 BIS8rp = 456, // MSP430InstrInfo.td:472
472 BIS8rr = 457, // MSP430InstrInfo.td:452
473 BIT16mc = 458, // MSP430InstrInfo.td:861
474 BIT16mi = 459, // MSP430InstrInfo.td:870
475 BIT16mm = 460, // MSP430InstrInfo.td:881
476 BIT16mn = 461, // MSP430InstrInfo.td:889
477 BIT16mp = 462, // MSP430InstrInfo.td:894
478 BIT16mr = 463, // MSP430InstrInfo.td:852
479 BIT16rc = 464, // MSP430InstrInfo.td:815
480 BIT16ri = 465, // MSP430InstrInfo.td:824
481 BIT16rm = 466, // MSP430InstrInfo.td:833
482 BIT16rn = 467, // MSP430InstrInfo.td:840
483 BIT16rp = 468, // MSP430InstrInfo.td:845
484 BIT16rr = 469, // MSP430InstrInfo.td:806
485 BIT8mc = 470, // MSP430InstrInfo.td:857
486 BIT8mi = 471, // MSP430InstrInfo.td:866
487 BIT8mm = 472, // MSP430InstrInfo.td:875
488 BIT8mn = 473, // MSP430InstrInfo.td:887
489 BIT8mp = 474, // MSP430InstrInfo.td:892
490 BIT8mr = 475, // MSP430InstrInfo.td:848
491 BIT8rc = 476, // MSP430InstrInfo.td:811
492 BIT8ri = 477, // MSP430InstrInfo.td:820
493 BIT8rm = 478, // MSP430InstrInfo.td:829
494 BIT8rn = 479, // MSP430InstrInfo.td:838
495 BIT8rp = 480, // MSP430InstrInfo.td:843
496 BIT8rr = 481, // MSP430InstrInfo.td:802
497 Bi = 482, // MSP430InstrInfo.td:255
498 Bm = 483, // MSP430InstrInfo.td:261
499 Br = 484, // MSP430InstrInfo.td:258
500 CALLi = 485, // MSP430InstrInfo.td:284
501 CALLm = 486, // MSP430InstrInfo.td:290
502 CALLn = 487, // MSP430InstrInfo.td:293
503 CALLp = 488, // MSP430InstrInfo.td:294
504 CALLr = 489, // MSP430InstrInfo.td:287
505 CMP16mc = 490, // MSP430InstrInfo.td:738
506 CMP16mi = 491, // MSP430InstrInfo.td:748
507 CMP16mm = 492, // MSP430InstrInfo.td:785
508 CMP16mn = 493, // MSP430InstrInfo.td:791
509 CMP16mp = 494, // MSP430InstrInfo.td:796
510 CMP16mr = 495, // MSP430InstrInfo.td:777
511 CMP16rc = 496, // MSP430InstrInfo.td:720
512 CMP16ri = 497, // MSP430InstrInfo.td:729
513 CMP16rm = 498, // MSP430InstrInfo.td:758
514 CMP16rn = 499, // MSP430InstrInfo.td:765
515 CMP16rp = 500, // MSP430InstrInfo.td:770
516 CMP16rr = 501, // MSP430InstrInfo.td:711
517 CMP8mc = 502, // MSP430InstrInfo.td:734
518 CMP8mi = 503, // MSP430InstrInfo.td:743
519 CMP8mm = 504, // MSP430InstrInfo.td:781
520 CMP8mn = 505, // MSP430InstrInfo.td:789
521 CMP8mp = 506, // MSP430InstrInfo.td:794
522 CMP8mr = 507, // MSP430InstrInfo.td:773
523 CMP8rc = 508, // MSP430InstrInfo.td:716
524 CMP8ri = 509, // MSP430InstrInfo.td:725
525 CMP8rm = 510, // MSP430InstrInfo.td:754
526 CMP8rn = 511, // MSP430InstrInfo.td:763
527 CMP8rp = 512, // MSP430InstrInfo.td:768
528 CMP8rr = 513, // MSP430InstrInfo.td:707
529 DADD16mc = 514, // MSP430InstrInfo.td:499
530 DADD16mi = 515, // MSP430InstrInfo.td:505
531 DADD16mm = 516, // MSP430InstrInfo.td:512
532 DADD16mn = 517, // MSP430InstrInfo.td:518
533 DADD16mp = 518, // MSP430InstrInfo.td:522
534 DADD16mr = 519, // MSP430InstrInfo.td:493
535 DADD16rc = 520, // MSP430InstrInfo.td:480
536 DADD16ri = 521, // MSP430InstrInfo.td:486
537 DADD16rm = 522, // MSP430InstrInfo.td:462
538 DADD16rn = 523, // MSP430InstrInfo.td:467
539 DADD16rp = 524, // MSP430InstrInfo.td:474
540 DADD16rr = 525, // MSP430InstrInfo.td:455
541 DADD8mc = 526, // MSP430InstrInfo.td:496
542 DADD8mi = 527, // MSP430InstrInfo.td:502
543 DADD8mm = 528, // MSP430InstrInfo.td:508
544 DADD8mn = 529, // MSP430InstrInfo.td:516
545 DADD8mp = 530, // MSP430InstrInfo.td:520
546 DADD8mr = 531, // MSP430InstrInfo.td:490
547 DADD8rc = 532, // MSP430InstrInfo.td:477
548 DADD8ri = 533, // MSP430InstrInfo.td:483
549 DADD8rm = 534, // MSP430InstrInfo.td:459
550 DADD8rn = 535, // MSP430InstrInfo.td:465
551 DADD8rp = 536, // MSP430InstrInfo.td:472
552 DADD8rr = 537, // MSP430InstrInfo.td:452
553 JCC = 538, // MSP430InstrInfo.td:269
554 JMP = 539, // MSP430InstrInfo.td:248
555 MOV16mc = 540, // MSP430InstrInfo.td:407
556 MOV16mi = 541, // MSP430InstrInfo.td:416
557 MOV16mm = 542, // MSP430InstrInfo.td:434
558 MOV16mn = 543, // MSP430InstrInfo.td:441
559 MOV16mr = 544, // MSP430InstrInfo.td:425
560 MOV16rc = 545, // MSP430InstrInfo.td:335
561 MOV16ri = 546, // MSP430InstrInfo.td:343
562 MOV16rm = 547, // MSP430InstrInfo.td:354
563 MOV16rn = 548, // MSP430InstrInfo.td:362
564 MOV16rp = 549, // MSP430InstrInfo.td:383
565 MOV16rr = 550, // MSP430InstrInfo.td:324
566 MOV8mc = 551, // MSP430InstrInfo.td:403
567 MOV8mi = 552, // MSP430InstrInfo.td:412
568 MOV8mm = 553, // MSP430InstrInfo.td:430
569 MOV8mn = 554, // MSP430InstrInfo.td:439
570 MOV8mr = 555, // MSP430InstrInfo.td:421
571 MOV8rc = 556, // MSP430InstrInfo.td:331
572 MOV8ri = 557, // MSP430InstrInfo.td:339
573 MOV8rm = 558, // MSP430InstrInfo.td:350
574 MOV8rn = 559, // MSP430InstrInfo.td:358
575 MOV8rp = 560, // MSP430InstrInfo.td:380
576 MOV8rr = 561, // MSP430InstrInfo.td:320
577 MOVZX16rm8 = 562, // MSP430InstrInfo.td:373
578 MOVZX16rr8 = 563, // MSP430InstrInfo.td:369
579 POP16r = 564, // MSP430InstrInfo.td:302
580 PUSH16c = 565, // MSP430InstrInfo.td:311
581 PUSH16i = 566, // MSP430InstrInfo.td:312
582 PUSH16r = 567, // MSP430InstrInfo.td:310
583 PUSH8r = 568, // MSP430InstrInfo.td:309
584 RET = 569, // MSP430InstrInfo.td:229
585 RETI = 570, // MSP430InstrInfo.td:235
586 RRA16m = 571, // MSP430InstrInfo.td:661
587 RRA16n = 572, // MSP430InstrInfo.td:667
588 RRA16p = 573, // MSP430InstrInfo.td:669
589 RRA16r = 574, // MSP430InstrInfo.td:619
590 RRA8m = 575, // MSP430InstrInfo.td:657
591 RRA8n = 576, // MSP430InstrInfo.td:666
592 RRA8p = 577, // MSP430InstrInfo.td:668
593 RRA8r = 578, // MSP430InstrInfo.td:615
594 RRC16m = 579, // MSP430InstrInfo.td:676
595 RRC16n = 580, // MSP430InstrInfo.td:682
596 RRC16p = 581, // MSP430InstrInfo.td:684
597 RRC16r = 582, // MSP430InstrInfo.td:629
598 RRC8m = 583, // MSP430InstrInfo.td:672
599 RRC8n = 584, // MSP430InstrInfo.td:681
600 RRC8p = 585, // MSP430InstrInfo.td:683
601 RRC8r = 586, // MSP430InstrInfo.td:625
602 Rrcl16 = 587, // MSP430InstrInfo.td:219
603 Rrcl8 = 588, // MSP430InstrInfo.td:217
604 SEXT16m = 589, // MSP430InstrInfo.td:688
605 SEXT16n = 590, // MSP430InstrInfo.td:693
606 SEXT16p = 591, // MSP430InstrInfo.td:694
607 SEXT16r = 592, // MSP430InstrInfo.td:635
608 SUB16mc = 593, // MSP430InstrInfo.td:499
609 SUB16mi = 594, // MSP430InstrInfo.td:505
610 SUB16mm = 595, // MSP430InstrInfo.td:512
611 SUB16mn = 596, // MSP430InstrInfo.td:518
612 SUB16mp = 597, // MSP430InstrInfo.td:522
613 SUB16mr = 598, // MSP430InstrInfo.td:493
614 SUB16rc = 599, // MSP430InstrInfo.td:480
615 SUB16ri = 600, // MSP430InstrInfo.td:486
616 SUB16rm = 601, // MSP430InstrInfo.td:462
617 SUB16rn = 602, // MSP430InstrInfo.td:467
618 SUB16rp = 603, // MSP430InstrInfo.td:474
619 SUB16rr = 604, // MSP430InstrInfo.td:455
620 SUB8mc = 605, // MSP430InstrInfo.td:496
621 SUB8mi = 606, // MSP430InstrInfo.td:502
622 SUB8mm = 607, // MSP430InstrInfo.td:508
623 SUB8mn = 608, // MSP430InstrInfo.td:516
624 SUB8mp = 609, // MSP430InstrInfo.td:520
625 SUB8mr = 610, // MSP430InstrInfo.td:490
626 SUB8rc = 611, // MSP430InstrInfo.td:477
627 SUB8ri = 612, // MSP430InstrInfo.td:483
628 SUB8rm = 613, // MSP430InstrInfo.td:459
629 SUB8rn = 614, // MSP430InstrInfo.td:465
630 SUB8rp = 615, // MSP430InstrInfo.td:472
631 SUB8rr = 616, // MSP430InstrInfo.td:452
632 SUBC16mc = 617, // MSP430InstrInfo.td:499
633 SUBC16mi = 618, // MSP430InstrInfo.td:505
634 SUBC16mm = 619, // MSP430InstrInfo.td:512
635 SUBC16mn = 620, // MSP430InstrInfo.td:518
636 SUBC16mp = 621, // MSP430InstrInfo.td:522
637 SUBC16mr = 622, // MSP430InstrInfo.td:493
638 SUBC16rc = 623, // MSP430InstrInfo.td:480
639 SUBC16ri = 624, // MSP430InstrInfo.td:486
640 SUBC16rm = 625, // MSP430InstrInfo.td:462
641 SUBC16rn = 626, // MSP430InstrInfo.td:467
642 SUBC16rp = 627, // MSP430InstrInfo.td:474
643 SUBC16rr = 628, // MSP430InstrInfo.td:455
644 SUBC8mc = 629, // MSP430InstrInfo.td:496
645 SUBC8mi = 630, // MSP430InstrInfo.td:502
646 SUBC8mm = 631, // MSP430InstrInfo.td:508
647 SUBC8mn = 632, // MSP430InstrInfo.td:516
648 SUBC8mp = 633, // MSP430InstrInfo.td:520
649 SUBC8mr = 634, // MSP430InstrInfo.td:490
650 SUBC8rc = 635, // MSP430InstrInfo.td:477
651 SUBC8ri = 636, // MSP430InstrInfo.td:483
652 SUBC8rm = 637, // MSP430InstrInfo.td:459
653 SUBC8rn = 638, // MSP430InstrInfo.td:465
654 SUBC8rp = 639, // MSP430InstrInfo.td:472
655 SUBC8rr = 640, // MSP430InstrInfo.td:452
656 SWPB16m = 641, // MSP430InstrInfo.td:698
657 SWPB16n = 642, // MSP430InstrInfo.td:702
658 SWPB16p = 643, // MSP430InstrInfo.td:703
659 SWPB16r = 644, // MSP430InstrInfo.td:648
660 Select16 = 645, // MSP430InstrInfo.td:193
661 Select8 = 646, // MSP430InstrInfo.td:189
662 Shl16 = 647, // MSP430InstrInfo.td:202
663 Shl8 = 648, // MSP430InstrInfo.td:199
664 Sra16 = 649, // MSP430InstrInfo.td:208
665 Sra8 = 650, // MSP430InstrInfo.td:205
666 Srl16 = 651, // MSP430InstrInfo.td:214
667 Srl8 = 652, // MSP430InstrInfo.td:211
668 XOR16mc = 653, // MSP430InstrInfo.td:499
669 XOR16mi = 654, // MSP430InstrInfo.td:505
670 XOR16mm = 655, // MSP430InstrInfo.td:512
671 XOR16mn = 656, // MSP430InstrInfo.td:518
672 XOR16mp = 657, // MSP430InstrInfo.td:522
673 XOR16mr = 658, // MSP430InstrInfo.td:493
674 XOR16rc = 659, // MSP430InstrInfo.td:480
675 XOR16ri = 660, // MSP430InstrInfo.td:486
676 XOR16rm = 661, // MSP430InstrInfo.td:462
677 XOR16rn = 662, // MSP430InstrInfo.td:467
678 XOR16rp = 663, // MSP430InstrInfo.td:474
679 XOR16rr = 664, // MSP430InstrInfo.td:455
680 XOR8mc = 665, // MSP430InstrInfo.td:496
681 XOR8mi = 666, // MSP430InstrInfo.td:502
682 XOR8mm = 667, // MSP430InstrInfo.td:508
683 XOR8mn = 668, // MSP430InstrInfo.td:516
684 XOR8mp = 669, // MSP430InstrInfo.td:520
685 XOR8mr = 670, // MSP430InstrInfo.td:490
686 XOR8rc = 671, // MSP430InstrInfo.td:477
687 XOR8ri = 672, // MSP430InstrInfo.td:483
688 XOR8rm = 673, // MSP430InstrInfo.td:459
689 XOR8rn = 674, // MSP430InstrInfo.td:465
690 XOR8rp = 675, // MSP430InstrInfo.td:472
691 XOR8rr = 676, // MSP430InstrInfo.td:452
692 ZEXT16r = 677, // MSP430InstrInfo.td:643
693 INSTRUCTION_LIST_END = 678
694 };
695
696} // namespace llvm::MSP430
697
698#endif // GET_INSTRINFO_ENUM
699
700#ifdef GET_INSTRINFO_SCHED_ENUM
701#undef GET_INSTRINFO_SCHED_ENUM
702
703namespace llvm::MSP430::Sched {
704
705 enum {
706 NoInstrModel = 0,
707 SCHED_LIST_END = 1
708 };
709
710} // namespace llvm::MSP430::Sched
711
712#endif // GET_INSTRINFO_SCHED_ENUM
713
714#if defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
715
716namespace llvm {
717
718struct MSP430InstrTable {
719 MCInstrDesc Insts[678];
720 static_assert(alignof(MCInstrDesc) >= alignof(MCPhysReg), "Unwanted padding between Insts and ImplicitOps");
721 MCPhysReg ImplicitOps[17];
722 char Padding[sizeof(MCOperandInfo) - sizeof ImplicitOps % sizeof(MCOperandInfo)];
723 static_assert(alignof(MCInstrDesc) >= alignof(MCOperandInfo), "Unwanted padding between Insts and OperandInfo");
724 MCOperandInfo OperandInfo[260];
725};
726} // namespace llvm
727
728#endif // defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
729
730#ifdef GET_INSTRINFO_MC_DESC
731#undef GET_INSTRINFO_MC_DESC
732
733namespace llvm {
734
735static_assert((sizeof MSP430InstrTable::ImplicitOps + sizeof MSP430InstrTable::Padding) % sizeof(MCOperandInfo) == 0);
736static constexpr unsigned MSP430OpInfoBase = (sizeof MSP430InstrTable::ImplicitOps + sizeof MSP430InstrTable::Padding) / sizeof(MCOperandInfo);
737
738extern const MSP430InstrTable MSP430Descs = {
739 {
740 { 677, 2, 1, 2, 0, 0, 0, MSP430OpInfoBase + 242, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ZEXT16r
741 { 676, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 207, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR8rr
742 { 675, 4, 2, 2, 0, 0, 1, MSP430OpInfoBase + 203, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR8rp
743 { 674, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR8rn
744 { 673, 4, 1, 4, 0, 0, 1, MSP430OpInfoBase + 196, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR8rm
745 { 672, 3, 1, 4, 0, 0, 1, MSP430OpInfoBase + 193, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR8ri
746 { 671, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 190, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR8rc
747 { 670, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 187, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR8mr
748 { 669, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR8mp
749 { 668, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR8mn
750 { 667, 4, 0, 6, 0, 0, 1, MSP430OpInfoBase + 157, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR8mm
751 { 666, 3, 0, 6, 0, 0, 1, MSP430OpInfoBase + 154, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR8mi
752 { 665, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 151, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR8mc
753 { 664, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 184, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR16rr
754 { 663, 4, 2, 2, 0, 0, 1, MSP430OpInfoBase + 180, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR16rp
755 { 662, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 177, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR16rn
756 { 661, 4, 1, 4, 0, 0, 1, MSP430OpInfoBase + 173, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR16rm
757 { 660, 3, 1, 4, 0, 0, 1, MSP430OpInfoBase + 170, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR16ri
758 { 659, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 167, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR16rc
759 { 658, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 164, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR16mr
760 { 657, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR16mp
761 { 656, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR16mn
762 { 655, 4, 0, 6, 0, 0, 1, MSP430OpInfoBase + 157, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR16mm
763 { 654, 3, 0, 6, 0, 0, 1, MSP430OpInfoBase + 154, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR16mi
764 { 653, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 151, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR16mc
765 { 652, 3, 1, 0, 0, 0, 1, MSP430OpInfoBase + 257, 0, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Srl8
766 { 651, 3, 1, 0, 0, 0, 1, MSP430OpInfoBase + 254, 0, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Srl16
767 { 650, 3, 1, 0, 0, 0, 1, MSP430OpInfoBase + 257, 0, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Sra8
768 { 649, 3, 1, 0, 0, 0, 1, MSP430OpInfoBase + 254, 0, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Sra16
769 { 648, 3, 1, 0, 0, 0, 1, MSP430OpInfoBase + 257, 0, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Shl8
770 { 647, 3, 1, 0, 0, 0, 1, MSP430OpInfoBase + 254, 0, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Shl16
771 { 646, 4, 1, 0, 0, 1, 0, MSP430OpInfoBase + 250, 0, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Select8
772 { 645, 4, 1, 0, 0, 1, 0, MSP430OpInfoBase + 246, 0, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Select16
773 { 644, 2, 1, 2, 0, 0, 0, MSP430OpInfoBase + 242, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SWPB16r
774 { 643, 1, 0, 2, 0, 0, 0, MSP430OpInfoBase + 232, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SWPB16p
775 { 642, 1, 0, 2, 0, 0, 0, MSP430OpInfoBase + 232, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SWPB16n
776 { 641, 2, 0, 4, 0, 0, 0, MSP430OpInfoBase + 230, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SWPB16m
777 { 640, 3, 1, 2, 0, 1, 1, MSP430OpInfoBase + 207, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC8rr
778 { 639, 4, 2, 2, 0, 1, 1, MSP430OpInfoBase + 203, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC8rp
779 { 638, 3, 1, 2, 0, 1, 1, MSP430OpInfoBase + 200, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC8rn
780 { 637, 4, 1, 4, 0, 1, 1, MSP430OpInfoBase + 196, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC8rm
781 { 636, 3, 1, 4, 0, 1, 1, MSP430OpInfoBase + 193, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC8ri
782 { 635, 3, 1, 2, 0, 1, 1, MSP430OpInfoBase + 190, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC8rc
783 { 634, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 187, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC8mr
784 { 633, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 161, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC8mp
785 { 632, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 161, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC8mn
786 { 631, 4, 0, 6, 0, 1, 1, MSP430OpInfoBase + 157, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC8mm
787 { 630, 3, 0, 6, 0, 1, 1, MSP430OpInfoBase + 154, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC8mi
788 { 629, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 151, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC8mc
789 { 628, 3, 1, 2, 0, 1, 1, MSP430OpInfoBase + 184, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC16rr
790 { 627, 4, 2, 2, 0, 1, 1, MSP430OpInfoBase + 180, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC16rp
791 { 626, 3, 1, 2, 0, 1, 1, MSP430OpInfoBase + 177, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC16rn
792 { 625, 4, 1, 4, 0, 1, 1, MSP430OpInfoBase + 173, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC16rm
793 { 624, 3, 1, 4, 0, 1, 1, MSP430OpInfoBase + 170, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC16ri
794 { 623, 3, 1, 2, 0, 1, 1, MSP430OpInfoBase + 167, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC16rc
795 { 622, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 164, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC16mr
796 { 621, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 161, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC16mp
797 { 620, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 161, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC16mn
798 { 619, 4, 0, 6, 0, 1, 1, MSP430OpInfoBase + 157, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC16mm
799 { 618, 3, 0, 6, 0, 1, 1, MSP430OpInfoBase + 154, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC16mi
800 { 617, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 151, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC16mc
801 { 616, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 207, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB8rr
802 { 615, 4, 2, 2, 0, 0, 1, MSP430OpInfoBase + 203, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB8rp
803 { 614, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB8rn
804 { 613, 4, 1, 4, 0, 0, 1, MSP430OpInfoBase + 196, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB8rm
805 { 612, 3, 1, 4, 0, 0, 1, MSP430OpInfoBase + 193, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB8ri
806 { 611, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 190, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB8rc
807 { 610, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 187, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB8mr
808 { 609, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB8mp
809 { 608, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB8mn
810 { 607, 4, 0, 6, 0, 0, 1, MSP430OpInfoBase + 157, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB8mm
811 { 606, 3, 0, 6, 0, 0, 1, MSP430OpInfoBase + 154, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB8mi
812 { 605, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 151, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB8mc
813 { 604, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 184, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB16rr
814 { 603, 4, 2, 2, 0, 0, 1, MSP430OpInfoBase + 180, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB16rp
815 { 602, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 177, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB16rn
816 { 601, 4, 1, 4, 0, 0, 1, MSP430OpInfoBase + 173, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB16rm
817 { 600, 3, 1, 4, 0, 0, 1, MSP430OpInfoBase + 170, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB16ri
818 { 599, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 167, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB16rc
819 { 598, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 164, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB16mr
820 { 597, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB16mp
821 { 596, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB16mn
822 { 595, 4, 0, 6, 0, 0, 1, MSP430OpInfoBase + 157, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB16mm
823 { 594, 3, 0, 6, 0, 0, 1, MSP430OpInfoBase + 154, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB16mi
824 { 593, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 151, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB16mc
825 { 592, 2, 1, 2, 0, 0, 1, MSP430OpInfoBase + 242, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SEXT16r
826 { 591, 1, 0, 2, 0, 0, 1, MSP430OpInfoBase + 232, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SEXT16p
827 { 590, 1, 0, 2, 0, 0, 1, MSP430OpInfoBase + 232, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SEXT16n
828 { 589, 2, 0, 4, 0, 0, 1, MSP430OpInfoBase + 230, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SEXT16m
829 { 588, 2, 1, 0, 0, 0, 1, MSP430OpInfoBase + 228, 0, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Rrcl8
830 { 587, 2, 1, 0, 0, 0, 1, MSP430OpInfoBase + 217, 0, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Rrcl16
831 { 586, 2, 1, 2, 0, 1, 1, MSP430OpInfoBase + 244, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RRC8r
832 { 585, 1, 0, 2, 0, 1, 1, MSP430OpInfoBase + 232, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RRC8p
833 { 584, 1, 0, 2, 0, 1, 1, MSP430OpInfoBase + 232, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RRC8n
834 { 583, 2, 0, 4, 0, 1, 1, MSP430OpInfoBase + 230, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RRC8m
835 { 582, 2, 1, 2, 0, 1, 1, MSP430OpInfoBase + 242, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RRC16r
836 { 581, 1, 0, 2, 0, 1, 1, MSP430OpInfoBase + 232, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RRC16p
837 { 580, 1, 0, 2, 0, 1, 1, MSP430OpInfoBase + 232, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RRC16n
838 { 579, 2, 0, 4, 0, 1, 1, MSP430OpInfoBase + 230, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RRC16m
839 { 578, 2, 1, 2, 0, 0, 1, MSP430OpInfoBase + 244, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RRA8r
840 { 577, 1, 0, 2, 0, 0, 1, MSP430OpInfoBase + 232, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RRA8p
841 { 576, 1, 0, 2, 0, 0, 1, MSP430OpInfoBase + 232, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RRA8n
842 { 575, 2, 0, 4, 0, 0, 1, MSP430OpInfoBase + 230, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RRA8m
843 { 574, 2, 1, 2, 0, 0, 1, MSP430OpInfoBase + 242, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RRA16r
844 { 573, 1, 0, 2, 0, 0, 1, MSP430OpInfoBase + 232, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RRA16p
845 { 572, 1, 0, 2, 0, 0, 1, MSP430OpInfoBase + 232, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RRA16n
846 { 571, 2, 0, 4, 0, 0, 1, MSP430OpInfoBase + 230, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RRA16m
847 { 570, 0, 0, 2, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RETI
848 { 569, 0, 0, 2, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RET
849 { 568, 1, 0, 2, 0, 1, 1, MSP430OpInfoBase + 241, 15, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PUSH8r
850 { 567, 1, 0, 2, 0, 1, 1, MSP430OpInfoBase + 28, 15, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PUSH16r
851 { 566, 1, 0, 4, 0, 1, 1, MSP430OpInfoBase + 1, 15, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PUSH16i
852 { 565, 1, 0, 2, 0, 1, 1, MSP430OpInfoBase + 0, 15, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PUSH16c
853 { 564, 1, 1, 2, 0, 1, 1, MSP430OpInfoBase + 28, 15, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // POP16r
854 { 563, 2, 1, 2, 0, 0, 0, MSP430OpInfoBase + 239, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOVZX16rr8
855 { 562, 3, 1, 4, 0, 0, 0, MSP430OpInfoBase + 212, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOVZX16rm8
856 { 561, 2, 1, 2, 0, 0, 0, MSP430OpInfoBase + 228, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV8rr
857 { 560, 3, 2, 2, 0, 0, 0, MSP430OpInfoBase + 236, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV8rp
858 { 559, 2, 1, 2, 0, 0, 0, MSP430OpInfoBase + 226, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV8rn
859 { 558, 3, 1, 4, 0, 0, 0, MSP430OpInfoBase + 223, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV8rm
860 { 557, 2, 1, 4, 0, 0, 0, MSP430OpInfoBase + 221, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV8ri
861 { 556, 2, 1, 2, 0, 0, 0, MSP430OpInfoBase + 219, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV8rc
862 { 555, 3, 0, 4, 0, 0, 0, MSP430OpInfoBase + 187, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV8mr
863 { 554, 3, 0, 4, 0, 0, 0, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV8mn
864 { 553, 4, 0, 6, 0, 0, 0, MSP430OpInfoBase + 157, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV8mm
865 { 552, 3, 0, 6, 0, 0, 0, MSP430OpInfoBase + 154, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV8mi
866 { 551, 3, 0, 4, 0, 0, 0, MSP430OpInfoBase + 151, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV8mc
867 { 550, 2, 1, 2, 0, 0, 0, MSP430OpInfoBase + 217, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV16rr
868 { 549, 3, 2, 2, 0, 0, 0, MSP430OpInfoBase + 233, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV16rp
869 { 548, 2, 1, 2, 0, 0, 0, MSP430OpInfoBase + 215, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV16rn
870 { 547, 3, 1, 4, 0, 0, 0, MSP430OpInfoBase + 212, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV16rm
871 { 546, 2, 1, 4, 0, 0, 0, MSP430OpInfoBase + 210, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV16ri
872 { 545, 2, 1, 2, 0, 0, 0, MSP430OpInfoBase + 34, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV16rc
873 { 544, 3, 0, 4, 0, 0, 0, MSP430OpInfoBase + 164, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV16mr
874 { 543, 3, 0, 4, 0, 0, 0, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV16mn
875 { 542, 4, 0, 6, 0, 0, 0, MSP430OpInfoBase + 157, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV16mm
876 { 541, 3, 0, 6, 0, 0, 0, MSP430OpInfoBase + 154, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV16mi
877 { 540, 3, 0, 4, 0, 0, 0, MSP430OpInfoBase + 151, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV16mc
878 { 539, 1, 0, 2, 0, 0, 0, MSP430OpInfoBase + 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JMP
879 { 538, 2, 0, 2, 0, 1, 0, MSP430OpInfoBase + 9, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JCC
880 { 537, 3, 1, 2, 0, 1, 1, MSP430OpInfoBase + 207, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD8rr
881 { 536, 4, 2, 2, 0, 1, 1, MSP430OpInfoBase + 203, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD8rp
882 { 535, 3, 1, 2, 0, 1, 1, MSP430OpInfoBase + 200, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD8rn
883 { 534, 4, 1, 4, 0, 1, 1, MSP430OpInfoBase + 196, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD8rm
884 { 533, 3, 1, 4, 0, 1, 1, MSP430OpInfoBase + 193, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD8ri
885 { 532, 3, 1, 2, 0, 1, 1, MSP430OpInfoBase + 190, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD8rc
886 { 531, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 187, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD8mr
887 { 530, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 161, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD8mp
888 { 529, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 161, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD8mn
889 { 528, 4, 0, 6, 0, 1, 1, MSP430OpInfoBase + 157, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD8mm
890 { 527, 3, 0, 6, 0, 1, 1, MSP430OpInfoBase + 154, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD8mi
891 { 526, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 151, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD8mc
892 { 525, 3, 1, 2, 0, 1, 1, MSP430OpInfoBase + 184, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD16rr
893 { 524, 4, 2, 2, 0, 1, 1, MSP430OpInfoBase + 180, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD16rp
894 { 523, 3, 1, 2, 0, 1, 1, MSP430OpInfoBase + 177, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD16rn
895 { 522, 4, 1, 4, 0, 1, 1, MSP430OpInfoBase + 173, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD16rm
896 { 521, 3, 1, 4, 0, 1, 1, MSP430OpInfoBase + 170, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD16ri
897 { 520, 3, 1, 2, 0, 1, 1, MSP430OpInfoBase + 167, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD16rc
898 { 519, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 164, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD16mr
899 { 518, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 161, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD16mp
900 { 517, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 161, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD16mn
901 { 516, 4, 0, 6, 0, 1, 1, MSP430OpInfoBase + 157, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD16mm
902 { 515, 3, 0, 6, 0, 1, 1, MSP430OpInfoBase + 154, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD16mi
903 { 514, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 151, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD16mc
904 { 513, 2, 0, 2, 0, 0, 1, MSP430OpInfoBase + 228, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP8rr
905 { 512, 2, 0, 2, 0, 0, 1, MSP430OpInfoBase + 226, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP8rp
906 { 511, 2, 0, 2, 0, 0, 1, MSP430OpInfoBase + 226, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP8rn
907 { 510, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 223, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP8rm
908 { 509, 2, 0, 4, 0, 0, 1, MSP430OpInfoBase + 221, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP8ri
909 { 508, 2, 0, 2, 0, 0, 1, MSP430OpInfoBase + 219, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP8rc
910 { 507, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 187, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP8mr
911 { 506, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP8mp
912 { 505, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP8mn
913 { 504, 4, 0, 6, 0, 0, 1, MSP430OpInfoBase + 157, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP8mm
914 { 503, 3, 0, 6, 0, 0, 1, MSP430OpInfoBase + 154, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP8mi
915 { 502, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 151, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP8mc
916 { 501, 2, 0, 2, 0, 0, 1, MSP430OpInfoBase + 217, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP16rr
917 { 500, 2, 0, 2, 0, 0, 1, MSP430OpInfoBase + 215, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP16rp
918 { 499, 2, 0, 2, 0, 0, 1, MSP430OpInfoBase + 215, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP16rn
919 { 498, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 212, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP16rm
920 { 497, 2, 0, 4, 0, 0, 1, MSP430OpInfoBase + 210, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP16ri
921 { 496, 2, 0, 2, 0, 0, 1, MSP430OpInfoBase + 34, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP16rc
922 { 495, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 164, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP16mr
923 { 494, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP16mp
924 { 493, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP16mn
925 { 492, 4, 0, 6, 0, 0, 1, MSP430OpInfoBase + 157, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP16mm
926 { 491, 3, 0, 6, 0, 0, 1, MSP430OpInfoBase + 154, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP16mi
927 { 490, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 151, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP16mc
928 { 489, 1, 0, 2, 0, 1, 6, MSP430OpInfoBase + 28, 8, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CALLr
929 { 488, 1, 0, 2, 0, 1, 6, MSP430OpInfoBase + 232, 8, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CALLp
930 { 487, 1, 0, 2, 0, 1, 6, MSP430OpInfoBase + 232, 8, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CALLn
931 { 486, 2, 0, 4, 0, 1, 6, MSP430OpInfoBase + 230, 8, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CALLm
932 { 485, 1, 0, 4, 0, 1, 6, MSP430OpInfoBase + 1, 8, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CALLi
933 { 484, 1, 0, 2, 0, 0, 0, MSP430OpInfoBase + 28, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Br
934 { 483, 2, 0, 4, 0, 0, 0, MSP430OpInfoBase + 230, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Bm
935 { 482, 1, 0, 4, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Bi
936 { 481, 2, 0, 2, 0, 0, 1, MSP430OpInfoBase + 228, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT8rr
937 { 480, 2, 0, 2, 0, 0, 1, MSP430OpInfoBase + 226, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT8rp
938 { 479, 2, 0, 2, 0, 0, 1, MSP430OpInfoBase + 226, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT8rn
939 { 478, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 223, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT8rm
940 { 477, 2, 0, 4, 0, 0, 1, MSP430OpInfoBase + 221, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT8ri
941 { 476, 2, 0, 2, 0, 0, 1, MSP430OpInfoBase + 219, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT8rc
942 { 475, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 187, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT8mr
943 { 474, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT8mp
944 { 473, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT8mn
945 { 472, 4, 0, 6, 0, 0, 1, MSP430OpInfoBase + 157, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT8mm
946 { 471, 3, 0, 6, 0, 0, 1, MSP430OpInfoBase + 154, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT8mi
947 { 470, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 151, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT8mc
948 { 469, 2, 0, 2, 0, 0, 1, MSP430OpInfoBase + 217, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT16rr
949 { 468, 2, 0, 2, 0, 0, 1, MSP430OpInfoBase + 215, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT16rp
950 { 467, 2, 0, 2, 0, 0, 1, MSP430OpInfoBase + 215, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT16rn
951 { 466, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 212, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT16rm
952 { 465, 2, 0, 4, 0, 0, 1, MSP430OpInfoBase + 210, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT16ri
953 { 464, 2, 0, 2, 0, 0, 1, MSP430OpInfoBase + 34, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT16rc
954 { 463, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 164, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT16mr
955 { 462, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT16mp
956 { 461, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT16mn
957 { 460, 4, 0, 6, 0, 0, 1, MSP430OpInfoBase + 157, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT16mm
958 { 459, 3, 0, 6, 0, 0, 1, MSP430OpInfoBase + 154, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT16mi
959 { 458, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 151, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT16mc
960 { 457, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 207, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS8rr
961 { 456, 4, 2, 2, 0, 0, 1, MSP430OpInfoBase + 203, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS8rp
962 { 455, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS8rn
963 { 454, 4, 1, 4, 0, 0, 1, MSP430OpInfoBase + 196, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS8rm
964 { 453, 3, 1, 4, 0, 0, 1, MSP430OpInfoBase + 193, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS8ri
965 { 452, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 190, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS8rc
966 { 451, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 187, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS8mr
967 { 450, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS8mp
968 { 449, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS8mn
969 { 448, 4, 0, 6, 0, 0, 1, MSP430OpInfoBase + 157, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS8mm
970 { 447, 3, 0, 6, 0, 0, 1, MSP430OpInfoBase + 154, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS8mi
971 { 446, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 151, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS8mc
972 { 445, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 184, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS16rr
973 { 444, 4, 2, 2, 0, 0, 1, MSP430OpInfoBase + 180, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS16rp
974 { 443, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 177, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS16rn
975 { 442, 4, 1, 4, 0, 0, 1, MSP430OpInfoBase + 173, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS16rm
976 { 441, 3, 1, 4, 0, 0, 1, MSP430OpInfoBase + 170, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS16ri
977 { 440, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 167, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS16rc
978 { 439, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 164, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS16mr
979 { 438, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS16mp
980 { 437, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS16mn
981 { 436, 4, 0, 6, 0, 0, 1, MSP430OpInfoBase + 157, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS16mm
982 { 435, 3, 0, 6, 0, 0, 1, MSP430OpInfoBase + 154, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS16mi
983 { 434, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 151, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS16mc
984 { 433, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 207, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC8rr
985 { 432, 4, 2, 2, 0, 0, 1, MSP430OpInfoBase + 203, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC8rp
986 { 431, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC8rn
987 { 430, 4, 1, 4, 0, 0, 1, MSP430OpInfoBase + 196, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC8rm
988 { 429, 3, 1, 4, 0, 0, 1, MSP430OpInfoBase + 193, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC8ri
989 { 428, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 190, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC8rc
990 { 427, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 187, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC8mr
991 { 426, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC8mp
992 { 425, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC8mn
993 { 424, 4, 0, 6, 0, 0, 1, MSP430OpInfoBase + 157, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC8mm
994 { 423, 3, 0, 6, 0, 0, 1, MSP430OpInfoBase + 154, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC8mi
995 { 422, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 151, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC8mc
996 { 421, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 184, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC16rr
997 { 420, 4, 2, 2, 0, 0, 1, MSP430OpInfoBase + 180, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC16rp
998 { 419, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 177, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC16rn
999 { 418, 4, 1, 4, 0, 0, 1, MSP430OpInfoBase + 173, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC16rm
1000 { 417, 3, 1, 4, 0, 0, 1, MSP430OpInfoBase + 170, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC16ri
1001 { 416, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 167, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC16rc
1002 { 415, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 164, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC16mr
1003 { 414, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC16mp
1004 { 413, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC16mn
1005 { 412, 4, 0, 6, 0, 0, 1, MSP430OpInfoBase + 157, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC16mm
1006 { 411, 3, 0, 6, 0, 0, 1, MSP430OpInfoBase + 154, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC16mi
1007 { 410, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 151, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC16mc
1008 { 409, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 207, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND8rr
1009 { 408, 4, 2, 2, 0, 0, 1, MSP430OpInfoBase + 203, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND8rp
1010 { 407, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND8rn
1011 { 406, 4, 1, 4, 0, 0, 1, MSP430OpInfoBase + 196, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND8rm
1012 { 405, 3, 1, 4, 0, 0, 1, MSP430OpInfoBase + 193, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND8ri
1013 { 404, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 190, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND8rc
1014 { 403, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 187, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND8mr
1015 { 402, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND8mp
1016 { 401, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND8mn
1017 { 400, 4, 0, 6, 0, 0, 1, MSP430OpInfoBase + 157, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND8mm
1018 { 399, 3, 0, 6, 0, 0, 1, MSP430OpInfoBase + 154, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND8mi
1019 { 398, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 151, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND8mc
1020 { 397, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 184, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND16rr
1021 { 396, 4, 2, 2, 0, 0, 1, MSP430OpInfoBase + 180, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND16rp
1022 { 395, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 177, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND16rn
1023 { 394, 4, 1, 4, 0, 0, 1, MSP430OpInfoBase + 173, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND16rm
1024 { 393, 3, 1, 4, 0, 0, 1, MSP430OpInfoBase + 170, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND16ri
1025 { 392, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 167, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND16rc
1026 { 391, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 164, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND16mr
1027 { 390, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND16mp
1028 { 389, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND16mn
1029 { 388, 4, 0, 6, 0, 0, 1, MSP430OpInfoBase + 157, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND16mm
1030 { 387, 3, 0, 6, 0, 0, 1, MSP430OpInfoBase + 154, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND16mi
1031 { 386, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 151, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND16mc
1032 { 385, 2, 0, 0, 0, 1, 2, MSP430OpInfoBase + 20, 5, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADJCALLSTACKUP
1033 { 384, 2, 0, 0, 0, 1, 2, MSP430OpInfoBase + 20, 5, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADJCALLSTACKDOWN
1034 { 383, 3, 1, 0, 0, 1, 1, MSP430OpInfoBase + 29, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDframe
1035 { 382, 3, 1, 2, 0, 1, 1, MSP430OpInfoBase + 207, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC8rr
1036 { 381, 4, 2, 2, 0, 1, 1, MSP430OpInfoBase + 203, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC8rp
1037 { 380, 3, 1, 2, 0, 1, 1, MSP430OpInfoBase + 200, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC8rn
1038 { 379, 4, 1, 4, 0, 1, 1, MSP430OpInfoBase + 196, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC8rm
1039 { 378, 3, 1, 4, 0, 1, 1, MSP430OpInfoBase + 193, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC8ri
1040 { 377, 3, 1, 2, 0, 1, 1, MSP430OpInfoBase + 190, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC8rc
1041 { 376, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 187, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC8mr
1042 { 375, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 161, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC8mp
1043 { 374, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 161, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC8mn
1044 { 373, 4, 0, 6, 0, 1, 1, MSP430OpInfoBase + 157, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC8mm
1045 { 372, 3, 0, 6, 0, 1, 1, MSP430OpInfoBase + 154, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC8mi
1046 { 371, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 151, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC8mc
1047 { 370, 3, 1, 2, 0, 1, 1, MSP430OpInfoBase + 184, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC16rr
1048 { 369, 4, 2, 2, 0, 1, 1, MSP430OpInfoBase + 180, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC16rp
1049 { 368, 3, 1, 2, 0, 1, 1, MSP430OpInfoBase + 177, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC16rn
1050 { 367, 4, 1, 4, 0, 1, 1, MSP430OpInfoBase + 173, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC16rm
1051 { 366, 3, 1, 4, 0, 1, 1, MSP430OpInfoBase + 170, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC16ri
1052 { 365, 3, 1, 2, 0, 1, 1, MSP430OpInfoBase + 167, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC16rc
1053 { 364, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 164, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC16mr
1054 { 363, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 161, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC16mp
1055 { 362, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 161, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC16mn
1056 { 361, 4, 0, 6, 0, 1, 1, MSP430OpInfoBase + 157, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC16mm
1057 { 360, 3, 0, 6, 0, 1, 1, MSP430OpInfoBase + 154, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC16mi
1058 { 359, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 151, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC16mc
1059 { 358, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 207, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD8rr
1060 { 357, 4, 2, 2, 0, 0, 1, MSP430OpInfoBase + 203, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD8rp
1061 { 356, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD8rn
1062 { 355, 4, 1, 4, 0, 0, 1, MSP430OpInfoBase + 196, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD8rm
1063 { 354, 3, 1, 4, 0, 0, 1, MSP430OpInfoBase + 193, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD8ri
1064 { 353, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 190, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD8rc
1065 { 352, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 187, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD8mr
1066 { 351, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD8mp
1067 { 350, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD8mn
1068 { 349, 4, 0, 6, 0, 0, 1, MSP430OpInfoBase + 157, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD8mm
1069 { 348, 3, 0, 6, 0, 0, 1, MSP430OpInfoBase + 154, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD8mi
1070 { 347, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 151, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD8mc
1071 { 346, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 184, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD16rr
1072 { 345, 4, 2, 2, 0, 0, 1, MSP430OpInfoBase + 180, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD16rp
1073 { 344, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 177, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD16rn
1074 { 343, 4, 1, 4, 0, 0, 1, MSP430OpInfoBase + 173, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD16rm
1075 { 342, 3, 1, 4, 0, 0, 1, MSP430OpInfoBase + 170, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD16ri
1076 { 341, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 167, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD16rc
1077 { 340, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 164, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD16mr
1078 { 339, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD16mp
1079 { 338, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD16mn
1080 { 337, 4, 0, 6, 0, 0, 1, MSP430OpInfoBase + 157, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD16mm
1081 { 336, 3, 0, 6, 0, 0, 1, MSP430OpInfoBase + 154, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD16mi
1082 { 335, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 151, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD16mc
1083 { 334, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 147, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UBFX
1084 { 333, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 147, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SBFX
1085 { 332, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_UMIN
1086 { 331, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_UMAX
1087 { 330, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SMIN
1088 { 329, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SMAX
1089 { 328, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_XOR
1090 { 327, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_OR
1091 { 326, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_AND
1092 { 325, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_MUL
1093 { 324, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_ADD
1094 { 323, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMINIMUMNUM
1095 { 322, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMAXIMUMNUM
1096 { 321, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMINIMUM
1097 { 320, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMAXIMUM
1098 { 319, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMIN
1099 { 318, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMAX
1100 { 317, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMUL
1101 { 316, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FADD
1102 { 315, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SEQ_FMUL
1103 { 314, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SEQ_FADD
1104 { 313, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UBSANTRAP
1105 { 312, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_DEBUGTRAP
1106 { 311, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRAP
1107 { 310, 3, 0, 0, 0, 0, 0, MSP430OpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMSET_INLINE
1108 { 309, 3, 0, 0, 0, 0, 0, MSP430OpInfoBase + 57, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BZERO
1109 { 308, 4, 0, 0, 0, 0, 0, MSP430OpInfoBase + 143, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMSET
1110 { 307, 4, 0, 0, 0, 0, 0, MSP430OpInfoBase + 143, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMMOVE
1111 { 306, 3, 0, 0, 0, 0, 0, MSP430OpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMCPY_INLINE
1112 { 305, 4, 0, 0, 0, 0, 0, MSP430OpInfoBase + 143, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMCPY
1113 { 304, 2, 0, 0, 0, 0, 0, MSP430OpInfoBase + 141, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_WRITE_REGISTER
1114 { 303, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_READ_REGISTER
1115 { 302, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FCMPS
1116 { 301, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FCMP
1117 { 300, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FLDEXP
1118 { 299, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FSQRT
1119 { 298, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FMA
1120 { 297, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FREM
1121 { 296, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FDIV
1122 { 295, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FMUL
1123 { 294, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FSUB
1124 { 293, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FADD
1125 { 292, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STACKRESTORE
1126 { 291, 1, 1, 0, 0, 0, 0, MSP430OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STACKSAVE
1127 { 290, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 68, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_DYN_STACKALLOC
1128 { 289, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_JUMP_TABLE
1129 { 288, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BLOCK_ADDR
1130 { 287, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ADDRSPACE_CAST
1131 { 286, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FNEARBYINT
1132 { 285, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FRINT
1133 { 284, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FFLOOR
1134 { 283, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSQRT
1135 { 282, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FTANH
1136 { 281, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSINH
1137 { 280, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCOSH
1138 { 279, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FATAN2
1139 { 278, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FATAN
1140 { 277, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FASIN
1141 { 276, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FACOS
1142 { 275, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FTAN
1143 { 274, 3, 2, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSINCOS
1144 { 273, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSIN
1145 { 272, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCOS
1146 { 271, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCEIL
1147 { 270, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CLMULR
1148 { 269, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CLMULH
1149 { 268, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CLMUL
1150 { 267, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BITREVERSE
1151 { 266, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BSWAP
1152 { 265, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTPOP
1153 { 264, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTLS
1154 { 263, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTLZ_ZERO_POISON
1155 { 262, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTLZ
1156 { 261, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTTZ_ZERO_POISON
1157 { 260, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTTZ
1158 { 259, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 137, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECTOR_COMPRESS
1159 { 258, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STEP_VECTOR
1160 { 257, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SPLAT_VECTOR
1161 { 256, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 133, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SHUFFLE_VECTOR
1162 { 255, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_EXTRACT_VECTOR_ELT
1163 { 254, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 126, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INSERT_VECTOR_ELT
1164 { 253, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 57, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_EXTRACT_SUBVECTOR
1165 { 252, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 62, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INSERT_SUBVECTOR
1166 { 251, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VSCALE
1167 { 250, 3, 0, 0, 0, 0, 0, MSP430OpInfoBase + 123, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BRJT
1168 { 249, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BR
1169 { 248, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LLROUND
1170 { 247, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LROUND
1171 { 246, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ABS
1172 { 245, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMAX
1173 { 244, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMIN
1174 { 243, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMAX
1175 { 242, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMIN
1176 { 241, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTRMASK
1177 { 240, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTR_ADD
1178 { 239, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SET_ROUNDING
1179 { 238, 1, 1, 0, 0, 0, 0, MSP430OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GET_ROUNDING
1180 { 237, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_RESET_FPMODE
1181 { 236, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SET_FPMODE
1182 { 235, 1, 1, 0, 0, 0, 0, MSP430OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GET_FPMODE
1183 { 234, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_RESET_FPENV
1184 { 233, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SET_FPENV
1185 { 232, 1, 1, 0, 0, 0, 0, MSP430OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GET_FPENV
1186 { 231, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXIMUMNUM
1187 { 230, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINIMUMNUM
1188 { 229, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXIMUM
1189 { 228, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINIMUM
1190 { 227, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXNUM_IEEE
1191 { 226, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINNUM_IEEE
1192 { 225, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXNUM
1193 { 224, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINNUM
1194 { 223, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCANONICALIZE
1195 { 222, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 97, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_IS_FPCLASS
1196 { 221, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCOPYSIGN
1197 { 220, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FABS
1198 { 219, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOUI_SAT
1199 { 218, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOSI_SAT
1200 { 217, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UITOFP
1201 { 216, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SITOFP
1202 { 215, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOUI
1203 { 214, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOSI
1204 { 213, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTRUNC
1205 { 212, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPEXT
1206 { 211, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FNEG
1207 { 210, 3, 2, 0, 0, 0, 0, MSP430OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FFREXP
1208 { 209, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLDEXP
1209 { 208, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLOG10
1210 { 207, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLOG2
1211 { 206, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLOG
1212 { 205, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FEXP10
1213 { 204, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FEXP2
1214 { 203, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FEXP
1215 { 202, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPOWI
1216 { 201, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPOW
1217 { 200, 3, 2, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMODF
1218 { 199, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FREM
1219 { 198, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FDIV
1220 { 197, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAD
1221 { 196, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMA
1222 { 195, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMUL
1223 { 194, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSUB
1224 { 193, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FADD
1225 { 192, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIVFIXSAT
1226 { 191, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIVFIXSAT
1227 { 190, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIVFIX
1228 { 189, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIVFIX
1229 { 188, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULFIXSAT
1230 { 187, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULFIXSAT
1231 { 186, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULFIX
1232 { 185, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULFIX
1233 { 184, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSHLSAT
1234 { 183, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USHLSAT
1235 { 182, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSUBSAT
1236 { 181, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USUBSAT
1237 { 180, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SADDSAT
1238 { 179, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UADDSAT
1239 { 178, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULH
1240 { 177, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULH
1241 { 176, 4, 2, 0, 0, 0, 0, MSP430OpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULO
1242 { 175, 4, 2, 0, 0, 0, 0, MSP430OpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULO
1243 { 174, 5, 2, 0, 0, 0, 0, MSP430OpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSUBE
1244 { 173, 4, 2, 0, 0, 0, 0, MSP430OpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSUBO
1245 { 172, 5, 2, 0, 0, 0, 0, MSP430OpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SADDE
1246 { 171, 4, 2, 0, 0, 0, 0, MSP430OpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SADDO
1247 { 170, 5, 2, 0, 0, 0, 0, MSP430OpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USUBE
1248 { 169, 4, 2, 0, 0, 0, 0, MSP430OpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USUBO
1249 { 168, 5, 2, 0, 0, 0, 0, MSP430OpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UADDE
1250 { 167, 4, 2, 0, 0, 0, 0, MSP430OpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UADDO
1251 { 166, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SELECT
1252 { 165, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 111, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UCMP
1253 { 164, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 111, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SCMP
1254 { 163, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCMP
1255 { 162, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ICMP
1256 { 161, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ROTL
1257 { 160, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ROTR
1258 { 159, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 103, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSHR
1259 { 158, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 103, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSHL
1260 { 157, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASHR
1261 { 156, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LSHR
1262 { 155, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SHL
1263 { 154, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ZEXT
1264 { 153, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SEXT_INREG
1265 { 152, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SEXT
1266 { 151, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 97, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VAARG
1267 { 150, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VASTART
1268 { 149, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCONSTANT
1269 { 148, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONSTANT
1270 { 147, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC_USAT_U
1271 { 146, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC_SSAT_U
1272 { 145, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC_SSAT_S
1273 { 144, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC
1274 { 143, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ANYEXT
1275 { 142, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
1276 { 141, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_INTRINSIC_CONVERGENT
1277 { 140, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_W_SIDE_EFFECTS
1278 { 139, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC
1279 { 138, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INVOKE_REGION_START
1280 { 137, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BRINDIRECT
1281 { 136, 2, 0, 0, 0, 0, 0, MSP430OpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BRCOND
1282 { 135, 4, 0, 0, 0, 0, 0, MSP430OpInfoBase + 93, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PREFETCH
1283 { 134, 2, 0, 0, 0, 0, 0, MSP430OpInfoBase + 20, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FENCE
1284 { 133, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_USUB_SAT
1285 { 132, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_USUB_COND
1286 { 131, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UDEC_WRAP
1287 { 130, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UINC_WRAP
1288 { 129, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMINIMUMNUM
1289 { 128, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMAXIMUMNUM
1290 { 127, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMINIMUM
1291 { 126, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMAXIMUM
1292 { 125, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMIN
1293 { 124, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMAX
1294 { 123, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FSUB
1295 { 122, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FADD
1296 { 121, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UMIN
1297 { 120, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UMAX
1298 { 119, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_MIN
1299 { 118, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_MAX
1300 { 117, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_XOR
1301 { 116, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_OR
1302 { 115, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_NAND
1303 { 114, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_AND
1304 { 113, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_SUB
1305 { 112, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_ADD
1306 { 111, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_XCHG
1307 { 110, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMIC_CMPXCHG
1308 { 109, 5, 2, 0, 0, 0, 0, MSP430OpInfoBase + 81, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
1309 { 108, 5, 1, 0, 0, 0, 0, MSP430OpInfoBase + 76, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_STORE
1310 { 107, 2, 0, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTRUNCSTORE
1311 { 106, 2, 0, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STORE
1312 { 105, 5, 2, 0, 0, 0, 0, MSP430OpInfoBase + 71, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_ZEXTLOAD
1313 { 104, 5, 2, 0, 0, 0, 0, MSP430OpInfoBase + 71, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_SEXTLOAD
1314 { 103, 5, 2, 0, 0, 0, 0, MSP430OpInfoBase + 71, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_LOAD
1315 { 102, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPEXTLOAD
1316 { 101, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ZEXTLOAD
1317 { 100, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SEXTLOAD
1318 { 99, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LOAD
1319 { 98, 1, 1, 0, 0, 0, 0, MSP430OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_READSTEADYCOUNTER
1320 { 97, 1, 1, 0, 0, 0, 0, MSP430OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_READCYCLECOUNTER
1321 { 96, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_ROUNDEVEN
1322 { 95, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_LLRINT
1323 { 94, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_LRINT
1324 { 93, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_ROUND
1325 { 92, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_TRUNC
1326 { 91, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 68, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_FPTRUNC_ROUND
1327 { 90, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONSTANT_FOLD_BARRIER
1328 { 89, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FREEZE
1329 { 88, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BITCAST
1330 { 87, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTTOPTR
1331 { 86, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTRTOINT
1332 { 85, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONCAT_VECTORS
1333 { 84, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BUILD_VECTOR_TRUNC
1334 { 83, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BUILD_VECTOR
1335 { 82, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MERGE_VALUES
1336 { 81, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 62, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INSERT
1337 { 80, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UNMERGE_VALUES
1338 { 79, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 57, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_EXTRACT
1339 { 78, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONSTANT_POOL
1340 { 77, 5, 1, 0, 0, 0, 0, MSP430OpInfoBase + 52, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTRAUTH_GLOBAL_VALUE
1341 { 76, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GLOBAL_VALUE
1342 { 75, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FRAME_INDEX
1343 { 74, 1, 1, 0, 0, 0, 0, MSP430OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PHI
1344 { 73, 1, 1, 0, 0, 0, 0, MSP430OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_IMPLICIT_DEF
1345 { 72, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SAVGCEIL
1346 { 71, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SAVGFLOOR
1347 { 70, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UAVGCEIL
1348 { 69, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UAVGFLOOR
1349 { 68, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ABDU
1350 { 67, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ABDS
1351 { 66, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_XOR
1352 { 65, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_OR
1353 { 64, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_AND
1354 { 63, 4, 2, 0, 0, 0, 0, MSP430OpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIVREM
1355 { 62, 4, 2, 0, 0, 0, 0, MSP430OpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIVREM
1356 { 61, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UREM
1357 { 60, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SREM
1358 { 59, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIV
1359 { 58, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIV
1360 { 57, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MUL
1361 { 56, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SUB
1362 { 55, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ADD
1363 { 54, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASSERT_ALIGN
1364 { 53, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASSERT_ZEXT
1365 { 52, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASSERT_SEXT
1366 { 51, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_GLUE
1367 { 50, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_LOOP
1368 { 49, 1, 1, 0, 0, 0, 0, MSP430OpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_ANCHOR
1369 { 48, 1, 1, 0, 0, 0, 0, MSP430OpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_ENTRY
1370 { 47, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RELOC_NONE
1371 { 46, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JUMP_TABLE_DEBUG_INFO
1372 { 45, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMBARRIER
1373 { 44, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FAKE_USE
1374 { 43, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ICALL_BRANCH_FUNNEL
1375 { 42, 3, 0, 0, 0, 0, 0, MSP430OpInfoBase + 36, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_14758
1376 { 41, 2, 0, 0, 0, 0, 0, MSP430OpInfoBase + 34, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_14757
1377 { 40, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_TAIL_CALL
1378 { 39, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_FUNCTION_EXIT
1379 { 38, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_RET
1380 { 37, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_FUNCTION_ENTER
1381 { 36, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_OP
1382 { 35, 1, 1, 0, 0, 0, 0, MSP430OpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FAULTING_OP
1383 { 34, 2, 0, 0, 0, 0, 0, MSP430OpInfoBase + 32, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_ESCAPE
1384 { 33, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STATEPOINT
1385 { 32, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 29, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_14756
1386 { 31, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PREALLOCATED_SETUP
1387 { 30, 1, 1, 0, 0, 0, 0, MSP430OpInfoBase + 28, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_14418
1388 { 29, 6, 1, 0, 0, 0, 0, MSP430OpInfoBase + 22, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHPOINT
1389 { 28, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FENTRY_CALL
1390 { 27, 2, 0, 0, 0, 0, 0, MSP430OpInfoBase + 20, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STACKMAP
1391 { 26, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 18, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARITH_FENCE
1392 { 25, 4, 0, 0, 0, 0, 0, MSP430OpInfoBase + 14, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PSEUDO_PROBE
1393 { 24, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LIFETIME_END
1394 { 23, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LIFETIME_START
1395 { 22, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BUNDLE
1396 { 21, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 11, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_LANEMASK
1397 { 20, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY
1398 { 19, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REG_SEQUENCE
1399 { 18, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_LABEL
1400 { 17, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_PHI
1401 { 16, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_INSTR_REF
1402 { 15, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_VALUE_LIST
1403 { 14, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_VALUE
1404 { 13, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_TO_REGCLASS
1405 { 12, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBREG_TO_REG
1406 { 11, 1, 1, 0, 0, 0, 0, MSP430OpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INIT_UNDEF
1407 { 10, 1, 1, 0, 0, 0, 0, MSP430OpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // IMPLICIT_DEF
1408 { 9, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 5, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INSERT_SUBREG
1409 { 8, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTRACT_SUBREG
1410 { 7, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // KILL
1411 { 6, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ANNOTATION_LABEL
1412 { 5, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GC_LABEL
1413 { 4, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EH_LABEL
1414 { 3, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CFI_INSTRUCTION
1415 { 2, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INLINEASM_BR
1416 { 1, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INLINEASM
1417 { 0, 1, 1, 0, 0, 0, 0, MSP430OpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PHI
1418 }, {
1419 /* 0 */
1420 /* 0 */ MSP430::SR,
1421 /* 1 */ MSP430::SR, MSP430::SR,
1422 /* 3 */ MSP430::SP, MSP430::SR,
1423 /* 5 */ MSP430::SP, MSP430::SP, MSP430::SR,
1424 /* 8 */ MSP430::SP, MSP430::R11, MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15, MSP430::SR,
1425 /* 15 */ MSP430::SP, MSP430::SP,
1426 }, {
1427 0
1428 }, {
1429 /* 0 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1430 /* 1 */
1431 /* 1 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1432 /* 2 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1433 /* 5 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1434 /* 9 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1435 /* 11 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1436 /* 14 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1437 /* 18 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) },
1438 /* 20 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1439 /* 22 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1440 /* 28 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1441 /* 29 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1442 /* 32 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1443 /* 34 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1444 /* 36 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1445 /* 39 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1446 /* 42 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1447 /* 45 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1448 /* 49 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1449 /* 50 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1450 /* 52 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1451 /* 57 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1452 /* 60 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1453 /* 62 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1454 /* 66 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1455 /* 68 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1456 /* 71 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1457 /* 76 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1458 /* 81 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1459 /* 86 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1460 /* 90 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1461 /* 93 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_2, 0 },
1462 /* 97 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1463 /* 100 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1464 /* 103 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1465 /* 107 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1466 /* 111 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1467 /* 114 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1468 /* 119 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1469 /* 123 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1470 /* 126 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
1471 /* 130 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
1472 /* 133 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1473 /* 137 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1474 /* 141 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1475 /* 143 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1476 /* 147 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1477 /* 151 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1478 /* 154 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1479 /* 157 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1480 /* 161 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 },
1481 /* 164 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1482 /* 167 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1483 /* 170 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1484 /* 173 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1485 /* 177 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 },
1486 /* 180 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(1) },
1487 /* 184 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1488 /* 187 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1489 /* 190 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1490 /* 193 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1491 /* 196 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1492 /* 200 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 },
1493 /* 203 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(1) },
1494 /* 207 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1495 /* 210 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1496 /* 212 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1497 /* 215 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 },
1498 /* 217 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1499 /* 219 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1500 /* 221 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1501 /* 223 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1502 /* 226 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 },
1503 /* 228 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1504 /* 230 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1505 /* 232 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 },
1506 /* 233 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(1) },
1507 /* 236 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(1) },
1508 /* 239 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1509 /* 241 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1510 /* 242 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
1511 /* 244 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
1512 /* 246 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1513 /* 250 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1514 /* 254 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1515 /* 257 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1516 }
1517};
1518
1519
1520#ifdef __GNUC__
1521#pragma GCC diagnostic push
1522#pragma GCC diagnostic ignored "-Woverlength-strings"
1523#endif
1524extern const char MSP430InstrNameData[] = {
1525 /* 0 */ "G_FLOG10\000"
1526 /* 9 */ "G_FEXP10\000"
1527 /* 18 */ "G_FLOG2\000"
1528 /* 26 */ "G_FATAN2\000"
1529 /* 35 */ "G_FEXP2\000"
1530 /* 43 */ "Sra16\000"
1531 /* 49 */ "Rrcl16\000"
1532 /* 56 */ "Shl16\000"
1533 /* 62 */ "Srl16\000"
1534 /* 68 */ "Select16\000"
1535 /* 77 */ "Sra8\000"
1536 /* 82 */ "Rrcl8\000"
1537 /* 88 */ "Shl8\000"
1538 /* 93 */ "Srl8\000"
1539 /* 98 */ "MOVZX16rm8\000"
1540 /* 109 */ "MOVZX16rr8\000"
1541 /* 120 */ "Select8\000"
1542 /* 128 */ "G_FMA\000"
1543 /* 134 */ "G_STRICT_FMA\000"
1544 /* 147 */ "G_FSUB\000"
1545 /* 154 */ "G_STRICT_FSUB\000"
1546 /* 168 */ "G_ATOMICRMW_FSUB\000"
1547 /* 185 */ "G_SUB\000"
1548 /* 191 */ "G_ATOMICRMW_SUB\000"
1549 /* 207 */ "JCC\000"
1550 /* 211 */ "G_INTRINSIC\000"
1551 /* 223 */ "G_FPTRUNC\000"
1552 /* 233 */ "G_INTRINSIC_TRUNC\000"
1553 /* 251 */ "G_TRUNC\000"
1554 /* 259 */ "G_BUILD_VECTOR_TRUNC\000"
1555 /* 280 */ "G_DYN_STACKALLOC\000"
1556 /* 297 */ "G_FMAD\000"
1557 /* 304 */ "G_FPEXTLOAD\000"
1558 /* 316 */ "G_INDEXED_SEXTLOAD\000"
1559 /* 335 */ "G_SEXTLOAD\000"
1560 /* 346 */ "G_INDEXED_ZEXTLOAD\000"
1561 /* 365 */ "G_ZEXTLOAD\000"
1562 /* 376 */ "G_INDEXED_LOAD\000"
1563 /* 391 */ "G_LOAD\000"
1564 /* 398 */ "G_VECREDUCE_FADD\000"
1565 /* 415 */ "G_FADD\000"
1566 /* 422 */ "G_VECREDUCE_SEQ_FADD\000"
1567 /* 443 */ "G_STRICT_FADD\000"
1568 /* 457 */ "G_ATOMICRMW_FADD\000"
1569 /* 474 */ "G_VECREDUCE_ADD\000"
1570 /* 490 */ "G_ADD\000"
1571 /* 496 */ "G_PTR_ADD\000"
1572 /* 506 */ "G_ATOMICRMW_ADD\000"
1573 /* 522 */ "G_ATOMICRMW_NAND\000"
1574 /* 539 */ "G_VECREDUCE_AND\000"
1575 /* 555 */ "G_AND\000"
1576 /* 561 */ "G_ATOMICRMW_AND\000"
1577 /* 577 */ "LIFETIME_END\000"
1578 /* 590 */ "G_BRCOND\000"
1579 /* 599 */ "G_ATOMICRMW_USUB_COND\000"
1580 /* 621 */ "G_LLROUND\000"
1581 /* 631 */ "G_LROUND\000"
1582 /* 640 */ "G_INTRINSIC_ROUND\000"
1583 /* 658 */ "G_INTRINSIC_FPTRUNC_ROUND\000"
1584 /* 684 */ "LOAD_STACK_GUARD\000"
1585 /* 701 */ "PSEUDO_PROBE\000"
1586 /* 714 */ "G_SSUBE\000"
1587 /* 722 */ "G_USUBE\000"
1588 /* 730 */ "G_FENCE\000"
1589 /* 738 */ "ARITH_FENCE\000"
1590 /* 750 */ "REG_SEQUENCE\000"
1591 /* 763 */ "G_SADDE\000"
1592 /* 771 */ "G_UADDE\000"
1593 /* 779 */ "G_GET_FPMODE\000"
1594 /* 792 */ "G_RESET_FPMODE\000"
1595 /* 807 */ "G_SET_FPMODE\000"
1596 /* 820 */ "G_FMINNUM_IEEE\000"
1597 /* 835 */ "G_FMAXNUM_IEEE\000"
1598 /* 850 */ "G_VSCALE\000"
1599 /* 859 */ "G_JUMP_TABLE\000"
1600 /* 872 */ "BUNDLE\000"
1601 /* 879 */ "G_MEMSET_INLINE\000"
1602 /* 895 */ "G_MEMCPY_INLINE\000"
1603 /* 911 */ "RELOC_NONE\000"
1604 /* 922 */ "LOCAL_ESCAPE\000"
1605 /* 935 */ "G_FPTRUNCSTORE\000"
1606 /* 950 */ "G_STACKRESTORE\000"
1607 /* 965 */ "G_INDEXED_STORE\000"
1608 /* 981 */ "G_STORE\000"
1609 /* 989 */ "G_BITREVERSE\000"
1610 /* 1002 */ "FAKE_USE\000"
1611 /* 1011 */ "DBG_VALUE\000"
1612 /* 1021 */ "G_GLOBAL_VALUE\000"
1613 /* 1036 */ "G_PTRAUTH_GLOBAL_VALUE\000"
1614 /* 1059 */ "CONVERGENCECTRL_GLUE\000"
1615 /* 1080 */ "G_STACKSAVE\000"
1616 /* 1092 */ "G_MEMMOVE\000"
1617 /* 1102 */ "G_FREEZE\000"
1618 /* 1111 */ "G_FCANONICALIZE\000"
1619 /* 1127 */ "G_FMODF\000"
1620 /* 1135 */ "INIT_UNDEF\000"
1621 /* 1146 */ "G_IMPLICIT_DEF\000"
1622 /* 1161 */ "DBG_INSTR_REF\000"
1623 /* 1175 */ "G_FNEG\000"
1624 /* 1182 */ "EXTRACT_SUBREG\000"
1625 /* 1197 */ "INSERT_SUBREG\000"
1626 /* 1211 */ "G_SEXT_INREG\000"
1627 /* 1224 */ "SUBREG_TO_REG\000"
1628 /* 1238 */ "G_ATOMIC_CMPXCHG\000"
1629 /* 1255 */ "G_ATOMICRMW_XCHG\000"
1630 /* 1272 */ "G_GET_ROUNDING\000"
1631 /* 1287 */ "G_SET_ROUNDING\000"
1632 /* 1302 */ "G_FLOG\000"
1633 /* 1309 */ "G_VAARG\000"
1634 /* 1317 */ "PREALLOCATED_ARG\000"
1635 /* 1334 */ "G_PREFETCH\000"
1636 /* 1345 */ "G_CLMULH\000"
1637 /* 1354 */ "G_SMULH\000"
1638 /* 1362 */ "G_UMULH\000"
1639 /* 1370 */ "G_FTANH\000"
1640 /* 1378 */ "G_FSINH\000"
1641 /* 1386 */ "G_FCOSH\000"
1642 /* 1394 */ "DBG_PHI\000"
1643 /* 1402 */ "G_FPTOSI\000"
1644 /* 1411 */ "RETI\000"
1645 /* 1416 */ "G_FPTOUI\000"
1646 /* 1425 */ "G_FPOWI\000"
1647 /* 1433 */ "COPY_LANEMASK\000"
1648 /* 1447 */ "G_PTRMASK\000"
1649 /* 1457 */ "GC_LABEL\000"
1650 /* 1466 */ "DBG_LABEL\000"
1651 /* 1476 */ "EH_LABEL\000"
1652 /* 1485 */ "ANNOTATION_LABEL\000"
1653 /* 1502 */ "ICALL_BRANCH_FUNNEL\000"
1654 /* 1522 */ "G_FSHL\000"
1655 /* 1529 */ "G_SHL\000"
1656 /* 1535 */ "G_FCEIL\000"
1657 /* 1543 */ "G_SAVGCEIL\000"
1658 /* 1554 */ "G_UAVGCEIL\000"
1659 /* 1565 */ "PATCHABLE_TAIL_CALL\000"
1660 /* 1585 */ "PATCHABLE_TYPED_EVENT_CALL\000"
1661 /* 1612 */ "PATCHABLE_EVENT_CALL\000"
1662 /* 1633 */ "FENTRY_CALL\000"
1663 /* 1645 */ "KILL\000"
1664 /* 1650 */ "G_CONSTANT_POOL\000"
1665 /* 1666 */ "G_ROTL\000"
1666 /* 1673 */ "G_VECREDUCE_FMUL\000"
1667 /* 1690 */ "G_FMUL\000"
1668 /* 1697 */ "G_VECREDUCE_SEQ_FMUL\000"
1669 /* 1718 */ "G_STRICT_FMUL\000"
1670 /* 1732 */ "G_CLMUL\000"
1671 /* 1740 */ "G_VECREDUCE_MUL\000"
1672 /* 1756 */ "G_MUL\000"
1673 /* 1762 */ "G_FREM\000"
1674 /* 1769 */ "G_STRICT_FREM\000"
1675 /* 1783 */ "G_SREM\000"
1676 /* 1790 */ "G_UREM\000"
1677 /* 1797 */ "G_SDIVREM\000"
1678 /* 1807 */ "G_UDIVREM\000"
1679 /* 1817 */ "INLINEASM\000"
1680 /* 1827 */ "G_VECREDUCE_FMINIMUM\000"
1681 /* 1848 */ "G_FMINIMUM\000"
1682 /* 1859 */ "G_ATOMICRMW_FMINIMUM\000"
1683 /* 1880 */ "G_VECREDUCE_FMAXIMUM\000"
1684 /* 1901 */ "G_FMAXIMUM\000"
1685 /* 1912 */ "G_ATOMICRMW_FMAXIMUM\000"
1686 /* 1933 */ "G_VECREDUCE_FMINIMUMNUM\000"
1687 /* 1957 */ "G_FMINIMUMNUM\000"
1688 /* 1971 */ "G_ATOMICRMW_FMINIMUMNUM\000"
1689 /* 1995 */ "G_VECREDUCE_FMAXIMUMNUM\000"
1690 /* 2019 */ "G_FMAXIMUMNUM\000"
1691 /* 2033 */ "G_ATOMICRMW_FMAXIMUMNUM\000"
1692 /* 2057 */ "G_FMINNUM\000"
1693 /* 2067 */ "G_FMAXNUM\000"
1694 /* 2077 */ "G_FATAN\000"
1695 /* 2085 */ "G_FTAN\000"
1696 /* 2092 */ "G_INTRINSIC_ROUNDEVEN\000"
1697 /* 2114 */ "G_ASSERT_ALIGN\000"
1698 /* 2129 */ "G_FCOPYSIGN\000"
1699 /* 2141 */ "G_VECREDUCE_FMIN\000"
1700 /* 2158 */ "G_ATOMICRMW_FMIN\000"
1701 /* 2175 */ "G_VECREDUCE_SMIN\000"
1702 /* 2192 */ "G_SMIN\000"
1703 /* 2199 */ "G_VECREDUCE_UMIN\000"
1704 /* 2216 */ "G_UMIN\000"
1705 /* 2223 */ "G_ATOMICRMW_UMIN\000"
1706 /* 2240 */ "G_ATOMICRMW_MIN\000"
1707 /* 2256 */ "G_FASIN\000"
1708 /* 2264 */ "G_FSIN\000"
1709 /* 2271 */ "CFI_INSTRUCTION\000"
1710 /* 2287 */ "G_CTLZ_ZERO_POISON\000"
1711 /* 2306 */ "G_CTTZ_ZERO_POISON\000"
1712 /* 2325 */ "ADJCALLSTACKDOWN\000"
1713 /* 2342 */ "G_SSUBO\000"
1714 /* 2350 */ "G_USUBO\000"
1715 /* 2358 */ "G_SADDO\000"
1716 /* 2366 */ "G_UADDO\000"
1717 /* 2374 */ "JUMP_TABLE_DEBUG_INFO\000"
1718 /* 2396 */ "G_SMULO\000"
1719 /* 2404 */ "G_UMULO\000"
1720 /* 2412 */ "G_BZERO\000"
1721 /* 2420 */ "STACKMAP\000"
1722 /* 2429 */ "G_DEBUGTRAP\000"
1723 /* 2441 */ "G_UBSANTRAP\000"
1724 /* 2453 */ "G_TRAP\000"
1725 /* 2460 */ "G_ATOMICRMW_UDEC_WRAP\000"
1726 /* 2482 */ "G_ATOMICRMW_UINC_WRAP\000"
1727 /* 2504 */ "G_BSWAP\000"
1728 /* 2512 */ "G_SITOFP\000"
1729 /* 2521 */ "G_UITOFP\000"
1730 /* 2530 */ "G_FCMP\000"
1731 /* 2537 */ "G_STRICT_FCMP\000"
1732 /* 2551 */ "G_ICMP\000"
1733 /* 2558 */ "G_SCMP\000"
1734 /* 2565 */ "G_UCMP\000"
1735 /* 2572 */ "JMP\000"
1736 /* 2576 */ "CONVERGENCECTRL_LOOP\000"
1737 /* 2597 */ "G_CTPOP\000"
1738 /* 2605 */ "PATCHABLE_OP\000"
1739 /* 2618 */ "FAULTING_OP\000"
1740 /* 2630 */ "ADJCALLSTACKUP\000"
1741 /* 2645 */ "PREALLOCATED_SETUP\000"
1742 /* 2664 */ "G_FLDEXP\000"
1743 /* 2673 */ "G_STRICT_FLDEXP\000"
1744 /* 2689 */ "G_FEXP\000"
1745 /* 2696 */ "G_FFREXP\000"
1746 /* 2705 */ "G_BR\000"
1747 /* 2710 */ "INLINEASM_BR\000"
1748 /* 2723 */ "G_BLOCK_ADDR\000"
1749 /* 2736 */ "MEMBARRIER\000"
1750 /* 2747 */ "G_CONSTANT_FOLD_BARRIER\000"
1751 /* 2771 */ "PATCHABLE_FUNCTION_ENTER\000"
1752 /* 2796 */ "G_READCYCLECOUNTER\000"
1753 /* 2815 */ "G_READSTEADYCOUNTER\000"
1754 /* 2835 */ "G_READ_REGISTER\000"
1755 /* 2851 */ "G_WRITE_REGISTER\000"
1756 /* 2868 */ "G_ASHR\000"
1757 /* 2875 */ "G_FSHR\000"
1758 /* 2882 */ "G_LSHR\000"
1759 /* 2889 */ "G_CLMULR\000"
1760 /* 2898 */ "CONVERGENCECTRL_ANCHOR\000"
1761 /* 2921 */ "G_FFLOOR\000"
1762 /* 2930 */ "G_SAVGFLOOR\000"
1763 /* 2942 */ "G_UAVGFLOOR\000"
1764 /* 2954 */ "G_EXTRACT_SUBVECTOR\000"
1765 /* 2974 */ "G_INSERT_SUBVECTOR\000"
1766 /* 2993 */ "G_BUILD_VECTOR\000"
1767 /* 3008 */ "G_SHUFFLE_VECTOR\000"
1768 /* 3025 */ "G_STEP_VECTOR\000"
1769 /* 3039 */ "G_SPLAT_VECTOR\000"
1770 /* 3054 */ "G_VECREDUCE_XOR\000"
1771 /* 3070 */ "G_XOR\000"
1772 /* 3076 */ "G_ATOMICRMW_XOR\000"
1773 /* 3092 */ "G_VECREDUCE_OR\000"
1774 /* 3107 */ "G_OR\000"
1775 /* 3112 */ "G_ATOMICRMW_OR\000"
1776 /* 3127 */ "G_ROTR\000"
1777 /* 3134 */ "G_INTTOPTR\000"
1778 /* 3145 */ "G_FABS\000"
1779 /* 3152 */ "G_ABS\000"
1780 /* 3158 */ "G_ABDS\000"
1781 /* 3165 */ "G_UNMERGE_VALUES\000"
1782 /* 3182 */ "G_MERGE_VALUES\000"
1783 /* 3197 */ "G_CTLS\000"
1784 /* 3204 */ "G_FACOS\000"
1785 /* 3212 */ "G_FCOS\000"
1786 /* 3219 */ "G_FSINCOS\000"
1787 /* 3229 */ "G_STRICT_FCMPS\000"
1788 /* 3244 */ "G_CONCAT_VECTORS\000"
1789 /* 3261 */ "COPY_TO_REGCLASS\000"
1790 /* 3278 */ "G_IS_FPCLASS\000"
1791 /* 3291 */ "G_ATOMIC_CMPXCHG_WITH_SUCCESS\000"
1792 /* 3321 */ "G_VECTOR_COMPRESS\000"
1793 /* 3339 */ "G_INTRINSIC_W_SIDE_EFFECTS\000"
1794 /* 3366 */ "G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS\000"
1795 /* 3404 */ "G_TRUNC_SSAT_S\000"
1796 /* 3419 */ "G_SSUBSAT\000"
1797 /* 3429 */ "G_USUBSAT\000"
1798 /* 3439 */ "G_SADDSAT\000"
1799 /* 3449 */ "G_UADDSAT\000"
1800 /* 3459 */ "G_SSHLSAT\000"
1801 /* 3469 */ "G_USHLSAT\000"
1802 /* 3479 */ "G_SMULFIXSAT\000"
1803 /* 3492 */ "G_UMULFIXSAT\000"
1804 /* 3505 */ "G_SDIVFIXSAT\000"
1805 /* 3518 */ "G_UDIVFIXSAT\000"
1806 /* 3531 */ "G_ATOMICRMW_USUB_SAT\000"
1807 /* 3552 */ "G_FPTOSI_SAT\000"
1808 /* 3565 */ "G_FPTOUI_SAT\000"
1809 /* 3578 */ "G_EXTRACT\000"
1810 /* 3588 */ "G_SELECT\000"
1811 /* 3597 */ "G_BRINDIRECT\000"
1812 /* 3610 */ "PATCHABLE_RET\000"
1813 /* 3624 */ "G_MEMSET\000"
1814 /* 3633 */ "PATCHABLE_FUNCTION_EXIT\000"
1815 /* 3657 */ "G_BRJT\000"
1816 /* 3664 */ "G_EXTRACT_VECTOR_ELT\000"
1817 /* 3685 */ "G_INSERT_VECTOR_ELT\000"
1818 /* 3705 */ "G_FCONSTANT\000"
1819 /* 3717 */ "G_CONSTANT\000"
1820 /* 3728 */ "G_INTRINSIC_CONVERGENT\000"
1821 /* 3751 */ "STATEPOINT\000"
1822 /* 3762 */ "PATCHPOINT\000"
1823 /* 3773 */ "G_PTRTOINT\000"
1824 /* 3784 */ "G_FRINT\000"
1825 /* 3792 */ "G_INTRINSIC_LLRINT\000"
1826 /* 3811 */ "G_INTRINSIC_LRINT\000"
1827 /* 3829 */ "G_FNEARBYINT\000"
1828 /* 3842 */ "G_VASTART\000"
1829 /* 3852 */ "LIFETIME_START\000"
1830 /* 3867 */ "G_INVOKE_REGION_START\000"
1831 /* 3889 */ "G_INSERT\000"
1832 /* 3898 */ "G_FSQRT\000"
1833 /* 3906 */ "G_STRICT_FSQRT\000"
1834 /* 3921 */ "G_BITCAST\000"
1835 /* 3931 */ "G_ADDRSPACE_CAST\000"
1836 /* 3948 */ "DBG_VALUE_LIST\000"
1837 /* 3963 */ "G_FPEXT\000"
1838 /* 3971 */ "G_SEXT\000"
1839 /* 3978 */ "G_ASSERT_SEXT\000"
1840 /* 3992 */ "G_ANYEXT\000"
1841 /* 4001 */ "G_ZEXT\000"
1842 /* 4008 */ "G_ASSERT_ZEXT\000"
1843 /* 4022 */ "G_ABDU\000"
1844 /* 4029 */ "G_TRUNC_SSAT_U\000"
1845 /* 4044 */ "G_TRUNC_USAT_U\000"
1846 /* 4059 */ "G_FDIV\000"
1847 /* 4066 */ "G_STRICT_FDIV\000"
1848 /* 4080 */ "G_SDIV\000"
1849 /* 4087 */ "G_UDIV\000"
1850 /* 4094 */ "G_GET_FPENV\000"
1851 /* 4106 */ "G_RESET_FPENV\000"
1852 /* 4120 */ "G_SET_FPENV\000"
1853 /* 4132 */ "G_FPOW\000"
1854 /* 4139 */ "G_VECREDUCE_FMAX\000"
1855 /* 4156 */ "G_ATOMICRMW_FMAX\000"
1856 /* 4173 */ "G_VECREDUCE_SMAX\000"
1857 /* 4190 */ "G_SMAX\000"
1858 /* 4197 */ "G_VECREDUCE_UMAX\000"
1859 /* 4214 */ "G_UMAX\000"
1860 /* 4221 */ "G_ATOMICRMW_UMAX\000"
1861 /* 4238 */ "G_ATOMICRMW_MAX\000"
1862 /* 4254 */ "G_FRAME_INDEX\000"
1863 /* 4268 */ "G_SBFX\000"
1864 /* 4275 */ "G_UBFX\000"
1865 /* 4282 */ "G_SMULFIX\000"
1866 /* 4292 */ "G_UMULFIX\000"
1867 /* 4302 */ "G_SDIVFIX\000"
1868 /* 4312 */ "G_UDIVFIX\000"
1869 /* 4322 */ "G_MEMCPY\000"
1870 /* 4331 */ "COPY\000"
1871 /* 4336 */ "CONVERGENCECTRL_ENTRY\000"
1872 /* 4358 */ "G_CTLZ\000"
1873 /* 4365 */ "G_CTTZ\000"
1874 /* 4372 */ "PUSH16c\000"
1875 /* 4380 */ "SUB16mc\000"
1876 /* 4388 */ "SUBC16mc\000"
1877 /* 4397 */ "ADDC16mc\000"
1878 /* 4406 */ "BIC16mc\000"
1879 /* 4414 */ "DADD16mc\000"
1880 /* 4423 */ "AND16mc\000"
1881 /* 4431 */ "CMP16mc\000"
1882 /* 4439 */ "XOR16mc\000"
1883 /* 4447 */ "BIS16mc\000"
1884 /* 4455 */ "BIT16mc\000"
1885 /* 4463 */ "MOV16mc\000"
1886 /* 4471 */ "SUB8mc\000"
1887 /* 4478 */ "SUBC8mc\000"
1888 /* 4486 */ "ADDC8mc\000"
1889 /* 4494 */ "BIC8mc\000"
1890 /* 4501 */ "DADD8mc\000"
1891 /* 4509 */ "AND8mc\000"
1892 /* 4516 */ "CMP8mc\000"
1893 /* 4523 */ "XOR8mc\000"
1894 /* 4530 */ "BIS8mc\000"
1895 /* 4537 */ "BIT8mc\000"
1896 /* 4544 */ "MOV8mc\000"
1897 /* 4551 */ "SUB16rc\000"
1898 /* 4559 */ "SUBC16rc\000"
1899 /* 4568 */ "ADDC16rc\000"
1900 /* 4577 */ "BIC16rc\000"
1901 /* 4585 */ "DADD16rc\000"
1902 /* 4594 */ "AND16rc\000"
1903 /* 4602 */ "CMP16rc\000"
1904 /* 4610 */ "XOR16rc\000"
1905 /* 4618 */ "BIS16rc\000"
1906 /* 4626 */ "BIT16rc\000"
1907 /* 4634 */ "MOV16rc\000"
1908 /* 4642 */ "SUB8rc\000"
1909 /* 4649 */ "SUBC8rc\000"
1910 /* 4657 */ "ADDC8rc\000"
1911 /* 4665 */ "BIC8rc\000"
1912 /* 4672 */ "DADD8rc\000"
1913 /* 4680 */ "AND8rc\000"
1914 /* 4687 */ "CMP8rc\000"
1915 /* 4694 */ "XOR8rc\000"
1916 /* 4701 */ "BIS8rc\000"
1917 /* 4708 */ "BIT8rc\000"
1918 /* 4715 */ "MOV8rc\000"
1919 /* 4722 */ "ADDframe\000"
1920 /* 4731 */ "PUSH16i\000"
1921 /* 4739 */ "Bi\000"
1922 /* 4742 */ "CALLi\000"
1923 /* 4748 */ "SUB16mi\000"
1924 /* 4756 */ "SUBC16mi\000"
1925 /* 4765 */ "ADDC16mi\000"
1926 /* 4774 */ "BIC16mi\000"
1927 /* 4782 */ "DADD16mi\000"
1928 /* 4791 */ "AND16mi\000"
1929 /* 4799 */ "CMP16mi\000"
1930 /* 4807 */ "XOR16mi\000"
1931 /* 4815 */ "BIS16mi\000"
1932 /* 4823 */ "BIT16mi\000"
1933 /* 4831 */ "MOV16mi\000"
1934 /* 4839 */ "SUB8mi\000"
1935 /* 4846 */ "SUBC8mi\000"
1936 /* 4854 */ "ADDC8mi\000"
1937 /* 4862 */ "BIC8mi\000"
1938 /* 4869 */ "DADD8mi\000"
1939 /* 4877 */ "AND8mi\000"
1940 /* 4884 */ "CMP8mi\000"
1941 /* 4891 */ "XOR8mi\000"
1942 /* 4898 */ "BIS8mi\000"
1943 /* 4905 */ "BIT8mi\000"
1944 /* 4912 */ "MOV8mi\000"
1945 /* 4919 */ "SUB16ri\000"
1946 /* 4927 */ "SUBC16ri\000"
1947 /* 4936 */ "ADDC16ri\000"
1948 /* 4945 */ "BIC16ri\000"
1949 /* 4953 */ "DADD16ri\000"
1950 /* 4962 */ "AND16ri\000"
1951 /* 4970 */ "CMP16ri\000"
1952 /* 4978 */ "XOR16ri\000"
1953 /* 4986 */ "BIS16ri\000"
1954 /* 4994 */ "BIT16ri\000"
1955 /* 5002 */ "MOV16ri\000"
1956 /* 5010 */ "SUB8ri\000"
1957 /* 5017 */ "SUBC8ri\000"
1958 /* 5025 */ "ADDC8ri\000"
1959 /* 5033 */ "BIC8ri\000"
1960 /* 5040 */ "DADD8ri\000"
1961 /* 5048 */ "AND8ri\000"
1962 /* 5055 */ "CMP8ri\000"
1963 /* 5062 */ "XOR8ri\000"
1964 /* 5069 */ "BIS8ri\000"
1965 /* 5076 */ "BIT8ri\000"
1966 /* 5083 */ "MOV8ri\000"
1967 /* 5090 */ "RRA16m\000"
1968 /* 5097 */ "SWPB16m\000"
1969 /* 5105 */ "RRC16m\000"
1970 /* 5112 */ "SEXT16m\000"
1971 /* 5120 */ "RRA8m\000"
1972 /* 5126 */ "RRC8m\000"
1973 /* 5132 */ "Bm\000"
1974 /* 5135 */ "CALLm\000"
1975 /* 5141 */ "SUB16mm\000"
1976 /* 5149 */ "SUBC16mm\000"
1977 /* 5158 */ "ADDC16mm\000"
1978 /* 5167 */ "BIC16mm\000"
1979 /* 5175 */ "DADD16mm\000"
1980 /* 5184 */ "AND16mm\000"
1981 /* 5192 */ "CMP16mm\000"
1982 /* 5200 */ "XOR16mm\000"
1983 /* 5208 */ "BIS16mm\000"
1984 /* 5216 */ "BIT16mm\000"
1985 /* 5224 */ "MOV16mm\000"
1986 /* 5232 */ "SUB8mm\000"
1987 /* 5239 */ "SUBC8mm\000"
1988 /* 5247 */ "ADDC8mm\000"
1989 /* 5255 */ "BIC8mm\000"
1990 /* 5262 */ "DADD8mm\000"
1991 /* 5270 */ "AND8mm\000"
1992 /* 5277 */ "CMP8mm\000"
1993 /* 5284 */ "XOR8mm\000"
1994 /* 5291 */ "BIS8mm\000"
1995 /* 5298 */ "BIT8mm\000"
1996 /* 5305 */ "MOV8mm\000"
1997 /* 5312 */ "SUB16rm\000"
1998 /* 5320 */ "SUBC16rm\000"
1999 /* 5329 */ "ADDC16rm\000"
2000 /* 5338 */ "BIC16rm\000"
2001 /* 5346 */ "DADD16rm\000"
2002 /* 5355 */ "AND16rm\000"
2003 /* 5363 */ "CMP16rm\000"
2004 /* 5371 */ "XOR16rm\000"
2005 /* 5379 */ "BIS16rm\000"
2006 /* 5387 */ "BIT16rm\000"
2007 /* 5395 */ "MOV16rm\000"
2008 /* 5403 */ "SUB8rm\000"
2009 /* 5410 */ "SUBC8rm\000"
2010 /* 5418 */ "ADDC8rm\000"
2011 /* 5426 */ "BIC8rm\000"
2012 /* 5433 */ "DADD8rm\000"
2013 /* 5441 */ "AND8rm\000"
2014 /* 5448 */ "CMP8rm\000"
2015 /* 5455 */ "XOR8rm\000"
2016 /* 5462 */ "BIS8rm\000"
2017 /* 5469 */ "BIT8rm\000"
2018 /* 5476 */ "MOV8rm\000"
2019 /* 5483 */ "RRA16n\000"
2020 /* 5490 */ "SWPB16n\000"
2021 /* 5498 */ "RRC16n\000"
2022 /* 5505 */ "SEXT16n\000"
2023 /* 5513 */ "RRA8n\000"
2024 /* 5519 */ "RRC8n\000"
2025 /* 5525 */ "CALLn\000"
2026 /* 5531 */ "SUB16mn\000"
2027 /* 5539 */ "SUBC16mn\000"
2028 /* 5548 */ "ADDC16mn\000"
2029 /* 5557 */ "BIC16mn\000"
2030 /* 5565 */ "DADD16mn\000"
2031 /* 5574 */ "AND16mn\000"
2032 /* 5582 */ "CMP16mn\000"
2033 /* 5590 */ "XOR16mn\000"
2034 /* 5598 */ "BIS16mn\000"
2035 /* 5606 */ "BIT16mn\000"
2036 /* 5614 */ "MOV16mn\000"
2037 /* 5622 */ "SUB8mn\000"
2038 /* 5629 */ "SUBC8mn\000"
2039 /* 5637 */ "ADDC8mn\000"
2040 /* 5645 */ "BIC8mn\000"
2041 /* 5652 */ "DADD8mn\000"
2042 /* 5660 */ "AND8mn\000"
2043 /* 5667 */ "CMP8mn\000"
2044 /* 5674 */ "XOR8mn\000"
2045 /* 5681 */ "BIS8mn\000"
2046 /* 5688 */ "BIT8mn\000"
2047 /* 5695 */ "MOV8mn\000"
2048 /* 5702 */ "SUB16rn\000"
2049 /* 5710 */ "SUBC16rn\000"
2050 /* 5719 */ "ADDC16rn\000"
2051 /* 5728 */ "BIC16rn\000"
2052 /* 5736 */ "DADD16rn\000"
2053 /* 5745 */ "AND16rn\000"
2054 /* 5753 */ "CMP16rn\000"
2055 /* 5761 */ "XOR16rn\000"
2056 /* 5769 */ "BIS16rn\000"
2057 /* 5777 */ "BIT16rn\000"
2058 /* 5785 */ "MOV16rn\000"
2059 /* 5793 */ "SUB8rn\000"
2060 /* 5800 */ "SUBC8rn\000"
2061 /* 5808 */ "ADDC8rn\000"
2062 /* 5816 */ "BIC8rn\000"
2063 /* 5823 */ "DADD8rn\000"
2064 /* 5831 */ "AND8rn\000"
2065 /* 5838 */ "CMP8rn\000"
2066 /* 5845 */ "XOR8rn\000"
2067 /* 5852 */ "BIS8rn\000"
2068 /* 5859 */ "BIT8rn\000"
2069 /* 5866 */ "MOV8rn\000"
2070 /* 5873 */ "RRA16p\000"
2071 /* 5880 */ "SWPB16p\000"
2072 /* 5888 */ "RRC16p\000"
2073 /* 5895 */ "SEXT16p\000"
2074 /* 5903 */ "RRA8p\000"
2075 /* 5909 */ "RRC8p\000"
2076 /* 5915 */ "CALLp\000"
2077 /* 5921 */ "SUB16mp\000"
2078 /* 5929 */ "SUBC16mp\000"
2079 /* 5938 */ "ADDC16mp\000"
2080 /* 5947 */ "BIC16mp\000"
2081 /* 5955 */ "DADD16mp\000"
2082 /* 5964 */ "AND16mp\000"
2083 /* 5972 */ "CMP16mp\000"
2084 /* 5980 */ "XOR16mp\000"
2085 /* 5988 */ "BIS16mp\000"
2086 /* 5996 */ "BIT16mp\000"
2087 /* 6004 */ "SUB8mp\000"
2088 /* 6011 */ "SUBC8mp\000"
2089 /* 6019 */ "ADDC8mp\000"
2090 /* 6027 */ "BIC8mp\000"
2091 /* 6034 */ "DADD8mp\000"
2092 /* 6042 */ "AND8mp\000"
2093 /* 6049 */ "CMP8mp\000"
2094 /* 6056 */ "XOR8mp\000"
2095 /* 6063 */ "BIS8mp\000"
2096 /* 6070 */ "BIT8mp\000"
2097 /* 6077 */ "SUB16rp\000"
2098 /* 6085 */ "SUBC16rp\000"
2099 /* 6094 */ "ADDC16rp\000"
2100 /* 6103 */ "BIC16rp\000"
2101 /* 6111 */ "DADD16rp\000"
2102 /* 6120 */ "AND16rp\000"
2103 /* 6128 */ "CMP16rp\000"
2104 /* 6136 */ "XOR16rp\000"
2105 /* 6144 */ "BIS16rp\000"
2106 /* 6152 */ "BIT16rp\000"
2107 /* 6160 */ "MOV16rp\000"
2108 /* 6168 */ "SUB8rp\000"
2109 /* 6175 */ "SUBC8rp\000"
2110 /* 6183 */ "ADDC8rp\000"
2111 /* 6191 */ "BIC8rp\000"
2112 /* 6198 */ "DADD8rp\000"
2113 /* 6206 */ "AND8rp\000"
2114 /* 6213 */ "CMP8rp\000"
2115 /* 6220 */ "XOR8rp\000"
2116 /* 6227 */ "BIS8rp\000"
2117 /* 6234 */ "BIT8rp\000"
2118 /* 6241 */ "MOV8rp\000"
2119 /* 6248 */ "RRA16r\000"
2120 /* 6255 */ "SWPB16r\000"
2121 /* 6263 */ "RRC16r\000"
2122 /* 6270 */ "PUSH16r\000"
2123 /* 6278 */ "POP16r\000"
2124 /* 6285 */ "SEXT16r\000"
2125 /* 6293 */ "ZEXT16r\000"
2126 /* 6301 */ "RRA8r\000"
2127 /* 6307 */ "RRC8r\000"
2128 /* 6313 */ "PUSH8r\000"
2129 /* 6320 */ "Br\000"
2130 /* 6323 */ "CALLr\000"
2131 /* 6329 */ "SUB16mr\000"
2132 /* 6337 */ "SUBC16mr\000"
2133 /* 6346 */ "ADDC16mr\000"
2134 /* 6355 */ "BIC16mr\000"
2135 /* 6363 */ "DADD16mr\000"
2136 /* 6372 */ "AND16mr\000"
2137 /* 6380 */ "CMP16mr\000"
2138 /* 6388 */ "XOR16mr\000"
2139 /* 6396 */ "BIS16mr\000"
2140 /* 6404 */ "BIT16mr\000"
2141 /* 6412 */ "MOV16mr\000"
2142 /* 6420 */ "SUB8mr\000"
2143 /* 6427 */ "SUBC8mr\000"
2144 /* 6435 */ "ADDC8mr\000"
2145 /* 6443 */ "BIC8mr\000"
2146 /* 6450 */ "DADD8mr\000"
2147 /* 6458 */ "AND8mr\000"
2148 /* 6465 */ "CMP8mr\000"
2149 /* 6472 */ "XOR8mr\000"
2150 /* 6479 */ "BIS8mr\000"
2151 /* 6486 */ "BIT8mr\000"
2152 /* 6493 */ "MOV8mr\000"
2153 /* 6500 */ "SUB16rr\000"
2154 /* 6508 */ "SUBC16rr\000"
2155 /* 6517 */ "ADDC16rr\000"
2156 /* 6526 */ "BIC16rr\000"
2157 /* 6534 */ "DADD16rr\000"
2158 /* 6543 */ "AND16rr\000"
2159 /* 6551 */ "CMP16rr\000"
2160 /* 6559 */ "XOR16rr\000"
2161 /* 6567 */ "BIS16rr\000"
2162 /* 6575 */ "BIT16rr\000"
2163 /* 6583 */ "MOV16rr\000"
2164 /* 6591 */ "SUB8rr\000"
2165 /* 6598 */ "SUBC8rr\000"
2166 /* 6606 */ "ADDC8rr\000"
2167 /* 6614 */ "BIC8rr\000"
2168 /* 6621 */ "DADD8rr\000"
2169 /* 6629 */ "AND8rr\000"
2170 /* 6636 */ "CMP8rr\000"
2171 /* 6643 */ "XOR8rr\000"
2172 /* 6650 */ "BIS8rr\000"
2173 /* 6657 */ "BIT8rr\000"
2174 /* 6664 */ "MOV8rr\000"
2175};
2176#ifdef __GNUC__
2177#pragma GCC diagnostic pop
2178#endif
2179
2180extern const unsigned MSP430InstrNameIndices[] = {
2181 1398U, 1817U, 2710U, 2271U, 1476U, 1457U, 1485U, 1645U,
2182 1182U, 1197U, 1148U, 1135U, 1224U, 3261U, 1011U, 3948U,
2183 1161U, 1394U, 1466U, 750U, 4331U, 1433U, 872U, 3852U,
2184 577U, 701U, 738U, 2420U, 1633U, 3762U, 684U, 2645U,
2185 1317U, 3751U, 922U, 2618U, 2605U, 2771U, 3610U, 3633U,
2186 1565U, 1612U, 1585U, 1502U, 1002U, 2736U, 2374U, 911U,
2187 4336U, 2898U, 2576U, 1059U, 3978U, 4008U, 2114U, 490U,
2188 185U, 1756U, 4080U, 4087U, 1783U, 1790U, 1797U, 1807U,
2189 555U, 3107U, 3070U, 3158U, 4022U, 2942U, 1554U, 2930U,
2190 1543U, 1146U, 1396U, 4254U, 1021U, 1036U, 1650U, 3578U,
2191 3165U, 3889U, 3182U, 2993U, 259U, 3244U, 3773U, 3134U,
2192 3921U, 1102U, 2747U, 658U, 233U, 640U, 3811U, 3792U,
2193 2092U, 2796U, 2815U, 391U, 335U, 365U, 304U, 376U,
2194 316U, 346U, 981U, 935U, 965U, 3291U, 1238U, 1255U,
2195 506U, 191U, 561U, 522U, 3112U, 3076U, 4238U, 2240U,
2196 4221U, 2223U, 457U, 168U, 4156U, 2158U, 1912U, 1859U,
2197 2033U, 1971U, 2482U, 2460U, 599U, 3531U, 730U, 1334U,
2198 590U, 3597U, 3867U, 211U, 3339U, 3728U, 3366U, 3992U,
2199 251U, 3404U, 4029U, 4044U, 3717U, 3705U, 3842U, 1309U,
2200 3971U, 1211U, 4001U, 1529U, 2882U, 2868U, 1522U, 2875U,
2201 3127U, 1666U, 2551U, 2530U, 2558U, 2565U, 3588U, 2366U,
2202 771U, 2350U, 722U, 2358U, 763U, 2342U, 714U, 2404U,
2203 2396U, 1362U, 1354U, 3449U, 3439U, 3429U, 3419U, 3469U,
2204 3459U, 4282U, 4292U, 3479U, 3492U, 4302U, 4312U, 3505U,
2205 3518U, 415U, 147U, 1690U, 128U, 297U, 4059U, 1762U,
2206 1127U, 4132U, 1425U, 2689U, 35U, 9U, 1302U, 18U,
2207 0U, 2664U, 2696U, 1175U, 3963U, 223U, 1402U, 1416U,
2208 2512U, 2521U, 3552U, 3565U, 3145U, 2129U, 3278U, 1111U,
2209 2057U, 2067U, 820U, 835U, 1848U, 1901U, 1957U, 2019U,
2210 4094U, 4120U, 4106U, 779U, 807U, 792U, 1272U, 1287U,
2211 496U, 1447U, 2192U, 4190U, 2216U, 4214U, 3152U, 631U,
2212 621U, 2705U, 3657U, 850U, 2974U, 2954U, 3685U, 3664U,
2213 3008U, 3039U, 3025U, 3321U, 4365U, 2306U, 4358U, 2287U,
2214 3197U, 2597U, 2504U, 989U, 1732U, 1345U, 2889U, 1535U,
2215 3212U, 2264U, 3219U, 2085U, 3204U, 2256U, 2077U, 26U,
2216 1386U, 1378U, 1370U, 3898U, 2921U, 3784U, 3829U, 3931U,
2217 2723U, 859U, 280U, 1080U, 950U, 443U, 154U, 1718U,
2218 4066U, 1769U, 134U, 3906U, 2673U, 2537U, 3229U, 2835U,
2219 2851U, 4322U, 895U, 1092U, 3624U, 2412U, 879U, 2453U,
2220 2429U, 2441U, 422U, 1697U, 398U, 1673U, 4139U, 2141U,
2221 1880U, 1827U, 1995U, 1933U, 474U, 1740U, 539U, 3092U,
2222 3054U, 4173U, 2175U, 4197U, 2199U, 4268U, 4275U, 4415U,
2223 4783U, 5176U, 5566U, 5956U, 6364U, 4586U, 4954U, 5347U,
2224 5737U, 6112U, 6535U, 4502U, 4870U, 5263U, 5653U, 6035U,
2225 6451U, 4673U, 5041U, 5434U, 5824U, 6199U, 6622U, 4397U,
2226 4765U, 5158U, 5548U, 5938U, 6346U, 4568U, 4936U, 5329U,
2227 5719U, 6094U, 6517U, 4486U, 4854U, 5247U, 5637U, 6019U,
2228 6435U, 4657U, 5025U, 5418U, 5808U, 6183U, 6606U, 4722U,
2229 2325U, 2630U, 4423U, 4791U, 5184U, 5574U, 5964U, 6372U,
2230 4594U, 4962U, 5355U, 5745U, 6120U, 6543U, 4509U, 4877U,
2231 5270U, 5660U, 6042U, 6458U, 4680U, 5048U, 5441U, 5831U,
2232 6206U, 6629U, 4406U, 4774U, 5167U, 5557U, 5947U, 6355U,
2233 4577U, 4945U, 5338U, 5728U, 6103U, 6526U, 4494U, 4862U,
2234 5255U, 5645U, 6027U, 6443U, 4665U, 5033U, 5426U, 5816U,
2235 6191U, 6614U, 4447U, 4815U, 5208U, 5598U, 5988U, 6396U,
2236 4618U, 4986U, 5379U, 5769U, 6144U, 6567U, 4530U, 4898U,
2237 5291U, 5681U, 6063U, 6479U, 4701U, 5069U, 5462U, 5852U,
2238 6227U, 6650U, 4455U, 4823U, 5216U, 5606U, 5996U, 6404U,
2239 4626U, 4994U, 5387U, 5777U, 6152U, 6575U, 4537U, 4905U,
2240 5298U, 5688U, 6070U, 6486U, 4708U, 5076U, 5469U, 5859U,
2241 6234U, 6657U, 4739U, 5132U, 6320U, 4742U, 5135U, 5525U,
2242 5915U, 6323U, 4431U, 4799U, 5192U, 5582U, 5972U, 6380U,
2243 4602U, 4970U, 5363U, 5753U, 6128U, 6551U, 4516U, 4884U,
2244 5277U, 5667U, 6049U, 6465U, 4687U, 5055U, 5448U, 5838U,
2245 6213U, 6636U, 4414U, 4782U, 5175U, 5565U, 5955U, 6363U,
2246 4585U, 4953U, 5346U, 5736U, 6111U, 6534U, 4501U, 4869U,
2247 5262U, 5652U, 6034U, 6450U, 4672U, 5040U, 5433U, 5823U,
2248 6198U, 6621U, 207U, 2572U, 4463U, 4831U, 5224U, 5614U,
2249 6412U, 4634U, 5002U, 5395U, 5785U, 6160U, 6583U, 4544U,
2250 4912U, 5305U, 5695U, 6493U, 4715U, 5083U, 5476U, 5866U,
2251 6241U, 6664U, 98U, 109U, 6278U, 4372U, 4731U, 6270U,
2252 6313U, 3620U, 1411U, 5090U, 5483U, 5873U, 6248U, 5120U,
2253 5513U, 5903U, 6301U, 5105U, 5498U, 5888U, 6263U, 5126U,
2254 5519U, 5909U, 6307U, 49U, 82U, 5112U, 5505U, 5895U,
2255 6285U, 4380U, 4748U, 5141U, 5531U, 5921U, 6329U, 4551U,
2256 4919U, 5312U, 5702U, 6077U, 6500U, 4471U, 4839U, 5232U,
2257 5622U, 6004U, 6420U, 4642U, 5010U, 5403U, 5793U, 6168U,
2258 6591U, 4388U, 4756U, 5149U, 5539U, 5929U, 6337U, 4559U,
2259 4927U, 5320U, 5710U, 6085U, 6508U, 4478U, 4846U, 5239U,
2260 5629U, 6011U, 6427U, 4649U, 5017U, 5410U, 5800U, 6175U,
2261 6598U, 5097U, 5490U, 5880U, 6255U, 68U, 120U, 56U,
2262 88U, 43U, 77U, 62U, 93U, 4439U, 4807U, 5200U,
2263 5590U, 5980U, 6388U, 4610U, 4978U, 5371U, 5761U, 6136U,
2264 6559U, 4523U, 4891U, 5284U, 5674U, 6056U, 6472U, 4694U,
2265 5062U, 5455U, 5845U, 6220U, 6643U, 6293U,
2266};
2267
2268static inline void InitMSP430MCInstrInfo(MCInstrInfo *II) {
2269 II->InitMCInstrInfo(MSP430Descs.Insts, MSP430InstrNameIndices, MSP430InstrNameData, nullptr, nullptr, 678, nullptr, 0);
2270}
2271
2272
2273} // namespace llvm
2274
2275#endif // GET_INSTRINFO_MC_DESC
2276
2277#ifdef GET_INSTRINFO_HEADER
2278#undef GET_INSTRINFO_HEADER
2279
2280namespace llvm {
2281
2282struct MSP430GenInstrInfo : public TargetInstrInfo {
2283 explicit MSP430GenInstrInfo(const TargetSubtargetInfo &STI, const TargetRegisterInfo &TRI, unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u, unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u);
2284 ~MSP430GenInstrInfo() override = default;
2285};
2286
2287} // namespace llvm
2288
2289namespace llvm::MSP430 {
2290
2291
2292} // namespace llvm::MSP430
2293
2294#endif // GET_INSTRINFO_HEADER
2295
2296#ifdef GET_INSTRINFO_HELPER_DECLS
2297#undef GET_INSTRINFO_HELPER_DECLS
2298
2299
2300#endif // GET_INSTRINFO_HELPER_DECLS
2301
2302#ifdef GET_INSTRINFO_HELPERS
2303#undef GET_INSTRINFO_HELPERS
2304
2305
2306#endif // GET_INSTRINFO_HELPERS
2307
2308#ifdef GET_INSTRINFO_CTOR_DTOR
2309#undef GET_INSTRINFO_CTOR_DTOR
2310
2311namespace llvm {
2312
2313extern const MSP430InstrTable MSP430Descs;
2314extern const unsigned MSP430InstrNameIndices[];
2315extern const char MSP430InstrNameData[];
2316MSP430GenInstrInfo::MSP430GenInstrInfo(const TargetSubtargetInfo &STI, const TargetRegisterInfo &TRI, unsigned CFSetupOpcode, unsigned CFDestroyOpcode, unsigned CatchRetOpcode, unsigned ReturnOpcode)
2317 : TargetInstrInfo(TRI, CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) {
2318 InitMCInstrInfo(MSP430Descs.Insts, MSP430InstrNameIndices, MSP430InstrNameData, nullptr, nullptr, 678);
2319}
2320
2321} // namespace llvm
2322
2323#endif // GET_INSTRINFO_CTOR_DTOR
2324
2325#ifdef GET_INSTRINFO_MC_HELPER_DECLS
2326#undef GET_INSTRINFO_MC_HELPER_DECLS
2327
2328namespace llvm {
2329
2330class MCInst;
2331class FeatureBitset;
2332
2333namespace MSP430_MC {
2334
2335void verifyInstructionPredicates(unsigned Opcode, const FeatureBitset &Features);
2336
2337} // namespace MSP430_MC
2338
2339} // namespace llvm
2340
2341#endif // GET_INSTRINFO_MC_HELPER_DECLS
2342
2343#ifdef GET_INSTRINFO_MC_HELPERS
2344#undef GET_INSTRINFO_MC_HELPERS
2345
2346namespace llvm::MSP430_MC {
2347
2348
2349} // namespace llvm::MSP430_MC
2350
2351#endif // GET_INSTRINFO_MC_HELPERS
2352
2353#if (defined(ENABLE_INSTR_PREDICATE_VERIFIER) && !defined(NDEBUG)) ||\
2354 defined(GET_AVAILABLE_OPCODE_CHECKER)
2355#define GET_COMPUTE_FEATURES
2356#endif
2357#ifdef GET_COMPUTE_FEATURES
2358#undef GET_COMPUTE_FEATURES
2359
2360namespace llvm::MSP430_MC {
2361
2362// Bits for subtarget features that participate in instruction matching.
2363enum SubtargetFeatureBits : uint8_t {
2364};
2365
2366inline FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) {
2367 FeatureBitset Features;
2368 return Features;
2369}
2370
2371inline FeatureBitset computeRequiredFeatures(unsigned Opcode) {
2372 enum : uint8_t {
2373 CEFBS_None,
2374 };
2375
2376 static constexpr FeatureBitset FeatureBitsets[] = {
2377 {}, // CEFBS_None
2378 };
2379 static constexpr uint8_t RequiredFeaturesRefs[] = {
2380 CEFBS_None, // PHI
2381 CEFBS_None, // INLINEASM
2382 CEFBS_None, // INLINEASM_BR
2383 CEFBS_None, // CFI_INSTRUCTION
2384 CEFBS_None, // EH_LABEL
2385 CEFBS_None, // GC_LABEL
2386 CEFBS_None, // ANNOTATION_LABEL
2387 CEFBS_None, // KILL
2388 CEFBS_None, // EXTRACT_SUBREG
2389 CEFBS_None, // INSERT_SUBREG
2390 CEFBS_None, // IMPLICIT_DEF
2391 CEFBS_None, // INIT_UNDEF
2392 CEFBS_None, // SUBREG_TO_REG
2393 CEFBS_None, // COPY_TO_REGCLASS
2394 CEFBS_None, // DBG_VALUE
2395 CEFBS_None, // DBG_VALUE_LIST
2396 CEFBS_None, // DBG_INSTR_REF
2397 CEFBS_None, // DBG_PHI
2398 CEFBS_None, // DBG_LABEL
2399 CEFBS_None, // REG_SEQUENCE
2400 CEFBS_None, // COPY
2401 CEFBS_None, // COPY_LANEMASK
2402 CEFBS_None, // BUNDLE
2403 CEFBS_None, // LIFETIME_START
2404 CEFBS_None, // LIFETIME_END
2405 CEFBS_None, // PSEUDO_PROBE
2406 CEFBS_None, // ARITH_FENCE
2407 CEFBS_None, // STACKMAP
2408 CEFBS_None, // FENTRY_CALL
2409 CEFBS_None, // PATCHPOINT
2410 CEFBS_None, // LOAD_STACK_GUARD
2411 CEFBS_None, // PREALLOCATED_SETUP
2412 CEFBS_None, // PREALLOCATED_ARG
2413 CEFBS_None, // STATEPOINT
2414 CEFBS_None, // LOCAL_ESCAPE
2415 CEFBS_None, // FAULTING_OP
2416 CEFBS_None, // PATCHABLE_OP
2417 CEFBS_None, // PATCHABLE_FUNCTION_ENTER
2418 CEFBS_None, // PATCHABLE_RET
2419 CEFBS_None, // PATCHABLE_FUNCTION_EXIT
2420 CEFBS_None, // PATCHABLE_TAIL_CALL
2421 CEFBS_None, // PATCHABLE_EVENT_CALL
2422 CEFBS_None, // PATCHABLE_TYPED_EVENT_CALL
2423 CEFBS_None, // ICALL_BRANCH_FUNNEL
2424 CEFBS_None, // FAKE_USE
2425 CEFBS_None, // MEMBARRIER
2426 CEFBS_None, // JUMP_TABLE_DEBUG_INFO
2427 CEFBS_None, // RELOC_NONE
2428 CEFBS_None, // CONVERGENCECTRL_ENTRY
2429 CEFBS_None, // CONVERGENCECTRL_ANCHOR
2430 CEFBS_None, // CONVERGENCECTRL_LOOP
2431 CEFBS_None, // CONVERGENCECTRL_GLUE
2432 CEFBS_None, // G_ASSERT_SEXT
2433 CEFBS_None, // G_ASSERT_ZEXT
2434 CEFBS_None, // G_ASSERT_ALIGN
2435 CEFBS_None, // G_ADD
2436 CEFBS_None, // G_SUB
2437 CEFBS_None, // G_MUL
2438 CEFBS_None, // G_SDIV
2439 CEFBS_None, // G_UDIV
2440 CEFBS_None, // G_SREM
2441 CEFBS_None, // G_UREM
2442 CEFBS_None, // G_SDIVREM
2443 CEFBS_None, // G_UDIVREM
2444 CEFBS_None, // G_AND
2445 CEFBS_None, // G_OR
2446 CEFBS_None, // G_XOR
2447 CEFBS_None, // G_ABDS
2448 CEFBS_None, // G_ABDU
2449 CEFBS_None, // G_UAVGFLOOR
2450 CEFBS_None, // G_UAVGCEIL
2451 CEFBS_None, // G_SAVGFLOOR
2452 CEFBS_None, // G_SAVGCEIL
2453 CEFBS_None, // G_IMPLICIT_DEF
2454 CEFBS_None, // G_PHI
2455 CEFBS_None, // G_FRAME_INDEX
2456 CEFBS_None, // G_GLOBAL_VALUE
2457 CEFBS_None, // G_PTRAUTH_GLOBAL_VALUE
2458 CEFBS_None, // G_CONSTANT_POOL
2459 CEFBS_None, // G_EXTRACT
2460 CEFBS_None, // G_UNMERGE_VALUES
2461 CEFBS_None, // G_INSERT
2462 CEFBS_None, // G_MERGE_VALUES
2463 CEFBS_None, // G_BUILD_VECTOR
2464 CEFBS_None, // G_BUILD_VECTOR_TRUNC
2465 CEFBS_None, // G_CONCAT_VECTORS
2466 CEFBS_None, // G_PTRTOINT
2467 CEFBS_None, // G_INTTOPTR
2468 CEFBS_None, // G_BITCAST
2469 CEFBS_None, // G_FREEZE
2470 CEFBS_None, // G_CONSTANT_FOLD_BARRIER
2471 CEFBS_None, // G_INTRINSIC_FPTRUNC_ROUND
2472 CEFBS_None, // G_INTRINSIC_TRUNC
2473 CEFBS_None, // G_INTRINSIC_ROUND
2474 CEFBS_None, // G_INTRINSIC_LRINT
2475 CEFBS_None, // G_INTRINSIC_LLRINT
2476 CEFBS_None, // G_INTRINSIC_ROUNDEVEN
2477 CEFBS_None, // G_READCYCLECOUNTER
2478 CEFBS_None, // G_READSTEADYCOUNTER
2479 CEFBS_None, // G_LOAD
2480 CEFBS_None, // G_SEXTLOAD
2481 CEFBS_None, // G_ZEXTLOAD
2482 CEFBS_None, // G_FPEXTLOAD
2483 CEFBS_None, // G_INDEXED_LOAD
2484 CEFBS_None, // G_INDEXED_SEXTLOAD
2485 CEFBS_None, // G_INDEXED_ZEXTLOAD
2486 CEFBS_None, // G_STORE
2487 CEFBS_None, // G_FPTRUNCSTORE
2488 CEFBS_None, // G_INDEXED_STORE
2489 CEFBS_None, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
2490 CEFBS_None, // G_ATOMIC_CMPXCHG
2491 CEFBS_None, // G_ATOMICRMW_XCHG
2492 CEFBS_None, // G_ATOMICRMW_ADD
2493 CEFBS_None, // G_ATOMICRMW_SUB
2494 CEFBS_None, // G_ATOMICRMW_AND
2495 CEFBS_None, // G_ATOMICRMW_NAND
2496 CEFBS_None, // G_ATOMICRMW_OR
2497 CEFBS_None, // G_ATOMICRMW_XOR
2498 CEFBS_None, // G_ATOMICRMW_MAX
2499 CEFBS_None, // G_ATOMICRMW_MIN
2500 CEFBS_None, // G_ATOMICRMW_UMAX
2501 CEFBS_None, // G_ATOMICRMW_UMIN
2502 CEFBS_None, // G_ATOMICRMW_FADD
2503 CEFBS_None, // G_ATOMICRMW_FSUB
2504 CEFBS_None, // G_ATOMICRMW_FMAX
2505 CEFBS_None, // G_ATOMICRMW_FMIN
2506 CEFBS_None, // G_ATOMICRMW_FMAXIMUM
2507 CEFBS_None, // G_ATOMICRMW_FMINIMUM
2508 CEFBS_None, // G_ATOMICRMW_FMAXIMUMNUM
2509 CEFBS_None, // G_ATOMICRMW_FMINIMUMNUM
2510 CEFBS_None, // G_ATOMICRMW_UINC_WRAP
2511 CEFBS_None, // G_ATOMICRMW_UDEC_WRAP
2512 CEFBS_None, // G_ATOMICRMW_USUB_COND
2513 CEFBS_None, // G_ATOMICRMW_USUB_SAT
2514 CEFBS_None, // G_FENCE
2515 CEFBS_None, // G_PREFETCH
2516 CEFBS_None, // G_BRCOND
2517 CEFBS_None, // G_BRINDIRECT
2518 CEFBS_None, // G_INVOKE_REGION_START
2519 CEFBS_None, // G_INTRINSIC
2520 CEFBS_None, // G_INTRINSIC_W_SIDE_EFFECTS
2521 CEFBS_None, // G_INTRINSIC_CONVERGENT
2522 CEFBS_None, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
2523 CEFBS_None, // G_ANYEXT
2524 CEFBS_None, // G_TRUNC
2525 CEFBS_None, // G_TRUNC_SSAT_S
2526 CEFBS_None, // G_TRUNC_SSAT_U
2527 CEFBS_None, // G_TRUNC_USAT_U
2528 CEFBS_None, // G_CONSTANT
2529 CEFBS_None, // G_FCONSTANT
2530 CEFBS_None, // G_VASTART
2531 CEFBS_None, // G_VAARG
2532 CEFBS_None, // G_SEXT
2533 CEFBS_None, // G_SEXT_INREG
2534 CEFBS_None, // G_ZEXT
2535 CEFBS_None, // G_SHL
2536 CEFBS_None, // G_LSHR
2537 CEFBS_None, // G_ASHR
2538 CEFBS_None, // G_FSHL
2539 CEFBS_None, // G_FSHR
2540 CEFBS_None, // G_ROTR
2541 CEFBS_None, // G_ROTL
2542 CEFBS_None, // G_ICMP
2543 CEFBS_None, // G_FCMP
2544 CEFBS_None, // G_SCMP
2545 CEFBS_None, // G_UCMP
2546 CEFBS_None, // G_SELECT
2547 CEFBS_None, // G_UADDO
2548 CEFBS_None, // G_UADDE
2549 CEFBS_None, // G_USUBO
2550 CEFBS_None, // G_USUBE
2551 CEFBS_None, // G_SADDO
2552 CEFBS_None, // G_SADDE
2553 CEFBS_None, // G_SSUBO
2554 CEFBS_None, // G_SSUBE
2555 CEFBS_None, // G_UMULO
2556 CEFBS_None, // G_SMULO
2557 CEFBS_None, // G_UMULH
2558 CEFBS_None, // G_SMULH
2559 CEFBS_None, // G_UADDSAT
2560 CEFBS_None, // G_SADDSAT
2561 CEFBS_None, // G_USUBSAT
2562 CEFBS_None, // G_SSUBSAT
2563 CEFBS_None, // G_USHLSAT
2564 CEFBS_None, // G_SSHLSAT
2565 CEFBS_None, // G_SMULFIX
2566 CEFBS_None, // G_UMULFIX
2567 CEFBS_None, // G_SMULFIXSAT
2568 CEFBS_None, // G_UMULFIXSAT
2569 CEFBS_None, // G_SDIVFIX
2570 CEFBS_None, // G_UDIVFIX
2571 CEFBS_None, // G_SDIVFIXSAT
2572 CEFBS_None, // G_UDIVFIXSAT
2573 CEFBS_None, // G_FADD
2574 CEFBS_None, // G_FSUB
2575 CEFBS_None, // G_FMUL
2576 CEFBS_None, // G_FMA
2577 CEFBS_None, // G_FMAD
2578 CEFBS_None, // G_FDIV
2579 CEFBS_None, // G_FREM
2580 CEFBS_None, // G_FMODF
2581 CEFBS_None, // G_FPOW
2582 CEFBS_None, // G_FPOWI
2583 CEFBS_None, // G_FEXP
2584 CEFBS_None, // G_FEXP2
2585 CEFBS_None, // G_FEXP10
2586 CEFBS_None, // G_FLOG
2587 CEFBS_None, // G_FLOG2
2588 CEFBS_None, // G_FLOG10
2589 CEFBS_None, // G_FLDEXP
2590 CEFBS_None, // G_FFREXP
2591 CEFBS_None, // G_FNEG
2592 CEFBS_None, // G_FPEXT
2593 CEFBS_None, // G_FPTRUNC
2594 CEFBS_None, // G_FPTOSI
2595 CEFBS_None, // G_FPTOUI
2596 CEFBS_None, // G_SITOFP
2597 CEFBS_None, // G_UITOFP
2598 CEFBS_None, // G_FPTOSI_SAT
2599 CEFBS_None, // G_FPTOUI_SAT
2600 CEFBS_None, // G_FABS
2601 CEFBS_None, // G_FCOPYSIGN
2602 CEFBS_None, // G_IS_FPCLASS
2603 CEFBS_None, // G_FCANONICALIZE
2604 CEFBS_None, // G_FMINNUM
2605 CEFBS_None, // G_FMAXNUM
2606 CEFBS_None, // G_FMINNUM_IEEE
2607 CEFBS_None, // G_FMAXNUM_IEEE
2608 CEFBS_None, // G_FMINIMUM
2609 CEFBS_None, // G_FMAXIMUM
2610 CEFBS_None, // G_FMINIMUMNUM
2611 CEFBS_None, // G_FMAXIMUMNUM
2612 CEFBS_None, // G_GET_FPENV
2613 CEFBS_None, // G_SET_FPENV
2614 CEFBS_None, // G_RESET_FPENV
2615 CEFBS_None, // G_GET_FPMODE
2616 CEFBS_None, // G_SET_FPMODE
2617 CEFBS_None, // G_RESET_FPMODE
2618 CEFBS_None, // G_GET_ROUNDING
2619 CEFBS_None, // G_SET_ROUNDING
2620 CEFBS_None, // G_PTR_ADD
2621 CEFBS_None, // G_PTRMASK
2622 CEFBS_None, // G_SMIN
2623 CEFBS_None, // G_SMAX
2624 CEFBS_None, // G_UMIN
2625 CEFBS_None, // G_UMAX
2626 CEFBS_None, // G_ABS
2627 CEFBS_None, // G_LROUND
2628 CEFBS_None, // G_LLROUND
2629 CEFBS_None, // G_BR
2630 CEFBS_None, // G_BRJT
2631 CEFBS_None, // G_VSCALE
2632 CEFBS_None, // G_INSERT_SUBVECTOR
2633 CEFBS_None, // G_EXTRACT_SUBVECTOR
2634 CEFBS_None, // G_INSERT_VECTOR_ELT
2635 CEFBS_None, // G_EXTRACT_VECTOR_ELT
2636 CEFBS_None, // G_SHUFFLE_VECTOR
2637 CEFBS_None, // G_SPLAT_VECTOR
2638 CEFBS_None, // G_STEP_VECTOR
2639 CEFBS_None, // G_VECTOR_COMPRESS
2640 CEFBS_None, // G_CTTZ
2641 CEFBS_None, // G_CTTZ_ZERO_POISON
2642 CEFBS_None, // G_CTLZ
2643 CEFBS_None, // G_CTLZ_ZERO_POISON
2644 CEFBS_None, // G_CTLS
2645 CEFBS_None, // G_CTPOP
2646 CEFBS_None, // G_BSWAP
2647 CEFBS_None, // G_BITREVERSE
2648 CEFBS_None, // G_CLMUL
2649 CEFBS_None, // G_CLMULH
2650 CEFBS_None, // G_CLMULR
2651 CEFBS_None, // G_FCEIL
2652 CEFBS_None, // G_FCOS
2653 CEFBS_None, // G_FSIN
2654 CEFBS_None, // G_FSINCOS
2655 CEFBS_None, // G_FTAN
2656 CEFBS_None, // G_FACOS
2657 CEFBS_None, // G_FASIN
2658 CEFBS_None, // G_FATAN
2659 CEFBS_None, // G_FATAN2
2660 CEFBS_None, // G_FCOSH
2661 CEFBS_None, // G_FSINH
2662 CEFBS_None, // G_FTANH
2663 CEFBS_None, // G_FSQRT
2664 CEFBS_None, // G_FFLOOR
2665 CEFBS_None, // G_FRINT
2666 CEFBS_None, // G_FNEARBYINT
2667 CEFBS_None, // G_ADDRSPACE_CAST
2668 CEFBS_None, // G_BLOCK_ADDR
2669 CEFBS_None, // G_JUMP_TABLE
2670 CEFBS_None, // G_DYN_STACKALLOC
2671 CEFBS_None, // G_STACKSAVE
2672 CEFBS_None, // G_STACKRESTORE
2673 CEFBS_None, // G_STRICT_FADD
2674 CEFBS_None, // G_STRICT_FSUB
2675 CEFBS_None, // G_STRICT_FMUL
2676 CEFBS_None, // G_STRICT_FDIV
2677 CEFBS_None, // G_STRICT_FREM
2678 CEFBS_None, // G_STRICT_FMA
2679 CEFBS_None, // G_STRICT_FSQRT
2680 CEFBS_None, // G_STRICT_FLDEXP
2681 CEFBS_None, // G_STRICT_FCMP
2682 CEFBS_None, // G_STRICT_FCMPS
2683 CEFBS_None, // G_READ_REGISTER
2684 CEFBS_None, // G_WRITE_REGISTER
2685 CEFBS_None, // G_MEMCPY
2686 CEFBS_None, // G_MEMCPY_INLINE
2687 CEFBS_None, // G_MEMMOVE
2688 CEFBS_None, // G_MEMSET
2689 CEFBS_None, // G_BZERO
2690 CEFBS_None, // G_MEMSET_INLINE
2691 CEFBS_None, // G_TRAP
2692 CEFBS_None, // G_DEBUGTRAP
2693 CEFBS_None, // G_UBSANTRAP
2694 CEFBS_None, // G_VECREDUCE_SEQ_FADD
2695 CEFBS_None, // G_VECREDUCE_SEQ_FMUL
2696 CEFBS_None, // G_VECREDUCE_FADD
2697 CEFBS_None, // G_VECREDUCE_FMUL
2698 CEFBS_None, // G_VECREDUCE_FMAX
2699 CEFBS_None, // G_VECREDUCE_FMIN
2700 CEFBS_None, // G_VECREDUCE_FMAXIMUM
2701 CEFBS_None, // G_VECREDUCE_FMINIMUM
2702 CEFBS_None, // G_VECREDUCE_FMAXIMUMNUM
2703 CEFBS_None, // G_VECREDUCE_FMINIMUMNUM
2704 CEFBS_None, // G_VECREDUCE_ADD
2705 CEFBS_None, // G_VECREDUCE_MUL
2706 CEFBS_None, // G_VECREDUCE_AND
2707 CEFBS_None, // G_VECREDUCE_OR
2708 CEFBS_None, // G_VECREDUCE_XOR
2709 CEFBS_None, // G_VECREDUCE_SMAX
2710 CEFBS_None, // G_VECREDUCE_SMIN
2711 CEFBS_None, // G_VECREDUCE_UMAX
2712 CEFBS_None, // G_VECREDUCE_UMIN
2713 CEFBS_None, // G_SBFX
2714 CEFBS_None, // G_UBFX
2715 CEFBS_None, // ADD16mc
2716 CEFBS_None, // ADD16mi
2717 CEFBS_None, // ADD16mm
2718 CEFBS_None, // ADD16mn
2719 CEFBS_None, // ADD16mp
2720 CEFBS_None, // ADD16mr
2721 CEFBS_None, // ADD16rc
2722 CEFBS_None, // ADD16ri
2723 CEFBS_None, // ADD16rm
2724 CEFBS_None, // ADD16rn
2725 CEFBS_None, // ADD16rp
2726 CEFBS_None, // ADD16rr
2727 CEFBS_None, // ADD8mc
2728 CEFBS_None, // ADD8mi
2729 CEFBS_None, // ADD8mm
2730 CEFBS_None, // ADD8mn
2731 CEFBS_None, // ADD8mp
2732 CEFBS_None, // ADD8mr
2733 CEFBS_None, // ADD8rc
2734 CEFBS_None, // ADD8ri
2735 CEFBS_None, // ADD8rm
2736 CEFBS_None, // ADD8rn
2737 CEFBS_None, // ADD8rp
2738 CEFBS_None, // ADD8rr
2739 CEFBS_None, // ADDC16mc
2740 CEFBS_None, // ADDC16mi
2741 CEFBS_None, // ADDC16mm
2742 CEFBS_None, // ADDC16mn
2743 CEFBS_None, // ADDC16mp
2744 CEFBS_None, // ADDC16mr
2745 CEFBS_None, // ADDC16rc
2746 CEFBS_None, // ADDC16ri
2747 CEFBS_None, // ADDC16rm
2748 CEFBS_None, // ADDC16rn
2749 CEFBS_None, // ADDC16rp
2750 CEFBS_None, // ADDC16rr
2751 CEFBS_None, // ADDC8mc
2752 CEFBS_None, // ADDC8mi
2753 CEFBS_None, // ADDC8mm
2754 CEFBS_None, // ADDC8mn
2755 CEFBS_None, // ADDC8mp
2756 CEFBS_None, // ADDC8mr
2757 CEFBS_None, // ADDC8rc
2758 CEFBS_None, // ADDC8ri
2759 CEFBS_None, // ADDC8rm
2760 CEFBS_None, // ADDC8rn
2761 CEFBS_None, // ADDC8rp
2762 CEFBS_None, // ADDC8rr
2763 CEFBS_None, // ADDframe
2764 CEFBS_None, // ADJCALLSTACKDOWN
2765 CEFBS_None, // ADJCALLSTACKUP
2766 CEFBS_None, // AND16mc
2767 CEFBS_None, // AND16mi
2768 CEFBS_None, // AND16mm
2769 CEFBS_None, // AND16mn
2770 CEFBS_None, // AND16mp
2771 CEFBS_None, // AND16mr
2772 CEFBS_None, // AND16rc
2773 CEFBS_None, // AND16ri
2774 CEFBS_None, // AND16rm
2775 CEFBS_None, // AND16rn
2776 CEFBS_None, // AND16rp
2777 CEFBS_None, // AND16rr
2778 CEFBS_None, // AND8mc
2779 CEFBS_None, // AND8mi
2780 CEFBS_None, // AND8mm
2781 CEFBS_None, // AND8mn
2782 CEFBS_None, // AND8mp
2783 CEFBS_None, // AND8mr
2784 CEFBS_None, // AND8rc
2785 CEFBS_None, // AND8ri
2786 CEFBS_None, // AND8rm
2787 CEFBS_None, // AND8rn
2788 CEFBS_None, // AND8rp
2789 CEFBS_None, // AND8rr
2790 CEFBS_None, // BIC16mc
2791 CEFBS_None, // BIC16mi
2792 CEFBS_None, // BIC16mm
2793 CEFBS_None, // BIC16mn
2794 CEFBS_None, // BIC16mp
2795 CEFBS_None, // BIC16mr
2796 CEFBS_None, // BIC16rc
2797 CEFBS_None, // BIC16ri
2798 CEFBS_None, // BIC16rm
2799 CEFBS_None, // BIC16rn
2800 CEFBS_None, // BIC16rp
2801 CEFBS_None, // BIC16rr
2802 CEFBS_None, // BIC8mc
2803 CEFBS_None, // BIC8mi
2804 CEFBS_None, // BIC8mm
2805 CEFBS_None, // BIC8mn
2806 CEFBS_None, // BIC8mp
2807 CEFBS_None, // BIC8mr
2808 CEFBS_None, // BIC8rc
2809 CEFBS_None, // BIC8ri
2810 CEFBS_None, // BIC8rm
2811 CEFBS_None, // BIC8rn
2812 CEFBS_None, // BIC8rp
2813 CEFBS_None, // BIC8rr
2814 CEFBS_None, // BIS16mc
2815 CEFBS_None, // BIS16mi
2816 CEFBS_None, // BIS16mm
2817 CEFBS_None, // BIS16mn
2818 CEFBS_None, // BIS16mp
2819 CEFBS_None, // BIS16mr
2820 CEFBS_None, // BIS16rc
2821 CEFBS_None, // BIS16ri
2822 CEFBS_None, // BIS16rm
2823 CEFBS_None, // BIS16rn
2824 CEFBS_None, // BIS16rp
2825 CEFBS_None, // BIS16rr
2826 CEFBS_None, // BIS8mc
2827 CEFBS_None, // BIS8mi
2828 CEFBS_None, // BIS8mm
2829 CEFBS_None, // BIS8mn
2830 CEFBS_None, // BIS8mp
2831 CEFBS_None, // BIS8mr
2832 CEFBS_None, // BIS8rc
2833 CEFBS_None, // BIS8ri
2834 CEFBS_None, // BIS8rm
2835 CEFBS_None, // BIS8rn
2836 CEFBS_None, // BIS8rp
2837 CEFBS_None, // BIS8rr
2838 CEFBS_None, // BIT16mc
2839 CEFBS_None, // BIT16mi
2840 CEFBS_None, // BIT16mm
2841 CEFBS_None, // BIT16mn
2842 CEFBS_None, // BIT16mp
2843 CEFBS_None, // BIT16mr
2844 CEFBS_None, // BIT16rc
2845 CEFBS_None, // BIT16ri
2846 CEFBS_None, // BIT16rm
2847 CEFBS_None, // BIT16rn
2848 CEFBS_None, // BIT16rp
2849 CEFBS_None, // BIT16rr
2850 CEFBS_None, // BIT8mc
2851 CEFBS_None, // BIT8mi
2852 CEFBS_None, // BIT8mm
2853 CEFBS_None, // BIT8mn
2854 CEFBS_None, // BIT8mp
2855 CEFBS_None, // BIT8mr
2856 CEFBS_None, // BIT8rc
2857 CEFBS_None, // BIT8ri
2858 CEFBS_None, // BIT8rm
2859 CEFBS_None, // BIT8rn
2860 CEFBS_None, // BIT8rp
2861 CEFBS_None, // BIT8rr
2862 CEFBS_None, // Bi
2863 CEFBS_None, // Bm
2864 CEFBS_None, // Br
2865 CEFBS_None, // CALLi
2866 CEFBS_None, // CALLm
2867 CEFBS_None, // CALLn
2868 CEFBS_None, // CALLp
2869 CEFBS_None, // CALLr
2870 CEFBS_None, // CMP16mc
2871 CEFBS_None, // CMP16mi
2872 CEFBS_None, // CMP16mm
2873 CEFBS_None, // CMP16mn
2874 CEFBS_None, // CMP16mp
2875 CEFBS_None, // CMP16mr
2876 CEFBS_None, // CMP16rc
2877 CEFBS_None, // CMP16ri
2878 CEFBS_None, // CMP16rm
2879 CEFBS_None, // CMP16rn
2880 CEFBS_None, // CMP16rp
2881 CEFBS_None, // CMP16rr
2882 CEFBS_None, // CMP8mc
2883 CEFBS_None, // CMP8mi
2884 CEFBS_None, // CMP8mm
2885 CEFBS_None, // CMP8mn
2886 CEFBS_None, // CMP8mp
2887 CEFBS_None, // CMP8mr
2888 CEFBS_None, // CMP8rc
2889 CEFBS_None, // CMP8ri
2890 CEFBS_None, // CMP8rm
2891 CEFBS_None, // CMP8rn
2892 CEFBS_None, // CMP8rp
2893 CEFBS_None, // CMP8rr
2894 CEFBS_None, // DADD16mc
2895 CEFBS_None, // DADD16mi
2896 CEFBS_None, // DADD16mm
2897 CEFBS_None, // DADD16mn
2898 CEFBS_None, // DADD16mp
2899 CEFBS_None, // DADD16mr
2900 CEFBS_None, // DADD16rc
2901 CEFBS_None, // DADD16ri
2902 CEFBS_None, // DADD16rm
2903 CEFBS_None, // DADD16rn
2904 CEFBS_None, // DADD16rp
2905 CEFBS_None, // DADD16rr
2906 CEFBS_None, // DADD8mc
2907 CEFBS_None, // DADD8mi
2908 CEFBS_None, // DADD8mm
2909 CEFBS_None, // DADD8mn
2910 CEFBS_None, // DADD8mp
2911 CEFBS_None, // DADD8mr
2912 CEFBS_None, // DADD8rc
2913 CEFBS_None, // DADD8ri
2914 CEFBS_None, // DADD8rm
2915 CEFBS_None, // DADD8rn
2916 CEFBS_None, // DADD8rp
2917 CEFBS_None, // DADD8rr
2918 CEFBS_None, // JCC
2919 CEFBS_None, // JMP
2920 CEFBS_None, // MOV16mc
2921 CEFBS_None, // MOV16mi
2922 CEFBS_None, // MOV16mm
2923 CEFBS_None, // MOV16mn
2924 CEFBS_None, // MOV16mr
2925 CEFBS_None, // MOV16rc
2926 CEFBS_None, // MOV16ri
2927 CEFBS_None, // MOV16rm
2928 CEFBS_None, // MOV16rn
2929 CEFBS_None, // MOV16rp
2930 CEFBS_None, // MOV16rr
2931 CEFBS_None, // MOV8mc
2932 CEFBS_None, // MOV8mi
2933 CEFBS_None, // MOV8mm
2934 CEFBS_None, // MOV8mn
2935 CEFBS_None, // MOV8mr
2936 CEFBS_None, // MOV8rc
2937 CEFBS_None, // MOV8ri
2938 CEFBS_None, // MOV8rm
2939 CEFBS_None, // MOV8rn
2940 CEFBS_None, // MOV8rp
2941 CEFBS_None, // MOV8rr
2942 CEFBS_None, // MOVZX16rm8
2943 CEFBS_None, // MOVZX16rr8
2944 CEFBS_None, // POP16r
2945 CEFBS_None, // PUSH16c
2946 CEFBS_None, // PUSH16i
2947 CEFBS_None, // PUSH16r
2948 CEFBS_None, // PUSH8r
2949 CEFBS_None, // RET
2950 CEFBS_None, // RETI
2951 CEFBS_None, // RRA16m
2952 CEFBS_None, // RRA16n
2953 CEFBS_None, // RRA16p
2954 CEFBS_None, // RRA16r
2955 CEFBS_None, // RRA8m
2956 CEFBS_None, // RRA8n
2957 CEFBS_None, // RRA8p
2958 CEFBS_None, // RRA8r
2959 CEFBS_None, // RRC16m
2960 CEFBS_None, // RRC16n
2961 CEFBS_None, // RRC16p
2962 CEFBS_None, // RRC16r
2963 CEFBS_None, // RRC8m
2964 CEFBS_None, // RRC8n
2965 CEFBS_None, // RRC8p
2966 CEFBS_None, // RRC8r
2967 CEFBS_None, // Rrcl16
2968 CEFBS_None, // Rrcl8
2969 CEFBS_None, // SEXT16m
2970 CEFBS_None, // SEXT16n
2971 CEFBS_None, // SEXT16p
2972 CEFBS_None, // SEXT16r
2973 CEFBS_None, // SUB16mc
2974 CEFBS_None, // SUB16mi
2975 CEFBS_None, // SUB16mm
2976 CEFBS_None, // SUB16mn
2977 CEFBS_None, // SUB16mp
2978 CEFBS_None, // SUB16mr
2979 CEFBS_None, // SUB16rc
2980 CEFBS_None, // SUB16ri
2981 CEFBS_None, // SUB16rm
2982 CEFBS_None, // SUB16rn
2983 CEFBS_None, // SUB16rp
2984 CEFBS_None, // SUB16rr
2985 CEFBS_None, // SUB8mc
2986 CEFBS_None, // SUB8mi
2987 CEFBS_None, // SUB8mm
2988 CEFBS_None, // SUB8mn
2989 CEFBS_None, // SUB8mp
2990 CEFBS_None, // SUB8mr
2991 CEFBS_None, // SUB8rc
2992 CEFBS_None, // SUB8ri
2993 CEFBS_None, // SUB8rm
2994 CEFBS_None, // SUB8rn
2995 CEFBS_None, // SUB8rp
2996 CEFBS_None, // SUB8rr
2997 CEFBS_None, // SUBC16mc
2998 CEFBS_None, // SUBC16mi
2999 CEFBS_None, // SUBC16mm
3000 CEFBS_None, // SUBC16mn
3001 CEFBS_None, // SUBC16mp
3002 CEFBS_None, // SUBC16mr
3003 CEFBS_None, // SUBC16rc
3004 CEFBS_None, // SUBC16ri
3005 CEFBS_None, // SUBC16rm
3006 CEFBS_None, // SUBC16rn
3007 CEFBS_None, // SUBC16rp
3008 CEFBS_None, // SUBC16rr
3009 CEFBS_None, // SUBC8mc
3010 CEFBS_None, // SUBC8mi
3011 CEFBS_None, // SUBC8mm
3012 CEFBS_None, // SUBC8mn
3013 CEFBS_None, // SUBC8mp
3014 CEFBS_None, // SUBC8mr
3015 CEFBS_None, // SUBC8rc
3016 CEFBS_None, // SUBC8ri
3017 CEFBS_None, // SUBC8rm
3018 CEFBS_None, // SUBC8rn
3019 CEFBS_None, // SUBC8rp
3020 CEFBS_None, // SUBC8rr
3021 CEFBS_None, // SWPB16m
3022 CEFBS_None, // SWPB16n
3023 CEFBS_None, // SWPB16p
3024 CEFBS_None, // SWPB16r
3025 CEFBS_None, // Select16
3026 CEFBS_None, // Select8
3027 CEFBS_None, // Shl16
3028 CEFBS_None, // Shl8
3029 CEFBS_None, // Sra16
3030 CEFBS_None, // Sra8
3031 CEFBS_None, // Srl16
3032 CEFBS_None, // Srl8
3033 CEFBS_None, // XOR16mc
3034 CEFBS_None, // XOR16mi
3035 CEFBS_None, // XOR16mm
3036 CEFBS_None, // XOR16mn
3037 CEFBS_None, // XOR16mp
3038 CEFBS_None, // XOR16mr
3039 CEFBS_None, // XOR16rc
3040 CEFBS_None, // XOR16ri
3041 CEFBS_None, // XOR16rm
3042 CEFBS_None, // XOR16rn
3043 CEFBS_None, // XOR16rp
3044 CEFBS_None, // XOR16rr
3045 CEFBS_None, // XOR8mc
3046 CEFBS_None, // XOR8mi
3047 CEFBS_None, // XOR8mm
3048 CEFBS_None, // XOR8mn
3049 CEFBS_None, // XOR8mp
3050 CEFBS_None, // XOR8mr
3051 CEFBS_None, // XOR8rc
3052 CEFBS_None, // XOR8ri
3053 CEFBS_None, // XOR8rm
3054 CEFBS_None, // XOR8rn
3055 CEFBS_None, // XOR8rp
3056 CEFBS_None, // XOR8rr
3057 CEFBS_None, // ZEXT16r
3058 };
3059
3060 assert(Opcode < 678);
3061 return FeatureBitsets[RequiredFeaturesRefs[Opcode]];
3062}
3063
3064
3065} // namespace llvm::MSP430_MC
3066
3067#endif // GET_COMPUTE_FEATURES
3068
3069#ifdef GET_AVAILABLE_OPCODE_CHECKER
3070#undef GET_AVAILABLE_OPCODE_CHECKER
3071
3072namespace llvm::MSP430_MC {
3073
3074bool isOpcodeAvailable(unsigned Opcode, const FeatureBitset &Features) {
3075 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
3076 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
3077 FeatureBitset MissingFeatures =
3078 (AvailableFeatures & RequiredFeatures) ^
3079 RequiredFeatures;
3080 return !MissingFeatures.any();
3081}
3082
3083} // namespace llvm::MSP430_MC
3084
3085#endif // GET_AVAILABLE_OPCODE_CHECKER
3086
3087#ifdef ENABLE_INSTR_PREDICATE_VERIFIER
3088#undef ENABLE_INSTR_PREDICATE_VERIFIER
3089
3090#include <sstream>
3091
3092namespace llvm::MSP430_MC {
3093
3094#ifndef NDEBUG
3095static const char *SubtargetFeatureNames[] = {
3096 nullptr
3097};
3098
3099#endif // NDEBUG
3100
3101void verifyInstructionPredicates(
3102 unsigned Opcode, const FeatureBitset &Features) {
3103#ifndef NDEBUG
3104 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
3105 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
3106 FeatureBitset MissingFeatures =
3107 (AvailableFeatures & RequiredFeatures) ^
3108 RequiredFeatures;
3109 if (MissingFeatures.any()) {
3110 std::ostringstream Msg;
3111 Msg << "Attempting to emit " << &MSP430InstrNameData[MSP430InstrNameIndices[Opcode]]
3112 << " instruction but the ";
3113 for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i)
3114 if (MissingFeatures.test(i))
3115 Msg << SubtargetFeatureNames[i] << " ";
3116 Msg << "predicate(s) are not met";
3117 report_fatal_error(Msg.str().c_str());
3118 }
3119#endif // NDEBUG
3120}
3121
3122} // namespace llvm::MSP430_MC
3123
3124#endif // ENABLE_INSTR_PREDICATE_VERIFIER
3125
3126