1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Instruction Enum Values and Descriptors *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_INSTRINFO_ENUM
10#undef GET_INSTRINFO_ENUM
11
12namespace llvm::MSP430 {
13
14 enum {
15 PHI = 0, // Target.td:1329
16 INLINEASM = 1, // Target.td:1335
17 INLINEASM_BR = 2, // Target.td:1341
18 CFI_INSTRUCTION = 3, // Target.td:1350
19 EH_LABEL = 4, // Target.td:1359
20 GC_LABEL = 5, // Target.td:1368
21 ANNOTATION_LABEL = 6, // Target.td:1377
22 KILL = 7, // Target.td:1385
23 EXTRACT_SUBREG = 8, // Target.td:1392
24 INSERT_SUBREG = 9, // Target.td:1398
25 IMPLICIT_DEF = 10, // Target.td:1405
26 INIT_UNDEF = 11, // Target.td:1414
27 SUBREG_TO_REG = 12, // Target.td:1421
28 COPY_TO_REGCLASS = 13, // Target.td:1427
29 DBG_VALUE = 14, // Target.td:1434
30 DBG_VALUE_LIST = 15, // Target.td:1441
31 DBG_INSTR_REF = 16, // Target.td:1448
32 DBG_PHI = 17, // Target.td:1455
33 DBG_LABEL = 18, // Target.td:1462
34 REG_SEQUENCE = 19, // Target.td:1469
35 COPY = 20, // Target.td:1476
36 COPY_LANEMASK = 21, // Target.td:1484
37 BUNDLE = 22, // Target.td:1491
38 LIFETIME_START = 23, // Target.td:1497
39 LIFETIME_END = 24, // Target.td:1504
40 PSEUDO_PROBE = 25, // Target.td:1511
41 ARITH_FENCE = 26, // Target.td:1518
42 STACKMAP = 27, // Target.td:1527
43 FENTRY_CALL = 28, // Target.td:1662
44 PATCHPOINT = 29, // Target.td:1535
45 LOAD_STACK_GUARD = 30, // Target.td:1553
46 PREALLOCATED_SETUP = 31, // Target.td:1561
47 PREALLOCATED_ARG = 32, // Target.td:1567
48 STATEPOINT = 33, // Target.td:1544
49 LOCAL_ESCAPE = 34, // Target.td:1573
50 FAULTING_OP = 35, // Target.td:1582
51 PATCHABLE_OP = 36, // Target.td:1602
52 PATCHABLE_FUNCTION_ENTER = 37, // Target.td:1610
53 PATCHABLE_RET = 38, // Target.td:1617
54 PATCHABLE_FUNCTION_EXIT = 39, // Target.td:1626
55 PATCHABLE_TAIL_CALL = 40, // Target.td:1634
56 PATCHABLE_EVENT_CALL = 41, // Target.td:1642
57 PATCHABLE_TYPED_EVENT_CALL = 42, // Target.td:1652
58 ICALL_BRANCH_FUNNEL = 43, // Target.td:1672
59 FAKE_USE = 44, // Target.td:1592
60 MEMBARRIER = 45, // Target.td:1678
61 JUMP_TABLE_DEBUG_INFO = 46, // Target.td:1686
62 RELOC_NONE = 47, // Target.td:1694
63 CONVERGENCECTRL_ENTRY = 48, // Target.td:1706
64 CONVERGENCECTRL_ANCHOR = 49, // Target.td:1702
65 CONVERGENCECTRL_LOOP = 50, // Target.td:1710
66 CONVERGENCECTRL_GLUE = 51, // Target.td:1714
67 G_ASSERT_SEXT = 52, // GenericOpcodes.td:1937
68 G_ASSERT_ZEXT = 53, // GenericOpcodes.td:1929
69 G_ASSERT_ALIGN = 54, // GenericOpcodes.td:1944
70 G_ADD = 55, // GenericOpcodes.td:308
71 G_SUB = 56, // GenericOpcodes.td:316
72 G_MUL = 57, // GenericOpcodes.td:324
73 G_SDIV = 58, // GenericOpcodes.td:332
74 G_UDIV = 59, // GenericOpcodes.td:340
75 G_SREM = 60, // GenericOpcodes.td:348
76 G_UREM = 61, // GenericOpcodes.td:356
77 G_SDIVREM = 62, // GenericOpcodes.td:364
78 G_UDIVREM = 63, // GenericOpcodes.td:372
79 G_AND = 64, // GenericOpcodes.td:380
80 G_OR = 65, // GenericOpcodes.td:388
81 G_XOR = 66, // GenericOpcodes.td:396
82 G_ABDS = 67, // GenericOpcodes.td:425
83 G_ABDU = 68, // GenericOpcodes.td:433
84 G_UAVGFLOOR = 69, // GenericOpcodes.td:441
85 G_UAVGCEIL = 70, // GenericOpcodes.td:448
86 G_SAVGFLOOR = 71, // GenericOpcodes.td:455
87 G_SAVGCEIL = 72, // GenericOpcodes.td:462
88 G_IMPLICIT_DEF = 73, // GenericOpcodes.td:111
89 G_PHI = 74, // GenericOpcodes.td:118
90 G_FRAME_INDEX = 75, // GenericOpcodes.td:125
91 G_GLOBAL_VALUE = 76, // GenericOpcodes.td:131
92 G_PTRAUTH_GLOBAL_VALUE = 77, // GenericOpcodes.td:137
93 G_CONSTANT_POOL = 78, // GenericOpcodes.td:143
94 G_EXTRACT = 79, // GenericOpcodes.td:1522
95 G_UNMERGE_VALUES = 80, // GenericOpcodes.td:1535
96 G_INSERT = 81, // GenericOpcodes.td:1544
97 G_MERGE_VALUES = 82, // GenericOpcodes.td:1554
98 G_BUILD_VECTOR = 83, // GenericOpcodes.td:1574
99 G_BUILD_VECTOR_TRUNC = 84, // GenericOpcodes.td:1584
100 G_CONCAT_VECTORS = 85, // GenericOpcodes.td:1591
101 G_PTRTOINT = 86, // GenericOpcodes.td:155
102 G_INTTOPTR = 87, // GenericOpcodes.td:149
103 G_BITCAST = 88, // GenericOpcodes.td:161
104 G_FREEZE = 89, // GenericOpcodes.td:284
105 G_CONSTANT_FOLD_BARRIER = 90, // GenericOpcodes.td:1951
106 G_INTRINSIC_FPTRUNC_ROUND = 91, // GenericOpcodes.td:1280
107 G_INTRINSIC_TRUNC = 92, // GenericOpcodes.td:1286
108 G_INTRINSIC_ROUND = 93, // GenericOpcodes.td:1292
109 G_INTRINSIC_LRINT = 94, // GenericOpcodes.td:1298
110 G_INTRINSIC_LLRINT = 95, // GenericOpcodes.td:1304
111 G_INTRINSIC_ROUNDEVEN = 96, // GenericOpcodes.td:1310
112 G_READCYCLECOUNTER = 97, // GenericOpcodes.td:1316
113 G_READSTEADYCOUNTER = 98, // GenericOpcodes.td:1322
114 G_LOAD = 99, // GenericOpcodes.td:1349
115 G_SEXTLOAD = 100, // GenericOpcodes.td:1358
116 G_ZEXTLOAD = 101, // GenericOpcodes.td:1366
117 G_FPEXTLOAD = 102, // GenericOpcodes.td:1375
118 G_INDEXED_LOAD = 103, // GenericOpcodes.td:1385
119 G_INDEXED_SEXTLOAD = 104, // GenericOpcodes.td:1394
120 G_INDEXED_ZEXTLOAD = 105, // GenericOpcodes.td:1402
121 G_STORE = 106, // GenericOpcodes.td:1410
122 G_FPTRUNCSTORE = 107, // GenericOpcodes.td:1420
123 G_INDEXED_STORE = 108, // GenericOpcodes.td:1428
124 G_ATOMIC_CMPXCHG_WITH_SUCCESS = 109, // GenericOpcodes.td:1439
125 G_ATOMIC_CMPXCHG = 110, // GenericOpcodes.td:1450
126 G_ATOMICRMW_XCHG = 111, // GenericOpcodes.td:1470
127 G_ATOMICRMW_ADD = 112, // GenericOpcodes.td:1471
128 G_ATOMICRMW_SUB = 113, // GenericOpcodes.td:1472
129 G_ATOMICRMW_AND = 114, // GenericOpcodes.td:1473
130 G_ATOMICRMW_NAND = 115, // GenericOpcodes.td:1474
131 G_ATOMICRMW_OR = 116, // GenericOpcodes.td:1475
132 G_ATOMICRMW_XOR = 117, // GenericOpcodes.td:1476
133 G_ATOMICRMW_MAX = 118, // GenericOpcodes.td:1477
134 G_ATOMICRMW_MIN = 119, // GenericOpcodes.td:1478
135 G_ATOMICRMW_UMAX = 120, // GenericOpcodes.td:1479
136 G_ATOMICRMW_UMIN = 121, // GenericOpcodes.td:1480
137 G_ATOMICRMW_FADD = 122, // GenericOpcodes.td:1491
138 G_ATOMICRMW_FSUB = 123, // GenericOpcodes.td:1492
139 G_ATOMICRMW_FMAX = 124, // GenericOpcodes.td:1493
140 G_ATOMICRMW_FMIN = 125, // GenericOpcodes.td:1494
141 G_ATOMICRMW_FMAXIMUM = 126, // GenericOpcodes.td:1495
142 G_ATOMICRMW_FMINIMUM = 127, // GenericOpcodes.td:1496
143 G_ATOMICRMW_FMAXIMUMNUM = 128, // GenericOpcodes.td:1497
144 G_ATOMICRMW_FMINIMUMNUM = 129, // GenericOpcodes.td:1498
145 G_ATOMICRMW_UINC_WRAP = 130, // GenericOpcodes.td:1481
146 G_ATOMICRMW_UDEC_WRAP = 131, // GenericOpcodes.td:1482
147 G_ATOMICRMW_USUB_COND = 132, // GenericOpcodes.td:1483
148 G_ATOMICRMW_USUB_SAT = 133, // GenericOpcodes.td:1484
149 G_FENCE = 134, // GenericOpcodes.td:1500
150 G_PREFETCH = 135, // GenericOpcodes.td:1507
151 G_BRCOND = 136, // GenericOpcodes.td:1647
152 G_BRINDIRECT = 137, // GenericOpcodes.td:1656
153 G_INVOKE_REGION_START = 138, // GenericOpcodes.td:1679
154 G_INTRINSIC = 139, // GenericOpcodes.td:1599
155 G_INTRINSIC_W_SIDE_EFFECTS = 140, // GenericOpcodes.td:1606
156 G_INTRINSIC_CONVERGENT = 141, // GenericOpcodes.td:1615
157 G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 142, // GenericOpcodes.td:1623
158 G_ANYEXT = 143, // GenericOpcodes.td:44
159 G_TRUNC = 144, // GenericOpcodes.td:83
160 G_TRUNC_SSAT_S = 145, // GenericOpcodes.td:91
161 G_TRUNC_SSAT_U = 146, // GenericOpcodes.td:98
162 G_TRUNC_USAT_U = 147, // GenericOpcodes.td:105
163 G_CONSTANT = 148, // GenericOpcodes.td:169
164 G_FCONSTANT = 149, // GenericOpcodes.td:177
165 G_VASTART = 150, // GenericOpcodes.td:184
166 G_VAARG = 151, // GenericOpcodes.td:191
167 G_SEXT = 152, // GenericOpcodes.td:52
168 G_SEXT_INREG = 153, // GenericOpcodes.td:66
169 G_ZEXT = 154, // GenericOpcodes.td:74
170 G_SHL = 155, // GenericOpcodes.td:404
171 G_LSHR = 156, // GenericOpcodes.td:411
172 G_ASHR = 157, // GenericOpcodes.td:418
173 G_FSHL = 158, // GenericOpcodes.td:470
174 G_FSHR = 159, // GenericOpcodes.td:478
175 G_ROTR = 160, // GenericOpcodes.td:485
176 G_ROTL = 161, // GenericOpcodes.td:492
177 G_ICMP = 162, // GenericOpcodes.td:499
178 G_FCMP = 163, // GenericOpcodes.td:506
179 G_SCMP = 164, // GenericOpcodes.td:513
180 G_UCMP = 165, // GenericOpcodes.td:520
181 G_SELECT = 166, // GenericOpcodes.td:527
182 G_UADDO = 167, // GenericOpcodes.td:601
183 G_UADDE = 168, // GenericOpcodes.td:609
184 G_USUBO = 169, // GenericOpcodes.td:631
185 G_USUBE = 170, // GenericOpcodes.td:637
186 G_SADDO = 171, // GenericOpcodes.td:616
187 G_SADDE = 172, // GenericOpcodes.td:624
188 G_SSUBO = 173, // GenericOpcodes.td:644
189 G_SSUBE = 174, // GenericOpcodes.td:651
190 G_UMULO = 175, // GenericOpcodes.td:658
191 G_SMULO = 176, // GenericOpcodes.td:666
192 G_UMULH = 177, // GenericOpcodes.td:675
193 G_SMULH = 178, // GenericOpcodes.td:684
194 G_UADDSAT = 179, // GenericOpcodes.td:696
195 G_SADDSAT = 180, // GenericOpcodes.td:704
196 G_USUBSAT = 181, // GenericOpcodes.td:712
197 G_SSUBSAT = 182, // GenericOpcodes.td:720
198 G_USHLSAT = 183, // GenericOpcodes.td:728
199 G_SSHLSAT = 184, // GenericOpcodes.td:736
200 G_SMULFIX = 185, // GenericOpcodes.td:748
201 G_UMULFIX = 186, // GenericOpcodes.td:755
202 G_SMULFIXSAT = 187, // GenericOpcodes.td:765
203 G_UMULFIXSAT = 188, // GenericOpcodes.td:772
204 G_SDIVFIX = 189, // GenericOpcodes.td:783
205 G_UDIVFIX = 190, // GenericOpcodes.td:790
206 G_SDIVFIXSAT = 191, // GenericOpcodes.td:800
207 G_UDIVFIXSAT = 192, // GenericOpcodes.td:807
208 G_FADD = 193, // GenericOpcodes.td:980
209 G_FSUB = 194, // GenericOpcodes.td:988
210 G_FMUL = 195, // GenericOpcodes.td:996
211 G_FMA = 196, // GenericOpcodes.td:1005
212 G_FMAD = 197, // GenericOpcodes.td:1014
213 G_FDIV = 198, // GenericOpcodes.td:1022
214 G_FREM = 199, // GenericOpcodes.td:1029
215 G_FMODF = 200, // GenericOpcodes.td:1036
216 G_FPOW = 201, // GenericOpcodes.td:1043
217 G_FPOWI = 202, // GenericOpcodes.td:1050
218 G_FEXP = 203, // GenericOpcodes.td:1057
219 G_FEXP2 = 204, // GenericOpcodes.td:1064
220 G_FEXP10 = 205, // GenericOpcodes.td:1071
221 G_FLOG = 206, // GenericOpcodes.td:1078
222 G_FLOG2 = 207, // GenericOpcodes.td:1085
223 G_FLOG10 = 208, // GenericOpcodes.td:1092
224 G_FLDEXP = 209, // GenericOpcodes.td:1099
225 G_FFREXP = 210, // GenericOpcodes.td:1106
226 G_FNEG = 211, // GenericOpcodes.td:818
227 G_FPEXT = 212, // GenericOpcodes.td:824
228 G_FPTRUNC = 213, // GenericOpcodes.td:830
229 G_FPTOSI = 214, // GenericOpcodes.td:836
230 G_FPTOUI = 215, // GenericOpcodes.td:842
231 G_SITOFP = 216, // GenericOpcodes.td:848
232 G_UITOFP = 217, // GenericOpcodes.td:854
233 G_FPTOSI_SAT = 218, // GenericOpcodes.td:860
234 G_FPTOUI_SAT = 219, // GenericOpcodes.td:866
235 G_FABS = 220, // GenericOpcodes.td:872
236 G_FCOPYSIGN = 221, // GenericOpcodes.td:878
237 G_IS_FPCLASS = 222, // GenericOpcodes.td:891
238 G_FCANONICALIZE = 223, // GenericOpcodes.td:884
239 G_FMINNUM = 224, // GenericOpcodes.td:904
240 G_FMAXNUM = 225, // GenericOpcodes.td:911
241 G_FMINNUM_IEEE = 226, // GenericOpcodes.td:929
242 G_FMAXNUM_IEEE = 227, // GenericOpcodes.td:936
243 G_FMINIMUM = 228, // GenericOpcodes.td:946
244 G_FMAXIMUM = 229, // GenericOpcodes.td:953
245 G_FMINIMUMNUM = 230, // GenericOpcodes.td:961
246 G_FMAXIMUMNUM = 231, // GenericOpcodes.td:968
247 G_GET_FPENV = 232, // GenericOpcodes.td:1236
248 G_SET_FPENV = 233, // GenericOpcodes.td:1243
249 G_RESET_FPENV = 234, // GenericOpcodes.td:1250
250 G_GET_FPMODE = 235, // GenericOpcodes.td:1257
251 G_SET_FPMODE = 236, // GenericOpcodes.td:1264
252 G_RESET_FPMODE = 237, // GenericOpcodes.td:1271
253 G_GET_ROUNDING = 238, // GenericOpcodes.td:1328
254 G_SET_ROUNDING = 239, // GenericOpcodes.td:1334
255 G_PTR_ADD = 240, // GenericOpcodes.td:534
256 G_PTRMASK = 241, // GenericOpcodes.td:542
257 G_SMIN = 242, // GenericOpcodes.td:549
258 G_SMAX = 243, // GenericOpcodes.td:557
259 G_UMIN = 244, // GenericOpcodes.td:565
260 G_UMAX = 245, // GenericOpcodes.td:573
261 G_ABS = 246, // GenericOpcodes.td:581
262 G_LROUND = 247, // GenericOpcodes.td:291
263 G_LLROUND = 248, // GenericOpcodes.td:297
264 G_BR = 249, // GenericOpcodes.td:1637
265 G_BRJT = 250, // GenericOpcodes.td:1667
266 G_VSCALE = 251, // GenericOpcodes.td:1565
267 G_INSERT_SUBVECTOR = 252, // GenericOpcodes.td:1711
268 G_EXTRACT_SUBVECTOR = 253, // GenericOpcodes.td:1719
269 G_INSERT_VECTOR_ELT = 254, // GenericOpcodes.td:1727
270 G_EXTRACT_VECTOR_ELT = 255, // GenericOpcodes.td:1735
271 G_SHUFFLE_VECTOR = 256, // GenericOpcodes.td:1746
272 G_SPLAT_VECTOR = 257, // GenericOpcodes.td:1754
273 G_STEP_VECTOR = 258, // GenericOpcodes.td:1762
274 G_VECTOR_COMPRESS = 259, // GenericOpcodes.td:1769
275 G_CTTZ = 260, // GenericOpcodes.td:211
276 G_CTTZ_ZERO_POISON = 261, // GenericOpcodes.td:217
277 G_CTLZ = 262, // GenericOpcodes.td:199
278 G_CTLZ_ZERO_POISON = 263, // GenericOpcodes.td:205
279 G_CTLS = 264, // GenericOpcodes.td:223
280 G_CTPOP = 265, // GenericOpcodes.td:229
281 G_BSWAP = 266, // GenericOpcodes.td:235
282 G_BITREVERSE = 267, // GenericOpcodes.td:242
283 G_CLMUL = 268, // GenericOpcodes.td:588
284 G_FCEIL = 269, // GenericOpcodes.td:1113
285 G_FCOS = 270, // GenericOpcodes.td:1120
286 G_FSIN = 271, // GenericOpcodes.td:1127
287 G_FSINCOS = 272, // GenericOpcodes.td:1134
288 G_FTAN = 273, // GenericOpcodes.td:1141
289 G_FACOS = 274, // GenericOpcodes.td:1148
290 G_FASIN = 275, // GenericOpcodes.td:1155
291 G_FATAN = 276, // GenericOpcodes.td:1162
292 G_FATAN2 = 277, // GenericOpcodes.td:1169
293 G_FCOSH = 278, // GenericOpcodes.td:1176
294 G_FSINH = 279, // GenericOpcodes.td:1183
295 G_FTANH = 280, // GenericOpcodes.td:1190
296 G_FSQRT = 281, // GenericOpcodes.td:1200
297 G_FFLOOR = 282, // GenericOpcodes.td:1207
298 G_FRINT = 283, // GenericOpcodes.td:1214
299 G_FNEARBYINT = 284, // GenericOpcodes.td:1221
300 G_ADDRSPACE_CAST = 285, // GenericOpcodes.td:248
301 G_BLOCK_ADDR = 286, // GenericOpcodes.td:254
302 G_JUMP_TABLE = 287, // GenericOpcodes.td:260
303 G_DYN_STACKALLOC = 288, // GenericOpcodes.td:266
304 G_STACKSAVE = 289, // GenericOpcodes.td:272
305 G_STACKRESTORE = 290, // GenericOpcodes.td:278
306 G_STRICT_FADD = 291, // GenericOpcodes.td:1821
307 G_STRICT_FSUB = 292, // GenericOpcodes.td:1822
308 G_STRICT_FMUL = 293, // GenericOpcodes.td:1823
309 G_STRICT_FDIV = 294, // GenericOpcodes.td:1824
310 G_STRICT_FREM = 295, // GenericOpcodes.td:1825
311 G_STRICT_FMA = 296, // GenericOpcodes.td:1826
312 G_STRICT_FSQRT = 297, // GenericOpcodes.td:1827
313 G_STRICT_FLDEXP = 298, // GenericOpcodes.td:1828
314 G_STRICT_FCMP = 299, // GenericOpcodes.td:1829
315 G_STRICT_FCMPS = 300, // GenericOpcodes.td:1830
316 G_READ_REGISTER = 301, // GenericOpcodes.td:1686
317 G_WRITE_REGISTER = 302, // GenericOpcodes.td:1696
318 G_MEMCPY = 303, // GenericOpcodes.td:1836
319 G_MEMCPY_INLINE = 304, // GenericOpcodes.td:1844
320 G_MEMMOVE = 305, // GenericOpcodes.td:1852
321 G_MEMSET = 306, // GenericOpcodes.td:1860
322 G_BZERO = 307, // GenericOpcodes.td:1867
323 G_MEMSET_INLINE = 308, // GenericOpcodes.td:1874
324 G_TRAP = 309, // GenericOpcodes.td:1884
325 G_DEBUGTRAP = 310, // GenericOpcodes.td:1891
326 G_UBSANTRAP = 311, // GenericOpcodes.td:1897
327 G_VECREDUCE_SEQ_FADD = 312, // GenericOpcodes.td:1785
328 G_VECREDUCE_SEQ_FMUL = 313, // GenericOpcodes.td:1791
329 G_VECREDUCE_FADD = 314, // GenericOpcodes.td:1797
330 G_VECREDUCE_FMUL = 315, // GenericOpcodes.td:1798
331 G_VECREDUCE_FMAX = 316, // GenericOpcodes.td:1800
332 G_VECREDUCE_FMIN = 317, // GenericOpcodes.td:1801
333 G_VECREDUCE_FMAXIMUM = 318, // GenericOpcodes.td:1802
334 G_VECREDUCE_FMINIMUM = 319, // GenericOpcodes.td:1803
335 G_VECREDUCE_FMAXIMUMNUM = 320, // GenericOpcodes.td:1804
336 G_VECREDUCE_FMINIMUMNUM = 321, // GenericOpcodes.td:1805
337 G_VECREDUCE_ADD = 322, // GenericOpcodes.td:1807
338 G_VECREDUCE_MUL = 323, // GenericOpcodes.td:1808
339 G_VECREDUCE_AND = 324, // GenericOpcodes.td:1809
340 G_VECREDUCE_OR = 325, // GenericOpcodes.td:1810
341 G_VECREDUCE_XOR = 326, // GenericOpcodes.td:1811
342 G_VECREDUCE_SMAX = 327, // GenericOpcodes.td:1812
343 G_VECREDUCE_SMIN = 328, // GenericOpcodes.td:1813
344 G_VECREDUCE_UMAX = 329, // GenericOpcodes.td:1814
345 G_VECREDUCE_UMIN = 330, // GenericOpcodes.td:1815
346 G_SBFX = 331, // GenericOpcodes.td:1909
347 G_UBFX = 332, // GenericOpcodes.td:1917
348 ADD16mc = 333, // MSP430InstrInfo.td:499
349 ADD16mi = 334, // MSP430InstrInfo.td:505
350 ADD16mm = 335, // MSP430InstrInfo.td:512
351 ADD16mn = 336, // MSP430InstrInfo.td:518
352 ADD16mp = 337, // MSP430InstrInfo.td:522
353 ADD16mr = 338, // MSP430InstrInfo.td:493
354 ADD16rc = 339, // MSP430InstrInfo.td:480
355 ADD16ri = 340, // MSP430InstrInfo.td:486
356 ADD16rm = 341, // MSP430InstrInfo.td:462
357 ADD16rn = 342, // MSP430InstrInfo.td:467
358 ADD16rp = 343, // MSP430InstrInfo.td:474
359 ADD16rr = 344, // MSP430InstrInfo.td:455
360 ADD8mc = 345, // MSP430InstrInfo.td:496
361 ADD8mi = 346, // MSP430InstrInfo.td:502
362 ADD8mm = 347, // MSP430InstrInfo.td:508
363 ADD8mn = 348, // MSP430InstrInfo.td:516
364 ADD8mp = 349, // MSP430InstrInfo.td:520
365 ADD8mr = 350, // MSP430InstrInfo.td:490
366 ADD8rc = 351, // MSP430InstrInfo.td:477
367 ADD8ri = 352, // MSP430InstrInfo.td:483
368 ADD8rm = 353, // MSP430InstrInfo.td:459
369 ADD8rn = 354, // MSP430InstrInfo.td:465
370 ADD8rp = 355, // MSP430InstrInfo.td:472
371 ADD8rr = 356, // MSP430InstrInfo.td:452
372 ADDC16mc = 357, // MSP430InstrInfo.td:499
373 ADDC16mi = 358, // MSP430InstrInfo.td:505
374 ADDC16mm = 359, // MSP430InstrInfo.td:512
375 ADDC16mn = 360, // MSP430InstrInfo.td:518
376 ADDC16mp = 361, // MSP430InstrInfo.td:522
377 ADDC16mr = 362, // MSP430InstrInfo.td:493
378 ADDC16rc = 363, // MSP430InstrInfo.td:480
379 ADDC16ri = 364, // MSP430InstrInfo.td:486
380 ADDC16rm = 365, // MSP430InstrInfo.td:462
381 ADDC16rn = 366, // MSP430InstrInfo.td:467
382 ADDC16rp = 367, // MSP430InstrInfo.td:474
383 ADDC16rr = 368, // MSP430InstrInfo.td:455
384 ADDC8mc = 369, // MSP430InstrInfo.td:496
385 ADDC8mi = 370, // MSP430InstrInfo.td:502
386 ADDC8mm = 371, // MSP430InstrInfo.td:508
387 ADDC8mn = 372, // MSP430InstrInfo.td:516
388 ADDC8mp = 373, // MSP430InstrInfo.td:520
389 ADDC8mr = 374, // MSP430InstrInfo.td:490
390 ADDC8rc = 375, // MSP430InstrInfo.td:477
391 ADDC8ri = 376, // MSP430InstrInfo.td:483
392 ADDC8rm = 377, // MSP430InstrInfo.td:459
393 ADDC8rn = 378, // MSP430InstrInfo.td:465
394 ADDC8rp = 379, // MSP430InstrInfo.td:472
395 ADDC8rr = 380, // MSP430InstrInfo.td:452
396 ADDframe = 381, // MSP430InstrInfo.td:183
397 ADJCALLSTACKDOWN = 382, // MSP430InstrInfo.td:174
398 ADJCALLSTACKUP = 383, // MSP430InstrInfo.td:177
399 AND16mc = 384, // MSP430InstrInfo.td:499
400 AND16mi = 385, // MSP430InstrInfo.td:505
401 AND16mm = 386, // MSP430InstrInfo.td:512
402 AND16mn = 387, // MSP430InstrInfo.td:518
403 AND16mp = 388, // MSP430InstrInfo.td:522
404 AND16mr = 389, // MSP430InstrInfo.td:493
405 AND16rc = 390, // MSP430InstrInfo.td:480
406 AND16ri = 391, // MSP430InstrInfo.td:486
407 AND16rm = 392, // MSP430InstrInfo.td:462
408 AND16rn = 393, // MSP430InstrInfo.td:467
409 AND16rp = 394, // MSP430InstrInfo.td:474
410 AND16rr = 395, // MSP430InstrInfo.td:455
411 AND8mc = 396, // MSP430InstrInfo.td:496
412 AND8mi = 397, // MSP430InstrInfo.td:502
413 AND8mm = 398, // MSP430InstrInfo.td:508
414 AND8mn = 399, // MSP430InstrInfo.td:516
415 AND8mp = 400, // MSP430InstrInfo.td:520
416 AND8mr = 401, // MSP430InstrInfo.td:490
417 AND8rc = 402, // MSP430InstrInfo.td:477
418 AND8ri = 403, // MSP430InstrInfo.td:483
419 AND8rm = 404, // MSP430InstrInfo.td:459
420 AND8rn = 405, // MSP430InstrInfo.td:465
421 AND8rp = 406, // MSP430InstrInfo.td:472
422 AND8rr = 407, // MSP430InstrInfo.td:452
423 BIC16mc = 408, // MSP430InstrInfo.td:499
424 BIC16mi = 409, // MSP430InstrInfo.td:505
425 BIC16mm = 410, // MSP430InstrInfo.td:512
426 BIC16mn = 411, // MSP430InstrInfo.td:518
427 BIC16mp = 412, // MSP430InstrInfo.td:522
428 BIC16mr = 413, // MSP430InstrInfo.td:493
429 BIC16rc = 414, // MSP430InstrInfo.td:480
430 BIC16ri = 415, // MSP430InstrInfo.td:486
431 BIC16rm = 416, // MSP430InstrInfo.td:462
432 BIC16rn = 417, // MSP430InstrInfo.td:467
433 BIC16rp = 418, // MSP430InstrInfo.td:474
434 BIC16rr = 419, // MSP430InstrInfo.td:455
435 BIC8mc = 420, // MSP430InstrInfo.td:496
436 BIC8mi = 421, // MSP430InstrInfo.td:502
437 BIC8mm = 422, // MSP430InstrInfo.td:508
438 BIC8mn = 423, // MSP430InstrInfo.td:516
439 BIC8mp = 424, // MSP430InstrInfo.td:520
440 BIC8mr = 425, // MSP430InstrInfo.td:490
441 BIC8rc = 426, // MSP430InstrInfo.td:477
442 BIC8ri = 427, // MSP430InstrInfo.td:483
443 BIC8rm = 428, // MSP430InstrInfo.td:459
444 BIC8rn = 429, // MSP430InstrInfo.td:465
445 BIC8rp = 430, // MSP430InstrInfo.td:472
446 BIC8rr = 431, // MSP430InstrInfo.td:452
447 BIS16mc = 432, // MSP430InstrInfo.td:499
448 BIS16mi = 433, // MSP430InstrInfo.td:505
449 BIS16mm = 434, // MSP430InstrInfo.td:512
450 BIS16mn = 435, // MSP430InstrInfo.td:518
451 BIS16mp = 436, // MSP430InstrInfo.td:522
452 BIS16mr = 437, // MSP430InstrInfo.td:493
453 BIS16rc = 438, // MSP430InstrInfo.td:480
454 BIS16ri = 439, // MSP430InstrInfo.td:486
455 BIS16rm = 440, // MSP430InstrInfo.td:462
456 BIS16rn = 441, // MSP430InstrInfo.td:467
457 BIS16rp = 442, // MSP430InstrInfo.td:474
458 BIS16rr = 443, // MSP430InstrInfo.td:455
459 BIS8mc = 444, // MSP430InstrInfo.td:496
460 BIS8mi = 445, // MSP430InstrInfo.td:502
461 BIS8mm = 446, // MSP430InstrInfo.td:508
462 BIS8mn = 447, // MSP430InstrInfo.td:516
463 BIS8mp = 448, // MSP430InstrInfo.td:520
464 BIS8mr = 449, // MSP430InstrInfo.td:490
465 BIS8rc = 450, // MSP430InstrInfo.td:477
466 BIS8ri = 451, // MSP430InstrInfo.td:483
467 BIS8rm = 452, // MSP430InstrInfo.td:459
468 BIS8rn = 453, // MSP430InstrInfo.td:465
469 BIS8rp = 454, // MSP430InstrInfo.td:472
470 BIS8rr = 455, // MSP430InstrInfo.td:452
471 BIT16mc = 456, // MSP430InstrInfo.td:861
472 BIT16mi = 457, // MSP430InstrInfo.td:870
473 BIT16mm = 458, // MSP430InstrInfo.td:881
474 BIT16mn = 459, // MSP430InstrInfo.td:889
475 BIT16mp = 460, // MSP430InstrInfo.td:894
476 BIT16mr = 461, // MSP430InstrInfo.td:852
477 BIT16rc = 462, // MSP430InstrInfo.td:815
478 BIT16ri = 463, // MSP430InstrInfo.td:824
479 BIT16rm = 464, // MSP430InstrInfo.td:833
480 BIT16rn = 465, // MSP430InstrInfo.td:840
481 BIT16rp = 466, // MSP430InstrInfo.td:845
482 BIT16rr = 467, // MSP430InstrInfo.td:806
483 BIT8mc = 468, // MSP430InstrInfo.td:857
484 BIT8mi = 469, // MSP430InstrInfo.td:866
485 BIT8mm = 470, // MSP430InstrInfo.td:875
486 BIT8mn = 471, // MSP430InstrInfo.td:887
487 BIT8mp = 472, // MSP430InstrInfo.td:892
488 BIT8mr = 473, // MSP430InstrInfo.td:848
489 BIT8rc = 474, // MSP430InstrInfo.td:811
490 BIT8ri = 475, // MSP430InstrInfo.td:820
491 BIT8rm = 476, // MSP430InstrInfo.td:829
492 BIT8rn = 477, // MSP430InstrInfo.td:838
493 BIT8rp = 478, // MSP430InstrInfo.td:843
494 BIT8rr = 479, // MSP430InstrInfo.td:802
495 Bi = 480, // MSP430InstrInfo.td:255
496 Bm = 481, // MSP430InstrInfo.td:261
497 Br = 482, // MSP430InstrInfo.td:258
498 CALLi = 483, // MSP430InstrInfo.td:284
499 CALLm = 484, // MSP430InstrInfo.td:290
500 CALLn = 485, // MSP430InstrInfo.td:293
501 CALLp = 486, // MSP430InstrInfo.td:294
502 CALLr = 487, // MSP430InstrInfo.td:287
503 CMP16mc = 488, // MSP430InstrInfo.td:738
504 CMP16mi = 489, // MSP430InstrInfo.td:748
505 CMP16mm = 490, // MSP430InstrInfo.td:785
506 CMP16mn = 491, // MSP430InstrInfo.td:791
507 CMP16mp = 492, // MSP430InstrInfo.td:796
508 CMP16mr = 493, // MSP430InstrInfo.td:777
509 CMP16rc = 494, // MSP430InstrInfo.td:720
510 CMP16ri = 495, // MSP430InstrInfo.td:729
511 CMP16rm = 496, // MSP430InstrInfo.td:758
512 CMP16rn = 497, // MSP430InstrInfo.td:765
513 CMP16rp = 498, // MSP430InstrInfo.td:770
514 CMP16rr = 499, // MSP430InstrInfo.td:711
515 CMP8mc = 500, // MSP430InstrInfo.td:734
516 CMP8mi = 501, // MSP430InstrInfo.td:743
517 CMP8mm = 502, // MSP430InstrInfo.td:781
518 CMP8mn = 503, // MSP430InstrInfo.td:789
519 CMP8mp = 504, // MSP430InstrInfo.td:794
520 CMP8mr = 505, // MSP430InstrInfo.td:773
521 CMP8rc = 506, // MSP430InstrInfo.td:716
522 CMP8ri = 507, // MSP430InstrInfo.td:725
523 CMP8rm = 508, // MSP430InstrInfo.td:754
524 CMP8rn = 509, // MSP430InstrInfo.td:763
525 CMP8rp = 510, // MSP430InstrInfo.td:768
526 CMP8rr = 511, // MSP430InstrInfo.td:707
527 DADD16mc = 512, // MSP430InstrInfo.td:499
528 DADD16mi = 513, // MSP430InstrInfo.td:505
529 DADD16mm = 514, // MSP430InstrInfo.td:512
530 DADD16mn = 515, // MSP430InstrInfo.td:518
531 DADD16mp = 516, // MSP430InstrInfo.td:522
532 DADD16mr = 517, // MSP430InstrInfo.td:493
533 DADD16rc = 518, // MSP430InstrInfo.td:480
534 DADD16ri = 519, // MSP430InstrInfo.td:486
535 DADD16rm = 520, // MSP430InstrInfo.td:462
536 DADD16rn = 521, // MSP430InstrInfo.td:467
537 DADD16rp = 522, // MSP430InstrInfo.td:474
538 DADD16rr = 523, // MSP430InstrInfo.td:455
539 DADD8mc = 524, // MSP430InstrInfo.td:496
540 DADD8mi = 525, // MSP430InstrInfo.td:502
541 DADD8mm = 526, // MSP430InstrInfo.td:508
542 DADD8mn = 527, // MSP430InstrInfo.td:516
543 DADD8mp = 528, // MSP430InstrInfo.td:520
544 DADD8mr = 529, // MSP430InstrInfo.td:490
545 DADD8rc = 530, // MSP430InstrInfo.td:477
546 DADD8ri = 531, // MSP430InstrInfo.td:483
547 DADD8rm = 532, // MSP430InstrInfo.td:459
548 DADD8rn = 533, // MSP430InstrInfo.td:465
549 DADD8rp = 534, // MSP430InstrInfo.td:472
550 DADD8rr = 535, // MSP430InstrInfo.td:452
551 JCC = 536, // MSP430InstrInfo.td:269
552 JMP = 537, // MSP430InstrInfo.td:248
553 MOV16mc = 538, // MSP430InstrInfo.td:407
554 MOV16mi = 539, // MSP430InstrInfo.td:416
555 MOV16mm = 540, // MSP430InstrInfo.td:434
556 MOV16mn = 541, // MSP430InstrInfo.td:441
557 MOV16mr = 542, // MSP430InstrInfo.td:425
558 MOV16rc = 543, // MSP430InstrInfo.td:335
559 MOV16ri = 544, // MSP430InstrInfo.td:343
560 MOV16rm = 545, // MSP430InstrInfo.td:354
561 MOV16rn = 546, // MSP430InstrInfo.td:362
562 MOV16rp = 547, // MSP430InstrInfo.td:383
563 MOV16rr = 548, // MSP430InstrInfo.td:324
564 MOV8mc = 549, // MSP430InstrInfo.td:403
565 MOV8mi = 550, // MSP430InstrInfo.td:412
566 MOV8mm = 551, // MSP430InstrInfo.td:430
567 MOV8mn = 552, // MSP430InstrInfo.td:439
568 MOV8mr = 553, // MSP430InstrInfo.td:421
569 MOV8rc = 554, // MSP430InstrInfo.td:331
570 MOV8ri = 555, // MSP430InstrInfo.td:339
571 MOV8rm = 556, // MSP430InstrInfo.td:350
572 MOV8rn = 557, // MSP430InstrInfo.td:358
573 MOV8rp = 558, // MSP430InstrInfo.td:380
574 MOV8rr = 559, // MSP430InstrInfo.td:320
575 MOVZX16rm8 = 560, // MSP430InstrInfo.td:373
576 MOVZX16rr8 = 561, // MSP430InstrInfo.td:369
577 POP16r = 562, // MSP430InstrInfo.td:302
578 PUSH16c = 563, // MSP430InstrInfo.td:311
579 PUSH16i = 564, // MSP430InstrInfo.td:312
580 PUSH16r = 565, // MSP430InstrInfo.td:310
581 PUSH8r = 566, // MSP430InstrInfo.td:309
582 RET = 567, // MSP430InstrInfo.td:229
583 RETI = 568, // MSP430InstrInfo.td:235
584 RRA16m = 569, // MSP430InstrInfo.td:661
585 RRA16n = 570, // MSP430InstrInfo.td:667
586 RRA16p = 571, // MSP430InstrInfo.td:669
587 RRA16r = 572, // MSP430InstrInfo.td:619
588 RRA8m = 573, // MSP430InstrInfo.td:657
589 RRA8n = 574, // MSP430InstrInfo.td:666
590 RRA8p = 575, // MSP430InstrInfo.td:668
591 RRA8r = 576, // MSP430InstrInfo.td:615
592 RRC16m = 577, // MSP430InstrInfo.td:676
593 RRC16n = 578, // MSP430InstrInfo.td:682
594 RRC16p = 579, // MSP430InstrInfo.td:684
595 RRC16r = 580, // MSP430InstrInfo.td:629
596 RRC8m = 581, // MSP430InstrInfo.td:672
597 RRC8n = 582, // MSP430InstrInfo.td:681
598 RRC8p = 583, // MSP430InstrInfo.td:683
599 RRC8r = 584, // MSP430InstrInfo.td:625
600 Rrcl16 = 585, // MSP430InstrInfo.td:219
601 Rrcl8 = 586, // MSP430InstrInfo.td:217
602 SEXT16m = 587, // MSP430InstrInfo.td:688
603 SEXT16n = 588, // MSP430InstrInfo.td:693
604 SEXT16p = 589, // MSP430InstrInfo.td:694
605 SEXT16r = 590, // MSP430InstrInfo.td:635
606 SUB16mc = 591, // MSP430InstrInfo.td:499
607 SUB16mi = 592, // MSP430InstrInfo.td:505
608 SUB16mm = 593, // MSP430InstrInfo.td:512
609 SUB16mn = 594, // MSP430InstrInfo.td:518
610 SUB16mp = 595, // MSP430InstrInfo.td:522
611 SUB16mr = 596, // MSP430InstrInfo.td:493
612 SUB16rc = 597, // MSP430InstrInfo.td:480
613 SUB16ri = 598, // MSP430InstrInfo.td:486
614 SUB16rm = 599, // MSP430InstrInfo.td:462
615 SUB16rn = 600, // MSP430InstrInfo.td:467
616 SUB16rp = 601, // MSP430InstrInfo.td:474
617 SUB16rr = 602, // MSP430InstrInfo.td:455
618 SUB8mc = 603, // MSP430InstrInfo.td:496
619 SUB8mi = 604, // MSP430InstrInfo.td:502
620 SUB8mm = 605, // MSP430InstrInfo.td:508
621 SUB8mn = 606, // MSP430InstrInfo.td:516
622 SUB8mp = 607, // MSP430InstrInfo.td:520
623 SUB8mr = 608, // MSP430InstrInfo.td:490
624 SUB8rc = 609, // MSP430InstrInfo.td:477
625 SUB8ri = 610, // MSP430InstrInfo.td:483
626 SUB8rm = 611, // MSP430InstrInfo.td:459
627 SUB8rn = 612, // MSP430InstrInfo.td:465
628 SUB8rp = 613, // MSP430InstrInfo.td:472
629 SUB8rr = 614, // MSP430InstrInfo.td:452
630 SUBC16mc = 615, // MSP430InstrInfo.td:499
631 SUBC16mi = 616, // MSP430InstrInfo.td:505
632 SUBC16mm = 617, // MSP430InstrInfo.td:512
633 SUBC16mn = 618, // MSP430InstrInfo.td:518
634 SUBC16mp = 619, // MSP430InstrInfo.td:522
635 SUBC16mr = 620, // MSP430InstrInfo.td:493
636 SUBC16rc = 621, // MSP430InstrInfo.td:480
637 SUBC16ri = 622, // MSP430InstrInfo.td:486
638 SUBC16rm = 623, // MSP430InstrInfo.td:462
639 SUBC16rn = 624, // MSP430InstrInfo.td:467
640 SUBC16rp = 625, // MSP430InstrInfo.td:474
641 SUBC16rr = 626, // MSP430InstrInfo.td:455
642 SUBC8mc = 627, // MSP430InstrInfo.td:496
643 SUBC8mi = 628, // MSP430InstrInfo.td:502
644 SUBC8mm = 629, // MSP430InstrInfo.td:508
645 SUBC8mn = 630, // MSP430InstrInfo.td:516
646 SUBC8mp = 631, // MSP430InstrInfo.td:520
647 SUBC8mr = 632, // MSP430InstrInfo.td:490
648 SUBC8rc = 633, // MSP430InstrInfo.td:477
649 SUBC8ri = 634, // MSP430InstrInfo.td:483
650 SUBC8rm = 635, // MSP430InstrInfo.td:459
651 SUBC8rn = 636, // MSP430InstrInfo.td:465
652 SUBC8rp = 637, // MSP430InstrInfo.td:472
653 SUBC8rr = 638, // MSP430InstrInfo.td:452
654 SWPB16m = 639, // MSP430InstrInfo.td:698
655 SWPB16n = 640, // MSP430InstrInfo.td:702
656 SWPB16p = 641, // MSP430InstrInfo.td:703
657 SWPB16r = 642, // MSP430InstrInfo.td:648
658 Select16 = 643, // MSP430InstrInfo.td:193
659 Select8 = 644, // MSP430InstrInfo.td:189
660 Shl16 = 645, // MSP430InstrInfo.td:202
661 Shl8 = 646, // MSP430InstrInfo.td:199
662 Sra16 = 647, // MSP430InstrInfo.td:208
663 Sra8 = 648, // MSP430InstrInfo.td:205
664 Srl16 = 649, // MSP430InstrInfo.td:214
665 Srl8 = 650, // MSP430InstrInfo.td:211
666 XOR16mc = 651, // MSP430InstrInfo.td:499
667 XOR16mi = 652, // MSP430InstrInfo.td:505
668 XOR16mm = 653, // MSP430InstrInfo.td:512
669 XOR16mn = 654, // MSP430InstrInfo.td:518
670 XOR16mp = 655, // MSP430InstrInfo.td:522
671 XOR16mr = 656, // MSP430InstrInfo.td:493
672 XOR16rc = 657, // MSP430InstrInfo.td:480
673 XOR16ri = 658, // MSP430InstrInfo.td:486
674 XOR16rm = 659, // MSP430InstrInfo.td:462
675 XOR16rn = 660, // MSP430InstrInfo.td:467
676 XOR16rp = 661, // MSP430InstrInfo.td:474
677 XOR16rr = 662, // MSP430InstrInfo.td:455
678 XOR8mc = 663, // MSP430InstrInfo.td:496
679 XOR8mi = 664, // MSP430InstrInfo.td:502
680 XOR8mm = 665, // MSP430InstrInfo.td:508
681 XOR8mn = 666, // MSP430InstrInfo.td:516
682 XOR8mp = 667, // MSP430InstrInfo.td:520
683 XOR8mr = 668, // MSP430InstrInfo.td:490
684 XOR8rc = 669, // MSP430InstrInfo.td:477
685 XOR8ri = 670, // MSP430InstrInfo.td:483
686 XOR8rm = 671, // MSP430InstrInfo.td:459
687 XOR8rn = 672, // MSP430InstrInfo.td:465
688 XOR8rp = 673, // MSP430InstrInfo.td:472
689 XOR8rr = 674, // MSP430InstrInfo.td:452
690 ZEXT16r = 675, // MSP430InstrInfo.td:643
691 INSTRUCTION_LIST_END = 676
692 };
693
694} // namespace llvm::MSP430
695
696#endif // GET_INSTRINFO_ENUM
697
698#ifdef GET_INSTRINFO_SCHED_ENUM
699#undef GET_INSTRINFO_SCHED_ENUM
700
701namespace llvm::MSP430::Sched {
702
703 enum {
704 NoInstrModel = 0,
705 SCHED_LIST_END = 1
706 };
707
708} // namespace llvm::MSP430::Sched
709
710#endif // GET_INSTRINFO_SCHED_ENUM
711
712#if defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
713
714namespace llvm {
715
716struct MSP430InstrTable {
717 MCInstrDesc Insts[676];
718 static_assert(alignof(MCInstrDesc) >= alignof(MCPhysReg), "Unwanted padding between Insts and ImplicitOps");
719 MCPhysReg ImplicitOps[17];
720 char Padding[sizeof(MCOperandInfo) - sizeof ImplicitOps % sizeof(MCOperandInfo)];
721 static_assert(alignof(MCInstrDesc) >= alignof(MCOperandInfo), "Unwanted padding between Insts and OperandInfo");
722 MCOperandInfo OperandInfo[260];
723};
724} // namespace llvm
725
726#endif // defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
727
728#ifdef GET_INSTRINFO_MC_DESC
729#undef GET_INSTRINFO_MC_DESC
730
731namespace llvm {
732
733static_assert((sizeof MSP430InstrTable::ImplicitOps + sizeof MSP430InstrTable::Padding) % sizeof(MCOperandInfo) == 0);
734static constexpr unsigned MSP430OpInfoBase = (sizeof MSP430InstrTable::ImplicitOps + sizeof MSP430InstrTable::Padding) / sizeof(MCOperandInfo);
735
736extern const MSP430InstrTable MSP430Descs = {
737 {
738 { 675, 2, 1, 2, 0, 0, 0, MSP430OpInfoBase + 242, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ZEXT16r
739 { 674, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 207, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR8rr
740 { 673, 4, 2, 2, 0, 0, 1, MSP430OpInfoBase + 203, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR8rp
741 { 672, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR8rn
742 { 671, 4, 1, 4, 0, 0, 1, MSP430OpInfoBase + 196, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR8rm
743 { 670, 3, 1, 4, 0, 0, 1, MSP430OpInfoBase + 193, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR8ri
744 { 669, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 190, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR8rc
745 { 668, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 187, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR8mr
746 { 667, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR8mp
747 { 666, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR8mn
748 { 665, 4, 0, 6, 0, 0, 1, MSP430OpInfoBase + 157, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR8mm
749 { 664, 3, 0, 6, 0, 0, 1, MSP430OpInfoBase + 154, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR8mi
750 { 663, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 151, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR8mc
751 { 662, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 184, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR16rr
752 { 661, 4, 2, 2, 0, 0, 1, MSP430OpInfoBase + 180, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR16rp
753 { 660, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 177, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR16rn
754 { 659, 4, 1, 4, 0, 0, 1, MSP430OpInfoBase + 173, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR16rm
755 { 658, 3, 1, 4, 0, 0, 1, MSP430OpInfoBase + 170, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR16ri
756 { 657, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 167, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR16rc
757 { 656, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 164, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR16mr
758 { 655, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR16mp
759 { 654, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR16mn
760 { 653, 4, 0, 6, 0, 0, 1, MSP430OpInfoBase + 157, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR16mm
761 { 652, 3, 0, 6, 0, 0, 1, MSP430OpInfoBase + 154, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR16mi
762 { 651, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 151, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR16mc
763 { 650, 3, 1, 0, 0, 0, 1, MSP430OpInfoBase + 257, 0, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Srl8
764 { 649, 3, 1, 0, 0, 0, 1, MSP430OpInfoBase + 254, 0, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Srl16
765 { 648, 3, 1, 0, 0, 0, 1, MSP430OpInfoBase + 257, 0, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Sra8
766 { 647, 3, 1, 0, 0, 0, 1, MSP430OpInfoBase + 254, 0, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Sra16
767 { 646, 3, 1, 0, 0, 0, 1, MSP430OpInfoBase + 257, 0, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Shl8
768 { 645, 3, 1, 0, 0, 0, 1, MSP430OpInfoBase + 254, 0, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Shl16
769 { 644, 4, 1, 0, 0, 1, 0, MSP430OpInfoBase + 250, 0, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Select8
770 { 643, 4, 1, 0, 0, 1, 0, MSP430OpInfoBase + 246, 0, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Select16
771 { 642, 2, 1, 2, 0, 0, 0, MSP430OpInfoBase + 242, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SWPB16r
772 { 641, 1, 0, 2, 0, 0, 0, MSP430OpInfoBase + 232, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SWPB16p
773 { 640, 1, 0, 2, 0, 0, 0, MSP430OpInfoBase + 232, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SWPB16n
774 { 639, 2, 0, 4, 0, 0, 0, MSP430OpInfoBase + 230, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SWPB16m
775 { 638, 3, 1, 2, 0, 1, 1, MSP430OpInfoBase + 207, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC8rr
776 { 637, 4, 2, 2, 0, 1, 1, MSP430OpInfoBase + 203, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC8rp
777 { 636, 3, 1, 2, 0, 1, 1, MSP430OpInfoBase + 200, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC8rn
778 { 635, 4, 1, 4, 0, 1, 1, MSP430OpInfoBase + 196, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC8rm
779 { 634, 3, 1, 4, 0, 1, 1, MSP430OpInfoBase + 193, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC8ri
780 { 633, 3, 1, 2, 0, 1, 1, MSP430OpInfoBase + 190, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC8rc
781 { 632, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 187, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC8mr
782 { 631, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 161, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC8mp
783 { 630, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 161, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC8mn
784 { 629, 4, 0, 6, 0, 1, 1, MSP430OpInfoBase + 157, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC8mm
785 { 628, 3, 0, 6, 0, 1, 1, MSP430OpInfoBase + 154, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC8mi
786 { 627, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 151, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC8mc
787 { 626, 3, 1, 2, 0, 1, 1, MSP430OpInfoBase + 184, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC16rr
788 { 625, 4, 2, 2, 0, 1, 1, MSP430OpInfoBase + 180, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC16rp
789 { 624, 3, 1, 2, 0, 1, 1, MSP430OpInfoBase + 177, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC16rn
790 { 623, 4, 1, 4, 0, 1, 1, MSP430OpInfoBase + 173, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC16rm
791 { 622, 3, 1, 4, 0, 1, 1, MSP430OpInfoBase + 170, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC16ri
792 { 621, 3, 1, 2, 0, 1, 1, MSP430OpInfoBase + 167, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC16rc
793 { 620, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 164, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC16mr
794 { 619, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 161, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC16mp
795 { 618, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 161, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC16mn
796 { 617, 4, 0, 6, 0, 1, 1, MSP430OpInfoBase + 157, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC16mm
797 { 616, 3, 0, 6, 0, 1, 1, MSP430OpInfoBase + 154, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC16mi
798 { 615, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 151, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC16mc
799 { 614, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 207, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB8rr
800 { 613, 4, 2, 2, 0, 0, 1, MSP430OpInfoBase + 203, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB8rp
801 { 612, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB8rn
802 { 611, 4, 1, 4, 0, 0, 1, MSP430OpInfoBase + 196, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB8rm
803 { 610, 3, 1, 4, 0, 0, 1, MSP430OpInfoBase + 193, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB8ri
804 { 609, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 190, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB8rc
805 { 608, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 187, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB8mr
806 { 607, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB8mp
807 { 606, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB8mn
808 { 605, 4, 0, 6, 0, 0, 1, MSP430OpInfoBase + 157, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB8mm
809 { 604, 3, 0, 6, 0, 0, 1, MSP430OpInfoBase + 154, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB8mi
810 { 603, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 151, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB8mc
811 { 602, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 184, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB16rr
812 { 601, 4, 2, 2, 0, 0, 1, MSP430OpInfoBase + 180, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB16rp
813 { 600, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 177, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB16rn
814 { 599, 4, 1, 4, 0, 0, 1, MSP430OpInfoBase + 173, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB16rm
815 { 598, 3, 1, 4, 0, 0, 1, MSP430OpInfoBase + 170, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB16ri
816 { 597, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 167, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB16rc
817 { 596, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 164, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB16mr
818 { 595, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB16mp
819 { 594, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB16mn
820 { 593, 4, 0, 6, 0, 0, 1, MSP430OpInfoBase + 157, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB16mm
821 { 592, 3, 0, 6, 0, 0, 1, MSP430OpInfoBase + 154, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB16mi
822 { 591, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 151, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB16mc
823 { 590, 2, 1, 2, 0, 0, 1, MSP430OpInfoBase + 242, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SEXT16r
824 { 589, 1, 0, 2, 0, 0, 1, MSP430OpInfoBase + 232, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SEXT16p
825 { 588, 1, 0, 2, 0, 0, 1, MSP430OpInfoBase + 232, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SEXT16n
826 { 587, 2, 0, 4, 0, 0, 1, MSP430OpInfoBase + 230, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SEXT16m
827 { 586, 2, 1, 0, 0, 0, 1, MSP430OpInfoBase + 228, 0, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Rrcl8
828 { 585, 2, 1, 0, 0, 0, 1, MSP430OpInfoBase + 217, 0, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Rrcl16
829 { 584, 2, 1, 2, 0, 1, 1, MSP430OpInfoBase + 244, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RRC8r
830 { 583, 1, 0, 2, 0, 1, 1, MSP430OpInfoBase + 232, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RRC8p
831 { 582, 1, 0, 2, 0, 1, 1, MSP430OpInfoBase + 232, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RRC8n
832 { 581, 2, 0, 4, 0, 1, 1, MSP430OpInfoBase + 230, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RRC8m
833 { 580, 2, 1, 2, 0, 1, 1, MSP430OpInfoBase + 242, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RRC16r
834 { 579, 1, 0, 2, 0, 1, 1, MSP430OpInfoBase + 232, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RRC16p
835 { 578, 1, 0, 2, 0, 1, 1, MSP430OpInfoBase + 232, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RRC16n
836 { 577, 2, 0, 4, 0, 1, 1, MSP430OpInfoBase + 230, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RRC16m
837 { 576, 2, 1, 2, 0, 0, 1, MSP430OpInfoBase + 244, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RRA8r
838 { 575, 1, 0, 2, 0, 0, 1, MSP430OpInfoBase + 232, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RRA8p
839 { 574, 1, 0, 2, 0, 0, 1, MSP430OpInfoBase + 232, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RRA8n
840 { 573, 2, 0, 4, 0, 0, 1, MSP430OpInfoBase + 230, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RRA8m
841 { 572, 2, 1, 2, 0, 0, 1, MSP430OpInfoBase + 242, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RRA16r
842 { 571, 1, 0, 2, 0, 0, 1, MSP430OpInfoBase + 232, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RRA16p
843 { 570, 1, 0, 2, 0, 0, 1, MSP430OpInfoBase + 232, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RRA16n
844 { 569, 2, 0, 4, 0, 0, 1, MSP430OpInfoBase + 230, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RRA16m
845 { 568, 0, 0, 2, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RETI
846 { 567, 0, 0, 2, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RET
847 { 566, 1, 0, 2, 0, 1, 1, MSP430OpInfoBase + 241, 15, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PUSH8r
848 { 565, 1, 0, 2, 0, 1, 1, MSP430OpInfoBase + 28, 15, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PUSH16r
849 { 564, 1, 0, 4, 0, 1, 1, MSP430OpInfoBase + 1, 15, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PUSH16i
850 { 563, 1, 0, 2, 0, 1, 1, MSP430OpInfoBase + 0, 15, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PUSH16c
851 { 562, 1, 1, 2, 0, 1, 1, MSP430OpInfoBase + 28, 15, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // POP16r
852 { 561, 2, 1, 2, 0, 0, 0, MSP430OpInfoBase + 239, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOVZX16rr8
853 { 560, 3, 1, 4, 0, 0, 0, MSP430OpInfoBase + 212, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOVZX16rm8
854 { 559, 2, 1, 2, 0, 0, 0, MSP430OpInfoBase + 228, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV8rr
855 { 558, 3, 2, 2, 0, 0, 0, MSP430OpInfoBase + 236, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV8rp
856 { 557, 2, 1, 2, 0, 0, 0, MSP430OpInfoBase + 226, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV8rn
857 { 556, 3, 1, 4, 0, 0, 0, MSP430OpInfoBase + 223, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV8rm
858 { 555, 2, 1, 4, 0, 0, 0, MSP430OpInfoBase + 221, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV8ri
859 { 554, 2, 1, 2, 0, 0, 0, MSP430OpInfoBase + 219, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV8rc
860 { 553, 3, 0, 4, 0, 0, 0, MSP430OpInfoBase + 187, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV8mr
861 { 552, 3, 0, 4, 0, 0, 0, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV8mn
862 { 551, 4, 0, 6, 0, 0, 0, MSP430OpInfoBase + 157, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV8mm
863 { 550, 3, 0, 6, 0, 0, 0, MSP430OpInfoBase + 154, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV8mi
864 { 549, 3, 0, 4, 0, 0, 0, MSP430OpInfoBase + 151, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV8mc
865 { 548, 2, 1, 2, 0, 0, 0, MSP430OpInfoBase + 217, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV16rr
866 { 547, 3, 2, 2, 0, 0, 0, MSP430OpInfoBase + 233, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV16rp
867 { 546, 2, 1, 2, 0, 0, 0, MSP430OpInfoBase + 215, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV16rn
868 { 545, 3, 1, 4, 0, 0, 0, MSP430OpInfoBase + 212, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV16rm
869 { 544, 2, 1, 4, 0, 0, 0, MSP430OpInfoBase + 210, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV16ri
870 { 543, 2, 1, 2, 0, 0, 0, MSP430OpInfoBase + 34, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV16rc
871 { 542, 3, 0, 4, 0, 0, 0, MSP430OpInfoBase + 164, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV16mr
872 { 541, 3, 0, 4, 0, 0, 0, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV16mn
873 { 540, 4, 0, 6, 0, 0, 0, MSP430OpInfoBase + 157, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV16mm
874 { 539, 3, 0, 6, 0, 0, 0, MSP430OpInfoBase + 154, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV16mi
875 { 538, 3, 0, 4, 0, 0, 0, MSP430OpInfoBase + 151, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV16mc
876 { 537, 1, 0, 2, 0, 0, 0, MSP430OpInfoBase + 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JMP
877 { 536, 2, 0, 2, 0, 1, 0, MSP430OpInfoBase + 9, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JCC
878 { 535, 3, 1, 2, 0, 1, 1, MSP430OpInfoBase + 207, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD8rr
879 { 534, 4, 2, 2, 0, 1, 1, MSP430OpInfoBase + 203, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD8rp
880 { 533, 3, 1, 2, 0, 1, 1, MSP430OpInfoBase + 200, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD8rn
881 { 532, 4, 1, 4, 0, 1, 1, MSP430OpInfoBase + 196, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD8rm
882 { 531, 3, 1, 4, 0, 1, 1, MSP430OpInfoBase + 193, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD8ri
883 { 530, 3, 1, 2, 0, 1, 1, MSP430OpInfoBase + 190, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD8rc
884 { 529, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 187, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD8mr
885 { 528, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 161, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD8mp
886 { 527, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 161, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD8mn
887 { 526, 4, 0, 6, 0, 1, 1, MSP430OpInfoBase + 157, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD8mm
888 { 525, 3, 0, 6, 0, 1, 1, MSP430OpInfoBase + 154, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD8mi
889 { 524, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 151, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD8mc
890 { 523, 3, 1, 2, 0, 1, 1, MSP430OpInfoBase + 184, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD16rr
891 { 522, 4, 2, 2, 0, 1, 1, MSP430OpInfoBase + 180, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD16rp
892 { 521, 3, 1, 2, 0, 1, 1, MSP430OpInfoBase + 177, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD16rn
893 { 520, 4, 1, 4, 0, 1, 1, MSP430OpInfoBase + 173, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD16rm
894 { 519, 3, 1, 4, 0, 1, 1, MSP430OpInfoBase + 170, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD16ri
895 { 518, 3, 1, 2, 0, 1, 1, MSP430OpInfoBase + 167, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD16rc
896 { 517, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 164, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD16mr
897 { 516, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 161, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD16mp
898 { 515, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 161, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD16mn
899 { 514, 4, 0, 6, 0, 1, 1, MSP430OpInfoBase + 157, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD16mm
900 { 513, 3, 0, 6, 0, 1, 1, MSP430OpInfoBase + 154, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD16mi
901 { 512, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 151, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD16mc
902 { 511, 2, 0, 2, 0, 0, 1, MSP430OpInfoBase + 228, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP8rr
903 { 510, 2, 0, 2, 0, 0, 1, MSP430OpInfoBase + 226, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP8rp
904 { 509, 2, 0, 2, 0, 0, 1, MSP430OpInfoBase + 226, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP8rn
905 { 508, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 223, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP8rm
906 { 507, 2, 0, 4, 0, 0, 1, MSP430OpInfoBase + 221, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP8ri
907 { 506, 2, 0, 2, 0, 0, 1, MSP430OpInfoBase + 219, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP8rc
908 { 505, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 187, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP8mr
909 { 504, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP8mp
910 { 503, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP8mn
911 { 502, 4, 0, 6, 0, 0, 1, MSP430OpInfoBase + 157, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP8mm
912 { 501, 3, 0, 6, 0, 0, 1, MSP430OpInfoBase + 154, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP8mi
913 { 500, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 151, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP8mc
914 { 499, 2, 0, 2, 0, 0, 1, MSP430OpInfoBase + 217, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP16rr
915 { 498, 2, 0, 2, 0, 0, 1, MSP430OpInfoBase + 215, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP16rp
916 { 497, 2, 0, 2, 0, 0, 1, MSP430OpInfoBase + 215, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP16rn
917 { 496, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 212, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP16rm
918 { 495, 2, 0, 4, 0, 0, 1, MSP430OpInfoBase + 210, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP16ri
919 { 494, 2, 0, 2, 0, 0, 1, MSP430OpInfoBase + 34, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP16rc
920 { 493, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 164, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP16mr
921 { 492, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP16mp
922 { 491, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP16mn
923 { 490, 4, 0, 6, 0, 0, 1, MSP430OpInfoBase + 157, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP16mm
924 { 489, 3, 0, 6, 0, 0, 1, MSP430OpInfoBase + 154, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP16mi
925 { 488, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 151, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP16mc
926 { 487, 1, 0, 2, 0, 1, 6, MSP430OpInfoBase + 28, 8, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CALLr
927 { 486, 1, 0, 2, 0, 1, 6, MSP430OpInfoBase + 232, 8, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CALLp
928 { 485, 1, 0, 2, 0, 1, 6, MSP430OpInfoBase + 232, 8, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CALLn
929 { 484, 2, 0, 4, 0, 1, 6, MSP430OpInfoBase + 230, 8, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CALLm
930 { 483, 1, 0, 4, 0, 1, 6, MSP430OpInfoBase + 1, 8, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CALLi
931 { 482, 1, 0, 2, 0, 0, 0, MSP430OpInfoBase + 28, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Br
932 { 481, 2, 0, 4, 0, 0, 0, MSP430OpInfoBase + 230, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Bm
933 { 480, 1, 0, 4, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Bi
934 { 479, 2, 0, 2, 0, 0, 1, MSP430OpInfoBase + 228, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT8rr
935 { 478, 2, 0, 2, 0, 0, 1, MSP430OpInfoBase + 226, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT8rp
936 { 477, 2, 0, 2, 0, 0, 1, MSP430OpInfoBase + 226, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT8rn
937 { 476, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 223, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT8rm
938 { 475, 2, 0, 4, 0, 0, 1, MSP430OpInfoBase + 221, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT8ri
939 { 474, 2, 0, 2, 0, 0, 1, MSP430OpInfoBase + 219, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT8rc
940 { 473, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 187, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT8mr
941 { 472, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT8mp
942 { 471, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT8mn
943 { 470, 4, 0, 6, 0, 0, 1, MSP430OpInfoBase + 157, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT8mm
944 { 469, 3, 0, 6, 0, 0, 1, MSP430OpInfoBase + 154, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT8mi
945 { 468, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 151, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT8mc
946 { 467, 2, 0, 2, 0, 0, 1, MSP430OpInfoBase + 217, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT16rr
947 { 466, 2, 0, 2, 0, 0, 1, MSP430OpInfoBase + 215, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT16rp
948 { 465, 2, 0, 2, 0, 0, 1, MSP430OpInfoBase + 215, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT16rn
949 { 464, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 212, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT16rm
950 { 463, 2, 0, 4, 0, 0, 1, MSP430OpInfoBase + 210, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT16ri
951 { 462, 2, 0, 2, 0, 0, 1, MSP430OpInfoBase + 34, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT16rc
952 { 461, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 164, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT16mr
953 { 460, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT16mp
954 { 459, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT16mn
955 { 458, 4, 0, 6, 0, 0, 1, MSP430OpInfoBase + 157, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT16mm
956 { 457, 3, 0, 6, 0, 0, 1, MSP430OpInfoBase + 154, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT16mi
957 { 456, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 151, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT16mc
958 { 455, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 207, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS8rr
959 { 454, 4, 2, 2, 0, 0, 1, MSP430OpInfoBase + 203, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS8rp
960 { 453, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS8rn
961 { 452, 4, 1, 4, 0, 0, 1, MSP430OpInfoBase + 196, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS8rm
962 { 451, 3, 1, 4, 0, 0, 1, MSP430OpInfoBase + 193, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS8ri
963 { 450, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 190, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS8rc
964 { 449, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 187, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS8mr
965 { 448, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS8mp
966 { 447, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS8mn
967 { 446, 4, 0, 6, 0, 0, 1, MSP430OpInfoBase + 157, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS8mm
968 { 445, 3, 0, 6, 0, 0, 1, MSP430OpInfoBase + 154, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS8mi
969 { 444, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 151, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS8mc
970 { 443, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 184, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS16rr
971 { 442, 4, 2, 2, 0, 0, 1, MSP430OpInfoBase + 180, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS16rp
972 { 441, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 177, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS16rn
973 { 440, 4, 1, 4, 0, 0, 1, MSP430OpInfoBase + 173, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS16rm
974 { 439, 3, 1, 4, 0, 0, 1, MSP430OpInfoBase + 170, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS16ri
975 { 438, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 167, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS16rc
976 { 437, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 164, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS16mr
977 { 436, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS16mp
978 { 435, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS16mn
979 { 434, 4, 0, 6, 0, 0, 1, MSP430OpInfoBase + 157, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS16mm
980 { 433, 3, 0, 6, 0, 0, 1, MSP430OpInfoBase + 154, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS16mi
981 { 432, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 151, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS16mc
982 { 431, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 207, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC8rr
983 { 430, 4, 2, 2, 0, 0, 1, MSP430OpInfoBase + 203, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC8rp
984 { 429, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC8rn
985 { 428, 4, 1, 4, 0, 0, 1, MSP430OpInfoBase + 196, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC8rm
986 { 427, 3, 1, 4, 0, 0, 1, MSP430OpInfoBase + 193, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC8ri
987 { 426, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 190, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC8rc
988 { 425, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 187, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC8mr
989 { 424, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC8mp
990 { 423, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC8mn
991 { 422, 4, 0, 6, 0, 0, 1, MSP430OpInfoBase + 157, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC8mm
992 { 421, 3, 0, 6, 0, 0, 1, MSP430OpInfoBase + 154, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC8mi
993 { 420, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 151, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC8mc
994 { 419, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 184, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC16rr
995 { 418, 4, 2, 2, 0, 0, 1, MSP430OpInfoBase + 180, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC16rp
996 { 417, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 177, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC16rn
997 { 416, 4, 1, 4, 0, 0, 1, MSP430OpInfoBase + 173, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC16rm
998 { 415, 3, 1, 4, 0, 0, 1, MSP430OpInfoBase + 170, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC16ri
999 { 414, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 167, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC16rc
1000 { 413, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 164, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC16mr
1001 { 412, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC16mp
1002 { 411, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC16mn
1003 { 410, 4, 0, 6, 0, 0, 1, MSP430OpInfoBase + 157, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC16mm
1004 { 409, 3, 0, 6, 0, 0, 1, MSP430OpInfoBase + 154, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC16mi
1005 { 408, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 151, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC16mc
1006 { 407, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 207, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND8rr
1007 { 406, 4, 2, 2, 0, 0, 1, MSP430OpInfoBase + 203, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND8rp
1008 { 405, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND8rn
1009 { 404, 4, 1, 4, 0, 0, 1, MSP430OpInfoBase + 196, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND8rm
1010 { 403, 3, 1, 4, 0, 0, 1, MSP430OpInfoBase + 193, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND8ri
1011 { 402, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 190, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND8rc
1012 { 401, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 187, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND8mr
1013 { 400, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND8mp
1014 { 399, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND8mn
1015 { 398, 4, 0, 6, 0, 0, 1, MSP430OpInfoBase + 157, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND8mm
1016 { 397, 3, 0, 6, 0, 0, 1, MSP430OpInfoBase + 154, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND8mi
1017 { 396, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 151, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND8mc
1018 { 395, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 184, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND16rr
1019 { 394, 4, 2, 2, 0, 0, 1, MSP430OpInfoBase + 180, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND16rp
1020 { 393, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 177, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND16rn
1021 { 392, 4, 1, 4, 0, 0, 1, MSP430OpInfoBase + 173, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND16rm
1022 { 391, 3, 1, 4, 0, 0, 1, MSP430OpInfoBase + 170, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND16ri
1023 { 390, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 167, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND16rc
1024 { 389, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 164, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND16mr
1025 { 388, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND16mp
1026 { 387, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND16mn
1027 { 386, 4, 0, 6, 0, 0, 1, MSP430OpInfoBase + 157, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND16mm
1028 { 385, 3, 0, 6, 0, 0, 1, MSP430OpInfoBase + 154, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND16mi
1029 { 384, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 151, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND16mc
1030 { 383, 2, 0, 0, 0, 1, 2, MSP430OpInfoBase + 20, 5, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADJCALLSTACKUP
1031 { 382, 2, 0, 0, 0, 1, 2, MSP430OpInfoBase + 20, 5, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADJCALLSTACKDOWN
1032 { 381, 3, 1, 0, 0, 1, 1, MSP430OpInfoBase + 29, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDframe
1033 { 380, 3, 1, 2, 0, 1, 1, MSP430OpInfoBase + 207, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC8rr
1034 { 379, 4, 2, 2, 0, 1, 1, MSP430OpInfoBase + 203, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC8rp
1035 { 378, 3, 1, 2, 0, 1, 1, MSP430OpInfoBase + 200, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC8rn
1036 { 377, 4, 1, 4, 0, 1, 1, MSP430OpInfoBase + 196, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC8rm
1037 { 376, 3, 1, 4, 0, 1, 1, MSP430OpInfoBase + 193, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC8ri
1038 { 375, 3, 1, 2, 0, 1, 1, MSP430OpInfoBase + 190, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC8rc
1039 { 374, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 187, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC8mr
1040 { 373, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 161, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC8mp
1041 { 372, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 161, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC8mn
1042 { 371, 4, 0, 6, 0, 1, 1, MSP430OpInfoBase + 157, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC8mm
1043 { 370, 3, 0, 6, 0, 1, 1, MSP430OpInfoBase + 154, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC8mi
1044 { 369, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 151, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC8mc
1045 { 368, 3, 1, 2, 0, 1, 1, MSP430OpInfoBase + 184, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC16rr
1046 { 367, 4, 2, 2, 0, 1, 1, MSP430OpInfoBase + 180, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC16rp
1047 { 366, 3, 1, 2, 0, 1, 1, MSP430OpInfoBase + 177, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC16rn
1048 { 365, 4, 1, 4, 0, 1, 1, MSP430OpInfoBase + 173, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC16rm
1049 { 364, 3, 1, 4, 0, 1, 1, MSP430OpInfoBase + 170, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC16ri
1050 { 363, 3, 1, 2, 0, 1, 1, MSP430OpInfoBase + 167, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC16rc
1051 { 362, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 164, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC16mr
1052 { 361, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 161, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC16mp
1053 { 360, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 161, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC16mn
1054 { 359, 4, 0, 6, 0, 1, 1, MSP430OpInfoBase + 157, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC16mm
1055 { 358, 3, 0, 6, 0, 1, 1, MSP430OpInfoBase + 154, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC16mi
1056 { 357, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 151, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC16mc
1057 { 356, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 207, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD8rr
1058 { 355, 4, 2, 2, 0, 0, 1, MSP430OpInfoBase + 203, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD8rp
1059 { 354, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD8rn
1060 { 353, 4, 1, 4, 0, 0, 1, MSP430OpInfoBase + 196, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD8rm
1061 { 352, 3, 1, 4, 0, 0, 1, MSP430OpInfoBase + 193, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD8ri
1062 { 351, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 190, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD8rc
1063 { 350, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 187, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD8mr
1064 { 349, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD8mp
1065 { 348, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD8mn
1066 { 347, 4, 0, 6, 0, 0, 1, MSP430OpInfoBase + 157, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD8mm
1067 { 346, 3, 0, 6, 0, 0, 1, MSP430OpInfoBase + 154, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD8mi
1068 { 345, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 151, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD8mc
1069 { 344, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 184, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD16rr
1070 { 343, 4, 2, 2, 0, 0, 1, MSP430OpInfoBase + 180, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD16rp
1071 { 342, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 177, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD16rn
1072 { 341, 4, 1, 4, 0, 0, 1, MSP430OpInfoBase + 173, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD16rm
1073 { 340, 3, 1, 4, 0, 0, 1, MSP430OpInfoBase + 170, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD16ri
1074 { 339, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 167, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD16rc
1075 { 338, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 164, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD16mr
1076 { 337, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD16mp
1077 { 336, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD16mn
1078 { 335, 4, 0, 6, 0, 0, 1, MSP430OpInfoBase + 157, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD16mm
1079 { 334, 3, 0, 6, 0, 0, 1, MSP430OpInfoBase + 154, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD16mi
1080 { 333, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 151, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD16mc
1081 { 332, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 147, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UBFX
1082 { 331, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 147, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SBFX
1083 { 330, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_UMIN
1084 { 329, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_UMAX
1085 { 328, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SMIN
1086 { 327, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SMAX
1087 { 326, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_XOR
1088 { 325, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_OR
1089 { 324, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_AND
1090 { 323, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_MUL
1091 { 322, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_ADD
1092 { 321, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMINIMUMNUM
1093 { 320, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMAXIMUMNUM
1094 { 319, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMINIMUM
1095 { 318, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMAXIMUM
1096 { 317, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMIN
1097 { 316, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMAX
1098 { 315, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMUL
1099 { 314, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FADD
1100 { 313, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SEQ_FMUL
1101 { 312, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SEQ_FADD
1102 { 311, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UBSANTRAP
1103 { 310, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_DEBUGTRAP
1104 { 309, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRAP
1105 { 308, 3, 0, 0, 0, 0, 0, MSP430OpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMSET_INLINE
1106 { 307, 3, 0, 0, 0, 0, 0, MSP430OpInfoBase + 57, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BZERO
1107 { 306, 4, 0, 0, 0, 0, 0, MSP430OpInfoBase + 143, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMSET
1108 { 305, 4, 0, 0, 0, 0, 0, MSP430OpInfoBase + 143, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMMOVE
1109 { 304, 3, 0, 0, 0, 0, 0, MSP430OpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMCPY_INLINE
1110 { 303, 4, 0, 0, 0, 0, 0, MSP430OpInfoBase + 143, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMCPY
1111 { 302, 2, 0, 0, 0, 0, 0, MSP430OpInfoBase + 141, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_WRITE_REGISTER
1112 { 301, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_READ_REGISTER
1113 { 300, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FCMPS
1114 { 299, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FCMP
1115 { 298, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FLDEXP
1116 { 297, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FSQRT
1117 { 296, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FMA
1118 { 295, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FREM
1119 { 294, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FDIV
1120 { 293, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FMUL
1121 { 292, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FSUB
1122 { 291, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FADD
1123 { 290, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STACKRESTORE
1124 { 289, 1, 1, 0, 0, 0, 0, MSP430OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STACKSAVE
1125 { 288, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 68, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_DYN_STACKALLOC
1126 { 287, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_JUMP_TABLE
1127 { 286, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BLOCK_ADDR
1128 { 285, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ADDRSPACE_CAST
1129 { 284, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FNEARBYINT
1130 { 283, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FRINT
1131 { 282, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FFLOOR
1132 { 281, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSQRT
1133 { 280, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FTANH
1134 { 279, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSINH
1135 { 278, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCOSH
1136 { 277, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FATAN2
1137 { 276, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FATAN
1138 { 275, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FASIN
1139 { 274, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FACOS
1140 { 273, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FTAN
1141 { 272, 3, 2, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSINCOS
1142 { 271, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSIN
1143 { 270, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCOS
1144 { 269, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCEIL
1145 { 268, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CLMUL
1146 { 267, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BITREVERSE
1147 { 266, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BSWAP
1148 { 265, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTPOP
1149 { 264, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTLS
1150 { 263, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTLZ_ZERO_POISON
1151 { 262, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTLZ
1152 { 261, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTTZ_ZERO_POISON
1153 { 260, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTTZ
1154 { 259, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 137, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECTOR_COMPRESS
1155 { 258, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STEP_VECTOR
1156 { 257, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SPLAT_VECTOR
1157 { 256, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 133, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SHUFFLE_VECTOR
1158 { 255, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_EXTRACT_VECTOR_ELT
1159 { 254, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 126, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INSERT_VECTOR_ELT
1160 { 253, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 57, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_EXTRACT_SUBVECTOR
1161 { 252, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 62, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INSERT_SUBVECTOR
1162 { 251, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VSCALE
1163 { 250, 3, 0, 0, 0, 0, 0, MSP430OpInfoBase + 123, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BRJT
1164 { 249, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BR
1165 { 248, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LLROUND
1166 { 247, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LROUND
1167 { 246, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ABS
1168 { 245, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMAX
1169 { 244, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMIN
1170 { 243, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMAX
1171 { 242, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMIN
1172 { 241, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTRMASK
1173 { 240, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTR_ADD
1174 { 239, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SET_ROUNDING
1175 { 238, 1, 1, 0, 0, 0, 0, MSP430OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GET_ROUNDING
1176 { 237, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_RESET_FPMODE
1177 { 236, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SET_FPMODE
1178 { 235, 1, 1, 0, 0, 0, 0, MSP430OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GET_FPMODE
1179 { 234, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_RESET_FPENV
1180 { 233, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SET_FPENV
1181 { 232, 1, 1, 0, 0, 0, 0, MSP430OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GET_FPENV
1182 { 231, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXIMUMNUM
1183 { 230, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINIMUMNUM
1184 { 229, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXIMUM
1185 { 228, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINIMUM
1186 { 227, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXNUM_IEEE
1187 { 226, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINNUM_IEEE
1188 { 225, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXNUM
1189 { 224, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINNUM
1190 { 223, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCANONICALIZE
1191 { 222, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 97, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_IS_FPCLASS
1192 { 221, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCOPYSIGN
1193 { 220, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FABS
1194 { 219, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOUI_SAT
1195 { 218, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOSI_SAT
1196 { 217, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UITOFP
1197 { 216, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SITOFP
1198 { 215, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOUI
1199 { 214, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOSI
1200 { 213, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTRUNC
1201 { 212, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPEXT
1202 { 211, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FNEG
1203 { 210, 3, 2, 0, 0, 0, 0, MSP430OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FFREXP
1204 { 209, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLDEXP
1205 { 208, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLOG10
1206 { 207, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLOG2
1207 { 206, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLOG
1208 { 205, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FEXP10
1209 { 204, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FEXP2
1210 { 203, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FEXP
1211 { 202, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPOWI
1212 { 201, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPOW
1213 { 200, 3, 2, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMODF
1214 { 199, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FREM
1215 { 198, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FDIV
1216 { 197, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAD
1217 { 196, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMA
1218 { 195, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMUL
1219 { 194, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSUB
1220 { 193, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FADD
1221 { 192, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIVFIXSAT
1222 { 191, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIVFIXSAT
1223 { 190, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIVFIX
1224 { 189, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIVFIX
1225 { 188, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULFIXSAT
1226 { 187, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULFIXSAT
1227 { 186, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULFIX
1228 { 185, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULFIX
1229 { 184, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSHLSAT
1230 { 183, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USHLSAT
1231 { 182, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSUBSAT
1232 { 181, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USUBSAT
1233 { 180, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SADDSAT
1234 { 179, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UADDSAT
1235 { 178, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULH
1236 { 177, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULH
1237 { 176, 4, 2, 0, 0, 0, 0, MSP430OpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULO
1238 { 175, 4, 2, 0, 0, 0, 0, MSP430OpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULO
1239 { 174, 5, 2, 0, 0, 0, 0, MSP430OpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSUBE
1240 { 173, 4, 2, 0, 0, 0, 0, MSP430OpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSUBO
1241 { 172, 5, 2, 0, 0, 0, 0, MSP430OpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SADDE
1242 { 171, 4, 2, 0, 0, 0, 0, MSP430OpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SADDO
1243 { 170, 5, 2, 0, 0, 0, 0, MSP430OpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USUBE
1244 { 169, 4, 2, 0, 0, 0, 0, MSP430OpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USUBO
1245 { 168, 5, 2, 0, 0, 0, 0, MSP430OpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UADDE
1246 { 167, 4, 2, 0, 0, 0, 0, MSP430OpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UADDO
1247 { 166, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SELECT
1248 { 165, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 111, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UCMP
1249 { 164, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 111, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SCMP
1250 { 163, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCMP
1251 { 162, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ICMP
1252 { 161, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ROTL
1253 { 160, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ROTR
1254 { 159, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 103, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSHR
1255 { 158, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 103, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSHL
1256 { 157, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASHR
1257 { 156, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LSHR
1258 { 155, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SHL
1259 { 154, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ZEXT
1260 { 153, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SEXT_INREG
1261 { 152, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SEXT
1262 { 151, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 97, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VAARG
1263 { 150, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VASTART
1264 { 149, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCONSTANT
1265 { 148, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONSTANT
1266 { 147, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC_USAT_U
1267 { 146, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC_SSAT_U
1268 { 145, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC_SSAT_S
1269 { 144, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC
1270 { 143, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ANYEXT
1271 { 142, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
1272 { 141, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_INTRINSIC_CONVERGENT
1273 { 140, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_W_SIDE_EFFECTS
1274 { 139, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC
1275 { 138, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INVOKE_REGION_START
1276 { 137, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BRINDIRECT
1277 { 136, 2, 0, 0, 0, 0, 0, MSP430OpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BRCOND
1278 { 135, 4, 0, 0, 0, 0, 0, MSP430OpInfoBase + 93, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PREFETCH
1279 { 134, 2, 0, 0, 0, 0, 0, MSP430OpInfoBase + 20, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FENCE
1280 { 133, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_USUB_SAT
1281 { 132, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_USUB_COND
1282 { 131, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UDEC_WRAP
1283 { 130, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UINC_WRAP
1284 { 129, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMINIMUMNUM
1285 { 128, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMAXIMUMNUM
1286 { 127, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMINIMUM
1287 { 126, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMAXIMUM
1288 { 125, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMIN
1289 { 124, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMAX
1290 { 123, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FSUB
1291 { 122, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FADD
1292 { 121, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UMIN
1293 { 120, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UMAX
1294 { 119, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_MIN
1295 { 118, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_MAX
1296 { 117, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_XOR
1297 { 116, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_OR
1298 { 115, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_NAND
1299 { 114, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_AND
1300 { 113, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_SUB
1301 { 112, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_ADD
1302 { 111, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_XCHG
1303 { 110, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMIC_CMPXCHG
1304 { 109, 5, 2, 0, 0, 0, 0, MSP430OpInfoBase + 81, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
1305 { 108, 5, 1, 0, 0, 0, 0, MSP430OpInfoBase + 76, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_STORE
1306 { 107, 2, 0, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTRUNCSTORE
1307 { 106, 2, 0, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STORE
1308 { 105, 5, 2, 0, 0, 0, 0, MSP430OpInfoBase + 71, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_ZEXTLOAD
1309 { 104, 5, 2, 0, 0, 0, 0, MSP430OpInfoBase + 71, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_SEXTLOAD
1310 { 103, 5, 2, 0, 0, 0, 0, MSP430OpInfoBase + 71, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_LOAD
1311 { 102, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPEXTLOAD
1312 { 101, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ZEXTLOAD
1313 { 100, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SEXTLOAD
1314 { 99, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LOAD
1315 { 98, 1, 1, 0, 0, 0, 0, MSP430OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_READSTEADYCOUNTER
1316 { 97, 1, 1, 0, 0, 0, 0, MSP430OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_READCYCLECOUNTER
1317 { 96, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_ROUNDEVEN
1318 { 95, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_LLRINT
1319 { 94, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_LRINT
1320 { 93, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_ROUND
1321 { 92, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_TRUNC
1322 { 91, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 68, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_FPTRUNC_ROUND
1323 { 90, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONSTANT_FOLD_BARRIER
1324 { 89, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FREEZE
1325 { 88, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BITCAST
1326 { 87, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTTOPTR
1327 { 86, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTRTOINT
1328 { 85, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONCAT_VECTORS
1329 { 84, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BUILD_VECTOR_TRUNC
1330 { 83, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BUILD_VECTOR
1331 { 82, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MERGE_VALUES
1332 { 81, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 62, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INSERT
1333 { 80, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UNMERGE_VALUES
1334 { 79, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 57, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_EXTRACT
1335 { 78, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONSTANT_POOL
1336 { 77, 5, 1, 0, 0, 0, 0, MSP430OpInfoBase + 52, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTRAUTH_GLOBAL_VALUE
1337 { 76, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GLOBAL_VALUE
1338 { 75, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FRAME_INDEX
1339 { 74, 1, 1, 0, 0, 0, 0, MSP430OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PHI
1340 { 73, 1, 1, 0, 0, 0, 0, MSP430OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_IMPLICIT_DEF
1341 { 72, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SAVGCEIL
1342 { 71, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SAVGFLOOR
1343 { 70, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UAVGCEIL
1344 { 69, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UAVGFLOOR
1345 { 68, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ABDU
1346 { 67, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ABDS
1347 { 66, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_XOR
1348 { 65, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_OR
1349 { 64, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_AND
1350 { 63, 4, 2, 0, 0, 0, 0, MSP430OpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIVREM
1351 { 62, 4, 2, 0, 0, 0, 0, MSP430OpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIVREM
1352 { 61, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UREM
1353 { 60, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SREM
1354 { 59, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIV
1355 { 58, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIV
1356 { 57, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MUL
1357 { 56, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SUB
1358 { 55, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ADD
1359 { 54, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASSERT_ALIGN
1360 { 53, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASSERT_ZEXT
1361 { 52, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASSERT_SEXT
1362 { 51, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_GLUE
1363 { 50, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_LOOP
1364 { 49, 1, 1, 0, 0, 0, 0, MSP430OpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_ANCHOR
1365 { 48, 1, 1, 0, 0, 0, 0, MSP430OpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_ENTRY
1366 { 47, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RELOC_NONE
1367 { 46, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JUMP_TABLE_DEBUG_INFO
1368 { 45, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMBARRIER
1369 { 44, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FAKE_USE
1370 { 43, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ICALL_BRANCH_FUNNEL
1371 { 42, 3, 0, 0, 0, 0, 0, MSP430OpInfoBase + 36, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_14315
1372 { 41, 2, 0, 0, 0, 0, 0, MSP430OpInfoBase + 34, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_14314
1373 { 40, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_TAIL_CALL
1374 { 39, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_FUNCTION_EXIT
1375 { 38, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_RET
1376 { 37, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_FUNCTION_ENTER
1377 { 36, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_OP
1378 { 35, 1, 1, 0, 0, 0, 0, MSP430OpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FAULTING_OP
1379 { 34, 2, 0, 0, 0, 0, 0, MSP430OpInfoBase + 32, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_ESCAPE
1380 { 33, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STATEPOINT
1381 { 32, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 29, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_14313
1382 { 31, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PREALLOCATED_SETUP
1383 { 30, 1, 1, 0, 0, 0, 0, MSP430OpInfoBase + 28, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_13978
1384 { 29, 6, 1, 0, 0, 0, 0, MSP430OpInfoBase + 22, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHPOINT
1385 { 28, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FENTRY_CALL
1386 { 27, 2, 0, 0, 0, 0, 0, MSP430OpInfoBase + 20, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STACKMAP
1387 { 26, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 18, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARITH_FENCE
1388 { 25, 4, 0, 0, 0, 0, 0, MSP430OpInfoBase + 14, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PSEUDO_PROBE
1389 { 24, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LIFETIME_END
1390 { 23, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LIFETIME_START
1391 { 22, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BUNDLE
1392 { 21, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 11, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_LANEMASK
1393 { 20, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY
1394 { 19, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REG_SEQUENCE
1395 { 18, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_LABEL
1396 { 17, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_PHI
1397 { 16, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_INSTR_REF
1398 { 15, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_VALUE_LIST
1399 { 14, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_VALUE
1400 { 13, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_TO_REGCLASS
1401 { 12, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBREG_TO_REG
1402 { 11, 1, 1, 0, 0, 0, 0, MSP430OpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INIT_UNDEF
1403 { 10, 1, 1, 0, 0, 0, 0, MSP430OpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // IMPLICIT_DEF
1404 { 9, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 5, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INSERT_SUBREG
1405 { 8, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTRACT_SUBREG
1406 { 7, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // KILL
1407 { 6, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ANNOTATION_LABEL
1408 { 5, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GC_LABEL
1409 { 4, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EH_LABEL
1410 { 3, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CFI_INSTRUCTION
1411 { 2, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INLINEASM_BR
1412 { 1, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INLINEASM
1413 { 0, 1, 1, 0, 0, 0, 0, MSP430OpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PHI
1414 }, {
1415 /* 0 */
1416 /* 0 */ MSP430::SR,
1417 /* 1 */ MSP430::SR, MSP430::SR,
1418 /* 3 */ MSP430::SP, MSP430::SR,
1419 /* 5 */ MSP430::SP, MSP430::SP, MSP430::SR,
1420 /* 8 */ MSP430::SP, MSP430::R11, MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15, MSP430::SR,
1421 /* 15 */ MSP430::SP, MSP430::SP,
1422 }, {
1423 0
1424 }, {
1425 /* 0 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1426 /* 1 */
1427 /* 1 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1428 /* 2 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1429 /* 5 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1430 /* 9 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1431 /* 11 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1432 /* 14 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1433 /* 18 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) },
1434 /* 20 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1435 /* 22 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1436 /* 28 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1437 /* 29 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1438 /* 32 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1439 /* 34 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1440 /* 36 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1441 /* 39 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1442 /* 42 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1443 /* 45 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1444 /* 49 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1445 /* 50 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1446 /* 52 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1447 /* 57 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1448 /* 60 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1449 /* 62 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1450 /* 66 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1451 /* 68 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1452 /* 71 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1453 /* 76 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1454 /* 81 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1455 /* 86 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1456 /* 90 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1457 /* 93 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_2, 0 },
1458 /* 97 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1459 /* 100 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1460 /* 103 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1461 /* 107 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1462 /* 111 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1463 /* 114 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1464 /* 119 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1465 /* 123 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1466 /* 126 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
1467 /* 130 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
1468 /* 133 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1469 /* 137 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1470 /* 141 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1471 /* 143 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1472 /* 147 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1473 /* 151 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1474 /* 154 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1475 /* 157 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1476 /* 161 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 },
1477 /* 164 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1478 /* 167 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1479 /* 170 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1480 /* 173 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1481 /* 177 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 },
1482 /* 180 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(1) },
1483 /* 184 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1484 /* 187 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1485 /* 190 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1486 /* 193 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1487 /* 196 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1488 /* 200 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 },
1489 /* 203 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(1) },
1490 /* 207 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1491 /* 210 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1492 /* 212 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1493 /* 215 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 },
1494 /* 217 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1495 /* 219 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1496 /* 221 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1497 /* 223 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1498 /* 226 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 },
1499 /* 228 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1500 /* 230 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1501 /* 232 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 },
1502 /* 233 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(1) },
1503 /* 236 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(1) },
1504 /* 239 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1505 /* 241 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1506 /* 242 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
1507 /* 244 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
1508 /* 246 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1509 /* 250 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1510 /* 254 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1511 /* 257 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1512 }
1513};
1514
1515
1516#ifdef __GNUC__
1517#pragma GCC diagnostic push
1518#pragma GCC diagnostic ignored "-Woverlength-strings"
1519#endif
1520extern const char MSP430InstrNameData[] = {
1521 /* 0 */ "G_FLOG10\000"
1522 /* 9 */ "G_FEXP10\000"
1523 /* 18 */ "G_FLOG2\000"
1524 /* 26 */ "G_FATAN2\000"
1525 /* 35 */ "G_FEXP2\000"
1526 /* 43 */ "Sra16\000"
1527 /* 49 */ "Rrcl16\000"
1528 /* 56 */ "Shl16\000"
1529 /* 62 */ "Srl16\000"
1530 /* 68 */ "Select16\000"
1531 /* 77 */ "Sra8\000"
1532 /* 82 */ "Rrcl8\000"
1533 /* 88 */ "Shl8\000"
1534 /* 93 */ "Srl8\000"
1535 /* 98 */ "MOVZX16rm8\000"
1536 /* 109 */ "MOVZX16rr8\000"
1537 /* 120 */ "Select8\000"
1538 /* 128 */ "G_FMA\000"
1539 /* 134 */ "G_STRICT_FMA\000"
1540 /* 147 */ "G_FSUB\000"
1541 /* 154 */ "G_STRICT_FSUB\000"
1542 /* 168 */ "G_ATOMICRMW_FSUB\000"
1543 /* 185 */ "G_SUB\000"
1544 /* 191 */ "G_ATOMICRMW_SUB\000"
1545 /* 207 */ "JCC\000"
1546 /* 211 */ "G_INTRINSIC\000"
1547 /* 223 */ "G_FPTRUNC\000"
1548 /* 233 */ "G_INTRINSIC_TRUNC\000"
1549 /* 251 */ "G_TRUNC\000"
1550 /* 259 */ "G_BUILD_VECTOR_TRUNC\000"
1551 /* 280 */ "G_DYN_STACKALLOC\000"
1552 /* 297 */ "G_FMAD\000"
1553 /* 304 */ "G_FPEXTLOAD\000"
1554 /* 316 */ "G_INDEXED_SEXTLOAD\000"
1555 /* 335 */ "G_SEXTLOAD\000"
1556 /* 346 */ "G_INDEXED_ZEXTLOAD\000"
1557 /* 365 */ "G_ZEXTLOAD\000"
1558 /* 376 */ "G_INDEXED_LOAD\000"
1559 /* 391 */ "G_LOAD\000"
1560 /* 398 */ "G_VECREDUCE_FADD\000"
1561 /* 415 */ "G_FADD\000"
1562 /* 422 */ "G_VECREDUCE_SEQ_FADD\000"
1563 /* 443 */ "G_STRICT_FADD\000"
1564 /* 457 */ "G_ATOMICRMW_FADD\000"
1565 /* 474 */ "G_VECREDUCE_ADD\000"
1566 /* 490 */ "G_ADD\000"
1567 /* 496 */ "G_PTR_ADD\000"
1568 /* 506 */ "G_ATOMICRMW_ADD\000"
1569 /* 522 */ "G_ATOMICRMW_NAND\000"
1570 /* 539 */ "G_VECREDUCE_AND\000"
1571 /* 555 */ "G_AND\000"
1572 /* 561 */ "G_ATOMICRMW_AND\000"
1573 /* 577 */ "LIFETIME_END\000"
1574 /* 590 */ "G_BRCOND\000"
1575 /* 599 */ "G_ATOMICRMW_USUB_COND\000"
1576 /* 621 */ "G_LLROUND\000"
1577 /* 631 */ "G_LROUND\000"
1578 /* 640 */ "G_INTRINSIC_ROUND\000"
1579 /* 658 */ "G_INTRINSIC_FPTRUNC_ROUND\000"
1580 /* 684 */ "LOAD_STACK_GUARD\000"
1581 /* 701 */ "PSEUDO_PROBE\000"
1582 /* 714 */ "G_SSUBE\000"
1583 /* 722 */ "G_USUBE\000"
1584 /* 730 */ "G_FENCE\000"
1585 /* 738 */ "ARITH_FENCE\000"
1586 /* 750 */ "REG_SEQUENCE\000"
1587 /* 763 */ "G_SADDE\000"
1588 /* 771 */ "G_UADDE\000"
1589 /* 779 */ "G_GET_FPMODE\000"
1590 /* 792 */ "G_RESET_FPMODE\000"
1591 /* 807 */ "G_SET_FPMODE\000"
1592 /* 820 */ "G_FMINNUM_IEEE\000"
1593 /* 835 */ "G_FMAXNUM_IEEE\000"
1594 /* 850 */ "G_VSCALE\000"
1595 /* 859 */ "G_JUMP_TABLE\000"
1596 /* 872 */ "BUNDLE\000"
1597 /* 879 */ "G_MEMSET_INLINE\000"
1598 /* 895 */ "G_MEMCPY_INLINE\000"
1599 /* 911 */ "RELOC_NONE\000"
1600 /* 922 */ "LOCAL_ESCAPE\000"
1601 /* 935 */ "G_FPTRUNCSTORE\000"
1602 /* 950 */ "G_STACKRESTORE\000"
1603 /* 965 */ "G_INDEXED_STORE\000"
1604 /* 981 */ "G_STORE\000"
1605 /* 989 */ "G_BITREVERSE\000"
1606 /* 1002 */ "FAKE_USE\000"
1607 /* 1011 */ "DBG_VALUE\000"
1608 /* 1021 */ "G_GLOBAL_VALUE\000"
1609 /* 1036 */ "G_PTRAUTH_GLOBAL_VALUE\000"
1610 /* 1059 */ "CONVERGENCECTRL_GLUE\000"
1611 /* 1080 */ "G_STACKSAVE\000"
1612 /* 1092 */ "G_MEMMOVE\000"
1613 /* 1102 */ "G_FREEZE\000"
1614 /* 1111 */ "G_FCANONICALIZE\000"
1615 /* 1127 */ "G_FMODF\000"
1616 /* 1135 */ "INIT_UNDEF\000"
1617 /* 1146 */ "G_IMPLICIT_DEF\000"
1618 /* 1161 */ "DBG_INSTR_REF\000"
1619 /* 1175 */ "G_FNEG\000"
1620 /* 1182 */ "EXTRACT_SUBREG\000"
1621 /* 1197 */ "INSERT_SUBREG\000"
1622 /* 1211 */ "G_SEXT_INREG\000"
1623 /* 1224 */ "SUBREG_TO_REG\000"
1624 /* 1238 */ "G_ATOMIC_CMPXCHG\000"
1625 /* 1255 */ "G_ATOMICRMW_XCHG\000"
1626 /* 1272 */ "G_GET_ROUNDING\000"
1627 /* 1287 */ "G_SET_ROUNDING\000"
1628 /* 1302 */ "G_FLOG\000"
1629 /* 1309 */ "G_VAARG\000"
1630 /* 1317 */ "PREALLOCATED_ARG\000"
1631 /* 1334 */ "G_PREFETCH\000"
1632 /* 1345 */ "G_SMULH\000"
1633 /* 1353 */ "G_UMULH\000"
1634 /* 1361 */ "G_FTANH\000"
1635 /* 1369 */ "G_FSINH\000"
1636 /* 1377 */ "G_FCOSH\000"
1637 /* 1385 */ "DBG_PHI\000"
1638 /* 1393 */ "G_FPTOSI\000"
1639 /* 1402 */ "RETI\000"
1640 /* 1407 */ "G_FPTOUI\000"
1641 /* 1416 */ "G_FPOWI\000"
1642 /* 1424 */ "COPY_LANEMASK\000"
1643 /* 1438 */ "G_PTRMASK\000"
1644 /* 1448 */ "GC_LABEL\000"
1645 /* 1457 */ "DBG_LABEL\000"
1646 /* 1467 */ "EH_LABEL\000"
1647 /* 1476 */ "ANNOTATION_LABEL\000"
1648 /* 1493 */ "ICALL_BRANCH_FUNNEL\000"
1649 /* 1513 */ "G_FSHL\000"
1650 /* 1520 */ "G_SHL\000"
1651 /* 1526 */ "G_FCEIL\000"
1652 /* 1534 */ "G_SAVGCEIL\000"
1653 /* 1545 */ "G_UAVGCEIL\000"
1654 /* 1556 */ "PATCHABLE_TAIL_CALL\000"
1655 /* 1576 */ "PATCHABLE_TYPED_EVENT_CALL\000"
1656 /* 1603 */ "PATCHABLE_EVENT_CALL\000"
1657 /* 1624 */ "FENTRY_CALL\000"
1658 /* 1636 */ "KILL\000"
1659 /* 1641 */ "G_CONSTANT_POOL\000"
1660 /* 1657 */ "G_ROTL\000"
1661 /* 1664 */ "G_VECREDUCE_FMUL\000"
1662 /* 1681 */ "G_FMUL\000"
1663 /* 1688 */ "G_VECREDUCE_SEQ_FMUL\000"
1664 /* 1709 */ "G_STRICT_FMUL\000"
1665 /* 1723 */ "G_CLMUL\000"
1666 /* 1731 */ "G_VECREDUCE_MUL\000"
1667 /* 1747 */ "G_MUL\000"
1668 /* 1753 */ "G_FREM\000"
1669 /* 1760 */ "G_STRICT_FREM\000"
1670 /* 1774 */ "G_SREM\000"
1671 /* 1781 */ "G_UREM\000"
1672 /* 1788 */ "G_SDIVREM\000"
1673 /* 1798 */ "G_UDIVREM\000"
1674 /* 1808 */ "INLINEASM\000"
1675 /* 1818 */ "G_VECREDUCE_FMINIMUM\000"
1676 /* 1839 */ "G_FMINIMUM\000"
1677 /* 1850 */ "G_ATOMICRMW_FMINIMUM\000"
1678 /* 1871 */ "G_VECREDUCE_FMAXIMUM\000"
1679 /* 1892 */ "G_FMAXIMUM\000"
1680 /* 1903 */ "G_ATOMICRMW_FMAXIMUM\000"
1681 /* 1924 */ "G_VECREDUCE_FMINIMUMNUM\000"
1682 /* 1948 */ "G_FMINIMUMNUM\000"
1683 /* 1962 */ "G_ATOMICRMW_FMINIMUMNUM\000"
1684 /* 1986 */ "G_VECREDUCE_FMAXIMUMNUM\000"
1685 /* 2010 */ "G_FMAXIMUMNUM\000"
1686 /* 2024 */ "G_ATOMICRMW_FMAXIMUMNUM\000"
1687 /* 2048 */ "G_FMINNUM\000"
1688 /* 2058 */ "G_FMAXNUM\000"
1689 /* 2068 */ "G_FATAN\000"
1690 /* 2076 */ "G_FTAN\000"
1691 /* 2083 */ "G_INTRINSIC_ROUNDEVEN\000"
1692 /* 2105 */ "G_ASSERT_ALIGN\000"
1693 /* 2120 */ "G_FCOPYSIGN\000"
1694 /* 2132 */ "G_VECREDUCE_FMIN\000"
1695 /* 2149 */ "G_ATOMICRMW_FMIN\000"
1696 /* 2166 */ "G_VECREDUCE_SMIN\000"
1697 /* 2183 */ "G_SMIN\000"
1698 /* 2190 */ "G_VECREDUCE_UMIN\000"
1699 /* 2207 */ "G_UMIN\000"
1700 /* 2214 */ "G_ATOMICRMW_UMIN\000"
1701 /* 2231 */ "G_ATOMICRMW_MIN\000"
1702 /* 2247 */ "G_FASIN\000"
1703 /* 2255 */ "G_FSIN\000"
1704 /* 2262 */ "CFI_INSTRUCTION\000"
1705 /* 2278 */ "G_CTLZ_ZERO_POISON\000"
1706 /* 2297 */ "G_CTTZ_ZERO_POISON\000"
1707 /* 2316 */ "ADJCALLSTACKDOWN\000"
1708 /* 2333 */ "G_SSUBO\000"
1709 /* 2341 */ "G_USUBO\000"
1710 /* 2349 */ "G_SADDO\000"
1711 /* 2357 */ "G_UADDO\000"
1712 /* 2365 */ "JUMP_TABLE_DEBUG_INFO\000"
1713 /* 2387 */ "G_SMULO\000"
1714 /* 2395 */ "G_UMULO\000"
1715 /* 2403 */ "G_BZERO\000"
1716 /* 2411 */ "STACKMAP\000"
1717 /* 2420 */ "G_DEBUGTRAP\000"
1718 /* 2432 */ "G_UBSANTRAP\000"
1719 /* 2444 */ "G_TRAP\000"
1720 /* 2451 */ "G_ATOMICRMW_UDEC_WRAP\000"
1721 /* 2473 */ "G_ATOMICRMW_UINC_WRAP\000"
1722 /* 2495 */ "G_BSWAP\000"
1723 /* 2503 */ "G_SITOFP\000"
1724 /* 2512 */ "G_UITOFP\000"
1725 /* 2521 */ "G_FCMP\000"
1726 /* 2528 */ "G_STRICT_FCMP\000"
1727 /* 2542 */ "G_ICMP\000"
1728 /* 2549 */ "G_SCMP\000"
1729 /* 2556 */ "G_UCMP\000"
1730 /* 2563 */ "JMP\000"
1731 /* 2567 */ "CONVERGENCECTRL_LOOP\000"
1732 /* 2588 */ "G_CTPOP\000"
1733 /* 2596 */ "PATCHABLE_OP\000"
1734 /* 2609 */ "FAULTING_OP\000"
1735 /* 2621 */ "ADJCALLSTACKUP\000"
1736 /* 2636 */ "PREALLOCATED_SETUP\000"
1737 /* 2655 */ "G_FLDEXP\000"
1738 /* 2664 */ "G_STRICT_FLDEXP\000"
1739 /* 2680 */ "G_FEXP\000"
1740 /* 2687 */ "G_FFREXP\000"
1741 /* 2696 */ "G_BR\000"
1742 /* 2701 */ "INLINEASM_BR\000"
1743 /* 2714 */ "G_BLOCK_ADDR\000"
1744 /* 2727 */ "MEMBARRIER\000"
1745 /* 2738 */ "G_CONSTANT_FOLD_BARRIER\000"
1746 /* 2762 */ "PATCHABLE_FUNCTION_ENTER\000"
1747 /* 2787 */ "G_READCYCLECOUNTER\000"
1748 /* 2806 */ "G_READSTEADYCOUNTER\000"
1749 /* 2826 */ "G_READ_REGISTER\000"
1750 /* 2842 */ "G_WRITE_REGISTER\000"
1751 /* 2859 */ "G_ASHR\000"
1752 /* 2866 */ "G_FSHR\000"
1753 /* 2873 */ "G_LSHR\000"
1754 /* 2880 */ "CONVERGENCECTRL_ANCHOR\000"
1755 /* 2903 */ "G_FFLOOR\000"
1756 /* 2912 */ "G_SAVGFLOOR\000"
1757 /* 2924 */ "G_UAVGFLOOR\000"
1758 /* 2936 */ "G_EXTRACT_SUBVECTOR\000"
1759 /* 2956 */ "G_INSERT_SUBVECTOR\000"
1760 /* 2975 */ "G_BUILD_VECTOR\000"
1761 /* 2990 */ "G_SHUFFLE_VECTOR\000"
1762 /* 3007 */ "G_STEP_VECTOR\000"
1763 /* 3021 */ "G_SPLAT_VECTOR\000"
1764 /* 3036 */ "G_VECREDUCE_XOR\000"
1765 /* 3052 */ "G_XOR\000"
1766 /* 3058 */ "G_ATOMICRMW_XOR\000"
1767 /* 3074 */ "G_VECREDUCE_OR\000"
1768 /* 3089 */ "G_OR\000"
1769 /* 3094 */ "G_ATOMICRMW_OR\000"
1770 /* 3109 */ "G_ROTR\000"
1771 /* 3116 */ "G_INTTOPTR\000"
1772 /* 3127 */ "G_FABS\000"
1773 /* 3134 */ "G_ABS\000"
1774 /* 3140 */ "G_ABDS\000"
1775 /* 3147 */ "G_UNMERGE_VALUES\000"
1776 /* 3164 */ "G_MERGE_VALUES\000"
1777 /* 3179 */ "G_CTLS\000"
1778 /* 3186 */ "G_FACOS\000"
1779 /* 3194 */ "G_FCOS\000"
1780 /* 3201 */ "G_FSINCOS\000"
1781 /* 3211 */ "G_STRICT_FCMPS\000"
1782 /* 3226 */ "G_CONCAT_VECTORS\000"
1783 /* 3243 */ "COPY_TO_REGCLASS\000"
1784 /* 3260 */ "G_IS_FPCLASS\000"
1785 /* 3273 */ "G_ATOMIC_CMPXCHG_WITH_SUCCESS\000"
1786 /* 3303 */ "G_VECTOR_COMPRESS\000"
1787 /* 3321 */ "G_INTRINSIC_W_SIDE_EFFECTS\000"
1788 /* 3348 */ "G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS\000"
1789 /* 3386 */ "G_TRUNC_SSAT_S\000"
1790 /* 3401 */ "G_SSUBSAT\000"
1791 /* 3411 */ "G_USUBSAT\000"
1792 /* 3421 */ "G_SADDSAT\000"
1793 /* 3431 */ "G_UADDSAT\000"
1794 /* 3441 */ "G_SSHLSAT\000"
1795 /* 3451 */ "G_USHLSAT\000"
1796 /* 3461 */ "G_SMULFIXSAT\000"
1797 /* 3474 */ "G_UMULFIXSAT\000"
1798 /* 3487 */ "G_SDIVFIXSAT\000"
1799 /* 3500 */ "G_UDIVFIXSAT\000"
1800 /* 3513 */ "G_ATOMICRMW_USUB_SAT\000"
1801 /* 3534 */ "G_FPTOSI_SAT\000"
1802 /* 3547 */ "G_FPTOUI_SAT\000"
1803 /* 3560 */ "G_EXTRACT\000"
1804 /* 3570 */ "G_SELECT\000"
1805 /* 3579 */ "G_BRINDIRECT\000"
1806 /* 3592 */ "PATCHABLE_RET\000"
1807 /* 3606 */ "G_MEMSET\000"
1808 /* 3615 */ "PATCHABLE_FUNCTION_EXIT\000"
1809 /* 3639 */ "G_BRJT\000"
1810 /* 3646 */ "G_EXTRACT_VECTOR_ELT\000"
1811 /* 3667 */ "G_INSERT_VECTOR_ELT\000"
1812 /* 3687 */ "G_FCONSTANT\000"
1813 /* 3699 */ "G_CONSTANT\000"
1814 /* 3710 */ "G_INTRINSIC_CONVERGENT\000"
1815 /* 3733 */ "STATEPOINT\000"
1816 /* 3744 */ "PATCHPOINT\000"
1817 /* 3755 */ "G_PTRTOINT\000"
1818 /* 3766 */ "G_FRINT\000"
1819 /* 3774 */ "G_INTRINSIC_LLRINT\000"
1820 /* 3793 */ "G_INTRINSIC_LRINT\000"
1821 /* 3811 */ "G_FNEARBYINT\000"
1822 /* 3824 */ "G_VASTART\000"
1823 /* 3834 */ "LIFETIME_START\000"
1824 /* 3849 */ "G_INVOKE_REGION_START\000"
1825 /* 3871 */ "G_INSERT\000"
1826 /* 3880 */ "G_FSQRT\000"
1827 /* 3888 */ "G_STRICT_FSQRT\000"
1828 /* 3903 */ "G_BITCAST\000"
1829 /* 3913 */ "G_ADDRSPACE_CAST\000"
1830 /* 3930 */ "DBG_VALUE_LIST\000"
1831 /* 3945 */ "G_FPEXT\000"
1832 /* 3953 */ "G_SEXT\000"
1833 /* 3960 */ "G_ASSERT_SEXT\000"
1834 /* 3974 */ "G_ANYEXT\000"
1835 /* 3983 */ "G_ZEXT\000"
1836 /* 3990 */ "G_ASSERT_ZEXT\000"
1837 /* 4004 */ "G_ABDU\000"
1838 /* 4011 */ "G_TRUNC_SSAT_U\000"
1839 /* 4026 */ "G_TRUNC_USAT_U\000"
1840 /* 4041 */ "G_FDIV\000"
1841 /* 4048 */ "G_STRICT_FDIV\000"
1842 /* 4062 */ "G_SDIV\000"
1843 /* 4069 */ "G_UDIV\000"
1844 /* 4076 */ "G_GET_FPENV\000"
1845 /* 4088 */ "G_RESET_FPENV\000"
1846 /* 4102 */ "G_SET_FPENV\000"
1847 /* 4114 */ "G_FPOW\000"
1848 /* 4121 */ "G_VECREDUCE_FMAX\000"
1849 /* 4138 */ "G_ATOMICRMW_FMAX\000"
1850 /* 4155 */ "G_VECREDUCE_SMAX\000"
1851 /* 4172 */ "G_SMAX\000"
1852 /* 4179 */ "G_VECREDUCE_UMAX\000"
1853 /* 4196 */ "G_UMAX\000"
1854 /* 4203 */ "G_ATOMICRMW_UMAX\000"
1855 /* 4220 */ "G_ATOMICRMW_MAX\000"
1856 /* 4236 */ "G_FRAME_INDEX\000"
1857 /* 4250 */ "G_SBFX\000"
1858 /* 4257 */ "G_UBFX\000"
1859 /* 4264 */ "G_SMULFIX\000"
1860 /* 4274 */ "G_UMULFIX\000"
1861 /* 4284 */ "G_SDIVFIX\000"
1862 /* 4294 */ "G_UDIVFIX\000"
1863 /* 4304 */ "G_MEMCPY\000"
1864 /* 4313 */ "COPY\000"
1865 /* 4318 */ "CONVERGENCECTRL_ENTRY\000"
1866 /* 4340 */ "G_CTLZ\000"
1867 /* 4347 */ "G_CTTZ\000"
1868 /* 4354 */ "PUSH16c\000"
1869 /* 4362 */ "SUB16mc\000"
1870 /* 4370 */ "SUBC16mc\000"
1871 /* 4379 */ "ADDC16mc\000"
1872 /* 4388 */ "BIC16mc\000"
1873 /* 4396 */ "DADD16mc\000"
1874 /* 4405 */ "AND16mc\000"
1875 /* 4413 */ "CMP16mc\000"
1876 /* 4421 */ "XOR16mc\000"
1877 /* 4429 */ "BIS16mc\000"
1878 /* 4437 */ "BIT16mc\000"
1879 /* 4445 */ "MOV16mc\000"
1880 /* 4453 */ "SUB8mc\000"
1881 /* 4460 */ "SUBC8mc\000"
1882 /* 4468 */ "ADDC8mc\000"
1883 /* 4476 */ "BIC8mc\000"
1884 /* 4483 */ "DADD8mc\000"
1885 /* 4491 */ "AND8mc\000"
1886 /* 4498 */ "CMP8mc\000"
1887 /* 4505 */ "XOR8mc\000"
1888 /* 4512 */ "BIS8mc\000"
1889 /* 4519 */ "BIT8mc\000"
1890 /* 4526 */ "MOV8mc\000"
1891 /* 4533 */ "SUB16rc\000"
1892 /* 4541 */ "SUBC16rc\000"
1893 /* 4550 */ "ADDC16rc\000"
1894 /* 4559 */ "BIC16rc\000"
1895 /* 4567 */ "DADD16rc\000"
1896 /* 4576 */ "AND16rc\000"
1897 /* 4584 */ "CMP16rc\000"
1898 /* 4592 */ "XOR16rc\000"
1899 /* 4600 */ "BIS16rc\000"
1900 /* 4608 */ "BIT16rc\000"
1901 /* 4616 */ "MOV16rc\000"
1902 /* 4624 */ "SUB8rc\000"
1903 /* 4631 */ "SUBC8rc\000"
1904 /* 4639 */ "ADDC8rc\000"
1905 /* 4647 */ "BIC8rc\000"
1906 /* 4654 */ "DADD8rc\000"
1907 /* 4662 */ "AND8rc\000"
1908 /* 4669 */ "CMP8rc\000"
1909 /* 4676 */ "XOR8rc\000"
1910 /* 4683 */ "BIS8rc\000"
1911 /* 4690 */ "BIT8rc\000"
1912 /* 4697 */ "MOV8rc\000"
1913 /* 4704 */ "ADDframe\000"
1914 /* 4713 */ "PUSH16i\000"
1915 /* 4721 */ "Bi\000"
1916 /* 4724 */ "CALLi\000"
1917 /* 4730 */ "SUB16mi\000"
1918 /* 4738 */ "SUBC16mi\000"
1919 /* 4747 */ "ADDC16mi\000"
1920 /* 4756 */ "BIC16mi\000"
1921 /* 4764 */ "DADD16mi\000"
1922 /* 4773 */ "AND16mi\000"
1923 /* 4781 */ "CMP16mi\000"
1924 /* 4789 */ "XOR16mi\000"
1925 /* 4797 */ "BIS16mi\000"
1926 /* 4805 */ "BIT16mi\000"
1927 /* 4813 */ "MOV16mi\000"
1928 /* 4821 */ "SUB8mi\000"
1929 /* 4828 */ "SUBC8mi\000"
1930 /* 4836 */ "ADDC8mi\000"
1931 /* 4844 */ "BIC8mi\000"
1932 /* 4851 */ "DADD8mi\000"
1933 /* 4859 */ "AND8mi\000"
1934 /* 4866 */ "CMP8mi\000"
1935 /* 4873 */ "XOR8mi\000"
1936 /* 4880 */ "BIS8mi\000"
1937 /* 4887 */ "BIT8mi\000"
1938 /* 4894 */ "MOV8mi\000"
1939 /* 4901 */ "SUB16ri\000"
1940 /* 4909 */ "SUBC16ri\000"
1941 /* 4918 */ "ADDC16ri\000"
1942 /* 4927 */ "BIC16ri\000"
1943 /* 4935 */ "DADD16ri\000"
1944 /* 4944 */ "AND16ri\000"
1945 /* 4952 */ "CMP16ri\000"
1946 /* 4960 */ "XOR16ri\000"
1947 /* 4968 */ "BIS16ri\000"
1948 /* 4976 */ "BIT16ri\000"
1949 /* 4984 */ "MOV16ri\000"
1950 /* 4992 */ "SUB8ri\000"
1951 /* 4999 */ "SUBC8ri\000"
1952 /* 5007 */ "ADDC8ri\000"
1953 /* 5015 */ "BIC8ri\000"
1954 /* 5022 */ "DADD8ri\000"
1955 /* 5030 */ "AND8ri\000"
1956 /* 5037 */ "CMP8ri\000"
1957 /* 5044 */ "XOR8ri\000"
1958 /* 5051 */ "BIS8ri\000"
1959 /* 5058 */ "BIT8ri\000"
1960 /* 5065 */ "MOV8ri\000"
1961 /* 5072 */ "RRA16m\000"
1962 /* 5079 */ "SWPB16m\000"
1963 /* 5087 */ "RRC16m\000"
1964 /* 5094 */ "SEXT16m\000"
1965 /* 5102 */ "RRA8m\000"
1966 /* 5108 */ "RRC8m\000"
1967 /* 5114 */ "Bm\000"
1968 /* 5117 */ "CALLm\000"
1969 /* 5123 */ "SUB16mm\000"
1970 /* 5131 */ "SUBC16mm\000"
1971 /* 5140 */ "ADDC16mm\000"
1972 /* 5149 */ "BIC16mm\000"
1973 /* 5157 */ "DADD16mm\000"
1974 /* 5166 */ "AND16mm\000"
1975 /* 5174 */ "CMP16mm\000"
1976 /* 5182 */ "XOR16mm\000"
1977 /* 5190 */ "BIS16mm\000"
1978 /* 5198 */ "BIT16mm\000"
1979 /* 5206 */ "MOV16mm\000"
1980 /* 5214 */ "SUB8mm\000"
1981 /* 5221 */ "SUBC8mm\000"
1982 /* 5229 */ "ADDC8mm\000"
1983 /* 5237 */ "BIC8mm\000"
1984 /* 5244 */ "DADD8mm\000"
1985 /* 5252 */ "AND8mm\000"
1986 /* 5259 */ "CMP8mm\000"
1987 /* 5266 */ "XOR8mm\000"
1988 /* 5273 */ "BIS8mm\000"
1989 /* 5280 */ "BIT8mm\000"
1990 /* 5287 */ "MOV8mm\000"
1991 /* 5294 */ "SUB16rm\000"
1992 /* 5302 */ "SUBC16rm\000"
1993 /* 5311 */ "ADDC16rm\000"
1994 /* 5320 */ "BIC16rm\000"
1995 /* 5328 */ "DADD16rm\000"
1996 /* 5337 */ "AND16rm\000"
1997 /* 5345 */ "CMP16rm\000"
1998 /* 5353 */ "XOR16rm\000"
1999 /* 5361 */ "BIS16rm\000"
2000 /* 5369 */ "BIT16rm\000"
2001 /* 5377 */ "MOV16rm\000"
2002 /* 5385 */ "SUB8rm\000"
2003 /* 5392 */ "SUBC8rm\000"
2004 /* 5400 */ "ADDC8rm\000"
2005 /* 5408 */ "BIC8rm\000"
2006 /* 5415 */ "DADD8rm\000"
2007 /* 5423 */ "AND8rm\000"
2008 /* 5430 */ "CMP8rm\000"
2009 /* 5437 */ "XOR8rm\000"
2010 /* 5444 */ "BIS8rm\000"
2011 /* 5451 */ "BIT8rm\000"
2012 /* 5458 */ "MOV8rm\000"
2013 /* 5465 */ "RRA16n\000"
2014 /* 5472 */ "SWPB16n\000"
2015 /* 5480 */ "RRC16n\000"
2016 /* 5487 */ "SEXT16n\000"
2017 /* 5495 */ "RRA8n\000"
2018 /* 5501 */ "RRC8n\000"
2019 /* 5507 */ "CALLn\000"
2020 /* 5513 */ "SUB16mn\000"
2021 /* 5521 */ "SUBC16mn\000"
2022 /* 5530 */ "ADDC16mn\000"
2023 /* 5539 */ "BIC16mn\000"
2024 /* 5547 */ "DADD16mn\000"
2025 /* 5556 */ "AND16mn\000"
2026 /* 5564 */ "CMP16mn\000"
2027 /* 5572 */ "XOR16mn\000"
2028 /* 5580 */ "BIS16mn\000"
2029 /* 5588 */ "BIT16mn\000"
2030 /* 5596 */ "MOV16mn\000"
2031 /* 5604 */ "SUB8mn\000"
2032 /* 5611 */ "SUBC8mn\000"
2033 /* 5619 */ "ADDC8mn\000"
2034 /* 5627 */ "BIC8mn\000"
2035 /* 5634 */ "DADD8mn\000"
2036 /* 5642 */ "AND8mn\000"
2037 /* 5649 */ "CMP8mn\000"
2038 /* 5656 */ "XOR8mn\000"
2039 /* 5663 */ "BIS8mn\000"
2040 /* 5670 */ "BIT8mn\000"
2041 /* 5677 */ "MOV8mn\000"
2042 /* 5684 */ "SUB16rn\000"
2043 /* 5692 */ "SUBC16rn\000"
2044 /* 5701 */ "ADDC16rn\000"
2045 /* 5710 */ "BIC16rn\000"
2046 /* 5718 */ "DADD16rn\000"
2047 /* 5727 */ "AND16rn\000"
2048 /* 5735 */ "CMP16rn\000"
2049 /* 5743 */ "XOR16rn\000"
2050 /* 5751 */ "BIS16rn\000"
2051 /* 5759 */ "BIT16rn\000"
2052 /* 5767 */ "MOV16rn\000"
2053 /* 5775 */ "SUB8rn\000"
2054 /* 5782 */ "SUBC8rn\000"
2055 /* 5790 */ "ADDC8rn\000"
2056 /* 5798 */ "BIC8rn\000"
2057 /* 5805 */ "DADD8rn\000"
2058 /* 5813 */ "AND8rn\000"
2059 /* 5820 */ "CMP8rn\000"
2060 /* 5827 */ "XOR8rn\000"
2061 /* 5834 */ "BIS8rn\000"
2062 /* 5841 */ "BIT8rn\000"
2063 /* 5848 */ "MOV8rn\000"
2064 /* 5855 */ "RRA16p\000"
2065 /* 5862 */ "SWPB16p\000"
2066 /* 5870 */ "RRC16p\000"
2067 /* 5877 */ "SEXT16p\000"
2068 /* 5885 */ "RRA8p\000"
2069 /* 5891 */ "RRC8p\000"
2070 /* 5897 */ "CALLp\000"
2071 /* 5903 */ "SUB16mp\000"
2072 /* 5911 */ "SUBC16mp\000"
2073 /* 5920 */ "ADDC16mp\000"
2074 /* 5929 */ "BIC16mp\000"
2075 /* 5937 */ "DADD16mp\000"
2076 /* 5946 */ "AND16mp\000"
2077 /* 5954 */ "CMP16mp\000"
2078 /* 5962 */ "XOR16mp\000"
2079 /* 5970 */ "BIS16mp\000"
2080 /* 5978 */ "BIT16mp\000"
2081 /* 5986 */ "SUB8mp\000"
2082 /* 5993 */ "SUBC8mp\000"
2083 /* 6001 */ "ADDC8mp\000"
2084 /* 6009 */ "BIC8mp\000"
2085 /* 6016 */ "DADD8mp\000"
2086 /* 6024 */ "AND8mp\000"
2087 /* 6031 */ "CMP8mp\000"
2088 /* 6038 */ "XOR8mp\000"
2089 /* 6045 */ "BIS8mp\000"
2090 /* 6052 */ "BIT8mp\000"
2091 /* 6059 */ "SUB16rp\000"
2092 /* 6067 */ "SUBC16rp\000"
2093 /* 6076 */ "ADDC16rp\000"
2094 /* 6085 */ "BIC16rp\000"
2095 /* 6093 */ "DADD16rp\000"
2096 /* 6102 */ "AND16rp\000"
2097 /* 6110 */ "CMP16rp\000"
2098 /* 6118 */ "XOR16rp\000"
2099 /* 6126 */ "BIS16rp\000"
2100 /* 6134 */ "BIT16rp\000"
2101 /* 6142 */ "MOV16rp\000"
2102 /* 6150 */ "SUB8rp\000"
2103 /* 6157 */ "SUBC8rp\000"
2104 /* 6165 */ "ADDC8rp\000"
2105 /* 6173 */ "BIC8rp\000"
2106 /* 6180 */ "DADD8rp\000"
2107 /* 6188 */ "AND8rp\000"
2108 /* 6195 */ "CMP8rp\000"
2109 /* 6202 */ "XOR8rp\000"
2110 /* 6209 */ "BIS8rp\000"
2111 /* 6216 */ "BIT8rp\000"
2112 /* 6223 */ "MOV8rp\000"
2113 /* 6230 */ "RRA16r\000"
2114 /* 6237 */ "SWPB16r\000"
2115 /* 6245 */ "RRC16r\000"
2116 /* 6252 */ "PUSH16r\000"
2117 /* 6260 */ "POP16r\000"
2118 /* 6267 */ "SEXT16r\000"
2119 /* 6275 */ "ZEXT16r\000"
2120 /* 6283 */ "RRA8r\000"
2121 /* 6289 */ "RRC8r\000"
2122 /* 6295 */ "PUSH8r\000"
2123 /* 6302 */ "Br\000"
2124 /* 6305 */ "CALLr\000"
2125 /* 6311 */ "SUB16mr\000"
2126 /* 6319 */ "SUBC16mr\000"
2127 /* 6328 */ "ADDC16mr\000"
2128 /* 6337 */ "BIC16mr\000"
2129 /* 6345 */ "DADD16mr\000"
2130 /* 6354 */ "AND16mr\000"
2131 /* 6362 */ "CMP16mr\000"
2132 /* 6370 */ "XOR16mr\000"
2133 /* 6378 */ "BIS16mr\000"
2134 /* 6386 */ "BIT16mr\000"
2135 /* 6394 */ "MOV16mr\000"
2136 /* 6402 */ "SUB8mr\000"
2137 /* 6409 */ "SUBC8mr\000"
2138 /* 6417 */ "ADDC8mr\000"
2139 /* 6425 */ "BIC8mr\000"
2140 /* 6432 */ "DADD8mr\000"
2141 /* 6440 */ "AND8mr\000"
2142 /* 6447 */ "CMP8mr\000"
2143 /* 6454 */ "XOR8mr\000"
2144 /* 6461 */ "BIS8mr\000"
2145 /* 6468 */ "BIT8mr\000"
2146 /* 6475 */ "MOV8mr\000"
2147 /* 6482 */ "SUB16rr\000"
2148 /* 6490 */ "SUBC16rr\000"
2149 /* 6499 */ "ADDC16rr\000"
2150 /* 6508 */ "BIC16rr\000"
2151 /* 6516 */ "DADD16rr\000"
2152 /* 6525 */ "AND16rr\000"
2153 /* 6533 */ "CMP16rr\000"
2154 /* 6541 */ "XOR16rr\000"
2155 /* 6549 */ "BIS16rr\000"
2156 /* 6557 */ "BIT16rr\000"
2157 /* 6565 */ "MOV16rr\000"
2158 /* 6573 */ "SUB8rr\000"
2159 /* 6580 */ "SUBC8rr\000"
2160 /* 6588 */ "ADDC8rr\000"
2161 /* 6596 */ "BIC8rr\000"
2162 /* 6603 */ "DADD8rr\000"
2163 /* 6611 */ "AND8rr\000"
2164 /* 6618 */ "CMP8rr\000"
2165 /* 6625 */ "XOR8rr\000"
2166 /* 6632 */ "BIS8rr\000"
2167 /* 6639 */ "BIT8rr\000"
2168 /* 6646 */ "MOV8rr\000"
2169};
2170#ifdef __GNUC__
2171#pragma GCC diagnostic pop
2172#endif
2173
2174extern const unsigned MSP430InstrNameIndices[] = {
2175 1389U, 1808U, 2701U, 2262U, 1467U, 1448U, 1476U, 1636U,
2176 1182U, 1197U, 1148U, 1135U, 1224U, 3243U, 1011U, 3930U,
2177 1161U, 1385U, 1457U, 750U, 4313U, 1424U, 872U, 3834U,
2178 577U, 701U, 738U, 2411U, 1624U, 3744U, 684U, 2636U,
2179 1317U, 3733U, 922U, 2609U, 2596U, 2762U, 3592U, 3615U,
2180 1556U, 1603U, 1576U, 1493U, 1002U, 2727U, 2365U, 911U,
2181 4318U, 2880U, 2567U, 1059U, 3960U, 3990U, 2105U, 490U,
2182 185U, 1747U, 4062U, 4069U, 1774U, 1781U, 1788U, 1798U,
2183 555U, 3089U, 3052U, 3140U, 4004U, 2924U, 1545U, 2912U,
2184 1534U, 1146U, 1387U, 4236U, 1021U, 1036U, 1641U, 3560U,
2185 3147U, 3871U, 3164U, 2975U, 259U, 3226U, 3755U, 3116U,
2186 3903U, 1102U, 2738U, 658U, 233U, 640U, 3793U, 3774U,
2187 2083U, 2787U, 2806U, 391U, 335U, 365U, 304U, 376U,
2188 316U, 346U, 981U, 935U, 965U, 3273U, 1238U, 1255U,
2189 506U, 191U, 561U, 522U, 3094U, 3058U, 4220U, 2231U,
2190 4203U, 2214U, 457U, 168U, 4138U, 2149U, 1903U, 1850U,
2191 2024U, 1962U, 2473U, 2451U, 599U, 3513U, 730U, 1334U,
2192 590U, 3579U, 3849U, 211U, 3321U, 3710U, 3348U, 3974U,
2193 251U, 3386U, 4011U, 4026U, 3699U, 3687U, 3824U, 1309U,
2194 3953U, 1211U, 3983U, 1520U, 2873U, 2859U, 1513U, 2866U,
2195 3109U, 1657U, 2542U, 2521U, 2549U, 2556U, 3570U, 2357U,
2196 771U, 2341U, 722U, 2349U, 763U, 2333U, 714U, 2395U,
2197 2387U, 1353U, 1345U, 3431U, 3421U, 3411U, 3401U, 3451U,
2198 3441U, 4264U, 4274U, 3461U, 3474U, 4284U, 4294U, 3487U,
2199 3500U, 415U, 147U, 1681U, 128U, 297U, 4041U, 1753U,
2200 1127U, 4114U, 1416U, 2680U, 35U, 9U, 1302U, 18U,
2201 0U, 2655U, 2687U, 1175U, 3945U, 223U, 1393U, 1407U,
2202 2503U, 2512U, 3534U, 3547U, 3127U, 2120U, 3260U, 1111U,
2203 2048U, 2058U, 820U, 835U, 1839U, 1892U, 1948U, 2010U,
2204 4076U, 4102U, 4088U, 779U, 807U, 792U, 1272U, 1287U,
2205 496U, 1438U, 2183U, 4172U, 2207U, 4196U, 3134U, 631U,
2206 621U, 2696U, 3639U, 850U, 2956U, 2936U, 3667U, 3646U,
2207 2990U, 3021U, 3007U, 3303U, 4347U, 2297U, 4340U, 2278U,
2208 3179U, 2588U, 2495U, 989U, 1723U, 1526U, 3194U, 2255U,
2209 3201U, 2076U, 3186U, 2247U, 2068U, 26U, 1377U, 1369U,
2210 1361U, 3880U, 2903U, 3766U, 3811U, 3913U, 2714U, 859U,
2211 280U, 1080U, 950U, 443U, 154U, 1709U, 4048U, 1760U,
2212 134U, 3888U, 2664U, 2528U, 3211U, 2826U, 2842U, 4304U,
2213 895U, 1092U, 3606U, 2403U, 879U, 2444U, 2420U, 2432U,
2214 422U, 1688U, 398U, 1664U, 4121U, 2132U, 1871U, 1818U,
2215 1986U, 1924U, 474U, 1731U, 539U, 3074U, 3036U, 4155U,
2216 2166U, 4179U, 2190U, 4250U, 4257U, 4397U, 4765U, 5158U,
2217 5548U, 5938U, 6346U, 4568U, 4936U, 5329U, 5719U, 6094U,
2218 6517U, 4484U, 4852U, 5245U, 5635U, 6017U, 6433U, 4655U,
2219 5023U, 5416U, 5806U, 6181U, 6604U, 4379U, 4747U, 5140U,
2220 5530U, 5920U, 6328U, 4550U, 4918U, 5311U, 5701U, 6076U,
2221 6499U, 4468U, 4836U, 5229U, 5619U, 6001U, 6417U, 4639U,
2222 5007U, 5400U, 5790U, 6165U, 6588U, 4704U, 2316U, 2621U,
2223 4405U, 4773U, 5166U, 5556U, 5946U, 6354U, 4576U, 4944U,
2224 5337U, 5727U, 6102U, 6525U, 4491U, 4859U, 5252U, 5642U,
2225 6024U, 6440U, 4662U, 5030U, 5423U, 5813U, 6188U, 6611U,
2226 4388U, 4756U, 5149U, 5539U, 5929U, 6337U, 4559U, 4927U,
2227 5320U, 5710U, 6085U, 6508U, 4476U, 4844U, 5237U, 5627U,
2228 6009U, 6425U, 4647U, 5015U, 5408U, 5798U, 6173U, 6596U,
2229 4429U, 4797U, 5190U, 5580U, 5970U, 6378U, 4600U, 4968U,
2230 5361U, 5751U, 6126U, 6549U, 4512U, 4880U, 5273U, 5663U,
2231 6045U, 6461U, 4683U, 5051U, 5444U, 5834U, 6209U, 6632U,
2232 4437U, 4805U, 5198U, 5588U, 5978U, 6386U, 4608U, 4976U,
2233 5369U, 5759U, 6134U, 6557U, 4519U, 4887U, 5280U, 5670U,
2234 6052U, 6468U, 4690U, 5058U, 5451U, 5841U, 6216U, 6639U,
2235 4721U, 5114U, 6302U, 4724U, 5117U, 5507U, 5897U, 6305U,
2236 4413U, 4781U, 5174U, 5564U, 5954U, 6362U, 4584U, 4952U,
2237 5345U, 5735U, 6110U, 6533U, 4498U, 4866U, 5259U, 5649U,
2238 6031U, 6447U, 4669U, 5037U, 5430U, 5820U, 6195U, 6618U,
2239 4396U, 4764U, 5157U, 5547U, 5937U, 6345U, 4567U, 4935U,
2240 5328U, 5718U, 6093U, 6516U, 4483U, 4851U, 5244U, 5634U,
2241 6016U, 6432U, 4654U, 5022U, 5415U, 5805U, 6180U, 6603U,
2242 207U, 2563U, 4445U, 4813U, 5206U, 5596U, 6394U, 4616U,
2243 4984U, 5377U, 5767U, 6142U, 6565U, 4526U, 4894U, 5287U,
2244 5677U, 6475U, 4697U, 5065U, 5458U, 5848U, 6223U, 6646U,
2245 98U, 109U, 6260U, 4354U, 4713U, 6252U, 6295U, 3602U,
2246 1402U, 5072U, 5465U, 5855U, 6230U, 5102U, 5495U, 5885U,
2247 6283U, 5087U, 5480U, 5870U, 6245U, 5108U, 5501U, 5891U,
2248 6289U, 49U, 82U, 5094U, 5487U, 5877U, 6267U, 4362U,
2249 4730U, 5123U, 5513U, 5903U, 6311U, 4533U, 4901U, 5294U,
2250 5684U, 6059U, 6482U, 4453U, 4821U, 5214U, 5604U, 5986U,
2251 6402U, 4624U, 4992U, 5385U, 5775U, 6150U, 6573U, 4370U,
2252 4738U, 5131U, 5521U, 5911U, 6319U, 4541U, 4909U, 5302U,
2253 5692U, 6067U, 6490U, 4460U, 4828U, 5221U, 5611U, 5993U,
2254 6409U, 4631U, 4999U, 5392U, 5782U, 6157U, 6580U, 5079U,
2255 5472U, 5862U, 6237U, 68U, 120U, 56U, 88U, 43U,
2256 77U, 62U, 93U, 4421U, 4789U, 5182U, 5572U, 5962U,
2257 6370U, 4592U, 4960U, 5353U, 5743U, 6118U, 6541U, 4505U,
2258 4873U, 5266U, 5656U, 6038U, 6454U, 4676U, 5044U, 5437U,
2259 5827U, 6202U, 6625U, 6275U,
2260};
2261
2262static inline void InitMSP430MCInstrInfo(MCInstrInfo *II) {
2263 II->InitMCInstrInfo(MSP430Descs.Insts, MSP430InstrNameIndices, MSP430InstrNameData, nullptr, nullptr, 676, nullptr, 0);
2264}
2265
2266
2267} // namespace llvm
2268
2269#endif // GET_INSTRINFO_MC_DESC
2270
2271#ifdef GET_INSTRINFO_HEADER
2272#undef GET_INSTRINFO_HEADER
2273
2274namespace llvm {
2275
2276struct MSP430GenInstrInfo : public TargetInstrInfo {
2277 explicit MSP430GenInstrInfo(const TargetSubtargetInfo &STI, const TargetRegisterInfo &TRI, unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u, unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u);
2278 ~MSP430GenInstrInfo() override = default;
2279};
2280
2281} // namespace llvm
2282
2283namespace llvm::MSP430 {
2284
2285
2286} // namespace llvm::MSP430
2287
2288#endif // GET_INSTRINFO_HEADER
2289
2290#ifdef GET_INSTRINFO_HELPER_DECLS
2291#undef GET_INSTRINFO_HELPER_DECLS
2292
2293
2294#endif // GET_INSTRINFO_HELPER_DECLS
2295
2296#ifdef GET_INSTRINFO_HELPERS
2297#undef GET_INSTRINFO_HELPERS
2298
2299
2300#endif // GET_INSTRINFO_HELPERS
2301
2302#ifdef GET_INSTRINFO_CTOR_DTOR
2303#undef GET_INSTRINFO_CTOR_DTOR
2304
2305namespace llvm {
2306
2307extern const MSP430InstrTable MSP430Descs;
2308extern const unsigned MSP430InstrNameIndices[];
2309extern const char MSP430InstrNameData[];
2310MSP430GenInstrInfo::MSP430GenInstrInfo(const TargetSubtargetInfo &STI, const TargetRegisterInfo &TRI, unsigned CFSetupOpcode, unsigned CFDestroyOpcode, unsigned CatchRetOpcode, unsigned ReturnOpcode)
2311 : TargetInstrInfo(TRI, CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) {
2312 InitMCInstrInfo(MSP430Descs.Insts, MSP430InstrNameIndices, MSP430InstrNameData, nullptr, nullptr, 676);
2313}
2314
2315} // namespace llvm
2316
2317#endif // GET_INSTRINFO_CTOR_DTOR
2318
2319#ifdef GET_INSTRINFO_MC_HELPER_DECLS
2320#undef GET_INSTRINFO_MC_HELPER_DECLS
2321
2322namespace llvm {
2323
2324class MCInst;
2325class FeatureBitset;
2326
2327namespace MSP430_MC {
2328
2329void verifyInstructionPredicates(unsigned Opcode, const FeatureBitset &Features);
2330
2331} // namespace MSP430_MC
2332
2333} // namespace llvm
2334
2335#endif // GET_INSTRINFO_MC_HELPER_DECLS
2336
2337#ifdef GET_INSTRINFO_MC_HELPERS
2338#undef GET_INSTRINFO_MC_HELPERS
2339
2340namespace llvm::MSP430_MC {
2341
2342
2343} // namespace llvm::MSP430_MC
2344
2345#endif // GET_INSTRINFO_MC_HELPERS
2346
2347#if (defined(ENABLE_INSTR_PREDICATE_VERIFIER) && !defined(NDEBUG)) ||\
2348 defined(GET_AVAILABLE_OPCODE_CHECKER)
2349#define GET_COMPUTE_FEATURES
2350#endif
2351#ifdef GET_COMPUTE_FEATURES
2352#undef GET_COMPUTE_FEATURES
2353
2354namespace llvm::MSP430_MC {
2355
2356// Bits for subtarget features that participate in instruction matching.
2357enum SubtargetFeatureBits : uint8_t {
2358};
2359
2360inline FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) {
2361 FeatureBitset Features;
2362 return Features;
2363}
2364
2365inline FeatureBitset computeRequiredFeatures(unsigned Opcode) {
2366 enum : uint8_t {
2367 CEFBS_None,
2368 };
2369
2370 static constexpr FeatureBitset FeatureBitsets[] = {
2371 {}, // CEFBS_None
2372 };
2373 static constexpr uint8_t RequiredFeaturesRefs[] = {
2374 CEFBS_None, // PHI
2375 CEFBS_None, // INLINEASM
2376 CEFBS_None, // INLINEASM_BR
2377 CEFBS_None, // CFI_INSTRUCTION
2378 CEFBS_None, // EH_LABEL
2379 CEFBS_None, // GC_LABEL
2380 CEFBS_None, // ANNOTATION_LABEL
2381 CEFBS_None, // KILL
2382 CEFBS_None, // EXTRACT_SUBREG
2383 CEFBS_None, // INSERT_SUBREG
2384 CEFBS_None, // IMPLICIT_DEF
2385 CEFBS_None, // INIT_UNDEF
2386 CEFBS_None, // SUBREG_TO_REG
2387 CEFBS_None, // COPY_TO_REGCLASS
2388 CEFBS_None, // DBG_VALUE
2389 CEFBS_None, // DBG_VALUE_LIST
2390 CEFBS_None, // DBG_INSTR_REF
2391 CEFBS_None, // DBG_PHI
2392 CEFBS_None, // DBG_LABEL
2393 CEFBS_None, // REG_SEQUENCE
2394 CEFBS_None, // COPY
2395 CEFBS_None, // COPY_LANEMASK
2396 CEFBS_None, // BUNDLE
2397 CEFBS_None, // LIFETIME_START
2398 CEFBS_None, // LIFETIME_END
2399 CEFBS_None, // PSEUDO_PROBE
2400 CEFBS_None, // ARITH_FENCE
2401 CEFBS_None, // STACKMAP
2402 CEFBS_None, // FENTRY_CALL
2403 CEFBS_None, // PATCHPOINT
2404 CEFBS_None, // LOAD_STACK_GUARD
2405 CEFBS_None, // PREALLOCATED_SETUP
2406 CEFBS_None, // PREALLOCATED_ARG
2407 CEFBS_None, // STATEPOINT
2408 CEFBS_None, // LOCAL_ESCAPE
2409 CEFBS_None, // FAULTING_OP
2410 CEFBS_None, // PATCHABLE_OP
2411 CEFBS_None, // PATCHABLE_FUNCTION_ENTER
2412 CEFBS_None, // PATCHABLE_RET
2413 CEFBS_None, // PATCHABLE_FUNCTION_EXIT
2414 CEFBS_None, // PATCHABLE_TAIL_CALL
2415 CEFBS_None, // PATCHABLE_EVENT_CALL
2416 CEFBS_None, // PATCHABLE_TYPED_EVENT_CALL
2417 CEFBS_None, // ICALL_BRANCH_FUNNEL
2418 CEFBS_None, // FAKE_USE
2419 CEFBS_None, // MEMBARRIER
2420 CEFBS_None, // JUMP_TABLE_DEBUG_INFO
2421 CEFBS_None, // RELOC_NONE
2422 CEFBS_None, // CONVERGENCECTRL_ENTRY
2423 CEFBS_None, // CONVERGENCECTRL_ANCHOR
2424 CEFBS_None, // CONVERGENCECTRL_LOOP
2425 CEFBS_None, // CONVERGENCECTRL_GLUE
2426 CEFBS_None, // G_ASSERT_SEXT
2427 CEFBS_None, // G_ASSERT_ZEXT
2428 CEFBS_None, // G_ASSERT_ALIGN
2429 CEFBS_None, // G_ADD
2430 CEFBS_None, // G_SUB
2431 CEFBS_None, // G_MUL
2432 CEFBS_None, // G_SDIV
2433 CEFBS_None, // G_UDIV
2434 CEFBS_None, // G_SREM
2435 CEFBS_None, // G_UREM
2436 CEFBS_None, // G_SDIVREM
2437 CEFBS_None, // G_UDIVREM
2438 CEFBS_None, // G_AND
2439 CEFBS_None, // G_OR
2440 CEFBS_None, // G_XOR
2441 CEFBS_None, // G_ABDS
2442 CEFBS_None, // G_ABDU
2443 CEFBS_None, // G_UAVGFLOOR
2444 CEFBS_None, // G_UAVGCEIL
2445 CEFBS_None, // G_SAVGFLOOR
2446 CEFBS_None, // G_SAVGCEIL
2447 CEFBS_None, // G_IMPLICIT_DEF
2448 CEFBS_None, // G_PHI
2449 CEFBS_None, // G_FRAME_INDEX
2450 CEFBS_None, // G_GLOBAL_VALUE
2451 CEFBS_None, // G_PTRAUTH_GLOBAL_VALUE
2452 CEFBS_None, // G_CONSTANT_POOL
2453 CEFBS_None, // G_EXTRACT
2454 CEFBS_None, // G_UNMERGE_VALUES
2455 CEFBS_None, // G_INSERT
2456 CEFBS_None, // G_MERGE_VALUES
2457 CEFBS_None, // G_BUILD_VECTOR
2458 CEFBS_None, // G_BUILD_VECTOR_TRUNC
2459 CEFBS_None, // G_CONCAT_VECTORS
2460 CEFBS_None, // G_PTRTOINT
2461 CEFBS_None, // G_INTTOPTR
2462 CEFBS_None, // G_BITCAST
2463 CEFBS_None, // G_FREEZE
2464 CEFBS_None, // G_CONSTANT_FOLD_BARRIER
2465 CEFBS_None, // G_INTRINSIC_FPTRUNC_ROUND
2466 CEFBS_None, // G_INTRINSIC_TRUNC
2467 CEFBS_None, // G_INTRINSIC_ROUND
2468 CEFBS_None, // G_INTRINSIC_LRINT
2469 CEFBS_None, // G_INTRINSIC_LLRINT
2470 CEFBS_None, // G_INTRINSIC_ROUNDEVEN
2471 CEFBS_None, // G_READCYCLECOUNTER
2472 CEFBS_None, // G_READSTEADYCOUNTER
2473 CEFBS_None, // G_LOAD
2474 CEFBS_None, // G_SEXTLOAD
2475 CEFBS_None, // G_ZEXTLOAD
2476 CEFBS_None, // G_FPEXTLOAD
2477 CEFBS_None, // G_INDEXED_LOAD
2478 CEFBS_None, // G_INDEXED_SEXTLOAD
2479 CEFBS_None, // G_INDEXED_ZEXTLOAD
2480 CEFBS_None, // G_STORE
2481 CEFBS_None, // G_FPTRUNCSTORE
2482 CEFBS_None, // G_INDEXED_STORE
2483 CEFBS_None, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
2484 CEFBS_None, // G_ATOMIC_CMPXCHG
2485 CEFBS_None, // G_ATOMICRMW_XCHG
2486 CEFBS_None, // G_ATOMICRMW_ADD
2487 CEFBS_None, // G_ATOMICRMW_SUB
2488 CEFBS_None, // G_ATOMICRMW_AND
2489 CEFBS_None, // G_ATOMICRMW_NAND
2490 CEFBS_None, // G_ATOMICRMW_OR
2491 CEFBS_None, // G_ATOMICRMW_XOR
2492 CEFBS_None, // G_ATOMICRMW_MAX
2493 CEFBS_None, // G_ATOMICRMW_MIN
2494 CEFBS_None, // G_ATOMICRMW_UMAX
2495 CEFBS_None, // G_ATOMICRMW_UMIN
2496 CEFBS_None, // G_ATOMICRMW_FADD
2497 CEFBS_None, // G_ATOMICRMW_FSUB
2498 CEFBS_None, // G_ATOMICRMW_FMAX
2499 CEFBS_None, // G_ATOMICRMW_FMIN
2500 CEFBS_None, // G_ATOMICRMW_FMAXIMUM
2501 CEFBS_None, // G_ATOMICRMW_FMINIMUM
2502 CEFBS_None, // G_ATOMICRMW_FMAXIMUMNUM
2503 CEFBS_None, // G_ATOMICRMW_FMINIMUMNUM
2504 CEFBS_None, // G_ATOMICRMW_UINC_WRAP
2505 CEFBS_None, // G_ATOMICRMW_UDEC_WRAP
2506 CEFBS_None, // G_ATOMICRMW_USUB_COND
2507 CEFBS_None, // G_ATOMICRMW_USUB_SAT
2508 CEFBS_None, // G_FENCE
2509 CEFBS_None, // G_PREFETCH
2510 CEFBS_None, // G_BRCOND
2511 CEFBS_None, // G_BRINDIRECT
2512 CEFBS_None, // G_INVOKE_REGION_START
2513 CEFBS_None, // G_INTRINSIC
2514 CEFBS_None, // G_INTRINSIC_W_SIDE_EFFECTS
2515 CEFBS_None, // G_INTRINSIC_CONVERGENT
2516 CEFBS_None, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
2517 CEFBS_None, // G_ANYEXT
2518 CEFBS_None, // G_TRUNC
2519 CEFBS_None, // G_TRUNC_SSAT_S
2520 CEFBS_None, // G_TRUNC_SSAT_U
2521 CEFBS_None, // G_TRUNC_USAT_U
2522 CEFBS_None, // G_CONSTANT
2523 CEFBS_None, // G_FCONSTANT
2524 CEFBS_None, // G_VASTART
2525 CEFBS_None, // G_VAARG
2526 CEFBS_None, // G_SEXT
2527 CEFBS_None, // G_SEXT_INREG
2528 CEFBS_None, // G_ZEXT
2529 CEFBS_None, // G_SHL
2530 CEFBS_None, // G_LSHR
2531 CEFBS_None, // G_ASHR
2532 CEFBS_None, // G_FSHL
2533 CEFBS_None, // G_FSHR
2534 CEFBS_None, // G_ROTR
2535 CEFBS_None, // G_ROTL
2536 CEFBS_None, // G_ICMP
2537 CEFBS_None, // G_FCMP
2538 CEFBS_None, // G_SCMP
2539 CEFBS_None, // G_UCMP
2540 CEFBS_None, // G_SELECT
2541 CEFBS_None, // G_UADDO
2542 CEFBS_None, // G_UADDE
2543 CEFBS_None, // G_USUBO
2544 CEFBS_None, // G_USUBE
2545 CEFBS_None, // G_SADDO
2546 CEFBS_None, // G_SADDE
2547 CEFBS_None, // G_SSUBO
2548 CEFBS_None, // G_SSUBE
2549 CEFBS_None, // G_UMULO
2550 CEFBS_None, // G_SMULO
2551 CEFBS_None, // G_UMULH
2552 CEFBS_None, // G_SMULH
2553 CEFBS_None, // G_UADDSAT
2554 CEFBS_None, // G_SADDSAT
2555 CEFBS_None, // G_USUBSAT
2556 CEFBS_None, // G_SSUBSAT
2557 CEFBS_None, // G_USHLSAT
2558 CEFBS_None, // G_SSHLSAT
2559 CEFBS_None, // G_SMULFIX
2560 CEFBS_None, // G_UMULFIX
2561 CEFBS_None, // G_SMULFIXSAT
2562 CEFBS_None, // G_UMULFIXSAT
2563 CEFBS_None, // G_SDIVFIX
2564 CEFBS_None, // G_UDIVFIX
2565 CEFBS_None, // G_SDIVFIXSAT
2566 CEFBS_None, // G_UDIVFIXSAT
2567 CEFBS_None, // G_FADD
2568 CEFBS_None, // G_FSUB
2569 CEFBS_None, // G_FMUL
2570 CEFBS_None, // G_FMA
2571 CEFBS_None, // G_FMAD
2572 CEFBS_None, // G_FDIV
2573 CEFBS_None, // G_FREM
2574 CEFBS_None, // G_FMODF
2575 CEFBS_None, // G_FPOW
2576 CEFBS_None, // G_FPOWI
2577 CEFBS_None, // G_FEXP
2578 CEFBS_None, // G_FEXP2
2579 CEFBS_None, // G_FEXP10
2580 CEFBS_None, // G_FLOG
2581 CEFBS_None, // G_FLOG2
2582 CEFBS_None, // G_FLOG10
2583 CEFBS_None, // G_FLDEXP
2584 CEFBS_None, // G_FFREXP
2585 CEFBS_None, // G_FNEG
2586 CEFBS_None, // G_FPEXT
2587 CEFBS_None, // G_FPTRUNC
2588 CEFBS_None, // G_FPTOSI
2589 CEFBS_None, // G_FPTOUI
2590 CEFBS_None, // G_SITOFP
2591 CEFBS_None, // G_UITOFP
2592 CEFBS_None, // G_FPTOSI_SAT
2593 CEFBS_None, // G_FPTOUI_SAT
2594 CEFBS_None, // G_FABS
2595 CEFBS_None, // G_FCOPYSIGN
2596 CEFBS_None, // G_IS_FPCLASS
2597 CEFBS_None, // G_FCANONICALIZE
2598 CEFBS_None, // G_FMINNUM
2599 CEFBS_None, // G_FMAXNUM
2600 CEFBS_None, // G_FMINNUM_IEEE
2601 CEFBS_None, // G_FMAXNUM_IEEE
2602 CEFBS_None, // G_FMINIMUM
2603 CEFBS_None, // G_FMAXIMUM
2604 CEFBS_None, // G_FMINIMUMNUM
2605 CEFBS_None, // G_FMAXIMUMNUM
2606 CEFBS_None, // G_GET_FPENV
2607 CEFBS_None, // G_SET_FPENV
2608 CEFBS_None, // G_RESET_FPENV
2609 CEFBS_None, // G_GET_FPMODE
2610 CEFBS_None, // G_SET_FPMODE
2611 CEFBS_None, // G_RESET_FPMODE
2612 CEFBS_None, // G_GET_ROUNDING
2613 CEFBS_None, // G_SET_ROUNDING
2614 CEFBS_None, // G_PTR_ADD
2615 CEFBS_None, // G_PTRMASK
2616 CEFBS_None, // G_SMIN
2617 CEFBS_None, // G_SMAX
2618 CEFBS_None, // G_UMIN
2619 CEFBS_None, // G_UMAX
2620 CEFBS_None, // G_ABS
2621 CEFBS_None, // G_LROUND
2622 CEFBS_None, // G_LLROUND
2623 CEFBS_None, // G_BR
2624 CEFBS_None, // G_BRJT
2625 CEFBS_None, // G_VSCALE
2626 CEFBS_None, // G_INSERT_SUBVECTOR
2627 CEFBS_None, // G_EXTRACT_SUBVECTOR
2628 CEFBS_None, // G_INSERT_VECTOR_ELT
2629 CEFBS_None, // G_EXTRACT_VECTOR_ELT
2630 CEFBS_None, // G_SHUFFLE_VECTOR
2631 CEFBS_None, // G_SPLAT_VECTOR
2632 CEFBS_None, // G_STEP_VECTOR
2633 CEFBS_None, // G_VECTOR_COMPRESS
2634 CEFBS_None, // G_CTTZ
2635 CEFBS_None, // G_CTTZ_ZERO_POISON
2636 CEFBS_None, // G_CTLZ
2637 CEFBS_None, // G_CTLZ_ZERO_POISON
2638 CEFBS_None, // G_CTLS
2639 CEFBS_None, // G_CTPOP
2640 CEFBS_None, // G_BSWAP
2641 CEFBS_None, // G_BITREVERSE
2642 CEFBS_None, // G_CLMUL
2643 CEFBS_None, // G_FCEIL
2644 CEFBS_None, // G_FCOS
2645 CEFBS_None, // G_FSIN
2646 CEFBS_None, // G_FSINCOS
2647 CEFBS_None, // G_FTAN
2648 CEFBS_None, // G_FACOS
2649 CEFBS_None, // G_FASIN
2650 CEFBS_None, // G_FATAN
2651 CEFBS_None, // G_FATAN2
2652 CEFBS_None, // G_FCOSH
2653 CEFBS_None, // G_FSINH
2654 CEFBS_None, // G_FTANH
2655 CEFBS_None, // G_FSQRT
2656 CEFBS_None, // G_FFLOOR
2657 CEFBS_None, // G_FRINT
2658 CEFBS_None, // G_FNEARBYINT
2659 CEFBS_None, // G_ADDRSPACE_CAST
2660 CEFBS_None, // G_BLOCK_ADDR
2661 CEFBS_None, // G_JUMP_TABLE
2662 CEFBS_None, // G_DYN_STACKALLOC
2663 CEFBS_None, // G_STACKSAVE
2664 CEFBS_None, // G_STACKRESTORE
2665 CEFBS_None, // G_STRICT_FADD
2666 CEFBS_None, // G_STRICT_FSUB
2667 CEFBS_None, // G_STRICT_FMUL
2668 CEFBS_None, // G_STRICT_FDIV
2669 CEFBS_None, // G_STRICT_FREM
2670 CEFBS_None, // G_STRICT_FMA
2671 CEFBS_None, // G_STRICT_FSQRT
2672 CEFBS_None, // G_STRICT_FLDEXP
2673 CEFBS_None, // G_STRICT_FCMP
2674 CEFBS_None, // G_STRICT_FCMPS
2675 CEFBS_None, // G_READ_REGISTER
2676 CEFBS_None, // G_WRITE_REGISTER
2677 CEFBS_None, // G_MEMCPY
2678 CEFBS_None, // G_MEMCPY_INLINE
2679 CEFBS_None, // G_MEMMOVE
2680 CEFBS_None, // G_MEMSET
2681 CEFBS_None, // G_BZERO
2682 CEFBS_None, // G_MEMSET_INLINE
2683 CEFBS_None, // G_TRAP
2684 CEFBS_None, // G_DEBUGTRAP
2685 CEFBS_None, // G_UBSANTRAP
2686 CEFBS_None, // G_VECREDUCE_SEQ_FADD
2687 CEFBS_None, // G_VECREDUCE_SEQ_FMUL
2688 CEFBS_None, // G_VECREDUCE_FADD
2689 CEFBS_None, // G_VECREDUCE_FMUL
2690 CEFBS_None, // G_VECREDUCE_FMAX
2691 CEFBS_None, // G_VECREDUCE_FMIN
2692 CEFBS_None, // G_VECREDUCE_FMAXIMUM
2693 CEFBS_None, // G_VECREDUCE_FMINIMUM
2694 CEFBS_None, // G_VECREDUCE_FMAXIMUMNUM
2695 CEFBS_None, // G_VECREDUCE_FMINIMUMNUM
2696 CEFBS_None, // G_VECREDUCE_ADD
2697 CEFBS_None, // G_VECREDUCE_MUL
2698 CEFBS_None, // G_VECREDUCE_AND
2699 CEFBS_None, // G_VECREDUCE_OR
2700 CEFBS_None, // G_VECREDUCE_XOR
2701 CEFBS_None, // G_VECREDUCE_SMAX
2702 CEFBS_None, // G_VECREDUCE_SMIN
2703 CEFBS_None, // G_VECREDUCE_UMAX
2704 CEFBS_None, // G_VECREDUCE_UMIN
2705 CEFBS_None, // G_SBFX
2706 CEFBS_None, // G_UBFX
2707 CEFBS_None, // ADD16mc
2708 CEFBS_None, // ADD16mi
2709 CEFBS_None, // ADD16mm
2710 CEFBS_None, // ADD16mn
2711 CEFBS_None, // ADD16mp
2712 CEFBS_None, // ADD16mr
2713 CEFBS_None, // ADD16rc
2714 CEFBS_None, // ADD16ri
2715 CEFBS_None, // ADD16rm
2716 CEFBS_None, // ADD16rn
2717 CEFBS_None, // ADD16rp
2718 CEFBS_None, // ADD16rr
2719 CEFBS_None, // ADD8mc
2720 CEFBS_None, // ADD8mi
2721 CEFBS_None, // ADD8mm
2722 CEFBS_None, // ADD8mn
2723 CEFBS_None, // ADD8mp
2724 CEFBS_None, // ADD8mr
2725 CEFBS_None, // ADD8rc
2726 CEFBS_None, // ADD8ri
2727 CEFBS_None, // ADD8rm
2728 CEFBS_None, // ADD8rn
2729 CEFBS_None, // ADD8rp
2730 CEFBS_None, // ADD8rr
2731 CEFBS_None, // ADDC16mc
2732 CEFBS_None, // ADDC16mi
2733 CEFBS_None, // ADDC16mm
2734 CEFBS_None, // ADDC16mn
2735 CEFBS_None, // ADDC16mp
2736 CEFBS_None, // ADDC16mr
2737 CEFBS_None, // ADDC16rc
2738 CEFBS_None, // ADDC16ri
2739 CEFBS_None, // ADDC16rm
2740 CEFBS_None, // ADDC16rn
2741 CEFBS_None, // ADDC16rp
2742 CEFBS_None, // ADDC16rr
2743 CEFBS_None, // ADDC8mc
2744 CEFBS_None, // ADDC8mi
2745 CEFBS_None, // ADDC8mm
2746 CEFBS_None, // ADDC8mn
2747 CEFBS_None, // ADDC8mp
2748 CEFBS_None, // ADDC8mr
2749 CEFBS_None, // ADDC8rc
2750 CEFBS_None, // ADDC8ri
2751 CEFBS_None, // ADDC8rm
2752 CEFBS_None, // ADDC8rn
2753 CEFBS_None, // ADDC8rp
2754 CEFBS_None, // ADDC8rr
2755 CEFBS_None, // ADDframe
2756 CEFBS_None, // ADJCALLSTACKDOWN
2757 CEFBS_None, // ADJCALLSTACKUP
2758 CEFBS_None, // AND16mc
2759 CEFBS_None, // AND16mi
2760 CEFBS_None, // AND16mm
2761 CEFBS_None, // AND16mn
2762 CEFBS_None, // AND16mp
2763 CEFBS_None, // AND16mr
2764 CEFBS_None, // AND16rc
2765 CEFBS_None, // AND16ri
2766 CEFBS_None, // AND16rm
2767 CEFBS_None, // AND16rn
2768 CEFBS_None, // AND16rp
2769 CEFBS_None, // AND16rr
2770 CEFBS_None, // AND8mc
2771 CEFBS_None, // AND8mi
2772 CEFBS_None, // AND8mm
2773 CEFBS_None, // AND8mn
2774 CEFBS_None, // AND8mp
2775 CEFBS_None, // AND8mr
2776 CEFBS_None, // AND8rc
2777 CEFBS_None, // AND8ri
2778 CEFBS_None, // AND8rm
2779 CEFBS_None, // AND8rn
2780 CEFBS_None, // AND8rp
2781 CEFBS_None, // AND8rr
2782 CEFBS_None, // BIC16mc
2783 CEFBS_None, // BIC16mi
2784 CEFBS_None, // BIC16mm
2785 CEFBS_None, // BIC16mn
2786 CEFBS_None, // BIC16mp
2787 CEFBS_None, // BIC16mr
2788 CEFBS_None, // BIC16rc
2789 CEFBS_None, // BIC16ri
2790 CEFBS_None, // BIC16rm
2791 CEFBS_None, // BIC16rn
2792 CEFBS_None, // BIC16rp
2793 CEFBS_None, // BIC16rr
2794 CEFBS_None, // BIC8mc
2795 CEFBS_None, // BIC8mi
2796 CEFBS_None, // BIC8mm
2797 CEFBS_None, // BIC8mn
2798 CEFBS_None, // BIC8mp
2799 CEFBS_None, // BIC8mr
2800 CEFBS_None, // BIC8rc
2801 CEFBS_None, // BIC8ri
2802 CEFBS_None, // BIC8rm
2803 CEFBS_None, // BIC8rn
2804 CEFBS_None, // BIC8rp
2805 CEFBS_None, // BIC8rr
2806 CEFBS_None, // BIS16mc
2807 CEFBS_None, // BIS16mi
2808 CEFBS_None, // BIS16mm
2809 CEFBS_None, // BIS16mn
2810 CEFBS_None, // BIS16mp
2811 CEFBS_None, // BIS16mr
2812 CEFBS_None, // BIS16rc
2813 CEFBS_None, // BIS16ri
2814 CEFBS_None, // BIS16rm
2815 CEFBS_None, // BIS16rn
2816 CEFBS_None, // BIS16rp
2817 CEFBS_None, // BIS16rr
2818 CEFBS_None, // BIS8mc
2819 CEFBS_None, // BIS8mi
2820 CEFBS_None, // BIS8mm
2821 CEFBS_None, // BIS8mn
2822 CEFBS_None, // BIS8mp
2823 CEFBS_None, // BIS8mr
2824 CEFBS_None, // BIS8rc
2825 CEFBS_None, // BIS8ri
2826 CEFBS_None, // BIS8rm
2827 CEFBS_None, // BIS8rn
2828 CEFBS_None, // BIS8rp
2829 CEFBS_None, // BIS8rr
2830 CEFBS_None, // BIT16mc
2831 CEFBS_None, // BIT16mi
2832 CEFBS_None, // BIT16mm
2833 CEFBS_None, // BIT16mn
2834 CEFBS_None, // BIT16mp
2835 CEFBS_None, // BIT16mr
2836 CEFBS_None, // BIT16rc
2837 CEFBS_None, // BIT16ri
2838 CEFBS_None, // BIT16rm
2839 CEFBS_None, // BIT16rn
2840 CEFBS_None, // BIT16rp
2841 CEFBS_None, // BIT16rr
2842 CEFBS_None, // BIT8mc
2843 CEFBS_None, // BIT8mi
2844 CEFBS_None, // BIT8mm
2845 CEFBS_None, // BIT8mn
2846 CEFBS_None, // BIT8mp
2847 CEFBS_None, // BIT8mr
2848 CEFBS_None, // BIT8rc
2849 CEFBS_None, // BIT8ri
2850 CEFBS_None, // BIT8rm
2851 CEFBS_None, // BIT8rn
2852 CEFBS_None, // BIT8rp
2853 CEFBS_None, // BIT8rr
2854 CEFBS_None, // Bi
2855 CEFBS_None, // Bm
2856 CEFBS_None, // Br
2857 CEFBS_None, // CALLi
2858 CEFBS_None, // CALLm
2859 CEFBS_None, // CALLn
2860 CEFBS_None, // CALLp
2861 CEFBS_None, // CALLr
2862 CEFBS_None, // CMP16mc
2863 CEFBS_None, // CMP16mi
2864 CEFBS_None, // CMP16mm
2865 CEFBS_None, // CMP16mn
2866 CEFBS_None, // CMP16mp
2867 CEFBS_None, // CMP16mr
2868 CEFBS_None, // CMP16rc
2869 CEFBS_None, // CMP16ri
2870 CEFBS_None, // CMP16rm
2871 CEFBS_None, // CMP16rn
2872 CEFBS_None, // CMP16rp
2873 CEFBS_None, // CMP16rr
2874 CEFBS_None, // CMP8mc
2875 CEFBS_None, // CMP8mi
2876 CEFBS_None, // CMP8mm
2877 CEFBS_None, // CMP8mn
2878 CEFBS_None, // CMP8mp
2879 CEFBS_None, // CMP8mr
2880 CEFBS_None, // CMP8rc
2881 CEFBS_None, // CMP8ri
2882 CEFBS_None, // CMP8rm
2883 CEFBS_None, // CMP8rn
2884 CEFBS_None, // CMP8rp
2885 CEFBS_None, // CMP8rr
2886 CEFBS_None, // DADD16mc
2887 CEFBS_None, // DADD16mi
2888 CEFBS_None, // DADD16mm
2889 CEFBS_None, // DADD16mn
2890 CEFBS_None, // DADD16mp
2891 CEFBS_None, // DADD16mr
2892 CEFBS_None, // DADD16rc
2893 CEFBS_None, // DADD16ri
2894 CEFBS_None, // DADD16rm
2895 CEFBS_None, // DADD16rn
2896 CEFBS_None, // DADD16rp
2897 CEFBS_None, // DADD16rr
2898 CEFBS_None, // DADD8mc
2899 CEFBS_None, // DADD8mi
2900 CEFBS_None, // DADD8mm
2901 CEFBS_None, // DADD8mn
2902 CEFBS_None, // DADD8mp
2903 CEFBS_None, // DADD8mr
2904 CEFBS_None, // DADD8rc
2905 CEFBS_None, // DADD8ri
2906 CEFBS_None, // DADD8rm
2907 CEFBS_None, // DADD8rn
2908 CEFBS_None, // DADD8rp
2909 CEFBS_None, // DADD8rr
2910 CEFBS_None, // JCC
2911 CEFBS_None, // JMP
2912 CEFBS_None, // MOV16mc
2913 CEFBS_None, // MOV16mi
2914 CEFBS_None, // MOV16mm
2915 CEFBS_None, // MOV16mn
2916 CEFBS_None, // MOV16mr
2917 CEFBS_None, // MOV16rc
2918 CEFBS_None, // MOV16ri
2919 CEFBS_None, // MOV16rm
2920 CEFBS_None, // MOV16rn
2921 CEFBS_None, // MOV16rp
2922 CEFBS_None, // MOV16rr
2923 CEFBS_None, // MOV8mc
2924 CEFBS_None, // MOV8mi
2925 CEFBS_None, // MOV8mm
2926 CEFBS_None, // MOV8mn
2927 CEFBS_None, // MOV8mr
2928 CEFBS_None, // MOV8rc
2929 CEFBS_None, // MOV8ri
2930 CEFBS_None, // MOV8rm
2931 CEFBS_None, // MOV8rn
2932 CEFBS_None, // MOV8rp
2933 CEFBS_None, // MOV8rr
2934 CEFBS_None, // MOVZX16rm8
2935 CEFBS_None, // MOVZX16rr8
2936 CEFBS_None, // POP16r
2937 CEFBS_None, // PUSH16c
2938 CEFBS_None, // PUSH16i
2939 CEFBS_None, // PUSH16r
2940 CEFBS_None, // PUSH8r
2941 CEFBS_None, // RET
2942 CEFBS_None, // RETI
2943 CEFBS_None, // RRA16m
2944 CEFBS_None, // RRA16n
2945 CEFBS_None, // RRA16p
2946 CEFBS_None, // RRA16r
2947 CEFBS_None, // RRA8m
2948 CEFBS_None, // RRA8n
2949 CEFBS_None, // RRA8p
2950 CEFBS_None, // RRA8r
2951 CEFBS_None, // RRC16m
2952 CEFBS_None, // RRC16n
2953 CEFBS_None, // RRC16p
2954 CEFBS_None, // RRC16r
2955 CEFBS_None, // RRC8m
2956 CEFBS_None, // RRC8n
2957 CEFBS_None, // RRC8p
2958 CEFBS_None, // RRC8r
2959 CEFBS_None, // Rrcl16
2960 CEFBS_None, // Rrcl8
2961 CEFBS_None, // SEXT16m
2962 CEFBS_None, // SEXT16n
2963 CEFBS_None, // SEXT16p
2964 CEFBS_None, // SEXT16r
2965 CEFBS_None, // SUB16mc
2966 CEFBS_None, // SUB16mi
2967 CEFBS_None, // SUB16mm
2968 CEFBS_None, // SUB16mn
2969 CEFBS_None, // SUB16mp
2970 CEFBS_None, // SUB16mr
2971 CEFBS_None, // SUB16rc
2972 CEFBS_None, // SUB16ri
2973 CEFBS_None, // SUB16rm
2974 CEFBS_None, // SUB16rn
2975 CEFBS_None, // SUB16rp
2976 CEFBS_None, // SUB16rr
2977 CEFBS_None, // SUB8mc
2978 CEFBS_None, // SUB8mi
2979 CEFBS_None, // SUB8mm
2980 CEFBS_None, // SUB8mn
2981 CEFBS_None, // SUB8mp
2982 CEFBS_None, // SUB8mr
2983 CEFBS_None, // SUB8rc
2984 CEFBS_None, // SUB8ri
2985 CEFBS_None, // SUB8rm
2986 CEFBS_None, // SUB8rn
2987 CEFBS_None, // SUB8rp
2988 CEFBS_None, // SUB8rr
2989 CEFBS_None, // SUBC16mc
2990 CEFBS_None, // SUBC16mi
2991 CEFBS_None, // SUBC16mm
2992 CEFBS_None, // SUBC16mn
2993 CEFBS_None, // SUBC16mp
2994 CEFBS_None, // SUBC16mr
2995 CEFBS_None, // SUBC16rc
2996 CEFBS_None, // SUBC16ri
2997 CEFBS_None, // SUBC16rm
2998 CEFBS_None, // SUBC16rn
2999 CEFBS_None, // SUBC16rp
3000 CEFBS_None, // SUBC16rr
3001 CEFBS_None, // SUBC8mc
3002 CEFBS_None, // SUBC8mi
3003 CEFBS_None, // SUBC8mm
3004 CEFBS_None, // SUBC8mn
3005 CEFBS_None, // SUBC8mp
3006 CEFBS_None, // SUBC8mr
3007 CEFBS_None, // SUBC8rc
3008 CEFBS_None, // SUBC8ri
3009 CEFBS_None, // SUBC8rm
3010 CEFBS_None, // SUBC8rn
3011 CEFBS_None, // SUBC8rp
3012 CEFBS_None, // SUBC8rr
3013 CEFBS_None, // SWPB16m
3014 CEFBS_None, // SWPB16n
3015 CEFBS_None, // SWPB16p
3016 CEFBS_None, // SWPB16r
3017 CEFBS_None, // Select16
3018 CEFBS_None, // Select8
3019 CEFBS_None, // Shl16
3020 CEFBS_None, // Shl8
3021 CEFBS_None, // Sra16
3022 CEFBS_None, // Sra8
3023 CEFBS_None, // Srl16
3024 CEFBS_None, // Srl8
3025 CEFBS_None, // XOR16mc
3026 CEFBS_None, // XOR16mi
3027 CEFBS_None, // XOR16mm
3028 CEFBS_None, // XOR16mn
3029 CEFBS_None, // XOR16mp
3030 CEFBS_None, // XOR16mr
3031 CEFBS_None, // XOR16rc
3032 CEFBS_None, // XOR16ri
3033 CEFBS_None, // XOR16rm
3034 CEFBS_None, // XOR16rn
3035 CEFBS_None, // XOR16rp
3036 CEFBS_None, // XOR16rr
3037 CEFBS_None, // XOR8mc
3038 CEFBS_None, // XOR8mi
3039 CEFBS_None, // XOR8mm
3040 CEFBS_None, // XOR8mn
3041 CEFBS_None, // XOR8mp
3042 CEFBS_None, // XOR8mr
3043 CEFBS_None, // XOR8rc
3044 CEFBS_None, // XOR8ri
3045 CEFBS_None, // XOR8rm
3046 CEFBS_None, // XOR8rn
3047 CEFBS_None, // XOR8rp
3048 CEFBS_None, // XOR8rr
3049 CEFBS_None, // ZEXT16r
3050 };
3051
3052 assert(Opcode < 676);
3053 return FeatureBitsets[RequiredFeaturesRefs[Opcode]];
3054}
3055
3056
3057} // namespace llvm::MSP430_MC
3058
3059#endif // GET_COMPUTE_FEATURES
3060
3061#ifdef GET_AVAILABLE_OPCODE_CHECKER
3062#undef GET_AVAILABLE_OPCODE_CHECKER
3063
3064namespace llvm::MSP430_MC {
3065
3066bool isOpcodeAvailable(unsigned Opcode, const FeatureBitset &Features) {
3067 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
3068 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
3069 FeatureBitset MissingFeatures =
3070 (AvailableFeatures & RequiredFeatures) ^
3071 RequiredFeatures;
3072 return !MissingFeatures.any();
3073}
3074
3075} // namespace llvm::MSP430_MC
3076
3077#endif // GET_AVAILABLE_OPCODE_CHECKER
3078
3079#ifdef ENABLE_INSTR_PREDICATE_VERIFIER
3080#undef ENABLE_INSTR_PREDICATE_VERIFIER
3081
3082#include <sstream>
3083
3084namespace llvm::MSP430_MC {
3085
3086#ifndef NDEBUG
3087static const char *SubtargetFeatureNames[] = {
3088 nullptr
3089};
3090
3091#endif // NDEBUG
3092
3093void verifyInstructionPredicates(
3094 unsigned Opcode, const FeatureBitset &Features) {
3095#ifndef NDEBUG
3096 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
3097 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
3098 FeatureBitset MissingFeatures =
3099 (AvailableFeatures & RequiredFeatures) ^
3100 RequiredFeatures;
3101 if (MissingFeatures.any()) {
3102 std::ostringstream Msg;
3103 Msg << "Attempting to emit " << &MSP430InstrNameData[MSP430InstrNameIndices[Opcode]]
3104 << " instruction but the ";
3105 for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i)
3106 if (MissingFeatures.test(i))
3107 Msg << SubtargetFeatureNames[i] << " ";
3108 Msg << "predicate(s) are not met";
3109 report_fatal_error(Msg.str().c_str());
3110 }
3111#endif // NDEBUG
3112}
3113
3114} // namespace llvm::MSP430_MC
3115
3116#endif // ENABLE_INSTR_PREDICATE_VERIFIER
3117
3118