1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Instruction Enum Values and Descriptors *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_INSTRINFO_ENUM
10#undef GET_INSTRINFO_ENUM
11
12namespace llvm::MSP430 {
13
14 enum {
15 PHI = 0, // Target.td:1200
16 INLINEASM = 1, // Target.td:1206
17 INLINEASM_BR = 2, // Target.td:1212
18 CFI_INSTRUCTION = 3, // Target.td:1221
19 EH_LABEL = 4, // Target.td:1230
20 GC_LABEL = 5, // Target.td:1239
21 ANNOTATION_LABEL = 6, // Target.td:1248
22 KILL = 7, // Target.td:1256
23 EXTRACT_SUBREG = 8, // Target.td:1263
24 INSERT_SUBREG = 9, // Target.td:1269
25 IMPLICIT_DEF = 10, // Target.td:1276
26 INIT_UNDEF = 11, // Target.td:1285
27 SUBREG_TO_REG = 12, // Target.td:1292
28 COPY_TO_REGCLASS = 13, // Target.td:1298
29 DBG_VALUE = 14, // Target.td:1305
30 DBG_VALUE_LIST = 15, // Target.td:1312
31 DBG_INSTR_REF = 16, // Target.td:1319
32 DBG_PHI = 17, // Target.td:1326
33 DBG_LABEL = 18, // Target.td:1333
34 REG_SEQUENCE = 19, // Target.td:1340
35 COPY = 20, // Target.td:1347
36 COPY_LANEMASK = 21, // Target.td:1355
37 BUNDLE = 22, // Target.td:1362
38 LIFETIME_START = 23, // Target.td:1368
39 LIFETIME_END = 24, // Target.td:1375
40 PSEUDO_PROBE = 25, // Target.td:1382
41 ARITH_FENCE = 26, // Target.td:1389
42 STACKMAP = 27, // Target.td:1398
43 FENTRY_CALL = 28, // Target.td:1533
44 PATCHPOINT = 29, // Target.td:1406
45 LOAD_STACK_GUARD = 30, // Target.td:1424
46 PREALLOCATED_SETUP = 31, // Target.td:1432
47 PREALLOCATED_ARG = 32, // Target.td:1438
48 STATEPOINT = 33, // Target.td:1415
49 LOCAL_ESCAPE = 34, // Target.td:1444
50 FAULTING_OP = 35, // Target.td:1453
51 PATCHABLE_OP = 36, // Target.td:1473
52 PATCHABLE_FUNCTION_ENTER = 37, // Target.td:1481
53 PATCHABLE_RET = 38, // Target.td:1488
54 PATCHABLE_FUNCTION_EXIT = 39, // Target.td:1497
55 PATCHABLE_TAIL_CALL = 40, // Target.td:1505
56 PATCHABLE_EVENT_CALL = 41, // Target.td:1513
57 PATCHABLE_TYPED_EVENT_CALL = 42, // Target.td:1523
58 ICALL_BRANCH_FUNNEL = 43, // Target.td:1543
59 FAKE_USE = 44, // Target.td:1463
60 MEMBARRIER = 45, // Target.td:1549
61 JUMP_TABLE_DEBUG_INFO = 46, // Target.td:1557
62 RELOC_NONE = 47, // Target.td:1565
63 CONVERGENCECTRL_ENTRY = 48, // Target.td:1576
64 CONVERGENCECTRL_ANCHOR = 49, // Target.td:1572
65 CONVERGENCECTRL_LOOP = 50, // Target.td:1580
66 CONVERGENCECTRL_GLUE = 51, // Target.td:1584
67 G_ASSERT_SEXT = 52, // GenericOpcodes.td:1865
68 G_ASSERT_ZEXT = 53, // GenericOpcodes.td:1857
69 G_ASSERT_ALIGN = 54, // GenericOpcodes.td:1872
70 G_ADD = 55, // GenericOpcodes.td:300
71 G_SUB = 56, // GenericOpcodes.td:308
72 G_MUL = 57, // GenericOpcodes.td:316
73 G_SDIV = 58, // GenericOpcodes.td:324
74 G_UDIV = 59, // GenericOpcodes.td:332
75 G_SREM = 60, // GenericOpcodes.td:340
76 G_UREM = 61, // GenericOpcodes.td:348
77 G_SDIVREM = 62, // GenericOpcodes.td:356
78 G_UDIVREM = 63, // GenericOpcodes.td:364
79 G_AND = 64, // GenericOpcodes.td:372
80 G_OR = 65, // GenericOpcodes.td:380
81 G_XOR = 66, // GenericOpcodes.td:388
82 G_ABDS = 67, // GenericOpcodes.td:417
83 G_ABDU = 68, // GenericOpcodes.td:425
84 G_UAVGFLOOR = 69, // GenericOpcodes.td:433
85 G_UAVGCEIL = 70, // GenericOpcodes.td:440
86 G_SAVGFLOOR = 71, // GenericOpcodes.td:447
87 G_SAVGCEIL = 72, // GenericOpcodes.td:454
88 G_IMPLICIT_DEF = 73, // GenericOpcodes.td:110
89 G_PHI = 74, // GenericOpcodes.td:116
90 G_FRAME_INDEX = 75, // GenericOpcodes.td:122
91 G_GLOBAL_VALUE = 76, // GenericOpcodes.td:128
92 G_PTRAUTH_GLOBAL_VALUE = 77, // GenericOpcodes.td:134
93 G_CONSTANT_POOL = 78, // GenericOpcodes.td:140
94 G_EXTRACT = 79, // GenericOpcodes.td:1472
95 G_UNMERGE_VALUES = 80, // GenericOpcodes.td:1484
96 G_INSERT = 81, // GenericOpcodes.td:1492
97 G_MERGE_VALUES = 82, // GenericOpcodes.td:1502
98 G_BUILD_VECTOR = 83, // GenericOpcodes.td:1521
99 G_BUILD_VECTOR_TRUNC = 84, // GenericOpcodes.td:1530
100 G_CONCAT_VECTORS = 85, // GenericOpcodes.td:1537
101 G_PTRTOINT = 86, // GenericOpcodes.td:152
102 G_INTTOPTR = 87, // GenericOpcodes.td:146
103 G_BITCAST = 88, // GenericOpcodes.td:158
104 G_FREEZE = 89, // GenericOpcodes.td:277
105 G_CONSTANT_FOLD_BARRIER = 90, // GenericOpcodes.td:1879
106 G_INTRINSIC_FPTRUNC_ROUND = 91, // GenericOpcodes.td:1263
107 G_INTRINSIC_TRUNC = 92, // GenericOpcodes.td:1269
108 G_INTRINSIC_ROUND = 93, // GenericOpcodes.td:1275
109 G_INTRINSIC_LRINT = 94, // GenericOpcodes.td:1281
110 G_INTRINSIC_LLRINT = 95, // GenericOpcodes.td:1287
111 G_INTRINSIC_ROUNDEVEN = 96, // GenericOpcodes.td:1293
112 G_READCYCLECOUNTER = 97, // GenericOpcodes.td:1299
113 G_READSTEADYCOUNTER = 98, // GenericOpcodes.td:1305
114 G_LOAD = 99, // GenericOpcodes.td:1332
115 G_SEXTLOAD = 100, // GenericOpcodes.td:1340
116 G_ZEXTLOAD = 101, // GenericOpcodes.td:1348
117 G_INDEXED_LOAD = 102, // GenericOpcodes.td:1358
118 G_INDEXED_SEXTLOAD = 103, // GenericOpcodes.td:1366
119 G_INDEXED_ZEXTLOAD = 104, // GenericOpcodes.td:1374
120 G_STORE = 105, // GenericOpcodes.td:1382
121 G_INDEXED_STORE = 106, // GenericOpcodes.td:1390
122 G_ATOMIC_CMPXCHG_WITH_SUCCESS = 107, // GenericOpcodes.td:1400
123 G_ATOMIC_CMPXCHG = 108, // GenericOpcodes.td:1410
124 G_ATOMICRMW_XCHG = 109, // GenericOpcodes.td:1428
125 G_ATOMICRMW_ADD = 110, // GenericOpcodes.td:1429
126 G_ATOMICRMW_SUB = 111, // GenericOpcodes.td:1430
127 G_ATOMICRMW_AND = 112, // GenericOpcodes.td:1431
128 G_ATOMICRMW_NAND = 113, // GenericOpcodes.td:1432
129 G_ATOMICRMW_OR = 114, // GenericOpcodes.td:1433
130 G_ATOMICRMW_XOR = 115, // GenericOpcodes.td:1434
131 G_ATOMICRMW_MAX = 116, // GenericOpcodes.td:1435
132 G_ATOMICRMW_MIN = 117, // GenericOpcodes.td:1436
133 G_ATOMICRMW_UMAX = 118, // GenericOpcodes.td:1437
134 G_ATOMICRMW_UMIN = 119, // GenericOpcodes.td:1438
135 G_ATOMICRMW_FADD = 120, // GenericOpcodes.td:1439
136 G_ATOMICRMW_FSUB = 121, // GenericOpcodes.td:1440
137 G_ATOMICRMW_FMAX = 122, // GenericOpcodes.td:1441
138 G_ATOMICRMW_FMIN = 123, // GenericOpcodes.td:1442
139 G_ATOMICRMW_FMAXIMUM = 124, // GenericOpcodes.td:1443
140 G_ATOMICRMW_FMINIMUM = 125, // GenericOpcodes.td:1444
141 G_ATOMICRMW_UINC_WRAP = 126, // GenericOpcodes.td:1445
142 G_ATOMICRMW_UDEC_WRAP = 127, // GenericOpcodes.td:1446
143 G_ATOMICRMW_USUB_COND = 128, // GenericOpcodes.td:1447
144 G_ATOMICRMW_USUB_SAT = 129, // GenericOpcodes.td:1448
145 G_FENCE = 130, // GenericOpcodes.td:1450
146 G_PREFETCH = 131, // GenericOpcodes.td:1457
147 G_BRCOND = 132, // GenericOpcodes.td:1592
148 G_BRINDIRECT = 133, // GenericOpcodes.td:1601
149 G_INVOKE_REGION_START = 134, // GenericOpcodes.td:1624
150 G_INTRINSIC = 135, // GenericOpcodes.td:1544
151 G_INTRINSIC_W_SIDE_EFFECTS = 136, // GenericOpcodes.td:1551
152 G_INTRINSIC_CONVERGENT = 137, // GenericOpcodes.td:1560
153 G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 138, // GenericOpcodes.td:1568
154 G_ANYEXT = 139, // GenericOpcodes.td:44
155 G_TRUNC = 140, // GenericOpcodes.td:83
156 G_TRUNC_SSAT_S = 141, // GenericOpcodes.td:90
157 G_TRUNC_SSAT_U = 142, // GenericOpcodes.td:97
158 G_TRUNC_USAT_U = 143, // GenericOpcodes.td:104
159 G_CONSTANT = 144, // GenericOpcodes.td:165
160 G_FCONSTANT = 145, // GenericOpcodes.td:172
161 G_VASTART = 146, // GenericOpcodes.td:178
162 G_VAARG = 147, // GenericOpcodes.td:185
163 G_SEXT = 148, // GenericOpcodes.td:52
164 G_SEXT_INREG = 149, // GenericOpcodes.td:66
165 G_ZEXT = 150, // GenericOpcodes.td:74
166 G_SHL = 151, // GenericOpcodes.td:396
167 G_LSHR = 152, // GenericOpcodes.td:403
168 G_ASHR = 153, // GenericOpcodes.td:410
169 G_FSHL = 154, // GenericOpcodes.td:462
170 G_FSHR = 155, // GenericOpcodes.td:470
171 G_ROTR = 156, // GenericOpcodes.td:477
172 G_ROTL = 157, // GenericOpcodes.td:484
173 G_ICMP = 158, // GenericOpcodes.td:491
174 G_FCMP = 159, // GenericOpcodes.td:498
175 G_SCMP = 160, // GenericOpcodes.td:505
176 G_UCMP = 161, // GenericOpcodes.td:512
177 G_SELECT = 162, // GenericOpcodes.td:519
178 G_UADDO = 163, // GenericOpcodes.td:584
179 G_UADDE = 164, // GenericOpcodes.td:592
180 G_USUBO = 165, // GenericOpcodes.td:614
181 G_USUBE = 166, // GenericOpcodes.td:620
182 G_SADDO = 167, // GenericOpcodes.td:599
183 G_SADDE = 168, // GenericOpcodes.td:607
184 G_SSUBO = 169, // GenericOpcodes.td:627
185 G_SSUBE = 170, // GenericOpcodes.td:634
186 G_UMULO = 171, // GenericOpcodes.td:641
187 G_SMULO = 172, // GenericOpcodes.td:649
188 G_UMULH = 173, // GenericOpcodes.td:658
189 G_SMULH = 174, // GenericOpcodes.td:667
190 G_UADDSAT = 175, // GenericOpcodes.td:679
191 G_SADDSAT = 176, // GenericOpcodes.td:687
192 G_USUBSAT = 177, // GenericOpcodes.td:695
193 G_SSUBSAT = 178, // GenericOpcodes.td:703
194 G_USHLSAT = 179, // GenericOpcodes.td:711
195 G_SSHLSAT = 180, // GenericOpcodes.td:719
196 G_SMULFIX = 181, // GenericOpcodes.td:731
197 G_UMULFIX = 182, // GenericOpcodes.td:738
198 G_SMULFIXSAT = 183, // GenericOpcodes.td:748
199 G_UMULFIXSAT = 184, // GenericOpcodes.td:755
200 G_SDIVFIX = 185, // GenericOpcodes.td:766
201 G_UDIVFIX = 186, // GenericOpcodes.td:773
202 G_SDIVFIXSAT = 187, // GenericOpcodes.td:783
203 G_UDIVFIXSAT = 188, // GenericOpcodes.td:790
204 G_FADD = 189, // GenericOpcodes.td:963
205 G_FSUB = 190, // GenericOpcodes.td:971
206 G_FMUL = 191, // GenericOpcodes.td:979
207 G_FMA = 192, // GenericOpcodes.td:988
208 G_FMAD = 193, // GenericOpcodes.td:997
209 G_FDIV = 194, // GenericOpcodes.td:1005
210 G_FREM = 195, // GenericOpcodes.td:1012
211 G_FMODF = 196, // GenericOpcodes.td:1019
212 G_FPOW = 197, // GenericOpcodes.td:1026
213 G_FPOWI = 198, // GenericOpcodes.td:1033
214 G_FEXP = 199, // GenericOpcodes.td:1040
215 G_FEXP2 = 200, // GenericOpcodes.td:1047
216 G_FEXP10 = 201, // GenericOpcodes.td:1054
217 G_FLOG = 202, // GenericOpcodes.td:1061
218 G_FLOG2 = 203, // GenericOpcodes.td:1068
219 G_FLOG10 = 204, // GenericOpcodes.td:1075
220 G_FLDEXP = 205, // GenericOpcodes.td:1082
221 G_FFREXP = 206, // GenericOpcodes.td:1089
222 G_FNEG = 207, // GenericOpcodes.td:801
223 G_FPEXT = 208, // GenericOpcodes.td:807
224 G_FPTRUNC = 209, // GenericOpcodes.td:813
225 G_FPTOSI = 210, // GenericOpcodes.td:819
226 G_FPTOUI = 211, // GenericOpcodes.td:825
227 G_SITOFP = 212, // GenericOpcodes.td:831
228 G_UITOFP = 213, // GenericOpcodes.td:837
229 G_FPTOSI_SAT = 214, // GenericOpcodes.td:843
230 G_FPTOUI_SAT = 215, // GenericOpcodes.td:849
231 G_FABS = 216, // GenericOpcodes.td:855
232 G_FCOPYSIGN = 217, // GenericOpcodes.td:861
233 G_IS_FPCLASS = 218, // GenericOpcodes.td:874
234 G_FCANONICALIZE = 219, // GenericOpcodes.td:867
235 G_FMINNUM = 220, // GenericOpcodes.td:887
236 G_FMAXNUM = 221, // GenericOpcodes.td:894
237 G_FMINNUM_IEEE = 222, // GenericOpcodes.td:912
238 G_FMAXNUM_IEEE = 223, // GenericOpcodes.td:919
239 G_FMINIMUM = 224, // GenericOpcodes.td:929
240 G_FMAXIMUM = 225, // GenericOpcodes.td:936
241 G_FMINIMUMNUM = 226, // GenericOpcodes.td:944
242 G_FMAXIMUMNUM = 227, // GenericOpcodes.td:951
243 G_GET_FPENV = 228, // GenericOpcodes.td:1219
244 G_SET_FPENV = 229, // GenericOpcodes.td:1226
245 G_RESET_FPENV = 230, // GenericOpcodes.td:1233
246 G_GET_FPMODE = 231, // GenericOpcodes.td:1240
247 G_SET_FPMODE = 232, // GenericOpcodes.td:1247
248 G_RESET_FPMODE = 233, // GenericOpcodes.td:1254
249 G_GET_ROUNDING = 234, // GenericOpcodes.td:1311
250 G_SET_ROUNDING = 235, // GenericOpcodes.td:1317
251 G_PTR_ADD = 236, // GenericOpcodes.td:526
252 G_PTRMASK = 237, // GenericOpcodes.td:534
253 G_SMIN = 238, // GenericOpcodes.td:541
254 G_SMAX = 239, // GenericOpcodes.td:549
255 G_UMIN = 240, // GenericOpcodes.td:557
256 G_UMAX = 241, // GenericOpcodes.td:565
257 G_ABS = 242, // GenericOpcodes.td:573
258 G_LROUND = 243, // GenericOpcodes.td:283
259 G_LLROUND = 244, // GenericOpcodes.td:289
260 G_BR = 245, // GenericOpcodes.td:1582
261 G_BRJT = 246, // GenericOpcodes.td:1612
262 G_VSCALE = 247, // GenericOpcodes.td:1512
263 G_INSERT_SUBVECTOR = 248, // GenericOpcodes.td:1656
264 G_EXTRACT_SUBVECTOR = 249, // GenericOpcodes.td:1663
265 G_INSERT_VECTOR_ELT = 250, // GenericOpcodes.td:1670
266 G_EXTRACT_VECTOR_ELT = 251, // GenericOpcodes.td:1677
267 G_SHUFFLE_VECTOR = 252, // GenericOpcodes.td:1687
268 G_SPLAT_VECTOR = 253, // GenericOpcodes.td:1694
269 G_STEP_VECTOR = 254, // GenericOpcodes.td:1701
270 G_VECTOR_COMPRESS = 255, // GenericOpcodes.td:1708
271 G_CTTZ = 256, // GenericOpcodes.td:205
272 G_CTTZ_ZERO_UNDEF = 257, // GenericOpcodes.td:211
273 G_CTLZ = 258, // GenericOpcodes.td:193
274 G_CTLZ_ZERO_UNDEF = 259, // GenericOpcodes.td:199
275 G_CTLS = 260, // GenericOpcodes.td:217
276 G_CTPOP = 261, // GenericOpcodes.td:223
277 G_BSWAP = 262, // GenericOpcodes.td:229
278 G_BITREVERSE = 263, // GenericOpcodes.td:235
279 G_FCEIL = 264, // GenericOpcodes.td:1096
280 G_FCOS = 265, // GenericOpcodes.td:1103
281 G_FSIN = 266, // GenericOpcodes.td:1110
282 G_FSINCOS = 267, // GenericOpcodes.td:1117
283 G_FTAN = 268, // GenericOpcodes.td:1124
284 G_FACOS = 269, // GenericOpcodes.td:1131
285 G_FASIN = 270, // GenericOpcodes.td:1138
286 G_FATAN = 271, // GenericOpcodes.td:1145
287 G_FATAN2 = 272, // GenericOpcodes.td:1152
288 G_FCOSH = 273, // GenericOpcodes.td:1159
289 G_FSINH = 274, // GenericOpcodes.td:1166
290 G_FTANH = 275, // GenericOpcodes.td:1173
291 G_FSQRT = 276, // GenericOpcodes.td:1183
292 G_FFLOOR = 277, // GenericOpcodes.td:1190
293 G_FRINT = 278, // GenericOpcodes.td:1197
294 G_FNEARBYINT = 279, // GenericOpcodes.td:1204
295 G_ADDRSPACE_CAST = 280, // GenericOpcodes.td:241
296 G_BLOCK_ADDR = 281, // GenericOpcodes.td:247
297 G_JUMP_TABLE = 282, // GenericOpcodes.td:253
298 G_DYN_STACKALLOC = 283, // GenericOpcodes.td:259
299 G_STACKSAVE = 284, // GenericOpcodes.td:265
300 G_STACKRESTORE = 285, // GenericOpcodes.td:271
301 G_STRICT_FADD = 286, // GenericOpcodes.td:1758
302 G_STRICT_FSUB = 287, // GenericOpcodes.td:1759
303 G_STRICT_FMUL = 288, // GenericOpcodes.td:1760
304 G_STRICT_FDIV = 289, // GenericOpcodes.td:1761
305 G_STRICT_FREM = 290, // GenericOpcodes.td:1762
306 G_STRICT_FMA = 291, // GenericOpcodes.td:1763
307 G_STRICT_FSQRT = 292, // GenericOpcodes.td:1764
308 G_STRICT_FLDEXP = 293, // GenericOpcodes.td:1765
309 G_READ_REGISTER = 294, // GenericOpcodes.td:1631
310 G_WRITE_REGISTER = 295, // GenericOpcodes.td:1641
311 G_MEMCPY = 296, // GenericOpcodes.td:1771
312 G_MEMCPY_INLINE = 297, // GenericOpcodes.td:1779
313 G_MEMMOVE = 298, // GenericOpcodes.td:1787
314 G_MEMSET = 299, // GenericOpcodes.td:1795
315 G_BZERO = 300, // GenericOpcodes.td:1802
316 G_TRAP = 301, // GenericOpcodes.td:1812
317 G_DEBUGTRAP = 302, // GenericOpcodes.td:1819
318 G_UBSANTRAP = 303, // GenericOpcodes.td:1825
319 G_VECREDUCE_SEQ_FADD = 304, // GenericOpcodes.td:1724
320 G_VECREDUCE_SEQ_FMUL = 305, // GenericOpcodes.td:1730
321 G_VECREDUCE_FADD = 306, // GenericOpcodes.td:1736
322 G_VECREDUCE_FMUL = 307, // GenericOpcodes.td:1737
323 G_VECREDUCE_FMAX = 308, // GenericOpcodes.td:1739
324 G_VECREDUCE_FMIN = 309, // GenericOpcodes.td:1740
325 G_VECREDUCE_FMAXIMUM = 310, // GenericOpcodes.td:1741
326 G_VECREDUCE_FMINIMUM = 311, // GenericOpcodes.td:1742
327 G_VECREDUCE_ADD = 312, // GenericOpcodes.td:1744
328 G_VECREDUCE_MUL = 313, // GenericOpcodes.td:1745
329 G_VECREDUCE_AND = 314, // GenericOpcodes.td:1746
330 G_VECREDUCE_OR = 315, // GenericOpcodes.td:1747
331 G_VECREDUCE_XOR = 316, // GenericOpcodes.td:1748
332 G_VECREDUCE_SMAX = 317, // GenericOpcodes.td:1749
333 G_VECREDUCE_SMIN = 318, // GenericOpcodes.td:1750
334 G_VECREDUCE_UMAX = 319, // GenericOpcodes.td:1751
335 G_VECREDUCE_UMIN = 320, // GenericOpcodes.td:1752
336 G_SBFX = 321, // GenericOpcodes.td:1837
337 G_UBFX = 322, // GenericOpcodes.td:1845
338 ADD16mc = 323, // MSP430InstrInfo.td:499
339 ADD16mi = 324, // MSP430InstrInfo.td:505
340 ADD16mm = 325, // MSP430InstrInfo.td:512
341 ADD16mn = 326, // MSP430InstrInfo.td:518
342 ADD16mp = 327, // MSP430InstrInfo.td:522
343 ADD16mr = 328, // MSP430InstrInfo.td:493
344 ADD16rc = 329, // MSP430InstrInfo.td:480
345 ADD16ri = 330, // MSP430InstrInfo.td:486
346 ADD16rm = 331, // MSP430InstrInfo.td:462
347 ADD16rn = 332, // MSP430InstrInfo.td:467
348 ADD16rp = 333, // MSP430InstrInfo.td:474
349 ADD16rr = 334, // MSP430InstrInfo.td:455
350 ADD8mc = 335, // MSP430InstrInfo.td:496
351 ADD8mi = 336, // MSP430InstrInfo.td:502
352 ADD8mm = 337, // MSP430InstrInfo.td:508
353 ADD8mn = 338, // MSP430InstrInfo.td:516
354 ADD8mp = 339, // MSP430InstrInfo.td:520
355 ADD8mr = 340, // MSP430InstrInfo.td:490
356 ADD8rc = 341, // MSP430InstrInfo.td:477
357 ADD8ri = 342, // MSP430InstrInfo.td:483
358 ADD8rm = 343, // MSP430InstrInfo.td:459
359 ADD8rn = 344, // MSP430InstrInfo.td:465
360 ADD8rp = 345, // MSP430InstrInfo.td:472
361 ADD8rr = 346, // MSP430InstrInfo.td:452
362 ADDC16mc = 347, // MSP430InstrInfo.td:499
363 ADDC16mi = 348, // MSP430InstrInfo.td:505
364 ADDC16mm = 349, // MSP430InstrInfo.td:512
365 ADDC16mn = 350, // MSP430InstrInfo.td:518
366 ADDC16mp = 351, // MSP430InstrInfo.td:522
367 ADDC16mr = 352, // MSP430InstrInfo.td:493
368 ADDC16rc = 353, // MSP430InstrInfo.td:480
369 ADDC16ri = 354, // MSP430InstrInfo.td:486
370 ADDC16rm = 355, // MSP430InstrInfo.td:462
371 ADDC16rn = 356, // MSP430InstrInfo.td:467
372 ADDC16rp = 357, // MSP430InstrInfo.td:474
373 ADDC16rr = 358, // MSP430InstrInfo.td:455
374 ADDC8mc = 359, // MSP430InstrInfo.td:496
375 ADDC8mi = 360, // MSP430InstrInfo.td:502
376 ADDC8mm = 361, // MSP430InstrInfo.td:508
377 ADDC8mn = 362, // MSP430InstrInfo.td:516
378 ADDC8mp = 363, // MSP430InstrInfo.td:520
379 ADDC8mr = 364, // MSP430InstrInfo.td:490
380 ADDC8rc = 365, // MSP430InstrInfo.td:477
381 ADDC8ri = 366, // MSP430InstrInfo.td:483
382 ADDC8rm = 367, // MSP430InstrInfo.td:459
383 ADDC8rn = 368, // MSP430InstrInfo.td:465
384 ADDC8rp = 369, // MSP430InstrInfo.td:472
385 ADDC8rr = 370, // MSP430InstrInfo.td:452
386 ADDframe = 371, // MSP430InstrInfo.td:183
387 ADJCALLSTACKDOWN = 372, // MSP430InstrInfo.td:174
388 ADJCALLSTACKUP = 373, // MSP430InstrInfo.td:177
389 AND16mc = 374, // MSP430InstrInfo.td:499
390 AND16mi = 375, // MSP430InstrInfo.td:505
391 AND16mm = 376, // MSP430InstrInfo.td:512
392 AND16mn = 377, // MSP430InstrInfo.td:518
393 AND16mp = 378, // MSP430InstrInfo.td:522
394 AND16mr = 379, // MSP430InstrInfo.td:493
395 AND16rc = 380, // MSP430InstrInfo.td:480
396 AND16ri = 381, // MSP430InstrInfo.td:486
397 AND16rm = 382, // MSP430InstrInfo.td:462
398 AND16rn = 383, // MSP430InstrInfo.td:467
399 AND16rp = 384, // MSP430InstrInfo.td:474
400 AND16rr = 385, // MSP430InstrInfo.td:455
401 AND8mc = 386, // MSP430InstrInfo.td:496
402 AND8mi = 387, // MSP430InstrInfo.td:502
403 AND8mm = 388, // MSP430InstrInfo.td:508
404 AND8mn = 389, // MSP430InstrInfo.td:516
405 AND8mp = 390, // MSP430InstrInfo.td:520
406 AND8mr = 391, // MSP430InstrInfo.td:490
407 AND8rc = 392, // MSP430InstrInfo.td:477
408 AND8ri = 393, // MSP430InstrInfo.td:483
409 AND8rm = 394, // MSP430InstrInfo.td:459
410 AND8rn = 395, // MSP430InstrInfo.td:465
411 AND8rp = 396, // MSP430InstrInfo.td:472
412 AND8rr = 397, // MSP430InstrInfo.td:452
413 BIC16mc = 398, // MSP430InstrInfo.td:499
414 BIC16mi = 399, // MSP430InstrInfo.td:505
415 BIC16mm = 400, // MSP430InstrInfo.td:512
416 BIC16mn = 401, // MSP430InstrInfo.td:518
417 BIC16mp = 402, // MSP430InstrInfo.td:522
418 BIC16mr = 403, // MSP430InstrInfo.td:493
419 BIC16rc = 404, // MSP430InstrInfo.td:480
420 BIC16ri = 405, // MSP430InstrInfo.td:486
421 BIC16rm = 406, // MSP430InstrInfo.td:462
422 BIC16rn = 407, // MSP430InstrInfo.td:467
423 BIC16rp = 408, // MSP430InstrInfo.td:474
424 BIC16rr = 409, // MSP430InstrInfo.td:455
425 BIC8mc = 410, // MSP430InstrInfo.td:496
426 BIC8mi = 411, // MSP430InstrInfo.td:502
427 BIC8mm = 412, // MSP430InstrInfo.td:508
428 BIC8mn = 413, // MSP430InstrInfo.td:516
429 BIC8mp = 414, // MSP430InstrInfo.td:520
430 BIC8mr = 415, // MSP430InstrInfo.td:490
431 BIC8rc = 416, // MSP430InstrInfo.td:477
432 BIC8ri = 417, // MSP430InstrInfo.td:483
433 BIC8rm = 418, // MSP430InstrInfo.td:459
434 BIC8rn = 419, // MSP430InstrInfo.td:465
435 BIC8rp = 420, // MSP430InstrInfo.td:472
436 BIC8rr = 421, // MSP430InstrInfo.td:452
437 BIS16mc = 422, // MSP430InstrInfo.td:499
438 BIS16mi = 423, // MSP430InstrInfo.td:505
439 BIS16mm = 424, // MSP430InstrInfo.td:512
440 BIS16mn = 425, // MSP430InstrInfo.td:518
441 BIS16mp = 426, // MSP430InstrInfo.td:522
442 BIS16mr = 427, // MSP430InstrInfo.td:493
443 BIS16rc = 428, // MSP430InstrInfo.td:480
444 BIS16ri = 429, // MSP430InstrInfo.td:486
445 BIS16rm = 430, // MSP430InstrInfo.td:462
446 BIS16rn = 431, // MSP430InstrInfo.td:467
447 BIS16rp = 432, // MSP430InstrInfo.td:474
448 BIS16rr = 433, // MSP430InstrInfo.td:455
449 BIS8mc = 434, // MSP430InstrInfo.td:496
450 BIS8mi = 435, // MSP430InstrInfo.td:502
451 BIS8mm = 436, // MSP430InstrInfo.td:508
452 BIS8mn = 437, // MSP430InstrInfo.td:516
453 BIS8mp = 438, // MSP430InstrInfo.td:520
454 BIS8mr = 439, // MSP430InstrInfo.td:490
455 BIS8rc = 440, // MSP430InstrInfo.td:477
456 BIS8ri = 441, // MSP430InstrInfo.td:483
457 BIS8rm = 442, // MSP430InstrInfo.td:459
458 BIS8rn = 443, // MSP430InstrInfo.td:465
459 BIS8rp = 444, // MSP430InstrInfo.td:472
460 BIS8rr = 445, // MSP430InstrInfo.td:452
461 BIT16mc = 446, // MSP430InstrInfo.td:861
462 BIT16mi = 447, // MSP430InstrInfo.td:870
463 BIT16mm = 448, // MSP430InstrInfo.td:881
464 BIT16mn = 449, // MSP430InstrInfo.td:889
465 BIT16mp = 450, // MSP430InstrInfo.td:894
466 BIT16mr = 451, // MSP430InstrInfo.td:852
467 BIT16rc = 452, // MSP430InstrInfo.td:815
468 BIT16ri = 453, // MSP430InstrInfo.td:824
469 BIT16rm = 454, // MSP430InstrInfo.td:833
470 BIT16rn = 455, // MSP430InstrInfo.td:840
471 BIT16rp = 456, // MSP430InstrInfo.td:845
472 BIT16rr = 457, // MSP430InstrInfo.td:806
473 BIT8mc = 458, // MSP430InstrInfo.td:857
474 BIT8mi = 459, // MSP430InstrInfo.td:866
475 BIT8mm = 460, // MSP430InstrInfo.td:875
476 BIT8mn = 461, // MSP430InstrInfo.td:887
477 BIT8mp = 462, // MSP430InstrInfo.td:892
478 BIT8mr = 463, // MSP430InstrInfo.td:848
479 BIT8rc = 464, // MSP430InstrInfo.td:811
480 BIT8ri = 465, // MSP430InstrInfo.td:820
481 BIT8rm = 466, // MSP430InstrInfo.td:829
482 BIT8rn = 467, // MSP430InstrInfo.td:838
483 BIT8rp = 468, // MSP430InstrInfo.td:843
484 BIT8rr = 469, // MSP430InstrInfo.td:802
485 Bi = 470, // MSP430InstrInfo.td:255
486 Bm = 471, // MSP430InstrInfo.td:261
487 Br = 472, // MSP430InstrInfo.td:258
488 CALLi = 473, // MSP430InstrInfo.td:284
489 CALLm = 474, // MSP430InstrInfo.td:290
490 CALLn = 475, // MSP430InstrInfo.td:293
491 CALLp = 476, // MSP430InstrInfo.td:294
492 CALLr = 477, // MSP430InstrInfo.td:287
493 CMP16mc = 478, // MSP430InstrInfo.td:738
494 CMP16mi = 479, // MSP430InstrInfo.td:748
495 CMP16mm = 480, // MSP430InstrInfo.td:785
496 CMP16mn = 481, // MSP430InstrInfo.td:791
497 CMP16mp = 482, // MSP430InstrInfo.td:796
498 CMP16mr = 483, // MSP430InstrInfo.td:777
499 CMP16rc = 484, // MSP430InstrInfo.td:720
500 CMP16ri = 485, // MSP430InstrInfo.td:729
501 CMP16rm = 486, // MSP430InstrInfo.td:758
502 CMP16rn = 487, // MSP430InstrInfo.td:765
503 CMP16rp = 488, // MSP430InstrInfo.td:770
504 CMP16rr = 489, // MSP430InstrInfo.td:711
505 CMP8mc = 490, // MSP430InstrInfo.td:734
506 CMP8mi = 491, // MSP430InstrInfo.td:743
507 CMP8mm = 492, // MSP430InstrInfo.td:781
508 CMP8mn = 493, // MSP430InstrInfo.td:789
509 CMP8mp = 494, // MSP430InstrInfo.td:794
510 CMP8mr = 495, // MSP430InstrInfo.td:773
511 CMP8rc = 496, // MSP430InstrInfo.td:716
512 CMP8ri = 497, // MSP430InstrInfo.td:725
513 CMP8rm = 498, // MSP430InstrInfo.td:754
514 CMP8rn = 499, // MSP430InstrInfo.td:763
515 CMP8rp = 500, // MSP430InstrInfo.td:768
516 CMP8rr = 501, // MSP430InstrInfo.td:707
517 DADD16mc = 502, // MSP430InstrInfo.td:499
518 DADD16mi = 503, // MSP430InstrInfo.td:505
519 DADD16mm = 504, // MSP430InstrInfo.td:512
520 DADD16mn = 505, // MSP430InstrInfo.td:518
521 DADD16mp = 506, // MSP430InstrInfo.td:522
522 DADD16mr = 507, // MSP430InstrInfo.td:493
523 DADD16rc = 508, // MSP430InstrInfo.td:480
524 DADD16ri = 509, // MSP430InstrInfo.td:486
525 DADD16rm = 510, // MSP430InstrInfo.td:462
526 DADD16rn = 511, // MSP430InstrInfo.td:467
527 DADD16rp = 512, // MSP430InstrInfo.td:474
528 DADD16rr = 513, // MSP430InstrInfo.td:455
529 DADD8mc = 514, // MSP430InstrInfo.td:496
530 DADD8mi = 515, // MSP430InstrInfo.td:502
531 DADD8mm = 516, // MSP430InstrInfo.td:508
532 DADD8mn = 517, // MSP430InstrInfo.td:516
533 DADD8mp = 518, // MSP430InstrInfo.td:520
534 DADD8mr = 519, // MSP430InstrInfo.td:490
535 DADD8rc = 520, // MSP430InstrInfo.td:477
536 DADD8ri = 521, // MSP430InstrInfo.td:483
537 DADD8rm = 522, // MSP430InstrInfo.td:459
538 DADD8rn = 523, // MSP430InstrInfo.td:465
539 DADD8rp = 524, // MSP430InstrInfo.td:472
540 DADD8rr = 525, // MSP430InstrInfo.td:452
541 JCC = 526, // MSP430InstrInfo.td:269
542 JMP = 527, // MSP430InstrInfo.td:248
543 MOV16mc = 528, // MSP430InstrInfo.td:407
544 MOV16mi = 529, // MSP430InstrInfo.td:416
545 MOV16mm = 530, // MSP430InstrInfo.td:434
546 MOV16mn = 531, // MSP430InstrInfo.td:441
547 MOV16mr = 532, // MSP430InstrInfo.td:425
548 MOV16rc = 533, // MSP430InstrInfo.td:335
549 MOV16ri = 534, // MSP430InstrInfo.td:343
550 MOV16rm = 535, // MSP430InstrInfo.td:354
551 MOV16rn = 536, // MSP430InstrInfo.td:362
552 MOV16rp = 537, // MSP430InstrInfo.td:383
553 MOV16rr = 538, // MSP430InstrInfo.td:324
554 MOV8mc = 539, // MSP430InstrInfo.td:403
555 MOV8mi = 540, // MSP430InstrInfo.td:412
556 MOV8mm = 541, // MSP430InstrInfo.td:430
557 MOV8mn = 542, // MSP430InstrInfo.td:439
558 MOV8mr = 543, // MSP430InstrInfo.td:421
559 MOV8rc = 544, // MSP430InstrInfo.td:331
560 MOV8ri = 545, // MSP430InstrInfo.td:339
561 MOV8rm = 546, // MSP430InstrInfo.td:350
562 MOV8rn = 547, // MSP430InstrInfo.td:358
563 MOV8rp = 548, // MSP430InstrInfo.td:380
564 MOV8rr = 549, // MSP430InstrInfo.td:320
565 MOVZX16rm8 = 550, // MSP430InstrInfo.td:373
566 MOVZX16rr8 = 551, // MSP430InstrInfo.td:369
567 POP16r = 552, // MSP430InstrInfo.td:302
568 PUSH16c = 553, // MSP430InstrInfo.td:311
569 PUSH16i = 554, // MSP430InstrInfo.td:312
570 PUSH16r = 555, // MSP430InstrInfo.td:310
571 PUSH8r = 556, // MSP430InstrInfo.td:309
572 RET = 557, // MSP430InstrInfo.td:229
573 RETI = 558, // MSP430InstrInfo.td:235
574 RRA16m = 559, // MSP430InstrInfo.td:661
575 RRA16n = 560, // MSP430InstrInfo.td:667
576 RRA16p = 561, // MSP430InstrInfo.td:669
577 RRA16r = 562, // MSP430InstrInfo.td:619
578 RRA8m = 563, // MSP430InstrInfo.td:657
579 RRA8n = 564, // MSP430InstrInfo.td:666
580 RRA8p = 565, // MSP430InstrInfo.td:668
581 RRA8r = 566, // MSP430InstrInfo.td:615
582 RRC16m = 567, // MSP430InstrInfo.td:676
583 RRC16n = 568, // MSP430InstrInfo.td:682
584 RRC16p = 569, // MSP430InstrInfo.td:684
585 RRC16r = 570, // MSP430InstrInfo.td:629
586 RRC8m = 571, // MSP430InstrInfo.td:672
587 RRC8n = 572, // MSP430InstrInfo.td:681
588 RRC8p = 573, // MSP430InstrInfo.td:683
589 RRC8r = 574, // MSP430InstrInfo.td:625
590 Rrcl16 = 575, // MSP430InstrInfo.td:219
591 Rrcl8 = 576, // MSP430InstrInfo.td:217
592 SEXT16m = 577, // MSP430InstrInfo.td:688
593 SEXT16n = 578, // MSP430InstrInfo.td:693
594 SEXT16p = 579, // MSP430InstrInfo.td:694
595 SEXT16r = 580, // MSP430InstrInfo.td:635
596 SUB16mc = 581, // MSP430InstrInfo.td:499
597 SUB16mi = 582, // MSP430InstrInfo.td:505
598 SUB16mm = 583, // MSP430InstrInfo.td:512
599 SUB16mn = 584, // MSP430InstrInfo.td:518
600 SUB16mp = 585, // MSP430InstrInfo.td:522
601 SUB16mr = 586, // MSP430InstrInfo.td:493
602 SUB16rc = 587, // MSP430InstrInfo.td:480
603 SUB16ri = 588, // MSP430InstrInfo.td:486
604 SUB16rm = 589, // MSP430InstrInfo.td:462
605 SUB16rn = 590, // MSP430InstrInfo.td:467
606 SUB16rp = 591, // MSP430InstrInfo.td:474
607 SUB16rr = 592, // MSP430InstrInfo.td:455
608 SUB8mc = 593, // MSP430InstrInfo.td:496
609 SUB8mi = 594, // MSP430InstrInfo.td:502
610 SUB8mm = 595, // MSP430InstrInfo.td:508
611 SUB8mn = 596, // MSP430InstrInfo.td:516
612 SUB8mp = 597, // MSP430InstrInfo.td:520
613 SUB8mr = 598, // MSP430InstrInfo.td:490
614 SUB8rc = 599, // MSP430InstrInfo.td:477
615 SUB8ri = 600, // MSP430InstrInfo.td:483
616 SUB8rm = 601, // MSP430InstrInfo.td:459
617 SUB8rn = 602, // MSP430InstrInfo.td:465
618 SUB8rp = 603, // MSP430InstrInfo.td:472
619 SUB8rr = 604, // MSP430InstrInfo.td:452
620 SUBC16mc = 605, // MSP430InstrInfo.td:499
621 SUBC16mi = 606, // MSP430InstrInfo.td:505
622 SUBC16mm = 607, // MSP430InstrInfo.td:512
623 SUBC16mn = 608, // MSP430InstrInfo.td:518
624 SUBC16mp = 609, // MSP430InstrInfo.td:522
625 SUBC16mr = 610, // MSP430InstrInfo.td:493
626 SUBC16rc = 611, // MSP430InstrInfo.td:480
627 SUBC16ri = 612, // MSP430InstrInfo.td:486
628 SUBC16rm = 613, // MSP430InstrInfo.td:462
629 SUBC16rn = 614, // MSP430InstrInfo.td:467
630 SUBC16rp = 615, // MSP430InstrInfo.td:474
631 SUBC16rr = 616, // MSP430InstrInfo.td:455
632 SUBC8mc = 617, // MSP430InstrInfo.td:496
633 SUBC8mi = 618, // MSP430InstrInfo.td:502
634 SUBC8mm = 619, // MSP430InstrInfo.td:508
635 SUBC8mn = 620, // MSP430InstrInfo.td:516
636 SUBC8mp = 621, // MSP430InstrInfo.td:520
637 SUBC8mr = 622, // MSP430InstrInfo.td:490
638 SUBC8rc = 623, // MSP430InstrInfo.td:477
639 SUBC8ri = 624, // MSP430InstrInfo.td:483
640 SUBC8rm = 625, // MSP430InstrInfo.td:459
641 SUBC8rn = 626, // MSP430InstrInfo.td:465
642 SUBC8rp = 627, // MSP430InstrInfo.td:472
643 SUBC8rr = 628, // MSP430InstrInfo.td:452
644 SWPB16m = 629, // MSP430InstrInfo.td:698
645 SWPB16n = 630, // MSP430InstrInfo.td:702
646 SWPB16p = 631, // MSP430InstrInfo.td:703
647 SWPB16r = 632, // MSP430InstrInfo.td:648
648 Select16 = 633, // MSP430InstrInfo.td:193
649 Select8 = 634, // MSP430InstrInfo.td:189
650 Shl16 = 635, // MSP430InstrInfo.td:202
651 Shl8 = 636, // MSP430InstrInfo.td:199
652 Sra16 = 637, // MSP430InstrInfo.td:208
653 Sra8 = 638, // MSP430InstrInfo.td:205
654 Srl16 = 639, // MSP430InstrInfo.td:214
655 Srl8 = 640, // MSP430InstrInfo.td:211
656 XOR16mc = 641, // MSP430InstrInfo.td:499
657 XOR16mi = 642, // MSP430InstrInfo.td:505
658 XOR16mm = 643, // MSP430InstrInfo.td:512
659 XOR16mn = 644, // MSP430InstrInfo.td:518
660 XOR16mp = 645, // MSP430InstrInfo.td:522
661 XOR16mr = 646, // MSP430InstrInfo.td:493
662 XOR16rc = 647, // MSP430InstrInfo.td:480
663 XOR16ri = 648, // MSP430InstrInfo.td:486
664 XOR16rm = 649, // MSP430InstrInfo.td:462
665 XOR16rn = 650, // MSP430InstrInfo.td:467
666 XOR16rp = 651, // MSP430InstrInfo.td:474
667 XOR16rr = 652, // MSP430InstrInfo.td:455
668 XOR8mc = 653, // MSP430InstrInfo.td:496
669 XOR8mi = 654, // MSP430InstrInfo.td:502
670 XOR8mm = 655, // MSP430InstrInfo.td:508
671 XOR8mn = 656, // MSP430InstrInfo.td:516
672 XOR8mp = 657, // MSP430InstrInfo.td:520
673 XOR8mr = 658, // MSP430InstrInfo.td:490
674 XOR8rc = 659, // MSP430InstrInfo.td:477
675 XOR8ri = 660, // MSP430InstrInfo.td:483
676 XOR8rm = 661, // MSP430InstrInfo.td:459
677 XOR8rn = 662, // MSP430InstrInfo.td:465
678 XOR8rp = 663, // MSP430InstrInfo.td:472
679 XOR8rr = 664, // MSP430InstrInfo.td:452
680 ZEXT16r = 665, // MSP430InstrInfo.td:643
681 INSTRUCTION_LIST_END = 666
682 };
683
684} // namespace llvm::MSP430
685
686#endif // GET_INSTRINFO_ENUM
687
688#ifdef GET_INSTRINFO_SCHED_ENUM
689#undef GET_INSTRINFO_SCHED_ENUM
690
691namespace llvm::MSP430::Sched {
692
693 enum {
694 NoInstrModel = 0,
695 SCHED_LIST_END = 1
696 };
697
698} // namespace llvm::MSP430::Sched
699
700#endif // GET_INSTRINFO_SCHED_ENUM
701
702#if defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
703
704namespace llvm {
705
706struct MSP430InstrTable {
707 MCInstrDesc Insts[666];
708 static_assert(alignof(MCInstrDesc) >= alignof(MCPhysReg), "Unwanted padding between Insts and ImplicitOps");
709 MCPhysReg ImplicitOps[17];
710 char Padding[sizeof(MCOperandInfo) - sizeof ImplicitOps % sizeof(MCOperandInfo)];
711 static_assert(alignof(MCInstrDesc) >= alignof(MCOperandInfo), "Unwanted padding between Insts and OperandInfo");
712 MCOperandInfo OperandInfo[264];
713};
714} // namespace llvm
715
716#endif // defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
717
718#ifdef GET_INSTRINFO_MC_DESC
719#undef GET_INSTRINFO_MC_DESC
720
721namespace llvm {
722
723static_assert((sizeof MSP430InstrTable::ImplicitOps + sizeof MSP430InstrTable::Padding) % sizeof(MCOperandInfo) == 0);
724static constexpr unsigned MSP430OpInfoBase = (sizeof MSP430InstrTable::ImplicitOps + sizeof MSP430InstrTable::Padding) / sizeof(MCOperandInfo);
725
726extern const MSP430InstrTable MSP430Descs = {
727 {
728 { 665, 2, 1, 2, 0, 0, 0, MSP430OpInfoBase + 246, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ZEXT16r
729 { 664, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 211, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR8rr
730 { 663, 4, 2, 2, 0, 0, 1, MSP430OpInfoBase + 207, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR8rp
731 { 662, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 204, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR8rn
732 { 661, 4, 1, 4, 0, 0, 1, MSP430OpInfoBase + 200, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR8rm
733 { 660, 3, 1, 4, 0, 0, 1, MSP430OpInfoBase + 197, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR8ri
734 { 659, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 194, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR8rc
735 { 658, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 191, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR8mr
736 { 657, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 165, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR8mp
737 { 656, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 165, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR8mn
738 { 655, 4, 0, 6, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR8mm
739 { 654, 3, 0, 6, 0, 0, 1, MSP430OpInfoBase + 158, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR8mi
740 { 653, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 155, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR8mc
741 { 652, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 188, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR16rr
742 { 651, 4, 2, 2, 0, 0, 1, MSP430OpInfoBase + 184, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR16rp
743 { 650, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 181, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR16rn
744 { 649, 4, 1, 4, 0, 0, 1, MSP430OpInfoBase + 177, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR16rm
745 { 648, 3, 1, 4, 0, 0, 1, MSP430OpInfoBase + 174, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR16ri
746 { 647, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 171, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR16rc
747 { 646, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 168, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR16mr
748 { 645, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 165, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR16mp
749 { 644, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 165, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR16mn
750 { 643, 4, 0, 6, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR16mm
751 { 642, 3, 0, 6, 0, 0, 1, MSP430OpInfoBase + 158, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR16mi
752 { 641, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 155, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR16mc
753 { 640, 3, 1, 0, 0, 0, 1, MSP430OpInfoBase + 261, 0, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Srl8
754 { 639, 3, 1, 0, 0, 0, 1, MSP430OpInfoBase + 258, 0, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Srl16
755 { 638, 3, 1, 0, 0, 0, 1, MSP430OpInfoBase + 261, 0, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Sra8
756 { 637, 3, 1, 0, 0, 0, 1, MSP430OpInfoBase + 258, 0, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Sra16
757 { 636, 3, 1, 0, 0, 0, 1, MSP430OpInfoBase + 261, 0, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Shl8
758 { 635, 3, 1, 0, 0, 0, 1, MSP430OpInfoBase + 258, 0, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Shl16
759 { 634, 4, 1, 0, 0, 1, 0, MSP430OpInfoBase + 254, 0, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Select8
760 { 633, 4, 1, 0, 0, 1, 0, MSP430OpInfoBase + 250, 0, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Select16
761 { 632, 2, 1, 2, 0, 0, 0, MSP430OpInfoBase + 246, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SWPB16r
762 { 631, 1, 0, 2, 0, 0, 0, MSP430OpInfoBase + 236, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SWPB16p
763 { 630, 1, 0, 2, 0, 0, 0, MSP430OpInfoBase + 236, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SWPB16n
764 { 629, 2, 0, 4, 0, 0, 0, MSP430OpInfoBase + 234, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SWPB16m
765 { 628, 3, 1, 2, 0, 1, 1, MSP430OpInfoBase + 211, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC8rr
766 { 627, 4, 2, 2, 0, 1, 1, MSP430OpInfoBase + 207, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC8rp
767 { 626, 3, 1, 2, 0, 1, 1, MSP430OpInfoBase + 204, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC8rn
768 { 625, 4, 1, 4, 0, 1, 1, MSP430OpInfoBase + 200, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC8rm
769 { 624, 3, 1, 4, 0, 1, 1, MSP430OpInfoBase + 197, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC8ri
770 { 623, 3, 1, 2, 0, 1, 1, MSP430OpInfoBase + 194, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC8rc
771 { 622, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 191, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC8mr
772 { 621, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 165, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC8mp
773 { 620, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 165, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC8mn
774 { 619, 4, 0, 6, 0, 1, 1, MSP430OpInfoBase + 161, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC8mm
775 { 618, 3, 0, 6, 0, 1, 1, MSP430OpInfoBase + 158, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC8mi
776 { 617, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 155, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC8mc
777 { 616, 3, 1, 2, 0, 1, 1, MSP430OpInfoBase + 188, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC16rr
778 { 615, 4, 2, 2, 0, 1, 1, MSP430OpInfoBase + 184, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC16rp
779 { 614, 3, 1, 2, 0, 1, 1, MSP430OpInfoBase + 181, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC16rn
780 { 613, 4, 1, 4, 0, 1, 1, MSP430OpInfoBase + 177, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC16rm
781 { 612, 3, 1, 4, 0, 1, 1, MSP430OpInfoBase + 174, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC16ri
782 { 611, 3, 1, 2, 0, 1, 1, MSP430OpInfoBase + 171, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC16rc
783 { 610, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 168, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC16mr
784 { 609, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 165, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC16mp
785 { 608, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 165, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC16mn
786 { 607, 4, 0, 6, 0, 1, 1, MSP430OpInfoBase + 161, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC16mm
787 { 606, 3, 0, 6, 0, 1, 1, MSP430OpInfoBase + 158, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC16mi
788 { 605, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 155, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC16mc
789 { 604, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 211, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB8rr
790 { 603, 4, 2, 2, 0, 0, 1, MSP430OpInfoBase + 207, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB8rp
791 { 602, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 204, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB8rn
792 { 601, 4, 1, 4, 0, 0, 1, MSP430OpInfoBase + 200, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB8rm
793 { 600, 3, 1, 4, 0, 0, 1, MSP430OpInfoBase + 197, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB8ri
794 { 599, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 194, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB8rc
795 { 598, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 191, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB8mr
796 { 597, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 165, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB8mp
797 { 596, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 165, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB8mn
798 { 595, 4, 0, 6, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB8mm
799 { 594, 3, 0, 6, 0, 0, 1, MSP430OpInfoBase + 158, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB8mi
800 { 593, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 155, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB8mc
801 { 592, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 188, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB16rr
802 { 591, 4, 2, 2, 0, 0, 1, MSP430OpInfoBase + 184, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB16rp
803 { 590, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 181, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB16rn
804 { 589, 4, 1, 4, 0, 0, 1, MSP430OpInfoBase + 177, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB16rm
805 { 588, 3, 1, 4, 0, 0, 1, MSP430OpInfoBase + 174, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB16ri
806 { 587, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 171, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB16rc
807 { 586, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 168, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB16mr
808 { 585, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 165, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB16mp
809 { 584, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 165, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB16mn
810 { 583, 4, 0, 6, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB16mm
811 { 582, 3, 0, 6, 0, 0, 1, MSP430OpInfoBase + 158, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB16mi
812 { 581, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 155, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB16mc
813 { 580, 2, 1, 2, 0, 0, 1, MSP430OpInfoBase + 246, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SEXT16r
814 { 579, 1, 0, 2, 0, 0, 1, MSP430OpInfoBase + 236, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SEXT16p
815 { 578, 1, 0, 2, 0, 0, 1, MSP430OpInfoBase + 236, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SEXT16n
816 { 577, 2, 0, 4, 0, 0, 1, MSP430OpInfoBase + 234, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SEXT16m
817 { 576, 2, 1, 0, 0, 0, 1, MSP430OpInfoBase + 232, 0, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Rrcl8
818 { 575, 2, 1, 0, 0, 0, 1, MSP430OpInfoBase + 221, 0, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Rrcl16
819 { 574, 2, 1, 2, 0, 1, 1, MSP430OpInfoBase + 248, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RRC8r
820 { 573, 1, 0, 2, 0, 1, 1, MSP430OpInfoBase + 236, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RRC8p
821 { 572, 1, 0, 2, 0, 1, 1, MSP430OpInfoBase + 236, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RRC8n
822 { 571, 2, 0, 4, 0, 1, 1, MSP430OpInfoBase + 234, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RRC8m
823 { 570, 2, 1, 2, 0, 1, 1, MSP430OpInfoBase + 246, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RRC16r
824 { 569, 1, 0, 2, 0, 1, 1, MSP430OpInfoBase + 236, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RRC16p
825 { 568, 1, 0, 2, 0, 1, 1, MSP430OpInfoBase + 236, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RRC16n
826 { 567, 2, 0, 4, 0, 1, 1, MSP430OpInfoBase + 234, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RRC16m
827 { 566, 2, 1, 2, 0, 0, 1, MSP430OpInfoBase + 248, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RRA8r
828 { 565, 1, 0, 2, 0, 0, 1, MSP430OpInfoBase + 236, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RRA8p
829 { 564, 1, 0, 2, 0, 0, 1, MSP430OpInfoBase + 236, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RRA8n
830 { 563, 2, 0, 4, 0, 0, 1, MSP430OpInfoBase + 234, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RRA8m
831 { 562, 2, 1, 2, 0, 0, 1, MSP430OpInfoBase + 246, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RRA16r
832 { 561, 1, 0, 2, 0, 0, 1, MSP430OpInfoBase + 236, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RRA16p
833 { 560, 1, 0, 2, 0, 0, 1, MSP430OpInfoBase + 236, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RRA16n
834 { 559, 2, 0, 4, 0, 0, 1, MSP430OpInfoBase + 234, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RRA16m
835 { 558, 0, 0, 2, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RETI
836 { 557, 0, 0, 2, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RET
837 { 556, 1, 0, 2, 0, 1, 1, MSP430OpInfoBase + 245, 15, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PUSH8r
838 { 555, 1, 0, 2, 0, 1, 1, MSP430OpInfoBase + 32, 15, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PUSH16r
839 { 554, 1, 0, 4, 0, 1, 1, MSP430OpInfoBase + 1, 15, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PUSH16i
840 { 553, 1, 0, 2, 0, 1, 1, MSP430OpInfoBase + 0, 15, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PUSH16c
841 { 552, 1, 1, 2, 0, 1, 1, MSP430OpInfoBase + 32, 15, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // POP16r
842 { 551, 2, 1, 2, 0, 0, 0, MSP430OpInfoBase + 243, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOVZX16rr8
843 { 550, 3, 1, 4, 0, 0, 0, MSP430OpInfoBase + 216, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOVZX16rm8
844 { 549, 2, 1, 2, 0, 0, 0, MSP430OpInfoBase + 232, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV8rr
845 { 548, 3, 2, 2, 0, 0, 0, MSP430OpInfoBase + 240, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV8rp
846 { 547, 2, 1, 2, 0, 0, 0, MSP430OpInfoBase + 230, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV8rn
847 { 546, 3, 1, 4, 0, 0, 0, MSP430OpInfoBase + 227, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV8rm
848 { 545, 2, 1, 4, 0, 0, 0, MSP430OpInfoBase + 225, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV8ri
849 { 544, 2, 1, 2, 0, 0, 0, MSP430OpInfoBase + 223, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV8rc
850 { 543, 3, 0, 4, 0, 0, 0, MSP430OpInfoBase + 191, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV8mr
851 { 542, 3, 0, 4, 0, 0, 0, MSP430OpInfoBase + 165, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV8mn
852 { 541, 4, 0, 6, 0, 0, 0, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV8mm
853 { 540, 3, 0, 6, 0, 0, 0, MSP430OpInfoBase + 158, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV8mi
854 { 539, 3, 0, 4, 0, 0, 0, MSP430OpInfoBase + 155, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV8mc
855 { 538, 2, 1, 2, 0, 0, 0, MSP430OpInfoBase + 221, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV16rr
856 { 537, 3, 2, 2, 0, 0, 0, MSP430OpInfoBase + 237, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV16rp
857 { 536, 2, 1, 2, 0, 0, 0, MSP430OpInfoBase + 219, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV16rn
858 { 535, 3, 1, 4, 0, 0, 0, MSP430OpInfoBase + 216, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV16rm
859 { 534, 2, 1, 4, 0, 0, 0, MSP430OpInfoBase + 214, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV16ri
860 { 533, 2, 1, 2, 0, 0, 0, MSP430OpInfoBase + 38, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV16rc
861 { 532, 3, 0, 4, 0, 0, 0, MSP430OpInfoBase + 168, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV16mr
862 { 531, 3, 0, 4, 0, 0, 0, MSP430OpInfoBase + 165, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV16mn
863 { 530, 4, 0, 6, 0, 0, 0, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV16mm
864 { 529, 3, 0, 6, 0, 0, 0, MSP430OpInfoBase + 158, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV16mi
865 { 528, 3, 0, 4, 0, 0, 0, MSP430OpInfoBase + 155, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV16mc
866 { 527, 1, 0, 2, 0, 0, 0, MSP430OpInfoBase + 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JMP
867 { 526, 2, 0, 2, 0, 1, 0, MSP430OpInfoBase + 13, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JCC
868 { 525, 3, 1, 2, 0, 1, 1, MSP430OpInfoBase + 211, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD8rr
869 { 524, 4, 2, 2, 0, 1, 1, MSP430OpInfoBase + 207, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD8rp
870 { 523, 3, 1, 2, 0, 1, 1, MSP430OpInfoBase + 204, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD8rn
871 { 522, 4, 1, 4, 0, 1, 1, MSP430OpInfoBase + 200, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD8rm
872 { 521, 3, 1, 4, 0, 1, 1, MSP430OpInfoBase + 197, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD8ri
873 { 520, 3, 1, 2, 0, 1, 1, MSP430OpInfoBase + 194, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD8rc
874 { 519, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 191, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD8mr
875 { 518, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 165, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD8mp
876 { 517, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 165, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD8mn
877 { 516, 4, 0, 6, 0, 1, 1, MSP430OpInfoBase + 161, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD8mm
878 { 515, 3, 0, 6, 0, 1, 1, MSP430OpInfoBase + 158, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD8mi
879 { 514, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 155, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD8mc
880 { 513, 3, 1, 2, 0, 1, 1, MSP430OpInfoBase + 188, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD16rr
881 { 512, 4, 2, 2, 0, 1, 1, MSP430OpInfoBase + 184, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD16rp
882 { 511, 3, 1, 2, 0, 1, 1, MSP430OpInfoBase + 181, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD16rn
883 { 510, 4, 1, 4, 0, 1, 1, MSP430OpInfoBase + 177, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD16rm
884 { 509, 3, 1, 4, 0, 1, 1, MSP430OpInfoBase + 174, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD16ri
885 { 508, 3, 1, 2, 0, 1, 1, MSP430OpInfoBase + 171, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD16rc
886 { 507, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 168, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD16mr
887 { 506, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 165, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD16mp
888 { 505, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 165, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD16mn
889 { 504, 4, 0, 6, 0, 1, 1, MSP430OpInfoBase + 161, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD16mm
890 { 503, 3, 0, 6, 0, 1, 1, MSP430OpInfoBase + 158, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD16mi
891 { 502, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 155, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD16mc
892 { 501, 2, 0, 2, 0, 0, 1, MSP430OpInfoBase + 232, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP8rr
893 { 500, 2, 0, 2, 0, 0, 1, MSP430OpInfoBase + 230, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP8rp
894 { 499, 2, 0, 2, 0, 0, 1, MSP430OpInfoBase + 230, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP8rn
895 { 498, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 227, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP8rm
896 { 497, 2, 0, 4, 0, 0, 1, MSP430OpInfoBase + 225, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP8ri
897 { 496, 2, 0, 2, 0, 0, 1, MSP430OpInfoBase + 223, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP8rc
898 { 495, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 191, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP8mr
899 { 494, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 165, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP8mp
900 { 493, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 165, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP8mn
901 { 492, 4, 0, 6, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP8mm
902 { 491, 3, 0, 6, 0, 0, 1, MSP430OpInfoBase + 158, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP8mi
903 { 490, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 155, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP8mc
904 { 489, 2, 0, 2, 0, 0, 1, MSP430OpInfoBase + 221, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP16rr
905 { 488, 2, 0, 2, 0, 0, 1, MSP430OpInfoBase + 219, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP16rp
906 { 487, 2, 0, 2, 0, 0, 1, MSP430OpInfoBase + 219, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP16rn
907 { 486, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 216, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP16rm
908 { 485, 2, 0, 4, 0, 0, 1, MSP430OpInfoBase + 214, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP16ri
909 { 484, 2, 0, 2, 0, 0, 1, MSP430OpInfoBase + 38, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP16rc
910 { 483, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 168, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP16mr
911 { 482, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 165, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP16mp
912 { 481, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 165, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP16mn
913 { 480, 4, 0, 6, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP16mm
914 { 479, 3, 0, 6, 0, 0, 1, MSP430OpInfoBase + 158, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP16mi
915 { 478, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 155, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP16mc
916 { 477, 1, 0, 2, 0, 1, 6, MSP430OpInfoBase + 32, 8, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CALLr
917 { 476, 1, 0, 2, 0, 1, 6, MSP430OpInfoBase + 236, 8, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CALLp
918 { 475, 1, 0, 2, 0, 1, 6, MSP430OpInfoBase + 236, 8, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CALLn
919 { 474, 2, 0, 4, 0, 1, 6, MSP430OpInfoBase + 234, 8, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CALLm
920 { 473, 1, 0, 4, 0, 1, 6, MSP430OpInfoBase + 1, 8, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CALLi
921 { 472, 1, 0, 2, 0, 0, 0, MSP430OpInfoBase + 32, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Br
922 { 471, 2, 0, 4, 0, 0, 0, MSP430OpInfoBase + 234, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Bm
923 { 470, 1, 0, 4, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Bi
924 { 469, 2, 0, 2, 0, 0, 1, MSP430OpInfoBase + 232, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT8rr
925 { 468, 2, 0, 2, 0, 0, 1, MSP430OpInfoBase + 230, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT8rp
926 { 467, 2, 0, 2, 0, 0, 1, MSP430OpInfoBase + 230, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT8rn
927 { 466, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 227, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT8rm
928 { 465, 2, 0, 4, 0, 0, 1, MSP430OpInfoBase + 225, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT8ri
929 { 464, 2, 0, 2, 0, 0, 1, MSP430OpInfoBase + 223, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT8rc
930 { 463, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 191, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT8mr
931 { 462, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 165, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT8mp
932 { 461, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 165, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT8mn
933 { 460, 4, 0, 6, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT8mm
934 { 459, 3, 0, 6, 0, 0, 1, MSP430OpInfoBase + 158, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT8mi
935 { 458, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 155, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT8mc
936 { 457, 2, 0, 2, 0, 0, 1, MSP430OpInfoBase + 221, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT16rr
937 { 456, 2, 0, 2, 0, 0, 1, MSP430OpInfoBase + 219, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT16rp
938 { 455, 2, 0, 2, 0, 0, 1, MSP430OpInfoBase + 219, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT16rn
939 { 454, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 216, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT16rm
940 { 453, 2, 0, 4, 0, 0, 1, MSP430OpInfoBase + 214, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT16ri
941 { 452, 2, 0, 2, 0, 0, 1, MSP430OpInfoBase + 38, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT16rc
942 { 451, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 168, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT16mr
943 { 450, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 165, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT16mp
944 { 449, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 165, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT16mn
945 { 448, 4, 0, 6, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT16mm
946 { 447, 3, 0, 6, 0, 0, 1, MSP430OpInfoBase + 158, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT16mi
947 { 446, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 155, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT16mc
948 { 445, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 211, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS8rr
949 { 444, 4, 2, 2, 0, 0, 1, MSP430OpInfoBase + 207, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS8rp
950 { 443, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 204, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS8rn
951 { 442, 4, 1, 4, 0, 0, 1, MSP430OpInfoBase + 200, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS8rm
952 { 441, 3, 1, 4, 0, 0, 1, MSP430OpInfoBase + 197, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS8ri
953 { 440, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 194, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS8rc
954 { 439, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 191, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS8mr
955 { 438, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 165, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS8mp
956 { 437, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 165, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS8mn
957 { 436, 4, 0, 6, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS8mm
958 { 435, 3, 0, 6, 0, 0, 1, MSP430OpInfoBase + 158, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS8mi
959 { 434, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 155, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS8mc
960 { 433, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 188, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS16rr
961 { 432, 4, 2, 2, 0, 0, 1, MSP430OpInfoBase + 184, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS16rp
962 { 431, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 181, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS16rn
963 { 430, 4, 1, 4, 0, 0, 1, MSP430OpInfoBase + 177, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS16rm
964 { 429, 3, 1, 4, 0, 0, 1, MSP430OpInfoBase + 174, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS16ri
965 { 428, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 171, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS16rc
966 { 427, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 168, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS16mr
967 { 426, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 165, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS16mp
968 { 425, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 165, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS16mn
969 { 424, 4, 0, 6, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS16mm
970 { 423, 3, 0, 6, 0, 0, 1, MSP430OpInfoBase + 158, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS16mi
971 { 422, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 155, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS16mc
972 { 421, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 211, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC8rr
973 { 420, 4, 2, 2, 0, 0, 1, MSP430OpInfoBase + 207, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC8rp
974 { 419, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 204, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC8rn
975 { 418, 4, 1, 4, 0, 0, 1, MSP430OpInfoBase + 200, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC8rm
976 { 417, 3, 1, 4, 0, 0, 1, MSP430OpInfoBase + 197, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC8ri
977 { 416, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 194, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC8rc
978 { 415, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 191, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC8mr
979 { 414, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 165, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC8mp
980 { 413, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 165, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC8mn
981 { 412, 4, 0, 6, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC8mm
982 { 411, 3, 0, 6, 0, 0, 1, MSP430OpInfoBase + 158, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC8mi
983 { 410, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 155, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC8mc
984 { 409, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 188, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC16rr
985 { 408, 4, 2, 2, 0, 0, 1, MSP430OpInfoBase + 184, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC16rp
986 { 407, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 181, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC16rn
987 { 406, 4, 1, 4, 0, 0, 1, MSP430OpInfoBase + 177, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC16rm
988 { 405, 3, 1, 4, 0, 0, 1, MSP430OpInfoBase + 174, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC16ri
989 { 404, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 171, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC16rc
990 { 403, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 168, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC16mr
991 { 402, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 165, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC16mp
992 { 401, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 165, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC16mn
993 { 400, 4, 0, 6, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC16mm
994 { 399, 3, 0, 6, 0, 0, 1, MSP430OpInfoBase + 158, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC16mi
995 { 398, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 155, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC16mc
996 { 397, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 211, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND8rr
997 { 396, 4, 2, 2, 0, 0, 1, MSP430OpInfoBase + 207, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND8rp
998 { 395, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 204, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND8rn
999 { 394, 4, 1, 4, 0, 0, 1, MSP430OpInfoBase + 200, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND8rm
1000 { 393, 3, 1, 4, 0, 0, 1, MSP430OpInfoBase + 197, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND8ri
1001 { 392, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 194, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND8rc
1002 { 391, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 191, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND8mr
1003 { 390, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 165, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND8mp
1004 { 389, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 165, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND8mn
1005 { 388, 4, 0, 6, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND8mm
1006 { 387, 3, 0, 6, 0, 0, 1, MSP430OpInfoBase + 158, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND8mi
1007 { 386, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 155, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND8mc
1008 { 385, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 188, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND16rr
1009 { 384, 4, 2, 2, 0, 0, 1, MSP430OpInfoBase + 184, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND16rp
1010 { 383, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 181, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND16rn
1011 { 382, 4, 1, 4, 0, 0, 1, MSP430OpInfoBase + 177, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND16rm
1012 { 381, 3, 1, 4, 0, 0, 1, MSP430OpInfoBase + 174, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND16ri
1013 { 380, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 171, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND16rc
1014 { 379, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 168, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND16mr
1015 { 378, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 165, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND16mp
1016 { 377, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 165, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND16mn
1017 { 376, 4, 0, 6, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND16mm
1018 { 375, 3, 0, 6, 0, 0, 1, MSP430OpInfoBase + 158, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND16mi
1019 { 374, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 155, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND16mc
1020 { 373, 2, 0, 0, 0, 1, 2, MSP430OpInfoBase + 24, 5, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADJCALLSTACKUP
1021 { 372, 2, 0, 0, 0, 1, 2, MSP430OpInfoBase + 24, 5, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADJCALLSTACKDOWN
1022 { 371, 3, 1, 0, 0, 1, 1, MSP430OpInfoBase + 33, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDframe
1023 { 370, 3, 1, 2, 0, 1, 1, MSP430OpInfoBase + 211, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC8rr
1024 { 369, 4, 2, 2, 0, 1, 1, MSP430OpInfoBase + 207, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC8rp
1025 { 368, 3, 1, 2, 0, 1, 1, MSP430OpInfoBase + 204, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC8rn
1026 { 367, 4, 1, 4, 0, 1, 1, MSP430OpInfoBase + 200, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC8rm
1027 { 366, 3, 1, 4, 0, 1, 1, MSP430OpInfoBase + 197, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC8ri
1028 { 365, 3, 1, 2, 0, 1, 1, MSP430OpInfoBase + 194, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC8rc
1029 { 364, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 191, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC8mr
1030 { 363, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 165, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC8mp
1031 { 362, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 165, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC8mn
1032 { 361, 4, 0, 6, 0, 1, 1, MSP430OpInfoBase + 161, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC8mm
1033 { 360, 3, 0, 6, 0, 1, 1, MSP430OpInfoBase + 158, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC8mi
1034 { 359, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 155, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC8mc
1035 { 358, 3, 1, 2, 0, 1, 1, MSP430OpInfoBase + 188, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC16rr
1036 { 357, 4, 2, 2, 0, 1, 1, MSP430OpInfoBase + 184, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC16rp
1037 { 356, 3, 1, 2, 0, 1, 1, MSP430OpInfoBase + 181, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC16rn
1038 { 355, 4, 1, 4, 0, 1, 1, MSP430OpInfoBase + 177, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC16rm
1039 { 354, 3, 1, 4, 0, 1, 1, MSP430OpInfoBase + 174, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC16ri
1040 { 353, 3, 1, 2, 0, 1, 1, MSP430OpInfoBase + 171, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC16rc
1041 { 352, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 168, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC16mr
1042 { 351, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 165, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC16mp
1043 { 350, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 165, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC16mn
1044 { 349, 4, 0, 6, 0, 1, 1, MSP430OpInfoBase + 161, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC16mm
1045 { 348, 3, 0, 6, 0, 1, 1, MSP430OpInfoBase + 158, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC16mi
1046 { 347, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 155, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC16mc
1047 { 346, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 211, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD8rr
1048 { 345, 4, 2, 2, 0, 0, 1, MSP430OpInfoBase + 207, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD8rp
1049 { 344, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 204, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD8rn
1050 { 343, 4, 1, 4, 0, 0, 1, MSP430OpInfoBase + 200, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD8rm
1051 { 342, 3, 1, 4, 0, 0, 1, MSP430OpInfoBase + 197, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD8ri
1052 { 341, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 194, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD8rc
1053 { 340, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 191, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD8mr
1054 { 339, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 165, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD8mp
1055 { 338, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 165, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD8mn
1056 { 337, 4, 0, 6, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD8mm
1057 { 336, 3, 0, 6, 0, 0, 1, MSP430OpInfoBase + 158, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD8mi
1058 { 335, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 155, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD8mc
1059 { 334, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 188, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD16rr
1060 { 333, 4, 2, 2, 0, 0, 1, MSP430OpInfoBase + 184, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD16rp
1061 { 332, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 181, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD16rn
1062 { 331, 4, 1, 4, 0, 0, 1, MSP430OpInfoBase + 177, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD16rm
1063 { 330, 3, 1, 4, 0, 0, 1, MSP430OpInfoBase + 174, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD16ri
1064 { 329, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 171, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD16rc
1065 { 328, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 168, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD16mr
1066 { 327, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 165, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD16mp
1067 { 326, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 165, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD16mn
1068 { 325, 4, 0, 6, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD16mm
1069 { 324, 3, 0, 6, 0, 0, 1, MSP430OpInfoBase + 158, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD16mi
1070 { 323, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 155, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD16mc
1071 { 322, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 151, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UBFX
1072 { 321, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 151, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SBFX
1073 { 320, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_UMIN
1074 { 319, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_UMAX
1075 { 318, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SMIN
1076 { 317, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SMAX
1077 { 316, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_XOR
1078 { 315, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_OR
1079 { 314, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_AND
1080 { 313, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_MUL
1081 { 312, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_ADD
1082 { 311, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMINIMUM
1083 { 310, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMAXIMUM
1084 { 309, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMIN
1085 { 308, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMAX
1086 { 307, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMUL
1087 { 306, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FADD
1088 { 305, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 134, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SEQ_FMUL
1089 { 304, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 134, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SEQ_FADD
1090 { 303, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UBSANTRAP
1091 { 302, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_DEBUGTRAP
1092 { 301, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRAP
1093 { 300, 3, 0, 0, 0, 0, 0, MSP430OpInfoBase + 61, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BZERO
1094 { 299, 4, 0, 0, 0, 0, 0, MSP430OpInfoBase + 147, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMSET
1095 { 298, 4, 0, 0, 0, 0, 0, MSP430OpInfoBase + 147, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMMOVE
1096 { 297, 3, 0, 0, 0, 0, 0, MSP430OpInfoBase + 134, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMCPY_INLINE
1097 { 296, 4, 0, 0, 0, 0, 0, MSP430OpInfoBase + 147, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMCPY
1098 { 295, 2, 0, 0, 0, 0, 0, MSP430OpInfoBase + 145, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_WRITE_REGISTER
1099 { 294, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 54, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_READ_REGISTER
1100 { 293, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 104, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FLDEXP
1101 { 292, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FSQRT
1102 { 291, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FMA
1103 { 290, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FREM
1104 { 289, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FDIV
1105 { 288, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FMUL
1106 { 287, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FSUB
1107 { 286, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FADD
1108 { 285, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 53, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STACKRESTORE
1109 { 284, 1, 1, 0, 0, 0, 0, MSP430OpInfoBase + 53, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STACKSAVE
1110 { 283, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 72, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_DYN_STACKALLOC
1111 { 282, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 54, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_JUMP_TABLE
1112 { 281, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 54, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BLOCK_ADDR
1113 { 280, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ADDRSPACE_CAST
1114 { 279, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FNEARBYINT
1115 { 278, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FRINT
1116 { 277, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FFLOOR
1117 { 276, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSQRT
1118 { 275, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FTANH
1119 { 274, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSINH
1120 { 273, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCOSH
1121 { 272, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FATAN2
1122 { 271, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FATAN
1123 { 270, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FASIN
1124 { 269, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FACOS
1125 { 268, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FTAN
1126 { 267, 3, 2, 0, 0, 0, 0, MSP430OpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSINCOS
1127 { 266, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSIN
1128 { 265, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCOS
1129 { 264, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCEIL
1130 { 263, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BITREVERSE
1131 { 262, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BSWAP
1132 { 261, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTPOP
1133 { 260, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTLS
1134 { 259, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTLZ_ZERO_UNDEF
1135 { 258, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTLZ
1136 { 257, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTTZ_ZERO_UNDEF
1137 { 256, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTTZ
1138 { 255, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 141, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECTOR_COMPRESS
1139 { 254, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 54, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STEP_VECTOR
1140 { 253, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SPLAT_VECTOR
1141 { 252, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 137, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SHUFFLE_VECTOR
1142 { 251, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 134, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_EXTRACT_VECTOR_ELT
1143 { 250, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INSERT_VECTOR_ELT
1144 { 249, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 61, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_EXTRACT_SUBVECTOR
1145 { 248, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INSERT_SUBVECTOR
1146 { 247, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 54, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VSCALE
1147 { 246, 3, 0, 0, 0, 0, 0, MSP430OpInfoBase + 127, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BRJT
1148 { 245, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BR
1149 { 244, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LLROUND
1150 { 243, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LROUND
1151 { 242, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ABS
1152 { 241, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMAX
1153 { 240, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMIN
1154 { 239, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMAX
1155 { 238, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMIN
1156 { 237, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 104, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTRMASK
1157 { 236, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 104, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTR_ADD
1158 { 235, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 53, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SET_ROUNDING
1159 { 234, 1, 1, 0, 0, 0, 0, MSP430OpInfoBase + 53, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GET_ROUNDING
1160 { 233, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_RESET_FPMODE
1161 { 232, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 53, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SET_FPMODE
1162 { 231, 1, 1, 0, 0, 0, 0, MSP430OpInfoBase + 53, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GET_FPMODE
1163 { 230, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_RESET_FPENV
1164 { 229, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 53, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SET_FPENV
1165 { 228, 1, 1, 0, 0, 0, 0, MSP430OpInfoBase + 53, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GET_FPENV
1166 { 227, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXIMUMNUM
1167 { 226, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINIMUMNUM
1168 { 225, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXIMUM
1169 { 224, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINIMUM
1170 { 223, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXNUM_IEEE
1171 { 222, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINNUM_IEEE
1172 { 221, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXNUM
1173 { 220, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINNUM
1174 { 219, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCANONICALIZE
1175 { 218, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 101, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_IS_FPCLASS
1176 { 217, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 104, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCOPYSIGN
1177 { 216, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FABS
1178 { 215, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOUI_SAT
1179 { 214, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOSI_SAT
1180 { 213, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UITOFP
1181 { 212, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SITOFP
1182 { 211, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOUI
1183 { 210, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOSI
1184 { 209, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTRUNC
1185 { 208, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPEXT
1186 { 207, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FNEG
1187 { 206, 3, 2, 0, 0, 0, 0, MSP430OpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FFREXP
1188 { 205, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 104, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLDEXP
1189 { 204, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLOG10
1190 { 203, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLOG2
1191 { 202, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLOG
1192 { 201, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FEXP10
1193 { 200, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FEXP2
1194 { 199, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FEXP
1195 { 198, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 104, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPOWI
1196 { 197, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPOW
1197 { 196, 3, 2, 0, 0, 0, 0, MSP430OpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMODF
1198 { 195, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FREM
1199 { 194, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FDIV
1200 { 193, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAD
1201 { 192, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMA
1202 { 191, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMUL
1203 { 190, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSUB
1204 { 189, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FADD
1205 { 188, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 123, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIVFIXSAT
1206 { 187, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 123, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIVFIXSAT
1207 { 186, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 123, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIVFIX
1208 { 185, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 123, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIVFIX
1209 { 184, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 123, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULFIXSAT
1210 { 183, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 123, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULFIXSAT
1211 { 182, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 123, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULFIX
1212 { 181, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 123, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULFIX
1213 { 180, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 104, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSHLSAT
1214 { 179, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 104, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USHLSAT
1215 { 178, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSUBSAT
1216 { 177, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USUBSAT
1217 { 176, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SADDSAT
1218 { 175, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UADDSAT
1219 { 174, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULH
1220 { 173, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULH
1221 { 172, 4, 2, 0, 0, 0, 0, MSP430OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULO
1222 { 171, 4, 2, 0, 0, 0, 0, MSP430OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULO
1223 { 170, 5, 2, 0, 0, 0, 0, MSP430OpInfoBase + 118, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSUBE
1224 { 169, 4, 2, 0, 0, 0, 0, MSP430OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSUBO
1225 { 168, 5, 2, 0, 0, 0, 0, MSP430OpInfoBase + 118, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SADDE
1226 { 167, 4, 2, 0, 0, 0, 0, MSP430OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SADDO
1227 { 166, 5, 2, 0, 0, 0, 0, MSP430OpInfoBase + 118, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USUBE
1228 { 165, 4, 2, 0, 0, 0, 0, MSP430OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USUBO
1229 { 164, 5, 2, 0, 0, 0, 0, MSP430OpInfoBase + 118, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UADDE
1230 { 163, 4, 2, 0, 0, 0, 0, MSP430OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UADDO
1231 { 162, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SELECT
1232 { 161, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 115, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UCMP
1233 { 160, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 115, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SCMP
1234 { 159, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 111, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCMP
1235 { 158, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 111, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ICMP
1236 { 157, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 104, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ROTL
1237 { 156, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 104, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ROTR
1238 { 155, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSHR
1239 { 154, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSHL
1240 { 153, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 104, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASHR
1241 { 152, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 104, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LSHR
1242 { 151, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 104, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SHL
1243 { 150, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ZEXT
1244 { 149, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 43, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SEXT_INREG
1245 { 148, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SEXT
1246 { 147, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 101, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VAARG
1247 { 146, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 53, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VASTART
1248 { 145, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 54, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCONSTANT
1249 { 144, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 54, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONSTANT
1250 { 143, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC_USAT_U
1251 { 142, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC_SSAT_U
1252 { 141, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC_SSAT_S
1253 { 140, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC
1254 { 139, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ANYEXT
1255 { 138, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
1256 { 137, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_INTRINSIC_CONVERGENT
1257 { 136, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_W_SIDE_EFFECTS
1258 { 135, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC
1259 { 134, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INVOKE_REGION_START
1260 { 133, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 53, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BRINDIRECT
1261 { 132, 2, 0, 0, 0, 0, 0, MSP430OpInfoBase + 54, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BRCOND
1262 { 131, 4, 0, 0, 0, 0, 0, MSP430OpInfoBase + 97, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PREFETCH
1263 { 130, 2, 0, 0, 0, 0, 0, MSP430OpInfoBase + 24, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FENCE
1264 { 129, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_USUB_SAT
1265 { 128, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_USUB_COND
1266 { 127, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UDEC_WRAP
1267 { 126, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UINC_WRAP
1268 { 125, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMINIMUM
1269 { 124, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMAXIMUM
1270 { 123, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMIN
1271 { 122, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMAX
1272 { 121, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FSUB
1273 { 120, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FADD
1274 { 119, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UMIN
1275 { 118, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UMAX
1276 { 117, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_MIN
1277 { 116, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_MAX
1278 { 115, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_XOR
1279 { 114, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_OR
1280 { 113, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_NAND
1281 { 112, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_AND
1282 { 111, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_SUB
1283 { 110, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_ADD
1284 { 109, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_XCHG
1285 { 108, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMIC_CMPXCHG
1286 { 107, 5, 2, 0, 0, 0, 0, MSP430OpInfoBase + 85, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
1287 { 106, 5, 1, 0, 0, 0, 0, MSP430OpInfoBase + 80, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_STORE
1288 { 105, 2, 0, 0, 0, 0, 0, MSP430OpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STORE
1289 { 104, 5, 2, 0, 0, 0, 0, MSP430OpInfoBase + 75, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_ZEXTLOAD
1290 { 103, 5, 2, 0, 0, 0, 0, MSP430OpInfoBase + 75, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_SEXTLOAD
1291 { 102, 5, 2, 0, 0, 0, 0, MSP430OpInfoBase + 75, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_LOAD
1292 { 101, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ZEXTLOAD
1293 { 100, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SEXTLOAD
1294 { 99, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LOAD
1295 { 98, 1, 1, 0, 0, 0, 0, MSP430OpInfoBase + 53, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_READSTEADYCOUNTER
1296 { 97, 1, 1, 0, 0, 0, 0, MSP430OpInfoBase + 53, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_READCYCLECOUNTER
1297 { 96, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_ROUNDEVEN
1298 { 95, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_LLRINT
1299 { 94, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_LRINT
1300 { 93, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_ROUND
1301 { 92, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_TRUNC
1302 { 91, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 72, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_FPTRUNC_ROUND
1303 { 90, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONSTANT_FOLD_BARRIER
1304 { 89, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FREEZE
1305 { 88, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BITCAST
1306 { 87, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTTOPTR
1307 { 86, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTRTOINT
1308 { 85, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONCAT_VECTORS
1309 { 84, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BUILD_VECTOR_TRUNC
1310 { 83, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BUILD_VECTOR
1311 { 82, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MERGE_VALUES
1312 { 81, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INSERT
1313 { 80, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UNMERGE_VALUES
1314 { 79, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 61, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_EXTRACT
1315 { 78, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 54, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONSTANT_POOL
1316 { 77, 5, 1, 0, 0, 0, 0, MSP430OpInfoBase + 56, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTRAUTH_GLOBAL_VALUE
1317 { 76, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 54, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GLOBAL_VALUE
1318 { 75, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 54, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FRAME_INDEX
1319 { 74, 1, 1, 0, 0, 0, 0, MSP430OpInfoBase + 53, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PHI
1320 { 73, 1, 1, 0, 0, 0, 0, MSP430OpInfoBase + 53, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_IMPLICIT_DEF
1321 { 72, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SAVGCEIL
1322 { 71, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SAVGFLOOR
1323 { 70, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UAVGCEIL
1324 { 69, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UAVGFLOOR
1325 { 68, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ABDU
1326 { 67, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ABDS
1327 { 66, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_XOR
1328 { 65, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_OR
1329 { 64, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_AND
1330 { 63, 4, 2, 0, 0, 0, 0, MSP430OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIVREM
1331 { 62, 4, 2, 0, 0, 0, 0, MSP430OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIVREM
1332 { 61, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UREM
1333 { 60, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SREM
1334 { 59, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIV
1335 { 58, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIV
1336 { 57, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MUL
1337 { 56, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SUB
1338 { 55, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ADD
1339 { 54, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 43, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASSERT_ALIGN
1340 { 53, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 43, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASSERT_ZEXT
1341 { 52, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 43, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASSERT_SEXT
1342 { 51, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_GLUE
1343 { 50, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 13, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_LOOP
1344 { 49, 1, 1, 0, 0, 0, 0, MSP430OpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_ANCHOR
1345 { 48, 1, 1, 0, 0, 0, 0, MSP430OpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_ENTRY
1346 { 47, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RELOC_NONE
1347 { 46, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JUMP_TABLE_DEBUG_INFO
1348 { 45, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMBARRIER
1349 { 44, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FAKE_USE
1350 { 43, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ICALL_BRANCH_FUNNEL
1351 { 42, 3, 0, 0, 0, 0, 0, MSP430OpInfoBase + 40, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_14633
1352 { 41, 2, 0, 0, 0, 0, 0, MSP430OpInfoBase + 38, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_14632
1353 { 40, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_TAIL_CALL
1354 { 39, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_FUNCTION_EXIT
1355 { 38, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_RET
1356 { 37, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_FUNCTION_ENTER
1357 { 36, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_OP
1358 { 35, 1, 1, 0, 0, 0, 0, MSP430OpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FAULTING_OP
1359 { 34, 2, 0, 0, 0, 0, 0, MSP430OpInfoBase + 36, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_ESCAPE
1360 { 33, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STATEPOINT
1361 { 32, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 33, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_14631
1362 { 31, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PREALLOCATED_SETUP
1363 { 30, 1, 1, 0, 0, 0, 0, MSP430OpInfoBase + 32, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_14301
1364 { 29, 6, 1, 0, 0, 0, 0, MSP430OpInfoBase + 26, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHPOINT
1365 { 28, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FENTRY_CALL
1366 { 27, 2, 0, 0, 0, 0, 0, MSP430OpInfoBase + 24, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STACKMAP
1367 { 26, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 22, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARITH_FENCE
1368 { 25, 4, 0, 0, 0, 0, 0, MSP430OpInfoBase + 18, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PSEUDO_PROBE
1369 { 24, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LIFETIME_END
1370 { 23, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LIFETIME_START
1371 { 22, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BUNDLE
1372 { 21, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 15, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_LANEMASK
1373 { 20, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 13, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY
1374 { 19, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 13, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REG_SEQUENCE
1375 { 18, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_LABEL
1376 { 17, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_PHI
1377 { 16, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_INSTR_REF
1378 { 15, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_VALUE_LIST
1379 { 14, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_VALUE
1380 { 13, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_TO_REGCLASS
1381 { 12, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBREG_TO_REG
1382 { 11, 1, 1, 0, 0, 0, 0, MSP430OpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INIT_UNDEF
1383 { 10, 1, 1, 0, 0, 0, 0, MSP430OpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // IMPLICIT_DEF
1384 { 9, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 5, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INSERT_SUBREG
1385 { 8, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTRACT_SUBREG
1386 { 7, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // KILL
1387 { 6, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ANNOTATION_LABEL
1388 { 5, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GC_LABEL
1389 { 4, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EH_LABEL
1390 { 3, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CFI_INSTRUCTION
1391 { 2, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INLINEASM_BR
1392 { 1, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INLINEASM
1393 { 0, 1, 1, 0, 0, 0, 0, MSP430OpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PHI
1394 }, {
1395 /* 0 */
1396 /* 0 */ MSP430::SR,
1397 /* 1 */ MSP430::SR, MSP430::SR,
1398 /* 3 */ MSP430::SP, MSP430::SR,
1399 /* 5 */ MSP430::SP, MSP430::SP, MSP430::SR,
1400 /* 8 */ MSP430::SP, MSP430::R11, MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15, MSP430::SR,
1401 /* 15 */ MSP430::SP, MSP430::SP,
1402 }, {
1403 0
1404 }, {
1405 /* 0 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1406 /* 1 */
1407 /* 1 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1408 /* 2 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1409 /* 5 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1410 /* 9 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1411 /* 13 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1412 /* 15 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1413 /* 18 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1414 /* 22 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) },
1415 /* 24 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1416 /* 26 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1417 /* 32 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1418 /* 33 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1419 /* 36 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1420 /* 38 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1421 /* 40 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1422 /* 43 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1423 /* 46 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1424 /* 49 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1425 /* 53 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1426 /* 54 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1427 /* 56 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1428 /* 61 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1429 /* 64 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1430 /* 66 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1431 /* 70 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1432 /* 72 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1433 /* 75 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1434 /* 80 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1435 /* 85 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1436 /* 90 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1437 /* 94 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1438 /* 97 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1439 /* 101 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1440 /* 104 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1441 /* 107 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1442 /* 111 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1443 /* 115 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1444 /* 118 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1445 /* 123 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1446 /* 127 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1447 /* 130 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
1448 /* 134 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
1449 /* 137 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1450 /* 141 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1451 /* 145 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1452 /* 147 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1453 /* 151 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1454 /* 155 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1455 /* 158 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1456 /* 161 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1457 /* 165 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 },
1458 /* 168 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1459 /* 171 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1460 /* 174 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1461 /* 177 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1462 /* 181 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 },
1463 /* 184 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(1) },
1464 /* 188 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1465 /* 191 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1466 /* 194 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1467 /* 197 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1468 /* 200 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1469 /* 204 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 },
1470 /* 207 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(1) },
1471 /* 211 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1472 /* 214 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1473 /* 216 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1474 /* 219 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 },
1475 /* 221 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1476 /* 223 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1477 /* 225 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1478 /* 227 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1479 /* 230 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 },
1480 /* 232 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1481 /* 234 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1482 /* 236 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 },
1483 /* 237 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(1) },
1484 /* 240 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(1) },
1485 /* 243 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1486 /* 245 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1487 /* 246 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
1488 /* 248 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
1489 /* 250 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1490 /* 254 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1491 /* 258 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1492 /* 261 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1493 }
1494};
1495
1496
1497#ifdef __GNUC__
1498#pragma GCC diagnostic push
1499#pragma GCC diagnostic ignored "-Woverlength-strings"
1500#endif
1501extern const char MSP430InstrNameData[] = {
1502 /* 0 */ "G_FLOG10\000"
1503 /* 9 */ "G_FEXP10\000"
1504 /* 18 */ "G_FLOG2\000"
1505 /* 26 */ "G_FATAN2\000"
1506 /* 35 */ "G_FEXP2\000"
1507 /* 43 */ "Sra16\000"
1508 /* 49 */ "Rrcl16\000"
1509 /* 56 */ "Shl16\000"
1510 /* 62 */ "Srl16\000"
1511 /* 68 */ "Select16\000"
1512 /* 77 */ "Sra8\000"
1513 /* 82 */ "Rrcl8\000"
1514 /* 88 */ "Shl8\000"
1515 /* 93 */ "Srl8\000"
1516 /* 98 */ "MOVZX16rm8\000"
1517 /* 109 */ "MOVZX16rr8\000"
1518 /* 120 */ "Select8\000"
1519 /* 128 */ "G_FMA\000"
1520 /* 134 */ "G_STRICT_FMA\000"
1521 /* 147 */ "G_FSUB\000"
1522 /* 154 */ "G_STRICT_FSUB\000"
1523 /* 168 */ "G_ATOMICRMW_FSUB\000"
1524 /* 185 */ "G_SUB\000"
1525 /* 191 */ "G_ATOMICRMW_SUB\000"
1526 /* 207 */ "JCC\000"
1527 /* 211 */ "G_INTRINSIC\000"
1528 /* 223 */ "G_FPTRUNC\000"
1529 /* 233 */ "G_INTRINSIC_TRUNC\000"
1530 /* 251 */ "G_TRUNC\000"
1531 /* 259 */ "G_BUILD_VECTOR_TRUNC\000"
1532 /* 280 */ "G_DYN_STACKALLOC\000"
1533 /* 297 */ "G_FMAD\000"
1534 /* 304 */ "G_INDEXED_SEXTLOAD\000"
1535 /* 323 */ "G_SEXTLOAD\000"
1536 /* 334 */ "G_INDEXED_ZEXTLOAD\000"
1537 /* 353 */ "G_ZEXTLOAD\000"
1538 /* 364 */ "G_INDEXED_LOAD\000"
1539 /* 379 */ "G_LOAD\000"
1540 /* 386 */ "G_VECREDUCE_FADD\000"
1541 /* 403 */ "G_FADD\000"
1542 /* 410 */ "G_VECREDUCE_SEQ_FADD\000"
1543 /* 431 */ "G_STRICT_FADD\000"
1544 /* 445 */ "G_ATOMICRMW_FADD\000"
1545 /* 462 */ "G_VECREDUCE_ADD\000"
1546 /* 478 */ "G_ADD\000"
1547 /* 484 */ "G_PTR_ADD\000"
1548 /* 494 */ "G_ATOMICRMW_ADD\000"
1549 /* 510 */ "G_ATOMICRMW_NAND\000"
1550 /* 527 */ "G_VECREDUCE_AND\000"
1551 /* 543 */ "G_AND\000"
1552 /* 549 */ "G_ATOMICRMW_AND\000"
1553 /* 565 */ "LIFETIME_END\000"
1554 /* 578 */ "G_BRCOND\000"
1555 /* 587 */ "G_ATOMICRMW_USUB_COND\000"
1556 /* 609 */ "G_LLROUND\000"
1557 /* 619 */ "G_LROUND\000"
1558 /* 628 */ "G_INTRINSIC_ROUND\000"
1559 /* 646 */ "G_INTRINSIC_FPTRUNC_ROUND\000"
1560 /* 672 */ "LOAD_STACK_GUARD\000"
1561 /* 689 */ "PSEUDO_PROBE\000"
1562 /* 702 */ "G_SSUBE\000"
1563 /* 710 */ "G_USUBE\000"
1564 /* 718 */ "G_FENCE\000"
1565 /* 726 */ "ARITH_FENCE\000"
1566 /* 738 */ "REG_SEQUENCE\000"
1567 /* 751 */ "G_SADDE\000"
1568 /* 759 */ "G_UADDE\000"
1569 /* 767 */ "G_GET_FPMODE\000"
1570 /* 780 */ "G_RESET_FPMODE\000"
1571 /* 795 */ "G_SET_FPMODE\000"
1572 /* 808 */ "G_FMINNUM_IEEE\000"
1573 /* 823 */ "G_FMAXNUM_IEEE\000"
1574 /* 838 */ "G_VSCALE\000"
1575 /* 847 */ "G_JUMP_TABLE\000"
1576 /* 860 */ "BUNDLE\000"
1577 /* 867 */ "G_MEMCPY_INLINE\000"
1578 /* 883 */ "RELOC_NONE\000"
1579 /* 894 */ "LOCAL_ESCAPE\000"
1580 /* 907 */ "G_STACKRESTORE\000"
1581 /* 922 */ "G_INDEXED_STORE\000"
1582 /* 938 */ "G_STORE\000"
1583 /* 946 */ "G_BITREVERSE\000"
1584 /* 959 */ "FAKE_USE\000"
1585 /* 968 */ "DBG_VALUE\000"
1586 /* 978 */ "G_GLOBAL_VALUE\000"
1587 /* 993 */ "G_PTRAUTH_GLOBAL_VALUE\000"
1588 /* 1016 */ "CONVERGENCECTRL_GLUE\000"
1589 /* 1037 */ "G_STACKSAVE\000"
1590 /* 1049 */ "G_MEMMOVE\000"
1591 /* 1059 */ "G_FREEZE\000"
1592 /* 1068 */ "G_FCANONICALIZE\000"
1593 /* 1084 */ "G_FMODF\000"
1594 /* 1092 */ "G_CTLZ_ZERO_UNDEF\000"
1595 /* 1110 */ "G_CTTZ_ZERO_UNDEF\000"
1596 /* 1128 */ "INIT_UNDEF\000"
1597 /* 1139 */ "G_IMPLICIT_DEF\000"
1598 /* 1154 */ "DBG_INSTR_REF\000"
1599 /* 1168 */ "G_FNEG\000"
1600 /* 1175 */ "EXTRACT_SUBREG\000"
1601 /* 1190 */ "INSERT_SUBREG\000"
1602 /* 1204 */ "G_SEXT_INREG\000"
1603 /* 1217 */ "SUBREG_TO_REG\000"
1604 /* 1231 */ "G_ATOMIC_CMPXCHG\000"
1605 /* 1248 */ "G_ATOMICRMW_XCHG\000"
1606 /* 1265 */ "G_GET_ROUNDING\000"
1607 /* 1280 */ "G_SET_ROUNDING\000"
1608 /* 1295 */ "G_FLOG\000"
1609 /* 1302 */ "G_VAARG\000"
1610 /* 1310 */ "PREALLOCATED_ARG\000"
1611 /* 1327 */ "G_PREFETCH\000"
1612 /* 1338 */ "G_SMULH\000"
1613 /* 1346 */ "G_UMULH\000"
1614 /* 1354 */ "G_FTANH\000"
1615 /* 1362 */ "G_FSINH\000"
1616 /* 1370 */ "G_FCOSH\000"
1617 /* 1378 */ "DBG_PHI\000"
1618 /* 1386 */ "G_FPTOSI\000"
1619 /* 1395 */ "RETI\000"
1620 /* 1400 */ "G_FPTOUI\000"
1621 /* 1409 */ "G_FPOWI\000"
1622 /* 1417 */ "COPY_LANEMASK\000"
1623 /* 1431 */ "G_PTRMASK\000"
1624 /* 1441 */ "GC_LABEL\000"
1625 /* 1450 */ "DBG_LABEL\000"
1626 /* 1460 */ "EH_LABEL\000"
1627 /* 1469 */ "ANNOTATION_LABEL\000"
1628 /* 1486 */ "ICALL_BRANCH_FUNNEL\000"
1629 /* 1506 */ "G_FSHL\000"
1630 /* 1513 */ "G_SHL\000"
1631 /* 1519 */ "G_FCEIL\000"
1632 /* 1527 */ "G_SAVGCEIL\000"
1633 /* 1538 */ "G_UAVGCEIL\000"
1634 /* 1549 */ "PATCHABLE_TAIL_CALL\000"
1635 /* 1569 */ "PATCHABLE_TYPED_EVENT_CALL\000"
1636 /* 1596 */ "PATCHABLE_EVENT_CALL\000"
1637 /* 1617 */ "FENTRY_CALL\000"
1638 /* 1629 */ "KILL\000"
1639 /* 1634 */ "G_CONSTANT_POOL\000"
1640 /* 1650 */ "G_ROTL\000"
1641 /* 1657 */ "G_VECREDUCE_FMUL\000"
1642 /* 1674 */ "G_FMUL\000"
1643 /* 1681 */ "G_VECREDUCE_SEQ_FMUL\000"
1644 /* 1702 */ "G_STRICT_FMUL\000"
1645 /* 1716 */ "G_VECREDUCE_MUL\000"
1646 /* 1732 */ "G_MUL\000"
1647 /* 1738 */ "G_FREM\000"
1648 /* 1745 */ "G_STRICT_FREM\000"
1649 /* 1759 */ "G_SREM\000"
1650 /* 1766 */ "G_UREM\000"
1651 /* 1773 */ "G_SDIVREM\000"
1652 /* 1783 */ "G_UDIVREM\000"
1653 /* 1793 */ "INLINEASM\000"
1654 /* 1803 */ "G_VECREDUCE_FMINIMUM\000"
1655 /* 1824 */ "G_FMINIMUM\000"
1656 /* 1835 */ "G_ATOMICRMW_FMINIMUM\000"
1657 /* 1856 */ "G_VECREDUCE_FMAXIMUM\000"
1658 /* 1877 */ "G_FMAXIMUM\000"
1659 /* 1888 */ "G_ATOMICRMW_FMAXIMUM\000"
1660 /* 1909 */ "G_FMINIMUMNUM\000"
1661 /* 1923 */ "G_FMAXIMUMNUM\000"
1662 /* 1937 */ "G_FMINNUM\000"
1663 /* 1947 */ "G_FMAXNUM\000"
1664 /* 1957 */ "G_FATAN\000"
1665 /* 1965 */ "G_FTAN\000"
1666 /* 1972 */ "G_INTRINSIC_ROUNDEVEN\000"
1667 /* 1994 */ "G_ASSERT_ALIGN\000"
1668 /* 2009 */ "G_FCOPYSIGN\000"
1669 /* 2021 */ "G_VECREDUCE_FMIN\000"
1670 /* 2038 */ "G_ATOMICRMW_FMIN\000"
1671 /* 2055 */ "G_VECREDUCE_SMIN\000"
1672 /* 2072 */ "G_SMIN\000"
1673 /* 2079 */ "G_VECREDUCE_UMIN\000"
1674 /* 2096 */ "G_UMIN\000"
1675 /* 2103 */ "G_ATOMICRMW_UMIN\000"
1676 /* 2120 */ "G_ATOMICRMW_MIN\000"
1677 /* 2136 */ "G_FASIN\000"
1678 /* 2144 */ "G_FSIN\000"
1679 /* 2151 */ "CFI_INSTRUCTION\000"
1680 /* 2167 */ "ADJCALLSTACKDOWN\000"
1681 /* 2184 */ "G_SSUBO\000"
1682 /* 2192 */ "G_USUBO\000"
1683 /* 2200 */ "G_SADDO\000"
1684 /* 2208 */ "G_UADDO\000"
1685 /* 2216 */ "JUMP_TABLE_DEBUG_INFO\000"
1686 /* 2238 */ "G_SMULO\000"
1687 /* 2246 */ "G_UMULO\000"
1688 /* 2254 */ "G_BZERO\000"
1689 /* 2262 */ "STACKMAP\000"
1690 /* 2271 */ "G_DEBUGTRAP\000"
1691 /* 2283 */ "G_UBSANTRAP\000"
1692 /* 2295 */ "G_TRAP\000"
1693 /* 2302 */ "G_ATOMICRMW_UDEC_WRAP\000"
1694 /* 2324 */ "G_ATOMICRMW_UINC_WRAP\000"
1695 /* 2346 */ "G_BSWAP\000"
1696 /* 2354 */ "G_SITOFP\000"
1697 /* 2363 */ "G_UITOFP\000"
1698 /* 2372 */ "G_FCMP\000"
1699 /* 2379 */ "G_ICMP\000"
1700 /* 2386 */ "G_SCMP\000"
1701 /* 2393 */ "G_UCMP\000"
1702 /* 2400 */ "JMP\000"
1703 /* 2404 */ "CONVERGENCECTRL_LOOP\000"
1704 /* 2425 */ "G_CTPOP\000"
1705 /* 2433 */ "PATCHABLE_OP\000"
1706 /* 2446 */ "FAULTING_OP\000"
1707 /* 2458 */ "ADJCALLSTACKUP\000"
1708 /* 2473 */ "PREALLOCATED_SETUP\000"
1709 /* 2492 */ "G_FLDEXP\000"
1710 /* 2501 */ "G_STRICT_FLDEXP\000"
1711 /* 2517 */ "G_FEXP\000"
1712 /* 2524 */ "G_FFREXP\000"
1713 /* 2533 */ "G_BR\000"
1714 /* 2538 */ "INLINEASM_BR\000"
1715 /* 2551 */ "G_BLOCK_ADDR\000"
1716 /* 2564 */ "MEMBARRIER\000"
1717 /* 2575 */ "G_CONSTANT_FOLD_BARRIER\000"
1718 /* 2599 */ "PATCHABLE_FUNCTION_ENTER\000"
1719 /* 2624 */ "G_READCYCLECOUNTER\000"
1720 /* 2643 */ "G_READSTEADYCOUNTER\000"
1721 /* 2663 */ "G_READ_REGISTER\000"
1722 /* 2679 */ "G_WRITE_REGISTER\000"
1723 /* 2696 */ "G_ASHR\000"
1724 /* 2703 */ "G_FSHR\000"
1725 /* 2710 */ "G_LSHR\000"
1726 /* 2717 */ "CONVERGENCECTRL_ANCHOR\000"
1727 /* 2740 */ "G_FFLOOR\000"
1728 /* 2749 */ "G_SAVGFLOOR\000"
1729 /* 2761 */ "G_UAVGFLOOR\000"
1730 /* 2773 */ "G_EXTRACT_SUBVECTOR\000"
1731 /* 2793 */ "G_INSERT_SUBVECTOR\000"
1732 /* 2812 */ "G_BUILD_VECTOR\000"
1733 /* 2827 */ "G_SHUFFLE_VECTOR\000"
1734 /* 2844 */ "G_STEP_VECTOR\000"
1735 /* 2858 */ "G_SPLAT_VECTOR\000"
1736 /* 2873 */ "G_VECREDUCE_XOR\000"
1737 /* 2889 */ "G_XOR\000"
1738 /* 2895 */ "G_ATOMICRMW_XOR\000"
1739 /* 2911 */ "G_VECREDUCE_OR\000"
1740 /* 2926 */ "G_OR\000"
1741 /* 2931 */ "G_ATOMICRMW_OR\000"
1742 /* 2946 */ "G_ROTR\000"
1743 /* 2953 */ "G_INTTOPTR\000"
1744 /* 2964 */ "G_FABS\000"
1745 /* 2971 */ "G_ABS\000"
1746 /* 2977 */ "G_ABDS\000"
1747 /* 2984 */ "G_UNMERGE_VALUES\000"
1748 /* 3001 */ "G_MERGE_VALUES\000"
1749 /* 3016 */ "G_CTLS\000"
1750 /* 3023 */ "G_FACOS\000"
1751 /* 3031 */ "G_FCOS\000"
1752 /* 3038 */ "G_FSINCOS\000"
1753 /* 3048 */ "G_CONCAT_VECTORS\000"
1754 /* 3065 */ "COPY_TO_REGCLASS\000"
1755 /* 3082 */ "G_IS_FPCLASS\000"
1756 /* 3095 */ "G_ATOMIC_CMPXCHG_WITH_SUCCESS\000"
1757 /* 3125 */ "G_VECTOR_COMPRESS\000"
1758 /* 3143 */ "G_INTRINSIC_W_SIDE_EFFECTS\000"
1759 /* 3170 */ "G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS\000"
1760 /* 3208 */ "G_TRUNC_SSAT_S\000"
1761 /* 3223 */ "G_SSUBSAT\000"
1762 /* 3233 */ "G_USUBSAT\000"
1763 /* 3243 */ "G_SADDSAT\000"
1764 /* 3253 */ "G_UADDSAT\000"
1765 /* 3263 */ "G_SSHLSAT\000"
1766 /* 3273 */ "G_USHLSAT\000"
1767 /* 3283 */ "G_SMULFIXSAT\000"
1768 /* 3296 */ "G_UMULFIXSAT\000"
1769 /* 3309 */ "G_SDIVFIXSAT\000"
1770 /* 3322 */ "G_UDIVFIXSAT\000"
1771 /* 3335 */ "G_ATOMICRMW_USUB_SAT\000"
1772 /* 3356 */ "G_FPTOSI_SAT\000"
1773 /* 3369 */ "G_FPTOUI_SAT\000"
1774 /* 3382 */ "G_EXTRACT\000"
1775 /* 3392 */ "G_SELECT\000"
1776 /* 3401 */ "G_BRINDIRECT\000"
1777 /* 3414 */ "PATCHABLE_RET\000"
1778 /* 3428 */ "G_MEMSET\000"
1779 /* 3437 */ "PATCHABLE_FUNCTION_EXIT\000"
1780 /* 3461 */ "G_BRJT\000"
1781 /* 3468 */ "G_EXTRACT_VECTOR_ELT\000"
1782 /* 3489 */ "G_INSERT_VECTOR_ELT\000"
1783 /* 3509 */ "G_FCONSTANT\000"
1784 /* 3521 */ "G_CONSTANT\000"
1785 /* 3532 */ "G_INTRINSIC_CONVERGENT\000"
1786 /* 3555 */ "STATEPOINT\000"
1787 /* 3566 */ "PATCHPOINT\000"
1788 /* 3577 */ "G_PTRTOINT\000"
1789 /* 3588 */ "G_FRINT\000"
1790 /* 3596 */ "G_INTRINSIC_LLRINT\000"
1791 /* 3615 */ "G_INTRINSIC_LRINT\000"
1792 /* 3633 */ "G_FNEARBYINT\000"
1793 /* 3646 */ "G_VASTART\000"
1794 /* 3656 */ "LIFETIME_START\000"
1795 /* 3671 */ "G_INVOKE_REGION_START\000"
1796 /* 3693 */ "G_INSERT\000"
1797 /* 3702 */ "G_FSQRT\000"
1798 /* 3710 */ "G_STRICT_FSQRT\000"
1799 /* 3725 */ "G_BITCAST\000"
1800 /* 3735 */ "G_ADDRSPACE_CAST\000"
1801 /* 3752 */ "DBG_VALUE_LIST\000"
1802 /* 3767 */ "G_FPEXT\000"
1803 /* 3775 */ "G_SEXT\000"
1804 /* 3782 */ "G_ASSERT_SEXT\000"
1805 /* 3796 */ "G_ANYEXT\000"
1806 /* 3805 */ "G_ZEXT\000"
1807 /* 3812 */ "G_ASSERT_ZEXT\000"
1808 /* 3826 */ "G_ABDU\000"
1809 /* 3833 */ "G_TRUNC_SSAT_U\000"
1810 /* 3848 */ "G_TRUNC_USAT_U\000"
1811 /* 3863 */ "G_FDIV\000"
1812 /* 3870 */ "G_STRICT_FDIV\000"
1813 /* 3884 */ "G_SDIV\000"
1814 /* 3891 */ "G_UDIV\000"
1815 /* 3898 */ "G_GET_FPENV\000"
1816 /* 3910 */ "G_RESET_FPENV\000"
1817 /* 3924 */ "G_SET_FPENV\000"
1818 /* 3936 */ "G_FPOW\000"
1819 /* 3943 */ "G_VECREDUCE_FMAX\000"
1820 /* 3960 */ "G_ATOMICRMW_FMAX\000"
1821 /* 3977 */ "G_VECREDUCE_SMAX\000"
1822 /* 3994 */ "G_SMAX\000"
1823 /* 4001 */ "G_VECREDUCE_UMAX\000"
1824 /* 4018 */ "G_UMAX\000"
1825 /* 4025 */ "G_ATOMICRMW_UMAX\000"
1826 /* 4042 */ "G_ATOMICRMW_MAX\000"
1827 /* 4058 */ "G_FRAME_INDEX\000"
1828 /* 4072 */ "G_SBFX\000"
1829 /* 4079 */ "G_UBFX\000"
1830 /* 4086 */ "G_SMULFIX\000"
1831 /* 4096 */ "G_UMULFIX\000"
1832 /* 4106 */ "G_SDIVFIX\000"
1833 /* 4116 */ "G_UDIVFIX\000"
1834 /* 4126 */ "G_MEMCPY\000"
1835 /* 4135 */ "COPY\000"
1836 /* 4140 */ "CONVERGENCECTRL_ENTRY\000"
1837 /* 4162 */ "G_CTLZ\000"
1838 /* 4169 */ "G_CTTZ\000"
1839 /* 4176 */ "PUSH16c\000"
1840 /* 4184 */ "SUB16mc\000"
1841 /* 4192 */ "SUBC16mc\000"
1842 /* 4201 */ "ADDC16mc\000"
1843 /* 4210 */ "BIC16mc\000"
1844 /* 4218 */ "DADD16mc\000"
1845 /* 4227 */ "AND16mc\000"
1846 /* 4235 */ "CMP16mc\000"
1847 /* 4243 */ "XOR16mc\000"
1848 /* 4251 */ "BIS16mc\000"
1849 /* 4259 */ "BIT16mc\000"
1850 /* 4267 */ "MOV16mc\000"
1851 /* 4275 */ "SUB8mc\000"
1852 /* 4282 */ "SUBC8mc\000"
1853 /* 4290 */ "ADDC8mc\000"
1854 /* 4298 */ "BIC8mc\000"
1855 /* 4305 */ "DADD8mc\000"
1856 /* 4313 */ "AND8mc\000"
1857 /* 4320 */ "CMP8mc\000"
1858 /* 4327 */ "XOR8mc\000"
1859 /* 4334 */ "BIS8mc\000"
1860 /* 4341 */ "BIT8mc\000"
1861 /* 4348 */ "MOV8mc\000"
1862 /* 4355 */ "SUB16rc\000"
1863 /* 4363 */ "SUBC16rc\000"
1864 /* 4372 */ "ADDC16rc\000"
1865 /* 4381 */ "BIC16rc\000"
1866 /* 4389 */ "DADD16rc\000"
1867 /* 4398 */ "AND16rc\000"
1868 /* 4406 */ "CMP16rc\000"
1869 /* 4414 */ "XOR16rc\000"
1870 /* 4422 */ "BIS16rc\000"
1871 /* 4430 */ "BIT16rc\000"
1872 /* 4438 */ "MOV16rc\000"
1873 /* 4446 */ "SUB8rc\000"
1874 /* 4453 */ "SUBC8rc\000"
1875 /* 4461 */ "ADDC8rc\000"
1876 /* 4469 */ "BIC8rc\000"
1877 /* 4476 */ "DADD8rc\000"
1878 /* 4484 */ "AND8rc\000"
1879 /* 4491 */ "CMP8rc\000"
1880 /* 4498 */ "XOR8rc\000"
1881 /* 4505 */ "BIS8rc\000"
1882 /* 4512 */ "BIT8rc\000"
1883 /* 4519 */ "MOV8rc\000"
1884 /* 4526 */ "ADDframe\000"
1885 /* 4535 */ "PUSH16i\000"
1886 /* 4543 */ "Bi\000"
1887 /* 4546 */ "CALLi\000"
1888 /* 4552 */ "SUB16mi\000"
1889 /* 4560 */ "SUBC16mi\000"
1890 /* 4569 */ "ADDC16mi\000"
1891 /* 4578 */ "BIC16mi\000"
1892 /* 4586 */ "DADD16mi\000"
1893 /* 4595 */ "AND16mi\000"
1894 /* 4603 */ "CMP16mi\000"
1895 /* 4611 */ "XOR16mi\000"
1896 /* 4619 */ "BIS16mi\000"
1897 /* 4627 */ "BIT16mi\000"
1898 /* 4635 */ "MOV16mi\000"
1899 /* 4643 */ "SUB8mi\000"
1900 /* 4650 */ "SUBC8mi\000"
1901 /* 4658 */ "ADDC8mi\000"
1902 /* 4666 */ "BIC8mi\000"
1903 /* 4673 */ "DADD8mi\000"
1904 /* 4681 */ "AND8mi\000"
1905 /* 4688 */ "CMP8mi\000"
1906 /* 4695 */ "XOR8mi\000"
1907 /* 4702 */ "BIS8mi\000"
1908 /* 4709 */ "BIT8mi\000"
1909 /* 4716 */ "MOV8mi\000"
1910 /* 4723 */ "SUB16ri\000"
1911 /* 4731 */ "SUBC16ri\000"
1912 /* 4740 */ "ADDC16ri\000"
1913 /* 4749 */ "BIC16ri\000"
1914 /* 4757 */ "DADD16ri\000"
1915 /* 4766 */ "AND16ri\000"
1916 /* 4774 */ "CMP16ri\000"
1917 /* 4782 */ "XOR16ri\000"
1918 /* 4790 */ "BIS16ri\000"
1919 /* 4798 */ "BIT16ri\000"
1920 /* 4806 */ "MOV16ri\000"
1921 /* 4814 */ "SUB8ri\000"
1922 /* 4821 */ "SUBC8ri\000"
1923 /* 4829 */ "ADDC8ri\000"
1924 /* 4837 */ "BIC8ri\000"
1925 /* 4844 */ "DADD8ri\000"
1926 /* 4852 */ "AND8ri\000"
1927 /* 4859 */ "CMP8ri\000"
1928 /* 4866 */ "XOR8ri\000"
1929 /* 4873 */ "BIS8ri\000"
1930 /* 4880 */ "BIT8ri\000"
1931 /* 4887 */ "MOV8ri\000"
1932 /* 4894 */ "RRA16m\000"
1933 /* 4901 */ "SWPB16m\000"
1934 /* 4909 */ "RRC16m\000"
1935 /* 4916 */ "SEXT16m\000"
1936 /* 4924 */ "RRA8m\000"
1937 /* 4930 */ "RRC8m\000"
1938 /* 4936 */ "Bm\000"
1939 /* 4939 */ "CALLm\000"
1940 /* 4945 */ "SUB16mm\000"
1941 /* 4953 */ "SUBC16mm\000"
1942 /* 4962 */ "ADDC16mm\000"
1943 /* 4971 */ "BIC16mm\000"
1944 /* 4979 */ "DADD16mm\000"
1945 /* 4988 */ "AND16mm\000"
1946 /* 4996 */ "CMP16mm\000"
1947 /* 5004 */ "XOR16mm\000"
1948 /* 5012 */ "BIS16mm\000"
1949 /* 5020 */ "BIT16mm\000"
1950 /* 5028 */ "MOV16mm\000"
1951 /* 5036 */ "SUB8mm\000"
1952 /* 5043 */ "SUBC8mm\000"
1953 /* 5051 */ "ADDC8mm\000"
1954 /* 5059 */ "BIC8mm\000"
1955 /* 5066 */ "DADD8mm\000"
1956 /* 5074 */ "AND8mm\000"
1957 /* 5081 */ "CMP8mm\000"
1958 /* 5088 */ "XOR8mm\000"
1959 /* 5095 */ "BIS8mm\000"
1960 /* 5102 */ "BIT8mm\000"
1961 /* 5109 */ "MOV8mm\000"
1962 /* 5116 */ "SUB16rm\000"
1963 /* 5124 */ "SUBC16rm\000"
1964 /* 5133 */ "ADDC16rm\000"
1965 /* 5142 */ "BIC16rm\000"
1966 /* 5150 */ "DADD16rm\000"
1967 /* 5159 */ "AND16rm\000"
1968 /* 5167 */ "CMP16rm\000"
1969 /* 5175 */ "XOR16rm\000"
1970 /* 5183 */ "BIS16rm\000"
1971 /* 5191 */ "BIT16rm\000"
1972 /* 5199 */ "MOV16rm\000"
1973 /* 5207 */ "SUB8rm\000"
1974 /* 5214 */ "SUBC8rm\000"
1975 /* 5222 */ "ADDC8rm\000"
1976 /* 5230 */ "BIC8rm\000"
1977 /* 5237 */ "DADD8rm\000"
1978 /* 5245 */ "AND8rm\000"
1979 /* 5252 */ "CMP8rm\000"
1980 /* 5259 */ "XOR8rm\000"
1981 /* 5266 */ "BIS8rm\000"
1982 /* 5273 */ "BIT8rm\000"
1983 /* 5280 */ "MOV8rm\000"
1984 /* 5287 */ "RRA16n\000"
1985 /* 5294 */ "SWPB16n\000"
1986 /* 5302 */ "RRC16n\000"
1987 /* 5309 */ "SEXT16n\000"
1988 /* 5317 */ "RRA8n\000"
1989 /* 5323 */ "RRC8n\000"
1990 /* 5329 */ "CALLn\000"
1991 /* 5335 */ "SUB16mn\000"
1992 /* 5343 */ "SUBC16mn\000"
1993 /* 5352 */ "ADDC16mn\000"
1994 /* 5361 */ "BIC16mn\000"
1995 /* 5369 */ "DADD16mn\000"
1996 /* 5378 */ "AND16mn\000"
1997 /* 5386 */ "CMP16mn\000"
1998 /* 5394 */ "XOR16mn\000"
1999 /* 5402 */ "BIS16mn\000"
2000 /* 5410 */ "BIT16mn\000"
2001 /* 5418 */ "MOV16mn\000"
2002 /* 5426 */ "SUB8mn\000"
2003 /* 5433 */ "SUBC8mn\000"
2004 /* 5441 */ "ADDC8mn\000"
2005 /* 5449 */ "BIC8mn\000"
2006 /* 5456 */ "DADD8mn\000"
2007 /* 5464 */ "AND8mn\000"
2008 /* 5471 */ "CMP8mn\000"
2009 /* 5478 */ "XOR8mn\000"
2010 /* 5485 */ "BIS8mn\000"
2011 /* 5492 */ "BIT8mn\000"
2012 /* 5499 */ "MOV8mn\000"
2013 /* 5506 */ "SUB16rn\000"
2014 /* 5514 */ "SUBC16rn\000"
2015 /* 5523 */ "ADDC16rn\000"
2016 /* 5532 */ "BIC16rn\000"
2017 /* 5540 */ "DADD16rn\000"
2018 /* 5549 */ "AND16rn\000"
2019 /* 5557 */ "CMP16rn\000"
2020 /* 5565 */ "XOR16rn\000"
2021 /* 5573 */ "BIS16rn\000"
2022 /* 5581 */ "BIT16rn\000"
2023 /* 5589 */ "MOV16rn\000"
2024 /* 5597 */ "SUB8rn\000"
2025 /* 5604 */ "SUBC8rn\000"
2026 /* 5612 */ "ADDC8rn\000"
2027 /* 5620 */ "BIC8rn\000"
2028 /* 5627 */ "DADD8rn\000"
2029 /* 5635 */ "AND8rn\000"
2030 /* 5642 */ "CMP8rn\000"
2031 /* 5649 */ "XOR8rn\000"
2032 /* 5656 */ "BIS8rn\000"
2033 /* 5663 */ "BIT8rn\000"
2034 /* 5670 */ "MOV8rn\000"
2035 /* 5677 */ "RRA16p\000"
2036 /* 5684 */ "SWPB16p\000"
2037 /* 5692 */ "RRC16p\000"
2038 /* 5699 */ "SEXT16p\000"
2039 /* 5707 */ "RRA8p\000"
2040 /* 5713 */ "RRC8p\000"
2041 /* 5719 */ "CALLp\000"
2042 /* 5725 */ "SUB16mp\000"
2043 /* 5733 */ "SUBC16mp\000"
2044 /* 5742 */ "ADDC16mp\000"
2045 /* 5751 */ "BIC16mp\000"
2046 /* 5759 */ "DADD16mp\000"
2047 /* 5768 */ "AND16mp\000"
2048 /* 5776 */ "CMP16mp\000"
2049 /* 5784 */ "XOR16mp\000"
2050 /* 5792 */ "BIS16mp\000"
2051 /* 5800 */ "BIT16mp\000"
2052 /* 5808 */ "SUB8mp\000"
2053 /* 5815 */ "SUBC8mp\000"
2054 /* 5823 */ "ADDC8mp\000"
2055 /* 5831 */ "BIC8mp\000"
2056 /* 5838 */ "DADD8mp\000"
2057 /* 5846 */ "AND8mp\000"
2058 /* 5853 */ "CMP8mp\000"
2059 /* 5860 */ "XOR8mp\000"
2060 /* 5867 */ "BIS8mp\000"
2061 /* 5874 */ "BIT8mp\000"
2062 /* 5881 */ "SUB16rp\000"
2063 /* 5889 */ "SUBC16rp\000"
2064 /* 5898 */ "ADDC16rp\000"
2065 /* 5907 */ "BIC16rp\000"
2066 /* 5915 */ "DADD16rp\000"
2067 /* 5924 */ "AND16rp\000"
2068 /* 5932 */ "CMP16rp\000"
2069 /* 5940 */ "XOR16rp\000"
2070 /* 5948 */ "BIS16rp\000"
2071 /* 5956 */ "BIT16rp\000"
2072 /* 5964 */ "MOV16rp\000"
2073 /* 5972 */ "SUB8rp\000"
2074 /* 5979 */ "SUBC8rp\000"
2075 /* 5987 */ "ADDC8rp\000"
2076 /* 5995 */ "BIC8rp\000"
2077 /* 6002 */ "DADD8rp\000"
2078 /* 6010 */ "AND8rp\000"
2079 /* 6017 */ "CMP8rp\000"
2080 /* 6024 */ "XOR8rp\000"
2081 /* 6031 */ "BIS8rp\000"
2082 /* 6038 */ "BIT8rp\000"
2083 /* 6045 */ "MOV8rp\000"
2084 /* 6052 */ "RRA16r\000"
2085 /* 6059 */ "SWPB16r\000"
2086 /* 6067 */ "RRC16r\000"
2087 /* 6074 */ "PUSH16r\000"
2088 /* 6082 */ "POP16r\000"
2089 /* 6089 */ "SEXT16r\000"
2090 /* 6097 */ "ZEXT16r\000"
2091 /* 6105 */ "RRA8r\000"
2092 /* 6111 */ "RRC8r\000"
2093 /* 6117 */ "PUSH8r\000"
2094 /* 6124 */ "Br\000"
2095 /* 6127 */ "CALLr\000"
2096 /* 6133 */ "SUB16mr\000"
2097 /* 6141 */ "SUBC16mr\000"
2098 /* 6150 */ "ADDC16mr\000"
2099 /* 6159 */ "BIC16mr\000"
2100 /* 6167 */ "DADD16mr\000"
2101 /* 6176 */ "AND16mr\000"
2102 /* 6184 */ "CMP16mr\000"
2103 /* 6192 */ "XOR16mr\000"
2104 /* 6200 */ "BIS16mr\000"
2105 /* 6208 */ "BIT16mr\000"
2106 /* 6216 */ "MOV16mr\000"
2107 /* 6224 */ "SUB8mr\000"
2108 /* 6231 */ "SUBC8mr\000"
2109 /* 6239 */ "ADDC8mr\000"
2110 /* 6247 */ "BIC8mr\000"
2111 /* 6254 */ "DADD8mr\000"
2112 /* 6262 */ "AND8mr\000"
2113 /* 6269 */ "CMP8mr\000"
2114 /* 6276 */ "XOR8mr\000"
2115 /* 6283 */ "BIS8mr\000"
2116 /* 6290 */ "BIT8mr\000"
2117 /* 6297 */ "MOV8mr\000"
2118 /* 6304 */ "SUB16rr\000"
2119 /* 6312 */ "SUBC16rr\000"
2120 /* 6321 */ "ADDC16rr\000"
2121 /* 6330 */ "BIC16rr\000"
2122 /* 6338 */ "DADD16rr\000"
2123 /* 6347 */ "AND16rr\000"
2124 /* 6355 */ "CMP16rr\000"
2125 /* 6363 */ "XOR16rr\000"
2126 /* 6371 */ "BIS16rr\000"
2127 /* 6379 */ "BIT16rr\000"
2128 /* 6387 */ "MOV16rr\000"
2129 /* 6395 */ "SUB8rr\000"
2130 /* 6402 */ "SUBC8rr\000"
2131 /* 6410 */ "ADDC8rr\000"
2132 /* 6418 */ "BIC8rr\000"
2133 /* 6425 */ "DADD8rr\000"
2134 /* 6433 */ "AND8rr\000"
2135 /* 6440 */ "CMP8rr\000"
2136 /* 6447 */ "XOR8rr\000"
2137 /* 6454 */ "BIS8rr\000"
2138 /* 6461 */ "BIT8rr\000"
2139 /* 6468 */ "MOV8rr\000"
2140};
2141#ifdef __GNUC__
2142#pragma GCC diagnostic pop
2143#endif
2144
2145extern const unsigned MSP430InstrNameIndices[] = {
2146 1382U, 1793U, 2538U, 2151U, 1460U, 1441U, 1469U, 1629U,
2147 1175U, 1190U, 1141U, 1128U, 1217U, 3065U, 968U, 3752U,
2148 1154U, 1378U, 1450U, 738U, 4135U, 1417U, 860U, 3656U,
2149 565U, 689U, 726U, 2262U, 1617U, 3566U, 672U, 2473U,
2150 1310U, 3555U, 894U, 2446U, 2433U, 2599U, 3414U, 3437U,
2151 1549U, 1596U, 1569U, 1486U, 959U, 2564U, 2216U, 883U,
2152 4140U, 2717U, 2404U, 1016U, 3782U, 3812U, 1994U, 478U,
2153 185U, 1732U, 3884U, 3891U, 1759U, 1766U, 1773U, 1783U,
2154 543U, 2926U, 2889U, 2977U, 3826U, 2761U, 1538U, 2749U,
2155 1527U, 1139U, 1380U, 4058U, 978U, 993U, 1634U, 3382U,
2156 2984U, 3693U, 3001U, 2812U, 259U, 3048U, 3577U, 2953U,
2157 3725U, 1059U, 2575U, 646U, 233U, 628U, 3615U, 3596U,
2158 1972U, 2624U, 2643U, 379U, 323U, 353U, 364U, 304U,
2159 334U, 938U, 922U, 3095U, 1231U, 1248U, 494U, 191U,
2160 549U, 510U, 2931U, 2895U, 4042U, 2120U, 4025U, 2103U,
2161 445U, 168U, 3960U, 2038U, 1888U, 1835U, 2324U, 2302U,
2162 587U, 3335U, 718U, 1327U, 578U, 3401U, 3671U, 211U,
2163 3143U, 3532U, 3170U, 3796U, 251U, 3208U, 3833U, 3848U,
2164 3521U, 3509U, 3646U, 1302U, 3775U, 1204U, 3805U, 1513U,
2165 2710U, 2696U, 1506U, 2703U, 2946U, 1650U, 2379U, 2372U,
2166 2386U, 2393U, 3392U, 2208U, 759U, 2192U, 710U, 2200U,
2167 751U, 2184U, 702U, 2246U, 2238U, 1346U, 1338U, 3253U,
2168 3243U, 3233U, 3223U, 3273U, 3263U, 4086U, 4096U, 3283U,
2169 3296U, 4106U, 4116U, 3309U, 3322U, 403U, 147U, 1674U,
2170 128U, 297U, 3863U, 1738U, 1084U, 3936U, 1409U, 2517U,
2171 35U, 9U, 1295U, 18U, 0U, 2492U, 2524U, 1168U,
2172 3767U, 223U, 1386U, 1400U, 2354U, 2363U, 3356U, 3369U,
2173 2964U, 2009U, 3082U, 1068U, 1937U, 1947U, 808U, 823U,
2174 1824U, 1877U, 1909U, 1923U, 3898U, 3924U, 3910U, 767U,
2175 795U, 780U, 1265U, 1280U, 484U, 1431U, 2072U, 3994U,
2176 2096U, 4018U, 2971U, 619U, 609U, 2533U, 3461U, 838U,
2177 2793U, 2773U, 3489U, 3468U, 2827U, 2858U, 2844U, 3125U,
2178 4169U, 1110U, 4162U, 1092U, 3016U, 2425U, 2346U, 946U,
2179 1519U, 3031U, 2144U, 3038U, 1965U, 3023U, 2136U, 1957U,
2180 26U, 1370U, 1362U, 1354U, 3702U, 2740U, 3588U, 3633U,
2181 3735U, 2551U, 847U, 280U, 1037U, 907U, 431U, 154U,
2182 1702U, 3870U, 1745U, 134U, 3710U, 2501U, 2663U, 2679U,
2183 4126U, 867U, 1049U, 3428U, 2254U, 2295U, 2271U, 2283U,
2184 410U, 1681U, 386U, 1657U, 3943U, 2021U, 1856U, 1803U,
2185 462U, 1716U, 527U, 2911U, 2873U, 3977U, 2055U, 4001U,
2186 2079U, 4072U, 4079U, 4219U, 4587U, 4980U, 5370U, 5760U,
2187 6168U, 4390U, 4758U, 5151U, 5541U, 5916U, 6339U, 4306U,
2188 4674U, 5067U, 5457U, 5839U, 6255U, 4477U, 4845U, 5238U,
2189 5628U, 6003U, 6426U, 4201U, 4569U, 4962U, 5352U, 5742U,
2190 6150U, 4372U, 4740U, 5133U, 5523U, 5898U, 6321U, 4290U,
2191 4658U, 5051U, 5441U, 5823U, 6239U, 4461U, 4829U, 5222U,
2192 5612U, 5987U, 6410U, 4526U, 2167U, 2458U, 4227U, 4595U,
2193 4988U, 5378U, 5768U, 6176U, 4398U, 4766U, 5159U, 5549U,
2194 5924U, 6347U, 4313U, 4681U, 5074U, 5464U, 5846U, 6262U,
2195 4484U, 4852U, 5245U, 5635U, 6010U, 6433U, 4210U, 4578U,
2196 4971U, 5361U, 5751U, 6159U, 4381U, 4749U, 5142U, 5532U,
2197 5907U, 6330U, 4298U, 4666U, 5059U, 5449U, 5831U, 6247U,
2198 4469U, 4837U, 5230U, 5620U, 5995U, 6418U, 4251U, 4619U,
2199 5012U, 5402U, 5792U, 6200U, 4422U, 4790U, 5183U, 5573U,
2200 5948U, 6371U, 4334U, 4702U, 5095U, 5485U, 5867U, 6283U,
2201 4505U, 4873U, 5266U, 5656U, 6031U, 6454U, 4259U, 4627U,
2202 5020U, 5410U, 5800U, 6208U, 4430U, 4798U, 5191U, 5581U,
2203 5956U, 6379U, 4341U, 4709U, 5102U, 5492U, 5874U, 6290U,
2204 4512U, 4880U, 5273U, 5663U, 6038U, 6461U, 4543U, 4936U,
2205 6124U, 4546U, 4939U, 5329U, 5719U, 6127U, 4235U, 4603U,
2206 4996U, 5386U, 5776U, 6184U, 4406U, 4774U, 5167U, 5557U,
2207 5932U, 6355U, 4320U, 4688U, 5081U, 5471U, 5853U, 6269U,
2208 4491U, 4859U, 5252U, 5642U, 6017U, 6440U, 4218U, 4586U,
2209 4979U, 5369U, 5759U, 6167U, 4389U, 4757U, 5150U, 5540U,
2210 5915U, 6338U, 4305U, 4673U, 5066U, 5456U, 5838U, 6254U,
2211 4476U, 4844U, 5237U, 5627U, 6002U, 6425U, 207U, 2400U,
2212 4267U, 4635U, 5028U, 5418U, 6216U, 4438U, 4806U, 5199U,
2213 5589U, 5964U, 6387U, 4348U, 4716U, 5109U, 5499U, 6297U,
2214 4519U, 4887U, 5280U, 5670U, 6045U, 6468U, 98U, 109U,
2215 6082U, 4176U, 4535U, 6074U, 6117U, 3424U, 1395U, 4894U,
2216 5287U, 5677U, 6052U, 4924U, 5317U, 5707U, 6105U, 4909U,
2217 5302U, 5692U, 6067U, 4930U, 5323U, 5713U, 6111U, 49U,
2218 82U, 4916U, 5309U, 5699U, 6089U, 4184U, 4552U, 4945U,
2219 5335U, 5725U, 6133U, 4355U, 4723U, 5116U, 5506U, 5881U,
2220 6304U, 4275U, 4643U, 5036U, 5426U, 5808U, 6224U, 4446U,
2221 4814U, 5207U, 5597U, 5972U, 6395U, 4192U, 4560U, 4953U,
2222 5343U, 5733U, 6141U, 4363U, 4731U, 5124U, 5514U, 5889U,
2223 6312U, 4282U, 4650U, 5043U, 5433U, 5815U, 6231U, 4453U,
2224 4821U, 5214U, 5604U, 5979U, 6402U, 4901U, 5294U, 5684U,
2225 6059U, 68U, 120U, 56U, 88U, 43U, 77U, 62U,
2226 93U, 4243U, 4611U, 5004U, 5394U, 5784U, 6192U, 4414U,
2227 4782U, 5175U, 5565U, 5940U, 6363U, 4327U, 4695U, 5088U,
2228 5478U, 5860U, 6276U, 4498U, 4866U, 5259U, 5649U, 6024U,
2229 6447U, 6097U,
2230};
2231
2232static inline void InitMSP430MCInstrInfo(MCInstrInfo *II) {
2233 II->InitMCInstrInfo(MSP430Descs.Insts, MSP430InstrNameIndices, MSP430InstrNameData, nullptr, nullptr, 666, nullptr, 0);
2234}
2235
2236
2237} // namespace llvm
2238
2239#endif // GET_INSTRINFO_MC_DESC
2240
2241#ifdef GET_INSTRINFO_HEADER
2242#undef GET_INSTRINFO_HEADER
2243
2244namespace llvm {
2245
2246struct MSP430GenInstrInfo : public TargetInstrInfo {
2247 explicit MSP430GenInstrInfo(const TargetSubtargetInfo &STI, const TargetRegisterInfo &TRI, unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u, unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u);
2248 ~MSP430GenInstrInfo() override = default;
2249};
2250
2251} // namespace llvm
2252
2253namespace llvm::MSP430 {
2254
2255
2256} // namespace llvm::MSP430
2257
2258#endif // GET_INSTRINFO_HEADER
2259
2260#ifdef GET_INSTRINFO_HELPER_DECLS
2261#undef GET_INSTRINFO_HELPER_DECLS
2262
2263
2264#endif // GET_INSTRINFO_HELPER_DECLS
2265
2266#ifdef GET_INSTRINFO_HELPERS
2267#undef GET_INSTRINFO_HELPERS
2268
2269
2270#endif // GET_INSTRINFO_HELPERS
2271
2272#ifdef GET_INSTRINFO_CTOR_DTOR
2273#undef GET_INSTRINFO_CTOR_DTOR
2274
2275namespace llvm {
2276
2277extern const MSP430InstrTable MSP430Descs;
2278extern const unsigned MSP430InstrNameIndices[];
2279extern const char MSP430InstrNameData[];
2280MSP430GenInstrInfo::MSP430GenInstrInfo(const TargetSubtargetInfo &STI, const TargetRegisterInfo &TRI, unsigned CFSetupOpcode, unsigned CFDestroyOpcode, unsigned CatchRetOpcode, unsigned ReturnOpcode)
2281 : TargetInstrInfo(TRI, CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) {
2282 InitMCInstrInfo(MSP430Descs.Insts, MSP430InstrNameIndices, MSP430InstrNameData, nullptr, nullptr, 666);
2283}
2284
2285} // namespace llvm
2286
2287#endif // GET_INSTRINFO_CTOR_DTOR
2288
2289#ifdef GET_INSTRINFO_MC_HELPER_DECLS
2290#undef GET_INSTRINFO_MC_HELPER_DECLS
2291
2292namespace llvm {
2293
2294class MCInst;
2295class FeatureBitset;
2296
2297namespace MSP430_MC {
2298
2299void verifyInstructionPredicates(unsigned Opcode, const FeatureBitset &Features);
2300
2301} // namespace MSP430_MC
2302
2303} // namespace llvm
2304
2305#endif // GET_INSTRINFO_MC_HELPER_DECLS
2306
2307#ifdef GET_INSTRINFO_MC_HELPERS
2308#undef GET_INSTRINFO_MC_HELPERS
2309
2310namespace llvm::MSP430_MC {
2311
2312
2313} // namespace llvm::MSP430_MC
2314
2315#endif // GET_INSTRINFO_MC_HELPERS
2316
2317#if (defined(ENABLE_INSTR_PREDICATE_VERIFIER) && !defined(NDEBUG)) ||\
2318 defined(GET_AVAILABLE_OPCODE_CHECKER)
2319#define GET_COMPUTE_FEATURES
2320#endif
2321#ifdef GET_COMPUTE_FEATURES
2322#undef GET_COMPUTE_FEATURES
2323
2324namespace llvm::MSP430_MC {
2325
2326// Bits for subtarget features that participate in instruction matching.
2327enum SubtargetFeatureBits : uint8_t {
2328};
2329
2330inline FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) {
2331 FeatureBitset Features;
2332 return Features;
2333}
2334
2335inline FeatureBitset computeRequiredFeatures(unsigned Opcode) {
2336 enum : uint8_t {
2337 CEFBS_None,
2338 };
2339
2340 static constexpr FeatureBitset FeatureBitsets[] = {
2341 {}, // CEFBS_None
2342 };
2343 static constexpr uint8_t RequiredFeaturesRefs[] = {
2344 CEFBS_None, // PHI
2345 CEFBS_None, // INLINEASM
2346 CEFBS_None, // INLINEASM_BR
2347 CEFBS_None, // CFI_INSTRUCTION
2348 CEFBS_None, // EH_LABEL
2349 CEFBS_None, // GC_LABEL
2350 CEFBS_None, // ANNOTATION_LABEL
2351 CEFBS_None, // KILL
2352 CEFBS_None, // EXTRACT_SUBREG
2353 CEFBS_None, // INSERT_SUBREG
2354 CEFBS_None, // IMPLICIT_DEF
2355 CEFBS_None, // INIT_UNDEF
2356 CEFBS_None, // SUBREG_TO_REG
2357 CEFBS_None, // COPY_TO_REGCLASS
2358 CEFBS_None, // DBG_VALUE
2359 CEFBS_None, // DBG_VALUE_LIST
2360 CEFBS_None, // DBG_INSTR_REF
2361 CEFBS_None, // DBG_PHI
2362 CEFBS_None, // DBG_LABEL
2363 CEFBS_None, // REG_SEQUENCE
2364 CEFBS_None, // COPY
2365 CEFBS_None, // COPY_LANEMASK
2366 CEFBS_None, // BUNDLE
2367 CEFBS_None, // LIFETIME_START
2368 CEFBS_None, // LIFETIME_END
2369 CEFBS_None, // PSEUDO_PROBE
2370 CEFBS_None, // ARITH_FENCE
2371 CEFBS_None, // STACKMAP
2372 CEFBS_None, // FENTRY_CALL
2373 CEFBS_None, // PATCHPOINT
2374 CEFBS_None, // LOAD_STACK_GUARD
2375 CEFBS_None, // PREALLOCATED_SETUP
2376 CEFBS_None, // PREALLOCATED_ARG
2377 CEFBS_None, // STATEPOINT
2378 CEFBS_None, // LOCAL_ESCAPE
2379 CEFBS_None, // FAULTING_OP
2380 CEFBS_None, // PATCHABLE_OP
2381 CEFBS_None, // PATCHABLE_FUNCTION_ENTER
2382 CEFBS_None, // PATCHABLE_RET
2383 CEFBS_None, // PATCHABLE_FUNCTION_EXIT
2384 CEFBS_None, // PATCHABLE_TAIL_CALL
2385 CEFBS_None, // PATCHABLE_EVENT_CALL
2386 CEFBS_None, // PATCHABLE_TYPED_EVENT_CALL
2387 CEFBS_None, // ICALL_BRANCH_FUNNEL
2388 CEFBS_None, // FAKE_USE
2389 CEFBS_None, // MEMBARRIER
2390 CEFBS_None, // JUMP_TABLE_DEBUG_INFO
2391 CEFBS_None, // RELOC_NONE
2392 CEFBS_None, // CONVERGENCECTRL_ENTRY
2393 CEFBS_None, // CONVERGENCECTRL_ANCHOR
2394 CEFBS_None, // CONVERGENCECTRL_LOOP
2395 CEFBS_None, // CONVERGENCECTRL_GLUE
2396 CEFBS_None, // G_ASSERT_SEXT
2397 CEFBS_None, // G_ASSERT_ZEXT
2398 CEFBS_None, // G_ASSERT_ALIGN
2399 CEFBS_None, // G_ADD
2400 CEFBS_None, // G_SUB
2401 CEFBS_None, // G_MUL
2402 CEFBS_None, // G_SDIV
2403 CEFBS_None, // G_UDIV
2404 CEFBS_None, // G_SREM
2405 CEFBS_None, // G_UREM
2406 CEFBS_None, // G_SDIVREM
2407 CEFBS_None, // G_UDIVREM
2408 CEFBS_None, // G_AND
2409 CEFBS_None, // G_OR
2410 CEFBS_None, // G_XOR
2411 CEFBS_None, // G_ABDS
2412 CEFBS_None, // G_ABDU
2413 CEFBS_None, // G_UAVGFLOOR
2414 CEFBS_None, // G_UAVGCEIL
2415 CEFBS_None, // G_SAVGFLOOR
2416 CEFBS_None, // G_SAVGCEIL
2417 CEFBS_None, // G_IMPLICIT_DEF
2418 CEFBS_None, // G_PHI
2419 CEFBS_None, // G_FRAME_INDEX
2420 CEFBS_None, // G_GLOBAL_VALUE
2421 CEFBS_None, // G_PTRAUTH_GLOBAL_VALUE
2422 CEFBS_None, // G_CONSTANT_POOL
2423 CEFBS_None, // G_EXTRACT
2424 CEFBS_None, // G_UNMERGE_VALUES
2425 CEFBS_None, // G_INSERT
2426 CEFBS_None, // G_MERGE_VALUES
2427 CEFBS_None, // G_BUILD_VECTOR
2428 CEFBS_None, // G_BUILD_VECTOR_TRUNC
2429 CEFBS_None, // G_CONCAT_VECTORS
2430 CEFBS_None, // G_PTRTOINT
2431 CEFBS_None, // G_INTTOPTR
2432 CEFBS_None, // G_BITCAST
2433 CEFBS_None, // G_FREEZE
2434 CEFBS_None, // G_CONSTANT_FOLD_BARRIER
2435 CEFBS_None, // G_INTRINSIC_FPTRUNC_ROUND
2436 CEFBS_None, // G_INTRINSIC_TRUNC
2437 CEFBS_None, // G_INTRINSIC_ROUND
2438 CEFBS_None, // G_INTRINSIC_LRINT
2439 CEFBS_None, // G_INTRINSIC_LLRINT
2440 CEFBS_None, // G_INTRINSIC_ROUNDEVEN
2441 CEFBS_None, // G_READCYCLECOUNTER
2442 CEFBS_None, // G_READSTEADYCOUNTER
2443 CEFBS_None, // G_LOAD
2444 CEFBS_None, // G_SEXTLOAD
2445 CEFBS_None, // G_ZEXTLOAD
2446 CEFBS_None, // G_INDEXED_LOAD
2447 CEFBS_None, // G_INDEXED_SEXTLOAD
2448 CEFBS_None, // G_INDEXED_ZEXTLOAD
2449 CEFBS_None, // G_STORE
2450 CEFBS_None, // G_INDEXED_STORE
2451 CEFBS_None, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
2452 CEFBS_None, // G_ATOMIC_CMPXCHG
2453 CEFBS_None, // G_ATOMICRMW_XCHG
2454 CEFBS_None, // G_ATOMICRMW_ADD
2455 CEFBS_None, // G_ATOMICRMW_SUB
2456 CEFBS_None, // G_ATOMICRMW_AND
2457 CEFBS_None, // G_ATOMICRMW_NAND
2458 CEFBS_None, // G_ATOMICRMW_OR
2459 CEFBS_None, // G_ATOMICRMW_XOR
2460 CEFBS_None, // G_ATOMICRMW_MAX
2461 CEFBS_None, // G_ATOMICRMW_MIN
2462 CEFBS_None, // G_ATOMICRMW_UMAX
2463 CEFBS_None, // G_ATOMICRMW_UMIN
2464 CEFBS_None, // G_ATOMICRMW_FADD
2465 CEFBS_None, // G_ATOMICRMW_FSUB
2466 CEFBS_None, // G_ATOMICRMW_FMAX
2467 CEFBS_None, // G_ATOMICRMW_FMIN
2468 CEFBS_None, // G_ATOMICRMW_FMAXIMUM
2469 CEFBS_None, // G_ATOMICRMW_FMINIMUM
2470 CEFBS_None, // G_ATOMICRMW_UINC_WRAP
2471 CEFBS_None, // G_ATOMICRMW_UDEC_WRAP
2472 CEFBS_None, // G_ATOMICRMW_USUB_COND
2473 CEFBS_None, // G_ATOMICRMW_USUB_SAT
2474 CEFBS_None, // G_FENCE
2475 CEFBS_None, // G_PREFETCH
2476 CEFBS_None, // G_BRCOND
2477 CEFBS_None, // G_BRINDIRECT
2478 CEFBS_None, // G_INVOKE_REGION_START
2479 CEFBS_None, // G_INTRINSIC
2480 CEFBS_None, // G_INTRINSIC_W_SIDE_EFFECTS
2481 CEFBS_None, // G_INTRINSIC_CONVERGENT
2482 CEFBS_None, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
2483 CEFBS_None, // G_ANYEXT
2484 CEFBS_None, // G_TRUNC
2485 CEFBS_None, // G_TRUNC_SSAT_S
2486 CEFBS_None, // G_TRUNC_SSAT_U
2487 CEFBS_None, // G_TRUNC_USAT_U
2488 CEFBS_None, // G_CONSTANT
2489 CEFBS_None, // G_FCONSTANT
2490 CEFBS_None, // G_VASTART
2491 CEFBS_None, // G_VAARG
2492 CEFBS_None, // G_SEXT
2493 CEFBS_None, // G_SEXT_INREG
2494 CEFBS_None, // G_ZEXT
2495 CEFBS_None, // G_SHL
2496 CEFBS_None, // G_LSHR
2497 CEFBS_None, // G_ASHR
2498 CEFBS_None, // G_FSHL
2499 CEFBS_None, // G_FSHR
2500 CEFBS_None, // G_ROTR
2501 CEFBS_None, // G_ROTL
2502 CEFBS_None, // G_ICMP
2503 CEFBS_None, // G_FCMP
2504 CEFBS_None, // G_SCMP
2505 CEFBS_None, // G_UCMP
2506 CEFBS_None, // G_SELECT
2507 CEFBS_None, // G_UADDO
2508 CEFBS_None, // G_UADDE
2509 CEFBS_None, // G_USUBO
2510 CEFBS_None, // G_USUBE
2511 CEFBS_None, // G_SADDO
2512 CEFBS_None, // G_SADDE
2513 CEFBS_None, // G_SSUBO
2514 CEFBS_None, // G_SSUBE
2515 CEFBS_None, // G_UMULO
2516 CEFBS_None, // G_SMULO
2517 CEFBS_None, // G_UMULH
2518 CEFBS_None, // G_SMULH
2519 CEFBS_None, // G_UADDSAT
2520 CEFBS_None, // G_SADDSAT
2521 CEFBS_None, // G_USUBSAT
2522 CEFBS_None, // G_SSUBSAT
2523 CEFBS_None, // G_USHLSAT
2524 CEFBS_None, // G_SSHLSAT
2525 CEFBS_None, // G_SMULFIX
2526 CEFBS_None, // G_UMULFIX
2527 CEFBS_None, // G_SMULFIXSAT
2528 CEFBS_None, // G_UMULFIXSAT
2529 CEFBS_None, // G_SDIVFIX
2530 CEFBS_None, // G_UDIVFIX
2531 CEFBS_None, // G_SDIVFIXSAT
2532 CEFBS_None, // G_UDIVFIXSAT
2533 CEFBS_None, // G_FADD
2534 CEFBS_None, // G_FSUB
2535 CEFBS_None, // G_FMUL
2536 CEFBS_None, // G_FMA
2537 CEFBS_None, // G_FMAD
2538 CEFBS_None, // G_FDIV
2539 CEFBS_None, // G_FREM
2540 CEFBS_None, // G_FMODF
2541 CEFBS_None, // G_FPOW
2542 CEFBS_None, // G_FPOWI
2543 CEFBS_None, // G_FEXP
2544 CEFBS_None, // G_FEXP2
2545 CEFBS_None, // G_FEXP10
2546 CEFBS_None, // G_FLOG
2547 CEFBS_None, // G_FLOG2
2548 CEFBS_None, // G_FLOG10
2549 CEFBS_None, // G_FLDEXP
2550 CEFBS_None, // G_FFREXP
2551 CEFBS_None, // G_FNEG
2552 CEFBS_None, // G_FPEXT
2553 CEFBS_None, // G_FPTRUNC
2554 CEFBS_None, // G_FPTOSI
2555 CEFBS_None, // G_FPTOUI
2556 CEFBS_None, // G_SITOFP
2557 CEFBS_None, // G_UITOFP
2558 CEFBS_None, // G_FPTOSI_SAT
2559 CEFBS_None, // G_FPTOUI_SAT
2560 CEFBS_None, // G_FABS
2561 CEFBS_None, // G_FCOPYSIGN
2562 CEFBS_None, // G_IS_FPCLASS
2563 CEFBS_None, // G_FCANONICALIZE
2564 CEFBS_None, // G_FMINNUM
2565 CEFBS_None, // G_FMAXNUM
2566 CEFBS_None, // G_FMINNUM_IEEE
2567 CEFBS_None, // G_FMAXNUM_IEEE
2568 CEFBS_None, // G_FMINIMUM
2569 CEFBS_None, // G_FMAXIMUM
2570 CEFBS_None, // G_FMINIMUMNUM
2571 CEFBS_None, // G_FMAXIMUMNUM
2572 CEFBS_None, // G_GET_FPENV
2573 CEFBS_None, // G_SET_FPENV
2574 CEFBS_None, // G_RESET_FPENV
2575 CEFBS_None, // G_GET_FPMODE
2576 CEFBS_None, // G_SET_FPMODE
2577 CEFBS_None, // G_RESET_FPMODE
2578 CEFBS_None, // G_GET_ROUNDING
2579 CEFBS_None, // G_SET_ROUNDING
2580 CEFBS_None, // G_PTR_ADD
2581 CEFBS_None, // G_PTRMASK
2582 CEFBS_None, // G_SMIN
2583 CEFBS_None, // G_SMAX
2584 CEFBS_None, // G_UMIN
2585 CEFBS_None, // G_UMAX
2586 CEFBS_None, // G_ABS
2587 CEFBS_None, // G_LROUND
2588 CEFBS_None, // G_LLROUND
2589 CEFBS_None, // G_BR
2590 CEFBS_None, // G_BRJT
2591 CEFBS_None, // G_VSCALE
2592 CEFBS_None, // G_INSERT_SUBVECTOR
2593 CEFBS_None, // G_EXTRACT_SUBVECTOR
2594 CEFBS_None, // G_INSERT_VECTOR_ELT
2595 CEFBS_None, // G_EXTRACT_VECTOR_ELT
2596 CEFBS_None, // G_SHUFFLE_VECTOR
2597 CEFBS_None, // G_SPLAT_VECTOR
2598 CEFBS_None, // G_STEP_VECTOR
2599 CEFBS_None, // G_VECTOR_COMPRESS
2600 CEFBS_None, // G_CTTZ
2601 CEFBS_None, // G_CTTZ_ZERO_UNDEF
2602 CEFBS_None, // G_CTLZ
2603 CEFBS_None, // G_CTLZ_ZERO_UNDEF
2604 CEFBS_None, // G_CTLS
2605 CEFBS_None, // G_CTPOP
2606 CEFBS_None, // G_BSWAP
2607 CEFBS_None, // G_BITREVERSE
2608 CEFBS_None, // G_FCEIL
2609 CEFBS_None, // G_FCOS
2610 CEFBS_None, // G_FSIN
2611 CEFBS_None, // G_FSINCOS
2612 CEFBS_None, // G_FTAN
2613 CEFBS_None, // G_FACOS
2614 CEFBS_None, // G_FASIN
2615 CEFBS_None, // G_FATAN
2616 CEFBS_None, // G_FATAN2
2617 CEFBS_None, // G_FCOSH
2618 CEFBS_None, // G_FSINH
2619 CEFBS_None, // G_FTANH
2620 CEFBS_None, // G_FSQRT
2621 CEFBS_None, // G_FFLOOR
2622 CEFBS_None, // G_FRINT
2623 CEFBS_None, // G_FNEARBYINT
2624 CEFBS_None, // G_ADDRSPACE_CAST
2625 CEFBS_None, // G_BLOCK_ADDR
2626 CEFBS_None, // G_JUMP_TABLE
2627 CEFBS_None, // G_DYN_STACKALLOC
2628 CEFBS_None, // G_STACKSAVE
2629 CEFBS_None, // G_STACKRESTORE
2630 CEFBS_None, // G_STRICT_FADD
2631 CEFBS_None, // G_STRICT_FSUB
2632 CEFBS_None, // G_STRICT_FMUL
2633 CEFBS_None, // G_STRICT_FDIV
2634 CEFBS_None, // G_STRICT_FREM
2635 CEFBS_None, // G_STRICT_FMA
2636 CEFBS_None, // G_STRICT_FSQRT
2637 CEFBS_None, // G_STRICT_FLDEXP
2638 CEFBS_None, // G_READ_REGISTER
2639 CEFBS_None, // G_WRITE_REGISTER
2640 CEFBS_None, // G_MEMCPY
2641 CEFBS_None, // G_MEMCPY_INLINE
2642 CEFBS_None, // G_MEMMOVE
2643 CEFBS_None, // G_MEMSET
2644 CEFBS_None, // G_BZERO
2645 CEFBS_None, // G_TRAP
2646 CEFBS_None, // G_DEBUGTRAP
2647 CEFBS_None, // G_UBSANTRAP
2648 CEFBS_None, // G_VECREDUCE_SEQ_FADD
2649 CEFBS_None, // G_VECREDUCE_SEQ_FMUL
2650 CEFBS_None, // G_VECREDUCE_FADD
2651 CEFBS_None, // G_VECREDUCE_FMUL
2652 CEFBS_None, // G_VECREDUCE_FMAX
2653 CEFBS_None, // G_VECREDUCE_FMIN
2654 CEFBS_None, // G_VECREDUCE_FMAXIMUM
2655 CEFBS_None, // G_VECREDUCE_FMINIMUM
2656 CEFBS_None, // G_VECREDUCE_ADD
2657 CEFBS_None, // G_VECREDUCE_MUL
2658 CEFBS_None, // G_VECREDUCE_AND
2659 CEFBS_None, // G_VECREDUCE_OR
2660 CEFBS_None, // G_VECREDUCE_XOR
2661 CEFBS_None, // G_VECREDUCE_SMAX
2662 CEFBS_None, // G_VECREDUCE_SMIN
2663 CEFBS_None, // G_VECREDUCE_UMAX
2664 CEFBS_None, // G_VECREDUCE_UMIN
2665 CEFBS_None, // G_SBFX
2666 CEFBS_None, // G_UBFX
2667 CEFBS_None, // ADD16mc
2668 CEFBS_None, // ADD16mi
2669 CEFBS_None, // ADD16mm
2670 CEFBS_None, // ADD16mn
2671 CEFBS_None, // ADD16mp
2672 CEFBS_None, // ADD16mr
2673 CEFBS_None, // ADD16rc
2674 CEFBS_None, // ADD16ri
2675 CEFBS_None, // ADD16rm
2676 CEFBS_None, // ADD16rn
2677 CEFBS_None, // ADD16rp
2678 CEFBS_None, // ADD16rr
2679 CEFBS_None, // ADD8mc
2680 CEFBS_None, // ADD8mi
2681 CEFBS_None, // ADD8mm
2682 CEFBS_None, // ADD8mn
2683 CEFBS_None, // ADD8mp
2684 CEFBS_None, // ADD8mr
2685 CEFBS_None, // ADD8rc
2686 CEFBS_None, // ADD8ri
2687 CEFBS_None, // ADD8rm
2688 CEFBS_None, // ADD8rn
2689 CEFBS_None, // ADD8rp
2690 CEFBS_None, // ADD8rr
2691 CEFBS_None, // ADDC16mc
2692 CEFBS_None, // ADDC16mi
2693 CEFBS_None, // ADDC16mm
2694 CEFBS_None, // ADDC16mn
2695 CEFBS_None, // ADDC16mp
2696 CEFBS_None, // ADDC16mr
2697 CEFBS_None, // ADDC16rc
2698 CEFBS_None, // ADDC16ri
2699 CEFBS_None, // ADDC16rm
2700 CEFBS_None, // ADDC16rn
2701 CEFBS_None, // ADDC16rp
2702 CEFBS_None, // ADDC16rr
2703 CEFBS_None, // ADDC8mc
2704 CEFBS_None, // ADDC8mi
2705 CEFBS_None, // ADDC8mm
2706 CEFBS_None, // ADDC8mn
2707 CEFBS_None, // ADDC8mp
2708 CEFBS_None, // ADDC8mr
2709 CEFBS_None, // ADDC8rc
2710 CEFBS_None, // ADDC8ri
2711 CEFBS_None, // ADDC8rm
2712 CEFBS_None, // ADDC8rn
2713 CEFBS_None, // ADDC8rp
2714 CEFBS_None, // ADDC8rr
2715 CEFBS_None, // ADDframe
2716 CEFBS_None, // ADJCALLSTACKDOWN
2717 CEFBS_None, // ADJCALLSTACKUP
2718 CEFBS_None, // AND16mc
2719 CEFBS_None, // AND16mi
2720 CEFBS_None, // AND16mm
2721 CEFBS_None, // AND16mn
2722 CEFBS_None, // AND16mp
2723 CEFBS_None, // AND16mr
2724 CEFBS_None, // AND16rc
2725 CEFBS_None, // AND16ri
2726 CEFBS_None, // AND16rm
2727 CEFBS_None, // AND16rn
2728 CEFBS_None, // AND16rp
2729 CEFBS_None, // AND16rr
2730 CEFBS_None, // AND8mc
2731 CEFBS_None, // AND8mi
2732 CEFBS_None, // AND8mm
2733 CEFBS_None, // AND8mn
2734 CEFBS_None, // AND8mp
2735 CEFBS_None, // AND8mr
2736 CEFBS_None, // AND8rc
2737 CEFBS_None, // AND8ri
2738 CEFBS_None, // AND8rm
2739 CEFBS_None, // AND8rn
2740 CEFBS_None, // AND8rp
2741 CEFBS_None, // AND8rr
2742 CEFBS_None, // BIC16mc
2743 CEFBS_None, // BIC16mi
2744 CEFBS_None, // BIC16mm
2745 CEFBS_None, // BIC16mn
2746 CEFBS_None, // BIC16mp
2747 CEFBS_None, // BIC16mr
2748 CEFBS_None, // BIC16rc
2749 CEFBS_None, // BIC16ri
2750 CEFBS_None, // BIC16rm
2751 CEFBS_None, // BIC16rn
2752 CEFBS_None, // BIC16rp
2753 CEFBS_None, // BIC16rr
2754 CEFBS_None, // BIC8mc
2755 CEFBS_None, // BIC8mi
2756 CEFBS_None, // BIC8mm
2757 CEFBS_None, // BIC8mn
2758 CEFBS_None, // BIC8mp
2759 CEFBS_None, // BIC8mr
2760 CEFBS_None, // BIC8rc
2761 CEFBS_None, // BIC8ri
2762 CEFBS_None, // BIC8rm
2763 CEFBS_None, // BIC8rn
2764 CEFBS_None, // BIC8rp
2765 CEFBS_None, // BIC8rr
2766 CEFBS_None, // BIS16mc
2767 CEFBS_None, // BIS16mi
2768 CEFBS_None, // BIS16mm
2769 CEFBS_None, // BIS16mn
2770 CEFBS_None, // BIS16mp
2771 CEFBS_None, // BIS16mr
2772 CEFBS_None, // BIS16rc
2773 CEFBS_None, // BIS16ri
2774 CEFBS_None, // BIS16rm
2775 CEFBS_None, // BIS16rn
2776 CEFBS_None, // BIS16rp
2777 CEFBS_None, // BIS16rr
2778 CEFBS_None, // BIS8mc
2779 CEFBS_None, // BIS8mi
2780 CEFBS_None, // BIS8mm
2781 CEFBS_None, // BIS8mn
2782 CEFBS_None, // BIS8mp
2783 CEFBS_None, // BIS8mr
2784 CEFBS_None, // BIS8rc
2785 CEFBS_None, // BIS8ri
2786 CEFBS_None, // BIS8rm
2787 CEFBS_None, // BIS8rn
2788 CEFBS_None, // BIS8rp
2789 CEFBS_None, // BIS8rr
2790 CEFBS_None, // BIT16mc
2791 CEFBS_None, // BIT16mi
2792 CEFBS_None, // BIT16mm
2793 CEFBS_None, // BIT16mn
2794 CEFBS_None, // BIT16mp
2795 CEFBS_None, // BIT16mr
2796 CEFBS_None, // BIT16rc
2797 CEFBS_None, // BIT16ri
2798 CEFBS_None, // BIT16rm
2799 CEFBS_None, // BIT16rn
2800 CEFBS_None, // BIT16rp
2801 CEFBS_None, // BIT16rr
2802 CEFBS_None, // BIT8mc
2803 CEFBS_None, // BIT8mi
2804 CEFBS_None, // BIT8mm
2805 CEFBS_None, // BIT8mn
2806 CEFBS_None, // BIT8mp
2807 CEFBS_None, // BIT8mr
2808 CEFBS_None, // BIT8rc
2809 CEFBS_None, // BIT8ri
2810 CEFBS_None, // BIT8rm
2811 CEFBS_None, // BIT8rn
2812 CEFBS_None, // BIT8rp
2813 CEFBS_None, // BIT8rr
2814 CEFBS_None, // Bi
2815 CEFBS_None, // Bm
2816 CEFBS_None, // Br
2817 CEFBS_None, // CALLi
2818 CEFBS_None, // CALLm
2819 CEFBS_None, // CALLn
2820 CEFBS_None, // CALLp
2821 CEFBS_None, // CALLr
2822 CEFBS_None, // CMP16mc
2823 CEFBS_None, // CMP16mi
2824 CEFBS_None, // CMP16mm
2825 CEFBS_None, // CMP16mn
2826 CEFBS_None, // CMP16mp
2827 CEFBS_None, // CMP16mr
2828 CEFBS_None, // CMP16rc
2829 CEFBS_None, // CMP16ri
2830 CEFBS_None, // CMP16rm
2831 CEFBS_None, // CMP16rn
2832 CEFBS_None, // CMP16rp
2833 CEFBS_None, // CMP16rr
2834 CEFBS_None, // CMP8mc
2835 CEFBS_None, // CMP8mi
2836 CEFBS_None, // CMP8mm
2837 CEFBS_None, // CMP8mn
2838 CEFBS_None, // CMP8mp
2839 CEFBS_None, // CMP8mr
2840 CEFBS_None, // CMP8rc
2841 CEFBS_None, // CMP8ri
2842 CEFBS_None, // CMP8rm
2843 CEFBS_None, // CMP8rn
2844 CEFBS_None, // CMP8rp
2845 CEFBS_None, // CMP8rr
2846 CEFBS_None, // DADD16mc
2847 CEFBS_None, // DADD16mi
2848 CEFBS_None, // DADD16mm
2849 CEFBS_None, // DADD16mn
2850 CEFBS_None, // DADD16mp
2851 CEFBS_None, // DADD16mr
2852 CEFBS_None, // DADD16rc
2853 CEFBS_None, // DADD16ri
2854 CEFBS_None, // DADD16rm
2855 CEFBS_None, // DADD16rn
2856 CEFBS_None, // DADD16rp
2857 CEFBS_None, // DADD16rr
2858 CEFBS_None, // DADD8mc
2859 CEFBS_None, // DADD8mi
2860 CEFBS_None, // DADD8mm
2861 CEFBS_None, // DADD8mn
2862 CEFBS_None, // DADD8mp
2863 CEFBS_None, // DADD8mr
2864 CEFBS_None, // DADD8rc
2865 CEFBS_None, // DADD8ri
2866 CEFBS_None, // DADD8rm
2867 CEFBS_None, // DADD8rn
2868 CEFBS_None, // DADD8rp
2869 CEFBS_None, // DADD8rr
2870 CEFBS_None, // JCC
2871 CEFBS_None, // JMP
2872 CEFBS_None, // MOV16mc
2873 CEFBS_None, // MOV16mi
2874 CEFBS_None, // MOV16mm
2875 CEFBS_None, // MOV16mn
2876 CEFBS_None, // MOV16mr
2877 CEFBS_None, // MOV16rc
2878 CEFBS_None, // MOV16ri
2879 CEFBS_None, // MOV16rm
2880 CEFBS_None, // MOV16rn
2881 CEFBS_None, // MOV16rp
2882 CEFBS_None, // MOV16rr
2883 CEFBS_None, // MOV8mc
2884 CEFBS_None, // MOV8mi
2885 CEFBS_None, // MOV8mm
2886 CEFBS_None, // MOV8mn
2887 CEFBS_None, // MOV8mr
2888 CEFBS_None, // MOV8rc
2889 CEFBS_None, // MOV8ri
2890 CEFBS_None, // MOV8rm
2891 CEFBS_None, // MOV8rn
2892 CEFBS_None, // MOV8rp
2893 CEFBS_None, // MOV8rr
2894 CEFBS_None, // MOVZX16rm8
2895 CEFBS_None, // MOVZX16rr8
2896 CEFBS_None, // POP16r
2897 CEFBS_None, // PUSH16c
2898 CEFBS_None, // PUSH16i
2899 CEFBS_None, // PUSH16r
2900 CEFBS_None, // PUSH8r
2901 CEFBS_None, // RET
2902 CEFBS_None, // RETI
2903 CEFBS_None, // RRA16m
2904 CEFBS_None, // RRA16n
2905 CEFBS_None, // RRA16p
2906 CEFBS_None, // RRA16r
2907 CEFBS_None, // RRA8m
2908 CEFBS_None, // RRA8n
2909 CEFBS_None, // RRA8p
2910 CEFBS_None, // RRA8r
2911 CEFBS_None, // RRC16m
2912 CEFBS_None, // RRC16n
2913 CEFBS_None, // RRC16p
2914 CEFBS_None, // RRC16r
2915 CEFBS_None, // RRC8m
2916 CEFBS_None, // RRC8n
2917 CEFBS_None, // RRC8p
2918 CEFBS_None, // RRC8r
2919 CEFBS_None, // Rrcl16
2920 CEFBS_None, // Rrcl8
2921 CEFBS_None, // SEXT16m
2922 CEFBS_None, // SEXT16n
2923 CEFBS_None, // SEXT16p
2924 CEFBS_None, // SEXT16r
2925 CEFBS_None, // SUB16mc
2926 CEFBS_None, // SUB16mi
2927 CEFBS_None, // SUB16mm
2928 CEFBS_None, // SUB16mn
2929 CEFBS_None, // SUB16mp
2930 CEFBS_None, // SUB16mr
2931 CEFBS_None, // SUB16rc
2932 CEFBS_None, // SUB16ri
2933 CEFBS_None, // SUB16rm
2934 CEFBS_None, // SUB16rn
2935 CEFBS_None, // SUB16rp
2936 CEFBS_None, // SUB16rr
2937 CEFBS_None, // SUB8mc
2938 CEFBS_None, // SUB8mi
2939 CEFBS_None, // SUB8mm
2940 CEFBS_None, // SUB8mn
2941 CEFBS_None, // SUB8mp
2942 CEFBS_None, // SUB8mr
2943 CEFBS_None, // SUB8rc
2944 CEFBS_None, // SUB8ri
2945 CEFBS_None, // SUB8rm
2946 CEFBS_None, // SUB8rn
2947 CEFBS_None, // SUB8rp
2948 CEFBS_None, // SUB8rr
2949 CEFBS_None, // SUBC16mc
2950 CEFBS_None, // SUBC16mi
2951 CEFBS_None, // SUBC16mm
2952 CEFBS_None, // SUBC16mn
2953 CEFBS_None, // SUBC16mp
2954 CEFBS_None, // SUBC16mr
2955 CEFBS_None, // SUBC16rc
2956 CEFBS_None, // SUBC16ri
2957 CEFBS_None, // SUBC16rm
2958 CEFBS_None, // SUBC16rn
2959 CEFBS_None, // SUBC16rp
2960 CEFBS_None, // SUBC16rr
2961 CEFBS_None, // SUBC8mc
2962 CEFBS_None, // SUBC8mi
2963 CEFBS_None, // SUBC8mm
2964 CEFBS_None, // SUBC8mn
2965 CEFBS_None, // SUBC8mp
2966 CEFBS_None, // SUBC8mr
2967 CEFBS_None, // SUBC8rc
2968 CEFBS_None, // SUBC8ri
2969 CEFBS_None, // SUBC8rm
2970 CEFBS_None, // SUBC8rn
2971 CEFBS_None, // SUBC8rp
2972 CEFBS_None, // SUBC8rr
2973 CEFBS_None, // SWPB16m
2974 CEFBS_None, // SWPB16n
2975 CEFBS_None, // SWPB16p
2976 CEFBS_None, // SWPB16r
2977 CEFBS_None, // Select16
2978 CEFBS_None, // Select8
2979 CEFBS_None, // Shl16
2980 CEFBS_None, // Shl8
2981 CEFBS_None, // Sra16
2982 CEFBS_None, // Sra8
2983 CEFBS_None, // Srl16
2984 CEFBS_None, // Srl8
2985 CEFBS_None, // XOR16mc
2986 CEFBS_None, // XOR16mi
2987 CEFBS_None, // XOR16mm
2988 CEFBS_None, // XOR16mn
2989 CEFBS_None, // XOR16mp
2990 CEFBS_None, // XOR16mr
2991 CEFBS_None, // XOR16rc
2992 CEFBS_None, // XOR16ri
2993 CEFBS_None, // XOR16rm
2994 CEFBS_None, // XOR16rn
2995 CEFBS_None, // XOR16rp
2996 CEFBS_None, // XOR16rr
2997 CEFBS_None, // XOR8mc
2998 CEFBS_None, // XOR8mi
2999 CEFBS_None, // XOR8mm
3000 CEFBS_None, // XOR8mn
3001 CEFBS_None, // XOR8mp
3002 CEFBS_None, // XOR8mr
3003 CEFBS_None, // XOR8rc
3004 CEFBS_None, // XOR8ri
3005 CEFBS_None, // XOR8rm
3006 CEFBS_None, // XOR8rn
3007 CEFBS_None, // XOR8rp
3008 CEFBS_None, // XOR8rr
3009 CEFBS_None, // ZEXT16r
3010 };
3011
3012 assert(Opcode < 666);
3013 return FeatureBitsets[RequiredFeaturesRefs[Opcode]];
3014}
3015
3016
3017} // namespace llvm::MSP430_MC
3018
3019#endif // GET_COMPUTE_FEATURES
3020
3021#ifdef GET_AVAILABLE_OPCODE_CHECKER
3022#undef GET_AVAILABLE_OPCODE_CHECKER
3023
3024namespace llvm::MSP430_MC {
3025
3026bool isOpcodeAvailable(unsigned Opcode, const FeatureBitset &Features) {
3027 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
3028 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
3029 FeatureBitset MissingFeatures =
3030 (AvailableFeatures & RequiredFeatures) ^
3031 RequiredFeatures;
3032 return !MissingFeatures.any();
3033}
3034
3035} // namespace llvm::MSP430_MC
3036
3037#endif // GET_AVAILABLE_OPCODE_CHECKER
3038
3039#ifdef ENABLE_INSTR_PREDICATE_VERIFIER
3040#undef ENABLE_INSTR_PREDICATE_VERIFIER
3041
3042#include <sstream>
3043
3044namespace llvm::MSP430_MC {
3045
3046#ifndef NDEBUG
3047static const char *SubtargetFeatureNames[] = {
3048 nullptr
3049};
3050
3051#endif // NDEBUG
3052
3053void verifyInstructionPredicates(
3054 unsigned Opcode, const FeatureBitset &Features) {
3055#ifndef NDEBUG
3056 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
3057 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
3058 FeatureBitset MissingFeatures =
3059 (AvailableFeatures & RequiredFeatures) ^
3060 RequiredFeatures;
3061 if (MissingFeatures.any()) {
3062 std::ostringstream Msg;
3063 Msg << "Attempting to emit " << &MSP430InstrNameData[MSP430InstrNameIndices[Opcode]]
3064 << " instruction but the ";
3065 for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i)
3066 if (MissingFeatures.test(i))
3067 Msg << SubtargetFeatureNames[i] << " ";
3068 Msg << "predicate(s) are not met";
3069 report_fatal_error(Msg.str().c_str());
3070 }
3071#endif // NDEBUG
3072}
3073
3074} // namespace llvm::MSP430_MC
3075
3076#endif // ENABLE_INSTR_PREDICATE_VERIFIER
3077
3078