1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Instruction Enum Values and Descriptors *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_INSTRINFO_ENUM
10#undef GET_INSTRINFO_ENUM
11
12namespace llvm::MSP430 {
13
14 enum {
15 PHI = 0, // Target.td:1314
16 INLINEASM = 1, // Target.td:1320
17 INLINEASM_BR = 2, // Target.td:1326
18 CFI_INSTRUCTION = 3, // Target.td:1335
19 EH_LABEL = 4, // Target.td:1344
20 GC_LABEL = 5, // Target.td:1353
21 ANNOTATION_LABEL = 6, // Target.td:1362
22 KILL = 7, // Target.td:1370
23 EXTRACT_SUBREG = 8, // Target.td:1377
24 INSERT_SUBREG = 9, // Target.td:1383
25 IMPLICIT_DEF = 10, // Target.td:1390
26 INIT_UNDEF = 11, // Target.td:1399
27 SUBREG_TO_REG = 12, // Target.td:1406
28 COPY_TO_REGCLASS = 13, // Target.td:1412
29 DBG_VALUE = 14, // Target.td:1419
30 DBG_VALUE_LIST = 15, // Target.td:1426
31 DBG_INSTR_REF = 16, // Target.td:1433
32 DBG_PHI = 17, // Target.td:1440
33 DBG_LABEL = 18, // Target.td:1447
34 REG_SEQUENCE = 19, // Target.td:1454
35 COPY = 20, // Target.td:1461
36 COPY_LANEMASK = 21, // Target.td:1469
37 BUNDLE = 22, // Target.td:1476
38 LIFETIME_START = 23, // Target.td:1482
39 LIFETIME_END = 24, // Target.td:1489
40 PSEUDO_PROBE = 25, // Target.td:1496
41 ARITH_FENCE = 26, // Target.td:1503
42 STACKMAP = 27, // Target.td:1512
43 FENTRY_CALL = 28, // Target.td:1647
44 PATCHPOINT = 29, // Target.td:1520
45 LOAD_STACK_GUARD = 30, // Target.td:1538
46 PREALLOCATED_SETUP = 31, // Target.td:1546
47 PREALLOCATED_ARG = 32, // Target.td:1552
48 STATEPOINT = 33, // Target.td:1529
49 LOCAL_ESCAPE = 34, // Target.td:1558
50 FAULTING_OP = 35, // Target.td:1567
51 PATCHABLE_OP = 36, // Target.td:1587
52 PATCHABLE_FUNCTION_ENTER = 37, // Target.td:1595
53 PATCHABLE_RET = 38, // Target.td:1602
54 PATCHABLE_FUNCTION_EXIT = 39, // Target.td:1611
55 PATCHABLE_TAIL_CALL = 40, // Target.td:1619
56 PATCHABLE_EVENT_CALL = 41, // Target.td:1627
57 PATCHABLE_TYPED_EVENT_CALL = 42, // Target.td:1637
58 ICALL_BRANCH_FUNNEL = 43, // Target.td:1657
59 FAKE_USE = 44, // Target.td:1577
60 MEMBARRIER = 45, // Target.td:1663
61 JUMP_TABLE_DEBUG_INFO = 46, // Target.td:1671
62 RELOC_NONE = 47, // Target.td:1679
63 CONVERGENCECTRL_ENTRY = 48, // Target.td:1691
64 CONVERGENCECTRL_ANCHOR = 49, // Target.td:1687
65 CONVERGENCECTRL_LOOP = 50, // Target.td:1695
66 CONVERGENCECTRL_GLUE = 51, // Target.td:1699
67 G_ASSERT_SEXT = 52, // GenericOpcodes.td:1945
68 G_ASSERT_ZEXT = 53, // GenericOpcodes.td:1937
69 G_ASSERT_ALIGN = 54, // GenericOpcodes.td:1952
70 G_ADD = 55, // GenericOpcodes.td:308
71 G_SUB = 56, // GenericOpcodes.td:316
72 G_MUL = 57, // GenericOpcodes.td:324
73 G_SDIV = 58, // GenericOpcodes.td:332
74 G_UDIV = 59, // GenericOpcodes.td:340
75 G_SREM = 60, // GenericOpcodes.td:348
76 G_UREM = 61, // GenericOpcodes.td:356
77 G_SDIVREM = 62, // GenericOpcodes.td:364
78 G_UDIVREM = 63, // GenericOpcodes.td:372
79 G_AND = 64, // GenericOpcodes.td:380
80 G_OR = 65, // GenericOpcodes.td:388
81 G_XOR = 66, // GenericOpcodes.td:396
82 G_ABDS = 67, // GenericOpcodes.td:425
83 G_ABDU = 68, // GenericOpcodes.td:433
84 G_UAVGFLOOR = 69, // GenericOpcodes.td:441
85 G_UAVGCEIL = 70, // GenericOpcodes.td:448
86 G_SAVGFLOOR = 71, // GenericOpcodes.td:455
87 G_SAVGCEIL = 72, // GenericOpcodes.td:462
88 G_IMPLICIT_DEF = 73, // GenericOpcodes.td:111
89 G_PHI = 74, // GenericOpcodes.td:118
90 G_FRAME_INDEX = 75, // GenericOpcodes.td:125
91 G_GLOBAL_VALUE = 76, // GenericOpcodes.td:131
92 G_PTRAUTH_GLOBAL_VALUE = 77, // GenericOpcodes.td:137
93 G_CONSTANT_POOL = 78, // GenericOpcodes.td:143
94 G_EXTRACT = 79, // GenericOpcodes.td:1530
95 G_UNMERGE_VALUES = 80, // GenericOpcodes.td:1543
96 G_INSERT = 81, // GenericOpcodes.td:1552
97 G_MERGE_VALUES = 82, // GenericOpcodes.td:1562
98 G_BUILD_VECTOR = 83, // GenericOpcodes.td:1582
99 G_BUILD_VECTOR_TRUNC = 84, // GenericOpcodes.td:1592
100 G_CONCAT_VECTORS = 85, // GenericOpcodes.td:1599
101 G_PTRTOINT = 86, // GenericOpcodes.td:155
102 G_INTTOPTR = 87, // GenericOpcodes.td:149
103 G_BITCAST = 88, // GenericOpcodes.td:161
104 G_FREEZE = 89, // GenericOpcodes.td:284
105 G_CONSTANT_FOLD_BARRIER = 90, // GenericOpcodes.td:1959
106 G_INTRINSIC_FPTRUNC_ROUND = 91, // GenericOpcodes.td:1288
107 G_INTRINSIC_TRUNC = 92, // GenericOpcodes.td:1294
108 G_INTRINSIC_ROUND = 93, // GenericOpcodes.td:1300
109 G_INTRINSIC_LRINT = 94, // GenericOpcodes.td:1306
110 G_INTRINSIC_LLRINT = 95, // GenericOpcodes.td:1312
111 G_INTRINSIC_ROUNDEVEN = 96, // GenericOpcodes.td:1318
112 G_READCYCLECOUNTER = 97, // GenericOpcodes.td:1324
113 G_READSTEADYCOUNTER = 98, // GenericOpcodes.td:1330
114 G_LOAD = 99, // GenericOpcodes.td:1357
115 G_SEXTLOAD = 100, // GenericOpcodes.td:1366
116 G_ZEXTLOAD = 101, // GenericOpcodes.td:1374
117 G_FPEXTLOAD = 102, // GenericOpcodes.td:1383
118 G_INDEXED_LOAD = 103, // GenericOpcodes.td:1393
119 G_INDEXED_SEXTLOAD = 104, // GenericOpcodes.td:1402
120 G_INDEXED_ZEXTLOAD = 105, // GenericOpcodes.td:1410
121 G_STORE = 106, // GenericOpcodes.td:1418
122 G_FPTRUNCSTORE = 107, // GenericOpcodes.td:1428
123 G_INDEXED_STORE = 108, // GenericOpcodes.td:1436
124 G_ATOMIC_CMPXCHG_WITH_SUCCESS = 109, // GenericOpcodes.td:1447
125 G_ATOMIC_CMPXCHG = 110, // GenericOpcodes.td:1458
126 G_ATOMICRMW_XCHG = 111, // GenericOpcodes.td:1478
127 G_ATOMICRMW_ADD = 112, // GenericOpcodes.td:1479
128 G_ATOMICRMW_SUB = 113, // GenericOpcodes.td:1480
129 G_ATOMICRMW_AND = 114, // GenericOpcodes.td:1481
130 G_ATOMICRMW_NAND = 115, // GenericOpcodes.td:1482
131 G_ATOMICRMW_OR = 116, // GenericOpcodes.td:1483
132 G_ATOMICRMW_XOR = 117, // GenericOpcodes.td:1484
133 G_ATOMICRMW_MAX = 118, // GenericOpcodes.td:1485
134 G_ATOMICRMW_MIN = 119, // GenericOpcodes.td:1486
135 G_ATOMICRMW_UMAX = 120, // GenericOpcodes.td:1487
136 G_ATOMICRMW_UMIN = 121, // GenericOpcodes.td:1488
137 G_ATOMICRMW_FADD = 122, // GenericOpcodes.td:1499
138 G_ATOMICRMW_FSUB = 123, // GenericOpcodes.td:1500
139 G_ATOMICRMW_FMAX = 124, // GenericOpcodes.td:1501
140 G_ATOMICRMW_FMIN = 125, // GenericOpcodes.td:1502
141 G_ATOMICRMW_FMAXIMUM = 126, // GenericOpcodes.td:1503
142 G_ATOMICRMW_FMINIMUM = 127, // GenericOpcodes.td:1504
143 G_ATOMICRMW_FMAXIMUMNUM = 128, // GenericOpcodes.td:1505
144 G_ATOMICRMW_FMINIMUMNUM = 129, // GenericOpcodes.td:1506
145 G_ATOMICRMW_UINC_WRAP = 130, // GenericOpcodes.td:1489
146 G_ATOMICRMW_UDEC_WRAP = 131, // GenericOpcodes.td:1490
147 G_ATOMICRMW_USUB_COND = 132, // GenericOpcodes.td:1491
148 G_ATOMICRMW_USUB_SAT = 133, // GenericOpcodes.td:1492
149 G_FENCE = 134, // GenericOpcodes.td:1508
150 G_PREFETCH = 135, // GenericOpcodes.td:1515
151 G_BRCOND = 136, // GenericOpcodes.td:1655
152 G_BRINDIRECT = 137, // GenericOpcodes.td:1664
153 G_INVOKE_REGION_START = 138, // GenericOpcodes.td:1687
154 G_INTRINSIC = 139, // GenericOpcodes.td:1607
155 G_INTRINSIC_W_SIDE_EFFECTS = 140, // GenericOpcodes.td:1614
156 G_INTRINSIC_CONVERGENT = 141, // GenericOpcodes.td:1623
157 G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 142, // GenericOpcodes.td:1631
158 G_ANYEXT = 143, // GenericOpcodes.td:44
159 G_TRUNC = 144, // GenericOpcodes.td:83
160 G_TRUNC_SSAT_S = 145, // GenericOpcodes.td:91
161 G_TRUNC_SSAT_U = 146, // GenericOpcodes.td:98
162 G_TRUNC_USAT_U = 147, // GenericOpcodes.td:105
163 G_CONSTANT = 148, // GenericOpcodes.td:169
164 G_FCONSTANT = 149, // GenericOpcodes.td:177
165 G_VASTART = 150, // GenericOpcodes.td:184
166 G_VAARG = 151, // GenericOpcodes.td:191
167 G_SEXT = 152, // GenericOpcodes.td:52
168 G_SEXT_INREG = 153, // GenericOpcodes.td:66
169 G_ZEXT = 154, // GenericOpcodes.td:74
170 G_SHL = 155, // GenericOpcodes.td:404
171 G_LSHR = 156, // GenericOpcodes.td:411
172 G_ASHR = 157, // GenericOpcodes.td:418
173 G_FSHL = 158, // GenericOpcodes.td:470
174 G_FSHR = 159, // GenericOpcodes.td:478
175 G_ROTR = 160, // GenericOpcodes.td:485
176 G_ROTL = 161, // GenericOpcodes.td:492
177 G_ICMP = 162, // GenericOpcodes.td:499
178 G_FCMP = 163, // GenericOpcodes.td:506
179 G_SCMP = 164, // GenericOpcodes.td:513
180 G_UCMP = 165, // GenericOpcodes.td:520
181 G_SELECT = 166, // GenericOpcodes.td:527
182 G_UADDO = 167, // GenericOpcodes.td:609
183 G_UADDE = 168, // GenericOpcodes.td:617
184 G_USUBO = 169, // GenericOpcodes.td:639
185 G_USUBE = 170, // GenericOpcodes.td:645
186 G_SADDO = 171, // GenericOpcodes.td:624
187 G_SADDE = 172, // GenericOpcodes.td:632
188 G_SSUBO = 173, // GenericOpcodes.td:652
189 G_SSUBE = 174, // GenericOpcodes.td:659
190 G_UMULO = 175, // GenericOpcodes.td:666
191 G_SMULO = 176, // GenericOpcodes.td:674
192 G_UMULH = 177, // GenericOpcodes.td:683
193 G_SMULH = 178, // GenericOpcodes.td:692
194 G_UADDSAT = 179, // GenericOpcodes.td:704
195 G_SADDSAT = 180, // GenericOpcodes.td:712
196 G_USUBSAT = 181, // GenericOpcodes.td:720
197 G_SSUBSAT = 182, // GenericOpcodes.td:728
198 G_USHLSAT = 183, // GenericOpcodes.td:736
199 G_SSHLSAT = 184, // GenericOpcodes.td:744
200 G_SMULFIX = 185, // GenericOpcodes.td:756
201 G_UMULFIX = 186, // GenericOpcodes.td:763
202 G_SMULFIXSAT = 187, // GenericOpcodes.td:773
203 G_UMULFIXSAT = 188, // GenericOpcodes.td:780
204 G_SDIVFIX = 189, // GenericOpcodes.td:791
205 G_UDIVFIX = 190, // GenericOpcodes.td:798
206 G_SDIVFIXSAT = 191, // GenericOpcodes.td:808
207 G_UDIVFIXSAT = 192, // GenericOpcodes.td:815
208 G_FADD = 193, // GenericOpcodes.td:988
209 G_FSUB = 194, // GenericOpcodes.td:996
210 G_FMUL = 195, // GenericOpcodes.td:1004
211 G_FMA = 196, // GenericOpcodes.td:1013
212 G_FMAD = 197, // GenericOpcodes.td:1022
213 G_FDIV = 198, // GenericOpcodes.td:1030
214 G_FREM = 199, // GenericOpcodes.td:1037
215 G_FMODF = 200, // GenericOpcodes.td:1044
216 G_FPOW = 201, // GenericOpcodes.td:1051
217 G_FPOWI = 202, // GenericOpcodes.td:1058
218 G_FEXP = 203, // GenericOpcodes.td:1065
219 G_FEXP2 = 204, // GenericOpcodes.td:1072
220 G_FEXP10 = 205, // GenericOpcodes.td:1079
221 G_FLOG = 206, // GenericOpcodes.td:1086
222 G_FLOG2 = 207, // GenericOpcodes.td:1093
223 G_FLOG10 = 208, // GenericOpcodes.td:1100
224 G_FLDEXP = 209, // GenericOpcodes.td:1107
225 G_FFREXP = 210, // GenericOpcodes.td:1114
226 G_FNEG = 211, // GenericOpcodes.td:826
227 G_FPEXT = 212, // GenericOpcodes.td:832
228 G_FPTRUNC = 213, // GenericOpcodes.td:838
229 G_FPTOSI = 214, // GenericOpcodes.td:844
230 G_FPTOUI = 215, // GenericOpcodes.td:850
231 G_SITOFP = 216, // GenericOpcodes.td:856
232 G_UITOFP = 217, // GenericOpcodes.td:862
233 G_FPTOSI_SAT = 218, // GenericOpcodes.td:868
234 G_FPTOUI_SAT = 219, // GenericOpcodes.td:874
235 G_FABS = 220, // GenericOpcodes.td:880
236 G_FCOPYSIGN = 221, // GenericOpcodes.td:886
237 G_IS_FPCLASS = 222, // GenericOpcodes.td:899
238 G_FCANONICALIZE = 223, // GenericOpcodes.td:892
239 G_FMINNUM = 224, // GenericOpcodes.td:912
240 G_FMAXNUM = 225, // GenericOpcodes.td:919
241 G_FMINNUM_IEEE = 226, // GenericOpcodes.td:937
242 G_FMAXNUM_IEEE = 227, // GenericOpcodes.td:944
243 G_FMINIMUM = 228, // GenericOpcodes.td:954
244 G_FMAXIMUM = 229, // GenericOpcodes.td:961
245 G_FMINIMUMNUM = 230, // GenericOpcodes.td:969
246 G_FMAXIMUMNUM = 231, // GenericOpcodes.td:976
247 G_GET_FPENV = 232, // GenericOpcodes.td:1244
248 G_SET_FPENV = 233, // GenericOpcodes.td:1251
249 G_RESET_FPENV = 234, // GenericOpcodes.td:1258
250 G_GET_FPMODE = 235, // GenericOpcodes.td:1265
251 G_SET_FPMODE = 236, // GenericOpcodes.td:1272
252 G_RESET_FPMODE = 237, // GenericOpcodes.td:1279
253 G_GET_ROUNDING = 238, // GenericOpcodes.td:1336
254 G_SET_ROUNDING = 239, // GenericOpcodes.td:1342
255 G_PTR_ADD = 240, // GenericOpcodes.td:534
256 G_PTRMASK = 241, // GenericOpcodes.td:542
257 G_SMIN = 242, // GenericOpcodes.td:549
258 G_SMAX = 243, // GenericOpcodes.td:557
259 G_UMIN = 244, // GenericOpcodes.td:565
260 G_UMAX = 245, // GenericOpcodes.td:573
261 G_ABS = 246, // GenericOpcodes.td:581
262 G_LROUND = 247, // GenericOpcodes.td:291
263 G_LLROUND = 248, // GenericOpcodes.td:297
264 G_BR = 249, // GenericOpcodes.td:1645
265 G_BRJT = 250, // GenericOpcodes.td:1675
266 G_VSCALE = 251, // GenericOpcodes.td:1573
267 G_INSERT_SUBVECTOR = 252, // GenericOpcodes.td:1719
268 G_EXTRACT_SUBVECTOR = 253, // GenericOpcodes.td:1727
269 G_INSERT_VECTOR_ELT = 254, // GenericOpcodes.td:1735
270 G_EXTRACT_VECTOR_ELT = 255, // GenericOpcodes.td:1743
271 G_SHUFFLE_VECTOR = 256, // GenericOpcodes.td:1754
272 G_SPLAT_VECTOR = 257, // GenericOpcodes.td:1762
273 G_STEP_VECTOR = 258, // GenericOpcodes.td:1770
274 G_VECTOR_COMPRESS = 259, // GenericOpcodes.td:1777
275 G_CTTZ = 260, // GenericOpcodes.td:211
276 G_CTTZ_ZERO_POISON = 261, // GenericOpcodes.td:217
277 G_CTLZ = 262, // GenericOpcodes.td:199
278 G_CTLZ_ZERO_POISON = 263, // GenericOpcodes.td:205
279 G_CTLS = 264, // GenericOpcodes.td:223
280 G_CTPOP = 265, // GenericOpcodes.td:229
281 G_BSWAP = 266, // GenericOpcodes.td:235
282 G_BITREVERSE = 267, // GenericOpcodes.td:242
283 G_CLMUL = 268, // GenericOpcodes.td:588
284 G_CLMULH = 269, // GenericOpcodes.td:596
285 G_FCEIL = 270, // GenericOpcodes.td:1121
286 G_FCOS = 271, // GenericOpcodes.td:1128
287 G_FSIN = 272, // GenericOpcodes.td:1135
288 G_FSINCOS = 273, // GenericOpcodes.td:1142
289 G_FTAN = 274, // GenericOpcodes.td:1149
290 G_FACOS = 275, // GenericOpcodes.td:1156
291 G_FASIN = 276, // GenericOpcodes.td:1163
292 G_FATAN = 277, // GenericOpcodes.td:1170
293 G_FATAN2 = 278, // GenericOpcodes.td:1177
294 G_FCOSH = 279, // GenericOpcodes.td:1184
295 G_FSINH = 280, // GenericOpcodes.td:1191
296 G_FTANH = 281, // GenericOpcodes.td:1198
297 G_FSQRT = 282, // GenericOpcodes.td:1208
298 G_FFLOOR = 283, // GenericOpcodes.td:1215
299 G_FRINT = 284, // GenericOpcodes.td:1222
300 G_FNEARBYINT = 285, // GenericOpcodes.td:1229
301 G_ADDRSPACE_CAST = 286, // GenericOpcodes.td:248
302 G_BLOCK_ADDR = 287, // GenericOpcodes.td:254
303 G_JUMP_TABLE = 288, // GenericOpcodes.td:260
304 G_DYN_STACKALLOC = 289, // GenericOpcodes.td:266
305 G_STACKSAVE = 290, // GenericOpcodes.td:272
306 G_STACKRESTORE = 291, // GenericOpcodes.td:278
307 G_STRICT_FADD = 292, // GenericOpcodes.td:1829
308 G_STRICT_FSUB = 293, // GenericOpcodes.td:1830
309 G_STRICT_FMUL = 294, // GenericOpcodes.td:1831
310 G_STRICT_FDIV = 295, // GenericOpcodes.td:1832
311 G_STRICT_FREM = 296, // GenericOpcodes.td:1833
312 G_STRICT_FMA = 297, // GenericOpcodes.td:1834
313 G_STRICT_FSQRT = 298, // GenericOpcodes.td:1835
314 G_STRICT_FLDEXP = 299, // GenericOpcodes.td:1836
315 G_STRICT_FCMP = 300, // GenericOpcodes.td:1837
316 G_STRICT_FCMPS = 301, // GenericOpcodes.td:1838
317 G_READ_REGISTER = 302, // GenericOpcodes.td:1694
318 G_WRITE_REGISTER = 303, // GenericOpcodes.td:1704
319 G_MEMCPY = 304, // GenericOpcodes.td:1844
320 G_MEMCPY_INLINE = 305, // GenericOpcodes.td:1852
321 G_MEMMOVE = 306, // GenericOpcodes.td:1860
322 G_MEMSET = 307, // GenericOpcodes.td:1868
323 G_BZERO = 308, // GenericOpcodes.td:1875
324 G_MEMSET_INLINE = 309, // GenericOpcodes.td:1882
325 G_TRAP = 310, // GenericOpcodes.td:1892
326 G_DEBUGTRAP = 311, // GenericOpcodes.td:1899
327 G_UBSANTRAP = 312, // GenericOpcodes.td:1905
328 G_VECREDUCE_SEQ_FADD = 313, // GenericOpcodes.td:1793
329 G_VECREDUCE_SEQ_FMUL = 314, // GenericOpcodes.td:1799
330 G_VECREDUCE_FADD = 315, // GenericOpcodes.td:1805
331 G_VECREDUCE_FMUL = 316, // GenericOpcodes.td:1806
332 G_VECREDUCE_FMAX = 317, // GenericOpcodes.td:1808
333 G_VECREDUCE_FMIN = 318, // GenericOpcodes.td:1809
334 G_VECREDUCE_FMAXIMUM = 319, // GenericOpcodes.td:1810
335 G_VECREDUCE_FMINIMUM = 320, // GenericOpcodes.td:1811
336 G_VECREDUCE_FMAXIMUMNUM = 321, // GenericOpcodes.td:1812
337 G_VECREDUCE_FMINIMUMNUM = 322, // GenericOpcodes.td:1813
338 G_VECREDUCE_ADD = 323, // GenericOpcodes.td:1815
339 G_VECREDUCE_MUL = 324, // GenericOpcodes.td:1816
340 G_VECREDUCE_AND = 325, // GenericOpcodes.td:1817
341 G_VECREDUCE_OR = 326, // GenericOpcodes.td:1818
342 G_VECREDUCE_XOR = 327, // GenericOpcodes.td:1819
343 G_VECREDUCE_SMAX = 328, // GenericOpcodes.td:1820
344 G_VECREDUCE_SMIN = 329, // GenericOpcodes.td:1821
345 G_VECREDUCE_UMAX = 330, // GenericOpcodes.td:1822
346 G_VECREDUCE_UMIN = 331, // GenericOpcodes.td:1823
347 G_SBFX = 332, // GenericOpcodes.td:1917
348 G_UBFX = 333, // GenericOpcodes.td:1925
349 ADD16mc = 334, // MSP430InstrInfo.td:499
350 ADD16mi = 335, // MSP430InstrInfo.td:505
351 ADD16mm = 336, // MSP430InstrInfo.td:512
352 ADD16mn = 337, // MSP430InstrInfo.td:518
353 ADD16mp = 338, // MSP430InstrInfo.td:522
354 ADD16mr = 339, // MSP430InstrInfo.td:493
355 ADD16rc = 340, // MSP430InstrInfo.td:480
356 ADD16ri = 341, // MSP430InstrInfo.td:486
357 ADD16rm = 342, // MSP430InstrInfo.td:462
358 ADD16rn = 343, // MSP430InstrInfo.td:467
359 ADD16rp = 344, // MSP430InstrInfo.td:474
360 ADD16rr = 345, // MSP430InstrInfo.td:455
361 ADD8mc = 346, // MSP430InstrInfo.td:496
362 ADD8mi = 347, // MSP430InstrInfo.td:502
363 ADD8mm = 348, // MSP430InstrInfo.td:508
364 ADD8mn = 349, // MSP430InstrInfo.td:516
365 ADD8mp = 350, // MSP430InstrInfo.td:520
366 ADD8mr = 351, // MSP430InstrInfo.td:490
367 ADD8rc = 352, // MSP430InstrInfo.td:477
368 ADD8ri = 353, // MSP430InstrInfo.td:483
369 ADD8rm = 354, // MSP430InstrInfo.td:459
370 ADD8rn = 355, // MSP430InstrInfo.td:465
371 ADD8rp = 356, // MSP430InstrInfo.td:472
372 ADD8rr = 357, // MSP430InstrInfo.td:452
373 ADDC16mc = 358, // MSP430InstrInfo.td:499
374 ADDC16mi = 359, // MSP430InstrInfo.td:505
375 ADDC16mm = 360, // MSP430InstrInfo.td:512
376 ADDC16mn = 361, // MSP430InstrInfo.td:518
377 ADDC16mp = 362, // MSP430InstrInfo.td:522
378 ADDC16mr = 363, // MSP430InstrInfo.td:493
379 ADDC16rc = 364, // MSP430InstrInfo.td:480
380 ADDC16ri = 365, // MSP430InstrInfo.td:486
381 ADDC16rm = 366, // MSP430InstrInfo.td:462
382 ADDC16rn = 367, // MSP430InstrInfo.td:467
383 ADDC16rp = 368, // MSP430InstrInfo.td:474
384 ADDC16rr = 369, // MSP430InstrInfo.td:455
385 ADDC8mc = 370, // MSP430InstrInfo.td:496
386 ADDC8mi = 371, // MSP430InstrInfo.td:502
387 ADDC8mm = 372, // MSP430InstrInfo.td:508
388 ADDC8mn = 373, // MSP430InstrInfo.td:516
389 ADDC8mp = 374, // MSP430InstrInfo.td:520
390 ADDC8mr = 375, // MSP430InstrInfo.td:490
391 ADDC8rc = 376, // MSP430InstrInfo.td:477
392 ADDC8ri = 377, // MSP430InstrInfo.td:483
393 ADDC8rm = 378, // MSP430InstrInfo.td:459
394 ADDC8rn = 379, // MSP430InstrInfo.td:465
395 ADDC8rp = 380, // MSP430InstrInfo.td:472
396 ADDC8rr = 381, // MSP430InstrInfo.td:452
397 ADDframe = 382, // MSP430InstrInfo.td:183
398 ADJCALLSTACKDOWN = 383, // MSP430InstrInfo.td:174
399 ADJCALLSTACKUP = 384, // MSP430InstrInfo.td:177
400 AND16mc = 385, // MSP430InstrInfo.td:499
401 AND16mi = 386, // MSP430InstrInfo.td:505
402 AND16mm = 387, // MSP430InstrInfo.td:512
403 AND16mn = 388, // MSP430InstrInfo.td:518
404 AND16mp = 389, // MSP430InstrInfo.td:522
405 AND16mr = 390, // MSP430InstrInfo.td:493
406 AND16rc = 391, // MSP430InstrInfo.td:480
407 AND16ri = 392, // MSP430InstrInfo.td:486
408 AND16rm = 393, // MSP430InstrInfo.td:462
409 AND16rn = 394, // MSP430InstrInfo.td:467
410 AND16rp = 395, // MSP430InstrInfo.td:474
411 AND16rr = 396, // MSP430InstrInfo.td:455
412 AND8mc = 397, // MSP430InstrInfo.td:496
413 AND8mi = 398, // MSP430InstrInfo.td:502
414 AND8mm = 399, // MSP430InstrInfo.td:508
415 AND8mn = 400, // MSP430InstrInfo.td:516
416 AND8mp = 401, // MSP430InstrInfo.td:520
417 AND8mr = 402, // MSP430InstrInfo.td:490
418 AND8rc = 403, // MSP430InstrInfo.td:477
419 AND8ri = 404, // MSP430InstrInfo.td:483
420 AND8rm = 405, // MSP430InstrInfo.td:459
421 AND8rn = 406, // MSP430InstrInfo.td:465
422 AND8rp = 407, // MSP430InstrInfo.td:472
423 AND8rr = 408, // MSP430InstrInfo.td:452
424 BIC16mc = 409, // MSP430InstrInfo.td:499
425 BIC16mi = 410, // MSP430InstrInfo.td:505
426 BIC16mm = 411, // MSP430InstrInfo.td:512
427 BIC16mn = 412, // MSP430InstrInfo.td:518
428 BIC16mp = 413, // MSP430InstrInfo.td:522
429 BIC16mr = 414, // MSP430InstrInfo.td:493
430 BIC16rc = 415, // MSP430InstrInfo.td:480
431 BIC16ri = 416, // MSP430InstrInfo.td:486
432 BIC16rm = 417, // MSP430InstrInfo.td:462
433 BIC16rn = 418, // MSP430InstrInfo.td:467
434 BIC16rp = 419, // MSP430InstrInfo.td:474
435 BIC16rr = 420, // MSP430InstrInfo.td:455
436 BIC8mc = 421, // MSP430InstrInfo.td:496
437 BIC8mi = 422, // MSP430InstrInfo.td:502
438 BIC8mm = 423, // MSP430InstrInfo.td:508
439 BIC8mn = 424, // MSP430InstrInfo.td:516
440 BIC8mp = 425, // MSP430InstrInfo.td:520
441 BIC8mr = 426, // MSP430InstrInfo.td:490
442 BIC8rc = 427, // MSP430InstrInfo.td:477
443 BIC8ri = 428, // MSP430InstrInfo.td:483
444 BIC8rm = 429, // MSP430InstrInfo.td:459
445 BIC8rn = 430, // MSP430InstrInfo.td:465
446 BIC8rp = 431, // MSP430InstrInfo.td:472
447 BIC8rr = 432, // MSP430InstrInfo.td:452
448 BIS16mc = 433, // MSP430InstrInfo.td:499
449 BIS16mi = 434, // MSP430InstrInfo.td:505
450 BIS16mm = 435, // MSP430InstrInfo.td:512
451 BIS16mn = 436, // MSP430InstrInfo.td:518
452 BIS16mp = 437, // MSP430InstrInfo.td:522
453 BIS16mr = 438, // MSP430InstrInfo.td:493
454 BIS16rc = 439, // MSP430InstrInfo.td:480
455 BIS16ri = 440, // MSP430InstrInfo.td:486
456 BIS16rm = 441, // MSP430InstrInfo.td:462
457 BIS16rn = 442, // MSP430InstrInfo.td:467
458 BIS16rp = 443, // MSP430InstrInfo.td:474
459 BIS16rr = 444, // MSP430InstrInfo.td:455
460 BIS8mc = 445, // MSP430InstrInfo.td:496
461 BIS8mi = 446, // MSP430InstrInfo.td:502
462 BIS8mm = 447, // MSP430InstrInfo.td:508
463 BIS8mn = 448, // MSP430InstrInfo.td:516
464 BIS8mp = 449, // MSP430InstrInfo.td:520
465 BIS8mr = 450, // MSP430InstrInfo.td:490
466 BIS8rc = 451, // MSP430InstrInfo.td:477
467 BIS8ri = 452, // MSP430InstrInfo.td:483
468 BIS8rm = 453, // MSP430InstrInfo.td:459
469 BIS8rn = 454, // MSP430InstrInfo.td:465
470 BIS8rp = 455, // MSP430InstrInfo.td:472
471 BIS8rr = 456, // MSP430InstrInfo.td:452
472 BIT16mc = 457, // MSP430InstrInfo.td:861
473 BIT16mi = 458, // MSP430InstrInfo.td:870
474 BIT16mm = 459, // MSP430InstrInfo.td:881
475 BIT16mn = 460, // MSP430InstrInfo.td:889
476 BIT16mp = 461, // MSP430InstrInfo.td:894
477 BIT16mr = 462, // MSP430InstrInfo.td:852
478 BIT16rc = 463, // MSP430InstrInfo.td:815
479 BIT16ri = 464, // MSP430InstrInfo.td:824
480 BIT16rm = 465, // MSP430InstrInfo.td:833
481 BIT16rn = 466, // MSP430InstrInfo.td:840
482 BIT16rp = 467, // MSP430InstrInfo.td:845
483 BIT16rr = 468, // MSP430InstrInfo.td:806
484 BIT8mc = 469, // MSP430InstrInfo.td:857
485 BIT8mi = 470, // MSP430InstrInfo.td:866
486 BIT8mm = 471, // MSP430InstrInfo.td:875
487 BIT8mn = 472, // MSP430InstrInfo.td:887
488 BIT8mp = 473, // MSP430InstrInfo.td:892
489 BIT8mr = 474, // MSP430InstrInfo.td:848
490 BIT8rc = 475, // MSP430InstrInfo.td:811
491 BIT8ri = 476, // MSP430InstrInfo.td:820
492 BIT8rm = 477, // MSP430InstrInfo.td:829
493 BIT8rn = 478, // MSP430InstrInfo.td:838
494 BIT8rp = 479, // MSP430InstrInfo.td:843
495 BIT8rr = 480, // MSP430InstrInfo.td:802
496 Bi = 481, // MSP430InstrInfo.td:255
497 Bm = 482, // MSP430InstrInfo.td:261
498 Br = 483, // MSP430InstrInfo.td:258
499 CALLi = 484, // MSP430InstrInfo.td:284
500 CALLm = 485, // MSP430InstrInfo.td:290
501 CALLn = 486, // MSP430InstrInfo.td:293
502 CALLp = 487, // MSP430InstrInfo.td:294
503 CALLr = 488, // MSP430InstrInfo.td:287
504 CMP16mc = 489, // MSP430InstrInfo.td:738
505 CMP16mi = 490, // MSP430InstrInfo.td:748
506 CMP16mm = 491, // MSP430InstrInfo.td:785
507 CMP16mn = 492, // MSP430InstrInfo.td:791
508 CMP16mp = 493, // MSP430InstrInfo.td:796
509 CMP16mr = 494, // MSP430InstrInfo.td:777
510 CMP16rc = 495, // MSP430InstrInfo.td:720
511 CMP16ri = 496, // MSP430InstrInfo.td:729
512 CMP16rm = 497, // MSP430InstrInfo.td:758
513 CMP16rn = 498, // MSP430InstrInfo.td:765
514 CMP16rp = 499, // MSP430InstrInfo.td:770
515 CMP16rr = 500, // MSP430InstrInfo.td:711
516 CMP8mc = 501, // MSP430InstrInfo.td:734
517 CMP8mi = 502, // MSP430InstrInfo.td:743
518 CMP8mm = 503, // MSP430InstrInfo.td:781
519 CMP8mn = 504, // MSP430InstrInfo.td:789
520 CMP8mp = 505, // MSP430InstrInfo.td:794
521 CMP8mr = 506, // MSP430InstrInfo.td:773
522 CMP8rc = 507, // MSP430InstrInfo.td:716
523 CMP8ri = 508, // MSP430InstrInfo.td:725
524 CMP8rm = 509, // MSP430InstrInfo.td:754
525 CMP8rn = 510, // MSP430InstrInfo.td:763
526 CMP8rp = 511, // MSP430InstrInfo.td:768
527 CMP8rr = 512, // MSP430InstrInfo.td:707
528 DADD16mc = 513, // MSP430InstrInfo.td:499
529 DADD16mi = 514, // MSP430InstrInfo.td:505
530 DADD16mm = 515, // MSP430InstrInfo.td:512
531 DADD16mn = 516, // MSP430InstrInfo.td:518
532 DADD16mp = 517, // MSP430InstrInfo.td:522
533 DADD16mr = 518, // MSP430InstrInfo.td:493
534 DADD16rc = 519, // MSP430InstrInfo.td:480
535 DADD16ri = 520, // MSP430InstrInfo.td:486
536 DADD16rm = 521, // MSP430InstrInfo.td:462
537 DADD16rn = 522, // MSP430InstrInfo.td:467
538 DADD16rp = 523, // MSP430InstrInfo.td:474
539 DADD16rr = 524, // MSP430InstrInfo.td:455
540 DADD8mc = 525, // MSP430InstrInfo.td:496
541 DADD8mi = 526, // MSP430InstrInfo.td:502
542 DADD8mm = 527, // MSP430InstrInfo.td:508
543 DADD8mn = 528, // MSP430InstrInfo.td:516
544 DADD8mp = 529, // MSP430InstrInfo.td:520
545 DADD8mr = 530, // MSP430InstrInfo.td:490
546 DADD8rc = 531, // MSP430InstrInfo.td:477
547 DADD8ri = 532, // MSP430InstrInfo.td:483
548 DADD8rm = 533, // MSP430InstrInfo.td:459
549 DADD8rn = 534, // MSP430InstrInfo.td:465
550 DADD8rp = 535, // MSP430InstrInfo.td:472
551 DADD8rr = 536, // MSP430InstrInfo.td:452
552 JCC = 537, // MSP430InstrInfo.td:269
553 JMP = 538, // MSP430InstrInfo.td:248
554 MOV16mc = 539, // MSP430InstrInfo.td:407
555 MOV16mi = 540, // MSP430InstrInfo.td:416
556 MOV16mm = 541, // MSP430InstrInfo.td:434
557 MOV16mn = 542, // MSP430InstrInfo.td:441
558 MOV16mr = 543, // MSP430InstrInfo.td:425
559 MOV16rc = 544, // MSP430InstrInfo.td:335
560 MOV16ri = 545, // MSP430InstrInfo.td:343
561 MOV16rm = 546, // MSP430InstrInfo.td:354
562 MOV16rn = 547, // MSP430InstrInfo.td:362
563 MOV16rp = 548, // MSP430InstrInfo.td:383
564 MOV16rr = 549, // MSP430InstrInfo.td:324
565 MOV8mc = 550, // MSP430InstrInfo.td:403
566 MOV8mi = 551, // MSP430InstrInfo.td:412
567 MOV8mm = 552, // MSP430InstrInfo.td:430
568 MOV8mn = 553, // MSP430InstrInfo.td:439
569 MOV8mr = 554, // MSP430InstrInfo.td:421
570 MOV8rc = 555, // MSP430InstrInfo.td:331
571 MOV8ri = 556, // MSP430InstrInfo.td:339
572 MOV8rm = 557, // MSP430InstrInfo.td:350
573 MOV8rn = 558, // MSP430InstrInfo.td:358
574 MOV8rp = 559, // MSP430InstrInfo.td:380
575 MOV8rr = 560, // MSP430InstrInfo.td:320
576 MOVZX16rm8 = 561, // MSP430InstrInfo.td:373
577 MOVZX16rr8 = 562, // MSP430InstrInfo.td:369
578 POP16r = 563, // MSP430InstrInfo.td:302
579 PUSH16c = 564, // MSP430InstrInfo.td:311
580 PUSH16i = 565, // MSP430InstrInfo.td:312
581 PUSH16r = 566, // MSP430InstrInfo.td:310
582 PUSH8r = 567, // MSP430InstrInfo.td:309
583 RET = 568, // MSP430InstrInfo.td:229
584 RETI = 569, // MSP430InstrInfo.td:235
585 RRA16m = 570, // MSP430InstrInfo.td:661
586 RRA16n = 571, // MSP430InstrInfo.td:667
587 RRA16p = 572, // MSP430InstrInfo.td:669
588 RRA16r = 573, // MSP430InstrInfo.td:619
589 RRA8m = 574, // MSP430InstrInfo.td:657
590 RRA8n = 575, // MSP430InstrInfo.td:666
591 RRA8p = 576, // MSP430InstrInfo.td:668
592 RRA8r = 577, // MSP430InstrInfo.td:615
593 RRC16m = 578, // MSP430InstrInfo.td:676
594 RRC16n = 579, // MSP430InstrInfo.td:682
595 RRC16p = 580, // MSP430InstrInfo.td:684
596 RRC16r = 581, // MSP430InstrInfo.td:629
597 RRC8m = 582, // MSP430InstrInfo.td:672
598 RRC8n = 583, // MSP430InstrInfo.td:681
599 RRC8p = 584, // MSP430InstrInfo.td:683
600 RRC8r = 585, // MSP430InstrInfo.td:625
601 Rrcl16 = 586, // MSP430InstrInfo.td:219
602 Rrcl8 = 587, // MSP430InstrInfo.td:217
603 SEXT16m = 588, // MSP430InstrInfo.td:688
604 SEXT16n = 589, // MSP430InstrInfo.td:693
605 SEXT16p = 590, // MSP430InstrInfo.td:694
606 SEXT16r = 591, // MSP430InstrInfo.td:635
607 SUB16mc = 592, // MSP430InstrInfo.td:499
608 SUB16mi = 593, // MSP430InstrInfo.td:505
609 SUB16mm = 594, // MSP430InstrInfo.td:512
610 SUB16mn = 595, // MSP430InstrInfo.td:518
611 SUB16mp = 596, // MSP430InstrInfo.td:522
612 SUB16mr = 597, // MSP430InstrInfo.td:493
613 SUB16rc = 598, // MSP430InstrInfo.td:480
614 SUB16ri = 599, // MSP430InstrInfo.td:486
615 SUB16rm = 600, // MSP430InstrInfo.td:462
616 SUB16rn = 601, // MSP430InstrInfo.td:467
617 SUB16rp = 602, // MSP430InstrInfo.td:474
618 SUB16rr = 603, // MSP430InstrInfo.td:455
619 SUB8mc = 604, // MSP430InstrInfo.td:496
620 SUB8mi = 605, // MSP430InstrInfo.td:502
621 SUB8mm = 606, // MSP430InstrInfo.td:508
622 SUB8mn = 607, // MSP430InstrInfo.td:516
623 SUB8mp = 608, // MSP430InstrInfo.td:520
624 SUB8mr = 609, // MSP430InstrInfo.td:490
625 SUB8rc = 610, // MSP430InstrInfo.td:477
626 SUB8ri = 611, // MSP430InstrInfo.td:483
627 SUB8rm = 612, // MSP430InstrInfo.td:459
628 SUB8rn = 613, // MSP430InstrInfo.td:465
629 SUB8rp = 614, // MSP430InstrInfo.td:472
630 SUB8rr = 615, // MSP430InstrInfo.td:452
631 SUBC16mc = 616, // MSP430InstrInfo.td:499
632 SUBC16mi = 617, // MSP430InstrInfo.td:505
633 SUBC16mm = 618, // MSP430InstrInfo.td:512
634 SUBC16mn = 619, // MSP430InstrInfo.td:518
635 SUBC16mp = 620, // MSP430InstrInfo.td:522
636 SUBC16mr = 621, // MSP430InstrInfo.td:493
637 SUBC16rc = 622, // MSP430InstrInfo.td:480
638 SUBC16ri = 623, // MSP430InstrInfo.td:486
639 SUBC16rm = 624, // MSP430InstrInfo.td:462
640 SUBC16rn = 625, // MSP430InstrInfo.td:467
641 SUBC16rp = 626, // MSP430InstrInfo.td:474
642 SUBC16rr = 627, // MSP430InstrInfo.td:455
643 SUBC8mc = 628, // MSP430InstrInfo.td:496
644 SUBC8mi = 629, // MSP430InstrInfo.td:502
645 SUBC8mm = 630, // MSP430InstrInfo.td:508
646 SUBC8mn = 631, // MSP430InstrInfo.td:516
647 SUBC8mp = 632, // MSP430InstrInfo.td:520
648 SUBC8mr = 633, // MSP430InstrInfo.td:490
649 SUBC8rc = 634, // MSP430InstrInfo.td:477
650 SUBC8ri = 635, // MSP430InstrInfo.td:483
651 SUBC8rm = 636, // MSP430InstrInfo.td:459
652 SUBC8rn = 637, // MSP430InstrInfo.td:465
653 SUBC8rp = 638, // MSP430InstrInfo.td:472
654 SUBC8rr = 639, // MSP430InstrInfo.td:452
655 SWPB16m = 640, // MSP430InstrInfo.td:698
656 SWPB16n = 641, // MSP430InstrInfo.td:702
657 SWPB16p = 642, // MSP430InstrInfo.td:703
658 SWPB16r = 643, // MSP430InstrInfo.td:648
659 Select16 = 644, // MSP430InstrInfo.td:193
660 Select8 = 645, // MSP430InstrInfo.td:189
661 Shl16 = 646, // MSP430InstrInfo.td:202
662 Shl8 = 647, // MSP430InstrInfo.td:199
663 Sra16 = 648, // MSP430InstrInfo.td:208
664 Sra8 = 649, // MSP430InstrInfo.td:205
665 Srl16 = 650, // MSP430InstrInfo.td:214
666 Srl8 = 651, // MSP430InstrInfo.td:211
667 XOR16mc = 652, // MSP430InstrInfo.td:499
668 XOR16mi = 653, // MSP430InstrInfo.td:505
669 XOR16mm = 654, // MSP430InstrInfo.td:512
670 XOR16mn = 655, // MSP430InstrInfo.td:518
671 XOR16mp = 656, // MSP430InstrInfo.td:522
672 XOR16mr = 657, // MSP430InstrInfo.td:493
673 XOR16rc = 658, // MSP430InstrInfo.td:480
674 XOR16ri = 659, // MSP430InstrInfo.td:486
675 XOR16rm = 660, // MSP430InstrInfo.td:462
676 XOR16rn = 661, // MSP430InstrInfo.td:467
677 XOR16rp = 662, // MSP430InstrInfo.td:474
678 XOR16rr = 663, // MSP430InstrInfo.td:455
679 XOR8mc = 664, // MSP430InstrInfo.td:496
680 XOR8mi = 665, // MSP430InstrInfo.td:502
681 XOR8mm = 666, // MSP430InstrInfo.td:508
682 XOR8mn = 667, // MSP430InstrInfo.td:516
683 XOR8mp = 668, // MSP430InstrInfo.td:520
684 XOR8mr = 669, // MSP430InstrInfo.td:490
685 XOR8rc = 670, // MSP430InstrInfo.td:477
686 XOR8ri = 671, // MSP430InstrInfo.td:483
687 XOR8rm = 672, // MSP430InstrInfo.td:459
688 XOR8rn = 673, // MSP430InstrInfo.td:465
689 XOR8rp = 674, // MSP430InstrInfo.td:472
690 XOR8rr = 675, // MSP430InstrInfo.td:452
691 ZEXT16r = 676, // MSP430InstrInfo.td:643
692 INSTRUCTION_LIST_END = 677
693 };
694
695} // namespace llvm::MSP430
696
697#endif // GET_INSTRINFO_ENUM
698
699#ifdef GET_INSTRINFO_SCHED_ENUM
700#undef GET_INSTRINFO_SCHED_ENUM
701
702namespace llvm::MSP430::Sched {
703
704 enum {
705 NoInstrModel = 0,
706 SCHED_LIST_END = 1
707 };
708
709} // namespace llvm::MSP430::Sched
710
711#endif // GET_INSTRINFO_SCHED_ENUM
712
713#if defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
714
715namespace llvm {
716
717struct MSP430InstrTable {
718 MCInstrDesc Insts[677];
719 static_assert(alignof(MCInstrDesc) >= alignof(MCPhysReg), "Unwanted padding between Insts and ImplicitOps");
720 MCPhysReg ImplicitOps[17];
721 char Padding[sizeof(MCOperandInfo) - sizeof ImplicitOps % sizeof(MCOperandInfo)];
722 static_assert(alignof(MCInstrDesc) >= alignof(MCOperandInfo), "Unwanted padding between Insts and OperandInfo");
723 MCOperandInfo OperandInfo[260];
724};
725} // namespace llvm
726
727#endif // defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
728
729#ifdef GET_INSTRINFO_MC_DESC
730#undef GET_INSTRINFO_MC_DESC
731
732namespace llvm {
733
734static_assert((sizeof MSP430InstrTable::ImplicitOps + sizeof MSP430InstrTable::Padding) % sizeof(MCOperandInfo) == 0);
735static constexpr unsigned MSP430OpInfoBase = (sizeof MSP430InstrTable::ImplicitOps + sizeof MSP430InstrTable::Padding) / sizeof(MCOperandInfo);
736
737extern const MSP430InstrTable MSP430Descs = {
738 {
739 { 676, 2, 1, 2, 0, 0, 0, MSP430OpInfoBase + 242, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ZEXT16r
740 { 675, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 207, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR8rr
741 { 674, 4, 2, 2, 0, 0, 1, MSP430OpInfoBase + 203, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR8rp
742 { 673, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR8rn
743 { 672, 4, 1, 4, 0, 0, 1, MSP430OpInfoBase + 196, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR8rm
744 { 671, 3, 1, 4, 0, 0, 1, MSP430OpInfoBase + 193, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR8ri
745 { 670, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 190, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR8rc
746 { 669, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 187, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR8mr
747 { 668, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR8mp
748 { 667, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR8mn
749 { 666, 4, 0, 6, 0, 0, 1, MSP430OpInfoBase + 157, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR8mm
750 { 665, 3, 0, 6, 0, 0, 1, MSP430OpInfoBase + 154, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR8mi
751 { 664, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 151, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR8mc
752 { 663, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 184, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR16rr
753 { 662, 4, 2, 2, 0, 0, 1, MSP430OpInfoBase + 180, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR16rp
754 { 661, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 177, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR16rn
755 { 660, 4, 1, 4, 0, 0, 1, MSP430OpInfoBase + 173, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR16rm
756 { 659, 3, 1, 4, 0, 0, 1, MSP430OpInfoBase + 170, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR16ri
757 { 658, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 167, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR16rc
758 { 657, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 164, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR16mr
759 { 656, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR16mp
760 { 655, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR16mn
761 { 654, 4, 0, 6, 0, 0, 1, MSP430OpInfoBase + 157, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR16mm
762 { 653, 3, 0, 6, 0, 0, 1, MSP430OpInfoBase + 154, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR16mi
763 { 652, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 151, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR16mc
764 { 651, 3, 1, 0, 0, 0, 1, MSP430OpInfoBase + 257, 0, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Srl8
765 { 650, 3, 1, 0, 0, 0, 1, MSP430OpInfoBase + 254, 0, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Srl16
766 { 649, 3, 1, 0, 0, 0, 1, MSP430OpInfoBase + 257, 0, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Sra8
767 { 648, 3, 1, 0, 0, 0, 1, MSP430OpInfoBase + 254, 0, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Sra16
768 { 647, 3, 1, 0, 0, 0, 1, MSP430OpInfoBase + 257, 0, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Shl8
769 { 646, 3, 1, 0, 0, 0, 1, MSP430OpInfoBase + 254, 0, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Shl16
770 { 645, 4, 1, 0, 0, 1, 0, MSP430OpInfoBase + 250, 0, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Select8
771 { 644, 4, 1, 0, 0, 1, 0, MSP430OpInfoBase + 246, 0, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Select16
772 { 643, 2, 1, 2, 0, 0, 0, MSP430OpInfoBase + 242, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SWPB16r
773 { 642, 1, 0, 2, 0, 0, 0, MSP430OpInfoBase + 232, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SWPB16p
774 { 641, 1, 0, 2, 0, 0, 0, MSP430OpInfoBase + 232, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SWPB16n
775 { 640, 2, 0, 4, 0, 0, 0, MSP430OpInfoBase + 230, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SWPB16m
776 { 639, 3, 1, 2, 0, 1, 1, MSP430OpInfoBase + 207, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC8rr
777 { 638, 4, 2, 2, 0, 1, 1, MSP430OpInfoBase + 203, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC8rp
778 { 637, 3, 1, 2, 0, 1, 1, MSP430OpInfoBase + 200, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC8rn
779 { 636, 4, 1, 4, 0, 1, 1, MSP430OpInfoBase + 196, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC8rm
780 { 635, 3, 1, 4, 0, 1, 1, MSP430OpInfoBase + 193, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC8ri
781 { 634, 3, 1, 2, 0, 1, 1, MSP430OpInfoBase + 190, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC8rc
782 { 633, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 187, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC8mr
783 { 632, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 161, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC8mp
784 { 631, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 161, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC8mn
785 { 630, 4, 0, 6, 0, 1, 1, MSP430OpInfoBase + 157, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC8mm
786 { 629, 3, 0, 6, 0, 1, 1, MSP430OpInfoBase + 154, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC8mi
787 { 628, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 151, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC8mc
788 { 627, 3, 1, 2, 0, 1, 1, MSP430OpInfoBase + 184, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC16rr
789 { 626, 4, 2, 2, 0, 1, 1, MSP430OpInfoBase + 180, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC16rp
790 { 625, 3, 1, 2, 0, 1, 1, MSP430OpInfoBase + 177, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC16rn
791 { 624, 4, 1, 4, 0, 1, 1, MSP430OpInfoBase + 173, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC16rm
792 { 623, 3, 1, 4, 0, 1, 1, MSP430OpInfoBase + 170, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC16ri
793 { 622, 3, 1, 2, 0, 1, 1, MSP430OpInfoBase + 167, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC16rc
794 { 621, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 164, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC16mr
795 { 620, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 161, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC16mp
796 { 619, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 161, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC16mn
797 { 618, 4, 0, 6, 0, 1, 1, MSP430OpInfoBase + 157, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC16mm
798 { 617, 3, 0, 6, 0, 1, 1, MSP430OpInfoBase + 154, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC16mi
799 { 616, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 151, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBC16mc
800 { 615, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 207, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB8rr
801 { 614, 4, 2, 2, 0, 0, 1, MSP430OpInfoBase + 203, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB8rp
802 { 613, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB8rn
803 { 612, 4, 1, 4, 0, 0, 1, MSP430OpInfoBase + 196, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB8rm
804 { 611, 3, 1, 4, 0, 0, 1, MSP430OpInfoBase + 193, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB8ri
805 { 610, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 190, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB8rc
806 { 609, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 187, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB8mr
807 { 608, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB8mp
808 { 607, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB8mn
809 { 606, 4, 0, 6, 0, 0, 1, MSP430OpInfoBase + 157, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB8mm
810 { 605, 3, 0, 6, 0, 0, 1, MSP430OpInfoBase + 154, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB8mi
811 { 604, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 151, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB8mc
812 { 603, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 184, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB16rr
813 { 602, 4, 2, 2, 0, 0, 1, MSP430OpInfoBase + 180, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB16rp
814 { 601, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 177, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB16rn
815 { 600, 4, 1, 4, 0, 0, 1, MSP430OpInfoBase + 173, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB16rm
816 { 599, 3, 1, 4, 0, 0, 1, MSP430OpInfoBase + 170, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB16ri
817 { 598, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 167, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB16rc
818 { 597, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 164, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB16mr
819 { 596, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB16mp
820 { 595, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB16mn
821 { 594, 4, 0, 6, 0, 0, 1, MSP430OpInfoBase + 157, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB16mm
822 { 593, 3, 0, 6, 0, 0, 1, MSP430OpInfoBase + 154, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB16mi
823 { 592, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 151, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB16mc
824 { 591, 2, 1, 2, 0, 0, 1, MSP430OpInfoBase + 242, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SEXT16r
825 { 590, 1, 0, 2, 0, 0, 1, MSP430OpInfoBase + 232, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SEXT16p
826 { 589, 1, 0, 2, 0, 0, 1, MSP430OpInfoBase + 232, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SEXT16n
827 { 588, 2, 0, 4, 0, 0, 1, MSP430OpInfoBase + 230, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SEXT16m
828 { 587, 2, 1, 0, 0, 0, 1, MSP430OpInfoBase + 228, 0, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Rrcl8
829 { 586, 2, 1, 0, 0, 0, 1, MSP430OpInfoBase + 217, 0, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Rrcl16
830 { 585, 2, 1, 2, 0, 1, 1, MSP430OpInfoBase + 244, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RRC8r
831 { 584, 1, 0, 2, 0, 1, 1, MSP430OpInfoBase + 232, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RRC8p
832 { 583, 1, 0, 2, 0, 1, 1, MSP430OpInfoBase + 232, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RRC8n
833 { 582, 2, 0, 4, 0, 1, 1, MSP430OpInfoBase + 230, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RRC8m
834 { 581, 2, 1, 2, 0, 1, 1, MSP430OpInfoBase + 242, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RRC16r
835 { 580, 1, 0, 2, 0, 1, 1, MSP430OpInfoBase + 232, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RRC16p
836 { 579, 1, 0, 2, 0, 1, 1, MSP430OpInfoBase + 232, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RRC16n
837 { 578, 2, 0, 4, 0, 1, 1, MSP430OpInfoBase + 230, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RRC16m
838 { 577, 2, 1, 2, 0, 0, 1, MSP430OpInfoBase + 244, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RRA8r
839 { 576, 1, 0, 2, 0, 0, 1, MSP430OpInfoBase + 232, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RRA8p
840 { 575, 1, 0, 2, 0, 0, 1, MSP430OpInfoBase + 232, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RRA8n
841 { 574, 2, 0, 4, 0, 0, 1, MSP430OpInfoBase + 230, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RRA8m
842 { 573, 2, 1, 2, 0, 0, 1, MSP430OpInfoBase + 242, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RRA16r
843 { 572, 1, 0, 2, 0, 0, 1, MSP430OpInfoBase + 232, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RRA16p
844 { 571, 1, 0, 2, 0, 0, 1, MSP430OpInfoBase + 232, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RRA16n
845 { 570, 2, 0, 4, 0, 0, 1, MSP430OpInfoBase + 230, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RRA16m
846 { 569, 0, 0, 2, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RETI
847 { 568, 0, 0, 2, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RET
848 { 567, 1, 0, 2, 0, 1, 1, MSP430OpInfoBase + 241, 15, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PUSH8r
849 { 566, 1, 0, 2, 0, 1, 1, MSP430OpInfoBase + 28, 15, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PUSH16r
850 { 565, 1, 0, 4, 0, 1, 1, MSP430OpInfoBase + 1, 15, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PUSH16i
851 { 564, 1, 0, 2, 0, 1, 1, MSP430OpInfoBase + 0, 15, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PUSH16c
852 { 563, 1, 1, 2, 0, 1, 1, MSP430OpInfoBase + 28, 15, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // POP16r
853 { 562, 2, 1, 2, 0, 0, 0, MSP430OpInfoBase + 239, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOVZX16rr8
854 { 561, 3, 1, 4, 0, 0, 0, MSP430OpInfoBase + 212, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOVZX16rm8
855 { 560, 2, 1, 2, 0, 0, 0, MSP430OpInfoBase + 228, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV8rr
856 { 559, 3, 2, 2, 0, 0, 0, MSP430OpInfoBase + 236, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV8rp
857 { 558, 2, 1, 2, 0, 0, 0, MSP430OpInfoBase + 226, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV8rn
858 { 557, 3, 1, 4, 0, 0, 0, MSP430OpInfoBase + 223, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV8rm
859 { 556, 2, 1, 4, 0, 0, 0, MSP430OpInfoBase + 221, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV8ri
860 { 555, 2, 1, 2, 0, 0, 0, MSP430OpInfoBase + 219, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV8rc
861 { 554, 3, 0, 4, 0, 0, 0, MSP430OpInfoBase + 187, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV8mr
862 { 553, 3, 0, 4, 0, 0, 0, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV8mn
863 { 552, 4, 0, 6, 0, 0, 0, MSP430OpInfoBase + 157, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV8mm
864 { 551, 3, 0, 6, 0, 0, 0, MSP430OpInfoBase + 154, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV8mi
865 { 550, 3, 0, 4, 0, 0, 0, MSP430OpInfoBase + 151, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV8mc
866 { 549, 2, 1, 2, 0, 0, 0, MSP430OpInfoBase + 217, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV16rr
867 { 548, 3, 2, 2, 0, 0, 0, MSP430OpInfoBase + 233, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV16rp
868 { 547, 2, 1, 2, 0, 0, 0, MSP430OpInfoBase + 215, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV16rn
869 { 546, 3, 1, 4, 0, 0, 0, MSP430OpInfoBase + 212, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV16rm
870 { 545, 2, 1, 4, 0, 0, 0, MSP430OpInfoBase + 210, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV16ri
871 { 544, 2, 1, 2, 0, 0, 0, MSP430OpInfoBase + 34, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV16rc
872 { 543, 3, 0, 4, 0, 0, 0, MSP430OpInfoBase + 164, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV16mr
873 { 542, 3, 0, 4, 0, 0, 0, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV16mn
874 { 541, 4, 0, 6, 0, 0, 0, MSP430OpInfoBase + 157, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV16mm
875 { 540, 3, 0, 6, 0, 0, 0, MSP430OpInfoBase + 154, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV16mi
876 { 539, 3, 0, 4, 0, 0, 0, MSP430OpInfoBase + 151, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV16mc
877 { 538, 1, 0, 2, 0, 0, 0, MSP430OpInfoBase + 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JMP
878 { 537, 2, 0, 2, 0, 1, 0, MSP430OpInfoBase + 9, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JCC
879 { 536, 3, 1, 2, 0, 1, 1, MSP430OpInfoBase + 207, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD8rr
880 { 535, 4, 2, 2, 0, 1, 1, MSP430OpInfoBase + 203, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD8rp
881 { 534, 3, 1, 2, 0, 1, 1, MSP430OpInfoBase + 200, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD8rn
882 { 533, 4, 1, 4, 0, 1, 1, MSP430OpInfoBase + 196, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD8rm
883 { 532, 3, 1, 4, 0, 1, 1, MSP430OpInfoBase + 193, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD8ri
884 { 531, 3, 1, 2, 0, 1, 1, MSP430OpInfoBase + 190, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD8rc
885 { 530, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 187, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD8mr
886 { 529, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 161, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD8mp
887 { 528, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 161, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD8mn
888 { 527, 4, 0, 6, 0, 1, 1, MSP430OpInfoBase + 157, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD8mm
889 { 526, 3, 0, 6, 0, 1, 1, MSP430OpInfoBase + 154, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD8mi
890 { 525, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 151, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD8mc
891 { 524, 3, 1, 2, 0, 1, 1, MSP430OpInfoBase + 184, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD16rr
892 { 523, 4, 2, 2, 0, 1, 1, MSP430OpInfoBase + 180, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD16rp
893 { 522, 3, 1, 2, 0, 1, 1, MSP430OpInfoBase + 177, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD16rn
894 { 521, 4, 1, 4, 0, 1, 1, MSP430OpInfoBase + 173, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD16rm
895 { 520, 3, 1, 4, 0, 1, 1, MSP430OpInfoBase + 170, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD16ri
896 { 519, 3, 1, 2, 0, 1, 1, MSP430OpInfoBase + 167, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD16rc
897 { 518, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 164, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD16mr
898 { 517, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 161, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD16mp
899 { 516, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 161, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD16mn
900 { 515, 4, 0, 6, 0, 1, 1, MSP430OpInfoBase + 157, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD16mm
901 { 514, 3, 0, 6, 0, 1, 1, MSP430OpInfoBase + 154, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD16mi
902 { 513, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 151, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DADD16mc
903 { 512, 2, 0, 2, 0, 0, 1, MSP430OpInfoBase + 228, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP8rr
904 { 511, 2, 0, 2, 0, 0, 1, MSP430OpInfoBase + 226, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP8rp
905 { 510, 2, 0, 2, 0, 0, 1, MSP430OpInfoBase + 226, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP8rn
906 { 509, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 223, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP8rm
907 { 508, 2, 0, 4, 0, 0, 1, MSP430OpInfoBase + 221, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP8ri
908 { 507, 2, 0, 2, 0, 0, 1, MSP430OpInfoBase + 219, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP8rc
909 { 506, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 187, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP8mr
910 { 505, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP8mp
911 { 504, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP8mn
912 { 503, 4, 0, 6, 0, 0, 1, MSP430OpInfoBase + 157, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP8mm
913 { 502, 3, 0, 6, 0, 0, 1, MSP430OpInfoBase + 154, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP8mi
914 { 501, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 151, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP8mc
915 { 500, 2, 0, 2, 0, 0, 1, MSP430OpInfoBase + 217, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP16rr
916 { 499, 2, 0, 2, 0, 0, 1, MSP430OpInfoBase + 215, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP16rp
917 { 498, 2, 0, 2, 0, 0, 1, MSP430OpInfoBase + 215, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP16rn
918 { 497, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 212, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP16rm
919 { 496, 2, 0, 4, 0, 0, 1, MSP430OpInfoBase + 210, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP16ri
920 { 495, 2, 0, 2, 0, 0, 1, MSP430OpInfoBase + 34, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP16rc
921 { 494, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 164, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP16mr
922 { 493, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP16mp
923 { 492, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP16mn
924 { 491, 4, 0, 6, 0, 0, 1, MSP430OpInfoBase + 157, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP16mm
925 { 490, 3, 0, 6, 0, 0, 1, MSP430OpInfoBase + 154, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP16mi
926 { 489, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 151, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMP16mc
927 { 488, 1, 0, 2, 0, 1, 6, MSP430OpInfoBase + 28, 8, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CALLr
928 { 487, 1, 0, 2, 0, 1, 6, MSP430OpInfoBase + 232, 8, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CALLp
929 { 486, 1, 0, 2, 0, 1, 6, MSP430OpInfoBase + 232, 8, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CALLn
930 { 485, 2, 0, 4, 0, 1, 6, MSP430OpInfoBase + 230, 8, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CALLm
931 { 484, 1, 0, 4, 0, 1, 6, MSP430OpInfoBase + 1, 8, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CALLi
932 { 483, 1, 0, 2, 0, 0, 0, MSP430OpInfoBase + 28, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Br
933 { 482, 2, 0, 4, 0, 0, 0, MSP430OpInfoBase + 230, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Bm
934 { 481, 1, 0, 4, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Bi
935 { 480, 2, 0, 2, 0, 0, 1, MSP430OpInfoBase + 228, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT8rr
936 { 479, 2, 0, 2, 0, 0, 1, MSP430OpInfoBase + 226, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT8rp
937 { 478, 2, 0, 2, 0, 0, 1, MSP430OpInfoBase + 226, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT8rn
938 { 477, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 223, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT8rm
939 { 476, 2, 0, 4, 0, 0, 1, MSP430OpInfoBase + 221, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT8ri
940 { 475, 2, 0, 2, 0, 0, 1, MSP430OpInfoBase + 219, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT8rc
941 { 474, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 187, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT8mr
942 { 473, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT8mp
943 { 472, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT8mn
944 { 471, 4, 0, 6, 0, 0, 1, MSP430OpInfoBase + 157, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT8mm
945 { 470, 3, 0, 6, 0, 0, 1, MSP430OpInfoBase + 154, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT8mi
946 { 469, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 151, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT8mc
947 { 468, 2, 0, 2, 0, 0, 1, MSP430OpInfoBase + 217, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT16rr
948 { 467, 2, 0, 2, 0, 0, 1, MSP430OpInfoBase + 215, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT16rp
949 { 466, 2, 0, 2, 0, 0, 1, MSP430OpInfoBase + 215, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT16rn
950 { 465, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 212, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT16rm
951 { 464, 2, 0, 4, 0, 0, 1, MSP430OpInfoBase + 210, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT16ri
952 { 463, 2, 0, 2, 0, 0, 1, MSP430OpInfoBase + 34, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT16rc
953 { 462, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 164, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT16mr
954 { 461, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT16mp
955 { 460, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT16mn
956 { 459, 4, 0, 6, 0, 0, 1, MSP430OpInfoBase + 157, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT16mm
957 { 458, 3, 0, 6, 0, 0, 1, MSP430OpInfoBase + 154, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT16mi
958 { 457, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 151, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIT16mc
959 { 456, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 207, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS8rr
960 { 455, 4, 2, 2, 0, 0, 1, MSP430OpInfoBase + 203, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS8rp
961 { 454, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS8rn
962 { 453, 4, 1, 4, 0, 0, 1, MSP430OpInfoBase + 196, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS8rm
963 { 452, 3, 1, 4, 0, 0, 1, MSP430OpInfoBase + 193, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS8ri
964 { 451, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 190, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS8rc
965 { 450, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 187, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS8mr
966 { 449, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS8mp
967 { 448, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS8mn
968 { 447, 4, 0, 6, 0, 0, 1, MSP430OpInfoBase + 157, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS8mm
969 { 446, 3, 0, 6, 0, 0, 1, MSP430OpInfoBase + 154, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS8mi
970 { 445, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 151, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS8mc
971 { 444, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 184, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS16rr
972 { 443, 4, 2, 2, 0, 0, 1, MSP430OpInfoBase + 180, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS16rp
973 { 442, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 177, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS16rn
974 { 441, 4, 1, 4, 0, 0, 1, MSP430OpInfoBase + 173, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS16rm
975 { 440, 3, 1, 4, 0, 0, 1, MSP430OpInfoBase + 170, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS16ri
976 { 439, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 167, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS16rc
977 { 438, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 164, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS16mr
978 { 437, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS16mp
979 { 436, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS16mn
980 { 435, 4, 0, 6, 0, 0, 1, MSP430OpInfoBase + 157, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS16mm
981 { 434, 3, 0, 6, 0, 0, 1, MSP430OpInfoBase + 154, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS16mi
982 { 433, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 151, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIS16mc
983 { 432, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 207, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC8rr
984 { 431, 4, 2, 2, 0, 0, 1, MSP430OpInfoBase + 203, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC8rp
985 { 430, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC8rn
986 { 429, 4, 1, 4, 0, 0, 1, MSP430OpInfoBase + 196, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC8rm
987 { 428, 3, 1, 4, 0, 0, 1, MSP430OpInfoBase + 193, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC8ri
988 { 427, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 190, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC8rc
989 { 426, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 187, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC8mr
990 { 425, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC8mp
991 { 424, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC8mn
992 { 423, 4, 0, 6, 0, 0, 1, MSP430OpInfoBase + 157, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC8mm
993 { 422, 3, 0, 6, 0, 0, 1, MSP430OpInfoBase + 154, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC8mi
994 { 421, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 151, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC8mc
995 { 420, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 184, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC16rr
996 { 419, 4, 2, 2, 0, 0, 1, MSP430OpInfoBase + 180, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC16rp
997 { 418, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 177, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC16rn
998 { 417, 4, 1, 4, 0, 0, 1, MSP430OpInfoBase + 173, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC16rm
999 { 416, 3, 1, 4, 0, 0, 1, MSP430OpInfoBase + 170, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC16ri
1000 { 415, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 167, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC16rc
1001 { 414, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 164, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC16mr
1002 { 413, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC16mp
1003 { 412, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC16mn
1004 { 411, 4, 0, 6, 0, 0, 1, MSP430OpInfoBase + 157, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC16mm
1005 { 410, 3, 0, 6, 0, 0, 1, MSP430OpInfoBase + 154, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC16mi
1006 { 409, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 151, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BIC16mc
1007 { 408, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 207, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND8rr
1008 { 407, 4, 2, 2, 0, 0, 1, MSP430OpInfoBase + 203, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND8rp
1009 { 406, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND8rn
1010 { 405, 4, 1, 4, 0, 0, 1, MSP430OpInfoBase + 196, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND8rm
1011 { 404, 3, 1, 4, 0, 0, 1, MSP430OpInfoBase + 193, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND8ri
1012 { 403, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 190, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND8rc
1013 { 402, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 187, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND8mr
1014 { 401, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND8mp
1015 { 400, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND8mn
1016 { 399, 4, 0, 6, 0, 0, 1, MSP430OpInfoBase + 157, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND8mm
1017 { 398, 3, 0, 6, 0, 0, 1, MSP430OpInfoBase + 154, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND8mi
1018 { 397, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 151, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND8mc
1019 { 396, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 184, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND16rr
1020 { 395, 4, 2, 2, 0, 0, 1, MSP430OpInfoBase + 180, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND16rp
1021 { 394, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 177, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND16rn
1022 { 393, 4, 1, 4, 0, 0, 1, MSP430OpInfoBase + 173, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND16rm
1023 { 392, 3, 1, 4, 0, 0, 1, MSP430OpInfoBase + 170, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND16ri
1024 { 391, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 167, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND16rc
1025 { 390, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 164, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND16mr
1026 { 389, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND16mp
1027 { 388, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND16mn
1028 { 387, 4, 0, 6, 0, 0, 1, MSP430OpInfoBase + 157, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND16mm
1029 { 386, 3, 0, 6, 0, 0, 1, MSP430OpInfoBase + 154, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND16mi
1030 { 385, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 151, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND16mc
1031 { 384, 2, 0, 0, 0, 1, 2, MSP430OpInfoBase + 20, 5, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADJCALLSTACKUP
1032 { 383, 2, 0, 0, 0, 1, 2, MSP430OpInfoBase + 20, 5, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADJCALLSTACKDOWN
1033 { 382, 3, 1, 0, 0, 1, 1, MSP430OpInfoBase + 29, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDframe
1034 { 381, 3, 1, 2, 0, 1, 1, MSP430OpInfoBase + 207, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC8rr
1035 { 380, 4, 2, 2, 0, 1, 1, MSP430OpInfoBase + 203, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC8rp
1036 { 379, 3, 1, 2, 0, 1, 1, MSP430OpInfoBase + 200, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC8rn
1037 { 378, 4, 1, 4, 0, 1, 1, MSP430OpInfoBase + 196, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC8rm
1038 { 377, 3, 1, 4, 0, 1, 1, MSP430OpInfoBase + 193, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC8ri
1039 { 376, 3, 1, 2, 0, 1, 1, MSP430OpInfoBase + 190, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC8rc
1040 { 375, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 187, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC8mr
1041 { 374, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 161, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC8mp
1042 { 373, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 161, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC8mn
1043 { 372, 4, 0, 6, 0, 1, 1, MSP430OpInfoBase + 157, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC8mm
1044 { 371, 3, 0, 6, 0, 1, 1, MSP430OpInfoBase + 154, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC8mi
1045 { 370, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 151, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC8mc
1046 { 369, 3, 1, 2, 0, 1, 1, MSP430OpInfoBase + 184, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC16rr
1047 { 368, 4, 2, 2, 0, 1, 1, MSP430OpInfoBase + 180, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC16rp
1048 { 367, 3, 1, 2, 0, 1, 1, MSP430OpInfoBase + 177, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC16rn
1049 { 366, 4, 1, 4, 0, 1, 1, MSP430OpInfoBase + 173, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC16rm
1050 { 365, 3, 1, 4, 0, 1, 1, MSP430OpInfoBase + 170, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC16ri
1051 { 364, 3, 1, 2, 0, 1, 1, MSP430OpInfoBase + 167, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC16rc
1052 { 363, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 164, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC16mr
1053 { 362, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 161, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC16mp
1054 { 361, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 161, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC16mn
1055 { 360, 4, 0, 6, 0, 1, 1, MSP430OpInfoBase + 157, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC16mm
1056 { 359, 3, 0, 6, 0, 1, 1, MSP430OpInfoBase + 154, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC16mi
1057 { 358, 3, 0, 4, 0, 1, 1, MSP430OpInfoBase + 151, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDC16mc
1058 { 357, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 207, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD8rr
1059 { 356, 4, 2, 2, 0, 0, 1, MSP430OpInfoBase + 203, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD8rp
1060 { 355, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 200, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD8rn
1061 { 354, 4, 1, 4, 0, 0, 1, MSP430OpInfoBase + 196, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD8rm
1062 { 353, 3, 1, 4, 0, 0, 1, MSP430OpInfoBase + 193, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD8ri
1063 { 352, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 190, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD8rc
1064 { 351, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 187, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD8mr
1065 { 350, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD8mp
1066 { 349, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD8mn
1067 { 348, 4, 0, 6, 0, 0, 1, MSP430OpInfoBase + 157, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD8mm
1068 { 347, 3, 0, 6, 0, 0, 1, MSP430OpInfoBase + 154, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD8mi
1069 { 346, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 151, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD8mc
1070 { 345, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 184, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD16rr
1071 { 344, 4, 2, 2, 0, 0, 1, MSP430OpInfoBase + 180, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD16rp
1072 { 343, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 177, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD16rn
1073 { 342, 4, 1, 4, 0, 0, 1, MSP430OpInfoBase + 173, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD16rm
1074 { 341, 3, 1, 4, 0, 0, 1, MSP430OpInfoBase + 170, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD16ri
1075 { 340, 3, 1, 2, 0, 0, 1, MSP430OpInfoBase + 167, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD16rc
1076 { 339, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 164, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD16mr
1077 { 338, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD16mp
1078 { 337, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 161, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD16mn
1079 { 336, 4, 0, 6, 0, 0, 1, MSP430OpInfoBase + 157, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD16mm
1080 { 335, 3, 0, 6, 0, 0, 1, MSP430OpInfoBase + 154, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD16mi
1081 { 334, 3, 0, 4, 0, 0, 1, MSP430OpInfoBase + 151, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD16mc
1082 { 333, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 147, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UBFX
1083 { 332, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 147, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SBFX
1084 { 331, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_UMIN
1085 { 330, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_UMAX
1086 { 329, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SMIN
1087 { 328, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SMAX
1088 { 327, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_XOR
1089 { 326, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_OR
1090 { 325, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_AND
1091 { 324, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_MUL
1092 { 323, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_ADD
1093 { 322, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMINIMUMNUM
1094 { 321, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMAXIMUMNUM
1095 { 320, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMINIMUM
1096 { 319, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMAXIMUM
1097 { 318, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMIN
1098 { 317, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMAX
1099 { 316, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMUL
1100 { 315, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FADD
1101 { 314, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SEQ_FMUL
1102 { 313, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SEQ_FADD
1103 { 312, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UBSANTRAP
1104 { 311, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_DEBUGTRAP
1105 { 310, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRAP
1106 { 309, 3, 0, 0, 0, 0, 0, MSP430OpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMSET_INLINE
1107 { 308, 3, 0, 0, 0, 0, 0, MSP430OpInfoBase + 57, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BZERO
1108 { 307, 4, 0, 0, 0, 0, 0, MSP430OpInfoBase + 143, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMSET
1109 { 306, 4, 0, 0, 0, 0, 0, MSP430OpInfoBase + 143, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMMOVE
1110 { 305, 3, 0, 0, 0, 0, 0, MSP430OpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMCPY_INLINE
1111 { 304, 4, 0, 0, 0, 0, 0, MSP430OpInfoBase + 143, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMCPY
1112 { 303, 2, 0, 0, 0, 0, 0, MSP430OpInfoBase + 141, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_WRITE_REGISTER
1113 { 302, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_READ_REGISTER
1114 { 301, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FCMPS
1115 { 300, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FCMP
1116 { 299, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FLDEXP
1117 { 298, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FSQRT
1118 { 297, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FMA
1119 { 296, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FREM
1120 { 295, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FDIV
1121 { 294, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FMUL
1122 { 293, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FSUB
1123 { 292, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FADD
1124 { 291, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STACKRESTORE
1125 { 290, 1, 1, 0, 0, 0, 0, MSP430OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STACKSAVE
1126 { 289, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 68, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_DYN_STACKALLOC
1127 { 288, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_JUMP_TABLE
1128 { 287, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BLOCK_ADDR
1129 { 286, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ADDRSPACE_CAST
1130 { 285, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FNEARBYINT
1131 { 284, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FRINT
1132 { 283, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FFLOOR
1133 { 282, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSQRT
1134 { 281, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FTANH
1135 { 280, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSINH
1136 { 279, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCOSH
1137 { 278, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FATAN2
1138 { 277, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FATAN
1139 { 276, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FASIN
1140 { 275, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FACOS
1141 { 274, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FTAN
1142 { 273, 3, 2, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSINCOS
1143 { 272, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSIN
1144 { 271, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCOS
1145 { 270, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCEIL
1146 { 269, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CLMULH
1147 { 268, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CLMUL
1148 { 267, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BITREVERSE
1149 { 266, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BSWAP
1150 { 265, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTPOP
1151 { 264, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTLS
1152 { 263, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTLZ_ZERO_POISON
1153 { 262, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTLZ
1154 { 261, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTTZ_ZERO_POISON
1155 { 260, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTTZ
1156 { 259, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 137, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECTOR_COMPRESS
1157 { 258, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STEP_VECTOR
1158 { 257, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SPLAT_VECTOR
1159 { 256, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 133, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SHUFFLE_VECTOR
1160 { 255, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_EXTRACT_VECTOR_ELT
1161 { 254, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 126, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INSERT_VECTOR_ELT
1162 { 253, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 57, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_EXTRACT_SUBVECTOR
1163 { 252, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 62, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INSERT_SUBVECTOR
1164 { 251, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VSCALE
1165 { 250, 3, 0, 0, 0, 0, 0, MSP430OpInfoBase + 123, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BRJT
1166 { 249, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BR
1167 { 248, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LLROUND
1168 { 247, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LROUND
1169 { 246, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ABS
1170 { 245, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMAX
1171 { 244, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMIN
1172 { 243, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMAX
1173 { 242, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMIN
1174 { 241, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTRMASK
1175 { 240, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTR_ADD
1176 { 239, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SET_ROUNDING
1177 { 238, 1, 1, 0, 0, 0, 0, MSP430OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GET_ROUNDING
1178 { 237, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_RESET_FPMODE
1179 { 236, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SET_FPMODE
1180 { 235, 1, 1, 0, 0, 0, 0, MSP430OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GET_FPMODE
1181 { 234, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_RESET_FPENV
1182 { 233, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SET_FPENV
1183 { 232, 1, 1, 0, 0, 0, 0, MSP430OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GET_FPENV
1184 { 231, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXIMUMNUM
1185 { 230, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINIMUMNUM
1186 { 229, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXIMUM
1187 { 228, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINIMUM
1188 { 227, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXNUM_IEEE
1189 { 226, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINNUM_IEEE
1190 { 225, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXNUM
1191 { 224, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINNUM
1192 { 223, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCANONICALIZE
1193 { 222, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 97, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_IS_FPCLASS
1194 { 221, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCOPYSIGN
1195 { 220, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FABS
1196 { 219, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOUI_SAT
1197 { 218, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOSI_SAT
1198 { 217, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UITOFP
1199 { 216, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SITOFP
1200 { 215, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOUI
1201 { 214, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOSI
1202 { 213, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTRUNC
1203 { 212, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPEXT
1204 { 211, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FNEG
1205 { 210, 3, 2, 0, 0, 0, 0, MSP430OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FFREXP
1206 { 209, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLDEXP
1207 { 208, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLOG10
1208 { 207, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLOG2
1209 { 206, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLOG
1210 { 205, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FEXP10
1211 { 204, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FEXP2
1212 { 203, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FEXP
1213 { 202, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPOWI
1214 { 201, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPOW
1215 { 200, 3, 2, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMODF
1216 { 199, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FREM
1217 { 198, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FDIV
1218 { 197, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAD
1219 { 196, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMA
1220 { 195, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMUL
1221 { 194, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSUB
1222 { 193, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FADD
1223 { 192, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIVFIXSAT
1224 { 191, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIVFIXSAT
1225 { 190, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIVFIX
1226 { 189, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIVFIX
1227 { 188, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULFIXSAT
1228 { 187, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULFIXSAT
1229 { 186, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULFIX
1230 { 185, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULFIX
1231 { 184, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSHLSAT
1232 { 183, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USHLSAT
1233 { 182, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSUBSAT
1234 { 181, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USUBSAT
1235 { 180, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SADDSAT
1236 { 179, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UADDSAT
1237 { 178, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULH
1238 { 177, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULH
1239 { 176, 4, 2, 0, 0, 0, 0, MSP430OpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULO
1240 { 175, 4, 2, 0, 0, 0, 0, MSP430OpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULO
1241 { 174, 5, 2, 0, 0, 0, 0, MSP430OpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSUBE
1242 { 173, 4, 2, 0, 0, 0, 0, MSP430OpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSUBO
1243 { 172, 5, 2, 0, 0, 0, 0, MSP430OpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SADDE
1244 { 171, 4, 2, 0, 0, 0, 0, MSP430OpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SADDO
1245 { 170, 5, 2, 0, 0, 0, 0, MSP430OpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USUBE
1246 { 169, 4, 2, 0, 0, 0, 0, MSP430OpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USUBO
1247 { 168, 5, 2, 0, 0, 0, 0, MSP430OpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UADDE
1248 { 167, 4, 2, 0, 0, 0, 0, MSP430OpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UADDO
1249 { 166, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SELECT
1250 { 165, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 111, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UCMP
1251 { 164, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 111, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SCMP
1252 { 163, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCMP
1253 { 162, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ICMP
1254 { 161, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ROTL
1255 { 160, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ROTR
1256 { 159, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 103, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSHR
1257 { 158, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 103, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSHL
1258 { 157, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASHR
1259 { 156, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LSHR
1260 { 155, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SHL
1261 { 154, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ZEXT
1262 { 153, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SEXT_INREG
1263 { 152, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SEXT
1264 { 151, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 97, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VAARG
1265 { 150, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VASTART
1266 { 149, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCONSTANT
1267 { 148, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONSTANT
1268 { 147, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC_USAT_U
1269 { 146, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC_SSAT_U
1270 { 145, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC_SSAT_S
1271 { 144, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC
1272 { 143, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ANYEXT
1273 { 142, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
1274 { 141, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_INTRINSIC_CONVERGENT
1275 { 140, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_W_SIDE_EFFECTS
1276 { 139, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC
1277 { 138, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INVOKE_REGION_START
1278 { 137, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BRINDIRECT
1279 { 136, 2, 0, 0, 0, 0, 0, MSP430OpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BRCOND
1280 { 135, 4, 0, 0, 0, 0, 0, MSP430OpInfoBase + 93, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PREFETCH
1281 { 134, 2, 0, 0, 0, 0, 0, MSP430OpInfoBase + 20, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FENCE
1282 { 133, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_USUB_SAT
1283 { 132, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_USUB_COND
1284 { 131, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UDEC_WRAP
1285 { 130, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UINC_WRAP
1286 { 129, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMINIMUMNUM
1287 { 128, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMAXIMUMNUM
1288 { 127, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMINIMUM
1289 { 126, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMAXIMUM
1290 { 125, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMIN
1291 { 124, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMAX
1292 { 123, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FSUB
1293 { 122, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FADD
1294 { 121, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UMIN
1295 { 120, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UMAX
1296 { 119, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_MIN
1297 { 118, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_MAX
1298 { 117, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_XOR
1299 { 116, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_OR
1300 { 115, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_NAND
1301 { 114, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_AND
1302 { 113, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_SUB
1303 { 112, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_ADD
1304 { 111, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_XCHG
1305 { 110, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMIC_CMPXCHG
1306 { 109, 5, 2, 0, 0, 0, 0, MSP430OpInfoBase + 81, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
1307 { 108, 5, 1, 0, 0, 0, 0, MSP430OpInfoBase + 76, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_STORE
1308 { 107, 2, 0, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTRUNCSTORE
1309 { 106, 2, 0, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STORE
1310 { 105, 5, 2, 0, 0, 0, 0, MSP430OpInfoBase + 71, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_ZEXTLOAD
1311 { 104, 5, 2, 0, 0, 0, 0, MSP430OpInfoBase + 71, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_SEXTLOAD
1312 { 103, 5, 2, 0, 0, 0, 0, MSP430OpInfoBase + 71, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_LOAD
1313 { 102, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPEXTLOAD
1314 { 101, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ZEXTLOAD
1315 { 100, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SEXTLOAD
1316 { 99, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LOAD
1317 { 98, 1, 1, 0, 0, 0, 0, MSP430OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_READSTEADYCOUNTER
1318 { 97, 1, 1, 0, 0, 0, 0, MSP430OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_READCYCLECOUNTER
1319 { 96, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_ROUNDEVEN
1320 { 95, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_LLRINT
1321 { 94, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_LRINT
1322 { 93, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_ROUND
1323 { 92, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_TRUNC
1324 { 91, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 68, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_FPTRUNC_ROUND
1325 { 90, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONSTANT_FOLD_BARRIER
1326 { 89, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FREEZE
1327 { 88, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BITCAST
1328 { 87, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTTOPTR
1329 { 86, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTRTOINT
1330 { 85, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONCAT_VECTORS
1331 { 84, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BUILD_VECTOR_TRUNC
1332 { 83, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BUILD_VECTOR
1333 { 82, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MERGE_VALUES
1334 { 81, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 62, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INSERT
1335 { 80, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UNMERGE_VALUES
1336 { 79, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 57, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_EXTRACT
1337 { 78, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONSTANT_POOL
1338 { 77, 5, 1, 0, 0, 0, 0, MSP430OpInfoBase + 52, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTRAUTH_GLOBAL_VALUE
1339 { 76, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GLOBAL_VALUE
1340 { 75, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FRAME_INDEX
1341 { 74, 1, 1, 0, 0, 0, 0, MSP430OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PHI
1342 { 73, 1, 1, 0, 0, 0, 0, MSP430OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_IMPLICIT_DEF
1343 { 72, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SAVGCEIL
1344 { 71, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SAVGFLOOR
1345 { 70, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UAVGCEIL
1346 { 69, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UAVGFLOOR
1347 { 68, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ABDU
1348 { 67, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ABDS
1349 { 66, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_XOR
1350 { 65, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_OR
1351 { 64, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_AND
1352 { 63, 4, 2, 0, 0, 0, 0, MSP430OpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIVREM
1353 { 62, 4, 2, 0, 0, 0, 0, MSP430OpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIVREM
1354 { 61, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UREM
1355 { 60, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SREM
1356 { 59, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIV
1357 { 58, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIV
1358 { 57, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MUL
1359 { 56, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SUB
1360 { 55, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ADD
1361 { 54, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASSERT_ALIGN
1362 { 53, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASSERT_ZEXT
1363 { 52, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASSERT_SEXT
1364 { 51, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_GLUE
1365 { 50, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_LOOP
1366 { 49, 1, 1, 0, 0, 0, 0, MSP430OpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_ANCHOR
1367 { 48, 1, 1, 0, 0, 0, 0, MSP430OpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_ENTRY
1368 { 47, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RELOC_NONE
1369 { 46, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JUMP_TABLE_DEBUG_INFO
1370 { 45, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMBARRIER
1371 { 44, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FAKE_USE
1372 { 43, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ICALL_BRANCH_FUNNEL
1373 { 42, 3, 0, 0, 0, 0, 0, MSP430OpInfoBase + 36, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_14686
1374 { 41, 2, 0, 0, 0, 0, 0, MSP430OpInfoBase + 34, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_14685
1375 { 40, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_TAIL_CALL
1376 { 39, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_FUNCTION_EXIT
1377 { 38, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_RET
1378 { 37, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_FUNCTION_ENTER
1379 { 36, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_OP
1380 { 35, 1, 1, 0, 0, 0, 0, MSP430OpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FAULTING_OP
1381 { 34, 2, 0, 0, 0, 0, 0, MSP430OpInfoBase + 32, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_ESCAPE
1382 { 33, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STATEPOINT
1383 { 32, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 29, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_14684
1384 { 31, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PREALLOCATED_SETUP
1385 { 30, 1, 1, 0, 0, 0, 0, MSP430OpInfoBase + 28, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_14348
1386 { 29, 6, 1, 0, 0, 0, 0, MSP430OpInfoBase + 22, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHPOINT
1387 { 28, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FENTRY_CALL
1388 { 27, 2, 0, 0, 0, 0, 0, MSP430OpInfoBase + 20, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STACKMAP
1389 { 26, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 18, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARITH_FENCE
1390 { 25, 4, 0, 0, 0, 0, 0, MSP430OpInfoBase + 14, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PSEUDO_PROBE
1391 { 24, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LIFETIME_END
1392 { 23, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LIFETIME_START
1393 { 22, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BUNDLE
1394 { 21, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 11, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_LANEMASK
1395 { 20, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY
1396 { 19, 2, 1, 0, 0, 0, 0, MSP430OpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REG_SEQUENCE
1397 { 18, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_LABEL
1398 { 17, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_PHI
1399 { 16, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_INSTR_REF
1400 { 15, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_VALUE_LIST
1401 { 14, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_VALUE
1402 { 13, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_TO_REGCLASS
1403 { 12, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBREG_TO_REG
1404 { 11, 1, 1, 0, 0, 0, 0, MSP430OpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INIT_UNDEF
1405 { 10, 1, 1, 0, 0, 0, 0, MSP430OpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // IMPLICIT_DEF
1406 { 9, 4, 1, 0, 0, 0, 0, MSP430OpInfoBase + 5, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INSERT_SUBREG
1407 { 8, 3, 1, 0, 0, 0, 0, MSP430OpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTRACT_SUBREG
1408 { 7, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // KILL
1409 { 6, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ANNOTATION_LABEL
1410 { 5, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GC_LABEL
1411 { 4, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EH_LABEL
1412 { 3, 1, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CFI_INSTRUCTION
1413 { 2, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INLINEASM_BR
1414 { 1, 0, 0, 0, 0, 0, 0, MSP430OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INLINEASM
1415 { 0, 1, 1, 0, 0, 0, 0, MSP430OpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PHI
1416 }, {
1417 /* 0 */
1418 /* 0 */ MSP430::SR,
1419 /* 1 */ MSP430::SR, MSP430::SR,
1420 /* 3 */ MSP430::SP, MSP430::SR,
1421 /* 5 */ MSP430::SP, MSP430::SP, MSP430::SR,
1422 /* 8 */ MSP430::SP, MSP430::R11, MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15, MSP430::SR,
1423 /* 15 */ MSP430::SP, MSP430::SP,
1424 }, {
1425 0
1426 }, {
1427 /* 0 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1428 /* 1 */
1429 /* 1 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1430 /* 2 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1431 /* 5 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1432 /* 9 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1433 /* 11 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1434 /* 14 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1435 /* 18 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) },
1436 /* 20 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1437 /* 22 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1438 /* 28 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1439 /* 29 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1440 /* 32 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1441 /* 34 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1442 /* 36 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1443 /* 39 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1444 /* 42 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1445 /* 45 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1446 /* 49 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1447 /* 50 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1448 /* 52 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1449 /* 57 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1450 /* 60 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1451 /* 62 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1452 /* 66 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1453 /* 68 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1454 /* 71 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1455 /* 76 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1456 /* 81 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1457 /* 86 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1458 /* 90 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1459 /* 93 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_2, 0 },
1460 /* 97 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1461 /* 100 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1462 /* 103 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1463 /* 107 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1464 /* 111 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1465 /* 114 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1466 /* 119 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1467 /* 123 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1468 /* 126 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
1469 /* 130 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
1470 /* 133 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1471 /* 137 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1472 /* 141 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1473 /* 143 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1474 /* 147 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1475 /* 151 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1476 /* 154 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1477 /* 157 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1478 /* 161 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 },
1479 /* 164 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1480 /* 167 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1481 /* 170 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1482 /* 173 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1483 /* 177 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 },
1484 /* 180 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(1) },
1485 /* 184 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1486 /* 187 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1487 /* 190 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1488 /* 193 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1489 /* 196 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1490 /* 200 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 },
1491 /* 203 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(1) },
1492 /* 207 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1493 /* 210 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1494 /* 212 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1495 /* 215 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 },
1496 /* 217 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1497 /* 219 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1498 /* 221 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1499 /* 223 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1500 /* 226 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 },
1501 /* 228 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1502 /* 230 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1503 /* 232 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 },
1504 /* 233 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(1) },
1505 /* 236 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(1) },
1506 /* 239 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1507 /* 241 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1508 /* 242 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
1509 /* 244 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
1510 /* 246 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1511 /* 250 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1512 /* 254 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1513 /* 257 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1514 }
1515};
1516
1517
1518#ifdef __GNUC__
1519#pragma GCC diagnostic push
1520#pragma GCC diagnostic ignored "-Woverlength-strings"
1521#endif
1522extern const char MSP430InstrNameData[] = {
1523 /* 0 */ "G_FLOG10\000"
1524 /* 9 */ "G_FEXP10\000"
1525 /* 18 */ "G_FLOG2\000"
1526 /* 26 */ "G_FATAN2\000"
1527 /* 35 */ "G_FEXP2\000"
1528 /* 43 */ "Sra16\000"
1529 /* 49 */ "Rrcl16\000"
1530 /* 56 */ "Shl16\000"
1531 /* 62 */ "Srl16\000"
1532 /* 68 */ "Select16\000"
1533 /* 77 */ "Sra8\000"
1534 /* 82 */ "Rrcl8\000"
1535 /* 88 */ "Shl8\000"
1536 /* 93 */ "Srl8\000"
1537 /* 98 */ "MOVZX16rm8\000"
1538 /* 109 */ "MOVZX16rr8\000"
1539 /* 120 */ "Select8\000"
1540 /* 128 */ "G_FMA\000"
1541 /* 134 */ "G_STRICT_FMA\000"
1542 /* 147 */ "G_FSUB\000"
1543 /* 154 */ "G_STRICT_FSUB\000"
1544 /* 168 */ "G_ATOMICRMW_FSUB\000"
1545 /* 185 */ "G_SUB\000"
1546 /* 191 */ "G_ATOMICRMW_SUB\000"
1547 /* 207 */ "JCC\000"
1548 /* 211 */ "G_INTRINSIC\000"
1549 /* 223 */ "G_FPTRUNC\000"
1550 /* 233 */ "G_INTRINSIC_TRUNC\000"
1551 /* 251 */ "G_TRUNC\000"
1552 /* 259 */ "G_BUILD_VECTOR_TRUNC\000"
1553 /* 280 */ "G_DYN_STACKALLOC\000"
1554 /* 297 */ "G_FMAD\000"
1555 /* 304 */ "G_FPEXTLOAD\000"
1556 /* 316 */ "G_INDEXED_SEXTLOAD\000"
1557 /* 335 */ "G_SEXTLOAD\000"
1558 /* 346 */ "G_INDEXED_ZEXTLOAD\000"
1559 /* 365 */ "G_ZEXTLOAD\000"
1560 /* 376 */ "G_INDEXED_LOAD\000"
1561 /* 391 */ "G_LOAD\000"
1562 /* 398 */ "G_VECREDUCE_FADD\000"
1563 /* 415 */ "G_FADD\000"
1564 /* 422 */ "G_VECREDUCE_SEQ_FADD\000"
1565 /* 443 */ "G_STRICT_FADD\000"
1566 /* 457 */ "G_ATOMICRMW_FADD\000"
1567 /* 474 */ "G_VECREDUCE_ADD\000"
1568 /* 490 */ "G_ADD\000"
1569 /* 496 */ "G_PTR_ADD\000"
1570 /* 506 */ "G_ATOMICRMW_ADD\000"
1571 /* 522 */ "G_ATOMICRMW_NAND\000"
1572 /* 539 */ "G_VECREDUCE_AND\000"
1573 /* 555 */ "G_AND\000"
1574 /* 561 */ "G_ATOMICRMW_AND\000"
1575 /* 577 */ "LIFETIME_END\000"
1576 /* 590 */ "G_BRCOND\000"
1577 /* 599 */ "G_ATOMICRMW_USUB_COND\000"
1578 /* 621 */ "G_LLROUND\000"
1579 /* 631 */ "G_LROUND\000"
1580 /* 640 */ "G_INTRINSIC_ROUND\000"
1581 /* 658 */ "G_INTRINSIC_FPTRUNC_ROUND\000"
1582 /* 684 */ "LOAD_STACK_GUARD\000"
1583 /* 701 */ "PSEUDO_PROBE\000"
1584 /* 714 */ "G_SSUBE\000"
1585 /* 722 */ "G_USUBE\000"
1586 /* 730 */ "G_FENCE\000"
1587 /* 738 */ "ARITH_FENCE\000"
1588 /* 750 */ "REG_SEQUENCE\000"
1589 /* 763 */ "G_SADDE\000"
1590 /* 771 */ "G_UADDE\000"
1591 /* 779 */ "G_GET_FPMODE\000"
1592 /* 792 */ "G_RESET_FPMODE\000"
1593 /* 807 */ "G_SET_FPMODE\000"
1594 /* 820 */ "G_FMINNUM_IEEE\000"
1595 /* 835 */ "G_FMAXNUM_IEEE\000"
1596 /* 850 */ "G_VSCALE\000"
1597 /* 859 */ "G_JUMP_TABLE\000"
1598 /* 872 */ "BUNDLE\000"
1599 /* 879 */ "G_MEMSET_INLINE\000"
1600 /* 895 */ "G_MEMCPY_INLINE\000"
1601 /* 911 */ "RELOC_NONE\000"
1602 /* 922 */ "LOCAL_ESCAPE\000"
1603 /* 935 */ "G_FPTRUNCSTORE\000"
1604 /* 950 */ "G_STACKRESTORE\000"
1605 /* 965 */ "G_INDEXED_STORE\000"
1606 /* 981 */ "G_STORE\000"
1607 /* 989 */ "G_BITREVERSE\000"
1608 /* 1002 */ "FAKE_USE\000"
1609 /* 1011 */ "DBG_VALUE\000"
1610 /* 1021 */ "G_GLOBAL_VALUE\000"
1611 /* 1036 */ "G_PTRAUTH_GLOBAL_VALUE\000"
1612 /* 1059 */ "CONVERGENCECTRL_GLUE\000"
1613 /* 1080 */ "G_STACKSAVE\000"
1614 /* 1092 */ "G_MEMMOVE\000"
1615 /* 1102 */ "G_FREEZE\000"
1616 /* 1111 */ "G_FCANONICALIZE\000"
1617 /* 1127 */ "G_FMODF\000"
1618 /* 1135 */ "INIT_UNDEF\000"
1619 /* 1146 */ "G_IMPLICIT_DEF\000"
1620 /* 1161 */ "DBG_INSTR_REF\000"
1621 /* 1175 */ "G_FNEG\000"
1622 /* 1182 */ "EXTRACT_SUBREG\000"
1623 /* 1197 */ "INSERT_SUBREG\000"
1624 /* 1211 */ "G_SEXT_INREG\000"
1625 /* 1224 */ "SUBREG_TO_REG\000"
1626 /* 1238 */ "G_ATOMIC_CMPXCHG\000"
1627 /* 1255 */ "G_ATOMICRMW_XCHG\000"
1628 /* 1272 */ "G_GET_ROUNDING\000"
1629 /* 1287 */ "G_SET_ROUNDING\000"
1630 /* 1302 */ "G_FLOG\000"
1631 /* 1309 */ "G_VAARG\000"
1632 /* 1317 */ "PREALLOCATED_ARG\000"
1633 /* 1334 */ "G_PREFETCH\000"
1634 /* 1345 */ "G_CLMULH\000"
1635 /* 1354 */ "G_SMULH\000"
1636 /* 1362 */ "G_UMULH\000"
1637 /* 1370 */ "G_FTANH\000"
1638 /* 1378 */ "G_FSINH\000"
1639 /* 1386 */ "G_FCOSH\000"
1640 /* 1394 */ "DBG_PHI\000"
1641 /* 1402 */ "G_FPTOSI\000"
1642 /* 1411 */ "RETI\000"
1643 /* 1416 */ "G_FPTOUI\000"
1644 /* 1425 */ "G_FPOWI\000"
1645 /* 1433 */ "COPY_LANEMASK\000"
1646 /* 1447 */ "G_PTRMASK\000"
1647 /* 1457 */ "GC_LABEL\000"
1648 /* 1466 */ "DBG_LABEL\000"
1649 /* 1476 */ "EH_LABEL\000"
1650 /* 1485 */ "ANNOTATION_LABEL\000"
1651 /* 1502 */ "ICALL_BRANCH_FUNNEL\000"
1652 /* 1522 */ "G_FSHL\000"
1653 /* 1529 */ "G_SHL\000"
1654 /* 1535 */ "G_FCEIL\000"
1655 /* 1543 */ "G_SAVGCEIL\000"
1656 /* 1554 */ "G_UAVGCEIL\000"
1657 /* 1565 */ "PATCHABLE_TAIL_CALL\000"
1658 /* 1585 */ "PATCHABLE_TYPED_EVENT_CALL\000"
1659 /* 1612 */ "PATCHABLE_EVENT_CALL\000"
1660 /* 1633 */ "FENTRY_CALL\000"
1661 /* 1645 */ "KILL\000"
1662 /* 1650 */ "G_CONSTANT_POOL\000"
1663 /* 1666 */ "G_ROTL\000"
1664 /* 1673 */ "G_VECREDUCE_FMUL\000"
1665 /* 1690 */ "G_FMUL\000"
1666 /* 1697 */ "G_VECREDUCE_SEQ_FMUL\000"
1667 /* 1718 */ "G_STRICT_FMUL\000"
1668 /* 1732 */ "G_CLMUL\000"
1669 /* 1740 */ "G_VECREDUCE_MUL\000"
1670 /* 1756 */ "G_MUL\000"
1671 /* 1762 */ "G_FREM\000"
1672 /* 1769 */ "G_STRICT_FREM\000"
1673 /* 1783 */ "G_SREM\000"
1674 /* 1790 */ "G_UREM\000"
1675 /* 1797 */ "G_SDIVREM\000"
1676 /* 1807 */ "G_UDIVREM\000"
1677 /* 1817 */ "INLINEASM\000"
1678 /* 1827 */ "G_VECREDUCE_FMINIMUM\000"
1679 /* 1848 */ "G_FMINIMUM\000"
1680 /* 1859 */ "G_ATOMICRMW_FMINIMUM\000"
1681 /* 1880 */ "G_VECREDUCE_FMAXIMUM\000"
1682 /* 1901 */ "G_FMAXIMUM\000"
1683 /* 1912 */ "G_ATOMICRMW_FMAXIMUM\000"
1684 /* 1933 */ "G_VECREDUCE_FMINIMUMNUM\000"
1685 /* 1957 */ "G_FMINIMUMNUM\000"
1686 /* 1971 */ "G_ATOMICRMW_FMINIMUMNUM\000"
1687 /* 1995 */ "G_VECREDUCE_FMAXIMUMNUM\000"
1688 /* 2019 */ "G_FMAXIMUMNUM\000"
1689 /* 2033 */ "G_ATOMICRMW_FMAXIMUMNUM\000"
1690 /* 2057 */ "G_FMINNUM\000"
1691 /* 2067 */ "G_FMAXNUM\000"
1692 /* 2077 */ "G_FATAN\000"
1693 /* 2085 */ "G_FTAN\000"
1694 /* 2092 */ "G_INTRINSIC_ROUNDEVEN\000"
1695 /* 2114 */ "G_ASSERT_ALIGN\000"
1696 /* 2129 */ "G_FCOPYSIGN\000"
1697 /* 2141 */ "G_VECREDUCE_FMIN\000"
1698 /* 2158 */ "G_ATOMICRMW_FMIN\000"
1699 /* 2175 */ "G_VECREDUCE_SMIN\000"
1700 /* 2192 */ "G_SMIN\000"
1701 /* 2199 */ "G_VECREDUCE_UMIN\000"
1702 /* 2216 */ "G_UMIN\000"
1703 /* 2223 */ "G_ATOMICRMW_UMIN\000"
1704 /* 2240 */ "G_ATOMICRMW_MIN\000"
1705 /* 2256 */ "G_FASIN\000"
1706 /* 2264 */ "G_FSIN\000"
1707 /* 2271 */ "CFI_INSTRUCTION\000"
1708 /* 2287 */ "G_CTLZ_ZERO_POISON\000"
1709 /* 2306 */ "G_CTTZ_ZERO_POISON\000"
1710 /* 2325 */ "ADJCALLSTACKDOWN\000"
1711 /* 2342 */ "G_SSUBO\000"
1712 /* 2350 */ "G_USUBO\000"
1713 /* 2358 */ "G_SADDO\000"
1714 /* 2366 */ "G_UADDO\000"
1715 /* 2374 */ "JUMP_TABLE_DEBUG_INFO\000"
1716 /* 2396 */ "G_SMULO\000"
1717 /* 2404 */ "G_UMULO\000"
1718 /* 2412 */ "G_BZERO\000"
1719 /* 2420 */ "STACKMAP\000"
1720 /* 2429 */ "G_DEBUGTRAP\000"
1721 /* 2441 */ "G_UBSANTRAP\000"
1722 /* 2453 */ "G_TRAP\000"
1723 /* 2460 */ "G_ATOMICRMW_UDEC_WRAP\000"
1724 /* 2482 */ "G_ATOMICRMW_UINC_WRAP\000"
1725 /* 2504 */ "G_BSWAP\000"
1726 /* 2512 */ "G_SITOFP\000"
1727 /* 2521 */ "G_UITOFP\000"
1728 /* 2530 */ "G_FCMP\000"
1729 /* 2537 */ "G_STRICT_FCMP\000"
1730 /* 2551 */ "G_ICMP\000"
1731 /* 2558 */ "G_SCMP\000"
1732 /* 2565 */ "G_UCMP\000"
1733 /* 2572 */ "JMP\000"
1734 /* 2576 */ "CONVERGENCECTRL_LOOP\000"
1735 /* 2597 */ "G_CTPOP\000"
1736 /* 2605 */ "PATCHABLE_OP\000"
1737 /* 2618 */ "FAULTING_OP\000"
1738 /* 2630 */ "ADJCALLSTACKUP\000"
1739 /* 2645 */ "PREALLOCATED_SETUP\000"
1740 /* 2664 */ "G_FLDEXP\000"
1741 /* 2673 */ "G_STRICT_FLDEXP\000"
1742 /* 2689 */ "G_FEXP\000"
1743 /* 2696 */ "G_FFREXP\000"
1744 /* 2705 */ "G_BR\000"
1745 /* 2710 */ "INLINEASM_BR\000"
1746 /* 2723 */ "G_BLOCK_ADDR\000"
1747 /* 2736 */ "MEMBARRIER\000"
1748 /* 2747 */ "G_CONSTANT_FOLD_BARRIER\000"
1749 /* 2771 */ "PATCHABLE_FUNCTION_ENTER\000"
1750 /* 2796 */ "G_READCYCLECOUNTER\000"
1751 /* 2815 */ "G_READSTEADYCOUNTER\000"
1752 /* 2835 */ "G_READ_REGISTER\000"
1753 /* 2851 */ "G_WRITE_REGISTER\000"
1754 /* 2868 */ "G_ASHR\000"
1755 /* 2875 */ "G_FSHR\000"
1756 /* 2882 */ "G_LSHR\000"
1757 /* 2889 */ "CONVERGENCECTRL_ANCHOR\000"
1758 /* 2912 */ "G_FFLOOR\000"
1759 /* 2921 */ "G_SAVGFLOOR\000"
1760 /* 2933 */ "G_UAVGFLOOR\000"
1761 /* 2945 */ "G_EXTRACT_SUBVECTOR\000"
1762 /* 2965 */ "G_INSERT_SUBVECTOR\000"
1763 /* 2984 */ "G_BUILD_VECTOR\000"
1764 /* 2999 */ "G_SHUFFLE_VECTOR\000"
1765 /* 3016 */ "G_STEP_VECTOR\000"
1766 /* 3030 */ "G_SPLAT_VECTOR\000"
1767 /* 3045 */ "G_VECREDUCE_XOR\000"
1768 /* 3061 */ "G_XOR\000"
1769 /* 3067 */ "G_ATOMICRMW_XOR\000"
1770 /* 3083 */ "G_VECREDUCE_OR\000"
1771 /* 3098 */ "G_OR\000"
1772 /* 3103 */ "G_ATOMICRMW_OR\000"
1773 /* 3118 */ "G_ROTR\000"
1774 /* 3125 */ "G_INTTOPTR\000"
1775 /* 3136 */ "G_FABS\000"
1776 /* 3143 */ "G_ABS\000"
1777 /* 3149 */ "G_ABDS\000"
1778 /* 3156 */ "G_UNMERGE_VALUES\000"
1779 /* 3173 */ "G_MERGE_VALUES\000"
1780 /* 3188 */ "G_CTLS\000"
1781 /* 3195 */ "G_FACOS\000"
1782 /* 3203 */ "G_FCOS\000"
1783 /* 3210 */ "G_FSINCOS\000"
1784 /* 3220 */ "G_STRICT_FCMPS\000"
1785 /* 3235 */ "G_CONCAT_VECTORS\000"
1786 /* 3252 */ "COPY_TO_REGCLASS\000"
1787 /* 3269 */ "G_IS_FPCLASS\000"
1788 /* 3282 */ "G_ATOMIC_CMPXCHG_WITH_SUCCESS\000"
1789 /* 3312 */ "G_VECTOR_COMPRESS\000"
1790 /* 3330 */ "G_INTRINSIC_W_SIDE_EFFECTS\000"
1791 /* 3357 */ "G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS\000"
1792 /* 3395 */ "G_TRUNC_SSAT_S\000"
1793 /* 3410 */ "G_SSUBSAT\000"
1794 /* 3420 */ "G_USUBSAT\000"
1795 /* 3430 */ "G_SADDSAT\000"
1796 /* 3440 */ "G_UADDSAT\000"
1797 /* 3450 */ "G_SSHLSAT\000"
1798 /* 3460 */ "G_USHLSAT\000"
1799 /* 3470 */ "G_SMULFIXSAT\000"
1800 /* 3483 */ "G_UMULFIXSAT\000"
1801 /* 3496 */ "G_SDIVFIXSAT\000"
1802 /* 3509 */ "G_UDIVFIXSAT\000"
1803 /* 3522 */ "G_ATOMICRMW_USUB_SAT\000"
1804 /* 3543 */ "G_FPTOSI_SAT\000"
1805 /* 3556 */ "G_FPTOUI_SAT\000"
1806 /* 3569 */ "G_EXTRACT\000"
1807 /* 3579 */ "G_SELECT\000"
1808 /* 3588 */ "G_BRINDIRECT\000"
1809 /* 3601 */ "PATCHABLE_RET\000"
1810 /* 3615 */ "G_MEMSET\000"
1811 /* 3624 */ "PATCHABLE_FUNCTION_EXIT\000"
1812 /* 3648 */ "G_BRJT\000"
1813 /* 3655 */ "G_EXTRACT_VECTOR_ELT\000"
1814 /* 3676 */ "G_INSERT_VECTOR_ELT\000"
1815 /* 3696 */ "G_FCONSTANT\000"
1816 /* 3708 */ "G_CONSTANT\000"
1817 /* 3719 */ "G_INTRINSIC_CONVERGENT\000"
1818 /* 3742 */ "STATEPOINT\000"
1819 /* 3753 */ "PATCHPOINT\000"
1820 /* 3764 */ "G_PTRTOINT\000"
1821 /* 3775 */ "G_FRINT\000"
1822 /* 3783 */ "G_INTRINSIC_LLRINT\000"
1823 /* 3802 */ "G_INTRINSIC_LRINT\000"
1824 /* 3820 */ "G_FNEARBYINT\000"
1825 /* 3833 */ "G_VASTART\000"
1826 /* 3843 */ "LIFETIME_START\000"
1827 /* 3858 */ "G_INVOKE_REGION_START\000"
1828 /* 3880 */ "G_INSERT\000"
1829 /* 3889 */ "G_FSQRT\000"
1830 /* 3897 */ "G_STRICT_FSQRT\000"
1831 /* 3912 */ "G_BITCAST\000"
1832 /* 3922 */ "G_ADDRSPACE_CAST\000"
1833 /* 3939 */ "DBG_VALUE_LIST\000"
1834 /* 3954 */ "G_FPEXT\000"
1835 /* 3962 */ "G_SEXT\000"
1836 /* 3969 */ "G_ASSERT_SEXT\000"
1837 /* 3983 */ "G_ANYEXT\000"
1838 /* 3992 */ "G_ZEXT\000"
1839 /* 3999 */ "G_ASSERT_ZEXT\000"
1840 /* 4013 */ "G_ABDU\000"
1841 /* 4020 */ "G_TRUNC_SSAT_U\000"
1842 /* 4035 */ "G_TRUNC_USAT_U\000"
1843 /* 4050 */ "G_FDIV\000"
1844 /* 4057 */ "G_STRICT_FDIV\000"
1845 /* 4071 */ "G_SDIV\000"
1846 /* 4078 */ "G_UDIV\000"
1847 /* 4085 */ "G_GET_FPENV\000"
1848 /* 4097 */ "G_RESET_FPENV\000"
1849 /* 4111 */ "G_SET_FPENV\000"
1850 /* 4123 */ "G_FPOW\000"
1851 /* 4130 */ "G_VECREDUCE_FMAX\000"
1852 /* 4147 */ "G_ATOMICRMW_FMAX\000"
1853 /* 4164 */ "G_VECREDUCE_SMAX\000"
1854 /* 4181 */ "G_SMAX\000"
1855 /* 4188 */ "G_VECREDUCE_UMAX\000"
1856 /* 4205 */ "G_UMAX\000"
1857 /* 4212 */ "G_ATOMICRMW_UMAX\000"
1858 /* 4229 */ "G_ATOMICRMW_MAX\000"
1859 /* 4245 */ "G_FRAME_INDEX\000"
1860 /* 4259 */ "G_SBFX\000"
1861 /* 4266 */ "G_UBFX\000"
1862 /* 4273 */ "G_SMULFIX\000"
1863 /* 4283 */ "G_UMULFIX\000"
1864 /* 4293 */ "G_SDIVFIX\000"
1865 /* 4303 */ "G_UDIVFIX\000"
1866 /* 4313 */ "G_MEMCPY\000"
1867 /* 4322 */ "COPY\000"
1868 /* 4327 */ "CONVERGENCECTRL_ENTRY\000"
1869 /* 4349 */ "G_CTLZ\000"
1870 /* 4356 */ "G_CTTZ\000"
1871 /* 4363 */ "PUSH16c\000"
1872 /* 4371 */ "SUB16mc\000"
1873 /* 4379 */ "SUBC16mc\000"
1874 /* 4388 */ "ADDC16mc\000"
1875 /* 4397 */ "BIC16mc\000"
1876 /* 4405 */ "DADD16mc\000"
1877 /* 4414 */ "AND16mc\000"
1878 /* 4422 */ "CMP16mc\000"
1879 /* 4430 */ "XOR16mc\000"
1880 /* 4438 */ "BIS16mc\000"
1881 /* 4446 */ "BIT16mc\000"
1882 /* 4454 */ "MOV16mc\000"
1883 /* 4462 */ "SUB8mc\000"
1884 /* 4469 */ "SUBC8mc\000"
1885 /* 4477 */ "ADDC8mc\000"
1886 /* 4485 */ "BIC8mc\000"
1887 /* 4492 */ "DADD8mc\000"
1888 /* 4500 */ "AND8mc\000"
1889 /* 4507 */ "CMP8mc\000"
1890 /* 4514 */ "XOR8mc\000"
1891 /* 4521 */ "BIS8mc\000"
1892 /* 4528 */ "BIT8mc\000"
1893 /* 4535 */ "MOV8mc\000"
1894 /* 4542 */ "SUB16rc\000"
1895 /* 4550 */ "SUBC16rc\000"
1896 /* 4559 */ "ADDC16rc\000"
1897 /* 4568 */ "BIC16rc\000"
1898 /* 4576 */ "DADD16rc\000"
1899 /* 4585 */ "AND16rc\000"
1900 /* 4593 */ "CMP16rc\000"
1901 /* 4601 */ "XOR16rc\000"
1902 /* 4609 */ "BIS16rc\000"
1903 /* 4617 */ "BIT16rc\000"
1904 /* 4625 */ "MOV16rc\000"
1905 /* 4633 */ "SUB8rc\000"
1906 /* 4640 */ "SUBC8rc\000"
1907 /* 4648 */ "ADDC8rc\000"
1908 /* 4656 */ "BIC8rc\000"
1909 /* 4663 */ "DADD8rc\000"
1910 /* 4671 */ "AND8rc\000"
1911 /* 4678 */ "CMP8rc\000"
1912 /* 4685 */ "XOR8rc\000"
1913 /* 4692 */ "BIS8rc\000"
1914 /* 4699 */ "BIT8rc\000"
1915 /* 4706 */ "MOV8rc\000"
1916 /* 4713 */ "ADDframe\000"
1917 /* 4722 */ "PUSH16i\000"
1918 /* 4730 */ "Bi\000"
1919 /* 4733 */ "CALLi\000"
1920 /* 4739 */ "SUB16mi\000"
1921 /* 4747 */ "SUBC16mi\000"
1922 /* 4756 */ "ADDC16mi\000"
1923 /* 4765 */ "BIC16mi\000"
1924 /* 4773 */ "DADD16mi\000"
1925 /* 4782 */ "AND16mi\000"
1926 /* 4790 */ "CMP16mi\000"
1927 /* 4798 */ "XOR16mi\000"
1928 /* 4806 */ "BIS16mi\000"
1929 /* 4814 */ "BIT16mi\000"
1930 /* 4822 */ "MOV16mi\000"
1931 /* 4830 */ "SUB8mi\000"
1932 /* 4837 */ "SUBC8mi\000"
1933 /* 4845 */ "ADDC8mi\000"
1934 /* 4853 */ "BIC8mi\000"
1935 /* 4860 */ "DADD8mi\000"
1936 /* 4868 */ "AND8mi\000"
1937 /* 4875 */ "CMP8mi\000"
1938 /* 4882 */ "XOR8mi\000"
1939 /* 4889 */ "BIS8mi\000"
1940 /* 4896 */ "BIT8mi\000"
1941 /* 4903 */ "MOV8mi\000"
1942 /* 4910 */ "SUB16ri\000"
1943 /* 4918 */ "SUBC16ri\000"
1944 /* 4927 */ "ADDC16ri\000"
1945 /* 4936 */ "BIC16ri\000"
1946 /* 4944 */ "DADD16ri\000"
1947 /* 4953 */ "AND16ri\000"
1948 /* 4961 */ "CMP16ri\000"
1949 /* 4969 */ "XOR16ri\000"
1950 /* 4977 */ "BIS16ri\000"
1951 /* 4985 */ "BIT16ri\000"
1952 /* 4993 */ "MOV16ri\000"
1953 /* 5001 */ "SUB8ri\000"
1954 /* 5008 */ "SUBC8ri\000"
1955 /* 5016 */ "ADDC8ri\000"
1956 /* 5024 */ "BIC8ri\000"
1957 /* 5031 */ "DADD8ri\000"
1958 /* 5039 */ "AND8ri\000"
1959 /* 5046 */ "CMP8ri\000"
1960 /* 5053 */ "XOR8ri\000"
1961 /* 5060 */ "BIS8ri\000"
1962 /* 5067 */ "BIT8ri\000"
1963 /* 5074 */ "MOV8ri\000"
1964 /* 5081 */ "RRA16m\000"
1965 /* 5088 */ "SWPB16m\000"
1966 /* 5096 */ "RRC16m\000"
1967 /* 5103 */ "SEXT16m\000"
1968 /* 5111 */ "RRA8m\000"
1969 /* 5117 */ "RRC8m\000"
1970 /* 5123 */ "Bm\000"
1971 /* 5126 */ "CALLm\000"
1972 /* 5132 */ "SUB16mm\000"
1973 /* 5140 */ "SUBC16mm\000"
1974 /* 5149 */ "ADDC16mm\000"
1975 /* 5158 */ "BIC16mm\000"
1976 /* 5166 */ "DADD16mm\000"
1977 /* 5175 */ "AND16mm\000"
1978 /* 5183 */ "CMP16mm\000"
1979 /* 5191 */ "XOR16mm\000"
1980 /* 5199 */ "BIS16mm\000"
1981 /* 5207 */ "BIT16mm\000"
1982 /* 5215 */ "MOV16mm\000"
1983 /* 5223 */ "SUB8mm\000"
1984 /* 5230 */ "SUBC8mm\000"
1985 /* 5238 */ "ADDC8mm\000"
1986 /* 5246 */ "BIC8mm\000"
1987 /* 5253 */ "DADD8mm\000"
1988 /* 5261 */ "AND8mm\000"
1989 /* 5268 */ "CMP8mm\000"
1990 /* 5275 */ "XOR8mm\000"
1991 /* 5282 */ "BIS8mm\000"
1992 /* 5289 */ "BIT8mm\000"
1993 /* 5296 */ "MOV8mm\000"
1994 /* 5303 */ "SUB16rm\000"
1995 /* 5311 */ "SUBC16rm\000"
1996 /* 5320 */ "ADDC16rm\000"
1997 /* 5329 */ "BIC16rm\000"
1998 /* 5337 */ "DADD16rm\000"
1999 /* 5346 */ "AND16rm\000"
2000 /* 5354 */ "CMP16rm\000"
2001 /* 5362 */ "XOR16rm\000"
2002 /* 5370 */ "BIS16rm\000"
2003 /* 5378 */ "BIT16rm\000"
2004 /* 5386 */ "MOV16rm\000"
2005 /* 5394 */ "SUB8rm\000"
2006 /* 5401 */ "SUBC8rm\000"
2007 /* 5409 */ "ADDC8rm\000"
2008 /* 5417 */ "BIC8rm\000"
2009 /* 5424 */ "DADD8rm\000"
2010 /* 5432 */ "AND8rm\000"
2011 /* 5439 */ "CMP8rm\000"
2012 /* 5446 */ "XOR8rm\000"
2013 /* 5453 */ "BIS8rm\000"
2014 /* 5460 */ "BIT8rm\000"
2015 /* 5467 */ "MOV8rm\000"
2016 /* 5474 */ "RRA16n\000"
2017 /* 5481 */ "SWPB16n\000"
2018 /* 5489 */ "RRC16n\000"
2019 /* 5496 */ "SEXT16n\000"
2020 /* 5504 */ "RRA8n\000"
2021 /* 5510 */ "RRC8n\000"
2022 /* 5516 */ "CALLn\000"
2023 /* 5522 */ "SUB16mn\000"
2024 /* 5530 */ "SUBC16mn\000"
2025 /* 5539 */ "ADDC16mn\000"
2026 /* 5548 */ "BIC16mn\000"
2027 /* 5556 */ "DADD16mn\000"
2028 /* 5565 */ "AND16mn\000"
2029 /* 5573 */ "CMP16mn\000"
2030 /* 5581 */ "XOR16mn\000"
2031 /* 5589 */ "BIS16mn\000"
2032 /* 5597 */ "BIT16mn\000"
2033 /* 5605 */ "MOV16mn\000"
2034 /* 5613 */ "SUB8mn\000"
2035 /* 5620 */ "SUBC8mn\000"
2036 /* 5628 */ "ADDC8mn\000"
2037 /* 5636 */ "BIC8mn\000"
2038 /* 5643 */ "DADD8mn\000"
2039 /* 5651 */ "AND8mn\000"
2040 /* 5658 */ "CMP8mn\000"
2041 /* 5665 */ "XOR8mn\000"
2042 /* 5672 */ "BIS8mn\000"
2043 /* 5679 */ "BIT8mn\000"
2044 /* 5686 */ "MOV8mn\000"
2045 /* 5693 */ "SUB16rn\000"
2046 /* 5701 */ "SUBC16rn\000"
2047 /* 5710 */ "ADDC16rn\000"
2048 /* 5719 */ "BIC16rn\000"
2049 /* 5727 */ "DADD16rn\000"
2050 /* 5736 */ "AND16rn\000"
2051 /* 5744 */ "CMP16rn\000"
2052 /* 5752 */ "XOR16rn\000"
2053 /* 5760 */ "BIS16rn\000"
2054 /* 5768 */ "BIT16rn\000"
2055 /* 5776 */ "MOV16rn\000"
2056 /* 5784 */ "SUB8rn\000"
2057 /* 5791 */ "SUBC8rn\000"
2058 /* 5799 */ "ADDC8rn\000"
2059 /* 5807 */ "BIC8rn\000"
2060 /* 5814 */ "DADD8rn\000"
2061 /* 5822 */ "AND8rn\000"
2062 /* 5829 */ "CMP8rn\000"
2063 /* 5836 */ "XOR8rn\000"
2064 /* 5843 */ "BIS8rn\000"
2065 /* 5850 */ "BIT8rn\000"
2066 /* 5857 */ "MOV8rn\000"
2067 /* 5864 */ "RRA16p\000"
2068 /* 5871 */ "SWPB16p\000"
2069 /* 5879 */ "RRC16p\000"
2070 /* 5886 */ "SEXT16p\000"
2071 /* 5894 */ "RRA8p\000"
2072 /* 5900 */ "RRC8p\000"
2073 /* 5906 */ "CALLp\000"
2074 /* 5912 */ "SUB16mp\000"
2075 /* 5920 */ "SUBC16mp\000"
2076 /* 5929 */ "ADDC16mp\000"
2077 /* 5938 */ "BIC16mp\000"
2078 /* 5946 */ "DADD16mp\000"
2079 /* 5955 */ "AND16mp\000"
2080 /* 5963 */ "CMP16mp\000"
2081 /* 5971 */ "XOR16mp\000"
2082 /* 5979 */ "BIS16mp\000"
2083 /* 5987 */ "BIT16mp\000"
2084 /* 5995 */ "SUB8mp\000"
2085 /* 6002 */ "SUBC8mp\000"
2086 /* 6010 */ "ADDC8mp\000"
2087 /* 6018 */ "BIC8mp\000"
2088 /* 6025 */ "DADD8mp\000"
2089 /* 6033 */ "AND8mp\000"
2090 /* 6040 */ "CMP8mp\000"
2091 /* 6047 */ "XOR8mp\000"
2092 /* 6054 */ "BIS8mp\000"
2093 /* 6061 */ "BIT8mp\000"
2094 /* 6068 */ "SUB16rp\000"
2095 /* 6076 */ "SUBC16rp\000"
2096 /* 6085 */ "ADDC16rp\000"
2097 /* 6094 */ "BIC16rp\000"
2098 /* 6102 */ "DADD16rp\000"
2099 /* 6111 */ "AND16rp\000"
2100 /* 6119 */ "CMP16rp\000"
2101 /* 6127 */ "XOR16rp\000"
2102 /* 6135 */ "BIS16rp\000"
2103 /* 6143 */ "BIT16rp\000"
2104 /* 6151 */ "MOV16rp\000"
2105 /* 6159 */ "SUB8rp\000"
2106 /* 6166 */ "SUBC8rp\000"
2107 /* 6174 */ "ADDC8rp\000"
2108 /* 6182 */ "BIC8rp\000"
2109 /* 6189 */ "DADD8rp\000"
2110 /* 6197 */ "AND8rp\000"
2111 /* 6204 */ "CMP8rp\000"
2112 /* 6211 */ "XOR8rp\000"
2113 /* 6218 */ "BIS8rp\000"
2114 /* 6225 */ "BIT8rp\000"
2115 /* 6232 */ "MOV8rp\000"
2116 /* 6239 */ "RRA16r\000"
2117 /* 6246 */ "SWPB16r\000"
2118 /* 6254 */ "RRC16r\000"
2119 /* 6261 */ "PUSH16r\000"
2120 /* 6269 */ "POP16r\000"
2121 /* 6276 */ "SEXT16r\000"
2122 /* 6284 */ "ZEXT16r\000"
2123 /* 6292 */ "RRA8r\000"
2124 /* 6298 */ "RRC8r\000"
2125 /* 6304 */ "PUSH8r\000"
2126 /* 6311 */ "Br\000"
2127 /* 6314 */ "CALLr\000"
2128 /* 6320 */ "SUB16mr\000"
2129 /* 6328 */ "SUBC16mr\000"
2130 /* 6337 */ "ADDC16mr\000"
2131 /* 6346 */ "BIC16mr\000"
2132 /* 6354 */ "DADD16mr\000"
2133 /* 6363 */ "AND16mr\000"
2134 /* 6371 */ "CMP16mr\000"
2135 /* 6379 */ "XOR16mr\000"
2136 /* 6387 */ "BIS16mr\000"
2137 /* 6395 */ "BIT16mr\000"
2138 /* 6403 */ "MOV16mr\000"
2139 /* 6411 */ "SUB8mr\000"
2140 /* 6418 */ "SUBC8mr\000"
2141 /* 6426 */ "ADDC8mr\000"
2142 /* 6434 */ "BIC8mr\000"
2143 /* 6441 */ "DADD8mr\000"
2144 /* 6449 */ "AND8mr\000"
2145 /* 6456 */ "CMP8mr\000"
2146 /* 6463 */ "XOR8mr\000"
2147 /* 6470 */ "BIS8mr\000"
2148 /* 6477 */ "BIT8mr\000"
2149 /* 6484 */ "MOV8mr\000"
2150 /* 6491 */ "SUB16rr\000"
2151 /* 6499 */ "SUBC16rr\000"
2152 /* 6508 */ "ADDC16rr\000"
2153 /* 6517 */ "BIC16rr\000"
2154 /* 6525 */ "DADD16rr\000"
2155 /* 6534 */ "AND16rr\000"
2156 /* 6542 */ "CMP16rr\000"
2157 /* 6550 */ "XOR16rr\000"
2158 /* 6558 */ "BIS16rr\000"
2159 /* 6566 */ "BIT16rr\000"
2160 /* 6574 */ "MOV16rr\000"
2161 /* 6582 */ "SUB8rr\000"
2162 /* 6589 */ "SUBC8rr\000"
2163 /* 6597 */ "ADDC8rr\000"
2164 /* 6605 */ "BIC8rr\000"
2165 /* 6612 */ "DADD8rr\000"
2166 /* 6620 */ "AND8rr\000"
2167 /* 6627 */ "CMP8rr\000"
2168 /* 6634 */ "XOR8rr\000"
2169 /* 6641 */ "BIS8rr\000"
2170 /* 6648 */ "BIT8rr\000"
2171 /* 6655 */ "MOV8rr\000"
2172};
2173#ifdef __GNUC__
2174#pragma GCC diagnostic pop
2175#endif
2176
2177extern const unsigned MSP430InstrNameIndices[] = {
2178 1398U, 1817U, 2710U, 2271U, 1476U, 1457U, 1485U, 1645U,
2179 1182U, 1197U, 1148U, 1135U, 1224U, 3252U, 1011U, 3939U,
2180 1161U, 1394U, 1466U, 750U, 4322U, 1433U, 872U, 3843U,
2181 577U, 701U, 738U, 2420U, 1633U, 3753U, 684U, 2645U,
2182 1317U, 3742U, 922U, 2618U, 2605U, 2771U, 3601U, 3624U,
2183 1565U, 1612U, 1585U, 1502U, 1002U, 2736U, 2374U, 911U,
2184 4327U, 2889U, 2576U, 1059U, 3969U, 3999U, 2114U, 490U,
2185 185U, 1756U, 4071U, 4078U, 1783U, 1790U, 1797U, 1807U,
2186 555U, 3098U, 3061U, 3149U, 4013U, 2933U, 1554U, 2921U,
2187 1543U, 1146U, 1396U, 4245U, 1021U, 1036U, 1650U, 3569U,
2188 3156U, 3880U, 3173U, 2984U, 259U, 3235U, 3764U, 3125U,
2189 3912U, 1102U, 2747U, 658U, 233U, 640U, 3802U, 3783U,
2190 2092U, 2796U, 2815U, 391U, 335U, 365U, 304U, 376U,
2191 316U, 346U, 981U, 935U, 965U, 3282U, 1238U, 1255U,
2192 506U, 191U, 561U, 522U, 3103U, 3067U, 4229U, 2240U,
2193 4212U, 2223U, 457U, 168U, 4147U, 2158U, 1912U, 1859U,
2194 2033U, 1971U, 2482U, 2460U, 599U, 3522U, 730U, 1334U,
2195 590U, 3588U, 3858U, 211U, 3330U, 3719U, 3357U, 3983U,
2196 251U, 3395U, 4020U, 4035U, 3708U, 3696U, 3833U, 1309U,
2197 3962U, 1211U, 3992U, 1529U, 2882U, 2868U, 1522U, 2875U,
2198 3118U, 1666U, 2551U, 2530U, 2558U, 2565U, 3579U, 2366U,
2199 771U, 2350U, 722U, 2358U, 763U, 2342U, 714U, 2404U,
2200 2396U, 1362U, 1354U, 3440U, 3430U, 3420U, 3410U, 3460U,
2201 3450U, 4273U, 4283U, 3470U, 3483U, 4293U, 4303U, 3496U,
2202 3509U, 415U, 147U, 1690U, 128U, 297U, 4050U, 1762U,
2203 1127U, 4123U, 1425U, 2689U, 35U, 9U, 1302U, 18U,
2204 0U, 2664U, 2696U, 1175U, 3954U, 223U, 1402U, 1416U,
2205 2512U, 2521U, 3543U, 3556U, 3136U, 2129U, 3269U, 1111U,
2206 2057U, 2067U, 820U, 835U, 1848U, 1901U, 1957U, 2019U,
2207 4085U, 4111U, 4097U, 779U, 807U, 792U, 1272U, 1287U,
2208 496U, 1447U, 2192U, 4181U, 2216U, 4205U, 3143U, 631U,
2209 621U, 2705U, 3648U, 850U, 2965U, 2945U, 3676U, 3655U,
2210 2999U, 3030U, 3016U, 3312U, 4356U, 2306U, 4349U, 2287U,
2211 3188U, 2597U, 2504U, 989U, 1732U, 1345U, 1535U, 3203U,
2212 2264U, 3210U, 2085U, 3195U, 2256U, 2077U, 26U, 1386U,
2213 1378U, 1370U, 3889U, 2912U, 3775U, 3820U, 3922U, 2723U,
2214 859U, 280U, 1080U, 950U, 443U, 154U, 1718U, 4057U,
2215 1769U, 134U, 3897U, 2673U, 2537U, 3220U, 2835U, 2851U,
2216 4313U, 895U, 1092U, 3615U, 2412U, 879U, 2453U, 2429U,
2217 2441U, 422U, 1697U, 398U, 1673U, 4130U, 2141U, 1880U,
2218 1827U, 1995U, 1933U, 474U, 1740U, 539U, 3083U, 3045U,
2219 4164U, 2175U, 4188U, 2199U, 4259U, 4266U, 4406U, 4774U,
2220 5167U, 5557U, 5947U, 6355U, 4577U, 4945U, 5338U, 5728U,
2221 6103U, 6526U, 4493U, 4861U, 5254U, 5644U, 6026U, 6442U,
2222 4664U, 5032U, 5425U, 5815U, 6190U, 6613U, 4388U, 4756U,
2223 5149U, 5539U, 5929U, 6337U, 4559U, 4927U, 5320U, 5710U,
2224 6085U, 6508U, 4477U, 4845U, 5238U, 5628U, 6010U, 6426U,
2225 4648U, 5016U, 5409U, 5799U, 6174U, 6597U, 4713U, 2325U,
2226 2630U, 4414U, 4782U, 5175U, 5565U, 5955U, 6363U, 4585U,
2227 4953U, 5346U, 5736U, 6111U, 6534U, 4500U, 4868U, 5261U,
2228 5651U, 6033U, 6449U, 4671U, 5039U, 5432U, 5822U, 6197U,
2229 6620U, 4397U, 4765U, 5158U, 5548U, 5938U, 6346U, 4568U,
2230 4936U, 5329U, 5719U, 6094U, 6517U, 4485U, 4853U, 5246U,
2231 5636U, 6018U, 6434U, 4656U, 5024U, 5417U, 5807U, 6182U,
2232 6605U, 4438U, 4806U, 5199U, 5589U, 5979U, 6387U, 4609U,
2233 4977U, 5370U, 5760U, 6135U, 6558U, 4521U, 4889U, 5282U,
2234 5672U, 6054U, 6470U, 4692U, 5060U, 5453U, 5843U, 6218U,
2235 6641U, 4446U, 4814U, 5207U, 5597U, 5987U, 6395U, 4617U,
2236 4985U, 5378U, 5768U, 6143U, 6566U, 4528U, 4896U, 5289U,
2237 5679U, 6061U, 6477U, 4699U, 5067U, 5460U, 5850U, 6225U,
2238 6648U, 4730U, 5123U, 6311U, 4733U, 5126U, 5516U, 5906U,
2239 6314U, 4422U, 4790U, 5183U, 5573U, 5963U, 6371U, 4593U,
2240 4961U, 5354U, 5744U, 6119U, 6542U, 4507U, 4875U, 5268U,
2241 5658U, 6040U, 6456U, 4678U, 5046U, 5439U, 5829U, 6204U,
2242 6627U, 4405U, 4773U, 5166U, 5556U, 5946U, 6354U, 4576U,
2243 4944U, 5337U, 5727U, 6102U, 6525U, 4492U, 4860U, 5253U,
2244 5643U, 6025U, 6441U, 4663U, 5031U, 5424U, 5814U, 6189U,
2245 6612U, 207U, 2572U, 4454U, 4822U, 5215U, 5605U, 6403U,
2246 4625U, 4993U, 5386U, 5776U, 6151U, 6574U, 4535U, 4903U,
2247 5296U, 5686U, 6484U, 4706U, 5074U, 5467U, 5857U, 6232U,
2248 6655U, 98U, 109U, 6269U, 4363U, 4722U, 6261U, 6304U,
2249 3611U, 1411U, 5081U, 5474U, 5864U, 6239U, 5111U, 5504U,
2250 5894U, 6292U, 5096U, 5489U, 5879U, 6254U, 5117U, 5510U,
2251 5900U, 6298U, 49U, 82U, 5103U, 5496U, 5886U, 6276U,
2252 4371U, 4739U, 5132U, 5522U, 5912U, 6320U, 4542U, 4910U,
2253 5303U, 5693U, 6068U, 6491U, 4462U, 4830U, 5223U, 5613U,
2254 5995U, 6411U, 4633U, 5001U, 5394U, 5784U, 6159U, 6582U,
2255 4379U, 4747U, 5140U, 5530U, 5920U, 6328U, 4550U, 4918U,
2256 5311U, 5701U, 6076U, 6499U, 4469U, 4837U, 5230U, 5620U,
2257 6002U, 6418U, 4640U, 5008U, 5401U, 5791U, 6166U, 6589U,
2258 5088U, 5481U, 5871U, 6246U, 68U, 120U, 56U, 88U,
2259 43U, 77U, 62U, 93U, 4430U, 4798U, 5191U, 5581U,
2260 5971U, 6379U, 4601U, 4969U, 5362U, 5752U, 6127U, 6550U,
2261 4514U, 4882U, 5275U, 5665U, 6047U, 6463U, 4685U, 5053U,
2262 5446U, 5836U, 6211U, 6634U, 6284U,
2263};
2264
2265static inline void InitMSP430MCInstrInfo(MCInstrInfo *II) {
2266 II->InitMCInstrInfo(MSP430Descs.Insts, MSP430InstrNameIndices, MSP430InstrNameData, nullptr, nullptr, 677, nullptr, 0);
2267}
2268
2269
2270} // namespace llvm
2271
2272#endif // GET_INSTRINFO_MC_DESC
2273
2274#ifdef GET_INSTRINFO_HEADER
2275#undef GET_INSTRINFO_HEADER
2276
2277namespace llvm {
2278
2279struct MSP430GenInstrInfo : public TargetInstrInfo {
2280 explicit MSP430GenInstrInfo(const TargetSubtargetInfo &STI, const TargetRegisterInfo &TRI, unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u, unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u);
2281 ~MSP430GenInstrInfo() override = default;
2282};
2283
2284} // namespace llvm
2285
2286namespace llvm::MSP430 {
2287
2288
2289} // namespace llvm::MSP430
2290
2291#endif // GET_INSTRINFO_HEADER
2292
2293#ifdef GET_INSTRINFO_HELPER_DECLS
2294#undef GET_INSTRINFO_HELPER_DECLS
2295
2296
2297#endif // GET_INSTRINFO_HELPER_DECLS
2298
2299#ifdef GET_INSTRINFO_HELPERS
2300#undef GET_INSTRINFO_HELPERS
2301
2302
2303#endif // GET_INSTRINFO_HELPERS
2304
2305#ifdef GET_INSTRINFO_CTOR_DTOR
2306#undef GET_INSTRINFO_CTOR_DTOR
2307
2308namespace llvm {
2309
2310extern const MSP430InstrTable MSP430Descs;
2311extern const unsigned MSP430InstrNameIndices[];
2312extern const char MSP430InstrNameData[];
2313MSP430GenInstrInfo::MSP430GenInstrInfo(const TargetSubtargetInfo &STI, const TargetRegisterInfo &TRI, unsigned CFSetupOpcode, unsigned CFDestroyOpcode, unsigned CatchRetOpcode, unsigned ReturnOpcode)
2314 : TargetInstrInfo(TRI, CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) {
2315 InitMCInstrInfo(MSP430Descs.Insts, MSP430InstrNameIndices, MSP430InstrNameData, nullptr, nullptr, 677);
2316}
2317
2318} // namespace llvm
2319
2320#endif // GET_INSTRINFO_CTOR_DTOR
2321
2322#ifdef GET_INSTRINFO_MC_HELPER_DECLS
2323#undef GET_INSTRINFO_MC_HELPER_DECLS
2324
2325namespace llvm {
2326
2327class MCInst;
2328class FeatureBitset;
2329
2330namespace MSP430_MC {
2331
2332void verifyInstructionPredicates(unsigned Opcode, const FeatureBitset &Features);
2333
2334} // namespace MSP430_MC
2335
2336} // namespace llvm
2337
2338#endif // GET_INSTRINFO_MC_HELPER_DECLS
2339
2340#ifdef GET_INSTRINFO_MC_HELPERS
2341#undef GET_INSTRINFO_MC_HELPERS
2342
2343namespace llvm::MSP430_MC {
2344
2345
2346} // namespace llvm::MSP430_MC
2347
2348#endif // GET_INSTRINFO_MC_HELPERS
2349
2350#if (defined(ENABLE_INSTR_PREDICATE_VERIFIER) && !defined(NDEBUG)) ||\
2351 defined(GET_AVAILABLE_OPCODE_CHECKER)
2352#define GET_COMPUTE_FEATURES
2353#endif
2354#ifdef GET_COMPUTE_FEATURES
2355#undef GET_COMPUTE_FEATURES
2356
2357namespace llvm::MSP430_MC {
2358
2359// Bits for subtarget features that participate in instruction matching.
2360enum SubtargetFeatureBits : uint8_t {
2361};
2362
2363inline FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) {
2364 FeatureBitset Features;
2365 return Features;
2366}
2367
2368inline FeatureBitset computeRequiredFeatures(unsigned Opcode) {
2369 enum : uint8_t {
2370 CEFBS_None,
2371 };
2372
2373 static constexpr FeatureBitset FeatureBitsets[] = {
2374 {}, // CEFBS_None
2375 };
2376 static constexpr uint8_t RequiredFeaturesRefs[] = {
2377 CEFBS_None, // PHI
2378 CEFBS_None, // INLINEASM
2379 CEFBS_None, // INLINEASM_BR
2380 CEFBS_None, // CFI_INSTRUCTION
2381 CEFBS_None, // EH_LABEL
2382 CEFBS_None, // GC_LABEL
2383 CEFBS_None, // ANNOTATION_LABEL
2384 CEFBS_None, // KILL
2385 CEFBS_None, // EXTRACT_SUBREG
2386 CEFBS_None, // INSERT_SUBREG
2387 CEFBS_None, // IMPLICIT_DEF
2388 CEFBS_None, // INIT_UNDEF
2389 CEFBS_None, // SUBREG_TO_REG
2390 CEFBS_None, // COPY_TO_REGCLASS
2391 CEFBS_None, // DBG_VALUE
2392 CEFBS_None, // DBG_VALUE_LIST
2393 CEFBS_None, // DBG_INSTR_REF
2394 CEFBS_None, // DBG_PHI
2395 CEFBS_None, // DBG_LABEL
2396 CEFBS_None, // REG_SEQUENCE
2397 CEFBS_None, // COPY
2398 CEFBS_None, // COPY_LANEMASK
2399 CEFBS_None, // BUNDLE
2400 CEFBS_None, // LIFETIME_START
2401 CEFBS_None, // LIFETIME_END
2402 CEFBS_None, // PSEUDO_PROBE
2403 CEFBS_None, // ARITH_FENCE
2404 CEFBS_None, // STACKMAP
2405 CEFBS_None, // FENTRY_CALL
2406 CEFBS_None, // PATCHPOINT
2407 CEFBS_None, // LOAD_STACK_GUARD
2408 CEFBS_None, // PREALLOCATED_SETUP
2409 CEFBS_None, // PREALLOCATED_ARG
2410 CEFBS_None, // STATEPOINT
2411 CEFBS_None, // LOCAL_ESCAPE
2412 CEFBS_None, // FAULTING_OP
2413 CEFBS_None, // PATCHABLE_OP
2414 CEFBS_None, // PATCHABLE_FUNCTION_ENTER
2415 CEFBS_None, // PATCHABLE_RET
2416 CEFBS_None, // PATCHABLE_FUNCTION_EXIT
2417 CEFBS_None, // PATCHABLE_TAIL_CALL
2418 CEFBS_None, // PATCHABLE_EVENT_CALL
2419 CEFBS_None, // PATCHABLE_TYPED_EVENT_CALL
2420 CEFBS_None, // ICALL_BRANCH_FUNNEL
2421 CEFBS_None, // FAKE_USE
2422 CEFBS_None, // MEMBARRIER
2423 CEFBS_None, // JUMP_TABLE_DEBUG_INFO
2424 CEFBS_None, // RELOC_NONE
2425 CEFBS_None, // CONVERGENCECTRL_ENTRY
2426 CEFBS_None, // CONVERGENCECTRL_ANCHOR
2427 CEFBS_None, // CONVERGENCECTRL_LOOP
2428 CEFBS_None, // CONVERGENCECTRL_GLUE
2429 CEFBS_None, // G_ASSERT_SEXT
2430 CEFBS_None, // G_ASSERT_ZEXT
2431 CEFBS_None, // G_ASSERT_ALIGN
2432 CEFBS_None, // G_ADD
2433 CEFBS_None, // G_SUB
2434 CEFBS_None, // G_MUL
2435 CEFBS_None, // G_SDIV
2436 CEFBS_None, // G_UDIV
2437 CEFBS_None, // G_SREM
2438 CEFBS_None, // G_UREM
2439 CEFBS_None, // G_SDIVREM
2440 CEFBS_None, // G_UDIVREM
2441 CEFBS_None, // G_AND
2442 CEFBS_None, // G_OR
2443 CEFBS_None, // G_XOR
2444 CEFBS_None, // G_ABDS
2445 CEFBS_None, // G_ABDU
2446 CEFBS_None, // G_UAVGFLOOR
2447 CEFBS_None, // G_UAVGCEIL
2448 CEFBS_None, // G_SAVGFLOOR
2449 CEFBS_None, // G_SAVGCEIL
2450 CEFBS_None, // G_IMPLICIT_DEF
2451 CEFBS_None, // G_PHI
2452 CEFBS_None, // G_FRAME_INDEX
2453 CEFBS_None, // G_GLOBAL_VALUE
2454 CEFBS_None, // G_PTRAUTH_GLOBAL_VALUE
2455 CEFBS_None, // G_CONSTANT_POOL
2456 CEFBS_None, // G_EXTRACT
2457 CEFBS_None, // G_UNMERGE_VALUES
2458 CEFBS_None, // G_INSERT
2459 CEFBS_None, // G_MERGE_VALUES
2460 CEFBS_None, // G_BUILD_VECTOR
2461 CEFBS_None, // G_BUILD_VECTOR_TRUNC
2462 CEFBS_None, // G_CONCAT_VECTORS
2463 CEFBS_None, // G_PTRTOINT
2464 CEFBS_None, // G_INTTOPTR
2465 CEFBS_None, // G_BITCAST
2466 CEFBS_None, // G_FREEZE
2467 CEFBS_None, // G_CONSTANT_FOLD_BARRIER
2468 CEFBS_None, // G_INTRINSIC_FPTRUNC_ROUND
2469 CEFBS_None, // G_INTRINSIC_TRUNC
2470 CEFBS_None, // G_INTRINSIC_ROUND
2471 CEFBS_None, // G_INTRINSIC_LRINT
2472 CEFBS_None, // G_INTRINSIC_LLRINT
2473 CEFBS_None, // G_INTRINSIC_ROUNDEVEN
2474 CEFBS_None, // G_READCYCLECOUNTER
2475 CEFBS_None, // G_READSTEADYCOUNTER
2476 CEFBS_None, // G_LOAD
2477 CEFBS_None, // G_SEXTLOAD
2478 CEFBS_None, // G_ZEXTLOAD
2479 CEFBS_None, // G_FPEXTLOAD
2480 CEFBS_None, // G_INDEXED_LOAD
2481 CEFBS_None, // G_INDEXED_SEXTLOAD
2482 CEFBS_None, // G_INDEXED_ZEXTLOAD
2483 CEFBS_None, // G_STORE
2484 CEFBS_None, // G_FPTRUNCSTORE
2485 CEFBS_None, // G_INDEXED_STORE
2486 CEFBS_None, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
2487 CEFBS_None, // G_ATOMIC_CMPXCHG
2488 CEFBS_None, // G_ATOMICRMW_XCHG
2489 CEFBS_None, // G_ATOMICRMW_ADD
2490 CEFBS_None, // G_ATOMICRMW_SUB
2491 CEFBS_None, // G_ATOMICRMW_AND
2492 CEFBS_None, // G_ATOMICRMW_NAND
2493 CEFBS_None, // G_ATOMICRMW_OR
2494 CEFBS_None, // G_ATOMICRMW_XOR
2495 CEFBS_None, // G_ATOMICRMW_MAX
2496 CEFBS_None, // G_ATOMICRMW_MIN
2497 CEFBS_None, // G_ATOMICRMW_UMAX
2498 CEFBS_None, // G_ATOMICRMW_UMIN
2499 CEFBS_None, // G_ATOMICRMW_FADD
2500 CEFBS_None, // G_ATOMICRMW_FSUB
2501 CEFBS_None, // G_ATOMICRMW_FMAX
2502 CEFBS_None, // G_ATOMICRMW_FMIN
2503 CEFBS_None, // G_ATOMICRMW_FMAXIMUM
2504 CEFBS_None, // G_ATOMICRMW_FMINIMUM
2505 CEFBS_None, // G_ATOMICRMW_FMAXIMUMNUM
2506 CEFBS_None, // G_ATOMICRMW_FMINIMUMNUM
2507 CEFBS_None, // G_ATOMICRMW_UINC_WRAP
2508 CEFBS_None, // G_ATOMICRMW_UDEC_WRAP
2509 CEFBS_None, // G_ATOMICRMW_USUB_COND
2510 CEFBS_None, // G_ATOMICRMW_USUB_SAT
2511 CEFBS_None, // G_FENCE
2512 CEFBS_None, // G_PREFETCH
2513 CEFBS_None, // G_BRCOND
2514 CEFBS_None, // G_BRINDIRECT
2515 CEFBS_None, // G_INVOKE_REGION_START
2516 CEFBS_None, // G_INTRINSIC
2517 CEFBS_None, // G_INTRINSIC_W_SIDE_EFFECTS
2518 CEFBS_None, // G_INTRINSIC_CONVERGENT
2519 CEFBS_None, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
2520 CEFBS_None, // G_ANYEXT
2521 CEFBS_None, // G_TRUNC
2522 CEFBS_None, // G_TRUNC_SSAT_S
2523 CEFBS_None, // G_TRUNC_SSAT_U
2524 CEFBS_None, // G_TRUNC_USAT_U
2525 CEFBS_None, // G_CONSTANT
2526 CEFBS_None, // G_FCONSTANT
2527 CEFBS_None, // G_VASTART
2528 CEFBS_None, // G_VAARG
2529 CEFBS_None, // G_SEXT
2530 CEFBS_None, // G_SEXT_INREG
2531 CEFBS_None, // G_ZEXT
2532 CEFBS_None, // G_SHL
2533 CEFBS_None, // G_LSHR
2534 CEFBS_None, // G_ASHR
2535 CEFBS_None, // G_FSHL
2536 CEFBS_None, // G_FSHR
2537 CEFBS_None, // G_ROTR
2538 CEFBS_None, // G_ROTL
2539 CEFBS_None, // G_ICMP
2540 CEFBS_None, // G_FCMP
2541 CEFBS_None, // G_SCMP
2542 CEFBS_None, // G_UCMP
2543 CEFBS_None, // G_SELECT
2544 CEFBS_None, // G_UADDO
2545 CEFBS_None, // G_UADDE
2546 CEFBS_None, // G_USUBO
2547 CEFBS_None, // G_USUBE
2548 CEFBS_None, // G_SADDO
2549 CEFBS_None, // G_SADDE
2550 CEFBS_None, // G_SSUBO
2551 CEFBS_None, // G_SSUBE
2552 CEFBS_None, // G_UMULO
2553 CEFBS_None, // G_SMULO
2554 CEFBS_None, // G_UMULH
2555 CEFBS_None, // G_SMULH
2556 CEFBS_None, // G_UADDSAT
2557 CEFBS_None, // G_SADDSAT
2558 CEFBS_None, // G_USUBSAT
2559 CEFBS_None, // G_SSUBSAT
2560 CEFBS_None, // G_USHLSAT
2561 CEFBS_None, // G_SSHLSAT
2562 CEFBS_None, // G_SMULFIX
2563 CEFBS_None, // G_UMULFIX
2564 CEFBS_None, // G_SMULFIXSAT
2565 CEFBS_None, // G_UMULFIXSAT
2566 CEFBS_None, // G_SDIVFIX
2567 CEFBS_None, // G_UDIVFIX
2568 CEFBS_None, // G_SDIVFIXSAT
2569 CEFBS_None, // G_UDIVFIXSAT
2570 CEFBS_None, // G_FADD
2571 CEFBS_None, // G_FSUB
2572 CEFBS_None, // G_FMUL
2573 CEFBS_None, // G_FMA
2574 CEFBS_None, // G_FMAD
2575 CEFBS_None, // G_FDIV
2576 CEFBS_None, // G_FREM
2577 CEFBS_None, // G_FMODF
2578 CEFBS_None, // G_FPOW
2579 CEFBS_None, // G_FPOWI
2580 CEFBS_None, // G_FEXP
2581 CEFBS_None, // G_FEXP2
2582 CEFBS_None, // G_FEXP10
2583 CEFBS_None, // G_FLOG
2584 CEFBS_None, // G_FLOG2
2585 CEFBS_None, // G_FLOG10
2586 CEFBS_None, // G_FLDEXP
2587 CEFBS_None, // G_FFREXP
2588 CEFBS_None, // G_FNEG
2589 CEFBS_None, // G_FPEXT
2590 CEFBS_None, // G_FPTRUNC
2591 CEFBS_None, // G_FPTOSI
2592 CEFBS_None, // G_FPTOUI
2593 CEFBS_None, // G_SITOFP
2594 CEFBS_None, // G_UITOFP
2595 CEFBS_None, // G_FPTOSI_SAT
2596 CEFBS_None, // G_FPTOUI_SAT
2597 CEFBS_None, // G_FABS
2598 CEFBS_None, // G_FCOPYSIGN
2599 CEFBS_None, // G_IS_FPCLASS
2600 CEFBS_None, // G_FCANONICALIZE
2601 CEFBS_None, // G_FMINNUM
2602 CEFBS_None, // G_FMAXNUM
2603 CEFBS_None, // G_FMINNUM_IEEE
2604 CEFBS_None, // G_FMAXNUM_IEEE
2605 CEFBS_None, // G_FMINIMUM
2606 CEFBS_None, // G_FMAXIMUM
2607 CEFBS_None, // G_FMINIMUMNUM
2608 CEFBS_None, // G_FMAXIMUMNUM
2609 CEFBS_None, // G_GET_FPENV
2610 CEFBS_None, // G_SET_FPENV
2611 CEFBS_None, // G_RESET_FPENV
2612 CEFBS_None, // G_GET_FPMODE
2613 CEFBS_None, // G_SET_FPMODE
2614 CEFBS_None, // G_RESET_FPMODE
2615 CEFBS_None, // G_GET_ROUNDING
2616 CEFBS_None, // G_SET_ROUNDING
2617 CEFBS_None, // G_PTR_ADD
2618 CEFBS_None, // G_PTRMASK
2619 CEFBS_None, // G_SMIN
2620 CEFBS_None, // G_SMAX
2621 CEFBS_None, // G_UMIN
2622 CEFBS_None, // G_UMAX
2623 CEFBS_None, // G_ABS
2624 CEFBS_None, // G_LROUND
2625 CEFBS_None, // G_LLROUND
2626 CEFBS_None, // G_BR
2627 CEFBS_None, // G_BRJT
2628 CEFBS_None, // G_VSCALE
2629 CEFBS_None, // G_INSERT_SUBVECTOR
2630 CEFBS_None, // G_EXTRACT_SUBVECTOR
2631 CEFBS_None, // G_INSERT_VECTOR_ELT
2632 CEFBS_None, // G_EXTRACT_VECTOR_ELT
2633 CEFBS_None, // G_SHUFFLE_VECTOR
2634 CEFBS_None, // G_SPLAT_VECTOR
2635 CEFBS_None, // G_STEP_VECTOR
2636 CEFBS_None, // G_VECTOR_COMPRESS
2637 CEFBS_None, // G_CTTZ
2638 CEFBS_None, // G_CTTZ_ZERO_POISON
2639 CEFBS_None, // G_CTLZ
2640 CEFBS_None, // G_CTLZ_ZERO_POISON
2641 CEFBS_None, // G_CTLS
2642 CEFBS_None, // G_CTPOP
2643 CEFBS_None, // G_BSWAP
2644 CEFBS_None, // G_BITREVERSE
2645 CEFBS_None, // G_CLMUL
2646 CEFBS_None, // G_CLMULH
2647 CEFBS_None, // G_FCEIL
2648 CEFBS_None, // G_FCOS
2649 CEFBS_None, // G_FSIN
2650 CEFBS_None, // G_FSINCOS
2651 CEFBS_None, // G_FTAN
2652 CEFBS_None, // G_FACOS
2653 CEFBS_None, // G_FASIN
2654 CEFBS_None, // G_FATAN
2655 CEFBS_None, // G_FATAN2
2656 CEFBS_None, // G_FCOSH
2657 CEFBS_None, // G_FSINH
2658 CEFBS_None, // G_FTANH
2659 CEFBS_None, // G_FSQRT
2660 CEFBS_None, // G_FFLOOR
2661 CEFBS_None, // G_FRINT
2662 CEFBS_None, // G_FNEARBYINT
2663 CEFBS_None, // G_ADDRSPACE_CAST
2664 CEFBS_None, // G_BLOCK_ADDR
2665 CEFBS_None, // G_JUMP_TABLE
2666 CEFBS_None, // G_DYN_STACKALLOC
2667 CEFBS_None, // G_STACKSAVE
2668 CEFBS_None, // G_STACKRESTORE
2669 CEFBS_None, // G_STRICT_FADD
2670 CEFBS_None, // G_STRICT_FSUB
2671 CEFBS_None, // G_STRICT_FMUL
2672 CEFBS_None, // G_STRICT_FDIV
2673 CEFBS_None, // G_STRICT_FREM
2674 CEFBS_None, // G_STRICT_FMA
2675 CEFBS_None, // G_STRICT_FSQRT
2676 CEFBS_None, // G_STRICT_FLDEXP
2677 CEFBS_None, // G_STRICT_FCMP
2678 CEFBS_None, // G_STRICT_FCMPS
2679 CEFBS_None, // G_READ_REGISTER
2680 CEFBS_None, // G_WRITE_REGISTER
2681 CEFBS_None, // G_MEMCPY
2682 CEFBS_None, // G_MEMCPY_INLINE
2683 CEFBS_None, // G_MEMMOVE
2684 CEFBS_None, // G_MEMSET
2685 CEFBS_None, // G_BZERO
2686 CEFBS_None, // G_MEMSET_INLINE
2687 CEFBS_None, // G_TRAP
2688 CEFBS_None, // G_DEBUGTRAP
2689 CEFBS_None, // G_UBSANTRAP
2690 CEFBS_None, // G_VECREDUCE_SEQ_FADD
2691 CEFBS_None, // G_VECREDUCE_SEQ_FMUL
2692 CEFBS_None, // G_VECREDUCE_FADD
2693 CEFBS_None, // G_VECREDUCE_FMUL
2694 CEFBS_None, // G_VECREDUCE_FMAX
2695 CEFBS_None, // G_VECREDUCE_FMIN
2696 CEFBS_None, // G_VECREDUCE_FMAXIMUM
2697 CEFBS_None, // G_VECREDUCE_FMINIMUM
2698 CEFBS_None, // G_VECREDUCE_FMAXIMUMNUM
2699 CEFBS_None, // G_VECREDUCE_FMINIMUMNUM
2700 CEFBS_None, // G_VECREDUCE_ADD
2701 CEFBS_None, // G_VECREDUCE_MUL
2702 CEFBS_None, // G_VECREDUCE_AND
2703 CEFBS_None, // G_VECREDUCE_OR
2704 CEFBS_None, // G_VECREDUCE_XOR
2705 CEFBS_None, // G_VECREDUCE_SMAX
2706 CEFBS_None, // G_VECREDUCE_SMIN
2707 CEFBS_None, // G_VECREDUCE_UMAX
2708 CEFBS_None, // G_VECREDUCE_UMIN
2709 CEFBS_None, // G_SBFX
2710 CEFBS_None, // G_UBFX
2711 CEFBS_None, // ADD16mc
2712 CEFBS_None, // ADD16mi
2713 CEFBS_None, // ADD16mm
2714 CEFBS_None, // ADD16mn
2715 CEFBS_None, // ADD16mp
2716 CEFBS_None, // ADD16mr
2717 CEFBS_None, // ADD16rc
2718 CEFBS_None, // ADD16ri
2719 CEFBS_None, // ADD16rm
2720 CEFBS_None, // ADD16rn
2721 CEFBS_None, // ADD16rp
2722 CEFBS_None, // ADD16rr
2723 CEFBS_None, // ADD8mc
2724 CEFBS_None, // ADD8mi
2725 CEFBS_None, // ADD8mm
2726 CEFBS_None, // ADD8mn
2727 CEFBS_None, // ADD8mp
2728 CEFBS_None, // ADD8mr
2729 CEFBS_None, // ADD8rc
2730 CEFBS_None, // ADD8ri
2731 CEFBS_None, // ADD8rm
2732 CEFBS_None, // ADD8rn
2733 CEFBS_None, // ADD8rp
2734 CEFBS_None, // ADD8rr
2735 CEFBS_None, // ADDC16mc
2736 CEFBS_None, // ADDC16mi
2737 CEFBS_None, // ADDC16mm
2738 CEFBS_None, // ADDC16mn
2739 CEFBS_None, // ADDC16mp
2740 CEFBS_None, // ADDC16mr
2741 CEFBS_None, // ADDC16rc
2742 CEFBS_None, // ADDC16ri
2743 CEFBS_None, // ADDC16rm
2744 CEFBS_None, // ADDC16rn
2745 CEFBS_None, // ADDC16rp
2746 CEFBS_None, // ADDC16rr
2747 CEFBS_None, // ADDC8mc
2748 CEFBS_None, // ADDC8mi
2749 CEFBS_None, // ADDC8mm
2750 CEFBS_None, // ADDC8mn
2751 CEFBS_None, // ADDC8mp
2752 CEFBS_None, // ADDC8mr
2753 CEFBS_None, // ADDC8rc
2754 CEFBS_None, // ADDC8ri
2755 CEFBS_None, // ADDC8rm
2756 CEFBS_None, // ADDC8rn
2757 CEFBS_None, // ADDC8rp
2758 CEFBS_None, // ADDC8rr
2759 CEFBS_None, // ADDframe
2760 CEFBS_None, // ADJCALLSTACKDOWN
2761 CEFBS_None, // ADJCALLSTACKUP
2762 CEFBS_None, // AND16mc
2763 CEFBS_None, // AND16mi
2764 CEFBS_None, // AND16mm
2765 CEFBS_None, // AND16mn
2766 CEFBS_None, // AND16mp
2767 CEFBS_None, // AND16mr
2768 CEFBS_None, // AND16rc
2769 CEFBS_None, // AND16ri
2770 CEFBS_None, // AND16rm
2771 CEFBS_None, // AND16rn
2772 CEFBS_None, // AND16rp
2773 CEFBS_None, // AND16rr
2774 CEFBS_None, // AND8mc
2775 CEFBS_None, // AND8mi
2776 CEFBS_None, // AND8mm
2777 CEFBS_None, // AND8mn
2778 CEFBS_None, // AND8mp
2779 CEFBS_None, // AND8mr
2780 CEFBS_None, // AND8rc
2781 CEFBS_None, // AND8ri
2782 CEFBS_None, // AND8rm
2783 CEFBS_None, // AND8rn
2784 CEFBS_None, // AND8rp
2785 CEFBS_None, // AND8rr
2786 CEFBS_None, // BIC16mc
2787 CEFBS_None, // BIC16mi
2788 CEFBS_None, // BIC16mm
2789 CEFBS_None, // BIC16mn
2790 CEFBS_None, // BIC16mp
2791 CEFBS_None, // BIC16mr
2792 CEFBS_None, // BIC16rc
2793 CEFBS_None, // BIC16ri
2794 CEFBS_None, // BIC16rm
2795 CEFBS_None, // BIC16rn
2796 CEFBS_None, // BIC16rp
2797 CEFBS_None, // BIC16rr
2798 CEFBS_None, // BIC8mc
2799 CEFBS_None, // BIC8mi
2800 CEFBS_None, // BIC8mm
2801 CEFBS_None, // BIC8mn
2802 CEFBS_None, // BIC8mp
2803 CEFBS_None, // BIC8mr
2804 CEFBS_None, // BIC8rc
2805 CEFBS_None, // BIC8ri
2806 CEFBS_None, // BIC8rm
2807 CEFBS_None, // BIC8rn
2808 CEFBS_None, // BIC8rp
2809 CEFBS_None, // BIC8rr
2810 CEFBS_None, // BIS16mc
2811 CEFBS_None, // BIS16mi
2812 CEFBS_None, // BIS16mm
2813 CEFBS_None, // BIS16mn
2814 CEFBS_None, // BIS16mp
2815 CEFBS_None, // BIS16mr
2816 CEFBS_None, // BIS16rc
2817 CEFBS_None, // BIS16ri
2818 CEFBS_None, // BIS16rm
2819 CEFBS_None, // BIS16rn
2820 CEFBS_None, // BIS16rp
2821 CEFBS_None, // BIS16rr
2822 CEFBS_None, // BIS8mc
2823 CEFBS_None, // BIS8mi
2824 CEFBS_None, // BIS8mm
2825 CEFBS_None, // BIS8mn
2826 CEFBS_None, // BIS8mp
2827 CEFBS_None, // BIS8mr
2828 CEFBS_None, // BIS8rc
2829 CEFBS_None, // BIS8ri
2830 CEFBS_None, // BIS8rm
2831 CEFBS_None, // BIS8rn
2832 CEFBS_None, // BIS8rp
2833 CEFBS_None, // BIS8rr
2834 CEFBS_None, // BIT16mc
2835 CEFBS_None, // BIT16mi
2836 CEFBS_None, // BIT16mm
2837 CEFBS_None, // BIT16mn
2838 CEFBS_None, // BIT16mp
2839 CEFBS_None, // BIT16mr
2840 CEFBS_None, // BIT16rc
2841 CEFBS_None, // BIT16ri
2842 CEFBS_None, // BIT16rm
2843 CEFBS_None, // BIT16rn
2844 CEFBS_None, // BIT16rp
2845 CEFBS_None, // BIT16rr
2846 CEFBS_None, // BIT8mc
2847 CEFBS_None, // BIT8mi
2848 CEFBS_None, // BIT8mm
2849 CEFBS_None, // BIT8mn
2850 CEFBS_None, // BIT8mp
2851 CEFBS_None, // BIT8mr
2852 CEFBS_None, // BIT8rc
2853 CEFBS_None, // BIT8ri
2854 CEFBS_None, // BIT8rm
2855 CEFBS_None, // BIT8rn
2856 CEFBS_None, // BIT8rp
2857 CEFBS_None, // BIT8rr
2858 CEFBS_None, // Bi
2859 CEFBS_None, // Bm
2860 CEFBS_None, // Br
2861 CEFBS_None, // CALLi
2862 CEFBS_None, // CALLm
2863 CEFBS_None, // CALLn
2864 CEFBS_None, // CALLp
2865 CEFBS_None, // CALLr
2866 CEFBS_None, // CMP16mc
2867 CEFBS_None, // CMP16mi
2868 CEFBS_None, // CMP16mm
2869 CEFBS_None, // CMP16mn
2870 CEFBS_None, // CMP16mp
2871 CEFBS_None, // CMP16mr
2872 CEFBS_None, // CMP16rc
2873 CEFBS_None, // CMP16ri
2874 CEFBS_None, // CMP16rm
2875 CEFBS_None, // CMP16rn
2876 CEFBS_None, // CMP16rp
2877 CEFBS_None, // CMP16rr
2878 CEFBS_None, // CMP8mc
2879 CEFBS_None, // CMP8mi
2880 CEFBS_None, // CMP8mm
2881 CEFBS_None, // CMP8mn
2882 CEFBS_None, // CMP8mp
2883 CEFBS_None, // CMP8mr
2884 CEFBS_None, // CMP8rc
2885 CEFBS_None, // CMP8ri
2886 CEFBS_None, // CMP8rm
2887 CEFBS_None, // CMP8rn
2888 CEFBS_None, // CMP8rp
2889 CEFBS_None, // CMP8rr
2890 CEFBS_None, // DADD16mc
2891 CEFBS_None, // DADD16mi
2892 CEFBS_None, // DADD16mm
2893 CEFBS_None, // DADD16mn
2894 CEFBS_None, // DADD16mp
2895 CEFBS_None, // DADD16mr
2896 CEFBS_None, // DADD16rc
2897 CEFBS_None, // DADD16ri
2898 CEFBS_None, // DADD16rm
2899 CEFBS_None, // DADD16rn
2900 CEFBS_None, // DADD16rp
2901 CEFBS_None, // DADD16rr
2902 CEFBS_None, // DADD8mc
2903 CEFBS_None, // DADD8mi
2904 CEFBS_None, // DADD8mm
2905 CEFBS_None, // DADD8mn
2906 CEFBS_None, // DADD8mp
2907 CEFBS_None, // DADD8mr
2908 CEFBS_None, // DADD8rc
2909 CEFBS_None, // DADD8ri
2910 CEFBS_None, // DADD8rm
2911 CEFBS_None, // DADD8rn
2912 CEFBS_None, // DADD8rp
2913 CEFBS_None, // DADD8rr
2914 CEFBS_None, // JCC
2915 CEFBS_None, // JMP
2916 CEFBS_None, // MOV16mc
2917 CEFBS_None, // MOV16mi
2918 CEFBS_None, // MOV16mm
2919 CEFBS_None, // MOV16mn
2920 CEFBS_None, // MOV16mr
2921 CEFBS_None, // MOV16rc
2922 CEFBS_None, // MOV16ri
2923 CEFBS_None, // MOV16rm
2924 CEFBS_None, // MOV16rn
2925 CEFBS_None, // MOV16rp
2926 CEFBS_None, // MOV16rr
2927 CEFBS_None, // MOV8mc
2928 CEFBS_None, // MOV8mi
2929 CEFBS_None, // MOV8mm
2930 CEFBS_None, // MOV8mn
2931 CEFBS_None, // MOV8mr
2932 CEFBS_None, // MOV8rc
2933 CEFBS_None, // MOV8ri
2934 CEFBS_None, // MOV8rm
2935 CEFBS_None, // MOV8rn
2936 CEFBS_None, // MOV8rp
2937 CEFBS_None, // MOV8rr
2938 CEFBS_None, // MOVZX16rm8
2939 CEFBS_None, // MOVZX16rr8
2940 CEFBS_None, // POP16r
2941 CEFBS_None, // PUSH16c
2942 CEFBS_None, // PUSH16i
2943 CEFBS_None, // PUSH16r
2944 CEFBS_None, // PUSH8r
2945 CEFBS_None, // RET
2946 CEFBS_None, // RETI
2947 CEFBS_None, // RRA16m
2948 CEFBS_None, // RRA16n
2949 CEFBS_None, // RRA16p
2950 CEFBS_None, // RRA16r
2951 CEFBS_None, // RRA8m
2952 CEFBS_None, // RRA8n
2953 CEFBS_None, // RRA8p
2954 CEFBS_None, // RRA8r
2955 CEFBS_None, // RRC16m
2956 CEFBS_None, // RRC16n
2957 CEFBS_None, // RRC16p
2958 CEFBS_None, // RRC16r
2959 CEFBS_None, // RRC8m
2960 CEFBS_None, // RRC8n
2961 CEFBS_None, // RRC8p
2962 CEFBS_None, // RRC8r
2963 CEFBS_None, // Rrcl16
2964 CEFBS_None, // Rrcl8
2965 CEFBS_None, // SEXT16m
2966 CEFBS_None, // SEXT16n
2967 CEFBS_None, // SEXT16p
2968 CEFBS_None, // SEXT16r
2969 CEFBS_None, // SUB16mc
2970 CEFBS_None, // SUB16mi
2971 CEFBS_None, // SUB16mm
2972 CEFBS_None, // SUB16mn
2973 CEFBS_None, // SUB16mp
2974 CEFBS_None, // SUB16mr
2975 CEFBS_None, // SUB16rc
2976 CEFBS_None, // SUB16ri
2977 CEFBS_None, // SUB16rm
2978 CEFBS_None, // SUB16rn
2979 CEFBS_None, // SUB16rp
2980 CEFBS_None, // SUB16rr
2981 CEFBS_None, // SUB8mc
2982 CEFBS_None, // SUB8mi
2983 CEFBS_None, // SUB8mm
2984 CEFBS_None, // SUB8mn
2985 CEFBS_None, // SUB8mp
2986 CEFBS_None, // SUB8mr
2987 CEFBS_None, // SUB8rc
2988 CEFBS_None, // SUB8ri
2989 CEFBS_None, // SUB8rm
2990 CEFBS_None, // SUB8rn
2991 CEFBS_None, // SUB8rp
2992 CEFBS_None, // SUB8rr
2993 CEFBS_None, // SUBC16mc
2994 CEFBS_None, // SUBC16mi
2995 CEFBS_None, // SUBC16mm
2996 CEFBS_None, // SUBC16mn
2997 CEFBS_None, // SUBC16mp
2998 CEFBS_None, // SUBC16mr
2999 CEFBS_None, // SUBC16rc
3000 CEFBS_None, // SUBC16ri
3001 CEFBS_None, // SUBC16rm
3002 CEFBS_None, // SUBC16rn
3003 CEFBS_None, // SUBC16rp
3004 CEFBS_None, // SUBC16rr
3005 CEFBS_None, // SUBC8mc
3006 CEFBS_None, // SUBC8mi
3007 CEFBS_None, // SUBC8mm
3008 CEFBS_None, // SUBC8mn
3009 CEFBS_None, // SUBC8mp
3010 CEFBS_None, // SUBC8mr
3011 CEFBS_None, // SUBC8rc
3012 CEFBS_None, // SUBC8ri
3013 CEFBS_None, // SUBC8rm
3014 CEFBS_None, // SUBC8rn
3015 CEFBS_None, // SUBC8rp
3016 CEFBS_None, // SUBC8rr
3017 CEFBS_None, // SWPB16m
3018 CEFBS_None, // SWPB16n
3019 CEFBS_None, // SWPB16p
3020 CEFBS_None, // SWPB16r
3021 CEFBS_None, // Select16
3022 CEFBS_None, // Select8
3023 CEFBS_None, // Shl16
3024 CEFBS_None, // Shl8
3025 CEFBS_None, // Sra16
3026 CEFBS_None, // Sra8
3027 CEFBS_None, // Srl16
3028 CEFBS_None, // Srl8
3029 CEFBS_None, // XOR16mc
3030 CEFBS_None, // XOR16mi
3031 CEFBS_None, // XOR16mm
3032 CEFBS_None, // XOR16mn
3033 CEFBS_None, // XOR16mp
3034 CEFBS_None, // XOR16mr
3035 CEFBS_None, // XOR16rc
3036 CEFBS_None, // XOR16ri
3037 CEFBS_None, // XOR16rm
3038 CEFBS_None, // XOR16rn
3039 CEFBS_None, // XOR16rp
3040 CEFBS_None, // XOR16rr
3041 CEFBS_None, // XOR8mc
3042 CEFBS_None, // XOR8mi
3043 CEFBS_None, // XOR8mm
3044 CEFBS_None, // XOR8mn
3045 CEFBS_None, // XOR8mp
3046 CEFBS_None, // XOR8mr
3047 CEFBS_None, // XOR8rc
3048 CEFBS_None, // XOR8ri
3049 CEFBS_None, // XOR8rm
3050 CEFBS_None, // XOR8rn
3051 CEFBS_None, // XOR8rp
3052 CEFBS_None, // XOR8rr
3053 CEFBS_None, // ZEXT16r
3054 };
3055
3056 assert(Opcode < 677);
3057 return FeatureBitsets[RequiredFeaturesRefs[Opcode]];
3058}
3059
3060
3061} // namespace llvm::MSP430_MC
3062
3063#endif // GET_COMPUTE_FEATURES
3064
3065#ifdef GET_AVAILABLE_OPCODE_CHECKER
3066#undef GET_AVAILABLE_OPCODE_CHECKER
3067
3068namespace llvm::MSP430_MC {
3069
3070bool isOpcodeAvailable(unsigned Opcode, const FeatureBitset &Features) {
3071 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
3072 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
3073 FeatureBitset MissingFeatures =
3074 (AvailableFeatures & RequiredFeatures) ^
3075 RequiredFeatures;
3076 return !MissingFeatures.any();
3077}
3078
3079} // namespace llvm::MSP430_MC
3080
3081#endif // GET_AVAILABLE_OPCODE_CHECKER
3082
3083#ifdef ENABLE_INSTR_PREDICATE_VERIFIER
3084#undef ENABLE_INSTR_PREDICATE_VERIFIER
3085
3086#include <sstream>
3087
3088namespace llvm::MSP430_MC {
3089
3090#ifndef NDEBUG
3091static const char *SubtargetFeatureNames[] = {
3092 nullptr
3093};
3094
3095#endif // NDEBUG
3096
3097void verifyInstructionPredicates(
3098 unsigned Opcode, const FeatureBitset &Features) {
3099#ifndef NDEBUG
3100 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
3101 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
3102 FeatureBitset MissingFeatures =
3103 (AvailableFeatures & RequiredFeatures) ^
3104 RequiredFeatures;
3105 if (MissingFeatures.any()) {
3106 std::ostringstream Msg;
3107 Msg << "Attempting to emit " << &MSP430InstrNameData[MSP430InstrNameIndices[Opcode]]
3108 << " instruction but the ";
3109 for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i)
3110 if (MissingFeatures.test(i))
3111 Msg << SubtargetFeatureNames[i] << " ";
3112 Msg << "predicate(s) are not met";
3113 report_fatal_error(Msg.str().c_str());
3114 }
3115#endif // NDEBUG
3116}
3117
3118} // namespace llvm::MSP430_MC
3119
3120#endif // ENABLE_INSTR_PREDICATE_VERIFIER
3121
3122