1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Register Enum Values *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9namespace llvm {
10
11class MCRegisterClass;
12const MCRegisterClass &getMSP430MCRegisterClass(unsigned RC);
13namespace MSP430 {
14
15enum : unsigned {
16 NoRegister,
17 CG = 1,
18 CGB = 2,
19 PC = 3,
20 PCB = 4,
21 SP = 5,
22 SPB = 6,
23 SR = 7,
24 SRB = 8,
25 R4 = 9,
26 R5 = 10,
27 R6 = 11,
28 R7 = 12,
29 R8 = 13,
30 R9 = 14,
31 R10 = 15,
32 R11 = 16,
33 R12 = 17,
34 R13 = 18,
35 R14 = 19,
36 R15 = 20,
37 R4B = 21,
38 R5B = 22,
39 R6B = 23,
40 R7B = 24,
41 R8B = 25,
42 R9B = 26,
43 R10B = 27,
44 R11B = 28,
45 R12B = 29,
46 R13B = 30,
47 R14B = 31,
48 R15B = 32,
49 NUM_TARGET_REGS // 33
50};
51
52} // namespace MSP430
53
54// Register classes
55
56namespace MSP430 {
57
58enum {
59 GR8RegClassID = 0,
60 GR16RegClassID = 1,
61
62};
63
64} // namespace MSP430
65
66// Subregister indices
67
68namespace MSP430 {
69
70enum : uint16_t {
71 NoSubRegister,
72 subreg_8bit, // 1
73 NUM_TARGET_SUBREGS
74};
75
76} // namespace MSP430
77// Register pressure sets enum.
78namespace MSP430 {
79
80enum RegisterPressureSets {
81 GR8 = 0,
82};
83
84} // namespace MSP430
85
86} // namespace llvm
87