1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Register Enum Values *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9namespace llvm {
10
11class MCRegisterClass;
12extern const MCRegisterClass MSP430MCRegisterClasses[];
13
14namespace MSP430 {
15
16enum : unsigned {
17 NoRegister,
18 CG = 1,
19 CGB = 2,
20 PC = 3,
21 PCB = 4,
22 SP = 5,
23 SPB = 6,
24 SR = 7,
25 SRB = 8,
26 R4 = 9,
27 R5 = 10,
28 R6 = 11,
29 R7 = 12,
30 R8 = 13,
31 R9 = 14,
32 R10 = 15,
33 R11 = 16,
34 R12 = 17,
35 R13 = 18,
36 R14 = 19,
37 R15 = 20,
38 R4B = 21,
39 R5B = 22,
40 R6B = 23,
41 R7B = 24,
42 R8B = 25,
43 R9B = 26,
44 R10B = 27,
45 R11B = 28,
46 R12B = 29,
47 R13B = 30,
48 R14B = 31,
49 R15B = 32,
50 NUM_TARGET_REGS // 33
51};
52
53} // namespace MSP430
54
55// Register classes
56
57namespace MSP430 {
58
59enum {
60 GR8RegClassID = 0,
61 GR16RegClassID = 1,
62
63};
64
65} // namespace MSP430
66
67// Subregister indices
68
69namespace MSP430 {
70
71enum : uint16_t {
72 NoSubRegister,
73 subreg_8bit, // 1
74 NUM_TARGET_SUBREGS
75};
76
77} // namespace MSP430
78// Register pressure sets enum.
79namespace MSP430 {
80
81enum RegisterPressureSets {
82 GR8 = 0,
83};
84
85} // namespace MSP430
86
87} // namespace llvm
88