1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Subtarget Enumeration Source Fragment *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_SUBTARGETINFO_ENUM
10#undef GET_SUBTARGETINFO_ENUM
11
12namespace llvm {
13
14namespace MSP430 {
15
16enum {
17 FeatureHWMult16 = 0,
18 FeatureHWMult32 = 1,
19 FeatureHWMultF5 = 2,
20 FeatureX = 3,
21 NumSubtargetFeatures = 4
22};
23
24} // namespace MSP430
25
26} // namespace llvm
27
28#endif // GET_SUBTARGETINFO_ENUM
29
30#ifdef GET_SUBTARGETINFO_MACRO
31
32GET_SUBTARGETINFO_MACRO(ExtendedInsts, false, extendedInsts)
33
34#undef GET_SUBTARGETINFO_MACRO
35#endif // GET_SUBTARGETINFO_MACRO
36
37#ifdef GET_SUBTARGETINFO_MC_DESC
38#undef GET_SUBTARGETINFO_MC_DESC
39
40namespace llvm {
41
42// Sorted (by key) array of values for CPU features.
43extern const llvm::SubtargetFeatureKVStorage< 4, 165> MSP430FeatureKVStorage = {
44 {
45 { sizeof(SubtargetFeatureKV) * 4 + 1, sizeof(SubtargetFeatureKV) * 4 + 5, MSP430::FeatureX, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
46 { sizeof(SubtargetFeatureKV) * 3 + 32, sizeof(SubtargetFeatureKV) * 3 + 41, MSP430::FeatureHWMult16, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
47 { sizeof(SubtargetFeatureKV) * 2 + 75, sizeof(SubtargetFeatureKV) * 2 + 84, MSP430::FeatureHWMult32, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
48 { sizeof(SubtargetFeatureKV) * 1 + 118, sizeof(SubtargetFeatureKV) * 1 + 127, MSP430::FeatureHWMultF5, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
49 },
50 "\000ext\000Enable MSP430-X extensions\000hwmult16\000Enable 16-bit hard"
51 "ware multiplier\000hwmult32\000Enable 32-bit hardware multiplier\000hwm"
52 "ultf5\000Enable F5 series hardware multiplier\000"};
53
54#ifdef DBGFIELD
55#error "<target>GenSubtargetInfo.inc requires a DBGFIELD macro"
56#endif
57#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
58#define DBGFIELD(x) x,
59#define DBGVAL_OR_NULLPTR(x) x
60#else
61#define DBGFIELD(x)
62#define DBGVAL_OR_NULLPTR(x) nullptr
63#endif
64
65// ===============================================================
66// Data tables for the new per-operand machine model.
67
68static_assert(0 <= UINT8_MAX, "NumWriteProcResEntries does not fit in uint8_t");
69static_assert(0 <= UINT8_MAX, "NumWriteLatencyEntries does not fit in uint8_t");
70
71// {ProcResourceIdx, ReleaseAtCycle, AcquireAtCycle}
72extern const llvm::MCWriteProcResEntry MSP430WriteProcResTable[] = {
73 { 0, 0, 0 }, // Invalid
74}; // MSP430WriteProcResTable
75
76// {Cycles, WriteResourceID}
77extern const llvm::MCWriteLatencyEntry MSP430WriteLatencyTable[] = {
78 { 0, 0}, // Invalid
79}; // MSP430WriteLatencyTable
80
81// {UseIdx, WriteResourceID, Cycles}
82extern const llvm::MCReadAdvanceEntry MSP430ReadAdvanceTable[] = {
83 {0, 0, 0}, // Invalid
84}; // MSP430ReadAdvanceTable
85
86#ifdef __GNUC__
87#pragma GCC diagnostic push
88#pragma GCC diagnostic ignored "-Woverlength-strings"
89#endif
90static constexpr char MSP430SchedClassNamesStorage[] =
91 "\0"
92 "InvalidSchedClass\0"
93 ;
94#ifdef __GNUC__
95#pragma GCC diagnostic pop
96#endif
97
98static constexpr llvm::StringTable
99MSP430SchedClassNames = MSP430SchedClassNamesStorage;
100
101extern const llvm::MCSchedModel MSP430SchedModels[] = {
102{ // NoSchedModel
103 MCSchedModel::DefaultIssueWidth,
104 MCSchedModel::DefaultMicroOpBufferSize,
105 MCSchedModel::DefaultLoopMicroOpBufferSize,
106 MCSchedModel::DefaultLoadLatency,
107 MCSchedModel::DefaultHighLatency,
108 MCSchedModel::DefaultMispredictPenalty,
109 false, // PostRAScheduler
110 false, // CompleteModel
111 false, // EnableIntervals
112 0, // Processor ID
113 nullptr, nullptr, 0, 0, // No instruction-level machine model.
114 DBGVAL_OR_NULLPTR(&MSP430SchedClassNames), // SchedClassNames
115 nullptr, // No Itinerary
116 nullptr // No extra processor descriptor
117 },
118};
119
120#undef DBGFIELD
121
122#undef DBGVAL_OR_NULLPTR
123
124static constexpr size_t MSP430CPUAliasArraySize = sizeof(std::array<SubtargetSubTypeAliasKV, 0>);
125// Sorted (by key) array of values for CPU subtype.
126extern const llvm::SubtargetSubTypeKVStorage< 3, 0, 25> MSP430SubTypeKVStorage = {
127 {
128 { sizeof(SubtargetSubTypeKV) * 3 + MSP430CPUAliasArraySize + 1, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
129 { sizeof(SubtargetSubTypeKV) * 2 + MSP430CPUAliasArraySize + 9, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
130 { sizeof(SubtargetSubTypeKV) * 1 + MSP430CPUAliasArraySize + 16, { { { 0x8ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
131 },
132 { {
133 } },
134 "\000generic\000msp430\000msp430x\000"};
135
136namespace MSP430_MC {
137
138unsigned resolveVariantSchedClassImpl(unsigned SchedClass,
139 const MCInst *MI, const MCInstrInfo *MCII, const MCSubtargetInfo &STI, unsigned CPUID) {
140 // Don't know how to resolve this scheduling class.
141 return 0;
142}
143
144} // namespace MSP430_MC
145struct MSP430GenMCSubtargetInfo : public MCSubtargetInfo {
146 MSP430GenMCSubtargetInfo(const Triple &TT,
147 StringRef CPU, StringRef TuneCPU, StringRef FS,
148 StringTable PN,
149 ArrayRef<SubtargetFeatureKV> PF,
150 ArrayRef<SubtargetSubTypeKV> PD,
151 ArrayRef<SubtargetSubTypeAliasKV> PA,
152 const MCSchedModel *PSM,
153 const MCWriteProcResEntry *WPR,
154 const MCWriteLatencyEntry *WL,
155 const MCReadAdvanceEntry *RA, const InstrStage *IS,
156 const unsigned *OC, const unsigned *FP) :
157 MCSubtargetInfo(TT, CPU, TuneCPU, FS, PN, PF, PD, PA, PSM,
158 WPR, WL, RA, IS, OC, FP) { }
159
160 unsigned resolveVariantSchedClass(unsigned SchedClass,
161 const MCInst *MI, const MCInstrInfo *MCII,
162 unsigned CPUID) const final {
163 return MSP430_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, *this, CPUID);
164 }
165};
166
167static inline MCSubtargetInfo *createMSP430MCSubtargetInfoImpl(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS) {
168 return new MSP430GenMCSubtargetInfo(TT, CPU, TuneCPU, FS, StringTable(MSP430SubTypeKVStorage.Strings), MSP430FeatureKVStorage.Features, MSP430SubTypeKVStorage.SubTypes, ArrayRef(MSP430SubTypeKVStorage.Aliases).take_front(0), MSP430SchedModels,
169 MSP430WriteProcResTable, MSP430WriteLatencyTable, MSP430ReadAdvanceTable,
170 nullptr, nullptr, nullptr);
171}
172
173
174} // namespace llvm
175
176#endif // GET_SUBTARGETINFO_MC_DESC
177
178#ifdef GET_SUBTARGETINFO_TARGET_DESC
179#undef GET_SUBTARGETINFO_TARGET_DESC
180
181#include "llvm/ADT/BitmaskEnum.h"
182#include "llvm/Support/Debug.h"
183#include "llvm/Support/raw_ostream.h"
184
185// ParseSubtargetFeatures - Parses features string setting specified
186// subtarget options.
187void llvm::MSP430Subtarget::ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS) {
188 LLVM_DEBUG(dbgs() << "\nFeatures:" << FS);
189 LLVM_DEBUG(dbgs() << "\nCPU:" << CPU);
190 LLVM_DEBUG(dbgs() << "\nTuneCPU:" << TuneCPU << "\n\n");
191 InitMCProcessorInfo(CPU, TuneCPU, FS);
192 const FeatureBitset &Bits = getFeatureBits();
193 if (Bits[MSP430::FeatureHWMult16] && HWMultMode < HWMult16) HWMultMode = HWMult16;
194 if (Bits[MSP430::FeatureHWMult32] && HWMultMode < HWMult32) HWMultMode = HWMult32;
195 if (Bits[MSP430::FeatureHWMultF5] && HWMultMode < HWMultF5) HWMultMode = HWMultF5;
196 if (Bits[MSP430::FeatureX]) ExtendedInsts = true;
197}
198
199#endif // GET_SUBTARGETINFO_TARGET_DESC
200
201#ifdef GET_SUBTARGETINFO_HEADER
202#undef GET_SUBTARGETINFO_HEADER
203
204namespace llvm {
205
206class DFAPacketizer;
207namespace MSP430_MC {
208
209unsigned resolveVariantSchedClassImpl(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, const MCSubtargetInfo &STI, unsigned CPUID);
210
211} // namespace MSP430_MC
212struct MSP430GenSubtargetInfo : public TargetSubtargetInfo {
213 explicit MSP430GenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS);
214public:
215 unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const final;
216 unsigned resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const final;
217 DFAPacketizer *createDFAPacketizer(const InstrItineraryData *IID) const;
218 const FeatureBitset &getInlineIgnoreFeatures() const override;
219 const FeatureBitset &getInlineInverseFeatures() const override;
220 const FeatureBitset &getInlineMustMatchFeatures() const override;
221};
222
223} // namespace llvm
224
225#endif // GET_SUBTARGETINFO_HEADER
226
227#ifdef GET_SUBTARGETINFO_CTOR
228#undef GET_SUBTARGETINFO_CTOR
229
230#include "llvm/CodeGen/TargetSchedule.h"
231
232namespace llvm {
233
234extern const llvm::StringRef MSP430Names[];
235extern const llvm::SubtargetFeatureKVStorage<4, 165> MSP430FeatureKVStorage;
236extern const llvm::SubtargetSubTypeKVStorage<3, 0, 25> MSP430SubTypeKVStorage;
237extern const llvm::MCSchedModel MSP430SchedModels[];
238extern const llvm::MCWriteProcResEntry MSP430WriteProcResTable[];
239extern const llvm::MCWriteLatencyEntry MSP430WriteLatencyTable[];
240extern const llvm::MCReadAdvanceEntry MSP430ReadAdvanceTable[];
241MSP430GenSubtargetInfo::MSP430GenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS)
242 : TargetSubtargetInfo(TT, CPU, TuneCPU, FS, StringTable(MSP430SubTypeKVStorage.Strings), ArrayRef(MSP430FeatureKVStorage.Features), ArrayRef(MSP430SubTypeKVStorage.SubTypes), ArrayRef(MSP430SubTypeKVStorage.Aliases).take_front(0), MSP430SchedModels,
243 MSP430WriteProcResTable, MSP430WriteLatencyTable, MSP430ReadAdvanceTable,
244 nullptr, nullptr, nullptr) {}
245
246unsigned MSP430GenSubtargetInfo
247::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const {
248 report_fatal_error("Expected a variant SchedClass");
249} // MSP430GenSubtargetInfo::resolveSchedClass
250
251unsigned MSP430GenSubtargetInfo
252::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const {
253 return MSP430_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, *this, CPUID);
254} // MSP430GenSubtargetInfo::resolveVariantSchedClass
255
256const FeatureBitset &MSP430GenSubtargetInfo::getInlineIgnoreFeatures() const {
257 static constexpr FeatureBitset Features = {
258 };
259 return Features;
260}
261
262const FeatureBitset &MSP430GenSubtargetInfo::getInlineInverseFeatures() const {
263 static constexpr FeatureBitset Features = {
264 };
265 return Features;
266}
267
268const FeatureBitset &MSP430GenSubtargetInfo::getInlineMustMatchFeatures() const {
269 static constexpr FeatureBitset Features = {
270 };
271 return Features;
272}
273
274
275} // namespace llvm
276
277#endif // GET_SUBTARGETINFO_CTOR
278
279#ifdef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
280#undef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
281
282
283#endif // GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
284
285#ifdef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
286#undef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
287
288
289#endif // GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
290
291