1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Subtarget Enumeration Source Fragment *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_SUBTARGETINFO_ENUM
10#undef GET_SUBTARGETINFO_ENUM
11
12namespace llvm {
13
14namespace MSP430 {
15
16enum {
17 FeatureHWMult16 = 0,
18 FeatureHWMult32 = 1,
19 FeatureHWMultF5 = 2,
20 FeatureX = 3,
21 NumSubtargetFeatures = 4
22};
23
24} // namespace MSP430
25
26} // namespace llvm
27
28#endif // GET_SUBTARGETINFO_ENUM
29
30#ifdef GET_SUBTARGETINFO_MACRO
31
32GET_SUBTARGETINFO_MACRO(ExtendedInsts, false, extendedInsts)
33
34#undef GET_SUBTARGETINFO_MACRO
35#endif // GET_SUBTARGETINFO_MACRO
36
37#ifdef GET_SUBTARGETINFO_MC_DESC
38#undef GET_SUBTARGETINFO_MC_DESC
39
40namespace llvm {
41
42// Sorted (by key) array of values for CPU features.
43extern const llvm::SubtargetFeatureKVStorage< 4, 165> MSP430FeatureKVStorage = {
44 {
45 { sizeof(SubtargetFeatureKV) * 4 + 1, sizeof(SubtargetFeatureKV) * 4 + 5, MSP430::FeatureX, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
46 { sizeof(SubtargetFeatureKV) * 3 + 32, sizeof(SubtargetFeatureKV) * 3 + 41, MSP430::FeatureHWMult16, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
47 { sizeof(SubtargetFeatureKV) * 2 + 75, sizeof(SubtargetFeatureKV) * 2 + 84, MSP430::FeatureHWMult32, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
48 { sizeof(SubtargetFeatureKV) * 1 + 118, sizeof(SubtargetFeatureKV) * 1 + 127, MSP430::FeatureHWMultF5, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
49 },
50 "\000ext\000Enable MSP430-X extensions\000hwmult16\000Enable 16-bit hard"
51 "ware multiplier\000hwmult32\000Enable 32-bit hardware multiplier\000hwm"
52 "ultf5\000Enable F5 series hardware multiplier\000"};
53
54#ifdef DBGFIELD
55#error "<target>GenSubtargetInfo.inc requires a DBGFIELD macro"
56#endif
57#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
58#define DBGFIELD(x) x,
59#define DBGVAL_OR_NULLPTR(x) x
60#else
61#define DBGFIELD(x)
62#define DBGVAL_OR_NULLPTR(x) nullptr
63#endif
64
65// ===============================================================
66// Data tables for the new per-operand machine model.
67
68static_assert(0 <= UINT8_MAX, "NumWriteProcResEntries does not fit in uint8_t");
69static_assert(0 <= UINT8_MAX, "NumWriteLatencyEntries does not fit in uint8_t");
70
71// {ProcResourceIdx, ReleaseAtCycle, AcquireAtCycle}
72extern const llvm::MCWriteProcResEntry MSP430WriteProcResTable[] = {
73 { 0, 0, 0 }, // Invalid
74}; // MSP430WriteProcResTable
75
76// {Cycles, WriteResourceID}
77extern const llvm::MCWriteLatencyEntry MSP430WriteLatencyTable[] = {
78 { 0, 0}, // Invalid
79}; // MSP430WriteLatencyTable
80
81// {UseIdx, WriteResourceID, Cycles}
82extern const llvm::MCReadAdvanceEntry MSP430ReadAdvanceTable[] = {
83 {0, 0, 0}, // Invalid
84}; // MSP430ReadAdvanceTable
85
86#ifdef __GNUC__
87#pragma GCC diagnostic push
88#pragma GCC diagnostic ignored "-Woverlength-strings"
89#endif
90static constexpr char MSP430SchedClassNamesStorage[] =
91 "\0"
92 "InvalidSchedClass\0"
93 ;
94#ifdef __GNUC__
95#pragma GCC diagnostic pop
96#endif
97
98static constexpr llvm::StringTable
99MSP430SchedClassNames = MSP430SchedClassNamesStorage;
100
101extern const llvm::MCSchedModel MSP430SchedModels[] = {
102{ // NoSchedModel
103 MCSchedModel::DefaultIssueWidth,
104 MCSchedModel::DefaultMicroOpBufferSize,
105 MCSchedModel::DefaultLoopMicroOpBufferSize,
106 MCSchedModel::DefaultLoadLatency,
107 MCSchedModel::DefaultHighLatency,
108 MCSchedModel::DefaultMispredictPenalty,
109 false, // PostRAScheduler
110 false, // CompleteModel
111 false, // EnableIntervals
112 0, // Processor ID
113 nullptr, nullptr, 0, 0, // No instruction-level machine model.
114 DBGVAL_OR_NULLPTR(&MSP430SchedClassNames), // SchedClassNames
115 nullptr, // No Itinerary
116 nullptr // No extra processor descriptor
117 },
118};
119
120#undef DBGFIELD
121
122#undef DBGVAL_OR_NULLPTR
123
124// Sorted (by key) array of values for CPU subtype.
125extern const llvm::SubtargetSubTypeKVStorage< 3, 25> MSP430SubTypeKVStorage = {
126 {
127 { sizeof(SubtargetSubTypeKV) * 3 + 1, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
128 { sizeof(SubtargetSubTypeKV) * 2 + 9, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
129 { sizeof(SubtargetSubTypeKV) * 1 + 16, { { { 0x8ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
130 },
131 "\000generic\000msp430\000msp430x\000"};
132
133namespace MSP430_MC {
134
135unsigned resolveVariantSchedClassImpl(unsigned SchedClass,
136 const MCInst *MI, const MCInstrInfo *MCII, const MCSubtargetInfo &STI, unsigned CPUID) {
137 // Don't know how to resolve this scheduling class.
138 return 0;
139}
140
141} // namespace MSP430_MC
142struct MSP430GenMCSubtargetInfo : public MCSubtargetInfo {
143 MSP430GenMCSubtargetInfo(const Triple &TT,
144 StringRef CPU, StringRef TuneCPU, StringRef FS,
145 StringTable PN,
146 ArrayRef<SubtargetFeatureKV> PF,
147 ArrayRef<SubtargetSubTypeKV> PD,
148 const MCSchedModel *PSM,
149 const MCWriteProcResEntry *WPR,
150 const MCWriteLatencyEntry *WL,
151 const MCReadAdvanceEntry *RA, const InstrStage *IS,
152 const unsigned *OC, const unsigned *FP) :
153 MCSubtargetInfo(TT, CPU, TuneCPU, FS, PN, PF, PD, PSM,
154 WPR, WL, RA, IS, OC, FP) { }
155
156 unsigned resolveVariantSchedClass(unsigned SchedClass,
157 const MCInst *MI, const MCInstrInfo *MCII,
158 unsigned CPUID) const final {
159 return MSP430_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, *this, CPUID);
160 }
161};
162
163static inline MCSubtargetInfo *createMSP430MCSubtargetInfoImpl(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS) {
164 return new MSP430GenMCSubtargetInfo(TT, CPU, TuneCPU, FS, StringTable(MSP430SubTypeKVStorage.Strings), MSP430FeatureKVStorage.Features, MSP430SubTypeKVStorage.SubTypes, MSP430SchedModels,
165 MSP430WriteProcResTable, MSP430WriteLatencyTable, MSP430ReadAdvanceTable,
166 nullptr, nullptr, nullptr);
167}
168
169
170} // namespace llvm
171
172#endif // GET_SUBTARGETINFO_MC_DESC
173
174#ifdef GET_SUBTARGETINFO_TARGET_DESC
175#undef GET_SUBTARGETINFO_TARGET_DESC
176
177#include "llvm/ADT/BitmaskEnum.h"
178#include "llvm/Support/Debug.h"
179#include "llvm/Support/raw_ostream.h"
180
181// ParseSubtargetFeatures - Parses features string setting specified
182// subtarget options.
183void llvm::MSP430Subtarget::ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS) {
184 LLVM_DEBUG(dbgs() << "\nFeatures:" << FS);
185 LLVM_DEBUG(dbgs() << "\nCPU:" << CPU);
186 LLVM_DEBUG(dbgs() << "\nTuneCPU:" << TuneCPU << "\n\n");
187 InitMCProcessorInfo(CPU, TuneCPU, FS);
188 const FeatureBitset &Bits = getFeatureBits();
189 if (Bits[MSP430::FeatureHWMult16] && HWMultMode < HWMult16) HWMultMode = HWMult16;
190 if (Bits[MSP430::FeatureHWMult32] && HWMultMode < HWMult32) HWMultMode = HWMult32;
191 if (Bits[MSP430::FeatureHWMultF5] && HWMultMode < HWMultF5) HWMultMode = HWMultF5;
192 if (Bits[MSP430::FeatureX]) ExtendedInsts = true;
193}
194
195#endif // GET_SUBTARGETINFO_TARGET_DESC
196
197#ifdef GET_SUBTARGETINFO_HEADER
198#undef GET_SUBTARGETINFO_HEADER
199
200namespace llvm {
201
202class DFAPacketizer;
203namespace MSP430_MC {
204
205unsigned resolveVariantSchedClassImpl(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, const MCSubtargetInfo &STI, unsigned CPUID);
206
207} // namespace MSP430_MC
208struct MSP430GenSubtargetInfo : public TargetSubtargetInfo {
209 explicit MSP430GenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS);
210public:
211 unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const final;
212 unsigned resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const final;
213 DFAPacketizer *createDFAPacketizer(const InstrItineraryData *IID) const;
214 const FeatureBitset &getInlineIgnoreFeatures() const override;
215 const FeatureBitset &getInlineInverseFeatures() const override;
216 const FeatureBitset &getInlineMustMatchFeatures() const override;
217};
218
219} // namespace llvm
220
221#endif // GET_SUBTARGETINFO_HEADER
222
223#ifdef GET_SUBTARGETINFO_CTOR
224#undef GET_SUBTARGETINFO_CTOR
225
226#include "llvm/CodeGen/TargetSchedule.h"
227
228namespace llvm {
229
230extern const llvm::StringRef MSP430Names[];
231extern const llvm::SubtargetFeatureKVStorage<4, 165> MSP430FeatureKVStorage;
232extern const llvm::SubtargetSubTypeKVStorage<3, 25> MSP430SubTypeKVStorage;
233extern const llvm::MCSchedModel MSP430SchedModels[];
234extern const llvm::MCWriteProcResEntry MSP430WriteProcResTable[];
235extern const llvm::MCWriteLatencyEntry MSP430WriteLatencyTable[];
236extern const llvm::MCReadAdvanceEntry MSP430ReadAdvanceTable[];
237MSP430GenSubtargetInfo::MSP430GenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS)
238 : TargetSubtargetInfo(TT, CPU, TuneCPU, FS, StringTable(MSP430SubTypeKVStorage.Strings), ArrayRef(MSP430FeatureKVStorage.Features), ArrayRef(MSP430SubTypeKVStorage.SubTypes), MSP430SchedModels,
239 MSP430WriteProcResTable, MSP430WriteLatencyTable, MSP430ReadAdvanceTable,
240 nullptr, nullptr, nullptr) {}
241
242unsigned MSP430GenSubtargetInfo
243::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const {
244 report_fatal_error("Expected a variant SchedClass");
245} // MSP430GenSubtargetInfo::resolveSchedClass
246
247unsigned MSP430GenSubtargetInfo
248::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const {
249 return MSP430_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, *this, CPUID);
250} // MSP430GenSubtargetInfo::resolveVariantSchedClass
251
252const FeatureBitset &MSP430GenSubtargetInfo::getInlineIgnoreFeatures() const {
253 static constexpr FeatureBitset Features = {
254 };
255 return Features;
256}
257
258const FeatureBitset &MSP430GenSubtargetInfo::getInlineInverseFeatures() const {
259 static constexpr FeatureBitset Features = {
260 };
261 return Features;
262}
263
264const FeatureBitset &MSP430GenSubtargetInfo::getInlineMustMatchFeatures() const {
265 static constexpr FeatureBitset Features = {
266 };
267 return Features;
268}
269
270
271} // namespace llvm
272
273#endif // GET_SUBTARGETINFO_CTOR
274
275#ifdef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
276#undef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
277
278
279#endif // GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
280
281#ifdef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
282#undef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
283
284
285#endif // GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
286
287