1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Subtarget Enumeration Source Fragment *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_SUBTARGETINFO_ENUM
10#undef GET_SUBTARGETINFO_ENUM
11
12namespace llvm {
13
14namespace MSP430 {
15
16enum {
17 FeatureHWMult16 = 0,
18 FeatureHWMult32 = 1,
19 FeatureHWMultF5 = 2,
20 FeatureX = 3,
21 NumSubtargetFeatures = 4
22};
23
24} // namespace MSP430
25
26} // namespace llvm
27
28#endif // GET_SUBTARGETINFO_ENUM
29
30#ifdef GET_SUBTARGETINFO_MACRO
31
32GET_SUBTARGETINFO_MACRO(ExtendedInsts, false, extendedInsts)
33
34#undef GET_SUBTARGETINFO_MACRO
35#endif // GET_SUBTARGETINFO_MACRO
36
37#ifdef GET_SUBTARGETINFO_MC_DESC
38#undef GET_SUBTARGETINFO_MC_DESC
39
40namespace llvm {
41
42// Sorted (by key) array of values for CPU features.
43extern const llvm::SubtargetFeatureKV MSP430FeatureKV[] = {
44 { "ext", "Enable MSP430-X extensions", MSP430::FeatureX, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
45 { "hwmult16", "Enable 16-bit hardware multiplier", MSP430::FeatureHWMult16, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
46 { "hwmult32", "Enable 32-bit hardware multiplier", MSP430::FeatureHWMult32, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
47 { "hwmultf5", "Enable F5 series hardware multiplier", MSP430::FeatureHWMultF5, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
48};
49
50#ifdef DBGFIELD
51#error "<target>GenSubtargetInfo.inc requires a DBGFIELD macro"
52#endif
53#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
54#define DBGFIELD(x) x,
55#define DBGVAL_OR_NULLPTR(x) x
56#else
57#define DBGFIELD(x)
58#define DBGVAL_OR_NULLPTR(x) nullptr
59#endif
60
61// ===============================================================
62// Data tables for the new per-operand machine model.
63
64// {ProcResourceIdx, ReleaseAtCycle, AcquireAtCycle}
65extern const llvm::MCWriteProcResEntry MSP430WriteProcResTable[] = {
66 { 0, 0, 0 }, // Invalid
67}; // MSP430WriteProcResTable
68
69// {Cycles, WriteResourceID}
70extern const llvm::MCWriteLatencyEntry MSP430WriteLatencyTable[] = {
71 { 0, 0}, // Invalid
72}; // MSP430WriteLatencyTable
73
74// {UseIdx, WriteResourceID, Cycles}
75extern const llvm::MCReadAdvanceEntry MSP430ReadAdvanceTable[] = {
76 {0, 0, 0}, // Invalid
77}; // MSP430ReadAdvanceTable
78
79#ifdef __GNUC__
80#pragma GCC diagnostic push
81#pragma GCC diagnostic ignored "-Woverlength-strings"
82#endif
83static constexpr char MSP430SchedClassNamesStorage[] =
84 "\0"
85 "InvalidSchedClass\0"
86 ;
87#ifdef __GNUC__
88#pragma GCC diagnostic pop
89#endif
90
91static constexpr llvm::StringTable
92MSP430SchedClassNames = MSP430SchedClassNamesStorage;
93
94static const llvm::MCSchedModel NoSchedModel = {
95 MCSchedModel::DefaultIssueWidth,
96 MCSchedModel::DefaultMicroOpBufferSize,
97 MCSchedModel::DefaultLoopMicroOpBufferSize,
98 MCSchedModel::DefaultLoadLatency,
99 MCSchedModel::DefaultHighLatency,
100 MCSchedModel::DefaultMispredictPenalty,
101 false, // PostRAScheduler
102 false, // CompleteModel
103 false, // EnableIntervals
104 0, // Processor ID
105 nullptr, nullptr, 0, 0, // No instruction-level machine model.
106 DBGVAL_OR_NULLPTR(&MSP430SchedClassNames), // SchedClassNames
107 nullptr, // No Itinerary
108 nullptr // No extra processor descriptor
109};
110
111#undef DBGFIELD
112
113#undef DBGVAL_OR_NULLPTR
114
115// Sorted (by key) array of values for CPU subtype.
116extern const llvm::SubtargetSubTypeKV MSP430SubTypeKV[] = {
117 { "generic", { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
118 { "msp430", { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
119 { "msp430x", { { { 0x8ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
120};
121
122// Sorted array of names of CPU subtypes, including aliases.
123extern const llvm::StringRef MSP430Names[] = {
124"generic",
125"msp430",
126"msp430x"};
127
128namespace MSP430_MC {
129
130unsigned resolveVariantSchedClassImpl(unsigned SchedClass,
131 const MCInst *MI, const MCInstrInfo *MCII, const MCSubtargetInfo &STI, unsigned CPUID) {
132 // Don't know how to resolve this scheduling class.
133 return 0;
134}
135
136} // namespace MSP430_MC
137struct MSP430GenMCSubtargetInfo : public MCSubtargetInfo {
138 MSP430GenMCSubtargetInfo(const Triple &TT,
139 StringRef CPU, StringRef TuneCPU, StringRef FS,
140 ArrayRef<StringRef> PN,
141 ArrayRef<SubtargetFeatureKV> PF,
142 ArrayRef<SubtargetSubTypeKV> PD,
143 const MCWriteProcResEntry *WPR,
144 const MCWriteLatencyEntry *WL,
145 const MCReadAdvanceEntry *RA, const InstrStage *IS,
146 const unsigned *OC, const unsigned *FP) :
147 MCSubtargetInfo(TT, CPU, TuneCPU, FS, PN, PF, PD,
148 WPR, WL, RA, IS, OC, FP) { }
149
150 unsigned resolveVariantSchedClass(unsigned SchedClass,
151 const MCInst *MI, const MCInstrInfo *MCII,
152 unsigned CPUID) const final {
153 return MSP430_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, *this, CPUID);
154 }
155};
156
157static inline MCSubtargetInfo *createMSP430MCSubtargetInfoImpl(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS) {
158 return new MSP430GenMCSubtargetInfo(TT, CPU, TuneCPU, FS, MSP430Names, MSP430FeatureKV, MSP430SubTypeKV,
159 MSP430WriteProcResTable, MSP430WriteLatencyTable, MSP430ReadAdvanceTable,
160 nullptr, nullptr, nullptr);
161}
162
163
164} // namespace llvm
165
166#endif // GET_SUBTARGETINFO_MC_DESC
167
168#ifdef GET_SUBTARGETINFO_TARGET_DESC
169#undef GET_SUBTARGETINFO_TARGET_DESC
170
171#include "llvm/ADT/BitmaskEnum.h"
172#include "llvm/Support/Debug.h"
173#include "llvm/Support/raw_ostream.h"
174
175// ParseSubtargetFeatures - Parses features string setting specified
176// subtarget options.
177void llvm::MSP430Subtarget::ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS) {
178 LLVM_DEBUG(dbgs() << "\nFeatures:" << FS);
179 LLVM_DEBUG(dbgs() << "\nCPU:" << CPU);
180 LLVM_DEBUG(dbgs() << "\nTuneCPU:" << TuneCPU << "\n\n");
181 InitMCProcessorInfo(CPU, TuneCPU, FS);
182 const FeatureBitset &Bits = getFeatureBits();
183 if (Bits[MSP430::FeatureHWMult16] && HWMultMode < HWMult16) HWMultMode = HWMult16;
184 if (Bits[MSP430::FeatureHWMult32] && HWMultMode < HWMult32) HWMultMode = HWMult32;
185 if (Bits[MSP430::FeatureHWMultF5] && HWMultMode < HWMultF5) HWMultMode = HWMultF5;
186 if (Bits[MSP430::FeatureX]) ExtendedInsts = true;
187}
188
189#endif // GET_SUBTARGETINFO_TARGET_DESC
190
191#ifdef GET_SUBTARGETINFO_HEADER
192#undef GET_SUBTARGETINFO_HEADER
193
194namespace llvm {
195
196class DFAPacketizer;
197namespace MSP430_MC {
198
199unsigned resolveVariantSchedClassImpl(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, const MCSubtargetInfo &STI, unsigned CPUID);
200
201} // namespace MSP430_MC
202struct MSP430GenSubtargetInfo : public TargetSubtargetInfo {
203 explicit MSP430GenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS);
204public:
205 unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const final;
206 unsigned resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const final;
207 DFAPacketizer *createDFAPacketizer(const InstrItineraryData *IID) const;
208};
209
210} // namespace llvm
211
212#endif // GET_SUBTARGETINFO_HEADER
213
214#ifdef GET_SUBTARGETINFO_CTOR
215#undef GET_SUBTARGETINFO_CTOR
216
217#include "llvm/CodeGen/TargetSchedule.h"
218
219namespace llvm {
220
221extern const llvm::StringRef MSP430Names[];
222extern const llvm::SubtargetFeatureKV MSP430FeatureKV[];
223extern const llvm::SubtargetSubTypeKV MSP430SubTypeKV[];
224extern const llvm::MCWriteProcResEntry MSP430WriteProcResTable[];
225extern const llvm::MCWriteLatencyEntry MSP430WriteLatencyTable[];
226extern const llvm::MCReadAdvanceEntry MSP430ReadAdvanceTable[];
227MSP430GenSubtargetInfo::MSP430GenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS)
228 : TargetSubtargetInfo(TT, CPU, TuneCPU, FS, ArrayRef(MSP430Names, 3), ArrayRef(MSP430FeatureKV, 4), ArrayRef(MSP430SubTypeKV, 3),
229 MSP430WriteProcResTable, MSP430WriteLatencyTable, MSP430ReadAdvanceTable,
230 nullptr, nullptr, nullptr) {}
231
232unsigned MSP430GenSubtargetInfo
233::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const {
234 report_fatal_error("Expected a variant SchedClass");
235} // MSP430GenSubtargetInfo::resolveSchedClass
236
237unsigned MSP430GenSubtargetInfo
238::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const {
239 return MSP430_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, *this, CPUID);
240} // MSP430GenSubtargetInfo::resolveVariantSchedClass
241
242
243} // namespace llvm
244
245#endif // GET_SUBTARGETINFO_CTOR
246
247#ifdef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
248#undef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
249
250
251#endif // GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
252
253#ifdef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
254#undef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
255
256
257#endif // GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
258
259