1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Assembly Matcher Source Fragment *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* From: Mips.td *|
7|* *|
8\*===----------------------------------------------------------------------===*/
9
10
11#ifdef GET_ASSEMBLER_HEADER
12#undef GET_ASSEMBLER_HEADER
13 // This should be included into the middle of the declaration of
14 // your subclasses implementation of MCTargetAsmParser.
15 FeatureBitset ComputeAvailableFeatures(const FeatureBitset &FB) const;
16 void convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode,
17 const OperandVector &Operands);
18 void convertToMapAndConstraints(unsigned Kind,
19 const OperandVector &Operands) override;
20 unsigned MatchInstructionImpl(const OperandVector &Operands,
21 MCInst &Inst,
22 uint64_t &ErrorInfo,
23 FeatureBitset &MissingFeatures,
24 bool matchingInlineAsm,
25 unsigned VariantID = 0);
26 unsigned MatchInstructionImpl(const OperandVector &Operands,
27 MCInst &Inst,
28 uint64_t &ErrorInfo,
29 bool matchingInlineAsm,
30 unsigned VariantID = 0) {
31 FeatureBitset MissingFeatures;
32 return MatchInstructionImpl(Operands, Inst, ErrorInfo, MissingFeatures,
33 matchingInlineAsm, VariantID);
34 }
35
36 ParseStatus MatchOperandParserImpl(
37 OperandVector &Operands,
38 StringRef Mnemonic,
39 bool ParseForAllFeatures = false);
40 ParseStatus tryCustomParseOperand(
41 OperandVector &Operands,
42 unsigned MCK);
43
44#endif // GET_ASSEMBLER_HEADER
45
46
47#ifdef GET_OPERAND_DIAGNOSTIC_TYPES
48#undef GET_OPERAND_DIAGNOSTIC_TYPES
49
50 Match_ConstantMemOffset,
51 Match_Immz,
52 Match_MemSImm10,
53 Match_MemSImm10Lsl1,
54 Match_MemSImm10Lsl2,
55 Match_MemSImm10Lsl3,
56 Match_MemSImm11,
57 Match_MemSImm12,
58 Match_MemSImm16,
59 Match_MemSImm9,
60 Match_MemSImmPtr,
61 Match_SImm10_0,
62 Match_SImm10_Lsl1,
63 Match_SImm10_Lsl2,
64 Match_SImm10_Lsl3,
65 Match_SImm11_0,
66 Match_SImm16,
67 Match_SImm16_Relaxed,
68 Match_SImm18_Lsl3,
69 Match_SImm19_Lsl2,
70 Match_SImm32,
71 Match_SImm32_Relaxed,
72 Match_SImm4_0,
73 Match_SImm5_0,
74 Match_SImm6_0,
75 Match_SImm7_Lsl2,
76 Match_SImm9_0,
77 Match_UImm10_0,
78 Match_UImm16,
79 Match_UImm16_AltRelaxed,
80 Match_UImm16_Relaxed,
81 Match_UImm1_0,
82 Match_UImm20_0,
83 Match_UImm26_0,
84 Match_UImm2_0,
85 Match_UImm2_1,
86 Match_UImm32_Coerced,
87 Match_UImm3_0,
88 Match_UImm4_0,
89 Match_UImm5_0,
90 Match_UImm5_0_Report_UImm6,
91 Match_UImm5_1,
92 Match_UImm5_32,
93 Match_UImm5_33,
94 Match_UImm5_Lsl2,
95 Match_UImm6_0,
96 Match_UImm6_Lsl2,
97 Match_UImm7_0,
98 Match_UImm7_N1,
99 Match_UImm8_0,
100 Match_UImmRange2_64,
101 END_OPERAND_DIAGNOSTIC_TYPES
102#endif // GET_OPERAND_DIAGNOSTIC_TYPES
103
104
105#ifdef GET_REGISTER_MATCHER
106#undef GET_REGISTER_MATCHER
107
108// Bits for subtarget features that participate in instruction matching.
109enum SubtargetFeatureBits : uint8_t {
110 Feature_IsPTR64bitBit = 37,
111 Feature_IsPTR32bitBit = 36,
112 Feature_UseCompactBranchesBit = 54,
113 Feature_HasMips2Bit = 11,
114 Feature_HasMips3_32Bit = 14,
115 Feature_HasMips3_32r2Bit = 15,
116 Feature_HasMips3Bit = 12,
117 Feature_NotMips3Bit = 48,
118 Feature_HasMips4_32Bit = 16,
119 Feature_NotMips4_32Bit = 49,
120 Feature_HasMips4_32r2Bit = 17,
121 Feature_HasMips5_32r2Bit = 18,
122 Feature_HasMips32Bit = 19,
123 Feature_HasMips32r2Bit = 20,
124 Feature_HasMips32r5Bit = 21,
125 Feature_HasMips32r6Bit = 22,
126 Feature_NotMips32r6Bit = 50,
127 Feature_IsGP64bitBit = 33,
128 Feature_IsGP32bitBit = 32,
129 Feature_HasMips64Bit = 23,
130 Feature_NotMips64Bit = 51,
131 Feature_HasMips64r2Bit = 24,
132 Feature_HasMips64r5Bit = 25,
133 Feature_HasMips64r6Bit = 26,
134 Feature_NotMips64r6Bit = 52,
135 Feature_InMips16ModeBit = 30,
136 Feature_NotInMips16ModeBit = 47,
137 Feature_HasCnMipsBit = 1,
138 Feature_NotCnMipsBit = 43,
139 Feature_HasCnMipsPBit = 2,
140 Feature_NotCnMipsPBit = 44,
141 Feature_IsSym32Bit = 40,
142 Feature_IsSym64Bit = 41,
143 Feature_HasStdEncBit = 27,
144 Feature_InMicroMipsBit = 29,
145 Feature_NotInMicroMipsBit = 46,
146 Feature_HasEVABit = 6,
147 Feature_HasMSABit = 8,
148 Feature_HasMadd4Bit = 10,
149 Feature_HasMTBit = 9,
150 Feature_UseIndirectJumpsHazardBit = 55,
151 Feature_NoIndirectJumpGuardsBit = 42,
152 Feature_IsR5900Bit = 38,
153 Feature_NotR5900Bit = 53,
154 Feature_HasCRCBit = 0,
155 Feature_HasVirtBit = 28,
156 Feature_HasGINVBit = 7,
157 Feature_IsFP64bitBit = 31,
158 Feature_NotFP64bitBit = 45,
159 Feature_IsSingleFloatBit = 39,
160 Feature_IsNotSingleFloatBit = 34,
161 Feature_IsNotSoftFloatBit = 35,
162 Feature_HasMips3DBit = 13,
163 Feature_HasDSPBit = 3,
164 Feature_HasDSPR2Bit = 4,
165 Feature_HasDSPR3Bit = 5,
166};
167
168[[maybe_unused]] static MCRegister MatchRegisterName(StringRef Name) {
169 switch (Name.size()) {
170 default: break;
171 case 1: // 74 strings to match.
172 switch (Name[0]) {
173 default: break;
174 case '0': // 5 strings to match.
175 return Mips::MSAIR; // "0"
176 case '1': // 7 strings to match.
177 return Mips::MSACSR; // "1"
178 case '2': // 7 strings to match.
179 return Mips::MSAAccess; // "2"
180 case '3': // 7 strings to match.
181 return Mips::MSASave; // "3"
182 case '4': // 8 strings to match.
183 return Mips::MSAModify; // "4"
184 case '5': // 8 strings to match.
185 return Mips::MSARequest; // "5"
186 case '6': // 8 strings to match.
187 return Mips::MSAMap; // "6"
188 case '7': // 8 strings to match.
189 return Mips::MSAUnmap; // "7"
190 case '8': // 8 strings to match.
191 return Mips::COP08; // "8"
192 case '9': // 8 strings to match.
193 return Mips::COP09; // "9"
194 }
195 break;
196 case 2: // 227 strings to match.
197 switch (Name[0]) {
198 default: break;
199 case '1': // 80 strings to match.
200 switch (Name[1]) {
201 default: break;
202 case '0': // 8 strings to match.
203 return Mips::COP010; // "10"
204 case '1': // 8 strings to match.
205 return Mips::COP011; // "11"
206 case '2': // 8 strings to match.
207 return Mips::COP012; // "12"
208 case '3': // 8 strings to match.
209 return Mips::COP013; // "13"
210 case '4': // 8 strings to match.
211 return Mips::COP014; // "14"
212 case '5': // 8 strings to match.
213 return Mips::COP015; // "15"
214 case '6': // 8 strings to match.
215 return Mips::COP016; // "16"
216 case '7': // 8 strings to match.
217 return Mips::COP017; // "17"
218 case '8': // 8 strings to match.
219 return Mips::COP018; // "18"
220 case '9': // 8 strings to match.
221 return Mips::COP019; // "19"
222 }
223 break;
224 case '2': // 76 strings to match.
225 switch (Name[1]) {
226 default: break;
227 case '0': // 8 strings to match.
228 return Mips::COP020; // "20"
229 case '1': // 8 strings to match.
230 return Mips::COP021; // "21"
231 case '2': // 8 strings to match.
232 return Mips::COP022; // "22"
233 case '3': // 8 strings to match.
234 return Mips::COP023; // "23"
235 case '4': // 8 strings to match.
236 return Mips::COP024; // "24"
237 case '5': // 8 strings to match.
238 return Mips::COP025; // "25"
239 case '6': // 8 strings to match.
240 return Mips::COP026; // "26"
241 case '7': // 8 strings to match.
242 return Mips::COP027; // "27"
243 case '8': // 6 strings to match.
244 return Mips::COP028; // "28"
245 case '9': // 6 strings to match.
246 return Mips::COP029; // "29"
247 }
248 break;
249 case '3': // 12 strings to match.
250 switch (Name[1]) {
251 default: break;
252 case '0': // 6 strings to match.
253 return Mips::COP030; // "30"
254 case '1': // 6 strings to match.
255 return Mips::COP031; // "31"
256 }
257 break;
258 case 'f': // 37 strings to match.
259 switch (Name[1]) {
260 default: break;
261 case '0': // 4 strings to match.
262 return Mips::D0; // "f0"
263 case '1': // 3 strings to match.
264 return Mips::F1; // "f1"
265 case '2': // 4 strings to match.
266 return Mips::D1; // "f2"
267 case '3': // 3 strings to match.
268 return Mips::F3; // "f3"
269 case '4': // 4 strings to match.
270 return Mips::D2; // "f4"
271 case '5': // 3 strings to match.
272 return Mips::F5; // "f5"
273 case '6': // 4 strings to match.
274 return Mips::D3; // "f6"
275 case '7': // 3 strings to match.
276 return Mips::F7; // "f7"
277 case '8': // 4 strings to match.
278 return Mips::D4; // "f8"
279 case '9': // 3 strings to match.
280 return Mips::F9; // "f9"
281 case 'p': // 2 strings to match.
282 return Mips::R30; // "fp"
283 }
284 break;
285 case 'g': // 2 strings to match.
286 if (Name[1] != 'p')
287 break;
288 return Mips::R28; // "gp"
289 case 'h': // 1 string to match.
290 if (Name[1] != 'i')
291 break;
292 return Mips::HI0_64; // "hi"
293 case 'l': // 1 string to match.
294 if (Name[1] != 'o')
295 break;
296 return Mips::LO0_64; // "lo"
297 case 'p': // 4 strings to match.
298 switch (Name[1]) {
299 default: break;
300 case '0': // 1 string to match.
301 return Mips::P0; // "p0"
302 case '1': // 1 string to match.
303 return Mips::P1; // "p1"
304 case '2': // 1 string to match.
305 return Mips::P2; // "p2"
306 case 'c': // 1 string to match.
307 return Mips::PC; // "pc"
308 }
309 break;
310 case 'r': // 2 strings to match.
311 if (Name[1] != 'a')
312 break;
313 return Mips::R31; // "ra"
314 case 's': // 2 strings to match.
315 if (Name[1] != 'p')
316 break;
317 return Mips::R29; // "sp"
318 case 'w': // 10 strings to match.
319 switch (Name[1]) {
320 default: break;
321 case '0': // 1 string to match.
322 return Mips::W0; // "w0"
323 case '1': // 1 string to match.
324 return Mips::W1; // "w1"
325 case '2': // 1 string to match.
326 return Mips::W2; // "w2"
327 case '3': // 1 string to match.
328 return Mips::W3; // "w3"
329 case '4': // 1 string to match.
330 return Mips::W4; // "w4"
331 case '5': // 1 string to match.
332 return Mips::W5; // "w5"
333 case '6': // 1 string to match.
334 return Mips::W6; // "w6"
335 case '7': // 1 string to match.
336 return Mips::W7; // "w7"
337 case '8': // 1 string to match.
338 return Mips::W8; // "w8"
339 case '9': // 1 string to match.
340 return Mips::W9; // "w9"
341 }
342 break;
343 }
344 break;
345 case 3: // 112 strings to match.
346 switch (Name[0]) {
347 default: break;
348 case 'a': // 13 strings to match.
349 if (Name[1] != 'c')
350 break;
351 switch (Name[2]) {
352 default: break;
353 case '0': // 4 strings to match.
354 return Mips::AC0; // "ac0"
355 case '1': // 3 strings to match.
356 return Mips::AC1; // "ac1"
357 case '2': // 3 strings to match.
358 return Mips::AC2; // "ac2"
359 case '3': // 3 strings to match.
360 return Mips::AC3; // "ac3"
361 }
362 break;
363 case 'f': // 77 strings to match.
364 switch (Name[1]) {
365 default: break;
366 case '1': // 35 strings to match.
367 switch (Name[2]) {
368 default: break;
369 case '0': // 4 strings to match.
370 return Mips::D5; // "f10"
371 case '1': // 3 strings to match.
372 return Mips::F11; // "f11"
373 case '2': // 4 strings to match.
374 return Mips::D6; // "f12"
375 case '3': // 3 strings to match.
376 return Mips::F13; // "f13"
377 case '4': // 4 strings to match.
378 return Mips::D7; // "f14"
379 case '5': // 3 strings to match.
380 return Mips::F15; // "f15"
381 case '6': // 4 strings to match.
382 return Mips::D8; // "f16"
383 case '7': // 3 strings to match.
384 return Mips::F17; // "f17"
385 case '8': // 4 strings to match.
386 return Mips::D9; // "f18"
387 case '9': // 3 strings to match.
388 return Mips::F19; // "f19"
389 }
390 break;
391 case '2': // 35 strings to match.
392 switch (Name[2]) {
393 default: break;
394 case '0': // 4 strings to match.
395 return Mips::D10; // "f20"
396 case '1': // 3 strings to match.
397 return Mips::F21; // "f21"
398 case '2': // 4 strings to match.
399 return Mips::D11; // "f22"
400 case '3': // 3 strings to match.
401 return Mips::F23; // "f23"
402 case '4': // 4 strings to match.
403 return Mips::D12; // "f24"
404 case '5': // 3 strings to match.
405 return Mips::F25; // "f25"
406 case '6': // 4 strings to match.
407 return Mips::D13; // "f26"
408 case '7': // 3 strings to match.
409 return Mips::F27; // "f27"
410 case '8': // 4 strings to match.
411 return Mips::D14; // "f28"
412 case '9': // 3 strings to match.
413 return Mips::F29; // "f29"
414 }
415 break;
416 case '3': // 7 strings to match.
417 switch (Name[2]) {
418 default: break;
419 case '0': // 4 strings to match.
420 return Mips::D15; // "f30"
421 case '1': // 3 strings to match.
422 return Mips::F31; // "f31"
423 }
424 break;
425 }
426 break;
427 case 'w': // 22 strings to match.
428 switch (Name[1]) {
429 default: break;
430 case '1': // 10 strings to match.
431 switch (Name[2]) {
432 default: break;
433 case '0': // 1 string to match.
434 return Mips::W10; // "w10"
435 case '1': // 1 string to match.
436 return Mips::W11; // "w11"
437 case '2': // 1 string to match.
438 return Mips::W12; // "w12"
439 case '3': // 1 string to match.
440 return Mips::W13; // "w13"
441 case '4': // 1 string to match.
442 return Mips::W14; // "w14"
443 case '5': // 1 string to match.
444 return Mips::W15; // "w15"
445 case '6': // 1 string to match.
446 return Mips::W16; // "w16"
447 case '7': // 1 string to match.
448 return Mips::W17; // "w17"
449 case '8': // 1 string to match.
450 return Mips::W18; // "w18"
451 case '9': // 1 string to match.
452 return Mips::W19; // "w19"
453 }
454 break;
455 case '2': // 10 strings to match.
456 switch (Name[2]) {
457 default: break;
458 case '0': // 1 string to match.
459 return Mips::W20; // "w20"
460 case '1': // 1 string to match.
461 return Mips::W21; // "w21"
462 case '2': // 1 string to match.
463 return Mips::W22; // "w22"
464 case '3': // 1 string to match.
465 return Mips::W23; // "w23"
466 case '4': // 1 string to match.
467 return Mips::W24; // "w24"
468 case '5': // 1 string to match.
469 return Mips::W25; // "w25"
470 case '6': // 1 string to match.
471 return Mips::W26; // "w26"
472 case '7': // 1 string to match.
473 return Mips::W27; // "w27"
474 case '8': // 1 string to match.
475 return Mips::W28; // "w28"
476 case '9': // 1 string to match.
477 return Mips::W29; // "w29"
478 }
479 break;
480 case '3': // 2 strings to match.
481 switch (Name[2]) {
482 default: break;
483 case '0': // 1 string to match.
484 return Mips::W30; // "w30"
485 case '1': // 1 string to match.
486 return Mips::W31; // "w31"
487 }
488 break;
489 }
490 break;
491 }
492 break;
493 case 4: // 13 strings to match.
494 switch (Name[0]) {
495 default: break;
496 case 'f': // 8 strings to match.
497 if (memcmp(Name.data()+1, "cc", 2) != 0)
498 break;
499 switch (Name[3]) {
500 default: break;
501 case '0': // 1 string to match.
502 return Mips::FCC0; // "fcc0"
503 case '1': // 1 string to match.
504 return Mips::FCC1; // "fcc1"
505 case '2': // 1 string to match.
506 return Mips::FCC2; // "fcc2"
507 case '3': // 1 string to match.
508 return Mips::FCC3; // "fcc3"
509 case '4': // 1 string to match.
510 return Mips::FCC4; // "fcc4"
511 case '5': // 1 string to match.
512 return Mips::FCC5; // "fcc5"
513 case '6': // 1 string to match.
514 return Mips::FCC6; // "fcc6"
515 case '7': // 1 string to match.
516 return Mips::FCC7; // "fcc7"
517 }
518 break;
519 case 'm': // 3 strings to match.
520 if (memcmp(Name.data()+1, "pl", 2) != 0)
521 break;
522 switch (Name[3]) {
523 default: break;
524 case '0': // 1 string to match.
525 return Mips::MPL0; // "mpl0"
526 case '1': // 1 string to match.
527 return Mips::MPL1; // "mpl1"
528 case '2': // 1 string to match.
529 return Mips::MPL2; // "mpl2"
530 }
531 break;
532 case 'z': // 2 strings to match.
533 if (memcmp(Name.data()+1, "ero", 3) != 0)
534 break;
535 return Mips::R0; // "zero"
536 }
537 break;
538 case 6: // 1 string to match.
539 if (memcmp(Name.data()+0, "hwr_cc", 6) != 0)
540 break;
541 return Mips::HWR2; // "hwr_cc"
542 case 9: // 1 string to match.
543 if (memcmp(Name.data()+0, "hwr_ccres", 9) != 0)
544 break;
545 return Mips::HWR3; // "hwr_ccres"
546 case 10: // 1 string to match.
547 if (memcmp(Name.data()+0, "hwr_cpunum", 10) != 0)
548 break;
549 return Mips::HWR0; // "hwr_cpunum"
550 case 14: // 1 string to match.
551 if (memcmp(Name.data()+0, "hwr_synci_step", 14) != 0)
552 break;
553 return Mips::HWR1; // "hwr_synci_step"
554 }
555 return Mips::NoRegister;
556}
557
558[[maybe_unused]] static MCRegister MatchRegisterAltName(StringRef Name, unsigned AltIdx) {
559 switch (AltIdx) {
560 default: break;
561 case Mips::NABIRegAltName: {
562 switch (Name.size()) {
563 default: break;
564 case 2: // 62 strings to match.
565 switch (Name[0]) {
566 default: break;
567 case 'a': // 18 strings to match.
568 switch (Name[1]) {
569 default: break;
570 case '0': // 2 strings to match.
571 return Mips::R4; // "a0"
572 case '1': // 2 strings to match.
573 return Mips::R5; // "a1"
574 case '2': // 2 strings to match.
575 return Mips::R6; // "a2"
576 case '3': // 2 strings to match.
577 return Mips::R7; // "a3"
578 case '4': // 2 strings to match.
579 return Mips::R8; // "a4"
580 case '5': // 2 strings to match.
581 return Mips::R9; // "a5"
582 case '6': // 2 strings to match.
583 return Mips::R10; // "a6"
584 case '7': // 2 strings to match.
585 return Mips::R11; // "a7"
586 case 't': // 2 strings to match.
587 return Mips::R1; // "at"
588 }
589 break;
590 case 'f': // 2 strings to match.
591 if (Name[1] != 'p')
592 break;
593 return Mips::R30; // "fp"
594 case 'g': // 2 strings to match.
595 if (Name[1] != 'p')
596 break;
597 return Mips::R28; // "gp"
598 case 'k': // 4 strings to match.
599 switch (Name[1]) {
600 default: break;
601 case '0': // 2 strings to match.
602 return Mips::R26; // "k0"
603 case '1': // 2 strings to match.
604 return Mips::R27; // "k1"
605 }
606 break;
607 case 'r': // 2 strings to match.
608 if (Name[1] != 'a')
609 break;
610 return Mips::R31; // "ra"
611 case 's': // 18 strings to match.
612 switch (Name[1]) {
613 default: break;
614 case '0': // 2 strings to match.
615 return Mips::R16; // "s0"
616 case '1': // 2 strings to match.
617 return Mips::R17; // "s1"
618 case '2': // 2 strings to match.
619 return Mips::R18; // "s2"
620 case '3': // 2 strings to match.
621 return Mips::R19; // "s3"
622 case '4': // 2 strings to match.
623 return Mips::R20; // "s4"
624 case '5': // 2 strings to match.
625 return Mips::R21; // "s5"
626 case '6': // 2 strings to match.
627 return Mips::R22; // "s6"
628 case '7': // 2 strings to match.
629 return Mips::R23; // "s7"
630 case 'p': // 2 strings to match.
631 return Mips::R29; // "sp"
632 }
633 break;
634 case 't': // 12 strings to match.
635 switch (Name[1]) {
636 default: break;
637 case '0': // 2 strings to match.
638 return Mips::R12; // "t0"
639 case '1': // 2 strings to match.
640 return Mips::R13; // "t1"
641 case '2': // 2 strings to match.
642 return Mips::R14; // "t2"
643 case '3': // 2 strings to match.
644 return Mips::R15; // "t3"
645 case '8': // 2 strings to match.
646 return Mips::R24; // "t8"
647 case '9': // 2 strings to match.
648 return Mips::R25; // "t9"
649 }
650 break;
651 case 'v': // 4 strings to match.
652 switch (Name[1]) {
653 default: break;
654 case '0': // 2 strings to match.
655 return Mips::R2; // "v0"
656 case '1': // 2 strings to match.
657 return Mips::R3; // "v1"
658 }
659 break;
660 }
661 break;
662 case 4: // 2 strings to match.
663 if (memcmp(Name.data()+0, "zero", 4) != 0)
664 break;
665 return Mips::R0; // "zero"
666 }
667 break;
668 }
669 case Mips::OABIRegAltName: {
670 switch (Name.size()) {
671 default: break;
672 case 2: // 62 strings to match.
673 switch (Name[0]) {
674 default: break;
675 case 'a': // 10 strings to match.
676 switch (Name[1]) {
677 default: break;
678 case '0': // 2 strings to match.
679 return Mips::R4; // "a0"
680 case '1': // 2 strings to match.
681 return Mips::R5; // "a1"
682 case '2': // 2 strings to match.
683 return Mips::R6; // "a2"
684 case '3': // 2 strings to match.
685 return Mips::R7; // "a3"
686 case 't': // 2 strings to match.
687 return Mips::R1; // "at"
688 }
689 break;
690 case 'f': // 2 strings to match.
691 if (Name[1] != 'p')
692 break;
693 return Mips::R30; // "fp"
694 case 'g': // 2 strings to match.
695 if (Name[1] != 'p')
696 break;
697 return Mips::R28; // "gp"
698 case 'k': // 4 strings to match.
699 switch (Name[1]) {
700 default: break;
701 case '0': // 2 strings to match.
702 return Mips::R26; // "k0"
703 case '1': // 2 strings to match.
704 return Mips::R27; // "k1"
705 }
706 break;
707 case 'r': // 2 strings to match.
708 if (Name[1] != 'a')
709 break;
710 return Mips::R31; // "ra"
711 case 's': // 18 strings to match.
712 switch (Name[1]) {
713 default: break;
714 case '0': // 2 strings to match.
715 return Mips::R16; // "s0"
716 case '1': // 2 strings to match.
717 return Mips::R17; // "s1"
718 case '2': // 2 strings to match.
719 return Mips::R18; // "s2"
720 case '3': // 2 strings to match.
721 return Mips::R19; // "s3"
722 case '4': // 2 strings to match.
723 return Mips::R20; // "s4"
724 case '5': // 2 strings to match.
725 return Mips::R21; // "s5"
726 case '6': // 2 strings to match.
727 return Mips::R22; // "s6"
728 case '7': // 2 strings to match.
729 return Mips::R23; // "s7"
730 case 'p': // 2 strings to match.
731 return Mips::R29; // "sp"
732 }
733 break;
734 case 't': // 20 strings to match.
735 switch (Name[1]) {
736 default: break;
737 case '0': // 2 strings to match.
738 return Mips::R8; // "t0"
739 case '1': // 2 strings to match.
740 return Mips::R9; // "t1"
741 case '2': // 2 strings to match.
742 return Mips::R10; // "t2"
743 case '3': // 2 strings to match.
744 return Mips::R11; // "t3"
745 case '4': // 2 strings to match.
746 return Mips::R12; // "t4"
747 case '5': // 2 strings to match.
748 return Mips::R13; // "t5"
749 case '6': // 2 strings to match.
750 return Mips::R14; // "t6"
751 case '7': // 2 strings to match.
752 return Mips::R15; // "t7"
753 case '8': // 2 strings to match.
754 return Mips::R24; // "t8"
755 case '9': // 2 strings to match.
756 return Mips::R25; // "t9"
757 }
758 break;
759 case 'v': // 4 strings to match.
760 switch (Name[1]) {
761 default: break;
762 case '0': // 2 strings to match.
763 return Mips::R2; // "v0"
764 case '1': // 2 strings to match.
765 return Mips::R3; // "v1"
766 }
767 break;
768 }
769 break;
770 case 4: // 2 strings to match.
771 if (memcmp(Name.data()+0, "zero", 4) != 0)
772 break;
773 return Mips::R0; // "zero"
774 }
775 break;
776 }
777 case Mips::PABIRegAltName: {
778 switch (Name.size()) {
779 default: break;
780 case 2: // 62 strings to match.
781 switch (Name[0]) {
782 default: break;
783 case 'a': // 18 strings to match.
784 switch (Name[1]) {
785 default: break;
786 case '0': // 2 strings to match.
787 return Mips::R4; // "a0"
788 case '1': // 2 strings to match.
789 return Mips::R5; // "a1"
790 case '2': // 2 strings to match.
791 return Mips::R6; // "a2"
792 case '3': // 2 strings to match.
793 return Mips::R7; // "a3"
794 case '4': // 2 strings to match.
795 return Mips::R8; // "a4"
796 case '5': // 2 strings to match.
797 return Mips::R9; // "a5"
798 case '6': // 2 strings to match.
799 return Mips::R10; // "a6"
800 case '7': // 2 strings to match.
801 return Mips::R11; // "a7"
802 case 't': // 2 strings to match.
803 return Mips::R1; // "at"
804 }
805 break;
806 case 'f': // 2 strings to match.
807 if (Name[1] != 'p')
808 break;
809 return Mips::R30; // "fp"
810 case 'g': // 2 strings to match.
811 if (Name[1] != 'p')
812 break;
813 return Mips::R28; // "gp"
814 case 'k': // 4 strings to match.
815 switch (Name[1]) {
816 default: break;
817 case '0': // 2 strings to match.
818 return Mips::R26; // "k0"
819 case '1': // 2 strings to match.
820 return Mips::R27; // "k1"
821 }
822 break;
823 case 'r': // 2 strings to match.
824 if (Name[1] != 'a')
825 break;
826 return Mips::R31; // "ra"
827 case 's': // 18 strings to match.
828 switch (Name[1]) {
829 default: break;
830 case '0': // 2 strings to match.
831 return Mips::R16; // "s0"
832 case '1': // 2 strings to match.
833 return Mips::R17; // "s1"
834 case '2': // 2 strings to match.
835 return Mips::R18; // "s2"
836 case '3': // 2 strings to match.
837 return Mips::R19; // "s3"
838 case '4': // 2 strings to match.
839 return Mips::R20; // "s4"
840 case '5': // 2 strings to match.
841 return Mips::R21; // "s5"
842 case '6': // 2 strings to match.
843 return Mips::R22; // "s6"
844 case '7': // 2 strings to match.
845 return Mips::R23; // "s7"
846 case 'p': // 2 strings to match.
847 return Mips::R29; // "sp"
848 }
849 break;
850 case 't': // 16 strings to match.
851 switch (Name[1]) {
852 default: break;
853 case '0': // 2 strings to match.
854 return Mips::R12; // "t0"
855 case '1': // 2 strings to match.
856 return Mips::R13; // "t1"
857 case '2': // 2 strings to match.
858 return Mips::R14; // "t2"
859 case '3': // 2 strings to match.
860 return Mips::R15; // "t3"
861 case '4': // 2 strings to match.
862 return Mips::R2; // "t4"
863 case '5': // 2 strings to match.
864 return Mips::R3; // "t5"
865 case '8': // 2 strings to match.
866 return Mips::R24; // "t8"
867 case '9': // 2 strings to match.
868 return Mips::R25; // "t9"
869 }
870 break;
871 }
872 break;
873 case 4: // 2 strings to match.
874 if (memcmp(Name.data()+0, "zero", 4) != 0)
875 break;
876 return Mips::R0; // "zero"
877 }
878 break;
879 }
880 case Mips::RegAliasName: {
881 switch (Name.size()) {
882 default: break;
883 case 2: // 2 strings to match.
884 switch (Name[0]) {
885 default: break;
886 case 'h': // 1 string to match.
887 if (Name[1] != 'i')
888 break;
889 return Mips::HI0; // "hi"
890 case 'l': // 1 string to match.
891 if (Name[1] != 'o')
892 break;
893 return Mips::LO0; // "lo"
894 }
895 break;
896 case 5: // 1 string to match.
897 if (memcmp(Name.data()+0, "msair", 5) != 0)
898 break;
899 return Mips::MSAIR; // "msair"
900 case 6: // 2 strings to match.
901 if (memcmp(Name.data()+0, "msa", 3) != 0)
902 break;
903 switch (Name[3]) {
904 default: break;
905 case 'c': // 1 string to match.
906 if (memcmp(Name.data()+4, "sr", 2) != 0)
907 break;
908 return Mips::MSACSR; // "msacsr"
909 case 'm': // 1 string to match.
910 if (memcmp(Name.data()+4, "ap", 2) != 0)
911 break;
912 return Mips::MSAMap; // "msamap"
913 }
914 break;
915 case 7: // 2 strings to match.
916 switch (Name[0]) {
917 default: break;
918 case 'h': // 1 string to match.
919 if (memcmp(Name.data()+1, "wr_ulr", 6) != 0)
920 break;
921 return Mips::HWR29; // "hwr_ulr"
922 case 'm': // 1 string to match.
923 if (memcmp(Name.data()+1, "sasave", 6) != 0)
924 break;
925 return Mips::MSASave; // "msasave"
926 }
927 break;
928 case 8: // 1 string to match.
929 if (memcmp(Name.data()+0, "msaunmap", 8) != 0)
930 break;
931 return Mips::MSAUnmap; // "msaunmap"
932 case 9: // 2 strings to match.
933 if (memcmp(Name.data()+0, "msa", 3) != 0)
934 break;
935 switch (Name[3]) {
936 default: break;
937 case 'a': // 1 string to match.
938 if (memcmp(Name.data()+4, "ccess", 5) != 0)
939 break;
940 return Mips::MSAAccess; // "msaaccess"
941 case 'm': // 1 string to match.
942 if (memcmp(Name.data()+4, "odify", 5) != 0)
943 break;
944 return Mips::MSAModify; // "msamodify"
945 }
946 break;
947 case 10: // 1 string to match.
948 if (memcmp(Name.data()+0, "msarequest", 10) != 0)
949 break;
950 return Mips::MSARequest; // "msarequest"
951 }
952 break;
953 }
954 }
955 return Mips::NoRegister;
956}
957
958#endif // GET_REGISTER_MATCHER
959
960
961#ifdef GET_SUBTARGET_FEATURE_NAME
962#undef GET_SUBTARGET_FEATURE_NAME
963
964// User-level names for subtarget features that participate in
965// instruction matching.
966static const char *getSubtargetFeatureName(uint64_t Val) {
967 switch(Val) {
968 case Feature_IsPTR64bitBit: return "";
969 case Feature_IsPTR32bitBit: return "";
970 case Feature_UseCompactBranchesBit: return "";
971 case Feature_HasMips2Bit: return "";
972 case Feature_HasMips3_32Bit: return "";
973 case Feature_HasMips3_32r2Bit: return "";
974 case Feature_HasMips3Bit: return "";
975 case Feature_NotMips3Bit: return "";
976 case Feature_HasMips4_32Bit: return "";
977 case Feature_NotMips4_32Bit: return "";
978 case Feature_HasMips4_32r2Bit: return "";
979 case Feature_HasMips5_32r2Bit: return "";
980 case Feature_HasMips32Bit: return "";
981 case Feature_HasMips32r2Bit: return "";
982 case Feature_HasMips32r5Bit: return "";
983 case Feature_HasMips32r6Bit: return "";
984 case Feature_NotMips32r6Bit: return "";
985 case Feature_IsGP64bitBit: return "";
986 case Feature_IsGP32bitBit: return "";
987 case Feature_HasMips64Bit: return "";
988 case Feature_NotMips64Bit: return "";
989 case Feature_HasMips64r2Bit: return "";
990 case Feature_HasMips64r5Bit: return "";
991 case Feature_HasMips64r6Bit: return "";
992 case Feature_NotMips64r6Bit: return "";
993 case Feature_InMips16ModeBit: return "";
994 case Feature_NotInMips16ModeBit: return "";
995 case Feature_HasCnMipsBit: return "";
996 case Feature_NotCnMipsBit: return "";
997 case Feature_HasCnMipsPBit: return "";
998 case Feature_NotCnMipsPBit: return "";
999 case Feature_IsSym32Bit: return "";
1000 case Feature_IsSym64Bit: return "";
1001 case Feature_HasStdEncBit: return "";
1002 case Feature_InMicroMipsBit: return "";
1003 case Feature_NotInMicroMipsBit: return "";
1004 case Feature_HasEVABit: return "";
1005 case Feature_HasMSABit: return "";
1006 case Feature_HasMadd4Bit: return "";
1007 case Feature_HasMTBit: return "";
1008 case Feature_UseIndirectJumpsHazardBit: return "";
1009 case Feature_NoIndirectJumpGuardsBit: return "";
1010 case Feature_IsR5900Bit: return "";
1011 case Feature_NotR5900Bit: return "";
1012 case Feature_HasCRCBit: return "";
1013 case Feature_HasVirtBit: return "";
1014 case Feature_HasGINVBit: return "";
1015 case Feature_IsFP64bitBit: return "";
1016 case Feature_NotFP64bitBit: return "";
1017 case Feature_IsSingleFloatBit: return "";
1018 case Feature_IsNotSingleFloatBit: return "";
1019 case Feature_IsNotSoftFloatBit: return "";
1020 case Feature_HasMips3DBit: return "";
1021 case Feature_HasDSPBit: return "";
1022 case Feature_HasDSPR2Bit: return "";
1023 case Feature_HasDSPR3Bit: return "";
1024 default: return "(unknown)";
1025 }
1026}
1027
1028#endif // GET_SUBTARGET_FEATURE_NAME
1029
1030
1031#ifdef GET_MATCHER_IMPLEMENTATION
1032#undef GET_MATCHER_IMPLEMENTATION
1033
1034enum {
1035 Tie0_1_1,
1036 Tie0_1_2,
1037};
1038
1039static const uint8_t TiedAsmOperandTable[][3] = {
1040 /* Tie0_1_1 */ { 0, 1, 1 },
1041 /* Tie0_1_2 */ { 0, 1, 2 },
1042};
1043
1044namespace {
1045enum OperatorConversionKind {
1046 CVT_Done,
1047 CVT_Reg,
1048 CVT_Tied,
1049 CVT_95_addGPR32AsmRegOperands,
1050 CVT_95_addAFGR64AsmRegOperands,
1051 CVT_95_addFGR64AsmRegOperands,
1052 CVT_95_addFGR32AsmRegOperands,
1053 CVT_95_addSImmOperands_LT_32_GT_,
1054 CVT_95_addMSA128AsmRegOperands,
1055 CVT_95_addSImmOperands_LT_16_GT_,
1056 CVT_95_Reg,
1057 CVT_95_addImmOperands,
1058 CVT_95_addGPRMM16AsmRegOperands,
1059 CVT_95_addConstantSImmOperands_LT_4_44__32_0_GT_,
1060 CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_,
1061 CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_,
1062 CVT_95_addUImmOperands_LT_16_GT_,
1063 CVT_95_addGPR64AsmRegOperands,
1064 CVT_95_addConstantUImmOperands_LT_8_44__32_0_GT_,
1065 CVT_regR0,
1066 CVT_95_addConstantUImmOperands_LT_5_44__32_32_44__32__MINUS_32_GT_,
1067 CVT_regFCC0,
1068 CVT_95_addFCCAsmRegOperands,
1069 CVT_95_addCOP2AsmRegOperands,
1070 CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_,
1071 CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_,
1072 CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_,
1073 CVT_imm_95_0,
1074 CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_,
1075 CVT_95_addPtrRegOperands,
1076 CVT_95_addConstantSImmOperands_LT_5_44__32_0_GT_,
1077 CVT_95_addCCRAsmRegOperands,
1078 CVT_95_addMSACtrlAsmRegOperands,
1079 CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_,
1080 CVT_95_addConstantUImmOperands_LT_5_44__32_33_GT_,
1081 CVT_95_addConstantUImmOperands_LT_5_44__32_32_GT_,
1082 CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_,
1083 CVT_95_addGPR32NonZeroAsmRegOperands,
1084 CVT_95_addGPR32ZeroAsmRegOperands,
1085 CVT_95_addMemOperands,
1086 CVT_95_addConstantUImmOperands_LT_2_44__32_1_GT_,
1087 CVT_95_addCOP0AsmRegOperands,
1088 CVT_regR0_64,
1089 CVT_95_addACC64DSPAsmRegOperands,
1090 CVT_95_addConstantUImmOperands_LT_1_GT_,
1091 CVT_regR31,
1092 CVT_regR31_64,
1093 CVT_95_addCOP3AsmRegOperands,
1094 CVT_95_addConstantSImmOperands_LT_10_44__32_0_GT_,
1095 CVT_95_addConstantUImmOperands_LT_32_GT_,
1096 CVT_95_addStrictlyAFGR64AsmRegOperands,
1097 CVT_95_addStrictlyFGR64AsmRegOperands,
1098 CVT_95_addStrictlyFGR32AsmRegOperands,
1099 CVT_95_addConstantUImmOperands_LT_7_44__32__MINUS_1_GT_,
1100 CVT_95_addRegListOperands,
1101 CVT_ConvertXWPOperands,
1102 CVT_regAC0,
1103 CVT_95_addGPRMM16AsmRegMovePPairFirstOperands,
1104 CVT_95_addGPRMM16AsmRegMovePPairSecondOperands,
1105 CVT_95_addGPRMM16AsmRegMovePOperands,
1106 CVT_95_addHI32DSPAsmRegOperands,
1107 CVT_95_addLO32DSPAsmRegOperands,
1108 CVT_regR16,
1109 CVT_95_addConstantUImmOperands_LT_7_44__32_0_GT_,
1110 CVT_95_addHWRegsAsmRegOperands,
1111 CVT_95_addGPRMM16AsmRegZeroOperands,
1112 CVT_95_addConstantUImmOperands_LT_20_44__32_0_GT_,
1113 CVT_95_addConstantSImmOperands_LT_6_44__32_0_GT_,
1114 CVT_imm_95_17,
1115 CVT_imm_95_16,
1116 CVT_imm_95_18,
1117 CVT_imm_95_19,
1118 CVT_imm_95_4,
1119 CVT_imm_95_2,
1120 CVT_imm_95_6,
1121 CVT_imm_95_5,
1122 CVT_imm_95_31,
1123 CVT_NUM_CONVERTERS
1124};
1125
1126enum InstructionConversionKind {
1127 Convert__GPR32AsmReg1_0__GPR32AsmReg1_1,
1128 Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1,
1129 Convert__FGR64AsmReg1_0__FGR64AsmReg1_1,
1130 Convert__FGR32AsmReg1_0__FGR32AsmReg1_1,
1131 Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1,
1132 Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1,
1133 Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2,
1134 Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2,
1135 Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2,
1136 Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2,
1137 Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2,
1138 Convert__FGR32AsmReg1_0__FGR32AsmReg1_2__FGR32AsmReg1_1,
1139 Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2,
1140 Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm161_1,
1141 Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm16_Relaxed1_1,
1142 Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2,
1143 Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm16_Relaxed1_2,
1144 Convert__SImm161_1,
1145 Convert__Reg1_0__SImm161_1,
1146 Convert__Reg1_0__SImm161_2,
1147 Convert__Reg1_0__Reg1_1__SImm161_2,
1148 Convert__Reg1_0__Tie0_1_1__SImm161_1,
1149 Convert__GPR32AsmReg1_0__Simm19_Lsl21_1,
1150 Convert__GPRMM16AsmReg1_0__Imm1_1,
1151 Convert__GPRMM16AsmReg1_0__UImm6Lsl21_1,
1152 Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Imm1_2,
1153 Convert__GPR32AsmReg1_0__Tie0_1_1__ConstantSImm4_01_1,
1154 Convert__Imm1_0,
1155 Convert__Reg1_0__Reg1_1__Reg1_2,
1156 Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__GPRMM16AsmReg1_2,
1157 Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2,
1158 Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__ConstantUImm2_01_3,
1159 Convert__GPR32AsmReg1_0__SImm161_1,
1160 Convert__Reg1_0__Tie0_1_1__Reg1_1,
1161 Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1,
1162 Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1,
1163 Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2,
1164 Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2,
1165 Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Tie0_1_1,
1166 Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm8_01_2,
1167 Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Tie0_1_1,
1168 Convert__regR0__regR0__JumpTarget1_0,
1169 Convert__JumpTarget1_0,
1170 Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1,
1171 Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2,
1172 Convert__regR0__JumpTarget1_0,
1173 Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm2_01_2__Tie0_1_1,
1174 Convert__GPR64AsmReg1_0__ConstantUImm5_32_Norm1_1__JumpTarget1_2,
1175 Convert__GPR64AsmReg1_0__ConstantUImm5_0_Report_UImm61_1__JumpTarget1_2,
1176 Convert__GPR64AsmReg1_0__ConstantUImm5_01_1__JumpTarget1_2,
1177 Convert__FGR32AsmReg1_0__JumpTarget1_1,
1178 Convert__regFCC0__JumpTarget1_0,
1179 Convert__FCCAsmReg1_0__JumpTarget1_1,
1180 Convert__COP2AsmReg1_0__JumpTarget1_1,
1181 Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2,
1182 Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2,
1183 Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2,
1184 Convert__GPR32AsmReg1_0__ConstantImm1_1__JumpTarget1_2,
1185 Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2,
1186 Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__JumpTarget1_2,
1187 Convert__Reg1_0__JumpTarget1_1,
1188 Convert__GPR32AsmReg1_0__regR0__JumpTarget1_1,
1189 Convert__GPRMM16AsmReg1_0__JumpTarget1_1,
1190 Convert__GPR32AsmReg1_0__JumpTarget1_1,
1191 Convert__GPR64AsmReg1_0__JumpTarget1_1,
1192 Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2,
1193 Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm3_01_2,
1194 Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm6_01_2,
1195 Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm4_01_2,
1196 Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm5_01_2,
1197 Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm8_01_2,
1198 Convert__MSA128AsmReg1_0__JumpTarget1_1,
1199 Convert__imm_95_0__imm_95_0,
1200 Convert_NoOperands,
1201 Convert__ConstantUImm10_01_0__imm_95_0,
1202 Convert__ConstantUImm10_01_0__ConstantUImm10_01_1,
1203 Convert__ConstantUImm4_01_0,
1204 Convert__SImm161_0,
1205 Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1,
1206 Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1,
1207 Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2,
1208 Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2,
1209 Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1,
1210 Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2,
1211 Convert__PtrReg1_3__SImmOffset9_01_1__ConstantUImm5_01_0,
1212 Convert__PtrReg1_3__SImmPtr1_1__ConstantUImm5_01_0,
1213 Convert__PtrReg1_3__AnyOffset1_1__ConstantUImm5_01_0,
1214 Convert__FGR64AsmReg1_0__FGR32AsmReg1_1,
1215 Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1,
1216 Convert__FGR32AsmReg1_0__FGR64AsmReg1_1,
1217 Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2,
1218 Convert__GPR32AsmReg1_0__CCRAsmReg1_1,
1219 Convert__GPR32AsmReg1_0__COP2AsmReg1_1,
1220 Convert__GPR32AsmReg1_0__MSACtrlAsmReg1_1,
1221 Convert__GPR32AsmReg1_0__FGR32AsmReg1_1,
1222 Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1__ConstantUImm5_01_2,
1223 Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_32_Norm1_1__ConstantUImm5_01_2,
1224 Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_01_3,
1225 Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_32_Norm1_2__ConstantUImm5_01_3,
1226 Convert__Reg1_0__Reg1_1,
1227 Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_3,
1228 Convert__GPR64AsmReg1_0__MSA128AsmReg1_1__ConstantUImm1_01_3,
1229 Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_3,
1230 Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm2_01_3,
1231 Convert__CCRAsmReg1_1__GPR32AsmReg1_0,
1232 Convert__COP2AsmReg1_1__GPR32AsmReg1_0,
1233 Convert__MSACtrlAsmReg1_0__GPR32AsmReg1_1,
1234 Convert__FGR32AsmReg1_1__GPR32AsmReg1_0,
1235 Convert__AFGR64AsmReg1_0__FGR32AsmReg1_1,
1236 Convert__FGR64AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2,
1237 Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__SImm161_1,
1238 Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm161_2,
1239 Convert__GPR64AsmReg1_0__Tie0_1_2__UImm16_AltRelaxed1_2,
1240 Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2__ConstantUImm3_01_3,
1241 Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__UImm161_2,
1242 Convert__GPR64AsmReg1_0__GPR64AsmReg1_1,
1243 Convert__GPR64AsmReg1_1__GPR64AsmReg1_2,
1244 Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_331_3,
1245 Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_321_2__ConstantUImm5_11_3,
1246 Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_0_Report_UImm61_2__ConstantUImm5_Plus1_Report_UImm61_3,
1247 Convert__regR0,
1248 Convert__GPR32AsmReg1_0,
1249 Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImmRange2_641_3__Tie0_1_1,
1250 Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_321_2__ConstantUImm5_11_3__Tie0_1_1,
1251 Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2__ConstantUImm5_11_3__Tie0_1_1,
1252 Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm321_1,
1253 Convert__GPR32NonZeroAsmReg1_0__GPR32NonZeroAsmReg1_0__GPR32AsmReg1_1,
1254 Convert__GPR32ZeroAsmReg1_0__GPR32AsmReg1_1,
1255 Convert__Reg1_1__Reg1_2,
1256 Convert__GPR32AsmReg1_1__GPR32AsmReg1_2,
1257 Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm321_2,
1258 Convert__GPR32NonZeroAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2,
1259 Convert__GPR64AsmReg1_0__Imm1_1,
1260 Convert__GPR64AsmReg1_0__Mem2_1,
1261 Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2__ConstantUImm2_11_3,
1262 Convert__GPR64AsmReg1_0__COP0AsmReg1_1__imm_95_0,
1263 Convert__GPR64AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2,
1264 Convert__GPR64AsmReg1_0__FGR64AsmReg1_1,
1265 Convert__GPR64AsmReg1_0__COP2AsmReg1_1__imm_95_0,
1266 Convert__GPR64AsmReg1_0__UImm161_1,
1267 Convert__GPR64AsmReg1_0__COP2AsmReg1_1__ConstantUImm3_01_2,
1268 Convert__COP0AsmReg1_1__GPR64AsmReg1_0__imm_95_0,
1269 Convert__COP0AsmReg1_1__GPR64AsmReg1_0__ConstantUImm3_01_2,
1270 Convert__FGR64AsmReg1_1__GPR64AsmReg1_0,
1271 Convert__COP2AsmReg1_1__GPR64AsmReg1_0__imm_95_0,
1272 Convert__COP2AsmReg1_1__GPR64AsmReg1_0__ConstantUImm3_01_2,
1273 Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm32_Relaxed1_2,
1274 Convert__GPR64AsmReg1_0__regR0_64__GPR64AsmReg1_0,
1275 Convert__GPR64AsmReg1_0__regR0_64__GPR64AsmReg1_1,
1276 Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1,
1277 Convert__GPR64AsmReg1_0__GPR64AsmReg1_0,
1278 Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__SImm32_Relaxed1_1,
1279 Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm6_01_1,
1280 Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2,
1281 Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1,
1282 Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2,
1283 Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2,
1284 Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR32AsmReg1_1,
1285 Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__InvNum1_1,
1286 Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__InvNum1_2,
1287 Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3,
1288 Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2,
1289 Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2,
1290 Convert__MSA128AsmReg1_0__MSA128AsmReg1_1,
1291 Convert__MSA128AsmReg1_0__GPR32AsmReg1_1,
1292 Convert__MSA128AsmReg1_0__GPR64AsmReg1_1,
1293 Convert__GPR32AsmReg1_1__GPR32AsmReg1_0__GPR32AsmReg1_2,
1294 Convert__GPR32AsmReg1_0__ConstantUImm2_01_1,
1295 Convert__imm_95_0,
1296 Convert__ConstantUImm10_01_0,
1297 Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3__Tie0_1_1,
1298 Convert__MSA128AsmReg1_0__Tie0_1_1__GPR32AsmReg1_4__ConstantUImm4_01_2,
1299 Convert__MSA128AsmReg1_0__Tie0_1_1__GPR64AsmReg1_4__ConstantUImm1_01_2,
1300 Convert__MSA128AsmReg1_0__Tie0_1_1__GPR32AsmReg1_4__ConstantUImm3_01_2,
1301 Convert__MSA128AsmReg1_0__Tie0_1_1__GPR32AsmReg1_4__ConstantUImm2_01_2,
1302 Convert__GPR32AsmReg1_0__Tie0_1_1__GPR32AsmReg1_1,
1303 Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm4_01_2__MSA128AsmReg1_4__ConstantImmz1_6,
1304 Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm1_01_2__MSA128AsmReg1_4__ConstantImmz1_6,
1305 Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm3_01_2__MSA128AsmReg1_4__ConstantImmz1_6,
1306 Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm2_01_2__MSA128AsmReg1_4__ConstantImmz1_6,
1307 Convert__regR31__GPR32AsmReg1_0,
1308 Convert__regR31_64__GPR64AsmReg1_0,
1309 Convert__Reg1_0,
1310 Convert__GPR32AsmReg1_0__imm_95_0,
1311 Convert__GPR64AsmReg1_0__imm_95_0,
1312 Convert__regR0__GPR32AsmReg1_0,
1313 Convert__GPR64AsmReg1_0,
1314 Convert__regR0_64__GPR64AsmReg1_0,
1315 Convert__UImm5Lsl21_0,
1316 Convert__AFGR64AsmReg1_0__PtrReg1_3__SImmOffset16_01_1,
1317 Convert__FGR64AsmReg1_0__PtrReg1_3__SImmOffset16_01_1,
1318 Convert__FGR32AsmReg1_0__PtrReg1_3__SImmOffset16_01_1,
1319 Convert__GPR32AsmReg1_0__Imm1_1,
1320 Convert__GPR32AsmReg1_0__Mem2_1,
1321 Convert__GPR32AsmReg1_0__PtrReg1_3__SImmOffset16_01_1,
1322 Convert__GPR32AsmReg1_0__PtrReg1_3__SImmPtr1_1,
1323 Convert__GPR32AsmReg1_0__PtrReg1_3__SImmOffset9_01_1,
1324 Convert__GPR32AsmReg1_0__PtrReg1_3__AnyOffset1_1,
1325 Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_3__UImmOffset4_0Minus11_1,
1326 Convert__GPR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1,
1327 Convert__GPR64AsmReg1_0__PtrReg1_3__SImmPtr1_1,
1328 Convert__MSA128AsmReg1_0__PtrReg1_3__SImmOffset10_01_1,
1329 Convert__MSA128AsmReg1_0__PtrReg1_3__SImmOffset10_31_1,
1330 Convert__MSA128AsmReg1_0__PtrReg1_3__SImmOffset10_11_1,
1331 Convert__MSA128AsmReg1_0__PtrReg1_3__SImmOffset10_21_1,
1332 Convert__COP2AsmReg1_0__PtrReg1_3__SImmOffset11_01_1,
1333 Convert__COP2AsmReg1_0__PtrReg1_3__SImmOffset16_01_1,
1334 Convert__COP3AsmReg1_0__PtrReg1_3__AnyOffset1_1,
1335 Convert__MSA128AsmReg1_0__ConstantSImm10_01_1,
1336 Convert__GPR64AsmReg1_0__PtrReg1_3__AnyOffset1_1__Tie0_1_1,
1337 Convert__GPR64AsmReg1_0__Simm18_Lsl31_1,
1338 Convert__AFGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1,
1339 Convert__FGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1,
1340 Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_3__UImmOffset4_101_1,
1341 Convert__GPR32AsmReg1_0__UImm32_Coerced1_1,
1342 Convert__StrictlyAFGR64AsmReg1_0__Imm1_1,
1343 Convert__StrictlyFGR64AsmReg1_0__Imm1_1,
1344 Convert__StrictlyFGR32AsmReg1_0__Imm1_1,
1345 Convert__GPRMM16AsmReg1_0__UImm7_N11_1,
1346 Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__ConstantUImm2_11_3,
1347 Convert__GPR32AsmReg1_2__GPR32AsmReg1_1__GPR32AsmReg1_0__ConstantUImm2_11_3,
1348 Convert__GPR32AsmReg1_0__UImm161_1,
1349 Convert__GPR32AsmReg1_0__UImm16_Relaxed1_1,
1350 Convert__Reg1_0__Imm1_1,
1351 Convert__Reg1_0__Reg1_3__SImm161_1,
1352 Convert__GPR32AsmReg1_0__MemBaseSP1_3__UImmOffset5_201_1,
1353 Convert__GPRMM16AsmReg1_0__MemBaseGP1_3__SImmOffset7_21_1,
1354 Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_3__UImmOffset4_201_1,
1355 Convert__GPR32AsmReg1_0__PtrReg1_3__AnyOffset1_1__Tie0_1_1,
1356 Convert__GPR32AsmReg1_0__PtrReg1_3__SImmOffset9_01_1__Tie0_1_1,
1357 Convert__RegList1_0__PtrReg1_3__AnyOffset1_1,
1358 Convert__RegList161_0__MemBaseSP1_3__UImmOffset4_201_1,
1359 Convert__RegList161_0__MemBaseSP1_3__UImmOffset6_001_1,
1360 ConvertCustom_ConvertXWPOperands,
1361 Convert__GPR32AsmReg1_0__PtrReg1_3__SImmOffset12_01_1,
1362 Convert__GPR64AsmReg1_0__PtrReg1_3__AnyOffset1_1,
1363 Convert__FGR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1,
1364 Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2__AFGR64AsmReg1_3,
1365 Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2__FGR64AsmReg1_3,
1366 Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2__FGR32AsmReg1_3,
1367 Convert__FGR64AsmReg1_0__Tie0_1_1__FGR64AsmReg1_1__FGR64AsmReg1_2,
1368 Convert__FGR32AsmReg1_0__Tie0_1_1__FGR32AsmReg1_1__FGR32AsmReg1_2,
1369 Convert__GPR32AsmReg1_0__COP0AsmReg1_1__imm_95_0,
1370 Convert__GPR32AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2,
1371 Convert__GPR32AsmReg1_0__FGR64AsmReg1_1,
1372 Convert__GPR32AsmReg1_0__COP2AsmReg1_1__imm_95_0,
1373 Convert__GPR32AsmReg1_0__COP2AsmReg1_1__ConstantUImm3_01_2,
1374 Convert__GPR32AsmReg1_0__AFGR64AsmReg1_1,
1375 Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1,
1376 Convert__GPR32AsmReg1_0__regAC0,
1377 Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0,
1378 Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm1_01_2__ConstantUImm3_01_3__ConstantUImm1_01_4,
1379 Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__regR0,
1380 Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__regR0_64,
1381 Convert__GPRMM16AsmRegMovePPairFirst1_0__GPRMM16AsmRegMovePPairSecond1_1__GPRMM16AsmRegMoveP1_2__GPRMM16AsmRegMoveP1_3,
1382 Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1,
1383 Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__FCCAsmReg1_2__Tie0_1_1,
1384 Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FCCAsmReg1_2__Tie0_1_1,
1385 Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1,
1386 Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1,
1387 Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1,
1388 Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1,
1389 Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1,
1390 Convert__COP0AsmReg1_1__GPR32AsmReg1_0__imm_95_0,
1391 Convert__COP0AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2,
1392 Convert__FGR64AsmReg1_1__GPR32AsmReg1_0,
1393 Convert__COP2AsmReg1_1__GPR32AsmReg1_0__imm_95_0,
1394 Convert__COP2AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2,
1395 Convert__AFGR64AsmReg1_1__Tie0_1_1__GPR32AsmReg1_0,
1396 Convert__FGR64AsmReg1_1__Tie0_1_1__GPR32AsmReg1_0,
1397 Convert__HI32DSPAsmReg1_1__GPR32AsmReg1_0,
1398 Convert__ACC64DSPAsmReg1_1__GPR32AsmReg1_0__Tie0_1_1,
1399 Convert__LO32DSPAsmReg1_1__GPR32AsmReg1_0,
1400 Convert__regAC0__GPR32AsmReg1_0,
1401 Convert__ACC64DSPAsmReg1_1__GPR32AsmReg1_0,
1402 Convert__GPR32AsmReg1_1__GPR32AsmReg1_0,
1403 Convert__GPR32AsmReg1_1__GPR32AsmReg1_0__ConstantUImm1_01_2__ConstantUImm3_01_3__ConstantUImm1_01_4,
1404 Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2,
1405 Convert__regR0__imm_95_0,
1406 Convert__GPR32AsmReg1_0__regR0__GPR32AsmReg1_0,
1407 Convert__GPR32AsmReg1_0__regR0__GPR32AsmReg1_1,
1408 Convert__regR0__regR0__imm_95_0,
1409 Convert__regR0__regR16,
1410 Convert__regR0__regR0,
1411 Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__regR0,
1412 Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1,
1413 Convert__GPR32AsmReg1_0__GPR32AsmReg1_0,
1414 Convert__GPR32AsmReg1_3__GPR32AsmReg1_1__ConstantUImm5_01_0,
1415 Convert__GPR32AsmReg1_0__ConstantUImm7_01_1,
1416 Convert__GPR32AsmReg1_0__ConstantUImm10_01_1,
1417 Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__imm_95_0,
1418 Convert__GPR64AsmReg1_0__HWRegsAsmReg1_1__imm_95_0,
1419 Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__ConstantUImm3_01_2,
1420 Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__ConstantUImm8_01_2,
1421 Convert__GPR32AsmReg1_0__ConstantSImm10_01_1,
1422 Convert__GPR32AsmReg1_0__ConstantUImm8_01_1,
1423 Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1,
1424 Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2,
1425 Convert__GPR64AsmReg1_0__GPR64AsmReg1_2,
1426 Convert__GPRMM16AsmRegZero1_0__GPRMM16AsmReg1_3__UImmOffset4_001_1,
1427 Convert__GPR32AsmReg1_0__Tie0_1_1__PtrReg1_3__SImmOffset9_01_1,
1428 Convert__GPR32AsmReg1_0__Tie0_1_1__PtrReg1_3__SImmPtr1_1,
1429 Convert__GPR32AsmReg1_0__Tie0_1_1__PtrReg1_3__AnyOffset1_1,
1430 Convert__GPR64AsmReg1_0__Tie0_1_1__PtrReg1_3__SImmPtr1_1,
1431 Convert__GPR64AsmReg1_0__Tie0_1_1__PtrReg1_3__AnyOffset1_1,
1432 Convert__ConstantUImm20_01_0,
1433 Convert__Reg1_0__Tie0_1_1,
1434 Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantSImm10_01_1,
1435 Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantSImm10_01_2,
1436 Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm32_Coerced1_1,
1437 Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm32_Coerced1_2,
1438 Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_0,
1439 Convert__GPR32AsmReg1_0__GPR32AsmReg1_2__GPR32AsmReg1_1,
1440 Convert__GPRMM16AsmRegZero1_0__GPRMM16AsmReg1_3__UImmOffset4_101_1,
1441 Convert__ACC64DSPAsmReg1_0__ConstantSImm6_01_1__Tie0_1_1,
1442 Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__Tie0_1_1,
1443 Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2,
1444 Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2,
1445 Convert__UImm161_0,
1446 Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__GPR32AsmReg1_3,
1447 Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm4_01_3,
1448 Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm1_01_3,
1449 Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm3_01_3,
1450 Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm2_01_3,
1451 Convert__Reg1_0__Reg1_1__ConstantUImm5_01_2,
1452 Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__GPR32AsmReg1_3,
1453 Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_3,
1454 Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm1_01_3,
1455 Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_3,
1456 Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm2_01_3,
1457 Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__InvNum1_1,
1458 Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__InvNum1_2,
1459 Convert__GPRMM16AsmRegZero1_0__GPRMM16AsmReg1_3__UImmOffset4_201_1,
1460 Convert__ConstantUImm5_01_0,
1461 Convert__imm_95_17,
1462 Convert__imm_95_16,
1463 Convert__imm_95_18,
1464 Convert__imm_95_19,
1465 Convert__imm_95_4,
1466 Convert__PtrReg1_2__SImmOffset16_01_0,
1467 Convert__imm_95_2,
1468 Convert__imm_95_6,
1469 Convert__imm_95_5,
1470 Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm10_01_2,
1471 Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1__GPR32AsmReg1_2,
1472 Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__GPR32AsmReg1_2,
1473 Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__GPR32AsmReg1_2,
1474 Convert__GPR32AsmReg1_0__imm_95_31,
1475 CVT_NUM_SIGNATURES
1476};
1477
1478} // end anonymous namespace
1479
1480static const uint8_t ConversionTable[CVT_NUM_SIGNATURES][11] = {
1481 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1
1482 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
1483 // Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1
1484 { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_Done },
1485 // Convert__FGR64AsmReg1_0__FGR64AsmReg1_1
1486 { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_Done },
1487 // Convert__FGR32AsmReg1_0__FGR32AsmReg1_1
1488 { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_Done },
1489 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1
1490 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
1491 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1
1492 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addSImmOperands_LT_32_GT_, 2, CVT_Done },
1493 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2
1494 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done },
1495 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2
1496 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addSImmOperands_LT_32_GT_, 3, CVT_Done },
1497 // Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2
1498 { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_95_addAFGR64AsmRegOperands, 3, CVT_Done },
1499 // Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2
1500 { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addFGR64AsmRegOperands, 3, CVT_Done },
1501 // Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2
1502 { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addFGR32AsmRegOperands, 3, CVT_Done },
1503 // Convert__FGR32AsmReg1_0__FGR32AsmReg1_2__FGR32AsmReg1_1
1504 { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 3, CVT_95_addFGR32AsmRegOperands, 2, CVT_Done },
1505 // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2
1506 { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addMSA128AsmRegOperands, 3, CVT_Done },
1507 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm161_1
1508 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addSImmOperands_LT_16_GT_, 2, CVT_Done },
1509 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm16_Relaxed1_1
1510 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addSImmOperands_LT_16_GT_, 2, CVT_Done },
1511 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2
1512 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addSImmOperands_LT_16_GT_, 3, CVT_Done },
1513 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm16_Relaxed1_2
1514 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addSImmOperands_LT_16_GT_, 3, CVT_Done },
1515 // Convert__SImm161_1
1516 { CVT_95_addSImmOperands_LT_16_GT_, 2, CVT_Done },
1517 // Convert__Reg1_0__SImm161_1
1518 { CVT_95_Reg, 1, CVT_95_addSImmOperands_LT_16_GT_, 2, CVT_Done },
1519 // Convert__Reg1_0__SImm161_2
1520 { CVT_95_Reg, 1, CVT_95_addSImmOperands_LT_16_GT_, 3, CVT_Done },
1521 // Convert__Reg1_0__Reg1_1__SImm161_2
1522 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addSImmOperands_LT_16_GT_, 3, CVT_Done },
1523 // Convert__Reg1_0__Tie0_1_1__SImm161_1
1524 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addSImmOperands_LT_16_GT_, 2, CVT_Done },
1525 // Convert__GPR32AsmReg1_0__Simm19_Lsl21_1
1526 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
1527 // Convert__GPRMM16AsmReg1_0__Imm1_1
1528 { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
1529 // Convert__GPRMM16AsmReg1_0__UImm6Lsl21_1
1530 { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
1531 // Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Imm1_2
1532 { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addGPRMM16AsmRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
1533 // Convert__GPR32AsmReg1_0__Tie0_1_1__ConstantSImm4_01_1
1534 { CVT_95_addGPR32AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addConstantSImmOperands_LT_4_44__32_0_GT_, 2, CVT_Done },
1535 // Convert__Imm1_0
1536 { CVT_95_addImmOperands, 1, CVT_Done },
1537 // Convert__Reg1_0__Reg1_1__Reg1_2
1538 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Done },
1539 // Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__GPRMM16AsmReg1_2
1540 { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addGPRMM16AsmRegOperands, 2, CVT_95_addGPRMM16AsmRegOperands, 3, CVT_Done },
1541 // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2
1542 { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done },
1543 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__ConstantUImm2_01_3
1544 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 4, CVT_Done },
1545 // Convert__GPR32AsmReg1_0__SImm161_1
1546 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addSImmOperands_LT_16_GT_, 2, CVT_Done },
1547 // Convert__Reg1_0__Tie0_1_1__Reg1_1
1548 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_Done },
1549 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1
1550 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addUImmOperands_LT_16_GT_, 2, CVT_Done },
1551 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1
1552 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
1553 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2
1554 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addUImmOperands_LT_16_GT_, 3, CVT_Done },
1555 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2
1556 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
1557 // Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Tie0_1_1
1558 { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addGPRMM16AsmRegOperands, 2, CVT_Tied, Tie0_1_1, CVT_Done },
1559 // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm8_01_2
1560 { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_8_44__32_0_GT_, 3, CVT_Done },
1561 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Tie0_1_1
1562 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Tied, Tie0_1_1, CVT_Done },
1563 // Convert__regR0__regR0__JumpTarget1_0
1564 { CVT_regR0, 0, CVT_regR0, 0, CVT_95_addImmOperands, 1, CVT_Done },
1565 // Convert__JumpTarget1_0
1566 { CVT_95_addImmOperands, 1, CVT_Done },
1567 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1
1568 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_Done },
1569 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2
1570 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 3, CVT_Done },
1571 // Convert__regR0__JumpTarget1_0
1572 { CVT_regR0, 0, CVT_95_addImmOperands, 1, CVT_Done },
1573 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm2_01_2__Tie0_1_1
1574 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 3, CVT_Tied, Tie0_1_1, CVT_Done },
1575 // Convert__GPR64AsmReg1_0__ConstantUImm5_32_Norm1_1__JumpTarget1_2
1576 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_5_44__32_32_44__32__MINUS_32_GT_, 2, CVT_95_addImmOperands, 3, CVT_Done },
1577 // Convert__GPR64AsmReg1_0__ConstantUImm5_0_Report_UImm61_1__JumpTarget1_2
1578 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 2, CVT_95_addImmOperands, 3, CVT_Done },
1579 // Convert__GPR64AsmReg1_0__ConstantUImm5_01_1__JumpTarget1_2
1580 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 2, CVT_95_addImmOperands, 3, CVT_Done },
1581 // Convert__FGR32AsmReg1_0__JumpTarget1_1
1582 { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
1583 // Convert__regFCC0__JumpTarget1_0
1584 { CVT_regFCC0, 0, CVT_95_addImmOperands, 1, CVT_Done },
1585 // Convert__FCCAsmReg1_0__JumpTarget1_1
1586 { CVT_95_addFCCAsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
1587 // Convert__COP2AsmReg1_0__JumpTarget1_1
1588 { CVT_95_addCOP2AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
1589 // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2
1590 { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
1591 // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2
1592 { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_, 3, CVT_Done },
1593 // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2
1594 { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 3, CVT_Done },
1595 // Convert__GPR32AsmReg1_0__ConstantImm1_1__JumpTarget1_2
1596 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
1597 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2
1598 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
1599 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__JumpTarget1_2
1600 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
1601 // Convert__Reg1_0__JumpTarget1_1
1602 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
1603 // Convert__GPR32AsmReg1_0__regR0__JumpTarget1_1
1604 { CVT_95_addGPR32AsmRegOperands, 1, CVT_regR0, 0, CVT_95_addImmOperands, 2, CVT_Done },
1605 // Convert__GPRMM16AsmReg1_0__JumpTarget1_1
1606 { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
1607 // Convert__GPR32AsmReg1_0__JumpTarget1_1
1608 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
1609 // Convert__GPR64AsmReg1_0__JumpTarget1_1
1610 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
1611 // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2
1612 { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addMSA128AsmRegOperands, 3, CVT_Done },
1613 // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm3_01_2
1614 { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
1615 // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm6_01_2
1616 { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_, 3, CVT_Done },
1617 // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm4_01_2
1618 { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 3, CVT_Done },
1619 // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm5_01_2
1620 { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done },
1621 // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm8_01_2
1622 { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_8_44__32_0_GT_, 3, CVT_Done },
1623 // Convert__MSA128AsmReg1_0__JumpTarget1_1
1624 { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
1625 // Convert__imm_95_0__imm_95_0
1626 { CVT_imm_95_0, 0, CVT_imm_95_0, 0, CVT_Done },
1627 // Convert_NoOperands
1628 { CVT_Done },
1629 // Convert__ConstantUImm10_01_0__imm_95_0
1630 { CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_, 1, CVT_imm_95_0, 0, CVT_Done },
1631 // Convert__ConstantUImm10_01_0__ConstantUImm10_01_1
1632 { CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_, 1, CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_, 2, CVT_Done },
1633 // Convert__ConstantUImm4_01_0
1634 { CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 1, CVT_Done },
1635 // Convert__SImm161_0
1636 { CVT_95_addSImmOperands_LT_16_GT_, 1, CVT_Done },
1637 // Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1
1638 { CVT_regFCC0, 0, CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_Done },
1639 // Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1
1640 { CVT_regFCC0, 0, CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_Done },
1641 // Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2
1642 { CVT_95_addFCCAsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_95_addAFGR64AsmRegOperands, 3, CVT_Done },
1643 // Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2
1644 { CVT_95_addFCCAsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addFGR64AsmRegOperands, 3, CVT_Done },
1645 // Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1
1646 { CVT_regFCC0, 0, CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_Done },
1647 // Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2
1648 { CVT_95_addFCCAsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addFGR32AsmRegOperands, 3, CVT_Done },
1649 // Convert__PtrReg1_3__SImmOffset9_01_1__ConstantUImm5_01_0
1650 { CVT_95_addPtrRegOperands, 4, CVT_95_addImmOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 1, CVT_Done },
1651 // Convert__PtrReg1_3__SImmPtr1_1__ConstantUImm5_01_0
1652 { CVT_95_addPtrRegOperands, 4, CVT_95_addImmOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 1, CVT_Done },
1653 // Convert__PtrReg1_3__AnyOffset1_1__ConstantUImm5_01_0
1654 { CVT_95_addPtrRegOperands, 4, CVT_95_addImmOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 1, CVT_Done },
1655 // Convert__FGR64AsmReg1_0__FGR32AsmReg1_1
1656 { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_Done },
1657 // Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1
1658 { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_Done },
1659 // Convert__FGR32AsmReg1_0__FGR64AsmReg1_1
1660 { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_Done },
1661 // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2
1662 { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantSImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done },
1663 // Convert__GPR32AsmReg1_0__CCRAsmReg1_1
1664 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addCCRAsmRegOperands, 2, CVT_Done },
1665 // Convert__GPR32AsmReg1_0__COP2AsmReg1_1
1666 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addCOP2AsmRegOperands, 2, CVT_Done },
1667 // Convert__GPR32AsmReg1_0__MSACtrlAsmReg1_1
1668 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMSACtrlAsmRegOperands, 2, CVT_Done },
1669 // Convert__GPR32AsmReg1_0__FGR32AsmReg1_1
1670 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_Done },
1671 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1__ConstantUImm5_01_2
1672 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done },
1673 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_32_Norm1_1__ConstantUImm5_01_2
1674 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_5_44__32_32_44__32__MINUS_32_GT_, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done },
1675 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_01_3
1676 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 4, CVT_Done },
1677 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_32_Norm1_2__ConstantUImm5_01_3
1678 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_32_44__32__MINUS_32_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 4, CVT_Done },
1679 // Convert__Reg1_0__Reg1_1
1680 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Done },
1681 // Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_3
1682 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 4, CVT_Done },
1683 // Convert__GPR64AsmReg1_0__MSA128AsmReg1_1__ConstantUImm1_01_3
1684 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 4, CVT_Done },
1685 // Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_3
1686 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 4, CVT_Done },
1687 // Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm2_01_3
1688 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 4, CVT_Done },
1689 // Convert__CCRAsmReg1_1__GPR32AsmReg1_0
1690 { CVT_95_addCCRAsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
1691 // Convert__COP2AsmReg1_1__GPR32AsmReg1_0
1692 { CVT_95_addCOP2AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
1693 // Convert__MSACtrlAsmReg1_0__GPR32AsmReg1_1
1694 { CVT_95_addMSACtrlAsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
1695 // Convert__FGR32AsmReg1_1__GPR32AsmReg1_0
1696 { CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
1697 // Convert__AFGR64AsmReg1_0__FGR32AsmReg1_1
1698 { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_Done },
1699 // Convert__FGR64AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2
1700 { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addFGR32AsmRegOperands, 3, CVT_Done },
1701 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__SImm161_1
1702 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addSImmOperands_LT_16_GT_, 2, CVT_Done },
1703 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm161_2
1704 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addSImmOperands_LT_16_GT_, 3, CVT_Done },
1705 // Convert__GPR64AsmReg1_0__Tie0_1_2__UImm16_AltRelaxed1_2
1706 { CVT_95_addGPR64AsmRegOperands, 1, CVT_Tied, Tie0_1_2, CVT_95_addSImmOperands_LT_16_GT_, 3, CVT_Done },
1707 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2__ConstantUImm3_01_3
1708 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 3, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 4, CVT_Done },
1709 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__UImm161_2
1710 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addUImmOperands_LT_16_GT_, 3, CVT_Done },
1711 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1
1712 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_Done },
1713 // Convert__GPR64AsmReg1_1__GPR64AsmReg1_2
1714 { CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 3, CVT_Done },
1715 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_331_3
1716 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_33_GT_, 4, CVT_Done },
1717 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_321_2__ConstantUImm5_11_3
1718 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_32_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_, 4, CVT_Done },
1719 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_0_Report_UImm61_2__ConstantUImm5_Plus1_Report_UImm61_3
1720 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_, 4, CVT_Done },
1721 // Convert__regR0
1722 { CVT_regR0, 0, CVT_Done },
1723 // Convert__GPR32AsmReg1_0
1724 { CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
1725 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImmRange2_641_3__Tie0_1_1
1726 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_95_addImmOperands, 4, CVT_Tied, Tie0_1_1, CVT_Done },
1727 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_321_2__ConstantUImm5_11_3__Tie0_1_1
1728 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_32_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_, 4, CVT_Tied, Tie0_1_1, CVT_Done },
1729 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2__ConstantUImm5_11_3__Tie0_1_1
1730 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_, 4, CVT_Tied, Tie0_1_1, CVT_Done },
1731 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm321_1
1732 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addSImmOperands_LT_32_GT_, 2, CVT_Done },
1733 // Convert__GPR32NonZeroAsmReg1_0__GPR32NonZeroAsmReg1_0__GPR32AsmReg1_1
1734 { CVT_95_addGPR32NonZeroAsmRegOperands, 1, CVT_95_addGPR32NonZeroAsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
1735 // Convert__GPR32ZeroAsmReg1_0__GPR32AsmReg1_1
1736 { CVT_95_addGPR32ZeroAsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
1737 // Convert__Reg1_1__Reg1_2
1738 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Done },
1739 // Convert__GPR32AsmReg1_1__GPR32AsmReg1_2
1740 { CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done },
1741 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm321_2
1742 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addSImmOperands_LT_32_GT_, 3, CVT_Done },
1743 // Convert__GPR32NonZeroAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2
1744 { CVT_95_addGPR32NonZeroAsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done },
1745 // Convert__GPR64AsmReg1_0__Imm1_1
1746 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
1747 // Convert__GPR64AsmReg1_0__Mem2_1
1748 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1749 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2__ConstantUImm2_11_3
1750 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 3, CVT_95_addConstantUImmOperands_LT_2_44__32_1_GT_, 4, CVT_Done },
1751 // Convert__GPR64AsmReg1_0__COP0AsmReg1_1__imm_95_0
1752 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addCOP0AsmRegOperands, 2, CVT_imm_95_0, 0, CVT_Done },
1753 // Convert__GPR64AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2
1754 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addCOP0AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
1755 // Convert__GPR64AsmReg1_0__FGR64AsmReg1_1
1756 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_Done },
1757 // Convert__GPR64AsmReg1_0__COP2AsmReg1_1__imm_95_0
1758 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addCOP2AsmRegOperands, 2, CVT_imm_95_0, 0, CVT_Done },
1759 // Convert__GPR64AsmReg1_0__UImm161_1
1760 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addUImmOperands_LT_16_GT_, 2, CVT_Done },
1761 // Convert__GPR64AsmReg1_0__COP2AsmReg1_1__ConstantUImm3_01_2
1762 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addCOP2AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
1763 // Convert__COP0AsmReg1_1__GPR64AsmReg1_0__imm_95_0
1764 { CVT_95_addCOP0AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 1, CVT_imm_95_0, 0, CVT_Done },
1765 // Convert__COP0AsmReg1_1__GPR64AsmReg1_0__ConstantUImm3_01_2
1766 { CVT_95_addCOP0AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
1767 // Convert__FGR64AsmReg1_1__GPR64AsmReg1_0
1768 { CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 1, CVT_Done },
1769 // Convert__COP2AsmReg1_1__GPR64AsmReg1_0__imm_95_0
1770 { CVT_95_addCOP2AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 1, CVT_imm_95_0, 0, CVT_Done },
1771 // Convert__COP2AsmReg1_1__GPR64AsmReg1_0__ConstantUImm3_01_2
1772 { CVT_95_addCOP2AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
1773 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm32_Relaxed1_2
1774 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addSImmOperands_LT_32_GT_, 3, CVT_Done },
1775 // Convert__GPR64AsmReg1_0__regR0_64__GPR64AsmReg1_0
1776 { CVT_95_addGPR64AsmRegOperands, 1, CVT_regR0_64, 0, CVT_95_addGPR64AsmRegOperands, 1, CVT_Done },
1777 // Convert__GPR64AsmReg1_0__regR0_64__GPR64AsmReg1_1
1778 { CVT_95_addGPR64AsmRegOperands, 1, CVT_regR0_64, 0, CVT_95_addGPR64AsmRegOperands, 2, CVT_Done },
1779 // Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1
1780 { CVT_95_addACC64DSPAsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done },
1781 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0
1782 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_Done },
1783 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__SImm32_Relaxed1_1
1784 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addSImmOperands_LT_32_GT_, 2, CVT_Done },
1785 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm6_01_1
1786 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_, 2, CVT_Done },
1787 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2
1788 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_, 3, CVT_Done },
1789 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1
1790 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 2, CVT_Done },
1791 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2
1792 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done },
1793 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2
1794 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done },
1795 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR32AsmReg1_1
1796 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
1797 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__InvNum1_1
1798 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
1799 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__InvNum1_2
1800 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
1801 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3
1802 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_, 4, CVT_Done },
1803 // Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2
1804 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addACC64DSPAsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done },
1805 // Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2
1806 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addACC64DSPAsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done },
1807 // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1
1808 { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_Done },
1809 // Convert__MSA128AsmReg1_0__GPR32AsmReg1_1
1810 { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
1811 // Convert__MSA128AsmReg1_0__GPR64AsmReg1_1
1812 { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_Done },
1813 // Convert__GPR32AsmReg1_1__GPR32AsmReg1_0__GPR32AsmReg1_2
1814 { CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done },
1815 // Convert__GPR32AsmReg1_0__ConstantUImm2_01_1
1816 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 2, CVT_Done },
1817 // Convert__imm_95_0
1818 { CVT_imm_95_0, 0, CVT_Done },
1819 // Convert__ConstantUImm10_01_0
1820 { CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_, 1, CVT_Done },
1821 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3__Tie0_1_1
1822 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_, 4, CVT_Tied, Tie0_1_1, CVT_Done },
1823 // Convert__MSA128AsmReg1_0__Tie0_1_1__GPR32AsmReg1_4__ConstantUImm4_01_2
1824 { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addGPR32AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 3, CVT_Done },
1825 // Convert__MSA128AsmReg1_0__Tie0_1_1__GPR64AsmReg1_4__ConstantUImm1_01_2
1826 { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addGPR64AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 3, CVT_Done },
1827 // Convert__MSA128AsmReg1_0__Tie0_1_1__GPR32AsmReg1_4__ConstantUImm3_01_2
1828 { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addGPR32AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
1829 // Convert__MSA128AsmReg1_0__Tie0_1_1__GPR32AsmReg1_4__ConstantUImm2_01_2
1830 { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addGPR32AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 3, CVT_Done },
1831 // Convert__GPR32AsmReg1_0__Tie0_1_1__GPR32AsmReg1_1
1832 { CVT_95_addGPR32AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
1833 // Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm4_01_2__MSA128AsmReg1_4__ConstantImmz1_6
1834 { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 3, CVT_95_addMSA128AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_1_GT_, 7, CVT_Done },
1835 // Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm1_01_2__MSA128AsmReg1_4__ConstantImmz1_6
1836 { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 3, CVT_95_addMSA128AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_1_GT_, 7, CVT_Done },
1837 // Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm3_01_2__MSA128AsmReg1_4__ConstantImmz1_6
1838 { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_95_addMSA128AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_1_GT_, 7, CVT_Done },
1839 // Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm2_01_2__MSA128AsmReg1_4__ConstantImmz1_6
1840 { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 3, CVT_95_addMSA128AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_1_GT_, 7, CVT_Done },
1841 // Convert__regR31__GPR32AsmReg1_0
1842 { CVT_regR31, 0, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
1843 // Convert__regR31_64__GPR64AsmReg1_0
1844 { CVT_regR31_64, 0, CVT_95_addGPR64AsmRegOperands, 1, CVT_Done },
1845 // Convert__Reg1_0
1846 { CVT_95_Reg, 1, CVT_Done },
1847 // Convert__GPR32AsmReg1_0__imm_95_0
1848 { CVT_95_addGPR32AsmRegOperands, 1, CVT_imm_95_0, 0, CVT_Done },
1849 // Convert__GPR64AsmReg1_0__imm_95_0
1850 { CVT_95_addGPR64AsmRegOperands, 1, CVT_imm_95_0, 0, CVT_Done },
1851 // Convert__regR0__GPR32AsmReg1_0
1852 { CVT_regR0, 0, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
1853 // Convert__GPR64AsmReg1_0
1854 { CVT_95_addGPR64AsmRegOperands, 1, CVT_Done },
1855 // Convert__regR0_64__GPR64AsmReg1_0
1856 { CVT_regR0_64, 0, CVT_95_addGPR64AsmRegOperands, 1, CVT_Done },
1857 // Convert__UImm5Lsl21_0
1858 { CVT_95_addImmOperands, 1, CVT_Done },
1859 // Convert__AFGR64AsmReg1_0__PtrReg1_3__SImmOffset16_01_1
1860 { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addPtrRegOperands, 4, CVT_95_addImmOperands, 2, CVT_Done },
1861 // Convert__FGR64AsmReg1_0__PtrReg1_3__SImmOffset16_01_1
1862 { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addPtrRegOperands, 4, CVT_95_addImmOperands, 2, CVT_Done },
1863 // Convert__FGR32AsmReg1_0__PtrReg1_3__SImmOffset16_01_1
1864 { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addPtrRegOperands, 4, CVT_95_addImmOperands, 2, CVT_Done },
1865 // Convert__GPR32AsmReg1_0__Imm1_1
1866 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
1867 // Convert__GPR32AsmReg1_0__Mem2_1
1868 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1869 // Convert__GPR32AsmReg1_0__PtrReg1_3__SImmOffset16_01_1
1870 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addPtrRegOperands, 4, CVT_95_addImmOperands, 2, CVT_Done },
1871 // Convert__GPR32AsmReg1_0__PtrReg1_3__SImmPtr1_1
1872 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addPtrRegOperands, 4, CVT_95_addImmOperands, 2, CVT_Done },
1873 // Convert__GPR32AsmReg1_0__PtrReg1_3__SImmOffset9_01_1
1874 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addPtrRegOperands, 4, CVT_95_addImmOperands, 2, CVT_Done },
1875 // Convert__GPR32AsmReg1_0__PtrReg1_3__AnyOffset1_1
1876 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addPtrRegOperands, 4, CVT_95_addImmOperands, 2, CVT_Done },
1877 // Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_3__UImmOffset4_0Minus11_1
1878 { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addGPRMM16AsmRegOperands, 4, CVT_95_addImmOperands, 2, CVT_Done },
1879 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1
1880 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 4, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
1881 // Convert__GPR64AsmReg1_0__PtrReg1_3__SImmPtr1_1
1882 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addPtrRegOperands, 4, CVT_95_addImmOperands, 2, CVT_Done },
1883 // Convert__MSA128AsmReg1_0__PtrReg1_3__SImmOffset10_01_1
1884 { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addPtrRegOperands, 4, CVT_95_addImmOperands, 2, CVT_Done },
1885 // Convert__MSA128AsmReg1_0__PtrReg1_3__SImmOffset10_31_1
1886 { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addPtrRegOperands, 4, CVT_95_addImmOperands, 2, CVT_Done },
1887 // Convert__MSA128AsmReg1_0__PtrReg1_3__SImmOffset10_11_1
1888 { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addPtrRegOperands, 4, CVT_95_addImmOperands, 2, CVT_Done },
1889 // Convert__MSA128AsmReg1_0__PtrReg1_3__SImmOffset10_21_1
1890 { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addPtrRegOperands, 4, CVT_95_addImmOperands, 2, CVT_Done },
1891 // Convert__COP2AsmReg1_0__PtrReg1_3__SImmOffset11_01_1
1892 { CVT_95_addCOP2AsmRegOperands, 1, CVT_95_addPtrRegOperands, 4, CVT_95_addImmOperands, 2, CVT_Done },
1893 // Convert__COP2AsmReg1_0__PtrReg1_3__SImmOffset16_01_1
1894 { CVT_95_addCOP2AsmRegOperands, 1, CVT_95_addPtrRegOperands, 4, CVT_95_addImmOperands, 2, CVT_Done },
1895 // Convert__COP3AsmReg1_0__PtrReg1_3__AnyOffset1_1
1896 { CVT_95_addCOP3AsmRegOperands, 1, CVT_95_addPtrRegOperands, 4, CVT_95_addImmOperands, 2, CVT_Done },
1897 // Convert__MSA128AsmReg1_0__ConstantSImm10_01_1
1898 { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addConstantSImmOperands_LT_10_44__32_0_GT_, 2, CVT_Done },
1899 // Convert__GPR64AsmReg1_0__PtrReg1_3__AnyOffset1_1__Tie0_1_1
1900 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addPtrRegOperands, 4, CVT_95_addImmOperands, 2, CVT_Tied, Tie0_1_1, CVT_Done },
1901 // Convert__GPR64AsmReg1_0__Simm18_Lsl31_1
1902 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
1903 // Convert__AFGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1
1904 { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 4, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
1905 // Convert__FGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1
1906 { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 4, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
1907 // Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_3__UImmOffset4_101_1
1908 { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addGPRMM16AsmRegOperands, 4, CVT_95_addImmOperands, 2, CVT_Done },
1909 // Convert__GPR32AsmReg1_0__UImm32_Coerced1_1
1910 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_32_GT_, 2, CVT_Done },
1911 // Convert__StrictlyAFGR64AsmReg1_0__Imm1_1
1912 { CVT_95_addStrictlyAFGR64AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
1913 // Convert__StrictlyFGR64AsmReg1_0__Imm1_1
1914 { CVT_95_addStrictlyFGR64AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
1915 // Convert__StrictlyFGR32AsmReg1_0__Imm1_1
1916 { CVT_95_addStrictlyFGR32AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
1917 // Convert__GPRMM16AsmReg1_0__UImm7_N11_1
1918 { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_7_44__32__MINUS_1_GT_, 2, CVT_Done },
1919 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__ConstantUImm2_11_3
1920 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_95_addConstantUImmOperands_LT_2_44__32_1_GT_, 4, CVT_Done },
1921 // Convert__GPR32AsmReg1_2__GPR32AsmReg1_1__GPR32AsmReg1_0__ConstantUImm2_11_3
1922 { CVT_95_addGPR32AsmRegOperands, 3, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_2_44__32_1_GT_, 4, CVT_Done },
1923 // Convert__GPR32AsmReg1_0__UImm161_1
1924 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addUImmOperands_LT_16_GT_, 2, CVT_Done },
1925 // Convert__GPR32AsmReg1_0__UImm16_Relaxed1_1
1926 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addUImmOperands_LT_16_GT_, 2, CVT_Done },
1927 // Convert__Reg1_0__Imm1_1
1928 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
1929 // Convert__Reg1_0__Reg1_3__SImm161_1
1930 { CVT_95_Reg, 1, CVT_95_Reg, 4, CVT_95_addSImmOperands_LT_16_GT_, 2, CVT_Done },
1931 // Convert__GPR32AsmReg1_0__MemBaseSP1_3__UImmOffset5_201_1
1932 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addPtrRegOperands, 4, CVT_95_addImmOperands, 2, CVT_Done },
1933 // Convert__GPRMM16AsmReg1_0__MemBaseGP1_3__SImmOffset7_21_1
1934 { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addPtrRegOperands, 4, CVT_95_addImmOperands, 2, CVT_Done },
1935 // Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_3__UImmOffset4_201_1
1936 { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addGPRMM16AsmRegOperands, 4, CVT_95_addImmOperands, 2, CVT_Done },
1937 // Convert__GPR32AsmReg1_0__PtrReg1_3__AnyOffset1_1__Tie0_1_1
1938 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addPtrRegOperands, 4, CVT_95_addImmOperands, 2, CVT_Tied, Tie0_1_1, CVT_Done },
1939 // Convert__GPR32AsmReg1_0__PtrReg1_3__SImmOffset9_01_1__Tie0_1_1
1940 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addPtrRegOperands, 4, CVT_95_addImmOperands, 2, CVT_Tied, Tie0_1_1, CVT_Done },
1941 // Convert__RegList1_0__PtrReg1_3__AnyOffset1_1
1942 { CVT_95_addRegListOperands, 1, CVT_95_addPtrRegOperands, 4, CVT_95_addImmOperands, 2, CVT_Done },
1943 // Convert__RegList161_0__MemBaseSP1_3__UImmOffset4_201_1
1944 { CVT_95_addRegListOperands, 1, CVT_95_addPtrRegOperands, 4, CVT_95_addImmOperands, 2, CVT_Done },
1945 // Convert__RegList161_0__MemBaseSP1_3__UImmOffset6_001_1
1946 { CVT_95_addRegListOperands, 1, CVT_95_addPtrRegOperands, 4, CVT_95_addImmOperands, 2, CVT_Done },
1947 // ConvertCustom_ConvertXWPOperands
1948 { CVT_ConvertXWPOperands, 0, CVT_Done },
1949 // Convert__GPR32AsmReg1_0__PtrReg1_3__SImmOffset12_01_1
1950 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addPtrRegOperands, 4, CVT_95_addImmOperands, 2, CVT_Done },
1951 // Convert__GPR64AsmReg1_0__PtrReg1_3__AnyOffset1_1
1952 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addPtrRegOperands, 4, CVT_95_addImmOperands, 2, CVT_Done },
1953 // Convert__FGR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1
1954 { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 4, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
1955 // Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2__AFGR64AsmReg1_3
1956 { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_95_addAFGR64AsmRegOperands, 3, CVT_95_addAFGR64AsmRegOperands, 4, CVT_Done },
1957 // Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2__FGR64AsmReg1_3
1958 { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addFGR64AsmRegOperands, 3, CVT_95_addFGR64AsmRegOperands, 4, CVT_Done },
1959 // Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2__FGR32AsmReg1_3
1960 { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addFGR32AsmRegOperands, 3, CVT_95_addFGR32AsmRegOperands, 4, CVT_Done },
1961 // Convert__FGR64AsmReg1_0__Tie0_1_1__FGR64AsmReg1_1__FGR64AsmReg1_2
1962 { CVT_95_addFGR64AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addFGR64AsmRegOperands, 3, CVT_Done },
1963 // Convert__FGR32AsmReg1_0__Tie0_1_1__FGR32AsmReg1_1__FGR32AsmReg1_2
1964 { CVT_95_addFGR32AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addFGR32AsmRegOperands, 3, CVT_Done },
1965 // Convert__GPR32AsmReg1_0__COP0AsmReg1_1__imm_95_0
1966 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addCOP0AsmRegOperands, 2, CVT_imm_95_0, 0, CVT_Done },
1967 // Convert__GPR32AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2
1968 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addCOP0AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
1969 // Convert__GPR32AsmReg1_0__FGR64AsmReg1_1
1970 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_Done },
1971 // Convert__GPR32AsmReg1_0__COP2AsmReg1_1__imm_95_0
1972 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addCOP2AsmRegOperands, 2, CVT_imm_95_0, 0, CVT_Done },
1973 // Convert__GPR32AsmReg1_0__COP2AsmReg1_1__ConstantUImm3_01_2
1974 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addCOP2AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
1975 // Convert__GPR32AsmReg1_0__AFGR64AsmReg1_1
1976 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_Done },
1977 // Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1
1978 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addACC64DSPAsmRegOperands, 2, CVT_Done },
1979 // Convert__GPR32AsmReg1_0__regAC0
1980 { CVT_95_addGPR32AsmRegOperands, 1, CVT_regAC0, 0, CVT_Done },
1981 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0
1982 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_imm_95_0, 0, CVT_Done },
1983 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm1_01_2__ConstantUImm3_01_3__ConstantUImm1_01_4
1984 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 4, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 5, CVT_Done },
1985 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__regR0
1986 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_regR0, 0, CVT_Done },
1987 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__regR0_64
1988 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_regR0_64, 0, CVT_Done },
1989 // Convert__GPRMM16AsmRegMovePPairFirst1_0__GPRMM16AsmRegMovePPairSecond1_1__GPRMM16AsmRegMoveP1_2__GPRMM16AsmRegMoveP1_3
1990 { CVT_95_addGPRMM16AsmRegMovePPairFirstOperands, 1, CVT_95_addGPRMM16AsmRegMovePPairSecondOperands, 2, CVT_95_addGPRMM16AsmRegMovePOperands, 3, CVT_95_addGPRMM16AsmRegMovePOperands, 4, CVT_Done },
1991 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1
1992 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addFCCAsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done },
1993 // Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__FCCAsmReg1_2__Tie0_1_1
1994 { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_95_addFCCAsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done },
1995 // Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FCCAsmReg1_2__Tie0_1_1
1996 { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addFCCAsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done },
1997 // Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1
1998 { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addFCCAsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done },
1999 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1
2000 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done },
2001 // Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1
2002 { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done },
2003 // Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1
2004 { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done },
2005 // Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1
2006 { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done },
2007 // Convert__COP0AsmReg1_1__GPR32AsmReg1_0__imm_95_0
2008 { CVT_95_addCOP0AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_imm_95_0, 0, CVT_Done },
2009 // Convert__COP0AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2
2010 { CVT_95_addCOP0AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
2011 // Convert__FGR64AsmReg1_1__GPR32AsmReg1_0
2012 { CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
2013 // Convert__COP2AsmReg1_1__GPR32AsmReg1_0__imm_95_0
2014 { CVT_95_addCOP2AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_imm_95_0, 0, CVT_Done },
2015 // Convert__COP2AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2
2016 { CVT_95_addCOP2AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
2017 // Convert__AFGR64AsmReg1_1__Tie0_1_1__GPR32AsmReg1_0
2018 { CVT_95_addAFGR64AsmRegOperands, 2, CVT_Tied, Tie0_1_1, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
2019 // Convert__FGR64AsmReg1_1__Tie0_1_1__GPR32AsmReg1_0
2020 { CVT_95_addFGR64AsmRegOperands, 2, CVT_Tied, Tie0_1_1, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
2021 // Convert__HI32DSPAsmReg1_1__GPR32AsmReg1_0
2022 { CVT_95_addHI32DSPAsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
2023 // Convert__ACC64DSPAsmReg1_1__GPR32AsmReg1_0__Tie0_1_1
2024 { CVT_95_addACC64DSPAsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_Done },
2025 // Convert__LO32DSPAsmReg1_1__GPR32AsmReg1_0
2026 { CVT_95_addLO32DSPAsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
2027 // Convert__regAC0__GPR32AsmReg1_0
2028 { CVT_regAC0, 0, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
2029 // Convert__ACC64DSPAsmReg1_1__GPR32AsmReg1_0
2030 { CVT_95_addACC64DSPAsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
2031 // Convert__GPR32AsmReg1_1__GPR32AsmReg1_0
2032 { CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
2033 // Convert__GPR32AsmReg1_1__GPR32AsmReg1_0__ConstantUImm1_01_2__ConstantUImm3_01_3__ConstantUImm1_01_4
2034 { CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 4, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 5, CVT_Done },
2035 // Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2
2036 { CVT_95_addACC64DSPAsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done },
2037 // Convert__regR0__imm_95_0
2038 { CVT_regR0, 0, CVT_imm_95_0, 0, CVT_Done },
2039 // Convert__GPR32AsmReg1_0__regR0__GPR32AsmReg1_0
2040 { CVT_95_addGPR32AsmRegOperands, 1, CVT_regR0, 0, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
2041 // Convert__GPR32AsmReg1_0__regR0__GPR32AsmReg1_1
2042 { CVT_95_addGPR32AsmRegOperands, 1, CVT_regR0, 0, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
2043 // Convert__regR0__regR0__imm_95_0
2044 { CVT_regR0, 0, CVT_regR0, 0, CVT_imm_95_0, 0, CVT_Done },
2045 // Convert__regR0__regR16
2046 { CVT_regR0, 0, CVT_regR16, 0, CVT_Done },
2047 // Convert__regR0__regR0
2048 { CVT_regR0, 0, CVT_regR0, 0, CVT_Done },
2049 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__regR0
2050 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_regR0, 0, CVT_Done },
2051 // Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1
2052 { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addGPRMM16AsmRegOperands, 2, CVT_Done },
2053 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0
2054 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
2055 // Convert__GPR32AsmReg1_3__GPR32AsmReg1_1__ConstantUImm5_01_0
2056 { CVT_95_addGPR32AsmRegOperands, 4, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 1, CVT_Done },
2057 // Convert__GPR32AsmReg1_0__ConstantUImm7_01_1
2058 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_7_44__32_0_GT_, 2, CVT_Done },
2059 // Convert__GPR32AsmReg1_0__ConstantUImm10_01_1
2060 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_, 2, CVT_Done },
2061 // Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__imm_95_0
2062 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addHWRegsAsmRegOperands, 2, CVT_imm_95_0, 0, CVT_Done },
2063 // Convert__GPR64AsmReg1_0__HWRegsAsmReg1_1__imm_95_0
2064 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addHWRegsAsmRegOperands, 2, CVT_imm_95_0, 0, CVT_Done },
2065 // Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__ConstantUImm3_01_2
2066 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addHWRegsAsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
2067 // Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__ConstantUImm8_01_2
2068 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addHWRegsAsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_8_44__32_0_GT_, 3, CVT_Done },
2069 // Convert__GPR32AsmReg1_0__ConstantSImm10_01_1
2070 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantSImmOperands_LT_10_44__32_0_GT_, 2, CVT_Done },
2071 // Convert__GPR32AsmReg1_0__ConstantUImm8_01_1
2072 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_8_44__32_0_GT_, 2, CVT_Done },
2073 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1
2074 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 2, CVT_Done },
2075 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2
2076 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done },
2077 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_2
2078 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 3, CVT_Done },
2079 // Convert__GPRMM16AsmRegZero1_0__GPRMM16AsmReg1_3__UImmOffset4_001_1
2080 { CVT_95_addGPRMM16AsmRegZeroOperands, 1, CVT_95_addGPRMM16AsmRegOperands, 4, CVT_95_addImmOperands, 2, CVT_Done },
2081 // Convert__GPR32AsmReg1_0__Tie0_1_1__PtrReg1_3__SImmOffset9_01_1
2082 { CVT_95_addGPR32AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addPtrRegOperands, 4, CVT_95_addImmOperands, 2, CVT_Done },
2083 // Convert__GPR32AsmReg1_0__Tie0_1_1__PtrReg1_3__SImmPtr1_1
2084 { CVT_95_addGPR32AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addPtrRegOperands, 4, CVT_95_addImmOperands, 2, CVT_Done },
2085 // Convert__GPR32AsmReg1_0__Tie0_1_1__PtrReg1_3__AnyOffset1_1
2086 { CVT_95_addGPR32AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addPtrRegOperands, 4, CVT_95_addImmOperands, 2, CVT_Done },
2087 // Convert__GPR64AsmReg1_0__Tie0_1_1__PtrReg1_3__SImmPtr1_1
2088 { CVT_95_addGPR64AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addPtrRegOperands, 4, CVT_95_addImmOperands, 2, CVT_Done },
2089 // Convert__GPR64AsmReg1_0__Tie0_1_1__PtrReg1_3__AnyOffset1_1
2090 { CVT_95_addGPR64AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addPtrRegOperands, 4, CVT_95_addImmOperands, 2, CVT_Done },
2091 // Convert__ConstantUImm20_01_0
2092 { CVT_95_addConstantUImmOperands_LT_20_44__32_0_GT_, 1, CVT_Done },
2093 // Convert__Reg1_0__Tie0_1_1
2094 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_Done },
2095 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantSImm10_01_1
2096 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantSImmOperands_LT_10_44__32_0_GT_, 2, CVT_Done },
2097 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantSImm10_01_2
2098 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantSImmOperands_LT_10_44__32_0_GT_, 3, CVT_Done },
2099 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm32_Coerced1_1
2100 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_32_GT_, 2, CVT_Done },
2101 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm32_Coerced1_2
2102 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_32_GT_, 3, CVT_Done },
2103 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_0
2104 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
2105 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_2__GPR32AsmReg1_1
2106 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 3, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
2107 // Convert__GPRMM16AsmRegZero1_0__GPRMM16AsmReg1_3__UImmOffset4_101_1
2108 { CVT_95_addGPRMM16AsmRegZeroOperands, 1, CVT_95_addGPRMM16AsmRegOperands, 4, CVT_95_addImmOperands, 2, CVT_Done },
2109 // Convert__ACC64DSPAsmReg1_0__ConstantSImm6_01_1__Tie0_1_1
2110 { CVT_95_addACC64DSPAsmRegOperands, 1, CVT_95_addConstantSImmOperands_LT_6_44__32_0_GT_, 2, CVT_Tied, Tie0_1_1, CVT_Done },
2111 // Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__Tie0_1_1
2112 { CVT_95_addACC64DSPAsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Tied, Tie0_1_1, CVT_Done },
2113 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2
2114 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 3, CVT_Done },
2115 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2
2116 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
2117 // Convert__UImm161_0
2118 { CVT_95_addUImmOperands_LT_16_GT_, 1, CVT_Done },
2119 // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__GPR32AsmReg1_3
2120 { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 4, CVT_Done },
2121 // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm4_01_3
2122 { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 4, CVT_Done },
2123 // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm1_01_3
2124 { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 4, CVT_Done },
2125 // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm3_01_3
2126 { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 4, CVT_Done },
2127 // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm2_01_3
2128 { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 4, CVT_Done },
2129 // Convert__Reg1_0__Reg1_1__ConstantUImm5_01_2
2130 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done },
2131 // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__GPR32AsmReg1_3
2132 { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 4, CVT_Done },
2133 // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_3
2134 { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 4, CVT_Done },
2135 // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm1_01_3
2136 { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 4, CVT_Done },
2137 // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_3
2138 { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 4, CVT_Done },
2139 // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm2_01_3
2140 { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 4, CVT_Done },
2141 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__InvNum1_1
2142 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
2143 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__InvNum1_2
2144 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
2145 // Convert__GPRMM16AsmRegZero1_0__GPRMM16AsmReg1_3__UImmOffset4_201_1
2146 { CVT_95_addGPRMM16AsmRegZeroOperands, 1, CVT_95_addGPRMM16AsmRegOperands, 4, CVT_95_addImmOperands, 2, CVT_Done },
2147 // Convert__ConstantUImm5_01_0
2148 { CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 1, CVT_Done },
2149 // Convert__imm_95_17
2150 { CVT_imm_95_17, 0, CVT_Done },
2151 // Convert__imm_95_16
2152 { CVT_imm_95_16, 0, CVT_Done },
2153 // Convert__imm_95_18
2154 { CVT_imm_95_18, 0, CVT_Done },
2155 // Convert__imm_95_19
2156 { CVT_imm_95_19, 0, CVT_Done },
2157 // Convert__imm_95_4
2158 { CVT_imm_95_4, 0, CVT_Done },
2159 // Convert__PtrReg1_2__SImmOffset16_01_0
2160 { CVT_95_addPtrRegOperands, 3, CVT_95_addImmOperands, 1, CVT_Done },
2161 // Convert__imm_95_2
2162 { CVT_imm_95_2, 0, CVT_Done },
2163 // Convert__imm_95_6
2164 { CVT_imm_95_6, 0, CVT_Done },
2165 // Convert__imm_95_5
2166 { CVT_imm_95_5, 0, CVT_Done },
2167 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm10_01_2
2168 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_, 3, CVT_Done },
2169 // Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1__GPR32AsmReg1_2
2170 { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done },
2171 // Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__GPR32AsmReg1_2
2172 { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done },
2173 // Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__GPR32AsmReg1_2
2174 { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done },
2175 // Convert__GPR32AsmReg1_0__imm_95_31
2176 { CVT_95_addGPR32AsmRegOperands, 1, CVT_imm_95_31, 0, CVT_Done },
2177};
2178
2179void MipsAsmParser::
2180convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode,
2181 const OperandVector &Operands) {
2182 assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!");
2183 const uint8_t *Converter = ConversionTable[Kind];
2184 Inst.setOpcode(Opcode);
2185 for (const uint8_t *p = Converter; *p; p += 2) {
2186 unsigned OpIdx = *(p + 1);
2187 switch (*p) {
2188 default: llvm_unreachable("invalid conversion entry!");
2189 case CVT_Reg:
2190 static_cast<MipsOperand &>(*Operands[OpIdx]).addRegOperands(Inst, 1);
2191 break;
2192 case CVT_Tied: {
2193 assert(*(p + 1) < (size_t)(std::end(TiedAsmOperandTable) -
2194 std::begin(TiedAsmOperandTable)) &&
2195 "Tied operand not found");
2196 unsigned TiedResOpnd = TiedAsmOperandTable[*(p + 1)][0];
2197 if (TiedResOpnd != (uint8_t)-1)
2198 Inst.addOperand(Inst.getOperand(TiedResOpnd));
2199 break;
2200 }
2201 case CVT_95_addGPR32AsmRegOperands:
2202 static_cast<MipsOperand &>(*Operands[OpIdx]).addGPR32AsmRegOperands(Inst, 1);
2203 break;
2204 case CVT_95_addAFGR64AsmRegOperands:
2205 static_cast<MipsOperand &>(*Operands[OpIdx]).addAFGR64AsmRegOperands(Inst, 1);
2206 break;
2207 case CVT_95_addFGR64AsmRegOperands:
2208 static_cast<MipsOperand &>(*Operands[OpIdx]).addFGR64AsmRegOperands(Inst, 1);
2209 break;
2210 case CVT_95_addFGR32AsmRegOperands:
2211 static_cast<MipsOperand &>(*Operands[OpIdx]).addFGR32AsmRegOperands(Inst, 1);
2212 break;
2213 case CVT_95_addSImmOperands_LT_32_GT_:
2214 static_cast<MipsOperand &>(*Operands[OpIdx]).addSImmOperands<32>(Inst, 1);
2215 break;
2216 case CVT_95_addMSA128AsmRegOperands:
2217 static_cast<MipsOperand &>(*Operands[OpIdx]).addMSA128AsmRegOperands(Inst, 1);
2218 break;
2219 case CVT_95_addSImmOperands_LT_16_GT_:
2220 static_cast<MipsOperand &>(*Operands[OpIdx]).addSImmOperands<16>(Inst, 1);
2221 break;
2222 case CVT_95_Reg:
2223 static_cast<MipsOperand &>(*Operands[OpIdx]).addRegOperands(Inst, 1);
2224 break;
2225 case CVT_95_addImmOperands:
2226 static_cast<MipsOperand &>(*Operands[OpIdx]).addImmOperands(Inst, 1);
2227 break;
2228 case CVT_95_addGPRMM16AsmRegOperands:
2229 static_cast<MipsOperand &>(*Operands[OpIdx]).addGPRMM16AsmRegOperands(Inst, 1);
2230 break;
2231 case CVT_95_addConstantSImmOperands_LT_4_44__32_0_GT_:
2232 static_cast<MipsOperand &>(*Operands[OpIdx]).addConstantSImmOperands<4, 0>(Inst, 1);
2233 break;
2234 case CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_:
2235 static_cast<MipsOperand &>(*Operands[OpIdx]).addConstantUImmOperands<5, 0>(Inst, 1);
2236 break;
2237 case CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_:
2238 static_cast<MipsOperand &>(*Operands[OpIdx]).addConstantUImmOperands<2, 0>(Inst, 1);
2239 break;
2240 case CVT_95_addUImmOperands_LT_16_GT_:
2241 static_cast<MipsOperand &>(*Operands[OpIdx]).addUImmOperands<16>(Inst, 1);
2242 break;
2243 case CVT_95_addGPR64AsmRegOperands:
2244 static_cast<MipsOperand &>(*Operands[OpIdx]).addGPR64AsmRegOperands(Inst, 1);
2245 break;
2246 case CVT_95_addConstantUImmOperands_LT_8_44__32_0_GT_:
2247 static_cast<MipsOperand &>(*Operands[OpIdx]).addConstantUImmOperands<8, 0>(Inst, 1);
2248 break;
2249 case CVT_regR0:
2250 Inst.addOperand(MCOperand::createReg(Mips::R0));
2251 break;
2252 case CVT_95_addConstantUImmOperands_LT_5_44__32_32_44__32__MINUS_32_GT_:
2253 static_cast<MipsOperand &>(*Operands[OpIdx]).addConstantUImmOperands<5, 32, -32>(Inst, 1);
2254 break;
2255 case CVT_regFCC0:
2256 Inst.addOperand(MCOperand::createReg(Mips::FCC0));
2257 break;
2258 case CVT_95_addFCCAsmRegOperands:
2259 static_cast<MipsOperand &>(*Operands[OpIdx]).addFCCAsmRegOperands(Inst, 1);
2260 break;
2261 case CVT_95_addCOP2AsmRegOperands:
2262 static_cast<MipsOperand &>(*Operands[OpIdx]).addCOP2AsmRegOperands(Inst, 1);
2263 break;
2264 case CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_:
2265 static_cast<MipsOperand &>(*Operands[OpIdx]).addConstantUImmOperands<3, 0>(Inst, 1);
2266 break;
2267 case CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_:
2268 static_cast<MipsOperand &>(*Operands[OpIdx]).addConstantUImmOperands<6, 0>(Inst, 1);
2269 break;
2270 case CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_:
2271 static_cast<MipsOperand &>(*Operands[OpIdx]).addConstantUImmOperands<4, 0>(Inst, 1);
2272 break;
2273 case CVT_imm_95_0:
2274 Inst.addOperand(MCOperand::createImm(0));
2275 break;
2276 case CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_:
2277 static_cast<MipsOperand &>(*Operands[OpIdx]).addConstantUImmOperands<10, 0>(Inst, 1);
2278 break;
2279 case CVT_95_addPtrRegOperands:
2280 static_cast<MipsOperand &>(*Operands[OpIdx]).addPtrRegOperands(Inst, 1);
2281 break;
2282 case CVT_95_addConstantSImmOperands_LT_5_44__32_0_GT_:
2283 static_cast<MipsOperand &>(*Operands[OpIdx]).addConstantSImmOperands<5, 0>(Inst, 1);
2284 break;
2285 case CVT_95_addCCRAsmRegOperands:
2286 static_cast<MipsOperand &>(*Operands[OpIdx]).addCCRAsmRegOperands(Inst, 1);
2287 break;
2288 case CVT_95_addMSACtrlAsmRegOperands:
2289 static_cast<MipsOperand &>(*Operands[OpIdx]).addMSACtrlAsmRegOperands(Inst, 1);
2290 break;
2291 case CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_:
2292 static_cast<MipsOperand &>(*Operands[OpIdx]).addConstantUImmOperands<1, 0>(Inst, 1);
2293 break;
2294 case CVT_95_addConstantUImmOperands_LT_5_44__32_33_GT_:
2295 static_cast<MipsOperand &>(*Operands[OpIdx]).addConstantUImmOperands<5, 33>(Inst, 1);
2296 break;
2297 case CVT_95_addConstantUImmOperands_LT_5_44__32_32_GT_:
2298 static_cast<MipsOperand &>(*Operands[OpIdx]).addConstantUImmOperands<5, 32>(Inst, 1);
2299 break;
2300 case CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_:
2301 static_cast<MipsOperand &>(*Operands[OpIdx]).addConstantUImmOperands<5, 1>(Inst, 1);
2302 break;
2303 case CVT_95_addGPR32NonZeroAsmRegOperands:
2304 static_cast<MipsOperand &>(*Operands[OpIdx]).addGPR32NonZeroAsmRegOperands(Inst, 1);
2305 break;
2306 case CVT_95_addGPR32ZeroAsmRegOperands:
2307 static_cast<MipsOperand &>(*Operands[OpIdx]).addGPR32ZeroAsmRegOperands(Inst, 1);
2308 break;
2309 case CVT_95_addMemOperands:
2310 static_cast<MipsOperand &>(*Operands[OpIdx]).addMemOperands(Inst, 2);
2311 break;
2312 case CVT_95_addConstantUImmOperands_LT_2_44__32_1_GT_:
2313 static_cast<MipsOperand &>(*Operands[OpIdx]).addConstantUImmOperands<2, 1>(Inst, 1);
2314 break;
2315 case CVT_95_addCOP0AsmRegOperands:
2316 static_cast<MipsOperand &>(*Operands[OpIdx]).addCOP0AsmRegOperands(Inst, 1);
2317 break;
2318 case CVT_regR0_64:
2319 Inst.addOperand(MCOperand::createReg(Mips::R0_64));
2320 break;
2321 case CVT_95_addACC64DSPAsmRegOperands:
2322 static_cast<MipsOperand &>(*Operands[OpIdx]).addACC64DSPAsmRegOperands(Inst, 1);
2323 break;
2324 case CVT_95_addConstantUImmOperands_LT_1_GT_:
2325 static_cast<MipsOperand &>(*Operands[OpIdx]).addConstantUImmOperands<1>(Inst, 1);
2326 break;
2327 case CVT_regR31:
2328 Inst.addOperand(MCOperand::createReg(Mips::R31));
2329 break;
2330 case CVT_regR31_64:
2331 Inst.addOperand(MCOperand::createReg(Mips::R31_64));
2332 break;
2333 case CVT_95_addCOP3AsmRegOperands:
2334 static_cast<MipsOperand &>(*Operands[OpIdx]).addCOP3AsmRegOperands(Inst, 1);
2335 break;
2336 case CVT_95_addConstantSImmOperands_LT_10_44__32_0_GT_:
2337 static_cast<MipsOperand &>(*Operands[OpIdx]).addConstantSImmOperands<10, 0>(Inst, 1);
2338 break;
2339 case CVT_95_addConstantUImmOperands_LT_32_GT_:
2340 static_cast<MipsOperand &>(*Operands[OpIdx]).addConstantUImmOperands<32>(Inst, 1);
2341 break;
2342 case CVT_95_addStrictlyAFGR64AsmRegOperands:
2343 static_cast<MipsOperand &>(*Operands[OpIdx]).addStrictlyAFGR64AsmRegOperands(Inst, 1);
2344 break;
2345 case CVT_95_addStrictlyFGR64AsmRegOperands:
2346 static_cast<MipsOperand &>(*Operands[OpIdx]).addStrictlyFGR64AsmRegOperands(Inst, 1);
2347 break;
2348 case CVT_95_addStrictlyFGR32AsmRegOperands:
2349 static_cast<MipsOperand &>(*Operands[OpIdx]).addStrictlyFGR32AsmRegOperands(Inst, 1);
2350 break;
2351 case CVT_95_addConstantUImmOperands_LT_7_44__32__MINUS_1_GT_:
2352 static_cast<MipsOperand &>(*Operands[OpIdx]).addConstantUImmOperands<7, -1>(Inst, 1);
2353 break;
2354 case CVT_95_addRegListOperands:
2355 static_cast<MipsOperand &>(*Operands[OpIdx]).addRegListOperands(Inst, 1);
2356 break;
2357 case CVT_ConvertXWPOperands:
2358 ConvertXWPOperands(Inst, Operands);
2359 break;
2360 case CVT_regAC0:
2361 Inst.addOperand(MCOperand::createReg(Mips::AC0));
2362 break;
2363 case CVT_95_addGPRMM16AsmRegMovePPairFirstOperands:
2364 static_cast<MipsOperand &>(*Operands[OpIdx]).addGPRMM16AsmRegMovePPairFirstOperands(Inst, 1);
2365 break;
2366 case CVT_95_addGPRMM16AsmRegMovePPairSecondOperands:
2367 static_cast<MipsOperand &>(*Operands[OpIdx]).addGPRMM16AsmRegMovePPairSecondOperands(Inst, 1);
2368 break;
2369 case CVT_95_addGPRMM16AsmRegMovePOperands:
2370 static_cast<MipsOperand &>(*Operands[OpIdx]).addGPRMM16AsmRegMovePOperands(Inst, 1);
2371 break;
2372 case CVT_95_addHI32DSPAsmRegOperands:
2373 static_cast<MipsOperand &>(*Operands[OpIdx]).addHI32DSPAsmRegOperands(Inst, 1);
2374 break;
2375 case CVT_95_addLO32DSPAsmRegOperands:
2376 static_cast<MipsOperand &>(*Operands[OpIdx]).addLO32DSPAsmRegOperands(Inst, 1);
2377 break;
2378 case CVT_regR16:
2379 Inst.addOperand(MCOperand::createReg(Mips::R16));
2380 break;
2381 case CVT_95_addConstantUImmOperands_LT_7_44__32_0_GT_:
2382 static_cast<MipsOperand &>(*Operands[OpIdx]).addConstantUImmOperands<7, 0>(Inst, 1);
2383 break;
2384 case CVT_95_addHWRegsAsmRegOperands:
2385 static_cast<MipsOperand &>(*Operands[OpIdx]).addHWRegsAsmRegOperands(Inst, 1);
2386 break;
2387 case CVT_95_addGPRMM16AsmRegZeroOperands:
2388 static_cast<MipsOperand &>(*Operands[OpIdx]).addGPRMM16AsmRegZeroOperands(Inst, 1);
2389 break;
2390 case CVT_95_addConstantUImmOperands_LT_20_44__32_0_GT_:
2391 static_cast<MipsOperand &>(*Operands[OpIdx]).addConstantUImmOperands<20, 0>(Inst, 1);
2392 break;
2393 case CVT_95_addConstantSImmOperands_LT_6_44__32_0_GT_:
2394 static_cast<MipsOperand &>(*Operands[OpIdx]).addConstantSImmOperands<6, 0>(Inst, 1);
2395 break;
2396 case CVT_imm_95_17:
2397 Inst.addOperand(MCOperand::createImm(17));
2398 break;
2399 case CVT_imm_95_16:
2400 Inst.addOperand(MCOperand::createImm(16));
2401 break;
2402 case CVT_imm_95_18:
2403 Inst.addOperand(MCOperand::createImm(18));
2404 break;
2405 case CVT_imm_95_19:
2406 Inst.addOperand(MCOperand::createImm(19));
2407 break;
2408 case CVT_imm_95_4:
2409 Inst.addOperand(MCOperand::createImm(4));
2410 break;
2411 case CVT_imm_95_2:
2412 Inst.addOperand(MCOperand::createImm(2));
2413 break;
2414 case CVT_imm_95_6:
2415 Inst.addOperand(MCOperand::createImm(6));
2416 break;
2417 case CVT_imm_95_5:
2418 Inst.addOperand(MCOperand::createImm(5));
2419 break;
2420 case CVT_imm_95_31:
2421 Inst.addOperand(MCOperand::createImm(31));
2422 break;
2423 }
2424 }
2425}
2426
2427void MipsAsmParser::
2428convertToMapAndConstraints(unsigned Kind,
2429 const OperandVector &Operands) {
2430 assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!");
2431 unsigned NumMCOperands = 0;
2432 const uint8_t *Converter = ConversionTable[Kind];
2433 for (const uint8_t *p = Converter; *p; p += 2) {
2434 switch (*p) {
2435 default: llvm_unreachable("invalid conversion entry!");
2436 case CVT_Reg:
2437 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2438 Operands[*(p + 1)]->setConstraint("r");
2439 ++NumMCOperands;
2440 break;
2441 case CVT_Tied:
2442 ++NumMCOperands;
2443 break;
2444 case CVT_95_addGPR32AsmRegOperands:
2445 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2446 Operands[*(p + 1)]->setConstraint("m");
2447 NumMCOperands += 1;
2448 break;
2449 case CVT_95_addAFGR64AsmRegOperands:
2450 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2451 Operands[*(p + 1)]->setConstraint("m");
2452 NumMCOperands += 1;
2453 break;
2454 case CVT_95_addFGR64AsmRegOperands:
2455 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2456 Operands[*(p + 1)]->setConstraint("m");
2457 NumMCOperands += 1;
2458 break;
2459 case CVT_95_addFGR32AsmRegOperands:
2460 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2461 Operands[*(p + 1)]->setConstraint("m");
2462 NumMCOperands += 1;
2463 break;
2464 case CVT_95_addSImmOperands_LT_32_GT_:
2465 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2466 Operands[*(p + 1)]->setConstraint("m");
2467 NumMCOperands += 1;
2468 break;
2469 case CVT_95_addMSA128AsmRegOperands:
2470 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2471 Operands[*(p + 1)]->setConstraint("m");
2472 NumMCOperands += 1;
2473 break;
2474 case CVT_95_addSImmOperands_LT_16_GT_:
2475 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2476 Operands[*(p + 1)]->setConstraint("m");
2477 NumMCOperands += 1;
2478 break;
2479 case CVT_95_Reg:
2480 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2481 Operands[*(p + 1)]->setConstraint("r");
2482 NumMCOperands += 1;
2483 break;
2484 case CVT_95_addImmOperands:
2485 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2486 Operands[*(p + 1)]->setConstraint("m");
2487 NumMCOperands += 1;
2488 break;
2489 case CVT_95_addGPRMM16AsmRegOperands:
2490 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2491 Operands[*(p + 1)]->setConstraint("m");
2492 NumMCOperands += 1;
2493 break;
2494 case CVT_95_addConstantSImmOperands_LT_4_44__32_0_GT_:
2495 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2496 Operands[*(p + 1)]->setConstraint("m");
2497 NumMCOperands += 1;
2498 break;
2499 case CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_:
2500 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2501 Operands[*(p + 1)]->setConstraint("m");
2502 NumMCOperands += 1;
2503 break;
2504 case CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_:
2505 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2506 Operands[*(p + 1)]->setConstraint("m");
2507 NumMCOperands += 1;
2508 break;
2509 case CVT_95_addUImmOperands_LT_16_GT_:
2510 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2511 Operands[*(p + 1)]->setConstraint("m");
2512 NumMCOperands += 1;
2513 break;
2514 case CVT_95_addGPR64AsmRegOperands:
2515 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2516 Operands[*(p + 1)]->setConstraint("m");
2517 NumMCOperands += 1;
2518 break;
2519 case CVT_95_addConstantUImmOperands_LT_8_44__32_0_GT_:
2520 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2521 Operands[*(p + 1)]->setConstraint("m");
2522 NumMCOperands += 1;
2523 break;
2524 case CVT_regR0:
2525 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2526 Operands[*(p + 1)]->setConstraint("m");
2527 ++NumMCOperands;
2528 break;
2529 case CVT_95_addConstantUImmOperands_LT_5_44__32_32_44__32__MINUS_32_GT_:
2530 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2531 Operands[*(p + 1)]->setConstraint("m");
2532 NumMCOperands += 1;
2533 break;
2534 case CVT_regFCC0:
2535 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2536 Operands[*(p + 1)]->setConstraint("m");
2537 ++NumMCOperands;
2538 break;
2539 case CVT_95_addFCCAsmRegOperands:
2540 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2541 Operands[*(p + 1)]->setConstraint("m");
2542 NumMCOperands += 1;
2543 break;
2544 case CVT_95_addCOP2AsmRegOperands:
2545 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2546 Operands[*(p + 1)]->setConstraint("m");
2547 NumMCOperands += 1;
2548 break;
2549 case CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_:
2550 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2551 Operands[*(p + 1)]->setConstraint("m");
2552 NumMCOperands += 1;
2553 break;
2554 case CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_:
2555 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2556 Operands[*(p + 1)]->setConstraint("m");
2557 NumMCOperands += 1;
2558 break;
2559 case CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_:
2560 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2561 Operands[*(p + 1)]->setConstraint("m");
2562 NumMCOperands += 1;
2563 break;
2564 case CVT_imm_95_0:
2565 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2566 Operands[*(p + 1)]->setConstraint("");
2567 ++NumMCOperands;
2568 break;
2569 case CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_:
2570 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2571 Operands[*(p + 1)]->setConstraint("m");
2572 NumMCOperands += 1;
2573 break;
2574 case CVT_95_addPtrRegOperands:
2575 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2576 Operands[*(p + 1)]->setConstraint("m");
2577 NumMCOperands += 1;
2578 break;
2579 case CVT_95_addConstantSImmOperands_LT_5_44__32_0_GT_:
2580 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2581 Operands[*(p + 1)]->setConstraint("m");
2582 NumMCOperands += 1;
2583 break;
2584 case CVT_95_addCCRAsmRegOperands:
2585 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2586 Operands[*(p + 1)]->setConstraint("m");
2587 NumMCOperands += 1;
2588 break;
2589 case CVT_95_addMSACtrlAsmRegOperands:
2590 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2591 Operands[*(p + 1)]->setConstraint("m");
2592 NumMCOperands += 1;
2593 break;
2594 case CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_:
2595 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2596 Operands[*(p + 1)]->setConstraint("m");
2597 NumMCOperands += 1;
2598 break;
2599 case CVT_95_addConstantUImmOperands_LT_5_44__32_33_GT_:
2600 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2601 Operands[*(p + 1)]->setConstraint("m");
2602 NumMCOperands += 1;
2603 break;
2604 case CVT_95_addConstantUImmOperands_LT_5_44__32_32_GT_:
2605 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2606 Operands[*(p + 1)]->setConstraint("m");
2607 NumMCOperands += 1;
2608 break;
2609 case CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_:
2610 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2611 Operands[*(p + 1)]->setConstraint("m");
2612 NumMCOperands += 1;
2613 break;
2614 case CVT_95_addGPR32NonZeroAsmRegOperands:
2615 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2616 Operands[*(p + 1)]->setConstraint("m");
2617 NumMCOperands += 1;
2618 break;
2619 case CVT_95_addGPR32ZeroAsmRegOperands:
2620 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2621 Operands[*(p + 1)]->setConstraint("m");
2622 NumMCOperands += 1;
2623 break;
2624 case CVT_95_addMemOperands:
2625 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2626 Operands[*(p + 1)]->setConstraint("m");
2627 NumMCOperands += 2;
2628 break;
2629 case CVT_95_addConstantUImmOperands_LT_2_44__32_1_GT_:
2630 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2631 Operands[*(p + 1)]->setConstraint("m");
2632 NumMCOperands += 1;
2633 break;
2634 case CVT_95_addCOP0AsmRegOperands:
2635 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2636 Operands[*(p + 1)]->setConstraint("m");
2637 NumMCOperands += 1;
2638 break;
2639 case CVT_regR0_64:
2640 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2641 Operands[*(p + 1)]->setConstraint("m");
2642 ++NumMCOperands;
2643 break;
2644 case CVT_95_addACC64DSPAsmRegOperands:
2645 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2646 Operands[*(p + 1)]->setConstraint("m");
2647 NumMCOperands += 1;
2648 break;
2649 case CVT_95_addConstantUImmOperands_LT_1_GT_:
2650 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2651 Operands[*(p + 1)]->setConstraint("m");
2652 NumMCOperands += 1;
2653 break;
2654 case CVT_regR31:
2655 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2656 Operands[*(p + 1)]->setConstraint("m");
2657 ++NumMCOperands;
2658 break;
2659 case CVT_regR31_64:
2660 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2661 Operands[*(p + 1)]->setConstraint("m");
2662 ++NumMCOperands;
2663 break;
2664 case CVT_95_addCOP3AsmRegOperands:
2665 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2666 Operands[*(p + 1)]->setConstraint("m");
2667 NumMCOperands += 1;
2668 break;
2669 case CVT_95_addConstantSImmOperands_LT_10_44__32_0_GT_:
2670 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2671 Operands[*(p + 1)]->setConstraint("m");
2672 NumMCOperands += 1;
2673 break;
2674 case CVT_95_addConstantUImmOperands_LT_32_GT_:
2675 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2676 Operands[*(p + 1)]->setConstraint("m");
2677 NumMCOperands += 1;
2678 break;
2679 case CVT_95_addStrictlyAFGR64AsmRegOperands:
2680 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2681 Operands[*(p + 1)]->setConstraint("m");
2682 NumMCOperands += 1;
2683 break;
2684 case CVT_95_addStrictlyFGR64AsmRegOperands:
2685 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2686 Operands[*(p + 1)]->setConstraint("m");
2687 NumMCOperands += 1;
2688 break;
2689 case CVT_95_addStrictlyFGR32AsmRegOperands:
2690 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2691 Operands[*(p + 1)]->setConstraint("m");
2692 NumMCOperands += 1;
2693 break;
2694 case CVT_95_addConstantUImmOperands_LT_7_44__32__MINUS_1_GT_:
2695 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2696 Operands[*(p + 1)]->setConstraint("m");
2697 NumMCOperands += 1;
2698 break;
2699 case CVT_95_addRegListOperands:
2700 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2701 Operands[*(p + 1)]->setConstraint("m");
2702 NumMCOperands += 1;
2703 break;
2704 case CVT_regAC0:
2705 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2706 Operands[*(p + 1)]->setConstraint("m");
2707 ++NumMCOperands;
2708 break;
2709 case CVT_95_addGPRMM16AsmRegMovePPairFirstOperands:
2710 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2711 Operands[*(p + 1)]->setConstraint("m");
2712 NumMCOperands += 1;
2713 break;
2714 case CVT_95_addGPRMM16AsmRegMovePPairSecondOperands:
2715 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2716 Operands[*(p + 1)]->setConstraint("m");
2717 NumMCOperands += 1;
2718 break;
2719 case CVT_95_addGPRMM16AsmRegMovePOperands:
2720 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2721 Operands[*(p + 1)]->setConstraint("m");
2722 NumMCOperands += 1;
2723 break;
2724 case CVT_95_addHI32DSPAsmRegOperands:
2725 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2726 Operands[*(p + 1)]->setConstraint("m");
2727 NumMCOperands += 1;
2728 break;
2729 case CVT_95_addLO32DSPAsmRegOperands:
2730 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2731 Operands[*(p + 1)]->setConstraint("m");
2732 NumMCOperands += 1;
2733 break;
2734 case CVT_regR16:
2735 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2736 Operands[*(p + 1)]->setConstraint("m");
2737 ++NumMCOperands;
2738 break;
2739 case CVT_95_addConstantUImmOperands_LT_7_44__32_0_GT_:
2740 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2741 Operands[*(p + 1)]->setConstraint("m");
2742 NumMCOperands += 1;
2743 break;
2744 case CVT_95_addHWRegsAsmRegOperands:
2745 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2746 Operands[*(p + 1)]->setConstraint("m");
2747 NumMCOperands += 1;
2748 break;
2749 case CVT_95_addGPRMM16AsmRegZeroOperands:
2750 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2751 Operands[*(p + 1)]->setConstraint("m");
2752 NumMCOperands += 1;
2753 break;
2754 case CVT_95_addConstantUImmOperands_LT_20_44__32_0_GT_:
2755 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2756 Operands[*(p + 1)]->setConstraint("m");
2757 NumMCOperands += 1;
2758 break;
2759 case CVT_95_addConstantSImmOperands_LT_6_44__32_0_GT_:
2760 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2761 Operands[*(p + 1)]->setConstraint("m");
2762 NumMCOperands += 1;
2763 break;
2764 case CVT_imm_95_17:
2765 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2766 Operands[*(p + 1)]->setConstraint("");
2767 ++NumMCOperands;
2768 break;
2769 case CVT_imm_95_16:
2770 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2771 Operands[*(p + 1)]->setConstraint("");
2772 ++NumMCOperands;
2773 break;
2774 case CVT_imm_95_18:
2775 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2776 Operands[*(p + 1)]->setConstraint("");
2777 ++NumMCOperands;
2778 break;
2779 case CVT_imm_95_19:
2780 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2781 Operands[*(p + 1)]->setConstraint("");
2782 ++NumMCOperands;
2783 break;
2784 case CVT_imm_95_4:
2785 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2786 Operands[*(p + 1)]->setConstraint("");
2787 ++NumMCOperands;
2788 break;
2789 case CVT_imm_95_2:
2790 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2791 Operands[*(p + 1)]->setConstraint("");
2792 ++NumMCOperands;
2793 break;
2794 case CVT_imm_95_6:
2795 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2796 Operands[*(p + 1)]->setConstraint("");
2797 ++NumMCOperands;
2798 break;
2799 case CVT_imm_95_5:
2800 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2801 Operands[*(p + 1)]->setConstraint("");
2802 ++NumMCOperands;
2803 break;
2804 case CVT_imm_95_31:
2805 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2806 Operands[*(p + 1)]->setConstraint("");
2807 ++NumMCOperands;
2808 break;
2809 }
2810 }
2811}
2812
2813namespace {
2814
2815/// MatchClassKind - The kinds of classes which participate in
2816/// instruction matching.
2817enum MatchClassKind {
2818 InvalidMatchClass = 0,
2819 OptionalMatchClass = 1,
2820 MCK__HASH_, // '#'
2821 MCK__40_, // '('
2822 MCK__41_, // ')'
2823 MCK_0, // '0'
2824 MCK_16, // '16'
2825 MCK__91_, // '['
2826 MCK__93_, // ']'
2827 MCK_bit, // 'bit'
2828 MCK_inst, // 'inst'
2829 MCK_LAST_TOKEN = MCK_inst,
2830 MCK_Reg37, // derived register class
2831 MCK_Reg19, // derived register class
2832 MCK_ACC128, // register class 'ACC128'
2833 MCK_ACC64, // register class 'ACC64'
2834 MCK_CPURAReg, // register class 'CPURAReg,R31'
2835 MCK_CPUSPReg, // register class 'CPUSPReg,SP32,R29'
2836 MCK_DSPCC, // register class 'DSPCC'
2837 MCK_GP32, // register class 'GP32'
2838 MCK_GP64, // register class 'GP64'
2839 MCK_GPR32ZERO, // register class 'GPR32ZERO,R0'
2840 MCK_HI32, // register class 'HI32'
2841 MCK_HI64, // register class 'HI64'
2842 MCK_LO32, // register class 'LO32'
2843 MCK_LO64, // register class 'LO64'
2844 MCK_PC, // register class 'PC'
2845 MCK_SP64, // register class 'SP64'
2846 MCK_Reg32, // derived register class
2847 MCK_Reg13, // derived register class
2848 MCK_Reg33, // derived register class
2849 MCK_Reg31, // derived register class
2850 MCK_Reg30, // derived register class
2851 MCK_Reg14, // derived register class
2852 MCK_Reg11, // derived register class
2853 MCK_GPRMM16MovePPairFirst, // register class 'GPRMM16MovePPairFirst'
2854 MCK_OCTEON_MPL, // register class 'OCTEON_MPL'
2855 MCK_OCTEON_P, // register class 'OCTEON_P'
2856 MCK_Reg28, // derived register class
2857 MCK_Reg23, // derived register class
2858 MCK_Reg9, // derived register class
2859 MCK_Reg4, // derived register class
2860 MCK_ACC64DSP, // register class 'ACC64DSP'
2861 MCK_HI32DSP, // register class 'HI32DSP'
2862 MCK_LO32DSP, // register class 'LO32DSP'
2863 MCK_Reg34, // derived register class
2864 MCK_GPRMM16MovePPairSecond, // register class 'GPRMM16MovePPairSecond'
2865 MCK_Reg29, // derived register class
2866 MCK_Reg27, // derived register class
2867 MCK_Reg10, // derived register class
2868 MCK_Reg8, // derived register class
2869 MCK_Reg25, // derived register class
2870 MCK_Reg22, // derived register class
2871 MCK_Reg21, // derived register class
2872 MCK_CPU16Regs, // register class 'CPU16Regs,GPRMM16'
2873 MCK_FCC, // register class 'FCC'
2874 MCK_GPRMM16MoveP, // register class 'GPRMM16MoveP'
2875 MCK_GPRMM16Zero, // register class 'GPRMM16Zero'
2876 MCK_Reg26, // derived register class
2877 MCK_CPU16RegsPlusSP, // register class 'CPU16RegsPlusSP'
2878 MCK_AFGR64, // register class 'AFGR64'
2879 MCK_MSA128WEvens, // register class 'MSA128WEvens'
2880 MCK_Reg24, // derived register class
2881 MCK_GPR32NONZERO, // register class 'GPR32NONZERO'
2882 MCK_CCR, // register class 'CCR'
2883 MCK_COP0, // register class 'COP0'
2884 MCK_COP2, // register class 'COP2'
2885 MCK_COP3, // register class 'COP3'
2886 MCK_DSPR, // register class 'DSPR,GPR32'
2887 MCK_FGR32, // register class 'FGR32'
2888 MCK_FGR64, // register class 'FGR64'
2889 MCK_GPR64, // register class 'GPR64'
2890 MCK_HWRegs, // register class 'HWRegs'
2891 MCK_MSA128B, // register class 'MSA128B,MSA128D,MSA128H,MSA128W'
2892 MCK_MSACtrl, // register class 'MSACtrl'
2893 MCK_LAST_REGISTER = MCK_MSACtrl,
2894 MCK_RegByHwMode_mips_ptr_rc, // register class by hwmode
2895 MCK_RegByHwMode_ptr_gp_rc, // register class by hwmode
2896 MCK_RegByHwMode_ptr_gpr16mm_rc, // register class by hwmode
2897 MCK_RegByHwMode_ptr_sp_rc, // register class by hwmode
2898 MCK_LAST_REGCLASS_BY_HWMODE = MCK_RegByHwMode_ptr_sp_rc,
2899 MCK_ACC64DSPAsmReg, // user defined class 'ACC64DSPAsmOperand'
2900 MCK_AFGR64AsmReg, // user defined class 'AFGR64AsmOperand'
2901 MCK_SImmOffset9_0, // user defined class 'anonymous_14694'
2902 MCK_SImmOffset10_0, // user defined class 'anonymous_14695'
2903 MCK_SImmOffset11_0, // user defined class 'anonymous_14696'
2904 MCK_SImmOffset12_0, // user defined class 'anonymous_14697'
2905 MCK_SImmOffset16_0, // user defined class 'anonymous_14698'
2906 MCK_SImmOffset10_1, // user defined class 'anonymous_14699'
2907 MCK_SImmOffset10_2, // user defined class 'anonymous_14700'
2908 MCK_SImmOffset10_3, // user defined class 'anonymous_14701'
2909 MCK_UImmOffset4_00, // user defined class 'anonymous_15869'
2910 MCK_UImmOffset4_10, // user defined class 'anonymous_15870'
2911 MCK_UImmOffset4_20, // user defined class 'anonymous_15871'
2912 MCK_UImmOffset4_0Minus1, // user defined class 'anonymous_15872'
2913 MCK_UImmOffset5_20, // user defined class 'anonymous_15873'
2914 MCK_SImmOffset7_2, // user defined class 'anonymous_15874'
2915 MCK_UImmOffset6_00, // user defined class 'anonymous_15875'
2916 MCK_SImmPtr, // user defined class 'SImmPtrAsmOperand'
2917 MCK_AnyOffset, // user defined class 'AnyOffsetAsmOperand'
2918 MCK_CCRAsmReg, // user defined class 'CCRAsmOperand'
2919 MCK_COP0AsmReg, // user defined class 'COP0AsmOperand'
2920 MCK_COP2AsmReg, // user defined class 'COP2AsmOperand'
2921 MCK_COP3AsmReg, // user defined class 'COP3AsmOperand'
2922 MCK_ConstantImm, // user defined class 'ConstantImmAsmOperandClass'
2923 MCK_FCCAsmReg, // user defined class 'FCCRegsAsmOperand'
2924 MCK_FGR32AsmReg, // user defined class 'FGR32AsmOperand'
2925 MCK_FGR64AsmReg, // user defined class 'FGR64AsmOperand'
2926 MCK_GPR32AsmReg, // user defined class 'GPR32AsmOperand'
2927 MCK_GPR32NonZeroAsmReg, // user defined class 'GPR32NonZeroAsmOperand'
2928 MCK_GPR32ZeroAsmReg, // user defined class 'GPR32ZeroAsmOperand'
2929 MCK_GPR64AsmReg, // user defined class 'GPR64AsmOperand'
2930 MCK_GPRMM16AsmReg, // user defined class 'GPRMM16AsmOperand'
2931 MCK_GPRMM16AsmRegMoveP, // user defined class 'GPRMM16AsmOperandMoveP'
2932 MCK_GPRMM16AsmRegMovePPairFirst, // user defined class 'GPRMM16AsmOperandMovePPairFirst'
2933 MCK_GPRMM16AsmRegMovePPairSecond, // user defined class 'GPRMM16AsmOperandMovePPairSecond'
2934 MCK_GPRMM16AsmRegZero, // user defined class 'GPRMM16AsmOperandZero'
2935 MCK_HI32DSPAsmReg, // user defined class 'HI32DSPAsmOperand'
2936 MCK_HWRegsAsmReg, // user defined class 'HWRegsAsmOperand'
2937 MCK_Imm, // user defined class 'ImmAsmOperand'
2938 MCK_LO32DSPAsmReg, // user defined class 'LO32DSPAsmOperand'
2939 MCK_MSA128AsmReg, // user defined class 'MSA128AsmOperand'
2940 MCK_MSACtrlAsmReg, // user defined class 'MSACtrlAsmOperand'
2941 MCK_InvNum, // user defined class 'MipsInvertedImmoperand'
2942 MCK_JumpTarget, // user defined class 'MipsJumpTargetAsmOperand'
2943 MCK_Mem, // user defined class 'MipsMemAsmOperand'
2944 MCK_MemBaseGP, // user defined class 'MemBaseGPAsmOperand'
2945 MCK_MemBaseSP, // user defined class 'MemBaseSPAsmOperand'
2946 MCK_PtrReg, // user defined class 'PtrRegAsmOperand'
2947 MCK_RegList16, // user defined class 'RegList16AsmOperand'
2948 MCK_RegList, // user defined class 'RegListAsmOperand'
2949 MCK_Simm18_Lsl3, // user defined class 'Simm18Lsl3AsmOperand'
2950 MCK_Simm19_Lsl2, // user defined class 'Simm19Lsl2AsmOperand'
2951 MCK_StrictlyAFGR64AsmReg, // user defined class 'StrictlyAFGR64AsmOperand'
2952 MCK_StrictlyFGR32AsmReg, // user defined class 'StrictlyFGR32AsmOperand'
2953 MCK_StrictlyFGR64AsmReg, // user defined class 'StrictlyFGR64AsmOperand'
2954 MCK_ConstantImmz, // user defined class 'ConstantImmzAsmOperandClass'
2955 MCK_ConstantUImm1_0, // user defined class 'ConstantUImm1AsmOperandClass'
2956 MCK_ConstantUImm2_0, // user defined class 'ConstantUImm2AsmOperandClass'
2957 MCK_ConstantUImm2_1, // user defined class 'ConstantUImm2Plus1AsmOperandClass'
2958 MCK_ConstantUImm3_0, // user defined class 'ConstantUImm3AsmOperandClass'
2959 MCK_ConstantSImm4_0, // user defined class 'ConstantSImm4AsmOperandClass'
2960 MCK_ConstantUImm4_0, // user defined class 'ConstantUImm4AsmOperandClass'
2961 MCK_ConstantSImm5_0, // user defined class 'ConstantSImm5AsmOperandClass'
2962 MCK_ConstantUImm5_0, // user defined class 'ConstantUImm5AsmOperandClass'
2963 MCK_ConstantUImm5_1, // user defined class 'ConstantUImm5Plus1AsmOperandClass'
2964 MCK_ConstantUImm5_Plus1_Report_UImm6, // user defined class 'ConstantUImm5Plus1ReportUImm6AsmOperandClass'
2965 MCK_ConstantUImm5_32_Norm, // user defined class 'ConstantUImm5Plus32NormalizeAsmOperandClass'
2966 MCK_ConstantUImm5_32, // user defined class 'ConstantUImm5Plus32AsmOperandClass'
2967 MCK_ConstantUImm5_0_Report_UImm6, // user defined class 'ConstantUImm5ReportUImm6AsmOperandClass'
2968 MCK_ConstantUImm5_33, // user defined class 'ConstantUImm5Plus33AsmOperandClass'
2969 MCK_ConstantUImmRange2_64, // user defined class 'ConstantUImm5_Range2_64AsmOperandClass'
2970 MCK_UImm5Lsl2, // user defined class 'ConstantUImm5Lsl2AsmOperandClass'
2971 MCK_ConstantSImm6_0, // user defined class 'ConstantSImm6AsmOperandClass'
2972 MCK_ConstantUImm6_0, // user defined class 'ConstantUImm6AsmOperandClass'
2973 MCK_UImm6Lsl2, // user defined class 'ConstantUImm6Lsl2AsmOperandClass'
2974 MCK_ConstantUImm7_0, // user defined class 'ConstantUImm7AsmOperandClass'
2975 MCK_UImm7_N1, // user defined class 'ConstantUImm7Sub1AsmOperandClass'
2976 MCK_ConstantUImm8_0, // user defined class 'ConstantUImm8AsmOperandClass'
2977 MCK_SImm7Lsl2, // user defined class 'ConstantSImm7Lsl2AsmOperandClass'
2978 MCK_ConstantSImm9_0, // user defined class 'ConstantSImm9AsmOperandClass'
2979 MCK_ConstantSImm10_0, // user defined class 'ConstantSImm10AsmOperandClass'
2980 MCK_ConstantUImm10_0, // user defined class 'ConstantUImm10AsmOperandClass'
2981 MCK_SImm10Lsl1, // user defined class 'ConstantSImm10Lsl1AsmOperandClass'
2982 MCK_ConstantSImm11_0, // user defined class 'ConstantSImm11AsmOperandClass'
2983 MCK_SImm10Lsl2, // user defined class 'ConstantSImm10Lsl2AsmOperandClass'
2984 MCK_SImm10Lsl3, // user defined class 'ConstantSImm10Lsl3AsmOperandClass'
2985 MCK_SImm16, // user defined class 'SImm16AsmOperandClass'
2986 MCK_SImm16_Relaxed, // user defined class 'SImm16RelaxedAsmOperandClass'
2987 MCK_UImm16_AltRelaxed, // user defined class 'UImm16AltRelaxedAsmOperandClass'
2988 MCK_UImm16, // user defined class 'UImm16AsmOperandClass'
2989 MCK_SImm19Lsl2, // user defined class 'ConstantSImm19Lsl2AsmOperandClass'
2990 MCK_UImm16_Relaxed, // user defined class 'UImm16RelaxedAsmOperandClass'
2991 MCK_ConstantUImm20_0, // user defined class 'ConstantUImm20AsmOperandClass'
2992 MCK_ConstantUImm26_0, // user defined class 'ConstantUImm26AsmOperandClass'
2993 MCK_SImm32, // user defined class 'SImm32AsmOperandClass'
2994 MCK_SImm32_Relaxed, // user defined class 'SImm32RelaxedAsmOperandClass'
2995 MCK_UImm32_Coerced, // user defined class 'UImm32CoercedAsmOperandClass'
2996 NumMatchClassKinds
2997};
2998
2999} // end anonymous namespace
3000
3001static unsigned getDiagKindFromRegisterClass(MatchClassKind RegisterClass) {
3002 return MCTargetAsmParser::Match_InvalidOperand;
3003}
3004
3005[[maybe_unused]] static const MCRegisterClass *getRegClassFromMatchKind(MatchClassKind Kind) {
3006 switch (Kind) {
3007 case MCK_ACC128:
3008 return &getMipsMCRegisterClass(Mips::ACC128RegClassID);
3009 case MCK_ACC64:
3010 return &getMipsMCRegisterClass(Mips::ACC64RegClassID);
3011 case MCK_CPURAReg:
3012 return &getMipsMCRegisterClass(Mips::CPURARegRegClassID);
3013 case MCK_CPUSPReg:
3014 return &getMipsMCRegisterClass(Mips::CPUSPRegRegClassID);
3015 case MCK_DSPCC:
3016 return &getMipsMCRegisterClass(Mips::DSPCCRegClassID);
3017 case MCK_GP32:
3018 return &getMipsMCRegisterClass(Mips::GP32RegClassID);
3019 case MCK_GP64:
3020 return &getMipsMCRegisterClass(Mips::GP64RegClassID);
3021 case MCK_GPR32ZERO:
3022 return &getMipsMCRegisterClass(Mips::GPR32ZERORegClassID);
3023 case MCK_HI32:
3024 return &getMipsMCRegisterClass(Mips::HI32RegClassID);
3025 case MCK_HI64:
3026 return &getMipsMCRegisterClass(Mips::HI64RegClassID);
3027 case MCK_LO32:
3028 return &getMipsMCRegisterClass(Mips::LO32RegClassID);
3029 case MCK_LO64:
3030 return &getMipsMCRegisterClass(Mips::LO64RegClassID);
3031 case MCK_SP64:
3032 return &getMipsMCRegisterClass(Mips::SP64RegClassID);
3033 case MCK_GPRMM16MovePPairFirst:
3034 return &getMipsMCRegisterClass(Mips::GPRMM16MovePPairFirstRegClassID);
3035 case MCK_OCTEON_MPL:
3036 return &getMipsMCRegisterClass(Mips::OCTEON_MPLRegClassID);
3037 case MCK_OCTEON_P:
3038 return &getMipsMCRegisterClass(Mips::OCTEON_PRegClassID);
3039 case MCK_ACC64DSP:
3040 return &getMipsMCRegisterClass(Mips::ACC64DSPRegClassID);
3041 case MCK_HI32DSP:
3042 return &getMipsMCRegisterClass(Mips::HI32DSPRegClassID);
3043 case MCK_LO32DSP:
3044 return &getMipsMCRegisterClass(Mips::LO32DSPRegClassID);
3045 case MCK_GPRMM16MovePPairSecond:
3046 return &getMipsMCRegisterClass(Mips::GPRMM16MovePPairSecondRegClassID);
3047 case MCK_CPU16Regs:
3048 return &getMipsMCRegisterClass(Mips::CPU16RegsRegClassID);
3049 case MCK_FCC:
3050 return &getMipsMCRegisterClass(Mips::FCCRegClassID);
3051 case MCK_GPRMM16MoveP:
3052 return &getMipsMCRegisterClass(Mips::GPRMM16MovePRegClassID);
3053 case MCK_GPRMM16Zero:
3054 return &getMipsMCRegisterClass(Mips::GPRMM16ZeroRegClassID);
3055 case MCK_CPU16RegsPlusSP:
3056 return &getMipsMCRegisterClass(Mips::CPU16RegsPlusSPRegClassID);
3057 case MCK_AFGR64:
3058 return &getMipsMCRegisterClass(Mips::AFGR64RegClassID);
3059 case MCK_MSA128WEvens:
3060 return &getMipsMCRegisterClass(Mips::MSA128WEvensRegClassID);
3061 case MCK_GPR32NONZERO:
3062 return &getMipsMCRegisterClass(Mips::GPR32NONZERORegClassID);
3063 case MCK_CCR:
3064 return &getMipsMCRegisterClass(Mips::CCRRegClassID);
3065 case MCK_COP0:
3066 return &getMipsMCRegisterClass(Mips::COP0RegClassID);
3067 case MCK_COP2:
3068 return &getMipsMCRegisterClass(Mips::COP2RegClassID);
3069 case MCK_COP3:
3070 return &getMipsMCRegisterClass(Mips::COP3RegClassID);
3071 case MCK_DSPR:
3072 return &getMipsMCRegisterClass(Mips::DSPRRegClassID);
3073 case MCK_FGR32:
3074 return &getMipsMCRegisterClass(Mips::FGR32RegClassID);
3075 case MCK_FGR64:
3076 return &getMipsMCRegisterClass(Mips::FGR64RegClassID);
3077 case MCK_GPR64:
3078 return &getMipsMCRegisterClass(Mips::GPR64RegClassID);
3079 case MCK_HWRegs:
3080 return &getMipsMCRegisterClass(Mips::HWRegsRegClassID);
3081 case MCK_MSA128B:
3082 return &getMipsMCRegisterClass(Mips::MSA128BRegClassID);
3083 case MCK_MSACtrl:
3084 return &getMipsMCRegisterClass(Mips::MSACtrlRegClassID);
3085 case MCK_ACC64DSPAsmReg:
3086 return &getMipsMCRegisterClass(Mips::ACC64DSPRegClassID);
3087 case MCK_AFGR64AsmReg:
3088 return &getMipsMCRegisterClass(Mips::AFGR64RegClassID);
3089 case MCK_CCRAsmReg:
3090 return &getMipsMCRegisterClass(Mips::CCRRegClassID);
3091 case MCK_COP0AsmReg:
3092 return &getMipsMCRegisterClass(Mips::COP0RegClassID);
3093 case MCK_COP2AsmReg:
3094 return &getMipsMCRegisterClass(Mips::COP2RegClassID);
3095 case MCK_COP3AsmReg:
3096 return &getMipsMCRegisterClass(Mips::COP3RegClassID);
3097 case MCK_FCCAsmReg:
3098 return &getMipsMCRegisterClass(Mips::FCCRegClassID);
3099 case MCK_FGR32AsmReg:
3100 return &getMipsMCRegisterClass(Mips::FGR32RegClassID);
3101 case MCK_FGR64AsmReg:
3102 return &getMipsMCRegisterClass(Mips::FGR64RegClassID);
3103 case MCK_GPR32AsmReg:
3104 return &getMipsMCRegisterClass(Mips::DSPRRegClassID);
3105 case MCK_GPR32NonZeroAsmReg:
3106 return &getMipsMCRegisterClass(Mips::GPR32NONZERORegClassID);
3107 case MCK_GPR32ZeroAsmReg:
3108 return &getMipsMCRegisterClass(Mips::GPR32ZERORegClassID);
3109 case MCK_GPR64AsmReg:
3110 return &getMipsMCRegisterClass(Mips::GPR64RegClassID);
3111 case MCK_GPRMM16AsmReg:
3112 return &getMipsMCRegisterClass(Mips::CPU16RegsRegClassID);
3113 case MCK_GPRMM16AsmRegMoveP:
3114 return &getMipsMCRegisterClass(Mips::GPRMM16MovePRegClassID);
3115 case MCK_GPRMM16AsmRegMovePPairFirst:
3116 return &getMipsMCRegisterClass(Mips::GPRMM16MovePPairFirstRegClassID);
3117 case MCK_GPRMM16AsmRegMovePPairSecond:
3118 return &getMipsMCRegisterClass(Mips::GPRMM16MovePPairSecondRegClassID);
3119 case MCK_GPRMM16AsmRegZero:
3120 return &getMipsMCRegisterClass(Mips::GPRMM16ZeroRegClassID);
3121 case MCK_HI32DSPAsmReg:
3122 return &getMipsMCRegisterClass(Mips::HI32DSPRegClassID);
3123 case MCK_HWRegsAsmReg:
3124 return &getMipsMCRegisterClass(Mips::HWRegsRegClassID);
3125 case MCK_LO32DSPAsmReg:
3126 return &getMipsMCRegisterClass(Mips::LO32DSPRegClassID);
3127 case MCK_MSA128AsmReg:
3128 return &getMipsMCRegisterClass(Mips::MSA128BRegClassID);
3129 case MCK_MSACtrlAsmReg:
3130 return &getMipsMCRegisterClass(Mips::MSACtrlRegClassID);
3131 case MCK_StrictlyAFGR64AsmReg:
3132 return &getMipsMCRegisterClass(Mips::AFGR64RegClassID);
3133 case MCK_StrictlyFGR32AsmReg:
3134 return &getMipsMCRegisterClass(Mips::FGR32RegClassID);
3135 case MCK_StrictlyFGR64AsmReg:
3136 return &getMipsMCRegisterClass(Mips::FGR64RegClassID);
3137 default:
3138 return nullptr;
3139 }
3140}
3141
3142static MatchClassKind matchTokenString(StringRef Name) {
3143 switch (Name.size()) {
3144 default: break;
3145 case 1: // 6 strings to match.
3146 switch (Name[0]) {
3147 default: break;
3148 case '#': // 1 string to match.
3149 return MCK__HASH_; // "#"
3150 case '(': // 1 string to match.
3151 return MCK__40_; // "("
3152 case ')': // 1 string to match.
3153 return MCK__41_; // ")"
3154 case '0': // 1 string to match.
3155 return MCK_0; // "0"
3156 case '[': // 1 string to match.
3157 return MCK__91_; // "["
3158 case ']': // 1 string to match.
3159 return MCK__93_; // "]"
3160 }
3161 break;
3162 case 2: // 1 string to match.
3163 if (memcmp(Name.data()+0, "16", 2) != 0)
3164 break;
3165 return MCK_16; // "16"
3166 case 3: // 1 string to match.
3167 if (memcmp(Name.data()+0, "bit", 3) != 0)
3168 break;
3169 return MCK_bit; // "bit"
3170 case 4: // 1 string to match.
3171 if (memcmp(Name.data()+0, "inst", 4) != 0)
3172 break;
3173 return MCK_inst; // "inst"
3174 }
3175 return InvalidMatchClass;
3176}
3177
3178/// isSubclass - Compute whether \p A is a subclass of \p B.
3179static bool isSubclass(MatchClassKind A, MatchClassKind B) {
3180 if (A == B)
3181 return true;
3182
3183 [[maybe_unused]] static constexpr struct {
3184 uint32_t Offset;
3185 uint16_t Start;
3186 uint16_t Length;
3187 } Table[] = {
3188 {0, 0, 0},
3189 {0, 0, 0},
3190 {0, 0, 0},
3191 {0, 0, 0},
3192 {0, 0, 0},
3193 {0, 0, 0},
3194 {0, 0, 0},
3195 {0, 0, 0},
3196 {0, 0, 0},
3197 {0, 0, 0},
3198 {0, 0, 0},
3199 {0, 61, 10},
3200 {10, 38, 33},
3201 {43, 0, 0},
3202 {43, 41, 1},
3203 {44, 62, 6},
3204 {50, 58, 10},
3205 {60, 0, 0},
3206 {60, 62, 6},
3207 {66, 61, 10},
3208 {76, 40, 28},
3209 {104, 42, 1},
3210 {105, 0, 0},
3211 {105, 43, 1},
3212 {106, 0, 0},
3213 {106, 0, 0},
3214 {106, 57, 14},
3215 {120, 29, 42},
3216 {162, 32, 36},
3217 {198, 44, 27},
3218 {225, 47, 24},
3219 {249, 37, 34},
3220 {283, 45, 23},
3221 {306, 39, 29},
3222 {335, 49, 19},
3223 {354, 0, 0},
3224 {354, 0, 0},
3225 {354, 46, 25},
3226 {379, 51, 20},
3227 {399, 48, 20},
3228 {419, 55, 13},
3229 {432, 0, 0},
3230 {432, 0, 0},
3231 {432, 0, 0},
3232 {432, 61, 10},
3233 {442, 62, 6},
3234 {448, 51, 20},
3235 {468, 50, 21},
3236 {489, 55, 13},
3237 {502, 53, 15},
3238 {517, 57, 14},
3239 {531, 70, 1},
3240 {532, 70, 1},
3241 {533, 58, 10},
3242 {543, 0, 0},
3243 {543, 67, 1},
3244 {544, 67, 1},
3245 {545, 61, 10},
3246 {555, 62, 6},
3247 {561, 0, 0},
3248 {561, 72, 1},
3249 {562, 70, 1},
3250 {563, 67, 1},
3251 {564, 0, 0},
3252 {564, 0, 0},
3253 {564, 0, 0},
3254 {564, 0, 0},
3255 {564, 0, 0},
3256 {564, 0, 0},
3257 {564, 0, 0},
3258 {564, 0, 0},
3259 {564, 0, 0},
3260 {564, 0, 0},
3261 {564, 0, 0},
3262 {564, 0, 0},
3263 {564, 0, 0},
3264 {564, 0, 0},
3265 {564, 0, 0},
3266 {564, 0, 0},
3267 {564, 0, 0},
3268 {564, 95, 2},
3269 {566, 95, 2},
3270 {568, 95, 2},
3271 {570, 95, 2},
3272 {572, 95, 2},
3273 {574, 95, 2},
3274 {576, 95, 2},
3275 {578, 95, 2},
3276 {580, 95, 2},
3277 {582, 95, 2},
3278 {584, 95, 2},
3279 {586, 95, 2},
3280 {588, 95, 2},
3281 {590, 95, 2},
3282 {592, 95, 2},
3283 {594, 96, 1},
3284 {595, 0, 0},
3285 {595, 0, 0},
3286 {595, 0, 0},
3287 {595, 0, 0},
3288 {595, 0, 0},
3289 {595, 0, 0},
3290 {595, 0, 0},
3291 {595, 0, 0},
3292 {595, 0, 0},
3293 {595, 0, 0},
3294 {595, 0, 0},
3295 {595, 0, 0},
3296 {595, 0, 0},
3297 {595, 0, 0},
3298 {595, 0, 0},
3299 {595, 0, 0},
3300 {595, 0, 0},
3301 {595, 0, 0},
3302 {595, 0, 0},
3303 {595, 0, 0},
3304 {595, 0, 0},
3305 {595, 0, 0},
3306 {595, 0, 0},
3307 {595, 0, 0},
3308 {595, 0, 0},
3309 {595, 0, 0},
3310 {595, 0, 0},
3311 {595, 125, 1},
3312 {596, 125, 1},
3313 {597, 0, 0},
3314 {597, 0, 0},
3315 {597, 0, 0},
3316 {597, 0, 0},
3317 {597, 0, 0},
3318 {597, 0, 0},
3319 {597, 0, 0},
3320 {597, 0, 0},
3321 {597, 134, 41},
3322 {638, 135, 40},
3323 {678, 137, 38},
3324 {716, 137, 38},
3325 {754, 138, 37},
3326 {791, 139, 36},
3327 {827, 140, 35},
3328 {862, 141, 34},
3329 {896, 142, 33},
3330 {929, 143, 32},
3331 {961, 144, 31},
3332 {992, 145, 30},
3333 {1022, 146, 29},
3334 {1051, 147, 28},
3335 {1079, 148, 27},
3336 {1106, 149, 26},
3337 {1132, 150, 25},
3338 {1157, 151, 24},
3339 {1181, 152, 23},
3340 {1204, 153, 22},
3341 {1226, 154, 21},
3342 {1247, 155, 20},
3343 {1267, 156, 19},
3344 {1286, 157, 18},
3345 {1304, 158, 17},
3346 {1321, 159, 16},
3347 {1337, 160, 15},
3348 {1352, 161, 14},
3349 {1366, 162, 13},
3350 {1379, 163, 12},
3351 {1391, 164, 11},
3352 {1402, 165, 10},
3353 {1412, 169, 6},
3354 {1418, 169, 6},
3355 {1424, 169, 6},
3356 {1430, 170, 5},
3357 {1435, 170, 5},
3358 {1440, 171, 4},
3359 {1444, 172, 3},
3360 {1447, 173, 2},
3361 {1449, 174, 1},
3362 {1450, 0, 0},
3363 };
3364
3365 static constexpr uint8_t Data[] = {
3366 0x01,
3367 0x06,
3368 0x80,
3369 0x01,
3370 0x00,
3371 0x1C,
3372 0x46,
3373 0x18,
3374 0x06,
3375 0x18,
3376 0x00,
3377 0x18,
3378 0x80,
3379 0x47,
3380 0x80,
3381 0x03,
3382 0x80,
3383 0xA4,
3384 0x10,
3385 0x01,
3386 0x16,
3387 0x80,
3388 0x88,
3389 0x14,
3390 0x61,
3391 0x52,
3392 0x88,
3393 0x00,
3394 0x53,
3395 0x88,
3396 0x00,
3397 0x07,
3398 0xCC,
3399 0x21,
3400 0x02,
3401 0x8C,
3402 0x48,
3403 0x11,
3404 0x0E,
3405 0x18,
3406 0x2D,
3407 0xC2,
3408 0x48,
3409 0x11,
3410 0xC6,
3411 0x20,
3412 0x02,
3413 0x1C,
3414 0x00,
3415 0xC0,
3416 0x50,
3417 0x22,
3418 0x1C,
3419 0x80,
3420 0x01,
3421 0x86,
3422 0x01,
3423 0x04,
3424 0x58,
3425 0x88,
3426 0x00,
3427 0x03,
3428 0x61,
3429 0x8A,
3430 0x30,
3431 0x02,
3432 0x3C,
3433 0xC2,
3434 0x03,
3435 0x0C,
3436 0xFF,
3437 0xFF,
3438 0xFF,
3439 0xFF,
3440 0x7F,
3441 0xFF,
3442 0xFF,
3443 0xFF,
3444 0x1F,
3445 0x7F,
3446 0xFF,
3447 0xFF,
3448 0xFF,
3449 0x1F,
3450 0xFF,
3451 0xFF,
3452 0xFF,
3453 0xFF,
3454 0xC7,
3455 0xFF,
3456 0xFF,
3457 0xFF,
3458 0xFF,
3459 0xF1,
3460 0xFF,
3461 0xFF,
3462 0xFF,
3463 0x3F,
3464 0xFE,
3465 0xFF,
3466 0xFF,
3467 0xFF,
3468 0xE3,
3469 0xFF,
3470 0xFF,
3471 0xFF,
3472 0x1F,
3473 0xFF,
3474 0xFF,
3475 0xFF,
3476 0x7F,
3477 0xFC,
3478 0xFF,
3479 0xFF,
3480 0xFF,
3481 0xF8,
3482 0xFF,
3483 0xFF,
3484 0xFF,
3485 0xF8,
3486 0xFF,
3487 0xFF,
3488 0x7F,
3489 0xFC,
3490 0xFF,
3491 0xFF,
3492 0x1F,
3493 0xFF,
3494 0xFF,
3495 0xFF,
3496 0xE3,
3497 0xFF,
3498 0xFF,
3499 0x3F,
3500 0xFE,
3501 0xFF,
3502 0xFF,
3503 0xF1,
3504 0xFF,
3505 0xFF,
3506 0xC7,
3507 0xFF,
3508 0xFF,
3509 0x8F,
3510 0xFF,
3511 0xFF,
3512 0x8F,
3513 0xFF,
3514 0xFF,
3515 0xC7,
3516 0xFF,
3517 0xFF,
3518 0xF1,
3519 0xFF,
3520 0x3F,
3521 0xFE,
3522 0xFF,
3523 0xE3,
3524 0xFF,
3525 0x1F,
3526 0xFF,
3527 0x7F,
3528 0xFC,
3529 0xFF,
3530 0xF8,
3531 0xFF,
3532 0xF8,
3533 0x7F,
3534 0xFC,
3535 0x1F,
3536 0xFF,
3537 0xE3,
3538 0x3F,
3539 0xFE,
3540 0xF1,
3541 0xC7,
3542 0xFF,
3543 0xFF,
3544 0xFF,
3545 0xFF,
3546 0xFF,
3547 0x03,
3548 };
3549
3550 auto &Entry = Table[A];
3551 unsigned Idx = B - Entry.Start;
3552 if (Idx >= Entry.Length)
3553 return false;
3554 Idx += Entry.Offset;
3555 return (Data[Idx / 8] >> (Idx % 8)) & 1;
3556}
3557
3558static constexpr MatchClassKind RegClassByHwModeMatchTable[2][4] = {
3559 { // DefaultMode
3560 MCK_DSPR, // mips_ptr_rc
3561 MCK_GP32, // ptr_gp_rc
3562 MCK_CPU16Regs, // ptr_gpr16mm_rc
3563 MCK_CPUSPReg, // ptr_sp_rc
3564 },
3565 { // MIPS64
3566 MCK_GPR64, // mips_ptr_rc
3567 MCK_GP64, // ptr_gp_rc
3568 MCK_CPU16Regs, // ptr_gpr16mm_rc
3569 MCK_SP64, // ptr_sp_rc
3570 },
3571};
3572
3573static_assert(MCK_LAST_REGCLASS_BY_HWMODE - MCK_LAST_REGISTER == 4);
3574
3575[[maybe_unused]] static inline MatchClassKind
3576remapRegClassByHwMode(unsigned Kind, const MCSubtargetInfo &STI) {
3577 if (Kind > MCK_LAST_REGISTER && Kind <= MCK_LAST_REGCLASS_BY_HWMODE) {
3578 unsigned HwMode = STI.getHwMode(MCSubtargetInfo::HwMode_RegInfo);
3579 assert(HwMode < 2 && "Invalid HwMode");
3580 return RegClassByHwModeMatchTable[HwMode][Kind - (MCK_LAST_REGISTER + 1)];
3581 }
3582 return static_cast<MatchClassKind>(Kind);
3583}
3584
3585static unsigned validateOperandClass(MCParsedAsmOperand &GOp, MatchClassKind Kind, const MCSubtargetInfo &STI) {
3586 MipsOperand &Operand = (MipsOperand &)GOp;
3587 if (Kind == InvalidMatchClass)
3588 return MCTargetAsmParser::Match_InvalidOperand;
3589
3590 if (Kind <= MCK_LAST_TOKEN) {
3591 if (Operand.isToken() &&
3592 isSubclass(matchTokenString(Operand.getToken()), Kind))
3593 return MCTargetAsmParser::Match_Success;
3594 return MCTargetAsmParser::Match_InvalidOperand;
3595 }
3596
3597 switch (Kind) {
3598 default: break;
3599 case MCK_ACC64DSPAsmReg: {
3600 DiagnosticPredicate DP(Operand.isACCAsmReg());
3601 if (DP.isMatch())
3602 return MCTargetAsmParser::Match_Success;
3603 break;
3604 }
3605 case MCK_AFGR64AsmReg: {
3606 DiagnosticPredicate DP(Operand.isFGRAsmReg());
3607 if (DP.isMatch())
3608 return MCTargetAsmParser::Match_Success;
3609 break;
3610 }
3611 case MCK_SImmOffset9_0: {
3612 DiagnosticPredicate DP(Operand.isScaledSImm<9, 0>());
3613 if (DP.isMatch())
3614 return MCTargetAsmParser::Match_Success;
3615 if (DP.isNearMatch())
3616 return MipsAsmParser::Match_MemSImm9;
3617 break;
3618 }
3619 case MCK_SImmOffset10_0: {
3620 DiagnosticPredicate DP(Operand.isScaledSImm<10, 0>());
3621 if (DP.isMatch())
3622 return MCTargetAsmParser::Match_Success;
3623 if (DP.isNearMatch())
3624 return MipsAsmParser::Match_MemSImm10;
3625 break;
3626 }
3627 case MCK_SImmOffset11_0: {
3628 DiagnosticPredicate DP(Operand.isScaledSImm<11, 0>());
3629 if (DP.isMatch())
3630 return MCTargetAsmParser::Match_Success;
3631 if (DP.isNearMatch())
3632 return MipsAsmParser::Match_MemSImm11;
3633 break;
3634 }
3635 case MCK_SImmOffset12_0: {
3636 DiagnosticPredicate DP(Operand.isScaledSImm<12, 0>());
3637 if (DP.isMatch())
3638 return MCTargetAsmParser::Match_Success;
3639 if (DP.isNearMatch())
3640 return MipsAsmParser::Match_MemSImm12;
3641 break;
3642 }
3643 case MCK_SImmOffset16_0: {
3644 DiagnosticPredicate DP(Operand.isScaledSImm<16, 0>());
3645 if (DP.isMatch())
3646 return MCTargetAsmParser::Match_Success;
3647 if (DP.isNearMatch())
3648 return MipsAsmParser::Match_MemSImm16;
3649 break;
3650 }
3651 case MCK_SImmOffset10_1: {
3652 DiagnosticPredicate DP(Operand.isScaledSImm<10, 1>());
3653 if (DP.isMatch())
3654 return MCTargetAsmParser::Match_Success;
3655 if (DP.isNearMatch())
3656 return MipsAsmParser::Match_MemSImm10Lsl1;
3657 break;
3658 }
3659 case MCK_SImmOffset10_2: {
3660 DiagnosticPredicate DP(Operand.isScaledSImm<10, 2>());
3661 if (DP.isMatch())
3662 return MCTargetAsmParser::Match_Success;
3663 if (DP.isNearMatch())
3664 return MipsAsmParser::Match_MemSImm10Lsl2;
3665 break;
3666 }
3667 case MCK_SImmOffset10_3: {
3668 DiagnosticPredicate DP(Operand.isScaledSImm<10, 3>());
3669 if (DP.isMatch())
3670 return MCTargetAsmParser::Match_Success;
3671 if (DP.isNearMatch())
3672 return MipsAsmParser::Match_MemSImm10Lsl3;
3673 break;
3674 }
3675 case MCK_UImmOffset4_00: {
3676 DiagnosticPredicate DP(Operand.isScaledUImm<4, 0, 0>());
3677 if (DP.isMatch())
3678 return MCTargetAsmParser::Match_Success;
3679 if (DP.isNearMatch())
3680 return MipsAsmParser::Match_ConstantMemOffset;
3681 break;
3682 }
3683 case MCK_UImmOffset4_10: {
3684 DiagnosticPredicate DP(Operand.isScaledUImm<4, 1, 0>());
3685 if (DP.isMatch())
3686 return MCTargetAsmParser::Match_Success;
3687 if (DP.isNearMatch())
3688 return MipsAsmParser::Match_ConstantMemOffset;
3689 break;
3690 }
3691 case MCK_UImmOffset4_20: {
3692 DiagnosticPredicate DP(Operand.isScaledUImm<4, 2, 0>());
3693 if (DP.isMatch())
3694 return MCTargetAsmParser::Match_Success;
3695 if (DP.isNearMatch())
3696 return MipsAsmParser::Match_ConstantMemOffset;
3697 break;
3698 }
3699 case MCK_UImmOffset4_0Minus1: {
3700 DiagnosticPredicate DP(Operand.isScaledUImm<4, 0, -1>());
3701 if (DP.isMatch())
3702 return MCTargetAsmParser::Match_Success;
3703 if (DP.isNearMatch())
3704 return MipsAsmParser::Match_ConstantMemOffset;
3705 break;
3706 }
3707 case MCK_UImmOffset5_20: {
3708 DiagnosticPredicate DP(Operand.isScaledUImm<5, 2, 0>());
3709 if (DP.isMatch())
3710 return MCTargetAsmParser::Match_Success;
3711 if (DP.isNearMatch())
3712 return MipsAsmParser::Match_ConstantMemOffset;
3713 break;
3714 }
3715 case MCK_SImmOffset7_2: {
3716 DiagnosticPredicate DP(Operand.isScaledSImm<7, 2>());
3717 if (DP.isMatch())
3718 return MCTargetAsmParser::Match_Success;
3719 if (DP.isNearMatch())
3720 return MipsAsmParser::Match_SImm7_Lsl2;
3721 break;
3722 }
3723 case MCK_UImmOffset6_00: {
3724 DiagnosticPredicate DP(Operand.isScaledUImm<6, 0, 0>());
3725 if (DP.isMatch())
3726 return MCTargetAsmParser::Match_Success;
3727 if (DP.isNearMatch())
3728 return MipsAsmParser::Match_ConstantMemOffset;
3729 break;
3730 }
3731 case MCK_SImmPtr: {
3732 DiagnosticPredicate DP(Operand.isSImmPtr());
3733 if (DP.isMatch())
3734 return MCTargetAsmParser::Match_Success;
3735 if (DP.isNearMatch())
3736 return MipsAsmParser::Match_MemSImmPtr;
3737 break;
3738 }
3739 case MCK_AnyOffset: {
3740 DiagnosticPredicate DP(Operand.isImm());
3741 if (DP.isMatch())
3742 return MCTargetAsmParser::Match_Success;
3743 break;
3744 }
3745 case MCK_CCRAsmReg: {
3746 DiagnosticPredicate DP(Operand.isCCRAsmReg());
3747 if (DP.isMatch())
3748 return MCTargetAsmParser::Match_Success;
3749 break;
3750 }
3751 case MCK_COP0AsmReg: {
3752 DiagnosticPredicate DP(Operand.isCOP0AsmReg());
3753 if (DP.isMatch())
3754 return MCTargetAsmParser::Match_Success;
3755 break;
3756 }
3757 case MCK_COP2AsmReg: {
3758 DiagnosticPredicate DP(Operand.isCOP2AsmReg());
3759 if (DP.isMatch())
3760 return MCTargetAsmParser::Match_Success;
3761 break;
3762 }
3763 case MCK_COP3AsmReg: {
3764 DiagnosticPredicate DP(Operand.isCOP3AsmReg());
3765 if (DP.isMatch())
3766 return MCTargetAsmParser::Match_Success;
3767 break;
3768 }
3769 case MCK_ConstantImm: {
3770 DiagnosticPredicate DP(Operand.isConstantImm());
3771 if (DP.isMatch())
3772 return MCTargetAsmParser::Match_Success;
3773 break;
3774 }
3775 case MCK_FCCAsmReg: {
3776 DiagnosticPredicate DP(Operand.isFCCAsmReg());
3777 if (DP.isMatch())
3778 return MCTargetAsmParser::Match_Success;
3779 break;
3780 }
3781 case MCK_FGR32AsmReg: {
3782 DiagnosticPredicate DP(Operand.isFGRAsmReg());
3783 if (DP.isMatch())
3784 return MCTargetAsmParser::Match_Success;
3785 break;
3786 }
3787 case MCK_FGR64AsmReg: {
3788 DiagnosticPredicate DP(Operand.isFGRAsmReg());
3789 if (DP.isMatch())
3790 return MCTargetAsmParser::Match_Success;
3791 break;
3792 }
3793 case MCK_GPR32AsmReg: {
3794 DiagnosticPredicate DP(Operand.isGPRAsmReg());
3795 if (DP.isMatch())
3796 return MCTargetAsmParser::Match_Success;
3797 break;
3798 }
3799 case MCK_GPR32NonZeroAsmReg: {
3800 DiagnosticPredicate DP(Operand.isGPRNonZeroAsmReg());
3801 if (DP.isMatch())
3802 return MCTargetAsmParser::Match_Success;
3803 break;
3804 }
3805 case MCK_GPR32ZeroAsmReg: {
3806 DiagnosticPredicate DP(Operand.isGPRZeroAsmReg());
3807 if (DP.isMatch())
3808 return MCTargetAsmParser::Match_Success;
3809 break;
3810 }
3811 case MCK_GPR64AsmReg: {
3812 DiagnosticPredicate DP(Operand.isGPRAsmReg());
3813 if (DP.isMatch())
3814 return MCTargetAsmParser::Match_Success;
3815 break;
3816 }
3817 case MCK_GPRMM16AsmReg: {
3818 DiagnosticPredicate DP(Operand.isMM16AsmReg());
3819 if (DP.isMatch())
3820 return MCTargetAsmParser::Match_Success;
3821 break;
3822 }
3823 case MCK_GPRMM16AsmRegMoveP: {
3824 DiagnosticPredicate DP(Operand.isMM16AsmRegMoveP());
3825 if (DP.isMatch())
3826 return MCTargetAsmParser::Match_Success;
3827 break;
3828 }
3829 case MCK_GPRMM16AsmRegMovePPairFirst: {
3830 DiagnosticPredicate DP(Operand.isMM16AsmRegMovePPairFirst());
3831 if (DP.isMatch())
3832 return MCTargetAsmParser::Match_Success;
3833 break;
3834 }
3835 case MCK_GPRMM16AsmRegMovePPairSecond: {
3836 DiagnosticPredicate DP(Operand.isMM16AsmRegMovePPairSecond());
3837 if (DP.isMatch())
3838 return MCTargetAsmParser::Match_Success;
3839 break;
3840 }
3841 case MCK_GPRMM16AsmRegZero: {
3842 DiagnosticPredicate DP(Operand.isMM16AsmRegZero());
3843 if (DP.isMatch())
3844 return MCTargetAsmParser::Match_Success;
3845 break;
3846 }
3847 case MCK_HI32DSPAsmReg: {
3848 DiagnosticPredicate DP(Operand.isACCAsmReg());
3849 if (DP.isMatch())
3850 return MCTargetAsmParser::Match_Success;
3851 break;
3852 }
3853 case MCK_HWRegsAsmReg: {
3854 DiagnosticPredicate DP(Operand.isHWRegsAsmReg());
3855 if (DP.isMatch())
3856 return MCTargetAsmParser::Match_Success;
3857 break;
3858 }
3859 case MCK_Imm: {
3860 DiagnosticPredicate DP(Operand.isImm());
3861 if (DP.isMatch())
3862 return MCTargetAsmParser::Match_Success;
3863 break;
3864 }
3865 case MCK_LO32DSPAsmReg: {
3866 DiagnosticPredicate DP(Operand.isACCAsmReg());
3867 if (DP.isMatch())
3868 return MCTargetAsmParser::Match_Success;
3869 break;
3870 }
3871 case MCK_MSA128AsmReg: {
3872 DiagnosticPredicate DP(Operand.isMSA128AsmReg());
3873 if (DP.isMatch())
3874 return MCTargetAsmParser::Match_Success;
3875 break;
3876 }
3877 case MCK_MSACtrlAsmReg: {
3878 DiagnosticPredicate DP(Operand.isMSACtrlAsmReg());
3879 if (DP.isMatch())
3880 return MCTargetAsmParser::Match_Success;
3881 break;
3882 }
3883 case MCK_InvNum: {
3884 DiagnosticPredicate DP(Operand.isInvNum());
3885 if (DP.isMatch())
3886 return MCTargetAsmParser::Match_Success;
3887 break;
3888 }
3889 case MCK_JumpTarget: {
3890 DiagnosticPredicate DP(Operand.isImm());
3891 if (DP.isMatch())
3892 return MCTargetAsmParser::Match_Success;
3893 break;
3894 }
3895 case MCK_Mem: {
3896 DiagnosticPredicate DP(Operand.isMemOperand());
3897 if (DP.isMatch())
3898 return MCTargetAsmParser::Match_Success;
3899 break;
3900 }
3901 case MCK_MemBaseGP: {
3902 DiagnosticPredicate DP(Operand.isGPAsmReg());
3903 if (DP.isMatch())
3904 return MCTargetAsmParser::Match_Success;
3905 break;
3906 }
3907 case MCK_MemBaseSP: {
3908 DiagnosticPredicate DP(Operand.isSPAsmReg());
3909 if (DP.isMatch())
3910 return MCTargetAsmParser::Match_Success;
3911 break;
3912 }
3913 case MCK_PtrReg: {
3914 DiagnosticPredicate DP(Operand.isGPRAsmReg());
3915 if (DP.isMatch())
3916 return MCTargetAsmParser::Match_Success;
3917 break;
3918 }
3919 case MCK_RegList16: {
3920 DiagnosticPredicate DP(Operand.isRegList16());
3921 if (DP.isMatch())
3922 return MCTargetAsmParser::Match_Success;
3923 break;
3924 }
3925 case MCK_RegList: {
3926 DiagnosticPredicate DP(Operand.isRegList());
3927 if (DP.isMatch())
3928 return MCTargetAsmParser::Match_Success;
3929 break;
3930 }
3931 case MCK_Simm18_Lsl3: {
3932 DiagnosticPredicate DP(Operand.isScaledSImm<18, 3>());
3933 if (DP.isMatch())
3934 return MCTargetAsmParser::Match_Success;
3935 if (DP.isNearMatch())
3936 return MipsAsmParser::Match_SImm18_Lsl3;
3937 break;
3938 }
3939 case MCK_Simm19_Lsl2: {
3940 DiagnosticPredicate DP(Operand.isScaledSImm<19, 2>());
3941 if (DP.isMatch())
3942 return MCTargetAsmParser::Match_Success;
3943 if (DP.isNearMatch())
3944 return MipsAsmParser::Match_SImm19_Lsl2;
3945 break;
3946 }
3947 case MCK_StrictlyAFGR64AsmReg: {
3948 DiagnosticPredicate DP(Operand.isStrictlyFGRAsmReg());
3949 if (DP.isMatch())
3950 return MCTargetAsmParser::Match_Success;
3951 break;
3952 }
3953 case MCK_StrictlyFGR32AsmReg: {
3954 DiagnosticPredicate DP(Operand.isStrictlyFGRAsmReg());
3955 if (DP.isMatch())
3956 return MCTargetAsmParser::Match_Success;
3957 break;
3958 }
3959 case MCK_StrictlyFGR64AsmReg: {
3960 DiagnosticPredicate DP(Operand.isStrictlyFGRAsmReg());
3961 if (DP.isMatch())
3962 return MCTargetAsmParser::Match_Success;
3963 break;
3964 }
3965 case MCK_ConstantImmz: {
3966 DiagnosticPredicate DP(Operand.isConstantImmz());
3967 if (DP.isMatch())
3968 return MCTargetAsmParser::Match_Success;
3969 if (DP.isNearMatch())
3970 return MipsAsmParser::Match_Immz;
3971 break;
3972 }
3973 case MCK_ConstantUImm1_0: {
3974 DiagnosticPredicate DP(Operand.isConstantUImm<1, 0>());
3975 if (DP.isMatch())
3976 return MCTargetAsmParser::Match_Success;
3977 if (DP.isNearMatch())
3978 return MipsAsmParser::Match_UImm1_0;
3979 break;
3980 }
3981 case MCK_ConstantUImm2_0: {
3982 DiagnosticPredicate DP(Operand.isConstantUImm<2, 0>());
3983 if (DP.isMatch())
3984 return MCTargetAsmParser::Match_Success;
3985 if (DP.isNearMatch())
3986 return MipsAsmParser::Match_UImm2_0;
3987 break;
3988 }
3989 case MCK_ConstantUImm2_1: {
3990 DiagnosticPredicate DP(Operand.isConstantUImm<2, 1>());
3991 if (DP.isMatch())
3992 return MCTargetAsmParser::Match_Success;
3993 if (DP.isNearMatch())
3994 return MipsAsmParser::Match_UImm2_1;
3995 break;
3996 }
3997 case MCK_ConstantUImm3_0: {
3998 DiagnosticPredicate DP(Operand.isConstantUImm<3, 0>());
3999 if (DP.isMatch())
4000 return MCTargetAsmParser::Match_Success;
4001 if (DP.isNearMatch())
4002 return MipsAsmParser::Match_UImm3_0;
4003 break;
4004 }
4005 case MCK_ConstantSImm4_0: {
4006 DiagnosticPredicate DP(Operand.isConstantSImm<4, 0>());
4007 if (DP.isMatch())
4008 return MCTargetAsmParser::Match_Success;
4009 if (DP.isNearMatch())
4010 return MipsAsmParser::Match_SImm4_0;
4011 break;
4012 }
4013 case MCK_ConstantUImm4_0: {
4014 DiagnosticPredicate DP(Operand.isConstantUImm<4, 0>());
4015 if (DP.isMatch())
4016 return MCTargetAsmParser::Match_Success;
4017 if (DP.isNearMatch())
4018 return MipsAsmParser::Match_UImm4_0;
4019 break;
4020 }
4021 case MCK_ConstantSImm5_0: {
4022 DiagnosticPredicate DP(Operand.isConstantSImm<5, 0>());
4023 if (DP.isMatch())
4024 return MCTargetAsmParser::Match_Success;
4025 if (DP.isNearMatch())
4026 return MipsAsmParser::Match_SImm5_0;
4027 break;
4028 }
4029 case MCK_ConstantUImm5_0: {
4030 DiagnosticPredicate DP(Operand.isConstantUImm<5, 0>());
4031 if (DP.isMatch())
4032 return MCTargetAsmParser::Match_Success;
4033 if (DP.isNearMatch())
4034 return MipsAsmParser::Match_UImm5_0;
4035 break;
4036 }
4037 case MCK_ConstantUImm5_1: {
4038 DiagnosticPredicate DP(Operand.isConstantUImm<5, 1>());
4039 if (DP.isMatch())
4040 return MCTargetAsmParser::Match_Success;
4041 if (DP.isNearMatch())
4042 return MipsAsmParser::Match_UImm5_1;
4043 break;
4044 }
4045 case MCK_ConstantUImm5_Plus1_Report_UImm6: {
4046 DiagnosticPredicate DP(Operand.isConstantUImm<5, 1>());
4047 if (DP.isMatch())
4048 return MCTargetAsmParser::Match_Success;
4049 if (DP.isNearMatch())
4050 return MipsAsmParser::Match_UImm5_1;
4051 break;
4052 }
4053 case MCK_ConstantUImm5_32_Norm: {
4054 DiagnosticPredicate DP(Operand.isConstantUImm<5, 32>());
4055 if (DP.isMatch())
4056 return MCTargetAsmParser::Match_Success;
4057 if (DP.isNearMatch())
4058 return MipsAsmParser::Match_UImm5_32;
4059 break;
4060 }
4061 case MCK_ConstantUImm5_32: {
4062 DiagnosticPredicate DP(Operand.isConstantUImm<5, 32>());
4063 if (DP.isMatch())
4064 return MCTargetAsmParser::Match_Success;
4065 if (DP.isNearMatch())
4066 return MipsAsmParser::Match_UImm5_32;
4067 break;
4068 }
4069 case MCK_ConstantUImm5_0_Report_UImm6: {
4070 DiagnosticPredicate DP(Operand.isConstantUImm<5, 0>());
4071 if (DP.isMatch())
4072 return MCTargetAsmParser::Match_Success;
4073 if (DP.isNearMatch())
4074 return MipsAsmParser::Match_UImm5_0_Report_UImm6;
4075 break;
4076 }
4077 case MCK_ConstantUImm5_33: {
4078 DiagnosticPredicate DP(Operand.isConstantUImm<5, 33>());
4079 if (DP.isMatch())
4080 return MCTargetAsmParser::Match_Success;
4081 if (DP.isNearMatch())
4082 return MipsAsmParser::Match_UImm5_33;
4083 break;
4084 }
4085 case MCK_ConstantUImmRange2_64: {
4086 DiagnosticPredicate DP(Operand.isConstantUImmRange<2, 64>());
4087 if (DP.isMatch())
4088 return MCTargetAsmParser::Match_Success;
4089 if (DP.isNearMatch())
4090 return MipsAsmParser::Match_UImmRange2_64;
4091 break;
4092 }
4093 case MCK_UImm5Lsl2: {
4094 DiagnosticPredicate DP(Operand.isScaledUImm<5, 2>());
4095 if (DP.isMatch())
4096 return MCTargetAsmParser::Match_Success;
4097 if (DP.isNearMatch())
4098 return MipsAsmParser::Match_UImm5_Lsl2;
4099 break;
4100 }
4101 case MCK_ConstantSImm6_0: {
4102 DiagnosticPredicate DP(Operand.isConstantSImm<6, 0>());
4103 if (DP.isMatch())
4104 return MCTargetAsmParser::Match_Success;
4105 if (DP.isNearMatch())
4106 return MipsAsmParser::Match_SImm6_0;
4107 break;
4108 }
4109 case MCK_ConstantUImm6_0: {
4110 DiagnosticPredicate DP(Operand.isConstantUImm<6, 0>());
4111 if (DP.isMatch())
4112 return MCTargetAsmParser::Match_Success;
4113 if (DP.isNearMatch())
4114 return MipsAsmParser::Match_UImm6_0;
4115 break;
4116 }
4117 case MCK_UImm6Lsl2: {
4118 DiagnosticPredicate DP(Operand.isScaledUImm<6, 2>());
4119 if (DP.isMatch())
4120 return MCTargetAsmParser::Match_Success;
4121 if (DP.isNearMatch())
4122 return MipsAsmParser::Match_UImm6_Lsl2;
4123 break;
4124 }
4125 case MCK_ConstantUImm7_0: {
4126 DiagnosticPredicate DP(Operand.isConstantUImm<7, 0>());
4127 if (DP.isMatch())
4128 return MCTargetAsmParser::Match_Success;
4129 if (DP.isNearMatch())
4130 return MipsAsmParser::Match_UImm7_0;
4131 break;
4132 }
4133 case MCK_UImm7_N1: {
4134 DiagnosticPredicate DP(Operand.isConstantUImm<7, -1>());
4135 if (DP.isMatch())
4136 return MCTargetAsmParser::Match_Success;
4137 if (DP.isNearMatch())
4138 return MipsAsmParser::Match_UImm7_N1;
4139 break;
4140 }
4141 case MCK_ConstantUImm8_0: {
4142 DiagnosticPredicate DP(Operand.isConstantUImm<8, 0>());
4143 if (DP.isMatch())
4144 return MCTargetAsmParser::Match_Success;
4145 if (DP.isNearMatch())
4146 return MipsAsmParser::Match_UImm8_0;
4147 break;
4148 }
4149 case MCK_SImm7Lsl2: {
4150 DiagnosticPredicate DP(Operand.isScaledSImm<7, 2>());
4151 if (DP.isMatch())
4152 return MCTargetAsmParser::Match_Success;
4153 if (DP.isNearMatch())
4154 return MipsAsmParser::Match_SImm7_Lsl2;
4155 break;
4156 }
4157 case MCK_ConstantSImm9_0: {
4158 DiagnosticPredicate DP(Operand.isConstantSImm<9, 0>());
4159 if (DP.isMatch())
4160 return MCTargetAsmParser::Match_Success;
4161 if (DP.isNearMatch())
4162 return MipsAsmParser::Match_SImm9_0;
4163 break;
4164 }
4165 case MCK_ConstantSImm10_0: {
4166 DiagnosticPredicate DP(Operand.isConstantSImm<10, 0>());
4167 if (DP.isMatch())
4168 return MCTargetAsmParser::Match_Success;
4169 if (DP.isNearMatch())
4170 return MipsAsmParser::Match_SImm10_0;
4171 break;
4172 }
4173 case MCK_ConstantUImm10_0: {
4174 DiagnosticPredicate DP(Operand.isConstantUImm<10, 0>());
4175 if (DP.isMatch())
4176 return MCTargetAsmParser::Match_Success;
4177 if (DP.isNearMatch())
4178 return MipsAsmParser::Match_UImm10_0;
4179 break;
4180 }
4181 case MCK_SImm10Lsl1: {
4182 DiagnosticPredicate DP(Operand.isScaledSImm<10, 1>());
4183 if (DP.isMatch())
4184 return MCTargetAsmParser::Match_Success;
4185 if (DP.isNearMatch())
4186 return MipsAsmParser::Match_SImm10_Lsl1;
4187 break;
4188 }
4189 case MCK_ConstantSImm11_0: {
4190 DiagnosticPredicate DP(Operand.isConstantSImm<11, 0>());
4191 if (DP.isMatch())
4192 return MCTargetAsmParser::Match_Success;
4193 if (DP.isNearMatch())
4194 return MipsAsmParser::Match_SImm11_0;
4195 break;
4196 }
4197 case MCK_SImm10Lsl2: {
4198 DiagnosticPredicate DP(Operand.isScaledSImm<10, 2>());
4199 if (DP.isMatch())
4200 return MCTargetAsmParser::Match_Success;
4201 if (DP.isNearMatch())
4202 return MipsAsmParser::Match_SImm10_Lsl2;
4203 break;
4204 }
4205 case MCK_SImm10Lsl3: {
4206 DiagnosticPredicate DP(Operand.isScaledSImm<10, 3>());
4207 if (DP.isMatch())
4208 return MCTargetAsmParser::Match_Success;
4209 if (DP.isNearMatch())
4210 return MipsAsmParser::Match_SImm10_Lsl3;
4211 break;
4212 }
4213 case MCK_SImm16: {
4214 DiagnosticPredicate DP(Operand.isSImm<16>());
4215 if (DP.isMatch())
4216 return MCTargetAsmParser::Match_Success;
4217 if (DP.isNearMatch())
4218 return MipsAsmParser::Match_SImm16;
4219 break;
4220 }
4221 case MCK_SImm16_Relaxed: {
4222 DiagnosticPredicate DP(Operand.isAnyImm<16>());
4223 if (DP.isMatch())
4224 return MCTargetAsmParser::Match_Success;
4225 if (DP.isNearMatch())
4226 return MipsAsmParser::Match_SImm16_Relaxed;
4227 break;
4228 }
4229 case MCK_UImm16_AltRelaxed: {
4230 DiagnosticPredicate DP(Operand.isUImm<16>());
4231 if (DP.isMatch())
4232 return MCTargetAsmParser::Match_Success;
4233 if (DP.isNearMatch())
4234 return MipsAsmParser::Match_UImm16_AltRelaxed;
4235 break;
4236 }
4237 case MCK_UImm16: {
4238 DiagnosticPredicate DP(Operand.isUImm<16>());
4239 if (DP.isMatch())
4240 return MCTargetAsmParser::Match_Success;
4241 if (DP.isNearMatch())
4242 return MipsAsmParser::Match_UImm16;
4243 break;
4244 }
4245 case MCK_SImm19Lsl2: {
4246 DiagnosticPredicate DP(Operand.isScaledSImm<19, 2>());
4247 if (DP.isMatch())
4248 return MCTargetAsmParser::Match_Success;
4249 if (DP.isNearMatch())
4250 return MipsAsmParser::Match_SImm19_Lsl2;
4251 break;
4252 }
4253 case MCK_UImm16_Relaxed: {
4254 DiagnosticPredicate DP(Operand.isAnyImm<16>());
4255 if (DP.isMatch())
4256 return MCTargetAsmParser::Match_Success;
4257 if (DP.isNearMatch())
4258 return MipsAsmParser::Match_UImm16_Relaxed;
4259 break;
4260 }
4261 case MCK_ConstantUImm20_0: {
4262 DiagnosticPredicate DP(Operand.isConstantUImm<20, 0>());
4263 if (DP.isMatch())
4264 return MCTargetAsmParser::Match_Success;
4265 if (DP.isNearMatch())
4266 return MipsAsmParser::Match_UImm20_0;
4267 break;
4268 }
4269 case MCK_ConstantUImm26_0: {
4270 DiagnosticPredicate DP(Operand.isConstantUImm<26, 0>());
4271 if (DP.isMatch())
4272 return MCTargetAsmParser::Match_Success;
4273 if (DP.isNearMatch())
4274 return MipsAsmParser::Match_UImm26_0;
4275 break;
4276 }
4277 case MCK_SImm32: {
4278 DiagnosticPredicate DP(Operand.isSImm<32>());
4279 if (DP.isMatch())
4280 return MCTargetAsmParser::Match_Success;
4281 if (DP.isNearMatch())
4282 return MipsAsmParser::Match_SImm32;
4283 break;
4284 }
4285 case MCK_SImm32_Relaxed: {
4286 DiagnosticPredicate DP(Operand.isAnyImm<33>());
4287 if (DP.isMatch())
4288 return MCTargetAsmParser::Match_Success;
4289 if (DP.isNearMatch())
4290 return MipsAsmParser::Match_SImm32_Relaxed;
4291 break;
4292 }
4293 case MCK_UImm32_Coerced: {
4294 DiagnosticPredicate DP(Operand.isSImm<33>());
4295 if (DP.isMatch())
4296 return MCTargetAsmParser::Match_Success;
4297 if (DP.isNearMatch())
4298 return MipsAsmParser::Match_UImm32_Coerced;
4299 break;
4300 }
4301 } // end switch (Kind)
4302
4303 Kind = remapRegClassByHwMode(Kind, STI);
4304
4305 if (Operand.isReg()) {
4306 static constexpr uint16_t Table[Mips::NUM_TARGET_REGS] = {
4307 InvalidMatchClass,
4308 MCK_DSPCC,
4309 InvalidMatchClass,
4310 InvalidMatchClass,
4311 InvalidMatchClass,
4312 InvalidMatchClass,
4313 InvalidMatchClass,
4314 MCK_MSACtrl,
4315 MCK_MSACtrl,
4316 MCK_MSACtrl,
4317 MCK_MSACtrl,
4318 MCK_MSACtrl,
4319 MCK_MSACtrl,
4320 MCK_MSACtrl,
4321 MCK_MSACtrl,
4322 MCK_PC,
4323 MCK_ACC64,
4324 MCK_ACC64DSP,
4325 MCK_ACC64DSP,
4326 MCK_ACC64DSP,
4327 MCK_COP0,
4328 MCK_COP0,
4329 MCK_COP0,
4330 MCK_COP0,
4331 MCK_COP0,
4332 MCK_COP0,
4333 MCK_COP0,
4334 MCK_COP0,
4335 MCK_COP0,
4336 MCK_COP0,
4337 MCK_COP2,
4338 MCK_COP2,
4339 MCK_COP2,
4340 MCK_COP2,
4341 MCK_COP2,
4342 MCK_COP2,
4343 MCK_COP2,
4344 MCK_COP2,
4345 MCK_COP2,
4346 MCK_COP2,
4347 MCK_COP3,
4348 MCK_COP3,
4349 MCK_COP3,
4350 MCK_COP3,
4351 MCK_COP3,
4352 MCK_COP3,
4353 MCK_COP3,
4354 MCK_COP3,
4355 MCK_COP3,
4356 MCK_COP3,
4357 MCK_COP0,
4358 MCK_COP0,
4359 MCK_COP0,
4360 MCK_COP0,
4361 MCK_COP0,
4362 MCK_COP0,
4363 MCK_COP0,
4364 MCK_COP0,
4365 MCK_COP0,
4366 MCK_COP0,
4367 MCK_COP0,
4368 MCK_COP0,
4369 MCK_COP0,
4370 MCK_COP0,
4371 MCK_COP0,
4372 MCK_COP0,
4373 MCK_COP0,
4374 MCK_COP0,
4375 MCK_COP0,
4376 MCK_COP0,
4377 MCK_COP0,
4378 MCK_COP0,
4379 MCK_COP2,
4380 MCK_COP2,
4381 MCK_COP2,
4382 MCK_COP2,
4383 MCK_COP2,
4384 MCK_COP2,
4385 MCK_COP2,
4386 MCK_COP2,
4387 MCK_COP2,
4388 MCK_COP2,
4389 MCK_COP2,
4390 MCK_COP2,
4391 MCK_COP2,
4392 MCK_COP2,
4393 MCK_COP2,
4394 MCK_COP2,
4395 MCK_COP2,
4396 MCK_COP2,
4397 MCK_COP2,
4398 MCK_COP2,
4399 MCK_COP2,
4400 MCK_COP2,
4401 MCK_COP3,
4402 MCK_COP3,
4403 MCK_COP3,
4404 MCK_COP3,
4405 MCK_COP3,
4406 MCK_COP3,
4407 MCK_COP3,
4408 MCK_COP3,
4409 MCK_COP3,
4410 MCK_COP3,
4411 MCK_COP3,
4412 MCK_COP3,
4413 MCK_COP3,
4414 MCK_COP3,
4415 MCK_COP3,
4416 MCK_COP3,
4417 MCK_COP3,
4418 MCK_COP3,
4419 MCK_COP3,
4420 MCK_COP3,
4421 MCK_COP3,
4422 MCK_COP3,
4423 MCK_AFGR64,
4424 MCK_AFGR64,
4425 MCK_AFGR64,
4426 MCK_AFGR64,
4427 MCK_AFGR64,
4428 MCK_AFGR64,
4429 MCK_AFGR64,
4430 MCK_AFGR64,
4431 MCK_AFGR64,
4432 MCK_AFGR64,
4433 MCK_AFGR64,
4434 MCK_AFGR64,
4435 MCK_AFGR64,
4436 MCK_AFGR64,
4437 MCK_AFGR64,
4438 MCK_AFGR64,
4439 InvalidMatchClass,
4440 InvalidMatchClass,
4441 InvalidMatchClass,
4442 InvalidMatchClass,
4443 MCK_FGR32,
4444 MCK_FGR32,
4445 MCK_FGR32,
4446 MCK_FGR32,
4447 MCK_FGR32,
4448 MCK_FGR32,
4449 MCK_FGR32,
4450 MCK_FGR32,
4451 MCK_FGR32,
4452 MCK_FGR32,
4453 MCK_FGR32,
4454 MCK_FGR32,
4455 MCK_FGR32,
4456 MCK_FGR32,
4457 MCK_FGR32,
4458 MCK_FGR32,
4459 MCK_FGR32,
4460 MCK_FGR32,
4461 MCK_FGR32,
4462 MCK_FGR32,
4463 MCK_FGR32,
4464 MCK_FGR32,
4465 MCK_FGR32,
4466 MCK_FGR32,
4467 MCK_FGR32,
4468 MCK_FGR32,
4469 MCK_FGR32,
4470 MCK_FGR32,
4471 MCK_FGR32,
4472 MCK_FGR32,
4473 MCK_FGR32,
4474 MCK_FGR32,
4475 MCK_FCC,
4476 MCK_FCC,
4477 MCK_FCC,
4478 MCK_FCC,
4479 MCK_FCC,
4480 MCK_FCC,
4481 MCK_FCC,
4482 MCK_FCC,
4483 MCK_CCR,
4484 MCK_CCR,
4485 MCK_CCR,
4486 MCK_CCR,
4487 MCK_CCR,
4488 MCK_CCR,
4489 MCK_CCR,
4490 MCK_CCR,
4491 MCK_CCR,
4492 MCK_CCR,
4493 MCK_CCR,
4494 MCK_CCR,
4495 MCK_CCR,
4496 MCK_CCR,
4497 MCK_CCR,
4498 MCK_CCR,
4499 MCK_CCR,
4500 MCK_CCR,
4501 MCK_CCR,
4502 MCK_CCR,
4503 MCK_CCR,
4504 MCK_CCR,
4505 MCK_CCR,
4506 MCK_CCR,
4507 MCK_CCR,
4508 MCK_CCR,
4509 MCK_CCR,
4510 MCK_CCR,
4511 MCK_CCR,
4512 MCK_CCR,
4513 MCK_CCR,
4514 MCK_CCR,
4515 InvalidMatchClass,
4516 InvalidMatchClass,
4517 InvalidMatchClass,
4518 InvalidMatchClass,
4519 InvalidMatchClass,
4520 InvalidMatchClass,
4521 InvalidMatchClass,
4522 InvalidMatchClass,
4523 InvalidMatchClass,
4524 InvalidMatchClass,
4525 InvalidMatchClass,
4526 InvalidMatchClass,
4527 InvalidMatchClass,
4528 InvalidMatchClass,
4529 InvalidMatchClass,
4530 InvalidMatchClass,
4531 InvalidMatchClass,
4532 InvalidMatchClass,
4533 InvalidMatchClass,
4534 InvalidMatchClass,
4535 InvalidMatchClass,
4536 InvalidMatchClass,
4537 InvalidMatchClass,
4538 InvalidMatchClass,
4539 InvalidMatchClass,
4540 InvalidMatchClass,
4541 InvalidMatchClass,
4542 InvalidMatchClass,
4543 InvalidMatchClass,
4544 InvalidMatchClass,
4545 InvalidMatchClass,
4546 InvalidMatchClass,
4547 MCK_HI32,
4548 MCK_HI32DSP,
4549 MCK_HI32DSP,
4550 MCK_HI32DSP,
4551 MCK_HWRegs,
4552 MCK_HWRegs,
4553 MCK_HWRegs,
4554 MCK_HWRegs,
4555 MCK_HWRegs,
4556 MCK_HWRegs,
4557 MCK_HWRegs,
4558 MCK_HWRegs,
4559 MCK_HWRegs,
4560 MCK_HWRegs,
4561 MCK_HWRegs,
4562 MCK_HWRegs,
4563 MCK_HWRegs,
4564 MCK_HWRegs,
4565 MCK_HWRegs,
4566 MCK_HWRegs,
4567 MCK_HWRegs,
4568 MCK_HWRegs,
4569 MCK_HWRegs,
4570 MCK_HWRegs,
4571 MCK_HWRegs,
4572 MCK_HWRegs,
4573 MCK_HWRegs,
4574 MCK_HWRegs,
4575 MCK_HWRegs,
4576 MCK_HWRegs,
4577 MCK_HWRegs,
4578 MCK_HWRegs,
4579 MCK_HWRegs,
4580 MCK_HWRegs,
4581 MCK_HWRegs,
4582 MCK_HWRegs,
4583 MCK_LO32,
4584 MCK_LO32DSP,
4585 MCK_LO32DSP,
4586 MCK_LO32DSP,
4587 MCK_OCTEON_MPL,
4588 MCK_OCTEON_MPL,
4589 MCK_OCTEON_MPL,
4590 MCK_MSACtrl,
4591 MCK_MSACtrl,
4592 MCK_MSACtrl,
4593 MCK_MSACtrl,
4594 MCK_MSACtrl,
4595 MCK_MSACtrl,
4596 MCK_MSACtrl,
4597 MCK_MSACtrl,
4598 MCK_MSACtrl,
4599 MCK_MSACtrl,
4600 MCK_MSACtrl,
4601 MCK_MSACtrl,
4602 MCK_MSACtrl,
4603 MCK_MSACtrl,
4604 MCK_MSACtrl,
4605 MCK_MSACtrl,
4606 MCK_MSACtrl,
4607 MCK_MSACtrl,
4608 MCK_MSACtrl,
4609 MCK_MSACtrl,
4610 MCK_MSACtrl,
4611 MCK_MSACtrl,
4612 MCK_MSACtrl,
4613 MCK_MSACtrl,
4614 MCK_OCTEON_P,
4615 MCK_OCTEON_P,
4616 MCK_OCTEON_P,
4617 MCK_GPR32ZERO,
4618 MCK_GPR32NONZERO,
4619 MCK_Reg11,
4620 MCK_Reg11,
4621 MCK_GPRMM16MovePPairFirst,
4622 MCK_Reg13,
4623 MCK_Reg13,
4624 MCK_Reg14,
4625 MCK_GPR32NONZERO,
4626 MCK_GPR32NONZERO,
4627 MCK_GPR32NONZERO,
4628 MCK_GPR32NONZERO,
4629 MCK_GPR32NONZERO,
4630 MCK_GPR32NONZERO,
4631 MCK_GPR32NONZERO,
4632 MCK_GPR32NONZERO,
4633 MCK_Reg9,
4634 MCK_Reg11,
4635 MCK_Reg10,
4636 MCK_Reg10,
4637 MCK_Reg10,
4638 MCK_GPRMM16MovePPairSecond,
4639 MCK_GPRMM16MovePPairSecond,
4640 MCK_GPR32NONZERO,
4641 MCK_GPR32NONZERO,
4642 MCK_GPR32NONZERO,
4643 MCK_GPR32NONZERO,
4644 MCK_GPR32NONZERO,
4645 MCK_GP32,
4646 MCK_CPUSPReg,
4647 MCK_GPR32NONZERO,
4648 MCK_CPURAReg,
4649 MCK_MSA128WEvens,
4650 MCK_MSA128B,
4651 MCK_MSA128WEvens,
4652 MCK_MSA128B,
4653 MCK_MSA128WEvens,
4654 MCK_MSA128B,
4655 MCK_MSA128WEvens,
4656 MCK_MSA128B,
4657 MCK_MSA128WEvens,
4658 MCK_MSA128B,
4659 MCK_MSA128WEvens,
4660 MCK_MSA128B,
4661 MCK_MSA128WEvens,
4662 MCK_MSA128B,
4663 MCK_MSA128WEvens,
4664 MCK_MSA128B,
4665 MCK_MSA128WEvens,
4666 MCK_MSA128B,
4667 MCK_MSA128WEvens,
4668 MCK_MSA128B,
4669 MCK_MSA128WEvens,
4670 MCK_MSA128B,
4671 MCK_MSA128WEvens,
4672 MCK_MSA128B,
4673 MCK_MSA128WEvens,
4674 MCK_MSA128B,
4675 MCK_MSA128WEvens,
4676 MCK_MSA128B,
4677 MCK_MSA128WEvens,
4678 MCK_MSA128B,
4679 MCK_MSA128WEvens,
4680 MCK_MSA128B,
4681 MCK_ACC128,
4682 MCK_FGR64,
4683 MCK_FGR64,
4684 MCK_FGR64,
4685 MCK_FGR64,
4686 MCK_FGR64,
4687 MCK_FGR64,
4688 MCK_FGR64,
4689 MCK_FGR64,
4690 MCK_FGR64,
4691 MCK_FGR64,
4692 MCK_FGR64,
4693 MCK_FGR64,
4694 MCK_FGR64,
4695 MCK_FGR64,
4696 MCK_FGR64,
4697 MCK_FGR64,
4698 MCK_FGR64,
4699 MCK_FGR64,
4700 MCK_FGR64,
4701 MCK_FGR64,
4702 MCK_FGR64,
4703 MCK_FGR64,
4704 MCK_FGR64,
4705 MCK_FGR64,
4706 MCK_FGR64,
4707 MCK_FGR64,
4708 MCK_FGR64,
4709 MCK_FGR64,
4710 MCK_FGR64,
4711 MCK_FGR64,
4712 MCK_FGR64,
4713 MCK_FGR64,
4714 InvalidMatchClass,
4715 MCK_HI64,
4716 MCK_LO64,
4717 MCK_Reg19,
4718 MCK_Reg24,
4719 MCK_Reg30,
4720 MCK_Reg30,
4721 MCK_Reg31,
4722 MCK_Reg32,
4723 MCK_Reg32,
4724 MCK_Reg33,
4725 MCK_Reg24,
4726 MCK_Reg24,
4727 MCK_Reg24,
4728 MCK_Reg24,
4729 MCK_Reg24,
4730 MCK_Reg24,
4731 MCK_Reg24,
4732 MCK_Reg24,
4733 MCK_Reg28,
4734 MCK_Reg30,
4735 MCK_Reg29,
4736 MCK_Reg29,
4737 MCK_Reg29,
4738 MCK_Reg34,
4739 MCK_Reg34,
4740 MCK_Reg24,
4741 MCK_Reg24,
4742 MCK_Reg24,
4743 MCK_Reg24,
4744 MCK_Reg24,
4745 MCK_GP64,
4746 MCK_SP64,
4747 MCK_Reg24,
4748 MCK_Reg37,
4749 };
4750
4751 MCRegister Reg = Operand.getReg();
4752 MatchClassKind OpKind = Reg.isPhysical() ? (MatchClassKind)Table[Reg.id()] : InvalidMatchClass;
4753 return isSubclass(OpKind, Kind) ? (unsigned)MCTargetAsmParser::Match_Success :
4754 getDiagKindFromRegisterClass(Kind);
4755 }
4756
4757 if (Kind > MCK_LAST_TOKEN && Kind <= MCK_LAST_REGISTER)
4758 return getDiagKindFromRegisterClass(Kind);
4759
4760 return MCTargetAsmParser::Match_InvalidOperand;
4761}
4762
4763#ifndef NDEBUG
4764const char *getMatchClassName(MatchClassKind Kind) {
4765 switch (Kind) {
4766 case InvalidMatchClass: return "InvalidMatchClass";
4767 case OptionalMatchClass: return "OptionalMatchClass";
4768 case MCK__HASH_: return "MCK__HASH_";
4769 case MCK__40_: return "MCK__40_";
4770 case MCK__41_: return "MCK__41_";
4771 case MCK_0: return "MCK_0";
4772 case MCK_16: return "MCK_16";
4773 case MCK__91_: return "MCK__91_";
4774 case MCK__93_: return "MCK__93_";
4775 case MCK_bit: return "MCK_bit";
4776 case MCK_inst: return "MCK_inst";
4777 case MCK_Reg37: return "MCK_Reg37";
4778 case MCK_Reg19: return "MCK_Reg19";
4779 case MCK_ACC128: return "MCK_ACC128";
4780 case MCK_ACC64: return "MCK_ACC64";
4781 case MCK_CPURAReg: return "MCK_CPURAReg";
4782 case MCK_CPUSPReg: return "MCK_CPUSPReg";
4783 case MCK_DSPCC: return "MCK_DSPCC";
4784 case MCK_GP32: return "MCK_GP32";
4785 case MCK_GP64: return "MCK_GP64";
4786 case MCK_GPR32ZERO: return "MCK_GPR32ZERO";
4787 case MCK_HI32: return "MCK_HI32";
4788 case MCK_HI64: return "MCK_HI64";
4789 case MCK_LO32: return "MCK_LO32";
4790 case MCK_LO64: return "MCK_LO64";
4791 case MCK_PC: return "MCK_PC";
4792 case MCK_SP64: return "MCK_SP64";
4793 case MCK_Reg32: return "MCK_Reg32";
4794 case MCK_Reg13: return "MCK_Reg13";
4795 case MCK_Reg33: return "MCK_Reg33";
4796 case MCK_Reg31: return "MCK_Reg31";
4797 case MCK_Reg30: return "MCK_Reg30";
4798 case MCK_Reg14: return "MCK_Reg14";
4799 case MCK_Reg11: return "MCK_Reg11";
4800 case MCK_GPRMM16MovePPairFirst: return "MCK_GPRMM16MovePPairFirst";
4801 case MCK_OCTEON_MPL: return "MCK_OCTEON_MPL";
4802 case MCK_OCTEON_P: return "MCK_OCTEON_P";
4803 case MCK_Reg28: return "MCK_Reg28";
4804 case MCK_Reg23: return "MCK_Reg23";
4805 case MCK_Reg9: return "MCK_Reg9";
4806 case MCK_Reg4: return "MCK_Reg4";
4807 case MCK_ACC64DSP: return "MCK_ACC64DSP";
4808 case MCK_HI32DSP: return "MCK_HI32DSP";
4809 case MCK_LO32DSP: return "MCK_LO32DSP";
4810 case MCK_Reg34: return "MCK_Reg34";
4811 case MCK_GPRMM16MovePPairSecond: return "MCK_GPRMM16MovePPairSecond";
4812 case MCK_Reg29: return "MCK_Reg29";
4813 case MCK_Reg27: return "MCK_Reg27";
4814 case MCK_Reg10: return "MCK_Reg10";
4815 case MCK_Reg8: return "MCK_Reg8";
4816 case MCK_Reg25: return "MCK_Reg25";
4817 case MCK_Reg22: return "MCK_Reg22";
4818 case MCK_Reg21: return "MCK_Reg21";
4819 case MCK_CPU16Regs: return "MCK_CPU16Regs";
4820 case MCK_FCC: return "MCK_FCC";
4821 case MCK_GPRMM16MoveP: return "MCK_GPRMM16MoveP";
4822 case MCK_GPRMM16Zero: return "MCK_GPRMM16Zero";
4823 case MCK_Reg26: return "MCK_Reg26";
4824 case MCK_CPU16RegsPlusSP: return "MCK_CPU16RegsPlusSP";
4825 case MCK_AFGR64: return "MCK_AFGR64";
4826 case MCK_MSA128WEvens: return "MCK_MSA128WEvens";
4827 case MCK_Reg24: return "MCK_Reg24";
4828 case MCK_GPR32NONZERO: return "MCK_GPR32NONZERO";
4829 case MCK_CCR: return "MCK_CCR";
4830 case MCK_COP0: return "MCK_COP0";
4831 case MCK_COP2: return "MCK_COP2";
4832 case MCK_COP3: return "MCK_COP3";
4833 case MCK_DSPR: return "MCK_DSPR";
4834 case MCK_FGR32: return "MCK_FGR32";
4835 case MCK_FGR64: return "MCK_FGR64";
4836 case MCK_GPR64: return "MCK_GPR64";
4837 case MCK_HWRegs: return "MCK_HWRegs";
4838 case MCK_MSA128B: return "MCK_MSA128B";
4839 case MCK_MSACtrl: return "MCK_MSACtrl";
4840 case MCK_RegByHwMode_mips_ptr_rc: return "MCK_RegByHwMode_mips_ptr_rc";
4841 case MCK_RegByHwMode_ptr_gp_rc: return "MCK_RegByHwMode_ptr_gp_rc";
4842 case MCK_RegByHwMode_ptr_gpr16mm_rc: return "MCK_RegByHwMode_ptr_gpr16mm_rc";
4843 case MCK_RegByHwMode_ptr_sp_rc: return "MCK_RegByHwMode_ptr_sp_rc";
4844 case MCK_ACC64DSPAsmReg: return "MCK_ACC64DSPAsmReg";
4845 case MCK_AFGR64AsmReg: return "MCK_AFGR64AsmReg";
4846 case MCK_SImmOffset9_0: return "MCK_SImmOffset9_0";
4847 case MCK_SImmOffset10_0: return "MCK_SImmOffset10_0";
4848 case MCK_SImmOffset11_0: return "MCK_SImmOffset11_0";
4849 case MCK_SImmOffset12_0: return "MCK_SImmOffset12_0";
4850 case MCK_SImmOffset16_0: return "MCK_SImmOffset16_0";
4851 case MCK_SImmOffset10_1: return "MCK_SImmOffset10_1";
4852 case MCK_SImmOffset10_2: return "MCK_SImmOffset10_2";
4853 case MCK_SImmOffset10_3: return "MCK_SImmOffset10_3";
4854 case MCK_UImmOffset4_00: return "MCK_UImmOffset4_00";
4855 case MCK_UImmOffset4_10: return "MCK_UImmOffset4_10";
4856 case MCK_UImmOffset4_20: return "MCK_UImmOffset4_20";
4857 case MCK_UImmOffset4_0Minus1: return "MCK_UImmOffset4_0Minus1";
4858 case MCK_UImmOffset5_20: return "MCK_UImmOffset5_20";
4859 case MCK_SImmOffset7_2: return "MCK_SImmOffset7_2";
4860 case MCK_UImmOffset6_00: return "MCK_UImmOffset6_00";
4861 case MCK_SImmPtr: return "MCK_SImmPtr";
4862 case MCK_AnyOffset: return "MCK_AnyOffset";
4863 case MCK_CCRAsmReg: return "MCK_CCRAsmReg";
4864 case MCK_COP0AsmReg: return "MCK_COP0AsmReg";
4865 case MCK_COP2AsmReg: return "MCK_COP2AsmReg";
4866 case MCK_COP3AsmReg: return "MCK_COP3AsmReg";
4867 case MCK_ConstantImm: return "MCK_ConstantImm";
4868 case MCK_FCCAsmReg: return "MCK_FCCAsmReg";
4869 case MCK_FGR32AsmReg: return "MCK_FGR32AsmReg";
4870 case MCK_FGR64AsmReg: return "MCK_FGR64AsmReg";
4871 case MCK_GPR32AsmReg: return "MCK_GPR32AsmReg";
4872 case MCK_GPR32NonZeroAsmReg: return "MCK_GPR32NonZeroAsmReg";
4873 case MCK_GPR32ZeroAsmReg: return "MCK_GPR32ZeroAsmReg";
4874 case MCK_GPR64AsmReg: return "MCK_GPR64AsmReg";
4875 case MCK_GPRMM16AsmReg: return "MCK_GPRMM16AsmReg";
4876 case MCK_GPRMM16AsmRegMoveP: return "MCK_GPRMM16AsmRegMoveP";
4877 case MCK_GPRMM16AsmRegMovePPairFirst: return "MCK_GPRMM16AsmRegMovePPairFirst";
4878 case MCK_GPRMM16AsmRegMovePPairSecond: return "MCK_GPRMM16AsmRegMovePPairSecond";
4879 case MCK_GPRMM16AsmRegZero: return "MCK_GPRMM16AsmRegZero";
4880 case MCK_HI32DSPAsmReg: return "MCK_HI32DSPAsmReg";
4881 case MCK_HWRegsAsmReg: return "MCK_HWRegsAsmReg";
4882 case MCK_Imm: return "MCK_Imm";
4883 case MCK_LO32DSPAsmReg: return "MCK_LO32DSPAsmReg";
4884 case MCK_MSA128AsmReg: return "MCK_MSA128AsmReg";
4885 case MCK_MSACtrlAsmReg: return "MCK_MSACtrlAsmReg";
4886 case MCK_InvNum: return "MCK_InvNum";
4887 case MCK_JumpTarget: return "MCK_JumpTarget";
4888 case MCK_Mem: return "MCK_Mem";
4889 case MCK_MemBaseGP: return "MCK_MemBaseGP";
4890 case MCK_MemBaseSP: return "MCK_MemBaseSP";
4891 case MCK_PtrReg: return "MCK_PtrReg";
4892 case MCK_RegList16: return "MCK_RegList16";
4893 case MCK_RegList: return "MCK_RegList";
4894 case MCK_Simm18_Lsl3: return "MCK_Simm18_Lsl3";
4895 case MCK_Simm19_Lsl2: return "MCK_Simm19_Lsl2";
4896 case MCK_StrictlyAFGR64AsmReg: return "MCK_StrictlyAFGR64AsmReg";
4897 case MCK_StrictlyFGR32AsmReg: return "MCK_StrictlyFGR32AsmReg";
4898 case MCK_StrictlyFGR64AsmReg: return "MCK_StrictlyFGR64AsmReg";
4899 case MCK_ConstantImmz: return "MCK_ConstantImmz";
4900 case MCK_ConstantUImm1_0: return "MCK_ConstantUImm1_0";
4901 case MCK_ConstantUImm2_0: return "MCK_ConstantUImm2_0";
4902 case MCK_ConstantUImm2_1: return "MCK_ConstantUImm2_1";
4903 case MCK_ConstantUImm3_0: return "MCK_ConstantUImm3_0";
4904 case MCK_ConstantSImm4_0: return "MCK_ConstantSImm4_0";
4905 case MCK_ConstantUImm4_0: return "MCK_ConstantUImm4_0";
4906 case MCK_ConstantSImm5_0: return "MCK_ConstantSImm5_0";
4907 case MCK_ConstantUImm5_0: return "MCK_ConstantUImm5_0";
4908 case MCK_ConstantUImm5_1: return "MCK_ConstantUImm5_1";
4909 case MCK_ConstantUImm5_Plus1_Report_UImm6: return "MCK_ConstantUImm5_Plus1_Report_UImm6";
4910 case MCK_ConstantUImm5_32_Norm: return "MCK_ConstantUImm5_32_Norm";
4911 case MCK_ConstantUImm5_32: return "MCK_ConstantUImm5_32";
4912 case MCK_ConstantUImm5_0_Report_UImm6: return "MCK_ConstantUImm5_0_Report_UImm6";
4913 case MCK_ConstantUImm5_33: return "MCK_ConstantUImm5_33";
4914 case MCK_ConstantUImmRange2_64: return "MCK_ConstantUImmRange2_64";
4915 case MCK_UImm5Lsl2: return "MCK_UImm5Lsl2";
4916 case MCK_ConstantSImm6_0: return "MCK_ConstantSImm6_0";
4917 case MCK_ConstantUImm6_0: return "MCK_ConstantUImm6_0";
4918 case MCK_UImm6Lsl2: return "MCK_UImm6Lsl2";
4919 case MCK_ConstantUImm7_0: return "MCK_ConstantUImm7_0";
4920 case MCK_UImm7_N1: return "MCK_UImm7_N1";
4921 case MCK_ConstantUImm8_0: return "MCK_ConstantUImm8_0";
4922 case MCK_SImm7Lsl2: return "MCK_SImm7Lsl2";
4923 case MCK_ConstantSImm9_0: return "MCK_ConstantSImm9_0";
4924 case MCK_ConstantSImm10_0: return "MCK_ConstantSImm10_0";
4925 case MCK_ConstantUImm10_0: return "MCK_ConstantUImm10_0";
4926 case MCK_SImm10Lsl1: return "MCK_SImm10Lsl1";
4927 case MCK_ConstantSImm11_0: return "MCK_ConstantSImm11_0";
4928 case MCK_SImm10Lsl2: return "MCK_SImm10Lsl2";
4929 case MCK_SImm10Lsl3: return "MCK_SImm10Lsl3";
4930 case MCK_SImm16: return "MCK_SImm16";
4931 case MCK_SImm16_Relaxed: return "MCK_SImm16_Relaxed";
4932 case MCK_UImm16_AltRelaxed: return "MCK_UImm16_AltRelaxed";
4933 case MCK_UImm16: return "MCK_UImm16";
4934 case MCK_SImm19Lsl2: return "MCK_SImm19Lsl2";
4935 case MCK_UImm16_Relaxed: return "MCK_UImm16_Relaxed";
4936 case MCK_ConstantUImm20_0: return "MCK_ConstantUImm20_0";
4937 case MCK_ConstantUImm26_0: return "MCK_ConstantUImm26_0";
4938 case MCK_SImm32: return "MCK_SImm32";
4939 case MCK_SImm32_Relaxed: return "MCK_SImm32_Relaxed";
4940 case MCK_UImm32_Coerced: return "MCK_UImm32_Coerced";
4941 case NumMatchClassKinds: return "NumMatchClassKinds";
4942 }
4943 llvm_unreachable("unhandled MatchClassKind!");
4944}
4945
4946#endif // NDEBUG
4947FeatureBitset MipsAsmParser::
4948ComputeAvailableFeatures(const FeatureBitset &FB) const {
4949 FeatureBitset Features;
4950 if (FB[Mips::FeaturePTR64Bit])
4951 Features.set(Feature_IsPTR64bitBit);
4952 if (!(FB[Mips::FeaturePTR64Bit]))
4953 Features.set(Feature_IsPTR32bitBit);
4954 if (FB[Mips::FeatureUseCompactBranches])
4955 Features.set(Feature_UseCompactBranchesBit);
4956 if (FB[Mips::FeatureMips2])
4957 Features.set(Feature_HasMips2Bit);
4958 if (FB[Mips::FeatureMips3_32])
4959 Features.set(Feature_HasMips3_32Bit);
4960 if (FB[Mips::FeatureMips3_32r2])
4961 Features.set(Feature_HasMips3_32r2Bit);
4962 if (FB[Mips::FeatureMips3])
4963 Features.set(Feature_HasMips3Bit);
4964 if (!(FB[Mips::FeatureMips3]))
4965 Features.set(Feature_NotMips3Bit);
4966 if (FB[Mips::FeatureMips4_32])
4967 Features.set(Feature_HasMips4_32Bit);
4968 if (!(FB[Mips::FeatureMips4_32]))
4969 Features.set(Feature_NotMips4_32Bit);
4970 if (FB[Mips::FeatureMips4_32r2])
4971 Features.set(Feature_HasMips4_32r2Bit);
4972 if (FB[Mips::FeatureMips5_32r2])
4973 Features.set(Feature_HasMips5_32r2Bit);
4974 if (FB[Mips::FeatureMips32])
4975 Features.set(Feature_HasMips32Bit);
4976 if (FB[Mips::FeatureMips32r2])
4977 Features.set(Feature_HasMips32r2Bit);
4978 if (FB[Mips::FeatureMips32r5])
4979 Features.set(Feature_HasMips32r5Bit);
4980 if (FB[Mips::FeatureMips32r6])
4981 Features.set(Feature_HasMips32r6Bit);
4982 if (!(FB[Mips::FeatureMips32r6]))
4983 Features.set(Feature_NotMips32r6Bit);
4984 if (FB[Mips::FeatureGP64Bit])
4985 Features.set(Feature_IsGP64bitBit);
4986 if (!(FB[Mips::FeatureGP64Bit]))
4987 Features.set(Feature_IsGP32bitBit);
4988 if (FB[Mips::FeatureMips64])
4989 Features.set(Feature_HasMips64Bit);
4990 if (!(FB[Mips::FeatureMips64]))
4991 Features.set(Feature_NotMips64Bit);
4992 if (FB[Mips::FeatureMips64r2])
4993 Features.set(Feature_HasMips64r2Bit);
4994 if (FB[Mips::FeatureMips64r5])
4995 Features.set(Feature_HasMips64r5Bit);
4996 if (FB[Mips::FeatureMips64r6])
4997 Features.set(Feature_HasMips64r6Bit);
4998 if (!(FB[Mips::FeatureMips64r6]))
4999 Features.set(Feature_NotMips64r6Bit);
5000 if (FB[Mips::FeatureMips16])
5001 Features.set(Feature_InMips16ModeBit);
5002 if (!(FB[Mips::FeatureMips16]))
5003 Features.set(Feature_NotInMips16ModeBit);
5004 if (FB[Mips::FeatureCnMips])
5005 Features.set(Feature_HasCnMipsBit);
5006 if (!(FB[Mips::FeatureCnMips]))
5007 Features.set(Feature_NotCnMipsBit);
5008 if (FB[Mips::FeatureCnMipsP])
5009 Features.set(Feature_HasCnMipsPBit);
5010 if (!(FB[Mips::FeatureCnMipsP]))
5011 Features.set(Feature_NotCnMipsPBit);
5012 if (FB[Mips::FeatureSym32])
5013 Features.set(Feature_IsSym32Bit);
5014 if (!(FB[Mips::FeatureSym32]))
5015 Features.set(Feature_IsSym64Bit);
5016 if (!(FB[Mips::FeatureMips16]))
5017 Features.set(Feature_HasStdEncBit);
5018 if (FB[Mips::FeatureMicroMips])
5019 Features.set(Feature_InMicroMipsBit);
5020 if (!(FB[Mips::FeatureMicroMips]))
5021 Features.set(Feature_NotInMicroMipsBit);
5022 if (FB[Mips::FeatureEVA])
5023 Features.set(Feature_HasEVABit);
5024 if (FB[Mips::FeatureMSA])
5025 Features.set(Feature_HasMSABit);
5026 if (!(FB[Mips::FeatureNoMadd4]))
5027 Features.set(Feature_HasMadd4Bit);
5028 if (FB[Mips::FeatureMT])
5029 Features.set(Feature_HasMTBit);
5030 if (FB[Mips::FeatureUseIndirectJumpsHazard])
5031 Features.set(Feature_UseIndirectJumpsHazardBit);
5032 if (!(FB[Mips::FeatureUseIndirectJumpsHazard]))
5033 Features.set(Feature_NoIndirectJumpGuardsBit);
5034 if (FB[Mips::FeatureR5900])
5035 Features.set(Feature_IsR5900Bit);
5036 if (!(FB[Mips::FeatureR5900]))
5037 Features.set(Feature_NotR5900Bit);
5038 if (FB[Mips::FeatureCRC])
5039 Features.set(Feature_HasCRCBit);
5040 if (FB[Mips::FeatureVirt])
5041 Features.set(Feature_HasVirtBit);
5042 if (FB[Mips::FeatureGINV])
5043 Features.set(Feature_HasGINVBit);
5044 if (FB[Mips::FeatureFP64Bit])
5045 Features.set(Feature_IsFP64bitBit);
5046 if (!(FB[Mips::FeatureFP64Bit]))
5047 Features.set(Feature_NotFP64bitBit);
5048 if (FB[Mips::FeatureSingleFloat])
5049 Features.set(Feature_IsSingleFloatBit);
5050 if (!(FB[Mips::FeatureSingleFloat]))
5051 Features.set(Feature_IsNotSingleFloatBit);
5052 if (!(FB[Mips::FeatureSoftFloat]))
5053 Features.set(Feature_IsNotSoftFloatBit);
5054 if (FB[Mips::FeatureMips3D])
5055 Features.set(Feature_HasMips3DBit);
5056 if (FB[Mips::FeatureDSP])
5057 Features.set(Feature_HasDSPBit);
5058 if (FB[Mips::FeatureDSPR2])
5059 Features.set(Feature_HasDSPR2Bit);
5060 if (FB[Mips::FeatureDSPR3])
5061 Features.set(Feature_HasDSPR3Bit);
5062 return Features;
5063}
5064
5065static bool checkAsmTiedOperandConstraints(const MipsAsmParser&AsmParser,
5066 unsigned Kind, const OperandVector &Operands,
5067 uint64_t &ErrorInfo) {
5068 assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!");
5069 const uint8_t *Converter = ConversionTable[Kind];
5070 for (const uint8_t *p = Converter; *p; p += 2) {
5071 switch (*p) {
5072 case CVT_Tied: {
5073 unsigned OpIdx = *(p + 1);
5074 assert(OpIdx < (size_t)(std::end(TiedAsmOperandTable) -
5075 std::begin(TiedAsmOperandTable)) &&
5076 "Tied operand not found");
5077 unsigned OpndNum1 = TiedAsmOperandTable[OpIdx][1];
5078 unsigned OpndNum2 = TiedAsmOperandTable[OpIdx][2];
5079 if (OpndNum1 != OpndNum2) {
5080 auto &SrcOp1 = Operands[OpndNum1];
5081 auto &SrcOp2 = Operands[OpndNum2];
5082 if (!AsmParser.areEqualRegs(*SrcOp1, *SrcOp2)) {
5083 ErrorInfo = OpndNum2;
5084 return false;
5085 }
5086 }
5087 break;
5088 }
5089 default:
5090 break;
5091 }
5092 }
5093 return true;
5094}
5095
5096static const char MnemonicTable[] =
5097 "\003abs\005abs.d\005abs.s\tabsq_s.ph\tabsq_s.qb\010absq_s.w\003add\005a"
5098 "dd.d\006add.ps\005add.s\007add_a.b\007add_a.d\007add_a.h\007add_a.w\004"
5099 "addi\005addiu\007addiupc\taddiur1sp\007addiur2\007addius5\007addiusp\007"
5100 "addq.ph\taddq_s.ph\010addq_s.w\010addqh.ph\007addqh.w\naddqh_r.ph\taddq"
5101 "h_r.w\007addr.ps\010adds_a.b\010adds_a.d\010adds_a.h\010adds_a.w\010add"
5102 "s_s.b\010adds_s.d\010adds_s.h\010adds_s.w\010adds_u.b\010adds_u.d\010ad"
5103 "ds_u.h\010adds_u.w\005addsc\004addu\007addu.ph\007addu.qb\006addu16\tad"
5104 "du_s.ph\taddu_s.qb\010adduh.qb\nadduh_r.qb\006addv.b\006addv.d\006addv."
5105 "h\006addv.w\007addvi.b\007addvi.d\007addvi.h\007addvi.w\005addwc\005ali"
5106 "gn\006aluipc\003and\005and.v\005and16\004andi\006andi.b\006andi16\006ap"
5107 "pend\010asub_s.b\010asub_s.d\010asub_s.h\010asub_s.w\010asub_u.b\010asu"
5108 "b_u.d\010asub_u.h\010asub_u.w\003aui\005auipc\007ave_s.b\007ave_s.d\007"
5109 "ave_s.h\007ave_s.w\007ave_u.b\007ave_u.d\007ave_u.h\007ave_u.w\010aver_"
5110 "s.b\010aver_s.d\010aver_s.h\010aver_s.w\010aver_u.b\010aver_u.d\010aver"
5111 "_u.h\010aver_u.w\001b\003b16\005baddu\003bal\004balc\006balign\005bbit0"
5112 "\007bbit032\005bbit1\007bbit132\002bc\004bc16\006bc1eqz\007bc1eqzc\004b"
5113 "c1f\005bc1fl\006bc1nez\007bc1nezc\004bc1t\005bc1tl\006bc2eqz\007bc2eqzc"
5114 "\006bc2nez\007bc2nezc\006bclr.b\006bclr.d\006bclr.h\006bclr.w\007bclri."
5115 "b\007bclri.d\007bclri.h\007bclri.w\003beq\004beqc\004beql\004beqz\006be"
5116 "qz16\007beqzalc\005beqzc\007beqzc16\005beqzl\003bge\004bgec\004bgel\004"
5117 "bgeu\005bgeuc\005bgeul\004bgez\006bgezal\007bgezalc\007bgezall\007bgeza"
5118 "ls\005bgezc\005bgezl\003bgt\004bgtl\004bgtu\005bgtul\004bgtz\007bgtzalc"
5119 "\005bgtzc\005bgtzl\007binsl.b\007binsl.d\007binsl.h\007binsl.w\010binsl"
5120 "i.b\010binsli.d\010binsli.h\010binsli.w\007binsr.b\007binsr.d\007binsr."
5121 "h\007binsr.w\010binsri.b\010binsri.d\010binsri.h\010binsri.w\006bitrev\007"
5122 "bitswap\003ble\004blel\004bleu\005bleul\004blez\007blezalc\005blezc\005"
5123 "blezl\003blt\004bltc\004bltl\004bltu\005bltuc\005bltul\004bltz\006bltza"
5124 "l\007bltzalc\007bltzall\007bltzals\005bltzc\005bltzl\006bmnz.v\007bmnzi"
5125 ".b\005bmz.v\006bmzi.b\003bne\004bnec\006bneg.b\006bneg.d\006bneg.h\006b"
5126 "neg.w\007bnegi.b\007bnegi.d\007bnegi.h\007bnegi.w\004bnel\004bnez\006bn"
5127 "ez16\007bnezalc\005bnezc\007bnezc16\005bnezl\004bnvc\005bnz.b\005bnz.d\005"
5128 "bnz.h\005bnz.v\005bnz.w\004bovc\010bposge32\tbposge32c\005break\007brea"
5129 "k16\006bsel.v\007bseli.b\006bset.b\006bset.d\006bset.h\006bset.w\007bse"
5130 "ti.b\007bseti.d\007bseti.h\007bseti.w\005bteqz\005btnez\004bz.b\004bz.d"
5131 "\004bz.h\004bz.v\004bz.w\006c.eq.d\006c.eq.s\005c.f.d\005c.f.s\006c.le."
5132 "d\006c.le.s\006c.lt.d\006c.lt.s\007c.nge.d\007c.nge.s\007c.ngl.d\007c.n"
5133 "gl.s\010c.ngle.d\010c.ngle.s\007c.ngt.d\007c.ngt.s\007c.ole.d\007c.ole."
5134 "s\007c.olt.d\007c.olt.s\007c.seq.d\007c.seq.s\006c.sf.d\006c.sf.s\007c."
5135 "ueq.d\007c.ueq.s\007c.ule.d\007c.ule.s\007c.ult.d\007c.ult.s\006c.un.d\006"
5136 "c.un.s\005cache\006cachee\010ceil.l.d\010ceil.l.s\010ceil.w.d\010ceil.w"
5137 ".s\005ceq.b\005ceq.d\005ceq.h\005ceq.w\006ceqi.b\006ceqi.d\006ceqi.h\006"
5138 "ceqi.w\004cfc1\004cfc2\006cfcmsa\005cftc1\004cins\006cins32\007class.d\007"
5139 "class.s\007cle_s.b\007cle_s.d\007cle_s.h\007cle_s.w\007cle_u.b\007cle_u"
5140 ".d\007cle_u.h\007cle_u.w\010clei_s.b\010clei_s.d\010clei_s.h\010clei_s."
5141 "w\010clei_u.b\010clei_u.d\010clei_u.h\010clei_u.w\003clo\007clt_s.b\007"
5142 "clt_s.d\007clt_s.h\007clt_s.w\007clt_u.b\007clt_u.d\007clt_u.h\007clt_u"
5143 ".w\010clti_s.b\010clti_s.d\010clti_s.h\010clti_s.w\010clti_u.b\010clti_"
5144 "u.d\010clti_u.h\010clti_u.w\003clz\003cmp\010cmp.af.d\010cmp.af.s\010cm"
5145 "p.eq.d\tcmp.eq.ph\010cmp.eq.s\010cmp.le.d\tcmp.le.ph\010cmp.le.s\010cmp"
5146 ".lt.d\tcmp.lt.ph\010cmp.lt.s\tcmp.saf.d\tcmp.saf.s\tcmp.seq.d\tcmp.seq."
5147 "s\tcmp.sle.d\tcmp.sle.s\tcmp.slt.d\tcmp.slt.s\ncmp.sueq.d\ncmp.sueq.s\n"
5148 "cmp.sule.d\ncmp.sule.s\ncmp.sult.d\ncmp.sult.s\tcmp.sun.d\tcmp.sun.s\tc"
5149 "mp.ueq.d\tcmp.ueq.s\tcmp.ule.d\tcmp.ule.s\tcmp.ult.d\tcmp.ult.s\010cmp."
5150 "un.d\010cmp.un.s\014cmpgdu.eq.qb\014cmpgdu.le.qb\014cmpgdu.lt.qb\013cmp"
5151 "gu.eq.qb\013cmpgu.le.qb\013cmpgu.lt.qb\004cmpi\ncmpu.eq.qb\ncmpu.le.qb\n"
5152 "cmpu.lt.qb\010copy_s.b\010copy_s.d\010copy_s.h\010copy_s.w\010copy_u.b\010"
5153 "copy_u.h\010copy_u.w\006crc32b\007crc32cb\007crc32cd\007crc32ch\007crc3"
5154 "2cw\006crc32d\006crc32h\006crc32w\004ctc1\004ctc2\006ctcmsa\005cttc1\007"
5155 "cvt.d.l\007cvt.d.s\007cvt.d.w\007cvt.l.d\007cvt.l.s\tcvt.ps.pw\010cvt.p"
5156 "s.s\tcvt.pw.ps\007cvt.s.d\007cvt.s.l\010cvt.s.pl\010cvt.s.pu\007cvt.s.w"
5157 "\007cvt.w.d\007cvt.w.s\004dadd\005daddi\006daddiu\005daddu\004dahi\006d"
5158 "align\004dati\004daui\010dbitswap\004dclo\004dclz\004ddiv\005ddivu\005d"
5159 "eret\004dext\005dextm\005dextu\002di\004dins\005dinsm\005dinsu\003div\005"
5160 "div.d\005div.s\007div_s.b\007div_s.d\007div_s.h\007div_s.w\007div_u.b\007"
5161 "div_u.d\007div_u.h\007div_u.w\004divu\003dla\003dli\004dlsa\005dmfc0\005"
5162 "dmfc1\005dmfc2\006dmfgc0\004dmod\005dmodu\003dmt\005dmtc0\005dmtc1\005d"
5163 "mtc2\006dmtgc0\004dmuh\005dmuhu\004dmul\005dmulo\006dmulou\005dmult\006"
5164 "dmultu\005dmulu\004dneg\005dnegu\010dotp_s.d\010dotp_s.h\010dotp_s.w\010"
5165 "dotp_u.d\010dotp_u.h\010dotp_u.w\010dpa.w.ph\tdpadd_s.d\tdpadd_s.h\tdpa"
5166 "dd_s.w\tdpadd_u.d\tdpadd_u.h\tdpadd_u.w\013dpaq_s.w.ph\013dpaq_sa.l.w\014"
5167 "dpaqx_s.w.ph\015dpaqx_sa.w.ph\ndpau.h.qbl\ndpau.h.qbr\tdpax.w.ph\004dpo"
5168 "p\010dps.w.ph\013dpsq_s.w.ph\013dpsq_sa.l.w\014dpsqx_s.w.ph\015dpsqx_sa"
5169 ".w.ph\ndpsu.h.qbl\ndpsu.h.qbr\tdpsub_s.d\tdpsub_s.h\tdpsub_s.w\tdpsub_u"
5170 ".d\tdpsub_u.h\tdpsub_u.w\tdpsx.w.ph\004drem\005dremu\004drol\004dror\005"
5171 "drotr\007drotr32\006drotrv\004dsbh\004dshd\004dsll\006dsll32\005dsllv\004"
5172 "dsra\006dsra32\005dsrav\004dsrl\006dsrl32\005dsrlv\004dsub\005dsubi\005"
5173 "dsubu\003dvp\004dvpe\003ehb\002ei\003emt\004eret\006eretnc\003evp\004ev"
5174 "pe\003ext\004extp\006extpdp\007extpdpv\005extpv\006extr.w\010extr_r.w\t"
5175 "extr_rs.w\010extr_s.h\007extrv.w\textrv_r.w\nextrv_rs.w\textrv_s.h\004e"
5176 "xts\006exts32\006fadd.d\006fadd.w\006fcaf.d\006fcaf.w\006fceq.d\006fceq"
5177 ".w\010fclass.d\010fclass.w\006fcle.d\006fcle.w\006fclt.d\006fclt.w\006f"
5178 "cne.d\006fcne.w\006fcor.d\006fcor.w\007fcueq.d\007fcueq.w\007fcule.d\007"
5179 "fcule.w\007fcult.d\007fcult.w\006fcun.d\006fcun.w\007fcune.d\007fcune.w"
5180 "\006fdiv.d\006fdiv.w\007fexdo.h\007fexdo.w\007fexp2.d\007fexp2.w\010fex"
5181 "upl.d\010fexupl.w\010fexupr.d\010fexupr.w\tffint_s.d\tffint_s.w\tffint_"
5182 "u.d\tffint_u.w\006ffql.d\006ffql.w\006ffqr.d\006ffqr.w\006fill.b\006fil"
5183 "l.d\006fill.h\006fill.w\007flog2.d\007flog2.w\tfloor.l.d\tfloor.l.s\tfl"
5184 "oor.w.d\tfloor.w.s\007fmadd.d\007fmadd.w\006fmax.d\006fmax.w\010fmax_a."
5185 "d\010fmax_a.w\006fmin.d\006fmin.w\010fmin_a.d\010fmin_a.w\007fmsub.d\007"
5186 "fmsub.w\006fmul.d\006fmul.w\004fork\006frcp.d\006frcp.w\007frint.d\007f"
5187 "rint.w\010frsqrt.d\010frsqrt.w\006fsaf.d\006fsaf.w\006fseq.d\006fseq.w\006"
5188 "fsle.d\006fsle.w\006fslt.d\006fslt.w\006fsne.d\006fsne.w\006fsor.d\006f"
5189 "sor.w\007fsqrt.d\007fsqrt.w\006fsub.d\006fsub.w\007fsueq.d\007fsueq.w\007"
5190 "fsule.d\007fsule.w\007fsult.d\007fsult.w\006fsun.d\006fsun.w\007fsune.d"
5191 "\007fsune.w\tftint_s.d\tftint_s.w\tftint_u.d\tftint_u.w\005ftq.h\005ftq"
5192 ".w\nftrunc_s.d\nftrunc_s.w\nftrunc_u.d\nftrunc_u.w\005ginvi\005ginvt\010"
5193 "hadd_s.d\010hadd_s.h\010hadd_s.w\010hadd_u.d\010hadd_u.h\010hadd_u.w\010"
5194 "hsub_s.d\010hsub_s.h\010hsub_s.w\010hsub_u.d\010hsub_u.h\010hsub_u.w\007"
5195 "hypcall\007ilvev.b\007ilvev.d\007ilvev.h\007ilvev.w\006ilvl.b\006ilvl.d"
5196 "\006ilvl.h\006ilvl.w\007ilvod.b\007ilvod.d\007ilvod.h\007ilvod.w\006ilv"
5197 "r.b\006ilvr.d\006ilvr.h\006ilvr.w\003ins\010insert.b\010insert.d\010ins"
5198 "ert.h\010insert.w\004insv\007insve.b\007insve.d\007insve.h\007insve.w\001"
5199 "j\003jal\004jalr\007jalr.hb\005jalrc\010jalrc.hb\005jalrs\007jalrs16\004"
5200 "jals\004jalx\005jialc\003jic\002jr\005jr.hb\004jr16\tjraddiusp\003jrc\005"
5201 "jrc16\njrcaddiusp\003l.d\003l.s\002la\004lapc\002lb\003lbe\003lbu\005lb"
5202 "u16\004lbue\004lbux\002ld\004ld.b\004ld.d\004ld.h\004ld.w\004ldc1\004ld"
5203 "c2\004ldc3\005ldi.b\005ldi.d\005ldi.h\005ldi.w\003ldl\004ldpc\003ldr\005"
5204 "ldxc1\002lh\003lhe\003lhu\005lhu16\004lhue\003lhx\002li\004li.d\004li.s"
5205 "\004li16\002ll\003lld\003lle\003lsa\003lui\005luxc1\002lw\004lw16\004lw"
5206 "c1\004lwc2\004lwc3\003lwe\003lwl\004lwle\003lwm\005lwm16\005lwm32\003lw"
5207 "p\004lwpc\003lwr\004lwre\003lwu\005lwupc\003lwx\005lwxc1\004lwxs\004mad"
5208 "d\006madd.d\006madd.s\010madd_q.h\010madd_q.w\007maddf.d\007maddf.s\tma"
5209 "ddr_q.h\tmaddr_q.w\005maddu\007maddv.b\007maddv.d\007maddv.h\007maddv.w"
5210 "\013maq_s.w.phl\013maq_s.w.phr\014maq_sa.w.phl\014maq_sa.w.phr\005max.d"
5211 "\005max.s\007max_a.b\007max_a.d\007max_a.h\007max_a.w\007max_s.b\007max"
5212 "_s.d\007max_s.h\007max_s.w\007max_u.b\007max_u.d\007max_u.h\007max_u.w\006"
5213 "maxa.d\006maxa.s\010maxi_s.b\010maxi_s.d\010maxi_s.h\010maxi_s.w\010max"
5214 "i_u.b\010maxi_u.d\010maxi_u.h\010maxi_u.w\004mfc0\004mfc1\004mfc2\005mf"
5215 "gc0\005mfhc0\005mfhc1\005mfhc2\006mfhgc0\004mfhi\006mfhi16\004mflo\006m"
5216 "flo16\006mftacx\005mftc0\005mftc1\006mftdsp\006mftgpr\006mfthc1\005mfth"
5217 "i\005mftlo\004mftr\005min.d\005min.s\007min_a.b\007min_a.d\007min_a.h\007"
5218 "min_a.w\007min_s.b\007min_s.d\007min_s.h\007min_s.w\007min_u.b\007min_u"
5219 ".d\007min_u.h\007min_u.w\006mina.d\006mina.s\010mini_s.b\010mini_s.d\010"
5220 "mini_s.h\010mini_s.w\010mini_u.b\010mini_u.d\010mini_u.h\010mini_u.w\003"
5221 "mod\007mod_s.b\007mod_s.d\007mod_s.h\007mod_s.w\007mod_u.b\007mod_u.d\007"
5222 "mod_u.h\007mod_u.w\006modsub\004modu\005mov.d\005mov.s\004move\006move."
5223 "v\006move16\005movep\004movf\006movf.d\006movf.s\004movn\006movn.d\006m"
5224 "ovn.s\004movt\006movt.d\006movt.s\004movz\006movz.d\006movz.s\004msub\006"
5225 "msub.d\006msub.s\010msub_q.h\010msub_q.w\007msubf.d\007msubf.s\tmsubr_q"
5226 ".h\tmsubr_q.w\005msubu\007msubv.b\007msubv.d\007msubv.h\007msubv.w\004m"
5227 "tc0\004mtc1\004mtc2\005mtgc0\005mthc0\005mthc1\005mthc2\006mthgc0\004mt"
5228 "hi\006mthlip\004mtlo\004mtm0\004mtm1\004mtm2\004mtp0\004mtp1\004mtp2\006"
5229 "mttacx\005mttc0\005mttc1\006mttdsp\006mttgpr\006mtthc1\005mtthi\005mttl"
5230 "o\004mttr\003muh\004muhu\003mul\005mul.d\006mul.ph\006mul.ps\005mul.s\007"
5231 "mul_q.h\007mul_q.w\010mul_s.ph\015muleq_s.w.phl\015muleq_s.w.phr\016mul"
5232 "eu_s.ph.qbl\016muleu_s.ph.qbr\004mulo\005mulou\nmulq_rs.ph\tmulq_rs.w\t"
5233 "mulq_s.ph\010mulq_s.w\007mulr.ps\010mulr_q.h\010mulr_q.w\nmulsa.w.ph\015"
5234 "mulsaq_s.w.ph\004mult\005multu\004mulu\006mulv.b\006mulv.d\006mulv.h\006"
5235 "mulv.w\003nal\003neg\005neg.d\005neg.s\004negu\006nloc.b\006nloc.d\006n"
5236 "loc.h\006nloc.w\006nlzc.b\006nlzc.d\006nlzc.h\006nlzc.w\007nmadd.d\007n"
5237 "madd.s\007nmsub.d\007nmsub.s\003nop\003nor\005nor.v\006nori.b\003not\005"
5238 "not16\002or\004or.v\004or16\003ori\005ori.b\tpackrl.ph\005pause\007pcke"
5239 "v.b\007pckev.d\007pckev.h\007pckev.w\007pckod.b\007pckod.d\007pckod.h\007"
5240 "pckod.w\006pcnt.b\006pcnt.d\006pcnt.h\006pcnt.w\007pick.ph\007pick.qb\006"
5241 "pll.ps\006plu.ps\003pop\014preceq.w.phl\014preceq.w.phr\016precequ.ph.q"
5242 "bl\017precequ.ph.qbla\016precequ.ph.qbr\017precequ.ph.qbra\015preceu.ph"
5243 ".qbl\016preceu.ph.qbla\015preceu.ph.qbr\016preceu.ph.qbra\013precr.qb.p"
5244 "h\016precr_sra.ph.w\020precr_sra_r.ph.w\013precrq.ph.w\014precrq.qb.ph\016"
5245 "precrq_rs.ph.w\017precrqu_s.qb.ph\004pref\005prefe\005prefx\007prepend\006"
5246 "pul.ps\006puu.ps\nraddu.w.qb\005rddsp\005rdhwr\006rdpgpr\007recip.d\007"
5247 "recip.s\003rem\004remu\007repl.ph\007repl.qb\010replv.ph\010replv.qb\006"
5248 "rint.d\006rint.s\003rol\003ror\004rotr\005rotrv\tround.l.d\tround.l.s\t"
5249 "round.w.d\tround.w.s\007rsqrt.d\007rsqrt.s\003s.d\003s.s\003saa\004saad"
5250 "\007sat_s.b\007sat_s.d\007sat_s.h\007sat_s.w\007sat_u.b\007sat_u.d\007s"
5251 "at_u.h\007sat_u.w\002sb\004sb16\003sbe\002sc\003scd\003sce\002sd\005sdb"
5252 "bp\007sdbbp16\004sdc1\004sdc2\004sdc3\003sdl\003sdr\005sdxc1\003seb\003"
5253 "seh\005sel.d\005sel.s\006seleqz\010seleqz.d\010seleqz.s\006selnez\010se"
5254 "lnez.d\010selnez.s\003seq\004seqi\003sge\004sgeu\003sgt\004sgtu\002sh\004"
5255 "sh16\003she\005shf.b\005shf.h\005shf.w\005shilo\006shilov\007shll.ph\007"
5256 "shll.qb\tshll_s.ph\010shll_s.w\010shllv.ph\010shllv.qb\nshllv_s.ph\tshl"
5257 "lv_s.w\007shra.ph\007shra.qb\tshra_r.ph\tshra_r.qb\010shra_r.w\010shrav"
5258 ".ph\010shrav.qb\nshrav_r.ph\nshrav_r.qb\tshrav_r.w\007shrl.ph\007shrl.q"
5259 "b\010shrlv.ph\010shrlv.qb\006sigrie\005sld.b\005sld.d\005sld.h\005sld.w"
5260 "\006sldi.b\006sldi.d\006sldi.h\006sldi.w\003sle\004sleu\003sll\005sll.b"
5261 "\005sll.d\005sll.h\005sll.w\005sll16\006slli.b\006slli.d\006slli.h\006s"
5262 "lli.w\004sllv\003slt\004slti\005sltiu\004sltu\003sne\004snei\007splat.b"
5263 "\007splat.d\007splat.h\007splat.w\010splati.b\010splati.d\010splati.h\010"
5264 "splati.w\006sqrt.d\006sqrt.s\003sra\005sra.b\005sra.d\005sra.h\005sra.w"
5265 "\006srai.b\006srai.d\006srai.h\006srai.w\006srar.b\006srar.d\006srar.h\006"
5266 "srar.w\007srari.b\007srari.d\007srari.h\007srari.w\004srav\003srl\005sr"
5267 "l.b\005srl.d\005srl.h\005srl.w\005srl16\006srli.b\006srli.d\006srli.h\006"
5268 "srli.w\006srlr.b\006srlr.d\006srlr.h\006srlr.w\007srlri.b\007srlri.d\007"
5269 "srlri.h\007srlri.w\004srlv\005ssnop\004st.b\004st.d\004st.h\004st.w\003"
5270 "sub\005sub.d\006sub.ps\005sub.s\007subq.ph\tsubq_s.ph\010subq_s.w\010su"
5271 "bqh.ph\007subqh.w\nsubqh_r.ph\tsubqh_r.w\010subs_s.b\010subs_s.d\010sub"
5272 "s_s.h\010subs_s.w\010subs_u.b\010subs_u.d\010subs_u.h\010subs_u.w\nsubs"
5273 "us_u.b\nsubsus_u.d\nsubsus_u.h\nsubsus_u.w\nsubsuu_s.b\nsubsuu_s.d\nsub"
5274 "suu_s.h\nsubsuu_s.w\004subu\007subu.ph\007subu.qb\006subu16\tsubu_s.ph\t"
5275 "subu_s.qb\010subuh.qb\nsubuh_r.qb\006subv.b\006subv.d\006subv.h\006subv"
5276 ".w\007subvi.b\007subvi.d\007subvi.h\007subvi.w\005suxc1\002sw\004sw16\004"
5277 "swc1\004swc2\004swc3\003swe\003swl\004swle\003swm\005swm16\005swm32\003"
5278 "swp\003swr\004swre\004swsp\005swxc1\004sync\014sync_acquire\007sync_mb\014"
5279 "sync_release\010sync_rmb\010sync_wmb\005synci\nsynciobdma\005syncs\005s"
5280 "yncw\006syncws\007syscall\003teq\004teqi\003tge\004tgei\005tgeiu\004tge"
5281 "u\007tlbginv\010tlbginvf\005tlbgp\005tlbgr\006tlbgwi\006tlbgwr\006tlbin"
5282 "v\007tlbinvf\004tlbp\004tlbr\005tlbwi\005tlbwr\003tlt\004tlti\005tltiu\004"
5283 "tltu\003tne\004tnei\ttrunc.l.d\ttrunc.l.s\ttrunc.w.d\ttrunc.w.s\003ulh\004"
5284 "ulhu\003ulw\003ush\003usw\006v3mulu\004vmm0\005vmulu\006vshf.b\006vshf."
5285 "d\006vshf.h\006vshf.w\004wait\005wrdsp\006wrpgpr\004wsbh\003xor\005xor."
5286 "v\005xor16\004xori\006xori.b\005yield";
5287
5288// Feature bitsets.
5289enum : uint8_t {
5290 AMFBS_None,
5291 AMFBS_HasCnMips,
5292 AMFBS_HasCnMipsP,
5293 AMFBS_HasDSP,
5294 AMFBS_HasDSPR2,
5295 AMFBS_HasMT,
5296 AMFBS_InMicroMips,
5297 AMFBS_InMips16Mode,
5298 AMFBS_IsGP32bit,
5299 AMFBS_IsGP64bit,
5300 AMFBS_IsNotSoftFloat,
5301 AMFBS_NotCnMips,
5302 AMFBS_NotInMicroMips,
5303 AMFBS_HasDSP_InMicroMips,
5304 AMFBS_HasDSP_NotInMicroMips,
5305 AMFBS_HasMT_NotInMicroMips,
5306 AMFBS_HasMips64_HasCnMips,
5307 AMFBS_HasStdEnc_HasMSA,
5308 AMFBS_HasStdEnc_HasMips3,
5309 AMFBS_HasStdEnc_HasMips32,
5310 AMFBS_HasStdEnc_HasMips32r6,
5311 AMFBS_HasStdEnc_HasMips64,
5312 AMFBS_HasStdEnc_HasMips64r6,
5313 AMFBS_HasStdEnc_IsNotSoftFloat,
5314 AMFBS_HasStdEnc_NotInMicroMips,
5315 AMFBS_HasStdEnc_NotMips3,
5316 AMFBS_InMicroMips_HasDSP,
5317 AMFBS_InMicroMips_HasDSPR2,
5318 AMFBS_InMicroMips_HasDSPR3,
5319 AMFBS_InMicroMips_HasEVA,
5320 AMFBS_InMicroMips_HasMips32r6,
5321 AMFBS_InMicroMips_IsNotSoftFloat,
5322 AMFBS_InMicroMips_NotMips32r6,
5323 AMFBS_IsGP32bit_NotInMicroMips,
5324 AMFBS_IsGP64bit_NotInMicroMips,
5325 AMFBS_NotInMips16Mode_HasDSP,
5326 AMFBS_NotInMips16Mode_IsPTR64bit,
5327 AMFBS_HasMips64_HasCnMips_NotInMicroMips,
5328 AMFBS_HasStdEnc_HasMSA_HasMips64,
5329 AMFBS_HasStdEnc_HasMT_NotInMicroMips,
5330 AMFBS_HasStdEnc_HasMips2_IsNotSoftFloat,
5331 AMFBS_HasStdEnc_HasMips2_NotInMicroMips,
5332 AMFBS_HasStdEnc_HasMips3_NotInMicroMips,
5333 AMFBS_HasStdEnc_HasMips32_NotInMicroMips,
5334 AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips,
5335 AMFBS_HasStdEnc_HasMips32r5_NotInMicroMips,
5336 AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips,
5337 AMFBS_HasStdEnc_HasMips3_32_NotInMicroMips,
5338 AMFBS_HasStdEnc_HasMips64_NotInMicroMips,
5339 AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips,
5340 AMFBS_HasStdEnc_HasMips64r5_HasVirt,
5341 AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips,
5342 AMFBS_HasStdEnc_IsGP32bit_HasMips32r6,
5343 AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips,
5344 AMFBS_HasStdEnc_IsGP64bit_HasMips3,
5345 AMFBS_HasStdEnc_IsGP64bit_HasMips32r6,
5346 AMFBS_HasStdEnc_IsGP64bit_HasMips64r6,
5347 AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
5348 AMFBS_HasStdEnc_NotInMicroMips_NoIndirectJumpGuards,
5349 AMFBS_HasStdEnc_NotMips32r6_NotMips64r6,
5350 AMFBS_InMicroMips_HasMips32r5_HasVirt,
5351 AMFBS_InMicroMips_HasMips32r6_HasGINV,
5352 AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat,
5353 AMFBS_InMicroMips_NotMips32r6_HasDSP,
5354 AMFBS_InMicroMips_NotMips32r6_HasEVA,
5355 AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat,
5356 AMFBS_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat,
5357 AMFBS_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat,
5358 AMFBS_NotInMips16Mode_IsPTR64bit_NotInMicroMips,
5359 AMFBS_HasMips3_NotMips64r6_NotCnMips_NotR5900,
5360 AMFBS_HasStdEnc_HasMips2_IsNotSoftFloat_NotInMicroMips,
5361 AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6,
5362 AMFBS_HasStdEnc_HasMips3_IsNotSoftFloat_IsNotSingleFloat,
5363 AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6,
5364 AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6,
5365 AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips,
5366 AMFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6,
5367 AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips,
5368 AMFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips,
5369 AMFBS_HasStdEnc_HasMips32r6_HasGINV_NotInMicroMips,
5370 AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips,
5371 AMFBS_HasStdEnc_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips,
5372 AMFBS_HasStdEnc_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips,
5373 AMFBS_HasStdEnc_HasMips64_NotMips64r6_NotInMicroMips,
5374 AMFBS_HasStdEnc_HasMips64r5_HasVirt_NotInMicroMips,
5375 AMFBS_HasStdEnc_HasMips64r6_HasCRC_NotInMicroMips,
5376 AMFBS_HasStdEnc_IsGP32bit_HasMips32r6_NotInMicroMips,
5377 AMFBS_HasStdEnc_IsGP64bit_HasMips3_NotInMicroMips,
5378 AMFBS_HasStdEnc_IsPTR32bit_HasMips32r6_NotInMicroMips,
5379 AMFBS_HasStdEnc_IsPTR64bit_HasMips64r6_NotInMicroMips,
5380 AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat,
5381 AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips,
5382 AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat,
5383 AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat,
5384 AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat_HasMadd4,
5385 AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips,
5386 AMFBS_HasStdEnc_HasMips2_NotR5900_IsNotSoftFloat_NotInMicroMips,
5387 AMFBS_HasStdEnc_HasMips2_NotR5900_NotCnMips_NotInMicroMips,
5388 AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips,
5389 AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900,
5390 AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips,
5391 AMFBS_HasStdEnc_HasMips3_32_NotMips32r6_NotMips64r6_NotInMicroMips,
5392 AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips,
5393 AMFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat,
5394 AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat,
5395 AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips,
5396 AMFBS_HasStdEnc_IsGP64bit_HasMips64_NotMips64r6_NotInMicroMips,
5397 AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat,
5398 AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips,
5399 AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips,
5400 AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_HasMips32r6_IsNotSoftFloat,
5401 AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat,
5402 AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat,
5403 AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips,
5404 AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips,
5405 AMFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips,
5406 AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips,
5407 AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips,
5408 AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips32r2_IsNotSoftFloat_NotInMicroMips,
5409 AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips3_32_IsNotSoftFloat_NotInMicroMips,
5410 AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips,
5411 AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips,
5412 AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips,
5413 AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips32r2_IsNotSoftFloat_NotInMicroMips,
5414 AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips,
5415 AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips,
5416 AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_NotCnMips_NotInMicroMips,
5417 AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat_HasMadd4,
5418 AMFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips,
5419 AMFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4,
5420 AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat,
5421 AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips,
5422 AMFBS_HasStdEnc_IsPTR32bit_HasMips2_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips,
5423 AMFBS_HasStdEnc_IsPTR64bit_HasMips2_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips,
5424 AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips,
5425 AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMips3D,
5426 AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips,
5427 AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips,
5428 AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips,
5429 AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips,
5430 AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips,
5431 AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips,
5432 AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips,
5433 AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4,
5434 AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips,
5435 AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4,
5436};
5437
5438static constexpr FeatureBitset FeatureBitsets[] = {
5439 {}, // AMFBS_None
5440 {Feature_HasCnMipsBit, }, // AMFBS_HasCnMips
5441 {Feature_HasCnMipsPBit, }, // AMFBS_HasCnMipsP
5442 {Feature_HasDSPBit, }, // AMFBS_HasDSP
5443 {Feature_HasDSPR2Bit, }, // AMFBS_HasDSPR2
5444 {Feature_HasMTBit, }, // AMFBS_HasMT
5445 {Feature_InMicroMipsBit, }, // AMFBS_InMicroMips
5446 {Feature_InMips16ModeBit, }, // AMFBS_InMips16Mode
5447 {Feature_IsGP32bitBit, }, // AMFBS_IsGP32bit
5448 {Feature_IsGP64bitBit, }, // AMFBS_IsGP64bit
5449 {Feature_IsNotSoftFloatBit, }, // AMFBS_IsNotSoftFloat
5450 {Feature_NotCnMipsBit, }, // AMFBS_NotCnMips
5451 {Feature_NotInMicroMipsBit, }, // AMFBS_NotInMicroMips
5452 {Feature_HasDSPBit, Feature_InMicroMipsBit, }, // AMFBS_HasDSP_InMicroMips
5453 {Feature_HasDSPBit, Feature_NotInMicroMipsBit, }, // AMFBS_HasDSP_NotInMicroMips
5454 {Feature_HasMTBit, Feature_NotInMicroMipsBit, }, // AMFBS_HasMT_NotInMicroMips
5455 {Feature_HasMips64Bit, Feature_HasCnMipsBit, }, // AMFBS_HasMips64_HasCnMips
5456 {Feature_HasStdEncBit, Feature_HasMSABit, }, // AMFBS_HasStdEnc_HasMSA
5457 {Feature_HasStdEncBit, Feature_HasMips3Bit, }, // AMFBS_HasStdEnc_HasMips3
5458 {Feature_HasStdEncBit, Feature_HasMips32Bit, }, // AMFBS_HasStdEnc_HasMips32
5459 {Feature_HasStdEncBit, Feature_HasMips32r6Bit, }, // AMFBS_HasStdEnc_HasMips32r6
5460 {Feature_HasStdEncBit, Feature_HasMips64Bit, }, // AMFBS_HasStdEnc_HasMips64
5461 {Feature_HasStdEncBit, Feature_HasMips64r6Bit, }, // AMFBS_HasStdEnc_HasMips64r6
5462 {Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, }, // AMFBS_HasStdEnc_IsNotSoftFloat
5463 {Feature_HasStdEncBit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_NotInMicroMips
5464 {Feature_HasStdEncBit, Feature_NotMips3Bit, }, // AMFBS_HasStdEnc_NotMips3
5465 {Feature_InMicroMipsBit, Feature_HasDSPBit, }, // AMFBS_InMicroMips_HasDSP
5466 {Feature_InMicroMipsBit, Feature_HasDSPR2Bit, }, // AMFBS_InMicroMips_HasDSPR2
5467 {Feature_InMicroMipsBit, Feature_HasDSPR3Bit, }, // AMFBS_InMicroMips_HasDSPR3
5468 {Feature_InMicroMipsBit, Feature_HasEVABit, }, // AMFBS_InMicroMips_HasEVA
5469 {Feature_InMicroMipsBit, Feature_HasMips32r6Bit, }, // AMFBS_InMicroMips_HasMips32r6
5470 {Feature_InMicroMipsBit, Feature_IsNotSoftFloatBit, }, // AMFBS_InMicroMips_IsNotSoftFloat
5471 {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, }, // AMFBS_InMicroMips_NotMips32r6
5472 {Feature_IsGP32bitBit, Feature_NotInMicroMipsBit, }, // AMFBS_IsGP32bit_NotInMicroMips
5473 {Feature_IsGP64bitBit, Feature_NotInMicroMipsBit, }, // AMFBS_IsGP64bit_NotInMicroMips
5474 {Feature_NotInMips16ModeBit, Feature_HasDSPBit, }, // AMFBS_NotInMips16Mode_HasDSP
5475 {Feature_NotInMips16ModeBit, Feature_IsPTR64bitBit, }, // AMFBS_NotInMips16Mode_IsPTR64bit
5476 {Feature_HasMips64Bit, Feature_HasCnMipsBit, Feature_NotInMicroMipsBit, }, // AMFBS_HasMips64_HasCnMips_NotInMicroMips
5477 {Feature_HasStdEncBit, Feature_HasMSABit, Feature_HasMips64Bit, }, // AMFBS_HasStdEnc_HasMSA_HasMips64
5478 {Feature_HasStdEncBit, Feature_HasMTBit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_HasMT_NotInMicroMips
5479 {Feature_HasStdEncBit, Feature_HasMips2Bit, Feature_IsNotSoftFloatBit, }, // AMFBS_HasStdEnc_HasMips2_IsNotSoftFloat
5480 {Feature_HasStdEncBit, Feature_HasMips2Bit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_HasMips2_NotInMicroMips
5481 {Feature_HasStdEncBit, Feature_HasMips3Bit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_HasMips3_NotInMicroMips
5482 {Feature_HasStdEncBit, Feature_HasMips32Bit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_HasMips32_NotInMicroMips
5483 {Feature_HasStdEncBit, Feature_HasMips32r2Bit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips
5484 {Feature_HasStdEncBit, Feature_HasMips32r5Bit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_HasMips32r5_NotInMicroMips
5485 {Feature_HasStdEncBit, Feature_HasMips32r6Bit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips
5486 {Feature_HasStdEncBit, Feature_HasMips3_32Bit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_HasMips3_32_NotInMicroMips
5487 {Feature_HasStdEncBit, Feature_HasMips64Bit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_HasMips64_NotInMicroMips
5488 {Feature_HasStdEncBit, Feature_HasMips64r2Bit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips
5489 {Feature_HasStdEncBit, Feature_HasMips64r5Bit, Feature_HasVirtBit, }, // AMFBS_HasStdEnc_HasMips64r5_HasVirt
5490 {Feature_HasStdEncBit, Feature_HasMips64r6Bit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips
5491 {Feature_HasStdEncBit, Feature_IsGP32bitBit, Feature_HasMips32r6Bit, }, // AMFBS_HasStdEnc_IsGP32bit_HasMips32r6
5492 {Feature_HasStdEncBit, Feature_IsGP32bitBit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips
5493 {Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_HasMips3Bit, }, // AMFBS_HasStdEnc_IsGP64bit_HasMips3
5494 {Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_HasMips32r6Bit, }, // AMFBS_HasStdEnc_IsGP64bit_HasMips32r6
5495 {Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_HasMips64r6Bit, }, // AMFBS_HasStdEnc_IsGP64bit_HasMips64r6
5496 {Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips
5497 {Feature_HasStdEncBit, Feature_NotInMicroMipsBit, Feature_NoIndirectJumpGuardsBit, }, // AMFBS_HasStdEnc_NotInMicroMips_NoIndirectJumpGuards
5498 {Feature_HasStdEncBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, }, // AMFBS_HasStdEnc_NotMips32r6_NotMips64r6
5499 {Feature_InMicroMipsBit, Feature_HasMips32r5Bit, Feature_HasVirtBit, }, // AMFBS_InMicroMips_HasMips32r5_HasVirt
5500 {Feature_InMicroMipsBit, Feature_HasMips32r6Bit, Feature_HasGINVBit, }, // AMFBS_InMicroMips_HasMips32r6_HasGINV
5501 {Feature_InMicroMipsBit, Feature_HasMips32r6Bit, Feature_IsNotSoftFloatBit, }, // AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat
5502 {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_HasDSPBit, }, // AMFBS_InMicroMips_NotMips32r6_HasDSP
5503 {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_HasEVABit, }, // AMFBS_InMicroMips_NotMips32r6_HasEVA
5504 {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_IsNotSoftFloatBit, }, // AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat
5505 {Feature_IsFP64bitBit, Feature_IsNotSingleFloatBit, Feature_IsNotSoftFloatBit, }, // AMFBS_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat
5506 {Feature_NotFP64bitBit, Feature_IsNotSingleFloatBit, Feature_IsNotSoftFloatBit, }, // AMFBS_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat
5507 {Feature_NotInMips16ModeBit, Feature_IsPTR64bitBit, Feature_NotInMicroMipsBit, }, // AMFBS_NotInMips16Mode_IsPTR64bit_NotInMicroMips
5508 {Feature_HasMips3Bit, Feature_NotMips64r6Bit, Feature_NotCnMipsBit, Feature_NotR5900Bit, }, // AMFBS_HasMips3_NotMips64r6_NotCnMips_NotR5900
5509 {Feature_HasStdEncBit, Feature_HasMips2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_HasMips2_IsNotSoftFloat_NotInMicroMips
5510 {Feature_HasStdEncBit, Feature_HasMips2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, }, // AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6
5511 {Feature_HasStdEncBit, Feature_HasMips3Bit, Feature_IsNotSoftFloatBit, Feature_IsNotSingleFloatBit, }, // AMFBS_HasStdEnc_HasMips3_IsNotSoftFloat_IsNotSingleFloat
5512 {Feature_HasStdEncBit, Feature_HasMips3Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, }, // AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6
5513 {Feature_HasStdEncBit, Feature_HasMips32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, }, // AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6
5514 {Feature_HasStdEncBit, Feature_HasMips32r2Bit, Feature_HasEVABit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips
5515 {Feature_HasStdEncBit, Feature_HasMips32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, }, // AMFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6
5516 {Feature_HasStdEncBit, Feature_HasMips32r5Bit, Feature_HasVirtBit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips
5517 {Feature_HasStdEncBit, Feature_HasMips32r6Bit, Feature_HasCRCBit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips
5518 {Feature_HasStdEncBit, Feature_HasMips32r6Bit, Feature_HasGINVBit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_HasMips32r6_HasGINV_NotInMicroMips
5519 {Feature_HasStdEncBit, Feature_HasMips32r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips
5520 {Feature_HasStdEncBit, Feature_HasMips3_32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips
5521 {Feature_HasStdEncBit, Feature_HasMips4_32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips
5522 {Feature_HasStdEncBit, Feature_HasMips64Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_HasMips64_NotMips64r6_NotInMicroMips
5523 {Feature_HasStdEncBit, Feature_HasMips64r5Bit, Feature_HasVirtBit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_HasMips64r5_HasVirt_NotInMicroMips
5524 {Feature_HasStdEncBit, Feature_HasMips64r6Bit, Feature_HasCRCBit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_HasMips64r6_HasCRC_NotInMicroMips
5525 {Feature_HasStdEncBit, Feature_IsGP32bitBit, Feature_HasMips32r6Bit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_IsGP32bit_HasMips32r6_NotInMicroMips
5526 {Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_HasMips3Bit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_IsGP64bit_HasMips3_NotInMicroMips
5527 {Feature_HasStdEncBit, Feature_IsPTR32bitBit, Feature_HasMips32r6Bit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_IsPTR32bit_HasMips32r6_NotInMicroMips
5528 {Feature_HasStdEncBit, Feature_IsPTR64bitBit, Feature_HasMips64r6Bit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_IsPTR64bit_HasMips64r6_NotInMicroMips
5529 {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_IsNotSingleFloatBit, Feature_IsNotSoftFloatBit, }, // AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat
5530 {Feature_HasStdEncBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips
5531 {Feature_InMicroMipsBit, Feature_IsFP64bitBit, Feature_IsNotSingleFloatBit, Feature_IsNotSoftFloatBit, }, // AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat
5532 {Feature_InMicroMipsBit, Feature_NotFP64bitBit, Feature_IsNotSingleFloatBit, Feature_IsNotSoftFloatBit, }, // AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat
5533 {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_IsNotSoftFloatBit, Feature_HasMadd4Bit, }, // AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat_HasMadd4
5534 {Feature_HasStdEncBit, Feature_HasMips2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips
5535 {Feature_HasStdEncBit, Feature_HasMips2Bit, Feature_NotR5900Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_HasMips2_NotR5900_IsNotSoftFloat_NotInMicroMips
5536 {Feature_HasStdEncBit, Feature_HasMips2Bit, Feature_NotR5900Bit, Feature_NotCnMipsBit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_HasMips2_NotR5900_NotCnMips_NotInMicroMips
5537 {Feature_HasStdEncBit, Feature_HasMips3Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips
5538 {Feature_HasStdEncBit, Feature_HasMips3Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotR5900Bit, }, // AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900
5539 {Feature_HasStdEncBit, Feature_HasMips32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips
5540 {Feature_HasStdEncBit, Feature_HasMips3_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_HasMips3_32_NotMips32r6_NotMips64r6_NotInMicroMips
5541 {Feature_HasStdEncBit, Feature_HasMips4_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips
5542 {Feature_HasStdEncBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, }, // AMFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat
5543 {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSingleFloatBit, Feature_HasMips2Bit, Feature_IsNotSoftFloatBit, }, // AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat
5544 {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSingleFloatBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips
5545 {Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_HasMips64Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_IsGP64bit_HasMips64_NotMips64r6_NotInMicroMips
5546 {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_IsNotSingleFloatBit, Feature_HasMips2Bit, Feature_IsNotSoftFloatBit, }, // AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat
5547 {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_IsNotSingleFloatBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips
5548 {Feature_HasStdEncBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips
5549 {Feature_InMicroMipsBit, Feature_IsFP64bitBit, Feature_IsNotSingleFloatBit, Feature_HasMips32r6Bit, Feature_IsNotSoftFloatBit, }, // AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_HasMips32r6_IsNotSoftFloat
5550 {Feature_InMicroMipsBit, Feature_IsFP64bitBit, Feature_IsNotSingleFloatBit, Feature_NotMips32r6Bit, Feature_IsNotSoftFloatBit, }, // AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat
5551 {Feature_InMicroMipsBit, Feature_NotFP64bitBit, Feature_IsNotSingleFloatBit, Feature_NotMips32r6Bit, Feature_IsNotSoftFloatBit, }, // AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat
5552 {Feature_HasStdEncBit, Feature_HasMips2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips
5553 {Feature_HasStdEncBit, Feature_HasMips3Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotR5900Bit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips
5554 {Feature_HasStdEncBit, Feature_HasMips32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_HasEVABit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips
5555 {Feature_HasStdEncBit, Feature_HasMips4_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips
5556 {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSingleFloatBit, Feature_HasMips2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips
5557 {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSingleFloatBit, Feature_HasMips32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips32r2_IsNotSoftFloat_NotInMicroMips
5558 {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSingleFloatBit, Feature_HasMips3_32Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips3_32_IsNotSoftFloat_NotInMicroMips
5559 {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSingleFloatBit, Feature_HasMips3_32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips
5560 {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSingleFloatBit, Feature_HasMips4_32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips
5561 {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_IsNotSingleFloatBit, Feature_HasMips2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips
5562 {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_IsNotSingleFloatBit, Feature_HasMips32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips32r2_IsNotSoftFloat_NotInMicroMips
5563 {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_IsNotSingleFloatBit, Feature_HasMips4_32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips
5564 {Feature_HasStdEncBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotR5900Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips
5565 {Feature_HasStdEncBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotR5900Bit, Feature_NotCnMipsBit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_NotCnMips_NotInMicroMips
5566 {Feature_InMicroMipsBit, Feature_NotFP64bitBit, Feature_IsNotSingleFloatBit, Feature_NotMips32r6Bit, Feature_IsNotSoftFloatBit, Feature_HasMadd4Bit, }, // AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat_HasMadd4
5567 {Feature_HasStdEncBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_HasMadd4Bit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips
5568 {Feature_HasStdEncBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, Feature_HasMadd4Bit, }, // AMFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4
5569 {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSingleFloatBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, }, // AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat
5570 {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSingleFloatBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips
5571 {Feature_HasStdEncBit, Feature_IsPTR32bitBit, Feature_HasMips2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotR5900Bit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_IsPTR32bit_HasMips2_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips
5572 {Feature_HasStdEncBit, Feature_IsPTR64bitBit, Feature_HasMips2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotR5900Bit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_IsPTR64bit_HasMips2_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips
5573 {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_IsNotSingleFloatBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips
5574 {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSingleFloatBit, Feature_HasMips32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_HasMips3DBit, }, // AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMips3D
5575 {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSingleFloatBit, Feature_HasMips32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips
5576 {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSingleFloatBit, Feature_HasMips4_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips
5577 {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSingleFloatBit, Feature_HasMips5_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips
5578 {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_IsNotSingleFloatBit, Feature_HasMips4_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips
5579 {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_IsNotSingleFloatBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips
5580 {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_IsNotSingleFloatBit, Feature_HasMips5_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips
5581 {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSingleFloatBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_HasMadd4Bit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips
5582 {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSingleFloatBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, Feature_HasMadd4Bit, }, // AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4
5583 {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_IsNotSingleFloatBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_HasMadd4Bit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips
5584 {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_IsNotSingleFloatBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, Feature_HasMadd4Bit, }, // AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4
5585};
5586
5587namespace {
5588 struct MatchEntry {
5589 uint16_t Mnemonic;
5590 uint32_t Opcode;
5591 uint16_t ConvertFn;
5592 uint8_t RequiredFeaturesIdx;
5593 uint8_t Classes[8];
5594 StringRef getMnemonic() const {
5595 return StringRef(MnemonicTable + Mnemonic + 1,
5596 MnemonicTable[Mnemonic]);
5597 }
5598 };
5599
5600 // Predicate for searching for an opcode.
5601 struct LessOpcode {
5602 bool operator()(const MatchEntry &LHS, StringRef RHS) {
5603 return LHS.getMnemonic() < RHS;
5604 }
5605 bool operator()(StringRef LHS, const MatchEntry &RHS) {
5606 return LHS < RHS.getMnemonic();
5607 }
5608 bool operator()(const MatchEntry &LHS, const MatchEntry &RHS) {
5609 return LHS.getMnemonic() < RHS.getMnemonic();
5610 }
5611 };
5612} // end anonymous namespace
5613
5614static const MatchEntry MatchTable0[] = {
5615 { 0 /* abs */, Mips::ABSMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_None, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5616 { 4 /* abs.d */, Mips::FABS_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5617 { 4 /* abs.d */, Mips::FABS_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5618 { 4 /* abs.d */, Mips::FABS_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5619 { 4 /* abs.d */, Mips::FABS_D64_MM, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5620 { 10 /* abs.s */, Mips::FABS_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5621 { 10 /* abs.s */, Mips::FABS_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5622 { 16 /* absq_s.ph */, Mips::ABSQ_S_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5623 { 16 /* absq_s.ph */, Mips::ABSQ_S_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5624 { 26 /* absq_s.qb */, Mips::ABSQ_S_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5625 { 26 /* absq_s.qb */, Mips::ABSQ_S_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5626 { 36 /* absq_s.w */, Mips::ABSQ_S_W_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5627 { 36 /* absq_s.w */, Mips::ABSQ_S_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5628 { 45 /* add */, Mips::ADD, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5629 { 45 /* add */, Mips::ADD_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5630 { 45 /* add */, Mips::ADD_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5631 { 45 /* add */, Mips::ADDi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
5632 { 45 /* add */, Mips::ADDi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
5633 { 45 /* add */, Mips::ADD, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5634 { 45 /* add */, Mips::ADD_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5635 { 45 /* add */, Mips::ADD_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5636 { 45 /* add */, Mips::ADDi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
5637 { 45 /* add */, Mips::ADDi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
5638 { 49 /* add.d */, Mips::FADD_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5639 { 49 /* add.d */, Mips::FADD_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5640 { 49 /* add.d */, Mips::FADD_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5641 { 49 /* add.d */, Mips::FADD_D64_MM, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5642 { 55 /* add.ps */, Mips::FADD_PS64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5643 { 62 /* add.s */, Mips::FADD_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5644 { 62 /* add.s */, Mips::FADD_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_2__FGR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5645 { 62 /* add.s */, Mips::FADD_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5646 { 68 /* add_a.b */, Mips::ADD_A_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5647 { 76 /* add_a.d */, Mips::ADD_A_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5648 { 84 /* add_a.h */, Mips::ADD_A_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5649 { 92 /* add_a.w */, Mips::ADD_A_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5650 { 100 /* addi */, Mips::ADDi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm161_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, },
5651 { 100 /* addi */, Mips::ADDi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm16_Relaxed1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm16_Relaxed }, },
5652 { 100 /* addi */, Mips::ADDi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16 }, },
5653 { 100 /* addi */, Mips::ADDi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm16_Relaxed1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16_Relaxed }, },
5654 { 105 /* addiu */, Mips::AddiuSpImmX16, Convert__SImm161_1, AMFBS_InMips16Mode, { MCK_CPUSPReg, MCK_SImm16 }, },
5655 { 105 /* addiu */, Mips::AddiuRxImmX16, Convert__Reg1_0__SImm161_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_SImm16 }, },
5656 { 105 /* addiu */, Mips::ADDIU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm161_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, },
5657 { 105 /* addiu */, Mips::ADDiu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm161_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, },
5658 { 105 /* addiu */, Mips::ADDiu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm16_Relaxed1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm16_Relaxed }, },
5659 { 105 /* addiu */, Mips::AddiuRxPcImmX16, Convert__Reg1_0__SImm161_2, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_PC, MCK_SImm16 }, },
5660 { 105 /* addiu */, Mips::AddiuRxRyOffMemX16, Convert__Reg1_0__Reg1_1__SImm161_2, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16RegsPlusSP, MCK_SImm16 }, },
5661 { 105 /* addiu */, Mips::ADDIU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16 }, },
5662 { 105 /* addiu */, Mips::ADDiu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16 }, },
5663 { 105 /* addiu */, Mips::ADDiu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm16_Relaxed1_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16_Relaxed }, },
5664 { 105 /* addiu */, Mips::AddiuSpImm16, Convert__SImm161_1, AMFBS_InMips16Mode, { MCK_CPUSPReg, MCK_SImm16, MCK__HASH_, MCK_16, MCK_bit, MCK_inst }, },
5665 { 105 /* addiu */, Mips::AddiuRxRxImm16, Convert__Reg1_0__Tie0_1_1__SImm161_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_SImm16, MCK__HASH_, MCK_16, MCK_bit, MCK_inst }, },
5666 { 111 /* addiupc */, Mips::ADDIUPC, Convert__GPR32AsmReg1_0__Simm19_Lsl21_1, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR32AsmReg, MCK_Simm19_Lsl2 }, },
5667 { 111 /* addiupc */, Mips::ADDIUPC_MMR6, Convert__GPR32AsmReg1_0__Simm19_Lsl21_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_Simm19_Lsl2 }, },
5668 { 111 /* addiupc */, Mips::ADDIUPC_MM, Convert__GPRMM16AsmReg1_0__Imm1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_Imm }, },
5669 { 119 /* addiur1sp */, Mips::ADDIUR1SP_MM, Convert__GPRMM16AsmReg1_0__UImm6Lsl21_1, AMFBS_InMicroMips, { MCK_GPRMM16AsmReg, MCK_UImm6Lsl2 }, },
5670 { 129 /* addiur2 */, Mips::ADDIUR2_MM, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Imm1_2, AMFBS_InMicroMips, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_Imm }, },
5671 { 137 /* addius5 */, Mips::ADDIUS5_MM, Convert__GPR32AsmReg1_0__Tie0_1_1__ConstantSImm4_01_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_ConstantSImm4_0 }, },
5672 { 145 /* addiusp */, Mips::ADDIUSP_MM, Convert__Imm1_0, AMFBS_InMicroMips, { MCK_Imm }, },
5673 { 153 /* addq.ph */, Mips::ADDQ_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5674 { 153 /* addq.ph */, Mips::ADDQ_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5675 { 161 /* addq_s.ph */, Mips::ADDQ_S_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5676 { 161 /* addq_s.ph */, Mips::ADDQ_S_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5677 { 171 /* addq_s.w */, Mips::ADDQ_S_W_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5678 { 171 /* addq_s.w */, Mips::ADDQ_S_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5679 { 180 /* addqh.ph */, Mips::ADDQH_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5680 { 180 /* addqh.ph */, Mips::ADDQH_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5681 { 189 /* addqh.w */, Mips::ADDQH_W_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5682 { 189 /* addqh.w */, Mips::ADDQH_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5683 { 197 /* addqh_r.ph */, Mips::ADDQH_R_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5684 { 197 /* addqh_r.ph */, Mips::ADDQH_R_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5685 { 208 /* addqh_r.w */, Mips::ADDQH_R_W_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5686 { 208 /* addqh_r.w */, Mips::ADDQH_R_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5687 { 218 /* addr.ps */, Mips::ADDR_PS64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMips3D, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5688 { 226 /* adds_a.b */, Mips::ADDS_A_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5689 { 235 /* adds_a.d */, Mips::ADDS_A_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5690 { 244 /* adds_a.h */, Mips::ADDS_A_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5691 { 253 /* adds_a.w */, Mips::ADDS_A_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5692 { 262 /* adds_s.b */, Mips::ADDS_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5693 { 271 /* adds_s.d */, Mips::ADDS_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5694 { 280 /* adds_s.h */, Mips::ADDS_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5695 { 289 /* adds_s.w */, Mips::ADDS_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5696 { 298 /* adds_u.b */, Mips::ADDS_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5697 { 307 /* adds_u.d */, Mips::ADDS_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5698 { 316 /* adds_u.h */, Mips::ADDS_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5699 { 325 /* adds_u.w */, Mips::ADDS_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5700 { 334 /* addsc */, Mips::ADDSC_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5701 { 334 /* addsc */, Mips::ADDSC, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5702 { 340 /* addu */, Mips::ADDU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5703 { 340 /* addu */, Mips::ADDu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5704 { 340 /* addu */, Mips::ADDu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5705 { 340 /* addu */, Mips::ADDiu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
5706 { 340 /* addu */, Mips::ADDiu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
5707 { 340 /* addu */, Mips::AdduRxRyRz16, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs, MCK_CPU16Regs }, },
5708 { 340 /* addu */, Mips::ADDU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5709 { 340 /* addu */, Mips::ADDu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5710 { 340 /* addu */, Mips::ADDu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5711 { 340 /* addu */, Mips::ADDiu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
5712 { 340 /* addu */, Mips::ADDiu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
5713 { 345 /* addu.ph */, Mips::ADDU_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5714 { 345 /* addu.ph */, Mips::ADDU_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5715 { 353 /* addu.qb */, Mips::ADDU_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5716 { 353 /* addu.qb */, Mips::ADDU_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5717 { 361 /* addu16 */, Mips::ADDU16_MM, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__GPRMM16AsmReg1_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, },
5718 { 361 /* addu16 */, Mips::ADDU16_MMR6, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__GPRMM16AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, },
5719 { 368 /* addu_s.ph */, Mips::ADDU_S_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5720 { 368 /* addu_s.ph */, Mips::ADDU_S_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5721 { 378 /* addu_s.qb */, Mips::ADDU_S_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5722 { 378 /* addu_s.qb */, Mips::ADDU_S_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5723 { 388 /* adduh.qb */, Mips::ADDUH_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5724 { 388 /* adduh.qb */, Mips::ADDUH_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5725 { 397 /* adduh_r.qb */, Mips::ADDUH_R_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5726 { 397 /* adduh_r.qb */, Mips::ADDUH_R_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5727 { 408 /* addv.b */, Mips::ADDV_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5728 { 415 /* addv.d */, Mips::ADDV_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5729 { 422 /* addv.h */, Mips::ADDV_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5730 { 429 /* addv.w */, Mips::ADDV_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5731 { 436 /* addvi.b */, Mips::ADDVI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
5732 { 444 /* addvi.d */, Mips::ADDVI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
5733 { 452 /* addvi.h */, Mips::ADDVI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
5734 { 460 /* addvi.w */, Mips::ADDVI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
5735 { 468 /* addwc */, Mips::ADDWC_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5736 { 468 /* addwc */, Mips::ADDWC, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5737 { 474 /* align */, Mips::ALIGN, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__ConstantUImm2_01_3, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm2_0 }, },
5738 { 474 /* align */, Mips::ALIGN_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__ConstantUImm2_01_3, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm2_0 }, },
5739 { 480 /* aluipc */, Mips::ALUIPC, Convert__GPR32AsmReg1_0__SImm161_1, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, },
5740 { 480 /* aluipc */, Mips::ALUIPC_MMR6, Convert__GPR32AsmReg1_0__SImm161_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, },
5741 { 487 /* and */, Mips::AndRxRxRy16, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs }, },
5742 { 487 /* and */, Mips::AND, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5743 { 487 /* and */, Mips::AND_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5744 { 487 /* and */, Mips::AND_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5745 { 487 /* and */, Mips::ANDI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_UImm16 }, },
5746 { 487 /* and */, Mips::ANDi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
5747 { 487 /* and */, Mips::ANDi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
5748 { 487 /* and */, Mips::ANDi64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, AMFBS_HasStdEnc_IsGP64bit_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_Imm }, },
5749 { 487 /* and */, Mips::AND, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5750 { 487 /* and */, Mips::AND_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5751 { 487 /* and */, Mips::AND_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5752 { 487 /* and */, Mips::ANDI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, },
5753 { 487 /* and */, Mips::ANDi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
5754 { 487 /* and */, Mips::ANDi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
5755 { 487 /* and */, Mips::ANDi64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, AMFBS_HasStdEnc_IsGP64bit_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, },
5756 { 491 /* and.v */, Mips::AND_V, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5757 { 497 /* and16 */, Mips::AND16_MM, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Tie0_1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, },
5758 { 497 /* and16 */, Mips::AND16_MMR6, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Tie0_1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, },
5759 { 503 /* andi */, Mips::ANDI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_UImm16 }, },
5760 { 503 /* andi */, Mips::ANDi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_UImm16 }, },
5761 { 503 /* andi */, Mips::ANDi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_UImm16 }, },
5762 { 503 /* andi */, Mips::ANDI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, },
5763 { 503 /* andi */, Mips::ANDi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, },
5764 { 503 /* andi */, Mips::ANDi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, },
5765 { 508 /* andi.b */, Mips::ANDI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm8_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm8_0 }, },
5766 { 515 /* andi16 */, Mips::ANDI16_MM, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Imm1_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_Imm }, },
5767 { 515 /* andi16 */, Mips::ANDI16_MMR6, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Imm1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_Imm }, },
5768 { 522 /* append */, Mips::APPEND_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Tie0_1_1, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
5769 { 522 /* append */, Mips::APPEND, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Tie0_1_1, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
5770 { 529 /* asub_s.b */, Mips::ASUB_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5771 { 538 /* asub_s.d */, Mips::ASUB_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5772 { 547 /* asub_s.h */, Mips::ASUB_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5773 { 556 /* asub_s.w */, Mips::ASUB_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5774 { 565 /* asub_u.b */, Mips::ASUB_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5775 { 574 /* asub_u.d */, Mips::ASUB_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5776 { 583 /* asub_u.h */, Mips::ASUB_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5777 { 592 /* asub_u.w */, Mips::ASUB_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5778 { 601 /* aui */, Mips::AUI, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, },
5779 { 601 /* aui */, Mips::AUI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, },
5780 { 605 /* auipc */, Mips::AUIPC, Convert__GPR32AsmReg1_0__SImm161_1, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, },
5781 { 605 /* auipc */, Mips::AUIPC_MMR6, Convert__GPR32AsmReg1_0__SImm161_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, },
5782 { 611 /* ave_s.b */, Mips::AVE_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5783 { 619 /* ave_s.d */, Mips::AVE_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5784 { 627 /* ave_s.h */, Mips::AVE_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5785 { 635 /* ave_s.w */, Mips::AVE_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5786 { 643 /* ave_u.b */, Mips::AVE_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5787 { 651 /* ave_u.d */, Mips::AVE_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5788 { 659 /* ave_u.h */, Mips::AVE_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5789 { 667 /* ave_u.w */, Mips::AVE_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5790 { 675 /* aver_s.b */, Mips::AVER_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5791 { 684 /* aver_s.d */, Mips::AVER_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5792 { 693 /* aver_s.h */, Mips::AVER_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5793 { 702 /* aver_s.w */, Mips::AVER_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5794 { 711 /* aver_u.b */, Mips::AVER_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5795 { 720 /* aver_u.d */, Mips::AVER_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5796 { 729 /* aver_u.h */, Mips::AVER_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5797 { 738 /* aver_u.w */, Mips::AVER_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5798 { 747 /* b */, Mips::BEQ, Convert__regR0__regR0__JumpTarget1_0, AMFBS_HasStdEnc_NotInMicroMips, { MCK_JumpTarget }, },
5799 { 747 /* b */, Mips::B_MM_Pseudo, Convert__JumpTarget1_0, AMFBS_InMicroMips, { MCK_JumpTarget }, },
5800 { 747 /* b */, Mips::BimmX16, Convert__JumpTarget1_0, AMFBS_InMips16Mode, { MCK_JumpTarget }, },
5801 { 747 /* b */, Mips::B_MMR6_Pseudo, Convert__JumpTarget1_0, AMFBS_None, { MCK_JumpTarget }, },
5802 { 747 /* b */, Mips::Bimm16, Convert__JumpTarget1_0, AMFBS_InMips16Mode, { MCK_JumpTarget, MCK__HASH_, MCK_16, MCK_bit, MCK_inst }, },
5803 { 749 /* b16 */, Mips::BC16_MMR6, Convert__JumpTarget1_0, AMFBS_InMicroMips_HasMips32r6, { MCK_JumpTarget }, },
5804 { 749 /* b16 */, Mips::B16_MM, Convert__JumpTarget1_0, AMFBS_InMicroMips, { MCK_JumpTarget }, },
5805 { 753 /* baddu */, Mips::BADDu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
5806 { 753 /* baddu */, Mips::BADDu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
5807 { 759 /* bal */, Mips::BGEZAL, Convert__regR0__JumpTarget1_0, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_JumpTarget }, },
5808 { 759 /* bal */, Mips::BAL, Convert__JumpTarget1_0, AMFBS_HasStdEnc_HasMips32r6, { MCK_JumpTarget }, },
5809 { 759 /* bal */, Mips::BGEZAL_MM, Convert__regR0__JumpTarget1_0, AMFBS_InMicroMips_NotMips32r6, { MCK_JumpTarget }, },
5810 { 763 /* balc */, Mips::BALC, Convert__JumpTarget1_0, AMFBS_HasStdEnc_HasMips32r6, { MCK_JumpTarget }, },
5811 { 763 /* balc */, Mips::BALC_MMR6, Convert__JumpTarget1_0, AMFBS_InMicroMips_HasMips32r6, { MCK_JumpTarget }, },
5812 { 768 /* balign */, Mips::BALIGN_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm2_01_2__Tie0_1_1, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm2_0 }, },
5813 { 768 /* balign */, Mips::BALIGN, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm2_01_2__Tie0_1_1, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm2_0 }, },
5814 { 775 /* bbit0 */, Mips::BBIT032, Convert__GPR64AsmReg1_0__ConstantUImm5_32_Norm1_1__JumpTarget1_2, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_32_Norm, MCK_JumpTarget }, },
5815 { 775 /* bbit0 */, Mips::BBIT0, Convert__GPR64AsmReg1_0__ConstantUImm5_0_Report_UImm61_1__JumpTarget1_2, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0_Report_UImm6, MCK_JumpTarget }, },
5816 { 781 /* bbit032 */, Mips::BBIT032, Convert__GPR64AsmReg1_0__ConstantUImm5_01_1__JumpTarget1_2, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_JumpTarget }, },
5817 { 789 /* bbit1 */, Mips::BBIT132, Convert__GPR64AsmReg1_0__ConstantUImm5_32_Norm1_1__JumpTarget1_2, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_32_Norm, MCK_JumpTarget }, },
5818 { 789 /* bbit1 */, Mips::BBIT1, Convert__GPR64AsmReg1_0__ConstantUImm5_0_Report_UImm61_1__JumpTarget1_2, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0_Report_UImm6, MCK_JumpTarget }, },
5819 { 795 /* bbit132 */, Mips::BBIT132, Convert__GPR64AsmReg1_0__ConstantUImm5_01_1__JumpTarget1_2, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_JumpTarget }, },
5820 { 803 /* bc */, Mips::BC, Convert__JumpTarget1_0, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_JumpTarget }, },
5821 { 803 /* bc */, Mips::BC_MMR6, Convert__JumpTarget1_0, AMFBS_InMicroMips_HasMips32r6, { MCK_JumpTarget }, },
5822 { 806 /* bc16 */, Mips::BC16_MMR6, Convert__JumpTarget1_0, AMFBS_InMicroMips_HasMips32r6, { MCK_JumpTarget }, },
5823 { 811 /* bc1eqz */, Mips::BC1EQZ, Convert__FGR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_JumpTarget }, },
5824 { 818 /* bc1eqzc */, Mips::BC1EQZC_MMR6, Convert__FGR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_JumpTarget }, },
5825 { 826 /* bc1f */, Mips::BC1F, Convert__regFCC0__JumpTarget1_0, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_JumpTarget }, },
5826 { 826 /* bc1f */, Mips::BC1F_MM, Convert__regFCC0__JumpTarget1_0, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_JumpTarget }, },
5827 { 826 /* bc1f */, Mips::BC1F, Convert__FCCAsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_JumpTarget }, },
5828 { 826 /* bc1f */, Mips::BC1F_MM, Convert__FCCAsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_JumpTarget }, },
5829 { 831 /* bc1fl */, Mips::BC1FL, Convert__regFCC0__JumpTarget1_0, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_JumpTarget }, },
5830 { 831 /* bc1fl */, Mips::BC1FL, Convert__FCCAsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_JumpTarget }, },
5831 { 837 /* bc1nez */, Mips::BC1NEZ, Convert__FGR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_JumpTarget }, },
5832 { 844 /* bc1nezc */, Mips::BC1NEZC_MMR6, Convert__FGR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_JumpTarget }, },
5833 { 852 /* bc1t */, Mips::BC1T, Convert__regFCC0__JumpTarget1_0, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_JumpTarget }, },
5834 { 852 /* bc1t */, Mips::BC1T_MM, Convert__regFCC0__JumpTarget1_0, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_JumpTarget }, },
5835 { 852 /* bc1t */, Mips::BC1T, Convert__FCCAsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_JumpTarget }, },
5836 { 852 /* bc1t */, Mips::BC1T_MM, Convert__FCCAsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_JumpTarget }, },
5837 { 857 /* bc1tl */, Mips::BC1TL, Convert__regFCC0__JumpTarget1_0, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_JumpTarget }, },
5838 { 857 /* bc1tl */, Mips::BC1TL, Convert__FCCAsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_JumpTarget }, },
5839 { 863 /* bc2eqz */, Mips::BC2EQZ, Convert__COP2AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_COP2AsmReg, MCK_JumpTarget }, },
5840 { 870 /* bc2eqzc */, Mips::BC2EQZC_MMR6, Convert__COP2AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_COP2AsmReg, MCK_JumpTarget }, },
5841 { 878 /* bc2nez */, Mips::BC2NEZ, Convert__COP2AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_COP2AsmReg, MCK_JumpTarget }, },
5842 { 885 /* bc2nezc */, Mips::BC2NEZC_MMR6, Convert__COP2AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_COP2AsmReg, MCK_JumpTarget }, },
5843 { 893 /* bclr.b */, Mips::BCLR_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5844 { 900 /* bclr.d */, Mips::BCLR_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5845 { 907 /* bclr.h */, Mips::BCLR_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5846 { 914 /* bclr.w */, Mips::BCLR_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5847 { 921 /* bclri.b */, Mips::BCLRI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, },
5848 { 929 /* bclri.d */, Mips::BCLRI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, },
5849 { 937 /* bclri.h */, Mips::BCLRI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, },
5850 { 945 /* bclri.w */, Mips::BCLRI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
5851 { 953 /* beq */, Mips::BeqImm, Convert__GPR32AsmReg1_0__ConstantImm1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_ConstantImm, MCK_JumpTarget }, },
5852 { 953 /* beq */, Mips::BEQ, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5853 { 953 /* beq */, Mips::BEQ_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5854 { 957 /* beqc */, Mips::BEQC, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5855 { 957 /* beqc */, Mips::BEQC_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5856 { 957 /* beqc */, Mips::BEQC64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_JumpTarget }, },
5857 { 962 /* beql */, Mips::BEQLImmMacro, Convert__GPR32AsmReg1_0__ConstantImm1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_ConstantImm, MCK_JumpTarget }, },
5858 { 962 /* beql */, Mips::BEQL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5859 { 967 /* beqz */, Mips::BeqzRxImmX16, Convert__Reg1_0__JumpTarget1_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_JumpTarget }, },
5860 { 967 /* beqz */, Mips::BEQ, Convert__GPR32AsmReg1_0__regR0__JumpTarget1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5861 { 967 /* beqz */, Mips::BEQ_MM, Convert__GPR32AsmReg1_0__regR0__JumpTarget1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5862 { 967 /* beqz */, Mips::BeqzRxImm16, Convert__Reg1_0__JumpTarget1_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_JumpTarget, MCK__HASH_, MCK_16, MCK_bit, MCK_inst }, },
5863 { 972 /* beqz16 */, Mips::BEQZ16_MM, Convert__GPRMM16AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_JumpTarget }, },
5864 { 972 /* beqz16 */, Mips::BEQZC16_MMR6, Convert__GPRMM16AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_JumpTarget }, },
5865 { 979 /* beqzalc */, Mips::BEQZALC, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5866 { 979 /* beqzalc */, Mips::BEQZALC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5867 { 987 /* beqzc */, Mips::BEQZC, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5868 { 987 /* beqzc */, Mips::BEQZC_MM, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5869 { 987 /* beqzc */, Mips::BEQZC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5870 { 987 /* beqzc */, Mips::BEQZC64, Convert__GPR64AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6, { MCK_GPR64AsmReg, MCK_JumpTarget }, },
5871 { 993 /* beqzc16 */, Mips::BEQZC16_MMR6, Convert__GPRMM16AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_JumpTarget }, },
5872 { 1001 /* beqzl */, Mips::BEQL, Convert__GPR32AsmReg1_0__regR0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips2_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5873 { 1007 /* bge */, Mips::BGEImmMacro, Convert__GPR32AsmReg1_0__ConstantImm1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_ConstantImm, MCK_JumpTarget }, },
5874 { 1007 /* bge */, Mips::BGE, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5875 { 1011 /* bgec */, Mips::BGEC, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5876 { 1011 /* bgec */, Mips::BGEC_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5877 { 1011 /* bgec */, Mips::BGEC64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_JumpTarget }, },
5878 { 1016 /* bgel */, Mips::BGELImmMacro, Convert__GPR32AsmReg1_0__ConstantImm1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_ConstantImm, MCK_JumpTarget }, },
5879 { 1016 /* bgel */, Mips::BGEL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5880 { 1021 /* bgeu */, Mips::BGEUImmMacro, Convert__GPR32AsmReg1_0__ConstantImm1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_ConstantImm, MCK_JumpTarget }, },
5881 { 1021 /* bgeu */, Mips::BGEU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5882 { 1026 /* bgeuc */, Mips::BGEUC, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5883 { 1026 /* bgeuc */, Mips::BGEUC_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5884 { 1026 /* bgeuc */, Mips::BGEUC64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_JumpTarget }, },
5885 { 1032 /* bgeul */, Mips::BGEULImmMacro, Convert__GPR32AsmReg1_0__ConstantImm1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_ConstantImm, MCK_JumpTarget }, },
5886 { 1032 /* bgeul */, Mips::BGEUL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5887 { 1038 /* bgez */, Mips::BGEZ, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5888 { 1038 /* bgez */, Mips::BGEZ_MM, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5889 { 1043 /* bgezal */, Mips::BGEZAL, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5890 { 1043 /* bgezal */, Mips::BGEZAL_MM, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5891 { 1050 /* bgezalc */, Mips::BGEZALC, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5892 { 1050 /* bgezalc */, Mips::BGEZALC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5893 { 1058 /* bgezall */, Mips::BGEZALL, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5894 { 1066 /* bgezals */, Mips::BGEZALS_MM, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5895 { 1074 /* bgezc */, Mips::BGEZC, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5896 { 1074 /* bgezc */, Mips::BGEZC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5897 { 1074 /* bgezc */, Mips::BGEZC64, Convert__GPR64AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6, { MCK_GPR64AsmReg, MCK_JumpTarget }, },
5898 { 1080 /* bgezl */, Mips::BGEZL, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5899 { 1086 /* bgt */, Mips::BGTImmMacro, Convert__GPR32AsmReg1_0__ConstantImm1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_ConstantImm, MCK_JumpTarget }, },
5900 { 1086 /* bgt */, Mips::BGT, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5901 { 1090 /* bgtl */, Mips::BGTLImmMacro, Convert__GPR32AsmReg1_0__ConstantImm1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_ConstantImm, MCK_JumpTarget }, },
5902 { 1090 /* bgtl */, Mips::BGTL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5903 { 1095 /* bgtu */, Mips::BGTUImmMacro, Convert__GPR32AsmReg1_0__ConstantImm1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_ConstantImm, MCK_JumpTarget }, },
5904 { 1095 /* bgtu */, Mips::BGTU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5905 { 1100 /* bgtul */, Mips::BGTULImmMacro, Convert__GPR32AsmReg1_0__ConstantImm1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_ConstantImm, MCK_JumpTarget }, },
5906 { 1100 /* bgtul */, Mips::BGTUL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5907 { 1106 /* bgtz */, Mips::BGTZ, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5908 { 1106 /* bgtz */, Mips::BGTZ_MM, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5909 { 1111 /* bgtzalc */, Mips::BGTZALC, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5910 { 1111 /* bgtzalc */, Mips::BGTZALC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5911 { 1119 /* bgtzc */, Mips::BGTZC, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5912 { 1119 /* bgtzc */, Mips::BGTZC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5913 { 1119 /* bgtzc */, Mips::BGTZC64, Convert__GPR64AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6, { MCK_GPR64AsmReg, MCK_JumpTarget }, },
5914 { 1125 /* bgtzl */, Mips::BGTZL, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5915 { 1131 /* binsl.b */, Mips::BINSL_B, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5916 { 1139 /* binsl.d */, Mips::BINSL_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5917 { 1147 /* binsl.h */, Mips::BINSL_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5918 { 1155 /* binsl.w */, Mips::BINSL_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5919 { 1163 /* binsli.b */, Mips::BINSLI_B, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, },
5920 { 1172 /* binsli.d */, Mips::BINSLI_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm6_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, },
5921 { 1181 /* binsli.h */, Mips::BINSLI_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm4_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, },
5922 { 1190 /* binsli.w */, Mips::BINSLI_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
5923 { 1199 /* binsr.b */, Mips::BINSR_B, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5924 { 1207 /* binsr.d */, Mips::BINSR_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5925 { 1215 /* binsr.h */, Mips::BINSR_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5926 { 1223 /* binsr.w */, Mips::BINSR_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5927 { 1231 /* binsri.b */, Mips::BINSRI_B, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, },
5928 { 1240 /* binsri.d */, Mips::BINSRI_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm6_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, },
5929 { 1249 /* binsri.h */, Mips::BINSRI_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm4_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, },
5930 { 1258 /* binsri.w */, Mips::BINSRI_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
5931 { 1267 /* bitrev */, Mips::BITREV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5932 { 1267 /* bitrev */, Mips::BITREV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5933 { 1274 /* bitswap */, Mips::BITSWAP, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5934 { 1274 /* bitswap */, Mips::BITSWAP_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5935 { 1282 /* ble */, Mips::BLEImmMacro, Convert__GPR32AsmReg1_0__ConstantImm1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_ConstantImm, MCK_JumpTarget }, },
5936 { 1282 /* ble */, Mips::BLE, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5937 { 1286 /* blel */, Mips::BLELImmMacro, Convert__GPR32AsmReg1_0__ConstantImm1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_ConstantImm, MCK_JumpTarget }, },
5938 { 1286 /* blel */, Mips::BLEL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5939 { 1291 /* bleu */, Mips::BLEUImmMacro, Convert__GPR32AsmReg1_0__ConstantImm1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_ConstantImm, MCK_JumpTarget }, },
5940 { 1291 /* bleu */, Mips::BLEU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5941 { 1296 /* bleul */, Mips::BLEULImmMacro, Convert__GPR32AsmReg1_0__ConstantImm1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_ConstantImm, MCK_JumpTarget }, },
5942 { 1296 /* bleul */, Mips::BLEUL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5943 { 1302 /* blez */, Mips::BLEZ, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5944 { 1302 /* blez */, Mips::BLEZ_MM, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5945 { 1307 /* blezalc */, Mips::BLEZALC, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5946 { 1307 /* blezalc */, Mips::BLEZALC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5947 { 1315 /* blezc */, Mips::BLEZC, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5948 { 1315 /* blezc */, Mips::BLEZC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5949 { 1315 /* blezc */, Mips::BLEZC64, Convert__GPR64AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6, { MCK_GPR64AsmReg, MCK_JumpTarget }, },
5950 { 1321 /* blezl */, Mips::BLEZL, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5951 { 1327 /* blt */, Mips::BLTImmMacro, Convert__GPR32AsmReg1_0__ConstantImm1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_ConstantImm, MCK_JumpTarget }, },
5952 { 1327 /* blt */, Mips::BLT, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5953 { 1331 /* bltc */, Mips::BLTC, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5954 { 1331 /* bltc */, Mips::BLTC_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5955 { 1331 /* bltc */, Mips::BLTC64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_JumpTarget }, },
5956 { 1336 /* bltl */, Mips::BLTLImmMacro, Convert__GPR32AsmReg1_0__ConstantImm1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_ConstantImm, MCK_JumpTarget }, },
5957 { 1336 /* bltl */, Mips::BLTL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5958 { 1341 /* bltu */, Mips::BLTUImmMacro, Convert__GPR32AsmReg1_0__ConstantImm1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_ConstantImm, MCK_JumpTarget }, },
5959 { 1341 /* bltu */, Mips::BLTU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5960 { 1346 /* bltuc */, Mips::BLTUC, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5961 { 1346 /* bltuc */, Mips::BLTUC_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5962 { 1346 /* bltuc */, Mips::BLTUC64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_JumpTarget }, },
5963 { 1352 /* bltul */, Mips::BLTULImmMacro, Convert__GPR32AsmReg1_0__ConstantImm1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_ConstantImm, MCK_JumpTarget }, },
5964 { 1352 /* bltul */, Mips::BLTUL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5965 { 1358 /* bltz */, Mips::BLTZ, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5966 { 1358 /* bltz */, Mips::BLTZ_MM, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5967 { 1363 /* bltzal */, Mips::BLTZAL, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5968 { 1363 /* bltzal */, Mips::BLTZAL_MM, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5969 { 1370 /* bltzalc */, Mips::BLTZALC, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5970 { 1370 /* bltzalc */, Mips::BLTZALC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5971 { 1378 /* bltzall */, Mips::BLTZALL, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5972 { 1386 /* bltzals */, Mips::BLTZALS_MM, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5973 { 1394 /* bltzc */, Mips::BLTZC, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5974 { 1394 /* bltzc */, Mips::BLTZC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5975 { 1394 /* bltzc */, Mips::BLTZC64, Convert__GPR64AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6, { MCK_GPR64AsmReg, MCK_JumpTarget }, },
5976 { 1400 /* bltzl */, Mips::BLTZL, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5977 { 1406 /* bmnz.v */, Mips::BMNZ_V, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5978 { 1413 /* bmnzi.b */, Mips::BMNZI_B, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm8_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm8_0 }, },
5979 { 1421 /* bmz.v */, Mips::BMZ_V, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5980 { 1427 /* bmzi.b */, Mips::BMZI_B, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm8_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm8_0 }, },
5981 { 1434 /* bne */, Mips::BneImm, Convert__GPR32AsmReg1_0__ConstantImm1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_ConstantImm, MCK_JumpTarget }, },
5982 { 1434 /* bne */, Mips::BNE, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5983 { 1434 /* bne */, Mips::BNE_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5984 { 1438 /* bnec */, Mips::BNEC, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5985 { 1438 /* bnec */, Mips::BNEC_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5986 { 1438 /* bnec */, Mips::BNEC64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_JumpTarget }, },
5987 { 1443 /* bneg.b */, Mips::BNEG_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5988 { 1450 /* bneg.d */, Mips::BNEG_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5989 { 1457 /* bneg.h */, Mips::BNEG_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5990 { 1464 /* bneg.w */, Mips::BNEG_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5991 { 1471 /* bnegi.b */, Mips::BNEGI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, },
5992 { 1479 /* bnegi.d */, Mips::BNEGI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, },
5993 { 1487 /* bnegi.h */, Mips::BNEGI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, },
5994 { 1495 /* bnegi.w */, Mips::BNEGI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
5995 { 1503 /* bnel */, Mips::BNELImmMacro, Convert__GPR32AsmReg1_0__ConstantImm1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_ConstantImm, MCK_JumpTarget }, },
5996 { 1503 /* bnel */, Mips::BNEL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5997 { 1508 /* bnez */, Mips::BnezRxImmX16, Convert__Reg1_0__JumpTarget1_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_JumpTarget }, },
5998 { 1508 /* bnez */, Mips::BNE, Convert__GPR32AsmReg1_0__regR0__JumpTarget1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5999 { 1508 /* bnez */, Mips::BNE_MM, Convert__GPR32AsmReg1_0__regR0__JumpTarget1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
6000 { 1508 /* bnez */, Mips::BnezRxImm16, Convert__Reg1_0__JumpTarget1_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_JumpTarget, MCK__HASH_, MCK_16, MCK_bit, MCK_inst }, },
6001 { 1513 /* bnez16 */, Mips::BNEZ16_MM, Convert__GPRMM16AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_JumpTarget }, },
6002 { 1513 /* bnez16 */, Mips::BNEZC16_MMR6, Convert__GPRMM16AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_JumpTarget }, },
6003 { 1520 /* bnezalc */, Mips::BNEZALC, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
6004 { 1520 /* bnezalc */, Mips::BNEZALC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
6005 { 1528 /* bnezc */, Mips::BNEZC, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
6006 { 1528 /* bnezc */, Mips::BNEZC_MM, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
6007 { 1528 /* bnezc */, Mips::BNEZC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
6008 { 1528 /* bnezc */, Mips::BNEZC64, Convert__GPR64AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6, { MCK_GPR64AsmReg, MCK_JumpTarget }, },
6009 { 1534 /* bnezc16 */, Mips::BNEZC16_MMR6, Convert__GPRMM16AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_JumpTarget }, },
6010 { 1542 /* bnezl */, Mips::BNEL, Convert__GPR32AsmReg1_0__regR0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips2_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
6011 { 1548 /* bnvc */, Mips::BNVC, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
6012 { 1548 /* bnvc */, Mips::BNVC_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
6013 { 1553 /* bnz.b */, Mips::BNZ_B, Convert__MSA128AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_JumpTarget }, },
6014 { 1559 /* bnz.d */, Mips::BNZ_D, Convert__MSA128AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_JumpTarget }, },
6015 { 1565 /* bnz.h */, Mips::BNZ_H, Convert__MSA128AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_JumpTarget }, },
6016 { 1571 /* bnz.v */, Mips::BNZ_V, Convert__MSA128AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_JumpTarget }, },
6017 { 1577 /* bnz.w */, Mips::BNZ_W, Convert__MSA128AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_JumpTarget }, },
6018 { 1583 /* bovc */, Mips::BOVC, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
6019 { 1583 /* bovc */, Mips::BOVC_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
6020 { 1588 /* bposge32 */, Mips::BPOSGE32_MM, Convert__JumpTarget1_0, AMFBS_InMicroMips_NotMips32r6_HasDSP, { MCK_JumpTarget }, },
6021 { 1588 /* bposge32 */, Mips::BPOSGE32, Convert__JumpTarget1_0, AMFBS_HasDSP_NotInMicroMips, { MCK_JumpTarget }, },
6022 { 1597 /* bposge32c */, Mips::BPOSGE32C_MMR3, Convert__JumpTarget1_0, AMFBS_InMicroMips_HasDSPR3, { MCK_JumpTarget }, },
6023 { 1607 /* break */, Mips::BREAK, Convert__imm_95_0__imm_95_0, AMFBS_HasStdEnc_NotInMicroMips, { }, },
6024 { 1607 /* break */, Mips::BREAK_MM, Convert__imm_95_0__imm_95_0, AMFBS_InMicroMips, { }, },
6025 { 1607 /* break */, Mips::Break16, Convert_NoOperands, AMFBS_InMips16Mode, { MCK_0 }, },
6026 { 1607 /* break */, Mips::BREAK, Convert__ConstantUImm10_01_0__imm_95_0, AMFBS_HasStdEnc_NotInMicroMips, { MCK_ConstantUImm10_0 }, },
6027 { 1607 /* break */, Mips::BREAK_MM, Convert__ConstantUImm10_01_0__imm_95_0, AMFBS_InMicroMips, { MCK_ConstantUImm10_0 }, },
6028 { 1607 /* break */, Mips::BREAK, Convert__ConstantUImm10_01_0__ConstantUImm10_01_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_ConstantUImm10_0, MCK_ConstantUImm10_0 }, },
6029 { 1607 /* break */, Mips::BREAK_MMR6, Convert__ConstantUImm10_01_0__ConstantUImm10_01_1, AMFBS_InMicroMips_HasMips32r6, { MCK_ConstantUImm10_0, MCK_ConstantUImm10_0 }, },
6030 { 1607 /* break */, Mips::BREAK_MM, Convert__ConstantUImm10_01_0__ConstantUImm10_01_1, AMFBS_InMicroMips, { MCK_ConstantUImm10_0, MCK_ConstantUImm10_0 }, },
6031 { 1613 /* break16 */, Mips::BREAK16_MM, Convert__ConstantUImm4_01_0, AMFBS_InMicroMips_NotMips32r6, { MCK_ConstantUImm4_0 }, },
6032 { 1613 /* break16 */, Mips::BREAK16_MMR6, Convert__ConstantUImm4_01_0, AMFBS_InMicroMips_HasMips32r6, { MCK_ConstantUImm4_0 }, },
6033 { 1621 /* bsel.v */, Mips::BSEL_V, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6034 { 1628 /* bseli.b */, Mips::BSELI_B, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm8_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm8_0 }, },
6035 { 1636 /* bset.b */, Mips::BSET_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6036 { 1643 /* bset.d */, Mips::BSET_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6037 { 1650 /* bset.h */, Mips::BSET_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6038 { 1657 /* bset.w */, Mips::BSET_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6039 { 1664 /* bseti.b */, Mips::BSETI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, },
6040 { 1672 /* bseti.d */, Mips::BSETI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, },
6041 { 1680 /* bseti.h */, Mips::BSETI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, },
6042 { 1688 /* bseti.w */, Mips::BSETI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
6043 { 1696 /* bteqz */, Mips::BteqzX16, Convert__SImm161_0, AMFBS_InMips16Mode, { MCK_SImm16 }, },
6044 { 1696 /* bteqz */, Mips::Bteqz16, Convert__SImm161_0, AMFBS_InMips16Mode, { MCK_SImm16, MCK__HASH_, MCK_16, MCK_bit, MCK_inst }, },
6045 { 1702 /* btnez */, Mips::BtnezX16, Convert__SImm161_0, AMFBS_InMips16Mode, { MCK_SImm16 }, },
6046 { 1702 /* btnez */, Mips::Btnez16, Convert__SImm161_0, AMFBS_InMips16Mode, { MCK_SImm16, MCK__HASH_, MCK_16, MCK_bit, MCK_inst }, },
6047 { 1708 /* bz.b */, Mips::BZ_B, Convert__MSA128AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_JumpTarget }, },
6048 { 1713 /* bz.d */, Mips::BZ_D, Convert__MSA128AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_JumpTarget }, },
6049 { 1718 /* bz.h */, Mips::BZ_H, Convert__MSA128AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_JumpTarget }, },
6050 { 1723 /* bz.v */, Mips::BZ_V, Convert__MSA128AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_JumpTarget }, },
6051 { 1728 /* bz.w */, Mips::BZ_W, Convert__MSA128AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_JumpTarget }, },
6052 { 1733 /* c.eq.d */, Mips::C_EQ_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6053 { 1733 /* c.eq.d */, Mips::C_EQ_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6054 { 1733 /* c.eq.d */, Mips::C_EQ_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6055 { 1733 /* c.eq.d */, Mips::C_EQ_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6056 { 1733 /* c.eq.d */, Mips::C_EQ_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6057 { 1733 /* c.eq.d */, Mips::C_EQ_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6058 { 1733 /* c.eq.d */, Mips::C_EQ_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6059 { 1733 /* c.eq.d */, Mips::C_EQ_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6060 { 1740 /* c.eq.s */, Mips::C_EQ_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6061 { 1740 /* c.eq.s */, Mips::C_EQ_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6062 { 1740 /* c.eq.s */, Mips::C_EQ_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6063 { 1740 /* c.eq.s */, Mips::C_EQ_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6064 { 1747 /* c.f.d */, Mips::C_F_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6065 { 1747 /* c.f.d */, Mips::C_F_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6066 { 1747 /* c.f.d */, Mips::C_F_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6067 { 1747 /* c.f.d */, Mips::C_F_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6068 { 1747 /* c.f.d */, Mips::C_F_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6069 { 1747 /* c.f.d */, Mips::C_F_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6070 { 1747 /* c.f.d */, Mips::C_F_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6071 { 1747 /* c.f.d */, Mips::C_F_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6072 { 1753 /* c.f.s */, Mips::C_F_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6073 { 1753 /* c.f.s */, Mips::C_F_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6074 { 1753 /* c.f.s */, Mips::C_F_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6075 { 1753 /* c.f.s */, Mips::C_F_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6076 { 1759 /* c.le.d */, Mips::C_LE_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6077 { 1759 /* c.le.d */, Mips::C_LE_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6078 { 1759 /* c.le.d */, Mips::C_LE_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6079 { 1759 /* c.le.d */, Mips::C_LE_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6080 { 1759 /* c.le.d */, Mips::C_LE_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6081 { 1759 /* c.le.d */, Mips::C_LE_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6082 { 1759 /* c.le.d */, Mips::C_LE_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6083 { 1759 /* c.le.d */, Mips::C_LE_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6084 { 1766 /* c.le.s */, Mips::C_LE_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6085 { 1766 /* c.le.s */, Mips::C_LE_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6086 { 1766 /* c.le.s */, Mips::C_LE_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6087 { 1766 /* c.le.s */, Mips::C_LE_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6088 { 1773 /* c.lt.d */, Mips::C_LT_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6089 { 1773 /* c.lt.d */, Mips::C_LT_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6090 { 1773 /* c.lt.d */, Mips::C_LT_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6091 { 1773 /* c.lt.d */, Mips::C_LT_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6092 { 1773 /* c.lt.d */, Mips::C_LT_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6093 { 1773 /* c.lt.d */, Mips::C_LT_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6094 { 1773 /* c.lt.d */, Mips::C_LT_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6095 { 1773 /* c.lt.d */, Mips::C_LT_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6096 { 1780 /* c.lt.s */, Mips::C_LT_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6097 { 1780 /* c.lt.s */, Mips::C_LT_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6098 { 1780 /* c.lt.s */, Mips::C_LT_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6099 { 1780 /* c.lt.s */, Mips::C_LT_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6100 { 1787 /* c.nge.d */, Mips::C_NGE_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6101 { 1787 /* c.nge.d */, Mips::C_NGE_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6102 { 1787 /* c.nge.d */, Mips::C_NGE_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6103 { 1787 /* c.nge.d */, Mips::C_NGE_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6104 { 1787 /* c.nge.d */, Mips::C_NGE_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6105 { 1787 /* c.nge.d */, Mips::C_NGE_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6106 { 1787 /* c.nge.d */, Mips::C_NGE_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6107 { 1787 /* c.nge.d */, Mips::C_NGE_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6108 { 1795 /* c.nge.s */, Mips::C_NGE_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6109 { 1795 /* c.nge.s */, Mips::C_NGE_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6110 { 1795 /* c.nge.s */, Mips::C_NGE_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6111 { 1795 /* c.nge.s */, Mips::C_NGE_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6112 { 1803 /* c.ngl.d */, Mips::C_NGL_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6113 { 1803 /* c.ngl.d */, Mips::C_NGL_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6114 { 1803 /* c.ngl.d */, Mips::C_NGL_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6115 { 1803 /* c.ngl.d */, Mips::C_NGL_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6116 { 1803 /* c.ngl.d */, Mips::C_NGL_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6117 { 1803 /* c.ngl.d */, Mips::C_NGL_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6118 { 1803 /* c.ngl.d */, Mips::C_NGL_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6119 { 1803 /* c.ngl.d */, Mips::C_NGL_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6120 { 1811 /* c.ngl.s */, Mips::C_NGL_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6121 { 1811 /* c.ngl.s */, Mips::C_NGL_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6122 { 1811 /* c.ngl.s */, Mips::C_NGL_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6123 { 1811 /* c.ngl.s */, Mips::C_NGL_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6124 { 1819 /* c.ngle.d */, Mips::C_NGLE_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6125 { 1819 /* c.ngle.d */, Mips::C_NGLE_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6126 { 1819 /* c.ngle.d */, Mips::C_NGLE_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6127 { 1819 /* c.ngle.d */, Mips::C_NGLE_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6128 { 1819 /* c.ngle.d */, Mips::C_NGLE_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6129 { 1819 /* c.ngle.d */, Mips::C_NGLE_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6130 { 1819 /* c.ngle.d */, Mips::C_NGLE_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6131 { 1819 /* c.ngle.d */, Mips::C_NGLE_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6132 { 1828 /* c.ngle.s */, Mips::C_NGLE_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6133 { 1828 /* c.ngle.s */, Mips::C_NGLE_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6134 { 1828 /* c.ngle.s */, Mips::C_NGLE_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6135 { 1828 /* c.ngle.s */, Mips::C_NGLE_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6136 { 1837 /* c.ngt.d */, Mips::C_NGT_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6137 { 1837 /* c.ngt.d */, Mips::C_NGT_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6138 { 1837 /* c.ngt.d */, Mips::C_NGT_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6139 { 1837 /* c.ngt.d */, Mips::C_NGT_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6140 { 1837 /* c.ngt.d */, Mips::C_NGT_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6141 { 1837 /* c.ngt.d */, Mips::C_NGT_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6142 { 1837 /* c.ngt.d */, Mips::C_NGT_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6143 { 1837 /* c.ngt.d */, Mips::C_NGT_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6144 { 1845 /* c.ngt.s */, Mips::C_NGT_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6145 { 1845 /* c.ngt.s */, Mips::C_NGT_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6146 { 1845 /* c.ngt.s */, Mips::C_NGT_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6147 { 1845 /* c.ngt.s */, Mips::C_NGT_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6148 { 1853 /* c.ole.d */, Mips::C_OLE_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6149 { 1853 /* c.ole.d */, Mips::C_OLE_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6150 { 1853 /* c.ole.d */, Mips::C_OLE_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6151 { 1853 /* c.ole.d */, Mips::C_OLE_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6152 { 1853 /* c.ole.d */, Mips::C_OLE_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6153 { 1853 /* c.ole.d */, Mips::C_OLE_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6154 { 1853 /* c.ole.d */, Mips::C_OLE_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6155 { 1853 /* c.ole.d */, Mips::C_OLE_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6156 { 1861 /* c.ole.s */, Mips::C_OLE_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6157 { 1861 /* c.ole.s */, Mips::C_OLE_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6158 { 1861 /* c.ole.s */, Mips::C_OLE_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6159 { 1861 /* c.ole.s */, Mips::C_OLE_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6160 { 1869 /* c.olt.d */, Mips::C_OLT_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6161 { 1869 /* c.olt.d */, Mips::C_OLT_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6162 { 1869 /* c.olt.d */, Mips::C_OLT_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6163 { 1869 /* c.olt.d */, Mips::C_OLT_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6164 { 1869 /* c.olt.d */, Mips::C_OLT_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6165 { 1869 /* c.olt.d */, Mips::C_OLT_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6166 { 1869 /* c.olt.d */, Mips::C_OLT_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6167 { 1869 /* c.olt.d */, Mips::C_OLT_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6168 { 1877 /* c.olt.s */, Mips::C_OLT_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6169 { 1877 /* c.olt.s */, Mips::C_OLT_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6170 { 1877 /* c.olt.s */, Mips::C_OLT_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6171 { 1877 /* c.olt.s */, Mips::C_OLT_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6172 { 1885 /* c.seq.d */, Mips::C_SEQ_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6173 { 1885 /* c.seq.d */, Mips::C_SEQ_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6174 { 1885 /* c.seq.d */, Mips::C_SEQ_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6175 { 1885 /* c.seq.d */, Mips::C_SEQ_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6176 { 1885 /* c.seq.d */, Mips::C_SEQ_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6177 { 1885 /* c.seq.d */, Mips::C_SEQ_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6178 { 1885 /* c.seq.d */, Mips::C_SEQ_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6179 { 1885 /* c.seq.d */, Mips::C_SEQ_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6180 { 1893 /* c.seq.s */, Mips::C_SEQ_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6181 { 1893 /* c.seq.s */, Mips::C_SEQ_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6182 { 1893 /* c.seq.s */, Mips::C_SEQ_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6183 { 1893 /* c.seq.s */, Mips::C_SEQ_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6184 { 1901 /* c.sf.d */, Mips::C_SF_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6185 { 1901 /* c.sf.d */, Mips::C_SF_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6186 { 1901 /* c.sf.d */, Mips::C_SF_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6187 { 1901 /* c.sf.d */, Mips::C_SF_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6188 { 1901 /* c.sf.d */, Mips::C_SF_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6189 { 1901 /* c.sf.d */, Mips::C_SF_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6190 { 1901 /* c.sf.d */, Mips::C_SF_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6191 { 1901 /* c.sf.d */, Mips::C_SF_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6192 { 1908 /* c.sf.s */, Mips::C_SF_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6193 { 1908 /* c.sf.s */, Mips::C_SF_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6194 { 1908 /* c.sf.s */, Mips::C_SF_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6195 { 1908 /* c.sf.s */, Mips::C_SF_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6196 { 1915 /* c.ueq.d */, Mips::C_UEQ_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6197 { 1915 /* c.ueq.d */, Mips::C_UEQ_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6198 { 1915 /* c.ueq.d */, Mips::C_UEQ_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6199 { 1915 /* c.ueq.d */, Mips::C_UEQ_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6200 { 1915 /* c.ueq.d */, Mips::C_UEQ_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6201 { 1915 /* c.ueq.d */, Mips::C_UEQ_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6202 { 1915 /* c.ueq.d */, Mips::C_UEQ_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6203 { 1915 /* c.ueq.d */, Mips::C_UEQ_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6204 { 1923 /* c.ueq.s */, Mips::C_UEQ_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6205 { 1923 /* c.ueq.s */, Mips::C_UEQ_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6206 { 1923 /* c.ueq.s */, Mips::C_UEQ_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6207 { 1923 /* c.ueq.s */, Mips::C_UEQ_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6208 { 1931 /* c.ule.d */, Mips::C_ULE_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6209 { 1931 /* c.ule.d */, Mips::C_ULE_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6210 { 1931 /* c.ule.d */, Mips::C_ULE_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6211 { 1931 /* c.ule.d */, Mips::C_ULE_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6212 { 1931 /* c.ule.d */, Mips::C_ULE_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6213 { 1931 /* c.ule.d */, Mips::C_ULE_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6214 { 1931 /* c.ule.d */, Mips::C_ULE_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6215 { 1931 /* c.ule.d */, Mips::C_ULE_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6216 { 1939 /* c.ule.s */, Mips::C_ULE_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6217 { 1939 /* c.ule.s */, Mips::C_ULE_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6218 { 1939 /* c.ule.s */, Mips::C_ULE_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6219 { 1939 /* c.ule.s */, Mips::C_ULE_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6220 { 1947 /* c.ult.d */, Mips::C_ULT_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6221 { 1947 /* c.ult.d */, Mips::C_ULT_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6222 { 1947 /* c.ult.d */, Mips::C_ULT_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6223 { 1947 /* c.ult.d */, Mips::C_ULT_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6224 { 1947 /* c.ult.d */, Mips::C_ULT_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6225 { 1947 /* c.ult.d */, Mips::C_ULT_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6226 { 1947 /* c.ult.d */, Mips::C_ULT_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6227 { 1947 /* c.ult.d */, Mips::C_ULT_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6228 { 1955 /* c.ult.s */, Mips::C_ULT_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6229 { 1955 /* c.ult.s */, Mips::C_ULT_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6230 { 1955 /* c.ult.s */, Mips::C_ULT_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6231 { 1955 /* c.ult.s */, Mips::C_ULT_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6232 { 1963 /* c.un.d */, Mips::C_UN_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6233 { 1963 /* c.un.d */, Mips::C_UN_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6234 { 1963 /* c.un.d */, Mips::C_UN_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6235 { 1963 /* c.un.d */, Mips::C_UN_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6236 { 1963 /* c.un.d */, Mips::C_UN_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6237 { 1963 /* c.un.d */, Mips::C_UN_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6238 { 1963 /* c.un.d */, Mips::C_UN_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6239 { 1963 /* c.un.d */, Mips::C_UN_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6240 { 1970 /* c.un.s */, Mips::C_UN_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6241 { 1970 /* c.un.s */, Mips::C_UN_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6242 { 1970 /* c.un.s */, Mips::C_UN_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6243 { 1970 /* c.un.s */, Mips::C_UN_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6244 { 1977 /* cache */, Mips::CACHE_R6, Convert__PtrReg1_3__SImmOffset9_01_1__ConstantUImm5_01_0, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_ConstantUImm5_0, MCK_SImmOffset9_0, MCK__40_, MCK_PtrReg, MCK__41_ }, },
6245 { 1977 /* cache */, Mips::CACHE, Convert__PtrReg1_3__SImmPtr1_1__ConstantUImm5_01_0, AMFBS_HasStdEnc_HasMips3_32_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_ConstantUImm5_0, MCK_SImmPtr, MCK__40_, MCK_PtrReg, MCK__41_ }, },
6246 { 1977 /* cache */, Mips::CACHE_MM, Convert__PtrReg1_3__AnyOffset1_1__ConstantUImm5_01_0, AMFBS_InMicroMips_NotMips32r6, { MCK_ConstantUImm5_0, MCK_AnyOffset, MCK__40_, MCK_PtrReg, MCK__41_ }, },
6247 { 1977 /* cache */, Mips::CACHE_MMR6, Convert__PtrReg1_3__AnyOffset1_1__ConstantUImm5_01_0, AMFBS_InMicroMips_HasMips32r6, { MCK_ConstantUImm5_0, MCK_AnyOffset, MCK__40_, MCK_PtrReg, MCK__41_ }, },
6248 { 1983 /* cachee */, Mips::CACHEE, Convert__PtrReg1_3__SImmOffset9_01_1__ConstantUImm5_01_0, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, { MCK_ConstantUImm5_0, MCK_SImmOffset9_0, MCK__40_, MCK_PtrReg, MCK__41_ }, },
6249 { 1983 /* cachee */, Mips::CACHEE_MM, Convert__PtrReg1_3__SImmOffset9_01_1__ConstantUImm5_01_0, AMFBS_InMicroMips_HasEVA, { MCK_ConstantUImm5_0, MCK_SImmOffset9_0, MCK__40_, MCK_PtrReg, MCK__41_ }, },
6250 { 1990 /* ceil.l.d */, Mips::CEIL_L_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips3_32_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6251 { 1990 /* ceil.l.d */, Mips::CEIL_L_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6252 { 1999 /* ceil.l.s */, Mips::CEIL_L_S, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, },
6253 { 1999 /* ceil.l.s */, Mips::CEIL_L_S_MMR6, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, },
6254 { 2008 /* ceil.w.d */, Mips::CEIL_W_D32, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, },
6255 { 2008 /* ceil.w.d */, Mips::CEIL_W_MM, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, },
6256 { 2008 /* ceil.w.d */, Mips::CEIL_W_D_MMR6, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, },
6257 { 2008 /* ceil.w.d */, Mips::CEIL_W_D64, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg }, },
6258 { 2017 /* ceil.w.s */, Mips::CEIL_W_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_HasMips2_NotR5900_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6259 { 2017 /* ceil.w.s */, Mips::CEIL_W_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6260 { 2017 /* ceil.w.s */, Mips::CEIL_W_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6261 { 2026 /* ceq.b */, Mips::CEQ_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6262 { 2032 /* ceq.d */, Mips::CEQ_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6263 { 2038 /* ceq.h */, Mips::CEQ_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6264 { 2044 /* ceq.w */, Mips::CEQ_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6265 { 2050 /* ceqi.b */, Mips::CEQI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
6266 { 2057 /* ceqi.d */, Mips::CEQI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
6267 { 2064 /* ceqi.h */, Mips::CEQI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
6268 { 2071 /* ceqi.w */, Mips::CEQI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
6269 { 2078 /* cfc1 */, Mips::CFC1, Convert__GPR32AsmReg1_0__CCRAsmReg1_1, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, { MCK_GPR32AsmReg, MCK_CCRAsmReg }, },
6270 { 2078 /* cfc1 */, Mips::CFC1_MM, Convert__GPR32AsmReg1_0__CCRAsmReg1_1, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_CCRAsmReg }, },
6271 { 2083 /* cfc2 */, Mips::CFC2_MM, Convert__GPR32AsmReg1_0__COP2AsmReg1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_COP2AsmReg }, },
6272 { 2088 /* cfcmsa */, Mips::CFCMSA, Convert__GPR32AsmReg1_0__MSACtrlAsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_GPR32AsmReg, MCK_MSACtrlAsmReg }, },
6273 { 2095 /* cftc1 */, Mips::CFTC1, Convert__GPR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasMT, { MCK_GPR32AsmReg, MCK_FGR32AsmReg }, },
6274 { 2101 /* cins */, Mips::CINS, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1__ConstantUImm5_01_2, AMFBS_HasMips64_HasCnMips_NotInMicroMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_0 }, },
6275 { 2101 /* cins */, Mips::CINS32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_32_Norm1_1__ConstantUImm5_01_2, AMFBS_HasMips64_HasCnMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_32_Norm, MCK_ConstantUImm5_0 }, },
6276 { 2101 /* cins */, Mips::CINS, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_01_3, AMFBS_HasMips64_HasCnMips_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_0 }, },
6277 { 2101 /* cins */, Mips::CINS32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_32_Norm1_2__ConstantUImm5_01_3, AMFBS_HasMips64_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_32_Norm, MCK_ConstantUImm5_0 }, },
6278 { 2106 /* cins32 */, Mips::CINS32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1__ConstantUImm5_01_2, AMFBS_HasMips64_HasCnMips_NotInMicroMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_0 }, },
6279 { 2106 /* cins32 */, Mips::CINS32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_01_3, AMFBS_HasMips64_HasCnMips_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_0 }, },
6280 { 2113 /* class.d */, Mips::CLASS_D, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6281 { 2113 /* class.d */, Mips::CLASS_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6282 { 2121 /* class.s */, Mips::CLASS_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6283 { 2121 /* class.s */, Mips::CLASS_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6284 { 2129 /* cle_s.b */, Mips::CLE_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6285 { 2137 /* cle_s.d */, Mips::CLE_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6286 { 2145 /* cle_s.h */, Mips::CLE_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6287 { 2153 /* cle_s.w */, Mips::CLE_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6288 { 2161 /* cle_u.b */, Mips::CLE_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6289 { 2169 /* cle_u.d */, Mips::CLE_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6290 { 2177 /* cle_u.h */, Mips::CLE_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6291 { 2185 /* cle_u.w */, Mips::CLE_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6292 { 2193 /* clei_s.b */, Mips::CLEI_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
6293 { 2202 /* clei_s.d */, Mips::CLEI_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
6294 { 2211 /* clei_s.h */, Mips::CLEI_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
6295 { 2220 /* clei_s.w */, Mips::CLEI_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
6296 { 2229 /* clei_u.b */, Mips::CLEI_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
6297 { 2238 /* clei_u.d */, Mips::CLEI_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
6298 { 2247 /* clei_u.h */, Mips::CLEI_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
6299 { 2256 /* clei_u.w */, Mips::CLEI_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
6300 { 2265 /* clo */, Mips::CLO, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6301 { 2265 /* clo */, Mips::CLO_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6302 { 2265 /* clo */, Mips::CLO_R6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6303 { 2265 /* clo */, Mips::CLO_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6304 { 2269 /* clt_s.b */, Mips::CLT_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6305 { 2277 /* clt_s.d */, Mips::CLT_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6306 { 2285 /* clt_s.h */, Mips::CLT_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6307 { 2293 /* clt_s.w */, Mips::CLT_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6308 { 2301 /* clt_u.b */, Mips::CLT_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6309 { 2309 /* clt_u.d */, Mips::CLT_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6310 { 2317 /* clt_u.h */, Mips::CLT_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6311 { 2325 /* clt_u.w */, Mips::CLT_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6312 { 2333 /* clti_s.b */, Mips::CLTI_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
6313 { 2342 /* clti_s.d */, Mips::CLTI_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
6314 { 2351 /* clti_s.h */, Mips::CLTI_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
6315 { 2360 /* clti_s.w */, Mips::CLTI_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
6316 { 2369 /* clti_u.b */, Mips::CLTI_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
6317 { 2378 /* clti_u.d */, Mips::CLTI_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
6318 { 2387 /* clti_u.h */, Mips::CLTI_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
6319 { 2396 /* clti_u.w */, Mips::CLTI_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
6320 { 2405 /* clz */, Mips::CLZ, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6321 { 2405 /* clz */, Mips::CLZ_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6322 { 2405 /* clz */, Mips::CLZ_R6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6323 { 2405 /* clz */, Mips::CLZ_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6324 { 2409 /* cmp */, Mips::CmpRxRy16, Convert__Reg1_0__Reg1_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs }, },
6325 { 2413 /* cmp.af.d */, Mips::CMP_F_D, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6326 { 2413 /* cmp.af.d */, Mips::CMP_AF_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6327 { 2422 /* cmp.af.s */, Mips::CMP_F_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6328 { 2422 /* cmp.af.s */, Mips::CMP_AF_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6329 { 2431 /* cmp.eq.d */, Mips::CMP_EQ_D, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6330 { 2431 /* cmp.eq.d */, Mips::CMP_EQ_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6331 { 2440 /* cmp.eq.ph */, Mips::CMP_EQ_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6332 { 2440 /* cmp.eq.ph */, Mips::CMP_EQ_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6333 { 2450 /* cmp.eq.s */, Mips::CMP_EQ_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6334 { 2450 /* cmp.eq.s */, Mips::CMP_EQ_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6335 { 2459 /* cmp.le.d */, Mips::CMP_LE_D, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6336 { 2459 /* cmp.le.d */, Mips::CMP_LE_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6337 { 2468 /* cmp.le.ph */, Mips::CMP_LE_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6338 { 2468 /* cmp.le.ph */, Mips::CMP_LE_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6339 { 2478 /* cmp.le.s */, Mips::CMP_LE_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6340 { 2478 /* cmp.le.s */, Mips::CMP_LE_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6341 { 2487 /* cmp.lt.d */, Mips::CMP_LT_D, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6342 { 2487 /* cmp.lt.d */, Mips::CMP_LT_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6343 { 2496 /* cmp.lt.ph */, Mips::CMP_LT_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6344 { 2496 /* cmp.lt.ph */, Mips::CMP_LT_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6345 { 2506 /* cmp.lt.s */, Mips::CMP_LT_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6346 { 2506 /* cmp.lt.s */, Mips::CMP_LT_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6347 { 2515 /* cmp.saf.d */, Mips::CMP_SAF_D, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6348 { 2515 /* cmp.saf.d */, Mips::CMP_SAF_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6349 { 2525 /* cmp.saf.s */, Mips::CMP_SAF_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6350 { 2525 /* cmp.saf.s */, Mips::CMP_SAF_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6351 { 2535 /* cmp.seq.d */, Mips::CMP_SEQ_D, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6352 { 2535 /* cmp.seq.d */, Mips::CMP_SEQ_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6353 { 2545 /* cmp.seq.s */, Mips::CMP_SEQ_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6354 { 2545 /* cmp.seq.s */, Mips::CMP_SEQ_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6355 { 2555 /* cmp.sle.d */, Mips::CMP_SLE_D, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6356 { 2555 /* cmp.sle.d */, Mips::CMP_SLE_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6357 { 2565 /* cmp.sle.s */, Mips::CMP_SLE_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6358 { 2565 /* cmp.sle.s */, Mips::CMP_SLE_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6359 { 2575 /* cmp.slt.d */, Mips::CMP_SLT_D, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6360 { 2575 /* cmp.slt.d */, Mips::CMP_SLT_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6361 { 2585 /* cmp.slt.s */, Mips::CMP_SLT_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6362 { 2585 /* cmp.slt.s */, Mips::CMP_SLT_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6363 { 2595 /* cmp.sueq.d */, Mips::CMP_SUEQ_D, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6364 { 2595 /* cmp.sueq.d */, Mips::CMP_SUEQ_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6365 { 2606 /* cmp.sueq.s */, Mips::CMP_SUEQ_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6366 { 2606 /* cmp.sueq.s */, Mips::CMP_SUEQ_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6367 { 2617 /* cmp.sule.d */, Mips::CMP_SULE_D, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6368 { 2617 /* cmp.sule.d */, Mips::CMP_SULE_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6369 { 2628 /* cmp.sule.s */, Mips::CMP_SULE_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6370 { 2628 /* cmp.sule.s */, Mips::CMP_SULE_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6371 { 2639 /* cmp.sult.d */, Mips::CMP_SULT_D, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6372 { 2639 /* cmp.sult.d */, Mips::CMP_SULT_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6373 { 2650 /* cmp.sult.s */, Mips::CMP_SULT_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6374 { 2650 /* cmp.sult.s */, Mips::CMP_SULT_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6375 { 2661 /* cmp.sun.d */, Mips::CMP_SUN_D, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6376 { 2661 /* cmp.sun.d */, Mips::CMP_SUN_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6377 { 2671 /* cmp.sun.s */, Mips::CMP_SUN_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6378 { 2671 /* cmp.sun.s */, Mips::CMP_SUN_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6379 { 2681 /* cmp.ueq.d */, Mips::CMP_UEQ_D, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6380 { 2681 /* cmp.ueq.d */, Mips::CMP_UEQ_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6381 { 2691 /* cmp.ueq.s */, Mips::CMP_UEQ_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6382 { 2691 /* cmp.ueq.s */, Mips::CMP_UEQ_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6383 { 2701 /* cmp.ule.d */, Mips::CMP_ULE_D, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6384 { 2701 /* cmp.ule.d */, Mips::CMP_ULE_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6385 { 2711 /* cmp.ule.s */, Mips::CMP_ULE_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6386 { 2711 /* cmp.ule.s */, Mips::CMP_ULE_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6387 { 2721 /* cmp.ult.d */, Mips::CMP_ULT_D, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6388 { 2721 /* cmp.ult.d */, Mips::CMP_ULT_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6389 { 2731 /* cmp.ult.s */, Mips::CMP_ULT_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6390 { 2731 /* cmp.ult.s */, Mips::CMP_ULT_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6391 { 2741 /* cmp.un.d */, Mips::CMP_UN_D, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6392 { 2741 /* cmp.un.d */, Mips::CMP_UN_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6393 { 2750 /* cmp.un.s */, Mips::CMP_UN_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6394 { 2750 /* cmp.un.s */, Mips::CMP_UN_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6395 { 2759 /* cmpgdu.eq.qb */, Mips::CMPGDU_EQ_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6396 { 2759 /* cmpgdu.eq.qb */, Mips::CMPGDU_EQ_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6397 { 2772 /* cmpgdu.le.qb */, Mips::CMPGDU_LE_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6398 { 2772 /* cmpgdu.le.qb */, Mips::CMPGDU_LE_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6399 { 2785 /* cmpgdu.lt.qb */, Mips::CMPGDU_LT_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6400 { 2785 /* cmpgdu.lt.qb */, Mips::CMPGDU_LT_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6401 { 2798 /* cmpgu.eq.qb */, Mips::CMPGU_EQ_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6402 { 2798 /* cmpgu.eq.qb */, Mips::CMPGU_EQ_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6403 { 2810 /* cmpgu.le.qb */, Mips::CMPGU_LE_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6404 { 2810 /* cmpgu.le.qb */, Mips::CMPGU_LE_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6405 { 2822 /* cmpgu.lt.qb */, Mips::CMPGU_LT_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6406 { 2822 /* cmpgu.lt.qb */, Mips::CMPGU_LT_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6407 { 2834 /* cmpi */, Mips::CmpiRxImmX16, Convert__Reg1_0__SImm161_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_SImm16 }, },
6408 { 2834 /* cmpi */, Mips::CmpiRxImm16, Convert__Reg1_0__SImm161_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_SImm16, MCK__HASH_, MCK_16, MCK_bit, MCK_inst }, },
6409 { 2839 /* cmpu.eq.qb */, Mips::CMPU_EQ_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6410 { 2839 /* cmpu.eq.qb */, Mips::CMPU_EQ_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6411 { 2850 /* cmpu.le.qb */, Mips::CMPU_LE_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6412 { 2850 /* cmpu.le.qb */, Mips::CMPU_LE_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6413 { 2861 /* cmpu.lt.qb */, Mips::CMPU_LT_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6414 { 2861 /* cmpu.lt.qb */, Mips::CMPU_LT_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6415 { 2872 /* copy_s.b */, Mips::COPY_S_B, Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_3, AMFBS_HasStdEnc_HasMSA, { MCK_GPR32AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm4_0, MCK__93_ }, },
6416 { 2881 /* copy_s.d */, Mips::COPY_S_D, Convert__GPR64AsmReg1_0__MSA128AsmReg1_1__ConstantUImm1_01_3, AMFBS_HasStdEnc_HasMSA_HasMips64, { MCK_GPR64AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm1_0, MCK__93_ }, },
6417 { 2890 /* copy_s.h */, Mips::COPY_S_H, Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_3, AMFBS_HasStdEnc_HasMSA, { MCK_GPR32AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm3_0, MCK__93_ }, },
6418 { 2899 /* copy_s.w */, Mips::COPY_S_W, Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm2_01_3, AMFBS_HasStdEnc_HasMSA, { MCK_GPR32AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm2_0, MCK__93_ }, },
6419 { 2908 /* copy_u.b */, Mips::COPY_U_B, Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_3, AMFBS_HasStdEnc_HasMSA, { MCK_GPR32AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm4_0, MCK__93_ }, },
6420 { 2917 /* copy_u.h */, Mips::COPY_U_H, Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_3, AMFBS_HasStdEnc_HasMSA, { MCK_GPR32AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm3_0, MCK__93_ }, },
6421 { 2926 /* copy_u.w */, Mips::COPY_U_W, Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm2_01_3, AMFBS_HasStdEnc_HasMSA_HasMips64, { MCK_GPR32AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm2_0, MCK__93_ }, },
6422 { 2935 /* crc32b */, Mips::CRC32B, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6423 { 2942 /* crc32cb */, Mips::CRC32CB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6424 { 2950 /* crc32cd */, Mips::CRC32CD, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips64r6_HasCRC_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6425 { 2958 /* crc32ch */, Mips::CRC32CH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6426 { 2966 /* crc32cw */, Mips::CRC32CW, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6427 { 2974 /* crc32d */, Mips::CRC32D, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips64r6_HasCRC_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6428 { 2981 /* crc32h */, Mips::CRC32H, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6429 { 2988 /* crc32w */, Mips::CRC32W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6430 { 2995 /* ctc1 */, Mips::CTC1, Convert__CCRAsmReg1_1__GPR32AsmReg1_0, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, { MCK_GPR32AsmReg, MCK_CCRAsmReg }, },
6431 { 2995 /* ctc1 */, Mips::CTC1_MM, Convert__CCRAsmReg1_1__GPR32AsmReg1_0, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_CCRAsmReg }, },
6432 { 3000 /* ctc2 */, Mips::CTC2_MM, Convert__COP2AsmReg1_1__GPR32AsmReg1_0, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_COP2AsmReg }, },
6433 { 3005 /* ctcmsa */, Mips::CTCMSA, Convert__MSACtrlAsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSACtrlAsmReg, MCK_GPR32AsmReg }, },
6434 { 3012 /* cttc1 */, Mips::CTTC1, Convert__FGR32AsmReg1_1__GPR32AsmReg1_0, AMFBS_HasMT, { MCK_GPR32AsmReg, MCK_FGR32AsmReg }, },
6435 { 3018 /* cvt.d.l */, Mips::CVT_D64_L, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6436 { 3018 /* cvt.d.l */, Mips::CVT_D_L_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6437 { 3026 /* cvt.d.s */, Mips::CVT_D32_S, Convert__AFGR64AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_FGR32AsmReg }, },
6438 { 3026 /* cvt.d.s */, Mips::CVT_D32_S_MM, Convert__AFGR64AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_FGR32AsmReg }, },
6439 { 3026 /* cvt.d.s */, Mips::CVT_D64_S, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, },
6440 { 3026 /* cvt.d.s */, Mips::CVT_D64_S_MM, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, },
6441 { 3034 /* cvt.d.w */, Mips::CVT_D32_W, Convert__AFGR64AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_FGR32AsmReg }, },
6442 { 3034 /* cvt.d.w */, Mips::CVT_D32_W_MM, Convert__AFGR64AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_FGR32AsmReg }, },
6443 { 3034 /* cvt.d.w */, Mips::CVT_D64_W, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, },
6444 { 3034 /* cvt.d.w */, Mips::CVT_D64_W_MM, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, },
6445 { 3042 /* cvt.l.d */, Mips::CVT_L_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6446 { 3042 /* cvt.l.d */, Mips::CVT_L_D64_MM, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6447 { 3042 /* cvt.l.d */, Mips::CVT_L_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6448 { 3050 /* cvt.l.s */, Mips::CVT_L_S, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, },
6449 { 3050 /* cvt.l.s */, Mips::CVT_L_S_MM, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, },
6450 { 3050 /* cvt.l.s */, Mips::CVT_L_S_MMR6, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, },
6451 { 3058 /* cvt.ps.pw */, Mips::CVT_PS_PW64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMips3D, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6452 { 3068 /* cvt.ps.s */, Mips::CVT_PS_S64, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6453 { 3077 /* cvt.pw.ps */, Mips::CVT_PW_PS64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMips3D, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6454 { 3087 /* cvt.s.d */, Mips::CVT_S_D32, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, },
6455 { 3087 /* cvt.s.d */, Mips::CVT_S_D32_MM, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, },
6456 { 3087 /* cvt.s.d */, Mips::CVT_S_D64, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg }, },
6457 { 3087 /* cvt.s.d */, Mips::CVT_S_D64_MM, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg }, },
6458 { 3095 /* cvt.s.l */, Mips::CVT_S_L, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg }, },
6459 { 3095 /* cvt.s.l */, Mips::CVT_S_L_MMR6, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, },
6460 { 3103 /* cvt.s.pl */, Mips::CVT_S_PL64, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg }, },
6461 { 3112 /* cvt.s.pu */, Mips::CVT_S_PU64, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg }, },
6462 { 3121 /* cvt.s.w */, Mips::CVT_S_W, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6463 { 3121 /* cvt.s.w */, Mips::CVT_S_W_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6464 { 3121 /* cvt.s.w */, Mips::CVT_S_W_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6465 { 3129 /* cvt.w.d */, Mips::CVT_W_D32, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, },
6466 { 3129 /* cvt.w.d */, Mips::CVT_W_D32_MM, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, },
6467 { 3129 /* cvt.w.d */, Mips::CVT_W_D64, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg }, },
6468 { 3129 /* cvt.w.d */, Mips::CVT_W_D64_MM, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg }, },
6469 { 3137 /* cvt.w.s */, Mips::CVT_W_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6470 { 3137 /* cvt.w.s */, Mips::CVT_W_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6471 { 3137 /* cvt.w.s */, Mips::CVT_W_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6472 { 3145 /* dadd */, Mips::DADD, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6473 { 3145 /* dadd */, Mips::DADDi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__SImm161_1, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_SImm16 }, },
6474 { 3145 /* dadd */, Mips::DADD, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6475 { 3145 /* dadd */, Mips::DADDi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm161_2, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_SImm16 }, },
6476 { 3150 /* daddi */, Mips::DADDi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__SImm161_1, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, { MCK_GPR64AsmReg, MCK_SImm16 }, },
6477 { 3150 /* daddi */, Mips::DADDi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm161_2, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_SImm16 }, },
6478 { 3156 /* daddiu */, Mips::DADDiu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__SImm161_1, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_SImm16 }, },
6479 { 3156 /* daddiu */, Mips::DADDiu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm161_2, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_SImm16 }, },
6480 { 3163 /* daddu */, Mips::DADDu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6481 { 3163 /* daddu */, Mips::DADDiu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__SImm161_1, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_SImm16 }, },
6482 { 3163 /* daddu */, Mips::DADDu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6483 { 3163 /* daddu */, Mips::DADDiu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm161_2, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_SImm16 }, },
6484 { 3169 /* dahi */, Mips::DAHI, Convert__GPR64AsmReg1_0__Tie0_1_2__UImm16_AltRelaxed1_2, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_UImm16_AltRelaxed }, },
6485 { 3174 /* dalign */, Mips::DALIGN, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2__ConstantUImm3_01_3, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm3_0 }, },
6486 { 3181 /* dati */, Mips::DATI, Convert__GPR64AsmReg1_0__Tie0_1_2__UImm16_AltRelaxed1_2, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_UImm16_AltRelaxed }, },
6487 { 3186 /* daui */, Mips::DAUI, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__UImm161_2, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_UImm16 }, },
6488 { 3191 /* dbitswap */, Mips::DBITSWAP, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6489 { 3200 /* dclo */, Mips::DCLO, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasStdEnc_IsGP64bit_HasMips64_NotMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6490 { 3200 /* dclo */, Mips::DCLO_R6, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6491 { 3205 /* dclz */, Mips::DCLZ, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasStdEnc_IsGP64bit_HasMips64_NotMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6492 { 3205 /* dclz */, Mips::DCLZ_R6, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6493 { 3210 /* ddiv */, Mips::DSDivMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6494 { 3210 /* ddiv */, Mips::DSDivIMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips, { MCK_GPR64AsmReg, MCK_Imm }, },
6495 { 3210 /* ddiv */, Mips::DSDIV, Convert__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips, { MCK_GPR32ZERO, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6496 { 3210 /* ddiv */, Mips::DSDivMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6497 { 3210 /* ddiv */, Mips::DDIV, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6498 { 3210 /* ddiv */, Mips::DSDivIMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, },
6499 { 3215 /* ddivu */, Mips::DUDivMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6500 { 3215 /* ddivu */, Mips::DUDivIMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips, { MCK_GPR64AsmReg, MCK_Imm }, },
6501 { 3215 /* ddivu */, Mips::DUDIV, Convert__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips, { MCK_GPR32ZERO, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6502 { 3215 /* ddivu */, Mips::DUDivMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6503 { 3215 /* ddivu */, Mips::DDIVU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6504 { 3215 /* ddivu */, Mips::DUDivIMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, },
6505 { 3221 /* deret */, Mips::DERET, Convert_NoOperands, AMFBS_HasStdEnc_HasMips32_NotInMicroMips, { }, },
6506 { 3221 /* deret */, Mips::DERET_MMR6, Convert_NoOperands, AMFBS_InMicroMips_HasMips32r6, { }, },
6507 { 3221 /* deret */, Mips::DERET_MM, Convert_NoOperands, AMFBS_InMicroMips, { }, },
6508 { 3227 /* dext */, Mips::DEXTM, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_331_3, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_33 }, },
6509 { 3227 /* dext */, Mips::DEXTU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_321_2__ConstantUImm5_11_3, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_32, MCK_ConstantUImm5_1 }, },
6510 { 3227 /* dext */, Mips::DEXT, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_0_Report_UImm61_2__ConstantUImm5_Plus1_Report_UImm61_3, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0_Report_UImm6, MCK_ConstantUImm5_Plus1_Report_UImm6 }, },
6511 { 3232 /* dextm */, Mips::DEXTM, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_331_3, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_33 }, },
6512 { 3238 /* dextu */, Mips::DEXTU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_321_2__ConstantUImm5_11_3, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_32, MCK_ConstantUImm5_1 }, },
6513 { 3244 /* di */, Mips::DI, Convert__regR0, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips, { }, },
6514 { 3244 /* di */, Mips::DI_MMR6, Convert__regR0, AMFBS_InMicroMips_HasMips32r6, { }, },
6515 { 3244 /* di */, Mips::DI_MM, Convert__regR0, AMFBS_InMicroMips, { }, },
6516 { 3244 /* di */, Mips::DI, Convert__GPR32AsmReg1_0, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips, { MCK_GPR32AsmReg }, },
6517 { 3244 /* di */, Mips::DI_MMR6, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg }, },
6518 { 3244 /* di */, Mips::DI_MM, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips, { MCK_GPR32AsmReg }, },
6519 { 3247 /* dins */, Mips::DINSM, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImmRange2_641_3__Tie0_1_1, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImmRange2_64 }, },
6520 { 3247 /* dins */, Mips::DINSU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_321_2__ConstantUImm5_11_3__Tie0_1_1, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_32, MCK_ConstantUImm5_1 }, },
6521 { 3247 /* dins */, Mips::DINS, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2__ConstantUImm5_11_3__Tie0_1_1, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm6_0, MCK_ConstantUImm5_1 }, },
6522 { 3252 /* dinsm */, Mips::DINSM, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImmRange2_641_3__Tie0_1_1, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImmRange2_64 }, },
6523 { 3258 /* dinsu */, Mips::DINSU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_321_2__ConstantUImm5_11_3__Tie0_1_1, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_32, MCK_ConstantUImm5_1 }, },
6524 { 3264 /* div */, Mips::DIV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6525 { 3264 /* div */, Mips::SDivIMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm321_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_SImm32 }, },
6526 { 3264 /* div */, Mips::SDivMacro, Convert__GPR32NonZeroAsmReg1_0__GPR32NonZeroAsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32NonZeroAsmReg, MCK_GPR32AsmReg }, },
6527 { 3264 /* div */, Mips::SDIV, Convert__GPR32ZeroAsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32ZeroAsmReg, MCK_GPR32AsmReg }, },
6528 { 3264 /* div */, Mips::DivRxRy16, Convert__Reg1_1__Reg1_2, AMFBS_InMips16Mode, { MCK_GPR32ZERO, MCK_CPU16Regs, MCK_CPU16Regs }, },
6529 { 3264 /* div */, Mips::SDIV, Convert__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32ZERO, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6530 { 3264 /* div */, Mips::SDIV_MM, Convert__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32ZERO, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6531 { 3264 /* div */, Mips::DIV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6532 { 3264 /* div */, Mips::DIV_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6533 { 3264 /* div */, Mips::SDivIMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm321_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32 }, },
6534 { 3264 /* div */, Mips::SDivMacro, Convert__GPR32NonZeroAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32NonZeroAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6535 { 3268 /* div.d */, Mips::FDIV_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6536 { 3268 /* div.d */, Mips::FDIV_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6537 { 3268 /* div.d */, Mips::FDIV_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6538 { 3268 /* div.d */, Mips::FDIV_D64_MM, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6539 { 3274 /* div.s */, Mips::FDIV_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6540 { 3274 /* div.s */, Mips::FDIV_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_2__FGR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6541 { 3274 /* div.s */, Mips::FDIV_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6542 { 3280 /* div_s.b */, Mips::DIV_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6543 { 3288 /* div_s.d */, Mips::DIV_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6544 { 3296 /* div_s.h */, Mips::DIV_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6545 { 3304 /* div_s.w */, Mips::DIV_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6546 { 3312 /* div_u.b */, Mips::DIV_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6547 { 3320 /* div_u.d */, Mips::DIV_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6548 { 3328 /* div_u.h */, Mips::DIV_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6549 { 3336 /* div_u.w */, Mips::DIV_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6550 { 3344 /* divu */, Mips::DIVU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6551 { 3344 /* divu */, Mips::UDivIMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm321_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_SImm32 }, },
6552 { 3344 /* divu */, Mips::UDivMacro, Convert__GPR32NonZeroAsmReg1_0__GPR32NonZeroAsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32NonZeroAsmReg, MCK_GPR32AsmReg }, },
6553 { 3344 /* divu */, Mips::UDIV, Convert__GPR32ZeroAsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32ZeroAsmReg, MCK_GPR32AsmReg }, },
6554 { 3344 /* divu */, Mips::DivuRxRy16, Convert__Reg1_1__Reg1_2, AMFBS_InMips16Mode, { MCK_GPR32ZERO, MCK_CPU16Regs, MCK_CPU16Regs }, },
6555 { 3344 /* divu */, Mips::UDIV, Convert__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32ZERO, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6556 { 3344 /* divu */, Mips::UDIV_MM, Convert__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32ZERO, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6557 { 3344 /* divu */, Mips::UDivMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6558 { 3344 /* divu */, Mips::DIVU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6559 { 3344 /* divu */, Mips::DIVU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6560 { 3344 /* divu */, Mips::UDivIMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm321_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32 }, },
6561 { 3349 /* dla */, Mips::LoadAddrImm64, Convert__GPR64AsmReg1_0__Imm1_1, AMFBS_None, { MCK_GPR64AsmReg, MCK_Imm }, },
6562 { 3349 /* dla */, Mips::LoadAddrReg64, Convert__GPR64AsmReg1_0__Mem2_1, AMFBS_None, { MCK_GPR64AsmReg, MCK_Mem }, },
6563 { 3353 /* dli */, Mips::LoadImm64, Convert__GPR64AsmReg1_0__Imm1_1, AMFBS_None, { MCK_GPR64AsmReg, MCK_Imm }, },
6564 { 3357 /* dlsa */, Mips::DLSA, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2__ConstantUImm2_11_3, AMFBS_HasStdEnc_HasMSA_HasMips64, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm2_1 }, },
6565 { 3357 /* dlsa */, Mips::DLSA_R6, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2__ConstantUImm2_11_3, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm2_1 }, },
6566 { 3362 /* dmfc0 */, Mips::DMFC0, Convert__GPR64AsmReg1_0__COP0AsmReg1_1__imm_95_0, AMFBS_NotInMicroMips, { MCK_GPR64AsmReg, MCK_COP0AsmReg }, },
6567 { 3362 /* dmfc0 */, Mips::DMFC0, Convert__GPR64AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasStdEnc_IsGP64bit_HasMips3, { MCK_GPR64AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
6568 { 3368 /* dmfc1 */, Mips::DMFC1, Convert__GPR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_HasMips3_IsNotSoftFloat_IsNotSingleFloat, { MCK_GPR64AsmReg, MCK_FGR64AsmReg }, },
6569 { 3374 /* dmfc2 */, Mips::DMFC2, Convert__GPR64AsmReg1_0__COP2AsmReg1_1__imm_95_0, AMFBS_None, { MCK_GPR64AsmReg, MCK_COP2AsmReg }, },
6570 { 3374 /* dmfc2 */, Mips::DMFC2_OCTEON, Convert__GPR64AsmReg1_0__UImm161_1, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_UImm16 }, },
6571 { 3374 /* dmfc2 */, Mips::DMFC2, Convert__GPR64AsmReg1_0__COP2AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasStdEnc_IsGP64bit_HasMips3, { MCK_GPR64AsmReg, MCK_COP2AsmReg, MCK_ConstantUImm3_0 }, },
6572 { 3380 /* dmfgc0 */, Mips::DMFGC0, Convert__GPR64AsmReg1_0__COP0AsmReg1_1__imm_95_0, AMFBS_HasStdEnc_HasMips64r5_HasVirt_NotInMicroMips, { MCK_GPR64AsmReg, MCK_COP0AsmReg }, },
6573 { 3380 /* dmfgc0 */, Mips::DMFGC0, Convert__GPR64AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasStdEnc_HasMips64r5_HasVirt, { MCK_GPR64AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
6574 { 3387 /* dmod */, Mips::DMOD, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6575 { 3392 /* dmodu */, Mips::DMODU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6576 { 3398 /* dmt */, Mips::DMT, Convert__regR0, AMFBS_HasMT_NotInMicroMips, { }, },
6577 { 3398 /* dmt */, Mips::DMT, Convert__GPR32AsmReg1_0, AMFBS_HasStdEnc_HasMT_NotInMicroMips, { MCK_GPR32AsmReg }, },
6578 { 3402 /* dmtc0 */, Mips::DMTC0, Convert__COP0AsmReg1_1__GPR64AsmReg1_0__imm_95_0, AMFBS_NotInMicroMips, { MCK_GPR64AsmReg, MCK_COP0AsmReg }, },
6579 { 3402 /* dmtc0 */, Mips::DMTC0, Convert__COP0AsmReg1_1__GPR64AsmReg1_0__ConstantUImm3_01_2, AMFBS_HasStdEnc_IsGP64bit_HasMips3, { MCK_GPR64AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
6580 { 3408 /* dmtc1 */, Mips::DMTC1, Convert__FGR64AsmReg1_1__GPR64AsmReg1_0, AMFBS_HasStdEnc_HasMips3_IsNotSoftFloat_IsNotSingleFloat, { MCK_GPR64AsmReg, MCK_FGR64AsmReg }, },
6581 { 3414 /* dmtc2 */, Mips::DMTC2, Convert__COP2AsmReg1_1__GPR64AsmReg1_0__imm_95_0, AMFBS_None, { MCK_GPR64AsmReg, MCK_COP2AsmReg }, },
6582 { 3414 /* dmtc2 */, Mips::DMTC2_OCTEON, Convert__GPR64AsmReg1_0__UImm161_1, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_UImm16 }, },
6583 { 3414 /* dmtc2 */, Mips::DMTC2, Convert__COP2AsmReg1_1__GPR64AsmReg1_0__ConstantUImm3_01_2, AMFBS_HasStdEnc_IsGP64bit_HasMips3, { MCK_GPR64AsmReg, MCK_COP2AsmReg, MCK_ConstantUImm3_0 }, },
6584 { 3420 /* dmtgc0 */, Mips::DMTGC0, Convert__COP0AsmReg1_1__GPR64AsmReg1_0__imm_95_0, AMFBS_HasStdEnc_HasMips64r5_HasVirt_NotInMicroMips, { MCK_GPR64AsmReg, MCK_COP0AsmReg }, },
6585 { 3420 /* dmtgc0 */, Mips::DMTGC0, Convert__COP0AsmReg1_1__GPR64AsmReg1_0__ConstantUImm3_01_2, AMFBS_HasStdEnc_HasMips64r5_HasVirt, { MCK_GPR64AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
6586 { 3427 /* dmuh */, Mips::DMUH, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6587 { 3432 /* dmuhu */, Mips::DMUHU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6588 { 3438 /* dmul */, Mips::DMUL, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6589 { 3438 /* dmul */, Mips::DMULMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasMips3_NotMips64r6_NotCnMips_NotR5900, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6590 { 3438 /* dmul */, Mips::DMUL_R6, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6591 { 3438 /* dmul */, Mips::DMUL, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6592 { 3438 /* dmul */, Mips::DMULImmMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm32_Relaxed1_2, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_SImm32_Relaxed }, },
6593 { 3443 /* dmulo */, Mips::DMULOMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6594 { 3449 /* dmulou */, Mips::DMULOUMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6595 { 3456 /* dmult */, Mips::DMULT, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6596 { 3462 /* dmultu */, Mips::DMULTu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6597 { 3469 /* dmulu */, Mips::DMULU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6598 { 3475 /* dneg */, Mips::DSUB, Convert__GPR64AsmReg1_0__regR0_64__GPR64AsmReg1_0, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg }, },
6599 { 3475 /* dneg */, Mips::DSUB, Convert__GPR64AsmReg1_0__regR0_64__GPR64AsmReg1_1, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6600 { 3480 /* dnegu */, Mips::DSUBu, Convert__GPR64AsmReg1_0__regR0_64__GPR64AsmReg1_0, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg }, },
6601 { 3480 /* dnegu */, Mips::DSUBu, Convert__GPR64AsmReg1_0__regR0_64__GPR64AsmReg1_1, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6602 { 3486 /* dotp_s.d */, Mips::DOTP_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6603 { 3495 /* dotp_s.h */, Mips::DOTP_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6604 { 3504 /* dotp_s.w */, Mips::DOTP_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6605 { 3513 /* dotp_u.d */, Mips::DOTP_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6606 { 3522 /* dotp_u.h */, Mips::DOTP_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6607 { 3531 /* dotp_u.w */, Mips::DOTP_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6608 { 3540 /* dpa.w.ph */, Mips::DPA_W_PH_MMR2, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6609 { 3540 /* dpa.w.ph */, Mips::DPA_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6610 { 3549 /* dpadd_s.d */, Mips::DPADD_S_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6611 { 3559 /* dpadd_s.h */, Mips::DPADD_S_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6612 { 3569 /* dpadd_s.w */, Mips::DPADD_S_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6613 { 3579 /* dpadd_u.d */, Mips::DPADD_U_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6614 { 3589 /* dpadd_u.h */, Mips::DPADD_U_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6615 { 3599 /* dpadd_u.w */, Mips::DPADD_U_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6616 { 3609 /* dpaq_s.w.ph */, Mips::DPAQ_S_W_PH_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6617 { 3609 /* dpaq_s.w.ph */, Mips::DPAQ_S_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6618 { 3621 /* dpaq_sa.l.w */, Mips::DPAQ_SA_L_W_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6619 { 3621 /* dpaq_sa.l.w */, Mips::DPAQ_SA_L_W, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6620 { 3633 /* dpaqx_s.w.ph */, Mips::DPAQX_S_W_PH_MMR2, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6621 { 3633 /* dpaqx_s.w.ph */, Mips::DPAQX_S_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6622 { 3646 /* dpaqx_sa.w.ph */, Mips::DPAQX_SA_W_PH_MMR2, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6623 { 3646 /* dpaqx_sa.w.ph */, Mips::DPAQX_SA_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6624 { 3660 /* dpau.h.qbl */, Mips::DPAU_H_QBL_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6625 { 3660 /* dpau.h.qbl */, Mips::DPAU_H_QBL, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6626 { 3671 /* dpau.h.qbr */, Mips::DPAU_H_QBR_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6627 { 3671 /* dpau.h.qbr */, Mips::DPAU_H_QBR, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6628 { 3682 /* dpax.w.ph */, Mips::DPAX_W_PH_MMR2, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6629 { 3682 /* dpax.w.ph */, Mips::DPAX_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6630 { 3692 /* dpop */, Mips::DPOP, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0, AMFBS_HasCnMips, { MCK_GPR64AsmReg }, },
6631 { 3692 /* dpop */, Mips::DPOP, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6632 { 3697 /* dps.w.ph */, Mips::DPS_W_PH_MMR2, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6633 { 3697 /* dps.w.ph */, Mips::DPS_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6634 { 3706 /* dpsq_s.w.ph */, Mips::DPSQ_S_W_PH_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6635 { 3706 /* dpsq_s.w.ph */, Mips::DPSQ_S_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6636 { 3718 /* dpsq_sa.l.w */, Mips::DPSQ_SA_L_W_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6637 { 3718 /* dpsq_sa.l.w */, Mips::DPSQ_SA_L_W, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6638 { 3730 /* dpsqx_s.w.ph */, Mips::DPSQX_S_W_PH_MMR2, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6639 { 3730 /* dpsqx_s.w.ph */, Mips::DPSQX_S_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6640 { 3743 /* dpsqx_sa.w.ph */, Mips::DPSQX_SA_W_PH_MMR2, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6641 { 3743 /* dpsqx_sa.w.ph */, Mips::DPSQX_SA_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6642 { 3757 /* dpsu.h.qbl */, Mips::DPSU_H_QBL_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6643 { 3757 /* dpsu.h.qbl */, Mips::DPSU_H_QBL, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6644 { 3768 /* dpsu.h.qbr */, Mips::DPSU_H_QBR_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6645 { 3768 /* dpsu.h.qbr */, Mips::DPSU_H_QBR, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6646 { 3779 /* dpsub_s.d */, Mips::DPSUB_S_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6647 { 3789 /* dpsub_s.h */, Mips::DPSUB_S_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6648 { 3799 /* dpsub_s.w */, Mips::DPSUB_S_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6649 { 3809 /* dpsub_u.d */, Mips::DPSUB_U_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6650 { 3819 /* dpsub_u.h */, Mips::DPSUB_U_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6651 { 3829 /* dpsub_u.w */, Mips::DPSUB_U_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6652 { 3839 /* dpsx.w.ph */, Mips::DPSX_W_PH_MMR2, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6653 { 3839 /* dpsx.w.ph */, Mips::DPSX_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6654 { 3849 /* drem */, Mips::DSRemMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6655 { 3849 /* drem */, Mips::DSRemIMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__SImm32_Relaxed1_1, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips, { MCK_GPR64AsmReg, MCK_SImm32_Relaxed }, },
6656 { 3849 /* drem */, Mips::DSRemMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6657 { 3849 /* drem */, Mips::DSRemIMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm32_Relaxed1_2, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_SImm32_Relaxed }, },
6658 { 3854 /* dremu */, Mips::DURemMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6659 { 3854 /* dremu */, Mips::DURemIMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__SImm32_Relaxed1_1, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips, { MCK_GPR64AsmReg, MCK_SImm32_Relaxed }, },
6660 { 3854 /* dremu */, Mips::DURemMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6661 { 3854 /* dremu */, Mips::DURemIMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm32_Relaxed1_2, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_SImm32_Relaxed }, },
6662 { 3860 /* drol */, Mips::DROL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips64, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6663 { 3860 /* drol */, Mips::DROLImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm161_1, AMFBS_HasStdEnc_HasMips64, { MCK_GPR32AsmReg, MCK_SImm16 }, },
6664 { 3860 /* drol */, Mips::DROL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips64, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6665 { 3860 /* drol */, Mips::DROLImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, AMFBS_HasStdEnc_HasMips64, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16 }, },
6666 { 3865 /* dror */, Mips::DROR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips64, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6667 { 3865 /* dror */, Mips::DRORImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm161_1, AMFBS_HasStdEnc_HasMips64, { MCK_GPR32AsmReg, MCK_SImm16 }, },
6668 { 3865 /* dror */, Mips::DROR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips64, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6669 { 3865 /* dror */, Mips::DRORImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, AMFBS_HasStdEnc_HasMips64, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16 }, },
6670 { 3870 /* drotr */, Mips::DROTR, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm6_01_1, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips, { MCK_GPR64AsmReg, MCK_ConstantUImm6_0 }, },
6671 { 3870 /* drotr */, Mips::DROTR, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm6_0 }, },
6672 { 3876 /* drotr32 */, Mips::DROTR32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0 }, },
6673 { 3876 /* drotr32 */, Mips::DROTR32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0 }, },
6674 { 3884 /* drotrv */, Mips::DROTRV, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR32AsmReg }, },
6675 { 3891 /* dsbh */, Mips::DSBH, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6676 { 3896 /* dshd */, Mips::DSHD, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6677 { 3901 /* dsll */, Mips::DSLLV, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR32AsmReg }, },
6678 { 3901 /* dsll */, Mips::DSLL, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm6_01_1, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_ConstantUImm6_0 }, },
6679 { 3901 /* dsll */, Mips::DSLLV, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR32AsmReg }, },
6680 { 3901 /* dsll */, Mips::DSLL, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm6_0 }, },
6681 { 3906 /* dsll32 */, Mips::DSLL32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0 }, },
6682 { 3906 /* dsll32 */, Mips::DSLL32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0 }, },
6683 { 3913 /* dsllv */, Mips::DSLLV, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR32AsmReg }, },
6684 { 3919 /* dsra */, Mips::DSRA, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm6_01_1, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_ConstantUImm6_0 }, },
6685 { 3919 /* dsra */, Mips::DSRAV, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips3, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR32AsmReg }, },
6686 { 3919 /* dsra */, Mips::DSRA, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm6_0 }, },
6687 { 3924 /* dsra32 */, Mips::DSRA32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0 }, },
6688 { 3924 /* dsra32 */, Mips::DSRA32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0 }, },
6689 { 3931 /* dsrav */, Mips::DSRAV, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR32AsmReg }, },
6690 { 3937 /* dsrl */, Mips::DSRLV, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR32AsmReg }, },
6691 { 3937 /* dsrl */, Mips::DSRL, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm6_01_1, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_ConstantUImm6_0 }, },
6692 { 3937 /* dsrl */, Mips::DSRLV, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR32AsmReg }, },
6693 { 3937 /* dsrl */, Mips::DSRL, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm6_0 }, },
6694 { 3942 /* dsrl32 */, Mips::DSRL32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0 }, },
6695 { 3942 /* dsrl32 */, Mips::DSRL32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0 }, },
6696 { 3949 /* dsrlv */, Mips::DSRLV, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR32AsmReg }, },
6697 { 3955 /* dsub */, Mips::DSUB, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6698 { 3955 /* dsub */, Mips::DADDi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__InvNum1_1, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, { MCK_GPR64AsmReg, MCK_InvNum }, },
6699 { 3955 /* dsub */, Mips::DSUB, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6700 { 3955 /* dsub */, Mips::DADDi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__InvNum1_2, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_InvNum }, },
6701 { 3960 /* dsubi */, Mips::DADDi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__InvNum1_1, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, { MCK_GPR64AsmReg, MCK_InvNum }, },
6702 { 3960 /* dsubi */, Mips::DADDi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__InvNum1_2, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_InvNum }, },
6703 { 3966 /* dsubu */, Mips::DSUBu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6704 { 3966 /* dsubu */, Mips::DADDiu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__InvNum1_1, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_InvNum }, },
6705 { 3966 /* dsubu */, Mips::DSUBu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6706 { 3966 /* dsubu */, Mips::DADDiu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__InvNum1_2, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_InvNum }, },
6707 { 3972 /* dvp */, Mips::DVP, Convert__regR0, AMFBS_HasStdEnc_HasMips32r6, { }, },
6708 { 3972 /* dvp */, Mips::DVP_MMR6, Convert__regR0, AMFBS_InMicroMips_HasMips32r6, { }, },
6709 { 3972 /* dvp */, Mips::DVP, Convert__GPR32AsmReg1_0, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR32AsmReg }, },
6710 { 3972 /* dvp */, Mips::DVP_MMR6, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg }, },
6711 { 3976 /* dvpe */, Mips::DVPE, Convert__regR0, AMFBS_HasMT_NotInMicroMips, { }, },
6712 { 3976 /* dvpe */, Mips::DVPE, Convert__GPR32AsmReg1_0, AMFBS_HasStdEnc_HasMT_NotInMicroMips, { MCK_GPR32AsmReg }, },
6713 { 3981 /* ehb */, Mips::EHB, Convert_NoOperands, AMFBS_HasStdEnc_NotInMicroMips, { }, },
6714 { 3981 /* ehb */, Mips::EHB_MMR6, Convert_NoOperands, AMFBS_InMicroMips_HasMips32r6, { }, },
6715 { 3981 /* ehb */, Mips::EHB_MM, Convert_NoOperands, AMFBS_InMicroMips, { }, },
6716 { 3985 /* ei */, Mips::EI, Convert__regR0, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips, { }, },
6717 { 3985 /* ei */, Mips::EI_MMR6, Convert__regR0, AMFBS_InMicroMips_HasMips32r6, { }, },
6718 { 3985 /* ei */, Mips::EI_MM, Convert__regR0, AMFBS_InMicroMips, { }, },
6719 { 3985 /* ei */, Mips::EI, Convert__GPR32AsmReg1_0, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips, { MCK_GPR32AsmReg }, },
6720 { 3985 /* ei */, Mips::EI_MMR6, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg }, },
6721 { 3985 /* ei */, Mips::EI_MM, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips, { MCK_GPR32AsmReg }, },
6722 { 3988 /* emt */, Mips::EMT, Convert__regR0, AMFBS_HasMT_NotInMicroMips, { }, },
6723 { 3988 /* emt */, Mips::EMT, Convert__GPR32AsmReg1_0, AMFBS_HasStdEnc_HasMT_NotInMicroMips, { MCK_GPR32AsmReg }, },
6724 { 3992 /* eret */, Mips::ERET, Convert_NoOperands, AMFBS_HasStdEnc_HasMips3_32_NotInMicroMips, { }, },
6725 { 3992 /* eret */, Mips::ERET_MMR6, Convert_NoOperands, AMFBS_InMicroMips_HasMips32r6, { }, },
6726 { 3992 /* eret */, Mips::ERET_MM, Convert_NoOperands, AMFBS_InMicroMips, { }, },
6727 { 3997 /* eretnc */, Mips::ERETNC, Convert_NoOperands, AMFBS_HasStdEnc_HasMips32r5_NotInMicroMips, { }, },
6728 { 3997 /* eretnc */, Mips::ERETNC_MMR6, Convert_NoOperands, AMFBS_InMicroMips_HasMips32r6, { }, },
6729 { 4004 /* evp */, Mips::EVP, Convert__regR0, AMFBS_HasStdEnc_HasMips32r6, { }, },
6730 { 4004 /* evp */, Mips::EVP_MMR6, Convert__regR0, AMFBS_InMicroMips_HasMips32r6, { }, },
6731 { 4004 /* evp */, Mips::EVP, Convert__GPR32AsmReg1_0, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR32AsmReg }, },
6732 { 4004 /* evp */, Mips::EVP_MMR6, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg }, },
6733 { 4008 /* evpe */, Mips::EVPE, Convert__regR0, AMFBS_HasMT_NotInMicroMips, { }, },
6734 { 4008 /* evpe */, Mips::EVPE, Convert__GPR32AsmReg1_0, AMFBS_HasStdEnc_HasMT_NotInMicroMips, { MCK_GPR32AsmReg }, },
6735 { 4013 /* ext */, Mips::EXT, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_1 }, },
6736 { 4013 /* ext */, Mips::EXT_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_1 }, },
6737 { 4013 /* ext */, Mips::EXT_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_1 }, },
6738 { 4017 /* extp */, Mips::EXTP_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, },
6739 { 4017 /* extp */, Mips::EXTP, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, },
6740 { 4022 /* extpdp */, Mips::EXTPDP_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, },
6741 { 4022 /* extpdp */, Mips::EXTPDP, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, },
6742 { 4029 /* extpdpv */, Mips::EXTPDPV_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, },
6743 { 4029 /* extpdpv */, Mips::EXTPDPV, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, },
6744 { 4037 /* extpv */, Mips::EXTPV_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, },
6745 { 4037 /* extpv */, Mips::EXTPV, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, },
6746 { 4043 /* extr.w */, Mips::EXTR_W_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, },
6747 { 4043 /* extr.w */, Mips::EXTR_W, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, },
6748 { 4050 /* extr_r.w */, Mips::EXTR_R_W_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, },
6749 { 4050 /* extr_r.w */, Mips::EXTR_R_W, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, },
6750 { 4059 /* extr_rs.w */, Mips::EXTR_RS_W_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, },
6751 { 4059 /* extr_rs.w */, Mips::EXTR_RS_W, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, },
6752 { 4069 /* extr_s.h */, Mips::EXTR_S_H_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, },
6753 { 4069 /* extr_s.h */, Mips::EXTR_S_H, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, },
6754 { 4078 /* extrv.w */, Mips::EXTRV_W_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, },
6755 { 4078 /* extrv.w */, Mips::EXTRV_W, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, },
6756 { 4086 /* extrv_r.w */, Mips::EXTRV_R_W_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, },
6757 { 4086 /* extrv_r.w */, Mips::EXTRV_R_W, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, },
6758 { 4096 /* extrv_rs.w */, Mips::EXTRV_RS_W_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, },
6759 { 4096 /* extrv_rs.w */, Mips::EXTRV_RS_W, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, },
6760 { 4107 /* extrv_s.h */, Mips::EXTRV_S_H_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, },
6761 { 4107 /* extrv_s.h */, Mips::EXTRV_S_H, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, },
6762 { 4117 /* exts */, Mips::EXTS, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1__ConstantUImm5_01_2, AMFBS_HasMips64_HasCnMips_NotInMicroMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_0 }, },
6763 { 4117 /* exts */, Mips::EXTS32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_32_Norm1_1__ConstantUImm5_01_2, AMFBS_HasMips64_HasCnMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_32_Norm, MCK_ConstantUImm5_0 }, },
6764 { 4117 /* exts */, Mips::EXTS, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_01_3, AMFBS_HasMips64_HasCnMips_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_0 }, },
6765 { 4117 /* exts */, Mips::EXTS32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_32_Norm1_2__ConstantUImm5_01_3, AMFBS_HasMips64_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_32_Norm, MCK_ConstantUImm5_0 }, },
6766 { 4122 /* exts32 */, Mips::EXTS32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1__ConstantUImm5_01_2, AMFBS_HasMips64_HasCnMips_NotInMicroMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_0 }, },
6767 { 4122 /* exts32 */, Mips::EXTS32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_01_3, AMFBS_HasMips64_HasCnMips_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_0 }, },
6768 { 4129 /* fadd.d */, Mips::FADD_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6769 { 4136 /* fadd.w */, Mips::FADD_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6770 { 4143 /* fcaf.d */, Mips::FCAF_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6771 { 4150 /* fcaf.w */, Mips::FCAF_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6772 { 4157 /* fceq.d */, Mips::FCEQ_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6773 { 4164 /* fceq.w */, Mips::FCEQ_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6774 { 4171 /* fclass.d */, Mips::FCLASS_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6775 { 4180 /* fclass.w */, Mips::FCLASS_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6776 { 4189 /* fcle.d */, Mips::FCLE_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6777 { 4196 /* fcle.w */, Mips::FCLE_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6778 { 4203 /* fclt.d */, Mips::FCLT_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6779 { 4210 /* fclt.w */, Mips::FCLT_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6780 { 4217 /* fcne.d */, Mips::FCNE_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6781 { 4224 /* fcne.w */, Mips::FCNE_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6782 { 4231 /* fcor.d */, Mips::FCOR_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6783 { 4238 /* fcor.w */, Mips::FCOR_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6784 { 4245 /* fcueq.d */, Mips::FCUEQ_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6785 { 4253 /* fcueq.w */, Mips::FCUEQ_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6786 { 4261 /* fcule.d */, Mips::FCULE_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6787 { 4269 /* fcule.w */, Mips::FCULE_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6788 { 4277 /* fcult.d */, Mips::FCULT_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6789 { 4285 /* fcult.w */, Mips::FCULT_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6790 { 4293 /* fcun.d */, Mips::FCUN_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6791 { 4300 /* fcun.w */, Mips::FCUN_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6792 { 4307 /* fcune.d */, Mips::FCUNE_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6793 { 4315 /* fcune.w */, Mips::FCUNE_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6794 { 4323 /* fdiv.d */, Mips::FDIV_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6795 { 4330 /* fdiv.w */, Mips::FDIV_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6796 { 4337 /* fexdo.h */, Mips::FEXDO_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6797 { 4345 /* fexdo.w */, Mips::FEXDO_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6798 { 4353 /* fexp2.d */, Mips::FEXP2_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6799 { 4361 /* fexp2.w */, Mips::FEXP2_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6800 { 4369 /* fexupl.d */, Mips::FEXUPL_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6801 { 4378 /* fexupl.w */, Mips::FEXUPL_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6802 { 4387 /* fexupr.d */, Mips::FEXUPR_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6803 { 4396 /* fexupr.w */, Mips::FEXUPR_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6804 { 4405 /* ffint_s.d */, Mips::FFINT_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6805 { 4415 /* ffint_s.w */, Mips::FFINT_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6806 { 4425 /* ffint_u.d */, Mips::FFINT_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6807 { 4435 /* ffint_u.w */, Mips::FFINT_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6808 { 4445 /* ffql.d */, Mips::FFQL_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6809 { 4452 /* ffql.w */, Mips::FFQL_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6810 { 4459 /* ffqr.d */, Mips::FFQR_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6811 { 4466 /* ffqr.w */, Mips::FFQR_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6812 { 4473 /* fill.b */, Mips::FILL_B, Convert__MSA128AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_GPR32AsmReg }, },
6813 { 4480 /* fill.d */, Mips::FILL_D, Convert__MSA128AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasStdEnc_HasMSA_HasMips64, { MCK_MSA128AsmReg, MCK_GPR64AsmReg }, },
6814 { 4487 /* fill.h */, Mips::FILL_H, Convert__MSA128AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_GPR32AsmReg }, },
6815 { 4494 /* fill.w */, Mips::FILL_W, Convert__MSA128AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_GPR32AsmReg }, },
6816 { 4501 /* flog2.d */, Mips::FLOG2_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6817 { 4509 /* flog2.w */, Mips::FLOG2_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6818 { 4517 /* floor.l.d */, Mips::FLOOR_L_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips3_32_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6819 { 4517 /* floor.l.d */, Mips::FLOOR_L_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6820 { 4527 /* floor.l.s */, Mips::FLOOR_L_S, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, },
6821 { 4527 /* floor.l.s */, Mips::FLOOR_L_S_MMR6, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, },
6822 { 4537 /* floor.w.d */, Mips::FLOOR_W_D32, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, },
6823 { 4537 /* floor.w.d */, Mips::FLOOR_W_MM, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, },
6824 { 4537 /* floor.w.d */, Mips::FLOOR_W_D_MMR6, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, },
6825 { 4537 /* floor.w.d */, Mips::FLOOR_W_D64, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg }, },
6826 { 4547 /* floor.w.s */, Mips::FLOOR_W_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_HasMips2_NotR5900_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6827 { 4547 /* floor.w.s */, Mips::FLOOR_W_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6828 { 4547 /* floor.w.s */, Mips::FLOOR_W_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6829 { 4557 /* fmadd.d */, Mips::FMADD_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6830 { 4565 /* fmadd.w */, Mips::FMADD_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6831 { 4573 /* fmax.d */, Mips::FMAX_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6832 { 4580 /* fmax.w */, Mips::FMAX_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6833 { 4587 /* fmax_a.d */, Mips::FMAX_A_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6834 { 4596 /* fmax_a.w */, Mips::FMAX_A_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6835 { 4605 /* fmin.d */, Mips::FMIN_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6836 { 4612 /* fmin.w */, Mips::FMIN_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6837 { 4619 /* fmin_a.d */, Mips::FMIN_A_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6838 { 4628 /* fmin_a.w */, Mips::FMIN_A_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6839 { 4637 /* fmsub.d */, Mips::FMSUB_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6840 { 4645 /* fmsub.w */, Mips::FMSUB_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6841 { 4653 /* fmul.d */, Mips::FMUL_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6842 { 4660 /* fmul.w */, Mips::FMUL_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6843 { 4667 /* fork */, Mips::FORK, Convert__GPR32AsmReg1_1__GPR32AsmReg1_0__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMT_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6844 { 4672 /* frcp.d */, Mips::FRCP_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6845 { 4679 /* frcp.w */, Mips::FRCP_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6846 { 4686 /* frint.d */, Mips::FRINT_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6847 { 4694 /* frint.w */, Mips::FRINT_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6848 { 4702 /* frsqrt.d */, Mips::FRSQRT_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6849 { 4711 /* frsqrt.w */, Mips::FRSQRT_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6850 { 4720 /* fsaf.d */, Mips::FSAF_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6851 { 4727 /* fsaf.w */, Mips::FSAF_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6852 { 4734 /* fseq.d */, Mips::FSEQ_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6853 { 4741 /* fseq.w */, Mips::FSEQ_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6854 { 4748 /* fsle.d */, Mips::FSLE_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6855 { 4755 /* fsle.w */, Mips::FSLE_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6856 { 4762 /* fslt.d */, Mips::FSLT_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6857 { 4769 /* fslt.w */, Mips::FSLT_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6858 { 4776 /* fsne.d */, Mips::FSNE_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6859 { 4783 /* fsne.w */, Mips::FSNE_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6860 { 4790 /* fsor.d */, Mips::FSOR_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6861 { 4797 /* fsor.w */, Mips::FSOR_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6862 { 4804 /* fsqrt.d */, Mips::FSQRT_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6863 { 4812 /* fsqrt.w */, Mips::FSQRT_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6864 { 4820 /* fsub.d */, Mips::FSUB_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6865 { 4827 /* fsub.w */, Mips::FSUB_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6866 { 4834 /* fsueq.d */, Mips::FSUEQ_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6867 { 4842 /* fsueq.w */, Mips::FSUEQ_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6868 { 4850 /* fsule.d */, Mips::FSULE_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6869 { 4858 /* fsule.w */, Mips::FSULE_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6870 { 4866 /* fsult.d */, Mips::FSULT_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6871 { 4874 /* fsult.w */, Mips::FSULT_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6872 { 4882 /* fsun.d */, Mips::FSUN_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6873 { 4889 /* fsun.w */, Mips::FSUN_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6874 { 4896 /* fsune.d */, Mips::FSUNE_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6875 { 4904 /* fsune.w */, Mips::FSUNE_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6876 { 4912 /* ftint_s.d */, Mips::FTINT_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6877 { 4922 /* ftint_s.w */, Mips::FTINT_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6878 { 4932 /* ftint_u.d */, Mips::FTINT_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6879 { 4942 /* ftint_u.w */, Mips::FTINT_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6880 { 4952 /* ftq.h */, Mips::FTQ_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6881 { 4958 /* ftq.w */, Mips::FTQ_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6882 { 4964 /* ftrunc_s.d */, Mips::FTRUNC_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6883 { 4975 /* ftrunc_s.w */, Mips::FTRUNC_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6884 { 4986 /* ftrunc_u.d */, Mips::FTRUNC_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6885 { 4997 /* ftrunc_u.w */, Mips::FTRUNC_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6886 { 5008 /* ginvi */, Mips::GINVI, Convert__GPR32AsmReg1_0, AMFBS_HasStdEnc_HasMips32r6_HasGINV_NotInMicroMips, { MCK_GPR32AsmReg }, },
6887 { 5008 /* ginvi */, Mips::GINVI_MMR6, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips_HasMips32r6_HasGINV, { MCK_GPR32AsmReg }, },
6888 { 5014 /* ginvt */, Mips::GINVT, Convert__GPR32AsmReg1_0__ConstantUImm2_01_1, AMFBS_HasStdEnc_HasMips32r6_HasGINV_NotInMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm2_0 }, },
6889 { 5014 /* ginvt */, Mips::GINVT_MMR6, Convert__GPR32AsmReg1_0__ConstantUImm2_01_1, AMFBS_InMicroMips_HasMips32r6_HasGINV, { MCK_GPR32AsmReg, MCK_ConstantUImm2_0 }, },
6890 { 5020 /* hadd_s.d */, Mips::HADD_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6891 { 5029 /* hadd_s.h */, Mips::HADD_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6892 { 5038 /* hadd_s.w */, Mips::HADD_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6893 { 5047 /* hadd_u.d */, Mips::HADD_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6894 { 5056 /* hadd_u.h */, Mips::HADD_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6895 { 5065 /* hadd_u.w */, Mips::HADD_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6896 { 5074 /* hsub_s.d */, Mips::HSUB_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6897 { 5083 /* hsub_s.h */, Mips::HSUB_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6898 { 5092 /* hsub_s.w */, Mips::HSUB_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6899 { 5101 /* hsub_u.d */, Mips::HSUB_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6900 { 5110 /* hsub_u.h */, Mips::HSUB_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6901 { 5119 /* hsub_u.w */, Mips::HSUB_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6902 { 5128 /* hypcall */, Mips::HYPCALL, Convert__imm_95_0, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, { }, },
6903 { 5128 /* hypcall */, Mips::HYPCALL_MM, Convert__imm_95_0, AMFBS_InMicroMips_HasMips32r5_HasVirt, { }, },
6904 { 5128 /* hypcall */, Mips::HYPCALL, Convert__ConstantUImm10_01_0, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, { MCK_ConstantUImm10_0 }, },
6905 { 5128 /* hypcall */, Mips::HYPCALL_MM, Convert__ConstantUImm10_01_0, AMFBS_InMicroMips_HasMips32r5_HasVirt, { MCK_ConstantUImm10_0 }, },
6906 { 5136 /* ilvev.b */, Mips::ILVEV_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6907 { 5144 /* ilvev.d */, Mips::ILVEV_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6908 { 5152 /* ilvev.h */, Mips::ILVEV_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6909 { 5160 /* ilvev.w */, Mips::ILVEV_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6910 { 5168 /* ilvl.b */, Mips::ILVL_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6911 { 5175 /* ilvl.d */, Mips::ILVL_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6912 { 5182 /* ilvl.h */, Mips::ILVL_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6913 { 5189 /* ilvl.w */, Mips::ILVL_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6914 { 5196 /* ilvod.b */, Mips::ILVOD_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6915 { 5204 /* ilvod.d */, Mips::ILVOD_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6916 { 5212 /* ilvod.h */, Mips::ILVOD_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6917 { 5220 /* ilvod.w */, Mips::ILVOD_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6918 { 5228 /* ilvr.b */, Mips::ILVR_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6919 { 5235 /* ilvr.d */, Mips::ILVR_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6920 { 5242 /* ilvr.h */, Mips::ILVR_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6921 { 5249 /* ilvr.w */, Mips::ILVR_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6922 { 5256 /* ins */, Mips::INS, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3__Tie0_1_1, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_1 }, },
6923 { 5256 /* ins */, Mips::INS_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3__Tie0_1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_1 }, },
6924 { 5256 /* ins */, Mips::INS_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3__Tie0_1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_1 }, },
6925 { 5260 /* insert.b */, Mips::INSERT_B, Convert__MSA128AsmReg1_0__Tie0_1_1__GPR32AsmReg1_4__ConstantUImm4_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm4_0, MCK__93_, MCK_GPR32AsmReg }, },
6926 { 5269 /* insert.d */, Mips::INSERT_D, Convert__MSA128AsmReg1_0__Tie0_1_1__GPR64AsmReg1_4__ConstantUImm1_01_2, AMFBS_HasStdEnc_HasMSA_HasMips64, { MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm1_0, MCK__93_, MCK_GPR64AsmReg }, },
6927 { 5278 /* insert.h */, Mips::INSERT_H, Convert__MSA128AsmReg1_0__Tie0_1_1__GPR32AsmReg1_4__ConstantUImm3_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm3_0, MCK__93_, MCK_GPR32AsmReg }, },
6928 { 5287 /* insert.w */, Mips::INSERT_W, Convert__MSA128AsmReg1_0__Tie0_1_1__GPR32AsmReg1_4__ConstantUImm2_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm2_0, MCK__93_, MCK_GPR32AsmReg }, },
6929 { 5296 /* insv */, Mips::INSV_MM, Convert__GPR32AsmReg1_0__Tie0_1_1__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6930 { 5296 /* insv */, Mips::INSV, Convert__GPR32AsmReg1_0__Tie0_1_1__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6931 { 5301 /* insve.b */, Mips::INSVE_B, Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm4_01_2__MSA128AsmReg1_4__ConstantImmz1_6, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm4_0, MCK__93_, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantImmz, MCK__93_ }, },
6932 { 5309 /* insve.d */, Mips::INSVE_D, Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm1_01_2__MSA128AsmReg1_4__ConstantImmz1_6, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm1_0, MCK__93_, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantImmz, MCK__93_ }, },
6933 { 5317 /* insve.h */, Mips::INSVE_H, Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm3_01_2__MSA128AsmReg1_4__ConstantImmz1_6, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm3_0, MCK__93_, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantImmz, MCK__93_ }, },
6934 { 5325 /* insve.w */, Mips::INSVE_W, Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm2_01_2__MSA128AsmReg1_4__ConstantImmz1_6, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm2_0, MCK__93_, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantImmz, MCK__93_ }, },
6935 { 5333 /* j */, Mips::JR, Convert__GPR32AsmReg1_0, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg }, },
6936 { 5333 /* j */, Mips::JALR, Convert__regR31__GPR32AsmReg1_0, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg }, },
6937 { 5333 /* j */, Mips::JR_MM, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg }, },
6938 { 5333 /* j */, Mips::J_MM, Convert__Imm1_0, AMFBS_InMicroMips_NotMips32r6, { MCK_Imm }, },
6939 { 5333 /* j */, Mips::J, Convert__JumpTarget1_0, AMFBS_HasStdEnc_NotInMicroMips, { MCK_JumpTarget }, },
6940 { 5335 /* jal */, Mips::JalOneReg, Convert__GPR32AsmReg1_0, AMFBS_None, { MCK_GPR32AsmReg }, },
6941 { 5335 /* jal */, Mips::JAL_MM, Convert__Imm1_0, AMFBS_InMicroMips_NotMips32r6, { MCK_Imm }, },
6942 { 5335 /* jal */, Mips::JAL, Convert__JumpTarget1_0, AMFBS_HasStdEnc_NotInMicroMips, { MCK_JumpTarget }, },
6943 { 5335 /* jal */, Mips::BALC_MMR6, Convert__JumpTarget1_0, AMFBS_InMicroMips_HasMips32r6, { MCK_JumpTarget }, },
6944 { 5335 /* jal */, Mips::JalTwoReg, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_None, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6945 { 5339 /* jalr */, Mips::JALR16_MM, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg }, },
6946 { 5339 /* jalr */, Mips::JALRC16_MMR6, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg }, },
6947 { 5339 /* jalr */, Mips::JALR, Convert__regR31__GPR32AsmReg1_0, AMFBS_NotInMicroMips, { MCK_GPR32AsmReg }, },
6948 { 5339 /* jalr */, Mips::JALR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotInMicroMips_NoIndirectJumpGuards, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6949 { 5339 /* jalr */, Mips::JALR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6950 { 5339 /* jalr */, Mips::JALR64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_NotInMips16Mode_IsPTR64bit, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6951 { 5344 /* jalr.hb */, Mips::JALR_HB, Convert__regR31__GPR32AsmReg1_0, AMFBS_HasStdEnc_HasMips32_NotInMicroMips, { MCK_GPR32AsmReg }, },
6952 { 5344 /* jalr.hb */, Mips::JALR_HB_MM, Convert__regR31__GPR32AsmReg1_0, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg }, },
6953 { 5344 /* jalr.hb */, Mips::JALR_HB64, Convert__regR31_64__GPR64AsmReg1_0, AMFBS_HasStdEnc_HasMips64_NotInMicroMips, { MCK_GPR64AsmReg }, },
6954 { 5344 /* jalr.hb */, Mips::JALR_HB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips32, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6955 { 5344 /* jalr.hb */, Mips::JALR_HB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6956 { 5344 /* jalr.hb */, Mips::JALR_HB64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6957 { 5352 /* jalrc */, Mips::JumpLinkReg16, Convert__Reg1_0, AMFBS_InMips16Mode, { MCK_CPU16Regs }, },
6958 { 5352 /* jalrc */, Mips::JIALC, Convert__GPR32AsmReg1_0__imm_95_0, AMFBS_HasStdEnc_IsGP32bit_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg }, },
6959 { 5352 /* jalrc */, Mips::JALRC_MMR6, Convert__regR31__GPR32AsmReg1_0, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg }, },
6960 { 5352 /* jalrc */, Mips::JIALC64, Convert__GPR64AsmReg1_0__imm_95_0, AMFBS_HasStdEnc_HasMips64r6, { MCK_GPR64AsmReg }, },
6961 { 5352 /* jalrc */, Mips::JALRC_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6962 { 5358 /* jalrc.hb */, Mips::JALRC_HB_MMR6, Convert__regR31__GPR32AsmReg1_0, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg }, },
6963 { 5358 /* jalrc.hb */, Mips::JALRC_HB_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6964 { 5367 /* jalrs */, Mips::JALRS_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6965 { 5373 /* jalrs16 */, Mips::JALRS16_MM, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg }, },
6966 { 5381 /* jals */, Mips::JALS_MM, Convert__Imm1_0, AMFBS_InMicroMips_NotMips32r6, { MCK_Imm }, },
6967 { 5386 /* jalx */, Mips::JALX, Convert__JumpTarget1_0, AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_JumpTarget }, },
6968 { 5386 /* jalx */, Mips::JALX_MM, Convert__JumpTarget1_0, AMFBS_InMicroMips_NotMips32r6, { MCK_JumpTarget }, },
6969 { 5391 /* jialc */, Mips::JIALC, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
6970 { 5391 /* jialc */, Mips::JIALC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
6971 { 5391 /* jialc */, Mips::JIALC64, Convert__GPR64AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6, { MCK_GPR64AsmReg, MCK_JumpTarget }, },
6972 { 5397 /* jic */, Mips::JIC, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
6973 { 5397 /* jic */, Mips::JIC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
6974 { 5397 /* jic */, Mips::JIC64, Convert__GPR64AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6, { MCK_GPR64AsmReg, MCK_JumpTarget }, },
6975 { 5401 /* jr */, Mips::JrRa16, Convert_NoOperands, AMFBS_InMips16Mode, { MCK_CPURAReg }, },
6976 { 5401 /* jr */, Mips::JR, Convert__GPR32AsmReg1_0, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg }, },
6977 { 5401 /* jr */, Mips::JALR, Convert__regR0__GPR32AsmReg1_0, AMFBS_HasStdEnc_IsGP32bit_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg }, },
6978 { 5401 /* jr */, Mips::JR_MM, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg }, },
6979 { 5401 /* jr */, Mips::JR64, Convert__GPR64AsmReg1_0, AMFBS_NotInMips16Mode_IsPTR64bit_NotInMicroMips, { MCK_GPR64AsmReg }, },
6980 { 5401 /* jr */, Mips::JALR64, Convert__regR0_64__GPR64AsmReg1_0, AMFBS_HasStdEnc_HasMips64r6, { MCK_GPR64AsmReg }, },
6981 { 5404 /* jr.hb */, Mips::JR_HB, Convert__GPR32AsmReg1_0, AMFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg }, },
6982 { 5404 /* jr.hb */, Mips::JR_HB_MM, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg }, },
6983 { 5404 /* jr.hb */, Mips::JR_HB_R6, Convert__GPR32AsmReg1_0, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR32AsmReg }, },
6984 { 5404 /* jr.hb */, Mips::JR_HB64, Convert__GPR64AsmReg1_0, AMFBS_HasStdEnc_HasMips64_NotMips64r6_NotInMicroMips, { MCK_GPR64AsmReg }, },
6985 { 5404 /* jr.hb */, Mips::JR_HB64_R6, Convert__GPR64AsmReg1_0, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR64AsmReg }, },
6986 { 5410 /* jr16 */, Mips::JR16_MM, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg }, },
6987 { 5415 /* jraddiusp */, Mips::JRADDIUSP, Convert__UImm5Lsl21_0, AMFBS_InMicroMips_NotMips32r6, { MCK_UImm5Lsl2 }, },
6988 { 5425 /* jrc */, Mips::JrcRa16, Convert_NoOperands, AMFBS_InMips16Mode, { MCK_CPURAReg }, },
6989 { 5425 /* jrc */, Mips::JrcRx16, Convert__Reg1_0, AMFBS_InMips16Mode, { MCK_CPU16Regs }, },
6990 { 5425 /* jrc */, Mips::JIC, Convert__GPR32AsmReg1_0__imm_95_0, AMFBS_HasStdEnc_IsGP32bit_HasMips32r6, { MCK_GPR32AsmReg }, },
6991 { 5425 /* jrc */, Mips::JRC16_MM, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg }, },
6992 { 5425 /* jrc */, Mips::JIC64, Convert__GPR64AsmReg1_0__imm_95_0, AMFBS_HasStdEnc_HasMips64r6, { MCK_GPR64AsmReg }, },
6993 { 5429 /* jrc16 */, Mips::JRC16_MMR6, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg }, },
6994 { 5435 /* jrcaddiusp */, Mips::JRCADDIUSP_MMR6, Convert__UImm5Lsl21_0, AMFBS_InMicroMips_HasMips32r6, { MCK_UImm5Lsl2 }, },
6995 { 5446 /* l.d */, Mips::LDC1, Convert__AFGR64AsmReg1_0__PtrReg1_3__SImmOffset16_01_1, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_SImmOffset16_0, MCK__40_, MCK_PtrReg, MCK__41_ }, },
6996 { 5446 /* l.d */, Mips::LDC164, Convert__FGR64AsmReg1_0__PtrReg1_3__SImmOffset16_01_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_SImmOffset16_0, MCK__40_, MCK_PtrReg, MCK__41_ }, },
6997 { 5450 /* l.s */, Mips::LWC1, Convert__FGR32AsmReg1_0__PtrReg1_3__SImmOffset16_01_1, AMFBS_HasStdEnc_HasMips2_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_SImmOffset16_0, MCK__40_, MCK_PtrReg, MCK__41_ }, },
6998 { 5454 /* la */, Mips::LoadAddrImm32, Convert__GPR32AsmReg1_0__Imm1_1, AMFBS_None, { MCK_GPR32AsmReg, MCK_Imm }, },
6999 { 5454 /* la */, Mips::LoadAddrReg32, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_None, { MCK_GPR32AsmReg, MCK_Mem }, },
7000 { 5457 /* lapc */, Mips::ADDIUPC, Convert__GPR32AsmReg1_0__Simm19_Lsl21_1, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR32AsmReg, MCK_Simm19_Lsl2 }, },
7001 { 5457 /* lapc */, Mips::ADDIUPC_MMR6, Convert__GPR32AsmReg1_0__Simm19_Lsl21_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_Simm19_Lsl2 }, },
7002 { 5462 /* lb */, Mips::LB_MMR6, Convert__GPR32AsmReg1_0__PtrReg1_3__SImmOffset16_01_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_SImmOffset16_0, MCK__40_, MCK_PtrReg, MCK__41_ }, },
7003 { 5462 /* lb */, Mips::LB_MM, Convert__GPR32AsmReg1_0__PtrReg1_3__SImmOffset16_01_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_SImmOffset16_0, MCK__40_, MCK_PtrReg, MCK__41_ }, },
7004 { 5462 /* lb */, Mips::LB, Convert__GPR32AsmReg1_0__PtrReg1_3__SImmPtr1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImmPtr, MCK__40_, MCK_PtrReg, MCK__41_ }, },
7005 { 5465 /* lbe */, Mips::LBE, Convert__GPR32AsmReg1_0__PtrReg1_3__SImmOffset9_01_1, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImmOffset9_0, MCK__40_, MCK_PtrReg, MCK__41_ }, },
7006 { 5465 /* lbe */, Mips::LBE_MM, Convert__GPR32AsmReg1_0__PtrReg1_3__AnyOffset1_1, AMFBS_InMicroMips_HasEVA, { MCK_GPR32AsmReg, MCK_AnyOffset, MCK__40_, MCK_PtrReg, MCK__41_ }, },
7007 { 5469 /* lbu */, Mips::LBU_MMR6, Convert__GPR32AsmReg1_0__PtrReg1_3__SImmOffset16_01_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_SImmOffset16_0, MCK__40_, MCK_PtrReg, MCK__41_ }, },
7008 { 5469 /* lbu */, Mips::LBu_MM, Convert__GPR32AsmReg1_0__PtrReg1_3__SImmOffset16_01_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_SImmOffset16_0, MCK__40_, MCK_PtrReg, MCK__41_ }, },
7009 { 5469 /* lbu */, Mips::LBu, Convert__GPR32AsmReg1_0__PtrReg1_3__SImmPtr1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImmPtr, MCK__40_, MCK_PtrReg, MCK__41_ }, },
7010 { 5473 /* lbu16 */, Mips::LBU16_MM, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_3__UImmOffset4_0Minus11_1, AMFBS_InMicroMips, { MCK_GPRMM16AsmReg, MCK_UImmOffset4_0Minus1, MCK__40_, MCK_GPRMM16AsmReg, MCK__41_ }, },
7011 { 5479 /* lbue */, Mips::LBuE, Convert__GPR32AsmReg1_0__PtrReg1_3__SImmOffset9_01_1, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImmOffset9_0, MCK__40_, MCK_PtrReg, MCK__41_ }, },
7012 { 5479 /* lbue */, Mips::LBuE_MM, Convert__GPR32AsmReg1_0__PtrReg1_3__AnyOffset1_1, AMFBS_InMicroMips_HasEVA, { MCK_GPR32AsmReg, MCK_AnyOffset, MCK__40_, MCK_PtrReg, MCK__41_ }, },
7013 { 5484 /* lbux */, Mips::LBUX_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
7014 { 5484 /* lbux */, Mips::LBUX, Convert__GPR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
7015 { 5489 /* ld */, Mips::LDMacro, Convert__GPR32AsmReg1_0__PtrReg1_3__SImmOffset16_01_1, AMFBS_HasStdEnc_NotMips3, { MCK_GPR32AsmReg, MCK_SImmOffset16_0, MCK__40_, MCK_PtrReg, MCK__41_ }, },
7016 { 5489 /* ld */, Mips::LD, Convert__GPR64AsmReg1_0__PtrReg1_3__SImmPtr1_1, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_SImmPtr, MCK__40_, MCK_PtrReg, MCK__41_ }, },
7017 { 5492 /* ld.b */, Mips::LD_B, Convert__MSA128AsmReg1_0__PtrReg1_3__SImmOffset10_01_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_SImmOffset10_0, MCK__40_, MCK_PtrReg, MCK__41_ }, },
7018 { 5497 /* ld.d */, Mips::LD_D, Convert__MSA128AsmReg1_0__PtrReg1_3__SImmOffset10_31_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_SImmOffset10_3, MCK__40_, MCK_PtrReg, MCK__41_ }, },
7019 { 5502 /* ld.h */, Mips::LD_H, Convert__MSA128AsmReg1_0__PtrReg1_3__SImmOffset10_11_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_SImmOffset10_1, MCK__40_, MCK_PtrReg, MCK__41_ }, },
7020 { 5507 /* ld.w */, Mips::LD_W, Convert__MSA128AsmReg1_0__PtrReg1_3__SImmOffset10_21_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_SImmOffset10_2, MCK__40_, MCK_PtrReg, MCK__41_ }, },
7021 { 5512 /* ldc1 */, Mips::LDC1, Convert__AFGR64AsmReg1_0__PtrReg1_3__SImmOffset16_01_1, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_SImmOffset16_0, MCK__40_, MCK_PtrReg, MCK__41_ }, },
7022 { 5512 /* ldc1 */, Mips::LDC1_MM_D32, Convert__AFGR64AsmReg1_0__PtrReg1_3__SImmOffset16_01_1, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_SImmOffset16_0, MCK__40_, MCK_PtrReg, MCK__41_ }, },
7023 { 5512 /* ldc1 */, Mips::LDC164, Convert__FGR64AsmReg1_0__PtrReg1_3__SImmOffset16_01_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_SImmOffset16_0, MCK__40_, MCK_PtrReg, MCK__41_ }, },
7024 { 5512 /* ldc1 */, Mips::LDC1_D64_MMR6, Convert__FGR64AsmReg1_0__PtrReg1_3__SImmOffset16_01_1, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_SImmOffset16_0, MCK__40_, MCK_PtrReg, MCK__41_ }, },
7025 { 5512 /* ldc1 */, Mips::LDC1_MM_D64, Convert__FGR64AsmReg1_0__PtrReg1_3__SImmOffset16_01_1, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_SImmOffset16_0, MCK__40_, MCK_PtrReg, MCK__41_ }, },
7026 { 5517 /* ldc2 */, Mips::LDC2_R6, Convert__COP2AsmReg1_0__PtrReg1_3__SImmOffset11_01_1, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_COP2AsmReg, MCK_SImmOffset11_0, MCK__40_, MCK_PtrReg, MCK__41_ }, },
7027 { 5517 /* ldc2 */, Mips::LDC2_MMR6, Convert__COP2AsmReg1_0__PtrReg1_3__SImmOffset11_01_1, AMFBS_InMicroMips_HasMips32r6, { MCK_COP2AsmReg, MCK_SImmOffset11_0, MCK__40_, MCK_PtrReg, MCK__41_ }, },
7028 { 5517 /* ldc2 */, Mips::LDC2, Convert__COP2AsmReg1_0__PtrReg1_3__SImmOffset16_01_1, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_COP2AsmReg, MCK_SImmOffset16_0, MCK__40_, MCK_PtrReg, MCK__41_ }, },
7029 { 5522 /* ldc3 */, Mips::LDC3, Convert__COP3AsmReg1_0__PtrReg1_3__AnyOffset1_1, AMFBS_HasStdEnc_HasMips2_NotR5900_NotCnMips_NotInMicroMips, { MCK_COP3AsmReg, MCK_AnyOffset, MCK__40_, MCK_PtrReg, MCK__41_ }, },
7030 { 5527 /* ldi.b */, Mips::LDI_B, Convert__MSA128AsmReg1_0__ConstantSImm10_01_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_ConstantSImm10_0 }, },
7031 { 5533 /* ldi.d */, Mips::LDI_D, Convert__MSA128AsmReg1_0__ConstantSImm10_01_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_ConstantSImm10_0 }, },
7032 { 5539 /* ldi.h */, Mips::LDI_H, Convert__MSA128AsmReg1_0__ConstantSImm10_01_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_ConstantSImm10_0 }, },
7033 { 5545 /* ldi.w */, Mips::LDI_W, Convert__MSA128AsmReg1_0__ConstantSImm10_01_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_ConstantSImm10_0 }, },
7034 { 5551 /* ldl */, Mips::LDL, Convert__GPR64AsmReg1_0__PtrReg1_3__AnyOffset1_1__Tie0_1_1, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, { MCK_GPR64AsmReg, MCK_AnyOffset, MCK__40_, MCK_PtrReg, MCK__41_ }, },
7035 { 5555 /* ldpc */, Mips::LDPC, Convert__GPR64AsmReg1_0__Simm18_Lsl31_1, AMFBS_HasStdEnc_HasMips64r6, { MCK_GPR64AsmReg, MCK_Simm18_Lsl3 }, },
7036 { 5560 /* ldr */, Mips::LDR, Convert__GPR64AsmReg1_0__PtrReg1_3__AnyOffset1_1__Tie0_1_1, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, { MCK_GPR64AsmReg, MCK_AnyOffset, MCK__40_, MCK_PtrReg, MCK__41_ }, },
7037 { 5564 /* ldxc1 */, Mips::LDXC1, Convert__AFGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
7038 { 5564 /* ldxc1 */, Mips::LDXC164, Convert__FGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
7039 { 5570 /* lh */, Mips::LH, Convert__GPR32AsmReg1_0__PtrReg1_3__SImmPtr1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImmPtr, MCK__40_, MCK_PtrReg, MCK__41_ }, },
7040 { 5570 /* lh */, Mips::LH_MM, Convert__GPR32AsmReg1_0__PtrReg1_3__SImmPtr1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_SImmPtr, MCK__40_, MCK_PtrReg, MCK__41_ }, },
7041 { 5573 /* lhe */, Mips::LHE, Convert__GPR32AsmReg1_0__PtrReg1_3__SImmOffset9_01_1, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImmOffset9_0, MCK__40_, MCK_PtrReg, MCK__41_ }, },
7042 { 5573 /* lhe */, Mips::LHE_MM, Convert__GPR32AsmReg1_0__PtrReg1_3__SImmOffset9_01_1, AMFBS_InMicroMips_HasEVA, { MCK_GPR32AsmReg, MCK_SImmOffset9_0, MCK__40_, MCK_PtrReg, MCK__41_ }, },
7043 { 5577 /* lhu */, Mips::LHu, Convert__GPR32AsmReg1_0__PtrReg1_3__SImmPtr1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImmPtr, MCK__40_, MCK_PtrReg, MCK__41_ }, },
7044 { 5577 /* lhu */, Mips::LHu_MM, Convert__GPR32AsmReg1_0__PtrReg1_3__SImmPtr1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_SImmPtr, MCK__40_, MCK_PtrReg, MCK__41_ }, },
7045 { 5581 /* lhu16 */, Mips::LHU16_MM, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_3__UImmOffset4_101_1, AMFBS_InMicroMips, { MCK_GPRMM16AsmReg, MCK_UImmOffset4_10, MCK__40_, MCK_GPRMM16AsmReg, MCK__41_ }, },
7046 { 5587 /* lhue */, Mips::LHuE, Convert__GPR32AsmReg1_0__PtrReg1_3__SImmOffset9_01_1, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImmOffset9_0, MCK__40_, MCK_PtrReg, MCK__41_ }, },
7047 { 5587 /* lhue */, Mips::LHuE_MM, Convert__GPR32AsmReg1_0__PtrReg1_3__SImmOffset9_01_1, AMFBS_InMicroMips_HasEVA, { MCK_GPR32AsmReg, MCK_SImmOffset9_0, MCK__40_, MCK_PtrReg, MCK__41_ }, },
7048 { 5592 /* lhx */, Mips::LHX_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
7049 { 5592 /* lhx */, Mips::LHX, Convert__GPR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
7050 { 5596 /* li */, Mips::LiRxImmX16, Convert__Reg1_0__SImm161_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_SImm16 }, },
7051 { 5596 /* li */, Mips::LoadImm32, Convert__GPR32AsmReg1_0__UImm32_Coerced1_1, AMFBS_None, { MCK_GPR32AsmReg, MCK_UImm32_Coerced }, },
7052 { 5596 /* li */, Mips::LiRxImm16, Convert__Reg1_0__SImm161_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_SImm16, MCK__HASH_, MCK_16, MCK_bit, MCK_inst }, },
7053 { 5599 /* li.d */, Mips::LoadImmDoubleGPR, Convert__GPR32AsmReg1_0__Imm1_1, AMFBS_None, { MCK_GPR32AsmReg, MCK_Imm }, },
7054 { 5599 /* li.d */, Mips::LoadImmDoubleFGR_32, Convert__StrictlyAFGR64AsmReg1_0__Imm1_1, AMFBS_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat, { MCK_StrictlyAFGR64AsmReg, MCK_Imm }, },
7055 { 5599 /* li.d */, Mips::LoadImmDoubleFGR, Convert__StrictlyFGR64AsmReg1_0__Imm1_1, AMFBS_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat, { MCK_StrictlyFGR64AsmReg, MCK_Imm }, },
7056 { 5604 /* li.s */, Mips::LoadImmSingleGPR, Convert__GPR32AsmReg1_0__Imm1_1, AMFBS_None, { MCK_GPR32AsmReg, MCK_Imm }, },
7057 { 5604 /* li.s */, Mips::LoadImmSingleFGR, Convert__StrictlyFGR32AsmReg1_0__Imm1_1, AMFBS_IsNotSoftFloat, { MCK_StrictlyFGR32AsmReg, MCK_Imm }, },
7058 { 5609 /* li16 */, Mips::LI16_MM, Convert__GPRMM16AsmReg1_0__UImm7_N11_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_UImm7_N1 }, },
7059 { 5609 /* li16 */, Mips::LI16_MMR6, Convert__GPRMM16AsmReg1_0__UImm7_N11_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_UImm7_N1 }, },
7060 { 5614 /* ll */, Mips::LL_MMR6, Convert__GPR32AsmReg1_0__PtrReg1_3__SImmOffset9_01_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_SImmOffset9_0, MCK__40_, MCK_PtrReg, MCK__41_ }, },
7061 { 5614 /* ll */, Mips::LL64_R6, Convert__GPR32AsmReg1_0__PtrReg1_3__SImmPtr1_1, AMFBS_HasStdEnc_IsPTR64bit_HasMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImmPtr, MCK__40_, MCK_PtrReg, MCK__41_ }, },
7062 { 5614 /* ll */, Mips::LL_R6, Convert__GPR32AsmReg1_0__PtrReg1_3__SImmPtr1_1, AMFBS_HasStdEnc_IsPTR32bit_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImmPtr, MCK__40_, MCK_PtrReg, MCK__41_ }, },
7063 { 5614 /* ll */, Mips::LL, Convert__GPR32AsmReg1_0__PtrReg1_3__AnyOffset1_1, AMFBS_HasStdEnc_IsPTR32bit_HasMips2_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips, { MCK_GPR32AsmReg, MCK_AnyOffset, MCK__40_, MCK_PtrReg, MCK__41_ }, },
7064 { 5614 /* ll */, Mips::LL64, Convert__GPR32AsmReg1_0__PtrReg1_3__AnyOffset1_1, AMFBS_HasStdEnc_IsPTR64bit_HasMips2_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips, { MCK_GPR32AsmReg, MCK_AnyOffset, MCK__40_, MCK_PtrReg, MCK__41_ }, },
7065 { 5614 /* ll */, Mips::LL_MM, Convert__GPR32AsmReg1_0__PtrReg1_3__AnyOffset1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_AnyOffset, MCK__40_, MCK_PtrReg, MCK__41_ }, },
7066 { 5617 /* lld */, Mips::LLD, Convert__GPR64AsmReg1_0__PtrReg1_3__SImmPtr1_1, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips, { MCK_GPR64AsmReg, MCK_SImmPtr, MCK__40_, MCK_PtrReg, MCK__41_ }, },
7067 { 5617 /* lld */, Mips::LLD_R6, Convert__GPR64AsmReg1_0__PtrReg1_3__SImmPtr1_1, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_SImmPtr, MCK__40_, MCK_PtrReg, MCK__41_ }, },
7068 { 5621 /* lle */, Mips::LLE, Convert__GPR32AsmReg1_0__PtrReg1_3__SImmOffset9_01_1, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImmOffset9_0, MCK__40_, MCK_PtrReg, MCK__41_ }, },
7069 { 5621 /* lle */, Mips::LLE_MM, Convert__GPR32AsmReg1_0__PtrReg1_3__SImmOffset9_01_1, AMFBS_InMicroMips_HasEVA, { MCK_GPR32AsmReg, MCK_SImmOffset9_0, MCK__40_, MCK_PtrReg, MCK__41_ }, },
7070 { 5625 /* lsa */, Mips::LSA, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__ConstantUImm2_11_3, AMFBS_HasStdEnc_HasMSA, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm2_1 }, },
7071 { 5625 /* lsa */, Mips::LSA_MMR6, Convert__GPR32AsmReg1_2__GPR32AsmReg1_1__GPR32AsmReg1_0__ConstantUImm2_11_3, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm2_1 }, },
7072 { 5625 /* lsa */, Mips::LSA_R6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__ConstantUImm2_11_3, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm2_1 }, },
7073 { 5629 /* lui */, Mips::LUI_MMR6, Convert__GPR32AsmReg1_0__UImm161_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_UImm16 }, },
7074 { 5629 /* lui */, Mips::LUi, Convert__GPR32AsmReg1_0__UImm16_Relaxed1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_UImm16_Relaxed }, },
7075 { 5629 /* lui */, Mips::LUi_MM, Convert__GPR32AsmReg1_0__UImm16_Relaxed1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_UImm16_Relaxed }, },
7076 { 5633 /* luxc1 */, Mips::LUXC1, Convert__AFGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
7077 { 5633 /* luxc1 */, Mips::LUXC164, Convert__FGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
7078 { 5633 /* luxc1 */, Mips::LUXC1_MM, Convert__FGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
7079 { 5639 /* lw */, Mips::LwRxPcTcpX16, Convert__Reg1_0__Imm1_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_Imm }, },
7080 { 5639 /* lw */, Mips::LwRxSpImmX16, Convert__Reg1_0__Reg1_3__SImm161_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_SImm16, MCK__40_, MCK_CPU16RegsPlusSP, MCK__41_ }, },
7081 { 5639 /* lw */, Mips::LWSP_MM, Convert__GPR32AsmReg1_0__MemBaseSP1_3__UImmOffset5_201_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_UImmOffset5_20, MCK__40_, MCK_MemBaseSP, MCK__41_ }, },
7082 { 5639 /* lw */, Mips::LW, Convert__GPR32AsmReg1_0__PtrReg1_3__AnyOffset1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_AnyOffset, MCK__40_, MCK_PtrReg, MCK__41_ }, },
7083 { 5639 /* lw */, Mips::LWDSP, Convert__GPR32AsmReg1_0__PtrReg1_3__AnyOffset1_1, AMFBS_NotInMips16Mode_HasDSP, { MCK_GPR32AsmReg, MCK_AnyOffset, MCK__40_, MCK_PtrReg, MCK__41_ }, },
7084 { 5639 /* lw */, Mips::LWDSP_MM, Convert__GPR32AsmReg1_0__PtrReg1_3__AnyOffset1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_AnyOffset, MCK__40_, MCK_PtrReg, MCK__41_ }, },
7085 { 5639 /* lw */, Mips::LW_MMR6, Convert__GPR32AsmReg1_0__PtrReg1_3__AnyOffset1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_AnyOffset, MCK__40_, MCK_PtrReg, MCK__41_ }, },
7086 { 5639 /* lw */, Mips::LW_MM, Convert__GPR32AsmReg1_0__PtrReg1_3__AnyOffset1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_AnyOffset, MCK__40_, MCK_PtrReg, MCK__41_ }, },
7087 { 5639 /* lw */, Mips::LWGP_MM, Convert__GPRMM16AsmReg1_0__MemBaseGP1_3__SImmOffset7_21_1, AMFBS_InMicroMips, { MCK_GPRMM16AsmReg, MCK_SImmOffset7_2, MCK__40_, MCK_MemBaseGP, MCK__41_ }, },
7088 { 5639 /* lw */, Mips::LwRxPcTcp16, Convert__Reg1_0__Imm1_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_Imm, MCK__HASH_, MCK_16, MCK_bit, MCK_inst }, },
7089 { 5642 /* lw16 */, Mips::LW16_MM, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_3__UImmOffset4_201_1, AMFBS_InMicroMips, { MCK_GPRMM16AsmReg, MCK_UImmOffset4_20, MCK__40_, MCK_GPRMM16AsmReg, MCK__41_ }, },
7090 { 5647 /* lwc1 */, Mips::LWC1, Convert__FGR32AsmReg1_0__PtrReg1_3__SImmOffset16_01_1, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_SImmOffset16_0, MCK__40_, MCK_PtrReg, MCK__41_ }, },
7091 { 5647 /* lwc1 */, Mips::LWC1_MM, Convert__FGR32AsmReg1_0__PtrReg1_3__SImmOffset16_01_1, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_SImmOffset16_0, MCK__40_, MCK_PtrReg, MCK__41_ }, },
7092 { 5652 /* lwc2 */, Mips::LWC2_R6, Convert__COP2AsmReg1_0__PtrReg1_3__SImmOffset11_01_1, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_COP2AsmReg, MCK_SImmOffset11_0, MCK__40_, MCK_PtrReg, MCK__41_ }, },
7093 { 5652 /* lwc2 */, Mips::LWC2_MMR6, Convert__COP2AsmReg1_0__PtrReg1_3__SImmOffset11_01_1, AMFBS_InMicroMips_HasMips32r6, { MCK_COP2AsmReg, MCK_SImmOffset11_0, MCK__40_, MCK_PtrReg, MCK__41_ }, },
7094 { 5652 /* lwc2 */, Mips::LWC2, Convert__COP2AsmReg1_0__PtrReg1_3__SImmOffset16_01_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_COP2AsmReg, MCK_SImmOffset16_0, MCK__40_, MCK_PtrReg, MCK__41_ }, },
7095 { 5657 /* lwc3 */, Mips::LWC3, Convert__COP3AsmReg1_0__PtrReg1_3__AnyOffset1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_NotCnMips_NotInMicroMips, { MCK_COP3AsmReg, MCK_AnyOffset, MCK__40_, MCK_PtrReg, MCK__41_ }, },
7096 { 5662 /* lwe */, Mips::LWE, Convert__GPR32AsmReg1_0__PtrReg1_3__SImmOffset9_01_1, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImmOffset9_0, MCK__40_, MCK_PtrReg, MCK__41_ }, },
7097 { 5662 /* lwe */, Mips::LWE_MM, Convert__GPR32AsmReg1_0__PtrReg1_3__SImmOffset9_01_1, AMFBS_InMicroMips_HasEVA, { MCK_GPR32AsmReg, MCK_SImmOffset9_0, MCK__40_, MCK_PtrReg, MCK__41_ }, },
7098 { 5666 /* lwl */, Mips::LWL, Convert__GPR32AsmReg1_0__PtrReg1_3__AnyOffset1_1__Tie0_1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_AnyOffset, MCK__40_, MCK_PtrReg, MCK__41_ }, },
7099 { 5666 /* lwl */, Mips::LWL_MM, Convert__GPR32AsmReg1_0__PtrReg1_3__AnyOffset1_1__Tie0_1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_AnyOffset, MCK__40_, MCK_PtrReg, MCK__41_ }, },
7100 { 5670 /* lwle */, Mips::LWLE, Convert__GPR32AsmReg1_0__PtrReg1_3__SImmOffset9_01_1__Tie0_1_1, AMFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImmOffset9_0, MCK__40_, MCK_PtrReg, MCK__41_ }, },
7101 { 5670 /* lwle */, Mips::LWLE_MM, Convert__GPR32AsmReg1_0__PtrReg1_3__SImmOffset9_01_1__Tie0_1_1, AMFBS_InMicroMips_NotMips32r6_HasEVA, { MCK_GPR32AsmReg, MCK_SImmOffset9_0, MCK__40_, MCK_PtrReg, MCK__41_ }, },
7102 { 5675 /* lwm */, Mips::LWM_MM, Convert__RegList1_0__PtrReg1_3__AnyOffset1_1, AMFBS_InMicroMips, { MCK_RegList, MCK_AnyOffset, MCK__40_, MCK_PtrReg, MCK__41_ }, },
7103 { 5679 /* lwm16 */, Mips::LWM16_MMR6, Convert__RegList161_0__MemBaseSP1_3__UImmOffset4_201_1, AMFBS_InMicroMips_HasMips32r6, { MCK_RegList16, MCK_UImmOffset4_20, MCK__40_, MCK_MemBaseSP, MCK__41_ }, },
7104 { 5679 /* lwm16 */, Mips::LWM16_MM, Convert__RegList161_0__MemBaseSP1_3__UImmOffset6_001_1, AMFBS_InMicroMips_NotMips32r6, { MCK_RegList16, MCK_UImmOffset6_00, MCK__40_, MCK_MemBaseSP, MCK__41_ }, },
7105 { 5685 /* lwm32 */, Mips::LWM32_MM, Convert__RegList1_0__PtrReg1_3__AnyOffset1_1, AMFBS_InMicroMips, { MCK_RegList, MCK_AnyOffset, MCK__40_, MCK_PtrReg, MCK__41_ }, },
7106 { 5691 /* lwp */, Mips::LWP_MM, ConvertCustom_ConvertXWPOperands, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_SImmOffset12_0, MCK__40_, MCK_PtrReg, MCK__41_ }, },
7107 { 5695 /* lwpc */, Mips::LWPC, Convert__GPR32AsmReg1_0__Simm19_Lsl21_1, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR32AsmReg, MCK_Simm19_Lsl2 }, },
7108 { 5695 /* lwpc */, Mips::LWPC_MMR6, Convert__GPR32AsmReg1_0__Simm19_Lsl21_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_Simm19_Lsl2 }, },
7109 { 5700 /* lwr */, Mips::LWR, Convert__GPR32AsmReg1_0__PtrReg1_3__AnyOffset1_1__Tie0_1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_AnyOffset, MCK__40_, MCK_PtrReg, MCK__41_ }, },
7110 { 5700 /* lwr */, Mips::LWR_MM, Convert__GPR32AsmReg1_0__PtrReg1_3__AnyOffset1_1__Tie0_1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_AnyOffset, MCK__40_, MCK_PtrReg, MCK__41_ }, },
7111 { 5704 /* lwre */, Mips::LWRE, Convert__GPR32AsmReg1_0__PtrReg1_3__SImmOffset9_01_1__Tie0_1_1, AMFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImmOffset9_0, MCK__40_, MCK_PtrReg, MCK__41_ }, },
7112 { 5704 /* lwre */, Mips::LWRE_MM, Convert__GPR32AsmReg1_0__PtrReg1_3__SImmOffset9_01_1__Tie0_1_1, AMFBS_InMicroMips_NotMips32r6_HasEVA, { MCK_GPR32AsmReg, MCK_SImmOffset9_0, MCK__40_, MCK_PtrReg, MCK__41_ }, },
7113 { 5709 /* lwu */, Mips::LWU_MM, Convert__GPR32AsmReg1_0__PtrReg1_3__SImmOffset12_01_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_SImmOffset12_0, MCK__40_, MCK_PtrReg, MCK__41_ }, },
7114 { 5709 /* lwu */, Mips::LWu, Convert__GPR64AsmReg1_0__PtrReg1_3__AnyOffset1_1, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_AnyOffset, MCK__40_, MCK_PtrReg, MCK__41_ }, },
7115 { 5713 /* lwupc */, Mips::LWUPC, Convert__GPR32AsmReg1_0__Simm19_Lsl21_1, AMFBS_HasStdEnc_HasMips64r6, { MCK_GPR32AsmReg, MCK_Simm19_Lsl2 }, },
7116 { 5719 /* lwx */, Mips::LWX_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
7117 { 5719 /* lwx */, Mips::LWX, Convert__GPR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
7118 { 5723 /* lwxc1 */, Mips::LWXC1, Convert__FGR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
7119 { 5723 /* lwxc1 */, Mips::LWXC1_MM, Convert__FGR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
7120 { 5729 /* lwxs */, Mips::LWXS_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
7121 { 5734 /* madd */, Mips::MADD, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7122 { 5734 /* madd */, Mips::MADD_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7123 { 5734 /* madd */, Mips::MADD_DSP_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7124 { 5734 /* madd */, Mips::MADD_DSP, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7125 { 5739 /* madd.d */, Mips::MADD_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2__AFGR64AsmReg1_3, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
7126 { 5739 /* madd.d */, Mips::MADD_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2__AFGR64AsmReg1_3, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat_HasMadd4, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
7127 { 5739 /* madd.d */, Mips::MADD_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2__FGR64AsmReg1_3, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7128 { 5746 /* madd.s */, Mips::MADD_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2__FGR32AsmReg1_3, AMFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7129 { 5746 /* madd.s */, Mips::MADD_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2__FGR32AsmReg1_3, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat_HasMadd4, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7130 { 5753 /* madd_q.h */, Mips::MADD_Q_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7131 { 5762 /* madd_q.w */, Mips::MADD_Q_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7132 { 5771 /* maddf.d */, Mips::MADDF_D, Convert__FGR64AsmReg1_0__Tie0_1_1__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7133 { 5771 /* maddf.d */, Mips::MADDF_D_MMR6, Convert__FGR64AsmReg1_0__Tie0_1_1__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7134 { 5779 /* maddf.s */, Mips::MADDF_S, Convert__FGR32AsmReg1_0__Tie0_1_1__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7135 { 5779 /* maddf.s */, Mips::MADDF_S_MMR6, Convert__FGR32AsmReg1_0__Tie0_1_1__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7136 { 5787 /* maddr_q.h */, Mips::MADDR_Q_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7137 { 5797 /* maddr_q.w */, Mips::MADDR_Q_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7138 { 5807 /* maddu */, Mips::MADDU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7139 { 5807 /* maddu */, Mips::MADDU_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7140 { 5807 /* maddu */, Mips::MADDU_DSP_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7141 { 5807 /* maddu */, Mips::MADDU_DSP, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7142 { 5813 /* maddv.b */, Mips::MADDV_B, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7143 { 5821 /* maddv.d */, Mips::MADDV_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7144 { 5829 /* maddv.h */, Mips::MADDV_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7145 { 5837 /* maddv.w */, Mips::MADDV_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7146 { 5845 /* maq_s.w.phl */, Mips::MAQ_S_W_PHL_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7147 { 5845 /* maq_s.w.phl */, Mips::MAQ_S_W_PHL, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7148 { 5857 /* maq_s.w.phr */, Mips::MAQ_S_W_PHR_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7149 { 5857 /* maq_s.w.phr */, Mips::MAQ_S_W_PHR, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7150 { 5869 /* maq_sa.w.phl */, Mips::MAQ_SA_W_PHL_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7151 { 5869 /* maq_sa.w.phl */, Mips::MAQ_SA_W_PHL, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7152 { 5882 /* maq_sa.w.phr */, Mips::MAQ_SA_W_PHR_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7153 { 5882 /* maq_sa.w.phr */, Mips::MAQ_SA_W_PHR, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7154 { 5895 /* max.d */, Mips::MAX_D, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7155 { 5895 /* max.d */, Mips::MAX_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7156 { 5901 /* max.s */, Mips::MAX_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7157 { 5901 /* max.s */, Mips::MAX_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7158 { 5907 /* max_a.b */, Mips::MAX_A_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7159 { 5915 /* max_a.d */, Mips::MAX_A_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7160 { 5923 /* max_a.h */, Mips::MAX_A_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7161 { 5931 /* max_a.w */, Mips::MAX_A_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7162 { 5939 /* max_s.b */, Mips::MAX_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7163 { 5947 /* max_s.d */, Mips::MAX_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7164 { 5955 /* max_s.h */, Mips::MAX_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7165 { 5963 /* max_s.w */, Mips::MAX_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7166 { 5971 /* max_u.b */, Mips::MAX_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7167 { 5979 /* max_u.d */, Mips::MAX_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7168 { 5987 /* max_u.h */, Mips::MAX_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7169 { 5995 /* max_u.w */, Mips::MAX_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7170 { 6003 /* maxa.d */, Mips::MAXA_D, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7171 { 6003 /* maxa.d */, Mips::MAXA_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7172 { 6010 /* maxa.s */, Mips::MAXA_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7173 { 6010 /* maxa.s */, Mips::MAXA_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7174 { 6017 /* maxi_s.b */, Mips::MAXI_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
7175 { 6026 /* maxi_s.d */, Mips::MAXI_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
7176 { 6035 /* maxi_s.h */, Mips::MAXI_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
7177 { 6044 /* maxi_s.w */, Mips::MAXI_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
7178 { 6053 /* maxi_u.b */, Mips::MAXI_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
7179 { 6062 /* maxi_u.d */, Mips::MAXI_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
7180 { 6071 /* maxi_u.h */, Mips::MAXI_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
7181 { 6080 /* maxi_u.w */, Mips::MAXI_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
7182 { 6089 /* mfc0 */, Mips::MFC0, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__imm_95_0, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, },
7183 { 6089 /* mfc0 */, Mips::MFC0_MM, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__imm_95_0, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, },
7184 { 6089 /* mfc0 */, Mips::MFC0_MMR6, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__imm_95_0, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, },
7185 { 6089 /* mfc0 */, Mips::MFC0, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
7186 { 6089 /* mfc0 */, Mips::MFC0_MM, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
7187 { 6089 /* mfc0 */, Mips::MFC0_MMR6, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
7188 { 6094 /* mfc1 */, Mips::MFC1, Convert__GPR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, { MCK_GPR32AsmReg, MCK_FGR32AsmReg }, },
7189 { 6094 /* mfc1 */, Mips::MFC1_MMR6, Convert__GPR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_FGR32AsmReg }, },
7190 { 6094 /* mfc1 */, Mips::MFC1_MM, Convert__GPR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_FGR32AsmReg }, },
7191 { 6094 /* mfc1 */, Mips::MFC1_D64, Convert__GPR32AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips, { MCK_GPR32AsmReg, MCK_FGR64AsmReg }, },
7192 { 6099 /* mfc2 */, Mips::MFC2_MMR6, Convert__GPR32AsmReg1_0__COP2AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP2AsmReg }, },
7193 { 6099 /* mfc2 */, Mips::MFC2, Convert__GPR32AsmReg1_0__COP2AsmReg1_1__imm_95_0, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP2AsmReg }, },
7194 { 6099 /* mfc2 */, Mips::MFC2, Convert__GPR32AsmReg1_0__COP2AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP2AsmReg, MCK_ConstantUImm3_0 }, },
7195 { 6104 /* mfgc0 */, Mips::MFGC0, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__imm_95_0, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, },
7196 { 6104 /* mfgc0 */, Mips::MFGC0_MM, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__imm_95_0, AMFBS_InMicroMips_HasMips32r5_HasVirt, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, },
7197 { 6104 /* mfgc0 */, Mips::MFGC0, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
7198 { 6104 /* mfgc0 */, Mips::MFGC0_MM, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2, AMFBS_InMicroMips_HasMips32r5_HasVirt, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
7199 { 6110 /* mfhc0 */, Mips::MFHC0_MMR6, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__imm_95_0, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, },
7200 { 6110 /* mfhc0 */, Mips::MFHC0_MMR6, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
7201 { 6116 /* mfhc1 */, Mips::MFHC1_D32, Convert__GPR32AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips32r2_IsNotSoftFloat_NotInMicroMips, { MCK_GPR32AsmReg, MCK_AFGR64AsmReg }, },
7202 { 6116 /* mfhc1 */, Mips::MFHC1_D32_MM, Convert__GPR32AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_AFGR64AsmReg }, },
7203 { 6116 /* mfhc1 */, Mips::MFHC1_D64, Convert__GPR32AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips32r2_IsNotSoftFloat_NotInMicroMips, { MCK_GPR32AsmReg, MCK_FGR64AsmReg }, },
7204 { 6116 /* mfhc1 */, Mips::MFHC1_D64_MM, Convert__GPR32AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_FGR64AsmReg }, },
7205 { 6122 /* mfhc2 */, Mips::MFHC2_MMR6, Convert__GPR32AsmReg1_0__COP2AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP2AsmReg }, },
7206 { 6128 /* mfhgc0 */, Mips::MFHGC0, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__imm_95_0, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, },
7207 { 6128 /* mfhgc0 */, Mips::MFHGC0_MM, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__imm_95_0, AMFBS_InMicroMips_HasMips32r5_HasVirt, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, },
7208 { 6128 /* mfhgc0 */, Mips::MFHGC0, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
7209 { 6128 /* mfhgc0 */, Mips::MFHGC0_MM, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2, AMFBS_InMicroMips_HasMips32r5_HasVirt, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
7210 { 6135 /* mfhi */, Mips::Mfhi16, Convert__Reg1_0, AMFBS_InMips16Mode, { MCK_CPU16Regs }, },
7211 { 6135 /* mfhi */, Mips::MFHI, Convert__GPR32AsmReg1_0, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg }, },
7212 { 6135 /* mfhi */, Mips::MFHI_MM, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg }, },
7213 { 6135 /* mfhi */, Mips::MFHI_DSP_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, },
7214 { 6135 /* mfhi */, Mips::MFHI_DSP, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, },
7215 { 6140 /* mfhi16 */, Mips::MFHI16_MM, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg }, },
7216 { 6147 /* mflo */, Mips::Mflo16, Convert__Reg1_0, AMFBS_InMips16Mode, { MCK_CPU16Regs }, },
7217 { 6147 /* mflo */, Mips::MFLO, Convert__GPR32AsmReg1_0, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg }, },
7218 { 6147 /* mflo */, Mips::MFLO_MM, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg }, },
7219 { 6147 /* mflo */, Mips::MFLO_DSP_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, },
7220 { 6147 /* mflo */, Mips::MFLO_DSP, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, },
7221 { 6152 /* mflo16 */, Mips::MFLO16_MM, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg }, },
7222 { 6159 /* mftacx */, Mips::MFTACX, Convert__GPR32AsmReg1_0__regAC0, AMFBS_HasMT_NotInMicroMips, { MCK_GPR32AsmReg }, },
7223 { 6159 /* mftacx */, Mips::MFTACX, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1, AMFBS_HasMT, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, },
7224 { 6166 /* mftc0 */, Mips::MFTC0, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__imm_95_0, AMFBS_HasMT_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, },
7225 { 6166 /* mftc0 */, Mips::MFTC0, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasMT, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
7226 { 6172 /* mftc1 */, Mips::MFTC1, Convert__GPR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasMT, { MCK_GPR32AsmReg, MCK_FGR32AsmReg }, },
7227 { 6178 /* mftdsp */, Mips::MFTDSP, Convert__GPR32AsmReg1_0, AMFBS_HasMT, { MCK_GPR32AsmReg }, },
7228 { 6185 /* mftgpr */, Mips::MFTGPR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, AMFBS_HasMT, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7229 { 6192 /* mfthc1 */, Mips::MFTHC1, Convert__GPR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasMT, { MCK_GPR32AsmReg, MCK_FGR32AsmReg }, },
7230 { 6199 /* mfthi */, Mips::MFTHI, Convert__GPR32AsmReg1_0__regAC0, AMFBS_HasMT_NotInMicroMips, { MCK_GPR32AsmReg }, },
7231 { 6199 /* mfthi */, Mips::MFTHI, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1, AMFBS_HasMT, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, },
7232 { 6205 /* mftlo */, Mips::MFTLO, Convert__GPR32AsmReg1_0__regAC0, AMFBS_HasMT_NotInMicroMips, { MCK_GPR32AsmReg }, },
7233 { 6205 /* mftlo */, Mips::MFTLO, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1, AMFBS_HasMT, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, },
7234 { 6211 /* mftr */, Mips::MFTR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm1_01_2__ConstantUImm3_01_3__ConstantUImm1_01_4, AMFBS_HasStdEnc_HasMT_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm1_0, MCK_ConstantUImm3_0, MCK_ConstantUImm1_0 }, },
7235 { 6216 /* min.d */, Mips::MIN_D, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7236 { 6216 /* min.d */, Mips::MIN_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7237 { 6222 /* min.s */, Mips::MIN_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7238 { 6222 /* min.s */, Mips::MIN_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7239 { 6228 /* min_a.b */, Mips::MIN_A_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7240 { 6236 /* min_a.d */, Mips::MIN_A_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7241 { 6244 /* min_a.h */, Mips::MIN_A_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7242 { 6252 /* min_a.w */, Mips::MIN_A_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7243 { 6260 /* min_s.b */, Mips::MIN_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7244 { 6268 /* min_s.d */, Mips::MIN_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7245 { 6276 /* min_s.h */, Mips::MIN_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7246 { 6284 /* min_s.w */, Mips::MIN_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7247 { 6292 /* min_u.b */, Mips::MIN_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7248 { 6300 /* min_u.d */, Mips::MIN_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7249 { 6308 /* min_u.h */, Mips::MIN_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7250 { 6316 /* min_u.w */, Mips::MIN_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7251 { 6324 /* mina.d */, Mips::MINA_D, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7252 { 6324 /* mina.d */, Mips::MINA_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7253 { 6331 /* mina.s */, Mips::MINA_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7254 { 6331 /* mina.s */, Mips::MINA_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7255 { 6338 /* mini_s.b */, Mips::MINI_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
7256 { 6347 /* mini_s.d */, Mips::MINI_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
7257 { 6356 /* mini_s.h */, Mips::MINI_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
7258 { 6365 /* mini_s.w */, Mips::MINI_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
7259 { 6374 /* mini_u.b */, Mips::MINI_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
7260 { 6383 /* mini_u.d */, Mips::MINI_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
7261 { 6392 /* mini_u.h */, Mips::MINI_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
7262 { 6401 /* mini_u.w */, Mips::MINI_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
7263 { 6410 /* mod */, Mips::MOD, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7264 { 6410 /* mod */, Mips::MOD_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7265 { 6414 /* mod_s.b */, Mips::MOD_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7266 { 6422 /* mod_s.d */, Mips::MOD_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7267 { 6430 /* mod_s.h */, Mips::MOD_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7268 { 6438 /* mod_s.w */, Mips::MOD_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7269 { 6446 /* mod_u.b */, Mips::MOD_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7270 { 6454 /* mod_u.d */, Mips::MOD_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7271 { 6462 /* mod_u.h */, Mips::MOD_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7272 { 6470 /* mod_u.w */, Mips::MOD_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7273 { 6478 /* modsub */, Mips::MODSUB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7274 { 6478 /* modsub */, Mips::MODSUB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7275 { 6485 /* modu */, Mips::MODU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7276 { 6485 /* modu */, Mips::MODU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7277 { 6490 /* mov.d */, Mips::FMOV_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
7278 { 6490 /* mov.d */, Mips::FMOV_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
7279 { 6490 /* mov.d */, Mips::FMOV_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7280 { 6490 /* mov.d */, Mips::FMOV_D64_MM, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7281 { 6490 /* mov.d */, Mips::FMOV_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7282 { 6496 /* mov.s */, Mips::FMOV_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7283 { 6496 /* mov.s */, Mips::FMOV_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7284 { 6496 /* mov.s */, Mips::FMOV_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7285 { 6502 /* move */, Mips::MoveR3216, Convert__Reg1_0__Reg1_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_DSPR }, },
7286 { 6502 /* move */, Mips::Move32R16, Convert__Reg1_0__Reg1_1, AMFBS_InMips16Mode, { MCK_DSPR, MCK_CPU16Regs }, },
7287 { 6502 /* move */, Mips::OR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__regR0, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7288 { 6502 /* move */, Mips::ADDu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__regR0, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7289 { 6502 /* move */, Mips::MOVE16_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7290 { 6502 /* move */, Mips::OR64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__regR0_64, AMFBS_IsGP64bit_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
7291 { 6502 /* move */, Mips::DADDu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__regR0_64, AMFBS_IsGP64bit_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
7292 { 6507 /* move.v */, Mips::MOVE_V, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7293 { 6514 /* move16 */, Mips::MOVE16_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7294 { 6521 /* movep */, Mips::MOVEP_MM, Convert__GPRMM16AsmRegMovePPairFirst1_0__GPRMM16AsmRegMovePPairSecond1_1__GPRMM16AsmRegMoveP1_2__GPRMM16AsmRegMoveP1_3, AMFBS_InMicroMips_NotMips32r6, { MCK_GPRMM16AsmRegMovePPairFirst, MCK_GPRMM16AsmRegMovePPairSecond, MCK_GPRMM16AsmRegMoveP, MCK_GPRMM16AsmRegMoveP }, },
7295 { 6521 /* movep */, Mips::MOVEP_MMR6, Convert__GPRMM16AsmRegMovePPairFirst1_0__GPRMM16AsmRegMovePPairSecond1_1__GPRMM16AsmRegMoveP1_2__GPRMM16AsmRegMoveP1_3, AMFBS_InMicroMips_HasMips32r6, { MCK_GPRMM16AsmRegMovePPairFirst, MCK_GPRMM16AsmRegMovePPairSecond, MCK_GPRMM16AsmRegMoveP, MCK_GPRMM16AsmRegMoveP }, },
7296 { 6527 /* movf */, Mips::MOVF_I, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_FCCAsmReg }, },
7297 { 6527 /* movf */, Mips::MOVF_I_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_FCCAsmReg }, },
7298 { 6532 /* movf.d */, Mips::MOVF_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_FCCAsmReg }, },
7299 { 6532 /* movf.d */, Mips::MOVF_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_FCCAsmReg }, },
7300 { 6532 /* movf.d */, Mips::MOVF_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FCCAsmReg }, },
7301 { 6539 /* movf.s */, Mips::MOVF_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FCCAsmReg }, },
7302 { 6539 /* movf.s */, Mips::MOVF_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FCCAsmReg }, },
7303 { 6546 /* movn */, Mips::MOVN_I_I, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7304 { 6546 /* movn */, Mips::MOVN_I_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7305 { 6551 /* movn.d */, Mips::MOVN_I_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_GPR32AsmReg }, },
7306 { 6551 /* movn.d */, Mips::MOVN_I_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_GPR32AsmReg }, },
7307 { 6551 /* movn.d */, Mips::MOVN_I_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_GPR32AsmReg }, },
7308 { 6558 /* movn.s */, Mips::MOVN_I_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_GPR32AsmReg }, },
7309 { 6558 /* movn.s */, Mips::MOVN_I_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_GPR32AsmReg }, },
7310 { 6565 /* movt */, Mips::MOVT_I, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_FCCAsmReg }, },
7311 { 6565 /* movt */, Mips::MOVT_I_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_FCCAsmReg }, },
7312 { 6570 /* movt.d */, Mips::MOVT_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_FCCAsmReg }, },
7313 { 6570 /* movt.d */, Mips::MOVT_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_FCCAsmReg }, },
7314 { 6570 /* movt.d */, Mips::MOVT_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FCCAsmReg }, },
7315 { 6577 /* movt.s */, Mips::MOVT_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FCCAsmReg }, },
7316 { 6577 /* movt.s */, Mips::MOVT_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FCCAsmReg }, },
7317 { 6584 /* movz */, Mips::MOVZ_I_I, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7318 { 6584 /* movz */, Mips::MOVZ_I_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7319 { 6589 /* movz.d */, Mips::MOVZ_I_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_GPR32AsmReg }, },
7320 { 6589 /* movz.d */, Mips::MOVZ_I_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_GPR32AsmReg }, },
7321 { 6589 /* movz.d */, Mips::MOVZ_I_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_GPR32AsmReg }, },
7322 { 6596 /* movz.s */, Mips::MOVZ_I_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_GPR32AsmReg }, },
7323 { 6596 /* movz.s */, Mips::MOVZ_I_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_GPR32AsmReg }, },
7324 { 6603 /* msub */, Mips::MSUB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7325 { 6603 /* msub */, Mips::MSUB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7326 { 6603 /* msub */, Mips::MSUB_DSP_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7327 { 6603 /* msub */, Mips::MSUB_DSP, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7328 { 6608 /* msub.d */, Mips::MSUB_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2__AFGR64AsmReg1_3, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
7329 { 6608 /* msub.d */, Mips::MSUB_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2__AFGR64AsmReg1_3, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat_HasMadd4, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
7330 { 6608 /* msub.d */, Mips::MSUB_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2__FGR64AsmReg1_3, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7331 { 6615 /* msub.s */, Mips::MSUB_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2__FGR32AsmReg1_3, AMFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7332 { 6615 /* msub.s */, Mips::MSUB_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2__FGR32AsmReg1_3, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat_HasMadd4, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7333 { 6622 /* msub_q.h */, Mips::MSUB_Q_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7334 { 6631 /* msub_q.w */, Mips::MSUB_Q_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7335 { 6640 /* msubf.d */, Mips::MSUBF_D, Convert__FGR64AsmReg1_0__Tie0_1_1__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7336 { 6640 /* msubf.d */, Mips::MSUBF_D_MMR6, Convert__FGR64AsmReg1_0__Tie0_1_1__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7337 { 6648 /* msubf.s */, Mips::MSUBF_S, Convert__FGR32AsmReg1_0__Tie0_1_1__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7338 { 6648 /* msubf.s */, Mips::MSUBF_S_MMR6, Convert__FGR32AsmReg1_0__Tie0_1_1__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7339 { 6656 /* msubr_q.h */, Mips::MSUBR_Q_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7340 { 6666 /* msubr_q.w */, Mips::MSUBR_Q_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7341 { 6676 /* msubu */, Mips::MSUBU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7342 { 6676 /* msubu */, Mips::MSUBU_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7343 { 6676 /* msubu */, Mips::MSUBU_DSP_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7344 { 6676 /* msubu */, Mips::MSUBU_DSP, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7345 { 6682 /* msubv.b */, Mips::MSUBV_B, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7346 { 6690 /* msubv.d */, Mips::MSUBV_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7347 { 6698 /* msubv.h */, Mips::MSUBV_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7348 { 6706 /* msubv.w */, Mips::MSUBV_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7349 { 6714 /* mtc0 */, Mips::MTC0, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__imm_95_0, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, },
7350 { 6714 /* mtc0 */, Mips::MTC0_MM, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__imm_95_0, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, },
7351 { 6714 /* mtc0 */, Mips::MTC0_MMR6, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__imm_95_0, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, },
7352 { 6714 /* mtc0 */, Mips::MTC0, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
7353 { 6714 /* mtc0 */, Mips::MTC0_MM, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
7354 { 6714 /* mtc0 */, Mips::MTC0_MMR6, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
7355 { 6719 /* mtc1 */, Mips::MTC1, Convert__FGR32AsmReg1_1__GPR32AsmReg1_0, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, { MCK_GPR32AsmReg, MCK_FGR32AsmReg }, },
7356 { 6719 /* mtc1 */, Mips::MTC1_MMR6, Convert__FGR32AsmReg1_1__GPR32AsmReg1_0, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_FGR32AsmReg }, },
7357 { 6719 /* mtc1 */, Mips::MTC1_MM, Convert__FGR32AsmReg1_1__GPR32AsmReg1_0, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_FGR32AsmReg }, },
7358 { 6719 /* mtc1 */, Mips::MTC1_D64, Convert__FGR64AsmReg1_1__GPR32AsmReg1_0, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips, { MCK_GPR32AsmReg, MCK_FGR64AsmReg }, },
7359 { 6719 /* mtc1 */, Mips::MTC1_D64_MM, Convert__FGR64AsmReg1_1__GPR32AsmReg1_0, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_FGR64AsmReg }, },
7360 { 6724 /* mtc2 */, Mips::MTC2_MMR6, Convert__COP2AsmReg1_1__GPR32AsmReg1_0, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP2AsmReg }, },
7361 { 6724 /* mtc2 */, Mips::MTC2, Convert__COP2AsmReg1_1__GPR32AsmReg1_0__imm_95_0, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP2AsmReg }, },
7362 { 6724 /* mtc2 */, Mips::MTC2, Convert__COP2AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP2AsmReg, MCK_ConstantUImm3_0 }, },
7363 { 6729 /* mtgc0 */, Mips::MTGC0, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__imm_95_0, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, },
7364 { 6729 /* mtgc0 */, Mips::MTGC0_MM, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__imm_95_0, AMFBS_InMicroMips_HasMips32r5_HasVirt, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, },
7365 { 6729 /* mtgc0 */, Mips::MTGC0, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
7366 { 6729 /* mtgc0 */, Mips::MTGC0_MM, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2, AMFBS_InMicroMips_HasMips32r5_HasVirt, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
7367 { 6735 /* mthc0 */, Mips::MTHC0_MMR6, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__imm_95_0, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, },
7368 { 6735 /* mthc0 */, Mips::MTHC0_MMR6, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
7369 { 6741 /* mthc1 */, Mips::MTHC1_D32, Convert__AFGR64AsmReg1_1__Tie0_1_1__GPR32AsmReg1_0, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips32r2_IsNotSoftFloat_NotInMicroMips, { MCK_GPR32AsmReg, MCK_AFGR64AsmReg }, },
7370 { 6741 /* mthc1 */, Mips::MTHC1_D32_MM, Convert__AFGR64AsmReg1_1__Tie0_1_1__GPR32AsmReg1_0, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_AFGR64AsmReg }, },
7371 { 6741 /* mthc1 */, Mips::MTHC1_D64, Convert__FGR64AsmReg1_1__Tie0_1_1__GPR32AsmReg1_0, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips32r2_IsNotSoftFloat_NotInMicroMips, { MCK_GPR32AsmReg, MCK_FGR64AsmReg }, },
7372 { 6741 /* mthc1 */, Mips::MTHC1_D64_MM, Convert__FGR64AsmReg1_1__Tie0_1_1__GPR32AsmReg1_0, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_FGR64AsmReg }, },
7373 { 6747 /* mthc2 */, Mips::MTHC2_MMR6, Convert__COP2AsmReg1_1__GPR32AsmReg1_0, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP2AsmReg }, },
7374 { 6753 /* mthgc0 */, Mips::MTHGC0, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__imm_95_0, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, },
7375 { 6753 /* mthgc0 */, Mips::MTHGC0_MM, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__imm_95_0, AMFBS_InMicroMips_HasMips32r5_HasVirt, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, },
7376 { 6753 /* mthgc0 */, Mips::MTHGC0, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
7377 { 6753 /* mthgc0 */, Mips::MTHGC0_MM, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2, AMFBS_InMicroMips_HasMips32r5_HasVirt, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
7378 { 6760 /* mthi */, Mips::MTHI, Convert__GPR32AsmReg1_0, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg }, },
7379 { 6760 /* mthi */, Mips::MTHI_MM, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg }, },
7380 { 6760 /* mthi */, Mips::MTHI_DSP_MM, Convert__HI32DSPAsmReg1_1__GPR32AsmReg1_0, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_HI32DSPAsmReg }, },
7381 { 6760 /* mthi */, Mips::MTHI_DSP, Convert__HI32DSPAsmReg1_1__GPR32AsmReg1_0, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_HI32DSPAsmReg }, },
7382 { 6765 /* mthlip */, Mips::MTHLIP_MM, Convert__ACC64DSPAsmReg1_1__GPR32AsmReg1_0__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, },
7383 { 6765 /* mthlip */, Mips::MTHLIP, Convert__ACC64DSPAsmReg1_1__GPR32AsmReg1_0__Tie0_1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, },
7384 { 6772 /* mtlo */, Mips::MTLO, Convert__GPR32AsmReg1_0, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg }, },
7385 { 6772 /* mtlo */, Mips::MTLO_MM, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg }, },
7386 { 6772 /* mtlo */, Mips::MTLO_DSP_MM, Convert__LO32DSPAsmReg1_1__GPR32AsmReg1_0, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_LO32DSPAsmReg }, },
7387 { 6772 /* mtlo */, Mips::MTLO_DSP, Convert__LO32DSPAsmReg1_1__GPR32AsmReg1_0, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_LO32DSPAsmReg }, },
7388 { 6777 /* mtm0 */, Mips::MTM0, Convert__GPR64AsmReg1_0, AMFBS_HasCnMips, { MCK_GPR64AsmReg }, },
7389 { 6782 /* mtm1 */, Mips::MTM1, Convert__GPR64AsmReg1_0, AMFBS_HasCnMips, { MCK_GPR64AsmReg }, },
7390 { 6787 /* mtm2 */, Mips::MTM2, Convert__GPR64AsmReg1_0, AMFBS_HasCnMips, { MCK_GPR64AsmReg }, },
7391 { 6792 /* mtp0 */, Mips::MTP0, Convert__GPR64AsmReg1_0, AMFBS_HasCnMips, { MCK_GPR64AsmReg }, },
7392 { 6797 /* mtp1 */, Mips::MTP1, Convert__GPR64AsmReg1_0, AMFBS_HasCnMips, { MCK_GPR64AsmReg }, },
7393 { 6802 /* mtp2 */, Mips::MTP2, Convert__GPR64AsmReg1_0, AMFBS_HasCnMips, { MCK_GPR64AsmReg }, },
7394 { 6807 /* mttacx */, Mips::MTTACX, Convert__regAC0__GPR32AsmReg1_0, AMFBS_HasMT_NotInMicroMips, { MCK_GPR32AsmReg }, },
7395 { 6807 /* mttacx */, Mips::MTTACX, Convert__ACC64DSPAsmReg1_1__GPR32AsmReg1_0, AMFBS_HasMT, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, },
7396 { 6814 /* mttc0 */, Mips::MTTC0, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__imm_95_0, AMFBS_HasMT_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, },
7397 { 6814 /* mttc0 */, Mips::MTTC0, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2, AMFBS_HasMT, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
7398 { 6820 /* mttc1 */, Mips::MTTC1, Convert__FGR32AsmReg1_1__GPR32AsmReg1_0, AMFBS_HasMT, { MCK_GPR32AsmReg, MCK_FGR32AsmReg }, },
7399 { 6826 /* mttdsp */, Mips::MTTDSP, Convert__GPR32AsmReg1_0, AMFBS_HasMT, { MCK_GPR32AsmReg }, },
7400 { 6833 /* mttgpr */, Mips::MTTGPR, Convert__GPR32AsmReg1_1__GPR32AsmReg1_0, AMFBS_HasMT, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7401 { 6840 /* mtthc1 */, Mips::MTTHC1, Convert__FGR32AsmReg1_1__GPR32AsmReg1_0, AMFBS_HasMT, { MCK_GPR32AsmReg, MCK_FGR32AsmReg }, },
7402 { 6847 /* mtthi */, Mips::MTTHI, Convert__regAC0__GPR32AsmReg1_0, AMFBS_HasMT_NotInMicroMips, { MCK_GPR32AsmReg }, },
7403 { 6847 /* mtthi */, Mips::MTTHI, Convert__ACC64DSPAsmReg1_1__GPR32AsmReg1_0, AMFBS_HasMT, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, },
7404 { 6853 /* mttlo */, Mips::MTTLO, Convert__regAC0__GPR32AsmReg1_0, AMFBS_HasMT_NotInMicroMips, { MCK_GPR32AsmReg }, },
7405 { 6853 /* mttlo */, Mips::MTTLO, Convert__ACC64DSPAsmReg1_1__GPR32AsmReg1_0, AMFBS_HasMT, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, },
7406 { 6859 /* mttr */, Mips::MTTR, Convert__GPR32AsmReg1_1__GPR32AsmReg1_0__ConstantUImm1_01_2__ConstantUImm3_01_3__ConstantUImm1_01_4, AMFBS_HasStdEnc_HasMT_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm1_0, MCK_ConstantUImm3_0, MCK_ConstantUImm1_0 }, },
7407 { 6864 /* muh */, Mips::MUH_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7408 { 6864 /* muh */, Mips::MUH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7409 { 6864 /* muh */, Mips::MUH_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7410 { 6868 /* muhu */, Mips::MUHU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7411 { 6868 /* muhu */, Mips::MUHU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7412 { 6868 /* muhu */, Mips::MUHU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7413 { 6873 /* mul */, Mips::MUL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7414 { 6873 /* mul */, Mips::MUL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7415 { 6873 /* mul */, Mips::MUL_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7416 { 6873 /* mul */, Mips::MUL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7417 { 6873 /* mul */, Mips::MUL_R6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7418 { 6873 /* mul */, Mips::MUL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7419 { 6873 /* mul */, Mips::MUL_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7420 { 6873 /* mul */, Mips::MULImmMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
7421 { 6877 /* mul.d */, Mips::FMUL_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
7422 { 6877 /* mul.d */, Mips::FMUL_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
7423 { 6877 /* mul.d */, Mips::FMUL_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7424 { 6877 /* mul.d */, Mips::FMUL_D64_MM, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7425 { 6883 /* mul.ph */, Mips::MUL_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7426 { 6883 /* mul.ph */, Mips::MUL_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7427 { 6890 /* mul.ps */, Mips::FMUL_PS64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7428 { 6897 /* mul.s */, Mips::FMUL_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7429 { 6897 /* mul.s */, Mips::FMUL_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_2__FGR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7430 { 6897 /* mul.s */, Mips::FMUL_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7431 { 6903 /* mul_q.h */, Mips::MUL_Q_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7432 { 6911 /* mul_q.w */, Mips::MUL_Q_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7433 { 6919 /* mul_s.ph */, Mips::MUL_S_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7434 { 6919 /* mul_s.ph */, Mips::MUL_S_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7435 { 6928 /* muleq_s.w.phl */, Mips::MULEQ_S_W_PHL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7436 { 6928 /* muleq_s.w.phl */, Mips::MULEQ_S_W_PHL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7437 { 6942 /* muleq_s.w.phr */, Mips::MULEQ_S_W_PHR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7438 { 6942 /* muleq_s.w.phr */, Mips::MULEQ_S_W_PHR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7439 { 6956 /* muleu_s.ph.qbl */, Mips::MULEU_S_PH_QBL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7440 { 6956 /* muleu_s.ph.qbl */, Mips::MULEU_S_PH_QBL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7441 { 6971 /* muleu_s.ph.qbr */, Mips::MULEU_S_PH_QBR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7442 { 6971 /* muleu_s.ph.qbr */, Mips::MULEU_S_PH_QBR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7443 { 6986 /* mulo */, Mips::MULOMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7444 { 6986 /* mulo */, Mips::MULOMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7445 { 6991 /* mulou */, Mips::MULOUMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7446 { 6991 /* mulou */, Mips::MULOUMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7447 { 6997 /* mulq_rs.ph */, Mips::MULQ_RS_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7448 { 6997 /* mulq_rs.ph */, Mips::MULQ_RS_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7449 { 7008 /* mulq_rs.w */, Mips::MULQ_RS_W_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7450 { 7008 /* mulq_rs.w */, Mips::MULQ_RS_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7451 { 7018 /* mulq_s.ph */, Mips::MULQ_S_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7452 { 7018 /* mulq_s.ph */, Mips::MULQ_S_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7453 { 7028 /* mulq_s.w */, Mips::MULQ_S_W_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7454 { 7028 /* mulq_s.w */, Mips::MULQ_S_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7455 { 7037 /* mulr.ps */, Mips::MULR_PS64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMips3D, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7456 { 7045 /* mulr_q.h */, Mips::MULR_Q_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7457 { 7054 /* mulr_q.w */, Mips::MULR_Q_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7458 { 7063 /* mulsa.w.ph */, Mips::MULSA_W_PH_MMR2, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7459 { 7063 /* mulsa.w.ph */, Mips::MULSA_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7460 { 7074 /* mulsaq_s.w.ph */, Mips::MULSAQ_S_W_PH_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7461 { 7074 /* mulsaq_s.w.ph */, Mips::MULSAQ_S_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7462 { 7088 /* mult */, Mips::MULT, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7463 { 7088 /* mult */, Mips::MULT_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7464 { 7088 /* mult */, Mips::MULT_DSP_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7465 { 7088 /* mult */, Mips::MULT_DSP, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7466 { 7093 /* multu */, Mips::MULTu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7467 { 7093 /* multu */, Mips::MULTu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7468 { 7093 /* multu */, Mips::MULTU_DSP_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7469 { 7093 /* multu */, Mips::MULTU_DSP, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7470 { 7099 /* mulu */, Mips::MULU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7471 { 7099 /* mulu */, Mips::MULU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7472 { 7099 /* mulu */, Mips::MULU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7473 { 7104 /* mulv.b */, Mips::MULV_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7474 { 7111 /* mulv.d */, Mips::MULV_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7475 { 7118 /* mulv.h */, Mips::MULV_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7476 { 7125 /* mulv.w */, Mips::MULV_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7477 { 7132 /* nal */, Mips::BLTZAL, Convert__regR0__imm_95_0, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { }, },
7478 { 7132 /* nal */, Mips::NAL, Convert_NoOperands, AMFBS_HasStdEnc_HasMips32r6, { }, },
7479 { 7136 /* neg */, Mips::SUB, Convert__GPR32AsmReg1_0__regR0__GPR32AsmReg1_0, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg }, },
7480 { 7136 /* neg */, Mips::SUB_MM, Convert__GPR32AsmReg1_0__regR0__GPR32AsmReg1_0, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg }, },
7481 { 7136 /* neg */, Mips::SUB_MMR6, Convert__GPR32AsmReg1_0__regR0__GPR32AsmReg1_0, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg }, },
7482 { 7136 /* neg */, Mips::NegRxRy16, Convert__Reg1_0__Reg1_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs }, },
7483 { 7136 /* neg */, Mips::SUB, Convert__GPR32AsmReg1_0__regR0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7484 { 7136 /* neg */, Mips::SUB_MM, Convert__GPR32AsmReg1_0__regR0__GPR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7485 { 7136 /* neg */, Mips::SUB_MMR6, Convert__GPR32AsmReg1_0__regR0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7486 { 7140 /* neg.d */, Mips::FNEG_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
7487 { 7140 /* neg.d */, Mips::FNEG_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
7488 { 7140 /* neg.d */, Mips::FNEG_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7489 { 7140 /* neg.d */, Mips::FNEG_D64_MM, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7490 { 7146 /* neg.s */, Mips::FNEG_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7491 { 7146 /* neg.s */, Mips::FNEG_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7492 { 7146 /* neg.s */, Mips::FNEG_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7493 { 7152 /* negu */, Mips::SUBu, Convert__GPR32AsmReg1_0__regR0__GPR32AsmReg1_0, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg }, },
7494 { 7152 /* negu */, Mips::SUBu_MM, Convert__GPR32AsmReg1_0__regR0__GPR32AsmReg1_0, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg }, },
7495 { 7152 /* negu */, Mips::SUBU_MMR6, Convert__GPR32AsmReg1_0__regR0__GPR32AsmReg1_0, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg }, },
7496 { 7152 /* negu */, Mips::SUBu, Convert__GPR32AsmReg1_0__regR0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7497 { 7152 /* negu */, Mips::SUBu_MM, Convert__GPR32AsmReg1_0__regR0__GPR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7498 { 7152 /* negu */, Mips::SUBU_MMR6, Convert__GPR32AsmReg1_0__regR0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7499 { 7157 /* nloc.b */, Mips::NLOC_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7500 { 7164 /* nloc.d */, Mips::NLOC_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7501 { 7171 /* nloc.h */, Mips::NLOC_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7502 { 7178 /* nloc.w */, Mips::NLOC_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7503 { 7185 /* nlzc.b */, Mips::NLZC_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7504 { 7192 /* nlzc.d */, Mips::NLZC_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7505 { 7199 /* nlzc.h */, Mips::NLZC_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7506 { 7206 /* nlzc.w */, Mips::NLZC_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7507 { 7213 /* nmadd.d */, Mips::NMADD_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2__AFGR64AsmReg1_3, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
7508 { 7213 /* nmadd.d */, Mips::NMADD_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2__AFGR64AsmReg1_3, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat_HasMadd4, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
7509 { 7213 /* nmadd.d */, Mips::NMADD_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2__FGR64AsmReg1_3, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7510 { 7221 /* nmadd.s */, Mips::NMADD_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2__FGR32AsmReg1_3, AMFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7511 { 7221 /* nmadd.s */, Mips::NMADD_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2__FGR32AsmReg1_3, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat_HasMadd4, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7512 { 7229 /* nmsub.d */, Mips::NMSUB_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2__AFGR64AsmReg1_3, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
7513 { 7229 /* nmsub.d */, Mips::NMSUB_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2__AFGR64AsmReg1_3, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat_HasMadd4, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
7514 { 7229 /* nmsub.d */, Mips::NMSUB_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2__FGR64AsmReg1_3, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7515 { 7237 /* nmsub.s */, Mips::NMSUB_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2__FGR32AsmReg1_3, AMFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7516 { 7237 /* nmsub.s */, Mips::NMSUB_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2__FGR32AsmReg1_3, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat_HasMadd4, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7517 { 7245 /* nop */, Mips::SLL, Convert__regR0__regR0__imm_95_0, AMFBS_HasStdEnc_NotInMicroMips, { }, },
7518 { 7245 /* nop */, Mips::SLL_MMR6, Convert__regR0__regR0__imm_95_0, AMFBS_InMicroMips_HasMips32r6, { }, },
7519 { 7245 /* nop */, Mips::Move32R16, Convert__regR0__regR16, AMFBS_InMips16Mode, { }, },
7520 { 7245 /* nop */, Mips::SLL_MM, Convert__regR0__regR0__imm_95_0, AMFBS_InMicroMips, { }, },
7521 { 7245 /* nop */, Mips::MOVE16_MM, Convert__regR0__regR0, AMFBS_InMicroMips, { }, },
7522 { 7249 /* nor */, Mips::NORImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, AMFBS_IsGP32bit, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
7523 { 7249 /* nor */, Mips::NORImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, AMFBS_IsGP64bit, { MCK_GPR64AsmReg, MCK_Imm }, },
7524 { 7249 /* nor */, Mips::NOR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7525 { 7249 /* nor */, Mips::NOR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7526 { 7249 /* nor */, Mips::NOR_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7527 { 7249 /* nor */, Mips::NORImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_IsGP32bit, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
7528 { 7249 /* nor */, Mips::NORImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, AMFBS_IsGP64bit, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, },
7529 { 7253 /* nor.v */, Mips::NOR_V, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7530 { 7259 /* nori.b */, Mips::NORI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm8_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm8_0 }, },
7531 { 7266 /* not */, Mips::NOR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__regR0, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg }, },
7532 { 7266 /* not */, Mips::NOR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__regR0, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg }, },
7533 { 7266 /* not */, Mips::NOR_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__regR0, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg }, },
7534 { 7266 /* not */, Mips::NotRxRy16, Convert__Reg1_0__Reg1_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs }, },
7535 { 7266 /* not */, Mips::NOR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__regR0, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7536 { 7266 /* not */, Mips::NOR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__regR0, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7537 { 7266 /* not */, Mips::NOR_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__regR0, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7538 { 7270 /* not16 */, Mips::NOT16_MM, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, },
7539 { 7270 /* not16 */, Mips::NOT16_MMR6, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, },
7540 { 7276 /* or */, Mips::OrRxRxRy16, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs }, },
7541 { 7276 /* or */, Mips::OR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7542 { 7276 /* or */, Mips::OR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7543 { 7276 /* or */, Mips::OR_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7544 { 7276 /* or */, Mips::ORI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_UImm16 }, },
7545 { 7276 /* or */, Mips::ORi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
7546 { 7276 /* or */, Mips::ORi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
7547 { 7276 /* or */, Mips::ORi64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, AMFBS_HasStdEnc_IsGP64bit_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_Imm }, },
7548 { 7276 /* or */, Mips::OR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7549 { 7276 /* or */, Mips::OR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7550 { 7276 /* or */, Mips::OR_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7551 { 7276 /* or */, Mips::ORI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, },
7552 { 7276 /* or */, Mips::ORi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
7553 { 7276 /* or */, Mips::ORi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
7554 { 7276 /* or */, Mips::ORi64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, AMFBS_HasStdEnc_IsGP64bit_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, },
7555 { 7279 /* or.v */, Mips::OR_V, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7556 { 7284 /* or16 */, Mips::OR16_MM, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Tie0_1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, },
7557 { 7284 /* or16 */, Mips::OR16_MMR6, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Tie0_1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, },
7558 { 7289 /* ori */, Mips::ORI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_UImm16 }, },
7559 { 7289 /* ori */, Mips::ORi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_UImm16 }, },
7560 { 7289 /* ori */, Mips::ORi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_UImm16 }, },
7561 { 7289 /* ori */, Mips::ORI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, },
7562 { 7289 /* ori */, Mips::ORi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, },
7563 { 7289 /* ori */, Mips::ORi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, },
7564 { 7293 /* ori.b */, Mips::ORI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm8_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm8_0 }, },
7565 { 7299 /* packrl.ph */, Mips::PACKRL_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7566 { 7299 /* packrl.ph */, Mips::PACKRL_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7567 { 7309 /* pause */, Mips::PAUSE, Convert_NoOperands, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips, { }, },
7568 { 7309 /* pause */, Mips::PAUSE_MMR6, Convert_NoOperands, AMFBS_InMicroMips_HasMips32r6, { }, },
7569 { 7309 /* pause */, Mips::PAUSE_MM, Convert_NoOperands, AMFBS_InMicroMips, { }, },
7570 { 7315 /* pckev.b */, Mips::PCKEV_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7571 { 7323 /* pckev.d */, Mips::PCKEV_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7572 { 7331 /* pckev.h */, Mips::PCKEV_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7573 { 7339 /* pckev.w */, Mips::PCKEV_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7574 { 7347 /* pckod.b */, Mips::PCKOD_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7575 { 7355 /* pckod.d */, Mips::PCKOD_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7576 { 7363 /* pckod.h */, Mips::PCKOD_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7577 { 7371 /* pckod.w */, Mips::PCKOD_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7578 { 7379 /* pcnt.b */, Mips::PCNT_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7579 { 7386 /* pcnt.d */, Mips::PCNT_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7580 { 7393 /* pcnt.h */, Mips::PCNT_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7581 { 7400 /* pcnt.w */, Mips::PCNT_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7582 { 7407 /* pick.ph */, Mips::PICK_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7583 { 7407 /* pick.ph */, Mips::PICK_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7584 { 7415 /* pick.qb */, Mips::PICK_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7585 { 7415 /* pick.qb */, Mips::PICK_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7586 { 7423 /* pll.ps */, Mips::PLL_PS64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7587 { 7430 /* plu.ps */, Mips::PLU_PS64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7588 { 7437 /* pop */, Mips::POP, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0, AMFBS_HasCnMips, { MCK_GPR32AsmReg }, },
7589 { 7437 /* pop */, Mips::POP, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasCnMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7590 { 7441 /* preceq.w.phl */, Mips::PRECEQ_W_PHL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7591 { 7441 /* preceq.w.phl */, Mips::PRECEQ_W_PHL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7592 { 7454 /* preceq.w.phr */, Mips::PRECEQ_W_PHR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7593 { 7454 /* preceq.w.phr */, Mips::PRECEQ_W_PHR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7594 { 7467 /* precequ.ph.qbl */, Mips::PRECEQU_PH_QBL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7595 { 7467 /* precequ.ph.qbl */, Mips::PRECEQU_PH_QBL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7596 { 7482 /* precequ.ph.qbla */, Mips::PRECEQU_PH_QBLA_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7597 { 7482 /* precequ.ph.qbla */, Mips::PRECEQU_PH_QBLA, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7598 { 7498 /* precequ.ph.qbr */, Mips::PRECEQU_PH_QBR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7599 { 7498 /* precequ.ph.qbr */, Mips::PRECEQU_PH_QBR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7600 { 7513 /* precequ.ph.qbra */, Mips::PRECEQU_PH_QBRA_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7601 { 7513 /* precequ.ph.qbra */, Mips::PRECEQU_PH_QBRA, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7602 { 7529 /* preceu.ph.qbl */, Mips::PRECEU_PH_QBL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7603 { 7529 /* preceu.ph.qbl */, Mips::PRECEU_PH_QBL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7604 { 7543 /* preceu.ph.qbla */, Mips::PRECEU_PH_QBLA_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7605 { 7543 /* preceu.ph.qbla */, Mips::PRECEU_PH_QBLA, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7606 { 7558 /* preceu.ph.qbr */, Mips::PRECEU_PH_QBR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7607 { 7558 /* preceu.ph.qbr */, Mips::PRECEU_PH_QBR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7608 { 7572 /* preceu.ph.qbra */, Mips::PRECEU_PH_QBRA_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7609 { 7572 /* preceu.ph.qbra */, Mips::PRECEU_PH_QBRA, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7610 { 7587 /* precr.qb.ph */, Mips::PRECR_QB_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7611 { 7587 /* precr.qb.ph */, Mips::PRECR_QB_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7612 { 7599 /* precr_sra.ph.w */, Mips::PRECR_SRA_PH_W_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Tie0_1_1, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7613 { 7599 /* precr_sra.ph.w */, Mips::PRECR_SRA_PH_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Tie0_1_1, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7614 { 7614 /* precr_sra_r.ph.w */, Mips::PRECR_SRA_R_PH_W_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Tie0_1_1, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7615 { 7614 /* precr_sra_r.ph.w */, Mips::PRECR_SRA_R_PH_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Tie0_1_1, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7616 { 7631 /* precrq.ph.w */, Mips::PRECRQ_PH_W_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7617 { 7631 /* precrq.ph.w */, Mips::PRECRQ_PH_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7618 { 7643 /* precrq.qb.ph */, Mips::PRECRQ_QB_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7619 { 7643 /* precrq.qb.ph */, Mips::PRECRQ_QB_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7620 { 7656 /* precrq_rs.ph.w */, Mips::PRECRQ_RS_PH_W_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7621 { 7656 /* precrq_rs.ph.w */, Mips::PRECRQ_RS_PH_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7622 { 7671 /* precrqu_s.qb.ph */, Mips::PRECRQU_S_QB_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7623 { 7671 /* precrqu_s.qb.ph */, Mips::PRECRQU_S_QB_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7624 { 7687 /* pref */, Mips::PREF_R6, Convert__PtrReg1_3__SImmOffset9_01_1__ConstantUImm5_01_0, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_ConstantUImm5_0, MCK_SImmOffset9_0, MCK__40_, MCK_PtrReg, MCK__41_ }, },
7625 { 7687 /* pref */, Mips::PREF, Convert__PtrReg1_3__SImmPtr1_1__ConstantUImm5_01_0, AMFBS_HasStdEnc_HasMips3_32_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_ConstantUImm5_0, MCK_SImmPtr, MCK__40_, MCK_PtrReg, MCK__41_ }, },
7626 { 7687 /* pref */, Mips::PREF_MM, Convert__PtrReg1_3__AnyOffset1_1__ConstantUImm5_01_0, AMFBS_InMicroMips_NotMips32r6, { MCK_ConstantUImm5_0, MCK_AnyOffset, MCK__40_, MCK_PtrReg, MCK__41_ }, },
7627 { 7687 /* pref */, Mips::PREF_MMR6, Convert__PtrReg1_3__AnyOffset1_1__ConstantUImm5_01_0, AMFBS_InMicroMips_HasMips32r6, { MCK_ConstantUImm5_0, MCK_AnyOffset, MCK__40_, MCK_PtrReg, MCK__41_ }, },
7628 { 7692 /* prefe */, Mips::PREFE, Convert__PtrReg1_3__SImmOffset9_01_1__ConstantUImm5_01_0, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, { MCK_ConstantUImm5_0, MCK_SImmOffset9_0, MCK__40_, MCK_PtrReg, MCK__41_ }, },
7629 { 7692 /* prefe */, Mips::PREFE_MM, Convert__PtrReg1_3__SImmOffset9_01_1__ConstantUImm5_01_0, AMFBS_InMicroMips_HasEVA, { MCK_ConstantUImm5_0, MCK_SImmOffset9_0, MCK__40_, MCK_PtrReg, MCK__41_ }, },
7630 { 7698 /* prefx */, Mips::PREFX_MM, Convert__GPR32AsmReg1_3__GPR32AsmReg1_1__ConstantUImm5_01_0, AMFBS_InMicroMips_NotMips32r6, { MCK_ConstantUImm5_0, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
7631 { 7704 /* prepend */, Mips::PREPEND_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Tie0_1_1, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7632 { 7704 /* prepend */, Mips::PREPEND, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Tie0_1_1, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7633 { 7712 /* pul.ps */, Mips::PUL_PS64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7634 { 7719 /* puu.ps */, Mips::PUU_PS64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7635 { 7726 /* raddu.w.qb */, Mips::RADDU_W_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7636 { 7726 /* raddu.w.qb */, Mips::RADDU_W_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7637 { 7737 /* rddsp */, Mips::RDDSP_MM, Convert__GPR32AsmReg1_0__ConstantUImm7_01_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ConstantUImm7_0 }, },
7638 { 7737 /* rddsp */, Mips::RDDSP, Convert__GPR32AsmReg1_0__ConstantUImm10_01_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_ConstantUImm10_0 }, },
7639 { 7743 /* rdhwr */, Mips::RDHWR, Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__imm_95_0, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_HWRegsAsmReg }, },
7640 { 7743 /* rdhwr */, Mips::RDHWR_MM, Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__imm_95_0, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_HWRegsAsmReg }, },
7641 { 7743 /* rdhwr */, Mips::RDHWR_MMR6, Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__imm_95_0, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_HWRegsAsmReg }, },
7642 { 7743 /* rdhwr */, Mips::RDHWR64, Convert__GPR64AsmReg1_0__HWRegsAsmReg1_1__imm_95_0, AMFBS_IsGP64bit, { MCK_GPR64AsmReg, MCK_HWRegsAsmReg }, },
7643 { 7743 /* rdhwr */, Mips::RDHWR_MMR6, Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__ConstantUImm3_01_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_HWRegsAsmReg, MCK_ConstantUImm3_0 }, },
7644 { 7743 /* rdhwr */, Mips::RDHWR, Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__ConstantUImm8_01_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_HWRegsAsmReg, MCK_ConstantUImm8_0 }, },
7645 { 7743 /* rdhwr */, Mips::RDHWR_MM, Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__ConstantUImm8_01_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_HWRegsAsmReg, MCK_ConstantUImm8_0 }, },
7646 { 7749 /* rdpgpr */, Mips::RDPGPR_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7647 { 7756 /* recip.d */, Mips::RECIP_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
7648 { 7756 /* recip.d */, Mips::RECIP_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
7649 { 7756 /* recip.d */, Mips::RECIP_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7650 { 7756 /* recip.d */, Mips::RECIP_D64_MM, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7651 { 7764 /* recip.s */, Mips::RECIP_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7652 { 7764 /* recip.s */, Mips::RECIP_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7653 { 7772 /* rem */, Mips::SRemMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7654 { 7772 /* rem */, Mips::SRemIMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
7655 { 7772 /* rem */, Mips::SRemMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7656 { 7772 /* rem */, Mips::SRemIMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
7657 { 7776 /* remu */, Mips::URemMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7658 { 7776 /* remu */, Mips::URemIMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
7659 { 7776 /* remu */, Mips::URemMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7660 { 7776 /* remu */, Mips::URemIMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
7661 { 7781 /* repl.ph */, Mips::REPL_PH_MM, Convert__GPR32AsmReg1_0__ConstantSImm10_01_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ConstantSImm10_0 }, },
7662 { 7781 /* repl.ph */, Mips::REPL_PH, Convert__GPR32AsmReg1_0__ConstantSImm10_01_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_ConstantSImm10_0 }, },
7663 { 7789 /* repl.qb */, Mips::REPL_QB_MM, Convert__GPR32AsmReg1_0__ConstantUImm8_01_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ConstantUImm8_0 }, },
7664 { 7789 /* repl.qb */, Mips::REPL_QB, Convert__GPR32AsmReg1_0__ConstantUImm8_01_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_ConstantUImm8_0 }, },
7665 { 7797 /* replv.ph */, Mips::REPLV_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7666 { 7797 /* replv.ph */, Mips::REPLV_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7667 { 7806 /* replv.qb */, Mips::REPLV_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7668 { 7806 /* replv.qb */, Mips::REPLV_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7669 { 7815 /* rint.d */, Mips::RINT_D, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7670 { 7815 /* rint.d */, Mips::RINT_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7671 { 7822 /* rint.s */, Mips::RINT_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7672 { 7822 /* rint.s */, Mips::RINT_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7673 { 7829 /* rol */, Mips::ROL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_None, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7674 { 7829 /* rol */, Mips::ROLImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm161_1, AMFBS_None, { MCK_GPR32AsmReg, MCK_SImm16 }, },
7675 { 7829 /* rol */, Mips::ROL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7676 { 7829 /* rol */, Mips::ROLImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16 }, },
7677 { 7833 /* ror */, Mips::ROR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_None, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7678 { 7833 /* ror */, Mips::RORImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm161_1, AMFBS_None, { MCK_GPR32AsmReg, MCK_SImm16 }, },
7679 { 7833 /* ror */, Mips::ROR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7680 { 7833 /* ror */, Mips::RORImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16 }, },
7681 { 7837 /* rotr */, Mips::ROTR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7682 { 7837 /* rotr */, Mips::ROTR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7683 { 7837 /* rotr */, Mips::ROTR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7684 { 7837 /* rotr */, Mips::ROTR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7685 { 7837 /* rotr */, Mips::ROTR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7686 { 7842 /* rotrv */, Mips::ROTRV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7687 { 7842 /* rotrv */, Mips::ROTRV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7688 { 7848 /* round.l.d */, Mips::ROUND_L_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips3_32_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7689 { 7848 /* round.l.d */, Mips::ROUND_L_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7690 { 7858 /* round.l.s */, Mips::ROUND_L_S, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, },
7691 { 7858 /* round.l.s */, Mips::ROUND_L_S_MMR6, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, },
7692 { 7868 /* round.w.d */, Mips::ROUND_W_D32, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, },
7693 { 7868 /* round.w.d */, Mips::ROUND_W_MM, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, },
7694 { 7868 /* round.w.d */, Mips::ROUND_W_D64, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg }, },
7695 { 7868 /* round.w.d */, Mips::ROUND_W_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7696 { 7878 /* round.w.s */, Mips::ROUND_W_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_HasMips2_NotR5900_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7697 { 7878 /* round.w.s */, Mips::ROUND_W_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7698 { 7878 /* round.w.s */, Mips::ROUND_W_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7699 { 7888 /* rsqrt.d */, Mips::RSQRT_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
7700 { 7888 /* rsqrt.d */, Mips::RSQRT_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
7701 { 7888 /* rsqrt.d */, Mips::RSQRT_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7702 { 7888 /* rsqrt.d */, Mips::RSQRT_D64_MM, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7703 { 7896 /* rsqrt.s */, Mips::RSQRT_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7704 { 7896 /* rsqrt.s */, Mips::RSQRT_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7705 { 7904 /* s.d */, Mips::SDC1, Convert__AFGR64AsmReg1_0__PtrReg1_3__SImmOffset16_01_1, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_SImmOffset16_0, MCK__40_, MCK_PtrReg, MCK__41_ }, },
7706 { 7904 /* s.d */, Mips::SDC1_M1, Convert__AFGR64AsmReg1_0__PtrReg1_3__SImmOffset16_01_1, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_SImmOffset16_0, MCK__40_, MCK_PtrReg, MCK__41_ }, },
7707 { 7904 /* s.d */, Mips::SDC1_M1, Convert__AFGR64AsmReg1_0__PtrReg1_3__SImmOffset16_01_1, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_SImmOffset16_0, MCK__40_, MCK_PtrReg, MCK__41_ }, },
7708 { 7904 /* s.d */, Mips::SDC164, Convert__FGR64AsmReg1_0__PtrReg1_3__SImmOffset16_01_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_SImmOffset16_0, MCK__40_, MCK_PtrReg, MCK__41_ }, },
7709 { 7908 /* s.s */, Mips::SWC1, Convert__FGR32AsmReg1_0__PtrReg1_3__SImmOffset16_01_1, AMFBS_HasStdEnc_HasMips2_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_SImmOffset16_0, MCK__40_, MCK_PtrReg, MCK__41_ }, },
7710 { 7912 /* saa */, Mips::SAA, Convert__GPR64AsmReg1_0__GPR64AsmReg1_2, AMFBS_HasCnMipsP, { MCK_GPR64AsmReg, MCK__40_, MCK_GPR64AsmReg, MCK__41_ }, },
7711 { 7912 /* saa */, Mips::SaaAddr, Convert__GPR64AsmReg1_0__PtrReg1_3__AnyOffset1_1, AMFBS_HasCnMipsP, { MCK_GPR64AsmReg, MCK_AnyOffset, MCK__40_, MCK_PtrReg, MCK__41_ }, },
7712 { 7916 /* saad */, Mips::SAAD, Convert__GPR64AsmReg1_0__GPR64AsmReg1_2, AMFBS_HasCnMipsP, { MCK_GPR64AsmReg, MCK__40_, MCK_GPR64AsmReg, MCK__41_ }, },
7713 { 7916 /* saad */, Mips::SaadAddr, Convert__GPR64AsmReg1_0__PtrReg1_3__AnyOffset1_1, AMFBS_HasCnMipsP, { MCK_GPR64AsmReg, MCK_AnyOffset, MCK__40_, MCK_PtrReg, MCK__41_ }, },
7714 { 7921 /* sat_s.b */, Mips::SAT_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, },
7715 { 7929 /* sat_s.d */, Mips::SAT_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, },
7716 { 7937 /* sat_s.h */, Mips::SAT_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, },
7717 { 7945 /* sat_s.w */, Mips::SAT_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
7718 { 7953 /* sat_u.b */, Mips::SAT_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, },
7719 { 7961 /* sat_u.d */, Mips::SAT_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, },
7720 { 7969 /* sat_u.h */, Mips::SAT_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, },
7721 { 7977 /* sat_u.w */, Mips::SAT_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
7722 { 7985 /* sb */, Mips::SbRxRyOffMemX16, Convert__Reg1_0__Reg1_3__SImm161_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_SImm16, MCK__40_, MCK_CPU16Regs, MCK__41_ }, },
7723 { 7985 /* sb */, Mips::SB, Convert__GPR32AsmReg1_0__PtrReg1_3__AnyOffset1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_AnyOffset, MCK__40_, MCK_PtrReg, MCK__41_ }, },
7724 { 7985 /* sb */, Mips::SB_MMR6, Convert__GPR32AsmReg1_0__PtrReg1_3__AnyOffset1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_AnyOffset, MCK__40_, MCK_PtrReg, MCK__41_ }, },
7725 { 7985 /* sb */, Mips::SB_MM, Convert__GPR32AsmReg1_0__PtrReg1_3__AnyOffset1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_AnyOffset, MCK__40_, MCK_PtrReg, MCK__41_ }, },
7726 { 7988 /* sb16 */, Mips::SB16_MM, Convert__GPRMM16AsmRegZero1_0__GPRMM16AsmReg1_3__UImmOffset4_001_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPRMM16AsmRegZero, MCK_UImmOffset4_00, MCK__40_, MCK_GPRMM16AsmReg, MCK__41_ }, },
7727 { 7988 /* sb16 */, Mips::SB16_MMR6, Convert__GPRMM16AsmRegZero1_0__GPRMM16AsmReg1_3__UImmOffset4_001_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPRMM16AsmRegZero, MCK_UImmOffset4_00, MCK__40_, MCK_GPRMM16AsmReg, MCK__41_ }, },
7728 { 7993 /* sbe */, Mips::SBE, Convert__GPR32AsmReg1_0__PtrReg1_3__SImmOffset9_01_1, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImmOffset9_0, MCK__40_, MCK_PtrReg, MCK__41_ }, },
7729 { 7993 /* sbe */, Mips::SBE_MM, Convert__GPR32AsmReg1_0__PtrReg1_3__SImmOffset9_01_1, AMFBS_InMicroMips_HasEVA, { MCK_GPR32AsmReg, MCK_SImmOffset9_0, MCK__40_, MCK_PtrReg, MCK__41_ }, },
7730 { 7997 /* sc */, Mips::SC_MMR6, Convert__GPR32AsmReg1_0__Tie0_1_1__PtrReg1_3__SImmOffset9_01_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_SImmOffset9_0, MCK__40_, MCK_PtrReg, MCK__41_ }, },
7731 { 7997 /* sc */, Mips::SC64_R6, Convert__GPR32AsmReg1_0__Tie0_1_1__PtrReg1_3__SImmPtr1_1, AMFBS_HasStdEnc_IsPTR64bit_HasMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImmPtr, MCK__40_, MCK_PtrReg, MCK__41_ }, },
7732 { 7997 /* sc */, Mips::SC_R6, Convert__GPR32AsmReg1_0__Tie0_1_1__PtrReg1_3__SImmPtr1_1, AMFBS_HasStdEnc_IsPTR32bit_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImmPtr, MCK__40_, MCK_PtrReg, MCK__41_ }, },
7733 { 7997 /* sc */, Mips::SC, Convert__GPR32AsmReg1_0__Tie0_1_1__PtrReg1_3__AnyOffset1_1, AMFBS_HasStdEnc_IsPTR32bit_HasMips2_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips, { MCK_GPR32AsmReg, MCK_AnyOffset, MCK__40_, MCK_PtrReg, MCK__41_ }, },
7734 { 7997 /* sc */, Mips::SC64, Convert__GPR32AsmReg1_0__Tie0_1_1__PtrReg1_3__AnyOffset1_1, AMFBS_HasStdEnc_IsPTR64bit_HasMips2_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips, { MCK_GPR32AsmReg, MCK_AnyOffset, MCK__40_, MCK_PtrReg, MCK__41_ }, },
7735 { 7997 /* sc */, Mips::SC_MM, Convert__GPR32AsmReg1_0__Tie0_1_1__PtrReg1_3__AnyOffset1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_AnyOffset, MCK__40_, MCK_PtrReg, MCK__41_ }, },
7736 { 8000 /* scd */, Mips::SCD_R6, Convert__GPR64AsmReg1_0__Tie0_1_1__PtrReg1_3__SImmPtr1_1, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR64AsmReg, MCK_SImmPtr, MCK__40_, MCK_PtrReg, MCK__41_ }, },
7737 { 8000 /* scd */, Mips::SCD, Convert__GPR64AsmReg1_0__Tie0_1_1__PtrReg1_3__AnyOffset1_1, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900, { MCK_GPR64AsmReg, MCK_AnyOffset, MCK__40_, MCK_PtrReg, MCK__41_ }, },
7738 { 8004 /* sce */, Mips::SCE, Convert__GPR32AsmReg1_0__Tie0_1_1__PtrReg1_3__SImmOffset9_01_1, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImmOffset9_0, MCK__40_, MCK_PtrReg, MCK__41_ }, },
7739 { 8004 /* sce */, Mips::SCE_MM, Convert__GPR32AsmReg1_0__Tie0_1_1__PtrReg1_3__SImmOffset9_01_1, AMFBS_InMicroMips_HasEVA, { MCK_GPR32AsmReg, MCK_SImmOffset9_0, MCK__40_, MCK_PtrReg, MCK__41_ }, },
7740 { 8008 /* sd */, Mips::SDMacro, Convert__GPR32AsmReg1_0__PtrReg1_3__SImmOffset16_01_1, AMFBS_HasStdEnc_NotMips3, { MCK_GPR32AsmReg, MCK_SImmOffset16_0, MCK__40_, MCK_PtrReg, MCK__41_ }, },
7741 { 8008 /* sd */, Mips::SD, Convert__GPR64AsmReg1_0__PtrReg1_3__SImmPtr1_1, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_SImmPtr, MCK__40_, MCK_PtrReg, MCK__41_ }, },
7742 { 8011 /* sdbbp */, Mips::SDBBP, Convert__imm_95_0, AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6, { }, },
7743 { 8011 /* sdbbp */, Mips::SDBBP_R6, Convert__imm_95_0, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { }, },
7744 { 8011 /* sdbbp */, Mips::SDBBP_MMR6, Convert__imm_95_0, AMFBS_InMicroMips_HasMips32r6, { }, },
7745 { 8011 /* sdbbp */, Mips::SDBBP_MM, Convert__ConstantUImm10_01_0, AMFBS_InMicroMips, { MCK_ConstantUImm10_0 }, },
7746 { 8011 /* sdbbp */, Mips::SDBBP, Convert__ConstantUImm20_01_0, AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_ConstantUImm20_0 }, },
7747 { 8011 /* sdbbp */, Mips::SDBBP_R6, Convert__ConstantUImm20_01_0, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_ConstantUImm20_0 }, },
7748 { 8011 /* sdbbp */, Mips::SDBBP_MMR6, Convert__ConstantUImm20_01_0, AMFBS_InMicroMips_HasMips32r6, { MCK_ConstantUImm20_0 }, },
7749 { 8017 /* sdbbp16 */, Mips::SDBBP16_MM, Convert__ConstantUImm4_01_0, AMFBS_InMicroMips_NotMips32r6, { MCK_ConstantUImm4_0 }, },
7750 { 8017 /* sdbbp16 */, Mips::SDBBP16_MMR6, Convert__ConstantUImm4_01_0, AMFBS_InMicroMips_HasMips32r6, { MCK_ConstantUImm4_0 }, },
7751 { 8025 /* sdc1 */, Mips::SDC1, Convert__AFGR64AsmReg1_0__PtrReg1_3__SImmOffset16_01_1, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_SImmOffset16_0, MCK__40_, MCK_PtrReg, MCK__41_ }, },
7752 { 8025 /* sdc1 */, Mips::SDC1_MM_D32, Convert__AFGR64AsmReg1_0__PtrReg1_3__SImmOffset16_01_1, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_SImmOffset16_0, MCK__40_, MCK_PtrReg, MCK__41_ }, },
7753 { 8025 /* sdc1 */, Mips::SDC164, Convert__FGR64AsmReg1_0__PtrReg1_3__SImmOffset16_01_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_SImmOffset16_0, MCK__40_, MCK_PtrReg, MCK__41_ }, },
7754 { 8025 /* sdc1 */, Mips::SDC1_D64_MMR6, Convert__FGR64AsmReg1_0__PtrReg1_3__SImmOffset16_01_1, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_SImmOffset16_0, MCK__40_, MCK_PtrReg, MCK__41_ }, },
7755 { 8025 /* sdc1 */, Mips::SDC1_MM_D64, Convert__FGR64AsmReg1_0__PtrReg1_3__SImmOffset16_01_1, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_SImmOffset16_0, MCK__40_, MCK_PtrReg, MCK__41_ }, },
7756 { 8030 /* sdc2 */, Mips::SDC2_R6, Convert__COP2AsmReg1_0__PtrReg1_3__SImmOffset11_01_1, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_COP2AsmReg, MCK_SImmOffset11_0, MCK__40_, MCK_PtrReg, MCK__41_ }, },
7757 { 8030 /* sdc2 */, Mips::SDC2_MMR6, Convert__COP2AsmReg1_0__PtrReg1_3__SImmOffset11_01_1, AMFBS_InMicroMips_HasMips32r6, { MCK_COP2AsmReg, MCK_SImmOffset11_0, MCK__40_, MCK_PtrReg, MCK__41_ }, },
7758 { 8030 /* sdc2 */, Mips::SDC2, Convert__COP2AsmReg1_0__PtrReg1_3__SImmOffset16_01_1, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_COP2AsmReg, MCK_SImmOffset16_0, MCK__40_, MCK_PtrReg, MCK__41_ }, },
7759 { 8035 /* sdc3 */, Mips::SDC3, Convert__COP3AsmReg1_0__PtrReg1_3__AnyOffset1_1, AMFBS_HasStdEnc_HasMips2_NotR5900_NotCnMips_NotInMicroMips, { MCK_COP3AsmReg, MCK_AnyOffset, MCK__40_, MCK_PtrReg, MCK__41_ }, },
7760 { 8040 /* sdl */, Mips::SDL, Convert__GPR64AsmReg1_0__PtrReg1_3__AnyOffset1_1, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, { MCK_GPR64AsmReg, MCK_AnyOffset, MCK__40_, MCK_PtrReg, MCK__41_ }, },
7761 { 8044 /* sdr */, Mips::SDR, Convert__GPR64AsmReg1_0__PtrReg1_3__AnyOffset1_1, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, { MCK_GPR64AsmReg, MCK_AnyOffset, MCK__40_, MCK_PtrReg, MCK__41_ }, },
7762 { 8048 /* sdxc1 */, Mips::SDXC1, Convert__AFGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
7763 { 8048 /* sdxc1 */, Mips::SDXC164, Convert__FGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
7764 { 8054 /* seb */, Mips::SebRx16, Convert__Reg1_0__Tie0_1_1, AMFBS_InMips16Mode, { MCK_CPU16Regs }, },
7765 { 8054 /* seb */, Mips::SEB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips, { MCK_GPR32AsmReg }, },
7766 { 8054 /* seb */, Mips::SEB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0, AMFBS_InMicroMips, { MCK_GPR32AsmReg }, },
7767 { 8054 /* seb */, Mips::SEB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7768 { 8054 /* seb */, Mips::SEB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7769 { 8058 /* seh */, Mips::SehRx16, Convert__Reg1_0__Tie0_1_1, AMFBS_InMips16Mode, { MCK_CPU16Regs }, },
7770 { 8058 /* seh */, Mips::SEH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips, { MCK_GPR32AsmReg }, },
7771 { 8058 /* seh */, Mips::SEH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0, AMFBS_InMicroMips, { MCK_GPR32AsmReg }, },
7772 { 8058 /* seh */, Mips::SEH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7773 { 8058 /* seh */, Mips::SEH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7774 { 8062 /* sel.d */, Mips::SEL_D, Convert__FGR64AsmReg1_0__Tie0_1_1__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7775 { 8062 /* sel.d */, Mips::SEL_D_MMR6, Convert__FGR64AsmReg1_0__Tie0_1_1__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7776 { 8068 /* sel.s */, Mips::SEL_S, Convert__FGR32AsmReg1_0__Tie0_1_1__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7777 { 8068 /* sel.s */, Mips::SEL_S_MMR6, Convert__FGR32AsmReg1_0__Tie0_1_1__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7778 { 8074 /* seleqz */, Mips::SELEQZ, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_IsGP32bit_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7779 { 8074 /* seleqz */, Mips::SELEQZ_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7780 { 8074 /* seleqz */, Mips::SELEQZ64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_IsGP64bit_HasMips32r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
7781 { 8081 /* seleqz.d */, Mips::SELEQZ_D, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7782 { 8081 /* seleqz.d */, Mips::SELEQZ_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7783 { 8090 /* seleqz.s */, Mips::SELEQZ_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7784 { 8090 /* seleqz.s */, Mips::SELEQZ_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7785 { 8099 /* selnez */, Mips::SELNEZ, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_IsGP32bit_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7786 { 8099 /* selnez */, Mips::SELNEZ_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7787 { 8099 /* selnez */, Mips::SELNEZ64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_IsGP64bit_HasMips32r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
7788 { 8106 /* selnez.d */, Mips::SELNEZ_D, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7789 { 8106 /* selnez.d */, Mips::SELNEZ_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7790 { 8115 /* selnez.s */, Mips::SELNEZ_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7791 { 8115 /* selnez.s */, Mips::SELNEZ_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7792 { 8124 /* seq */, Mips::SEQMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_NotCnMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7793 { 8124 /* seq */, Mips::SEQIMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm321_1, AMFBS_NotCnMips, { MCK_GPR32AsmReg, MCK_SImm32 }, },
7794 { 8124 /* seq */, Mips::SEQ, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
7795 { 8124 /* seq */, Mips::SEQMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_NotCnMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7796 { 8124 /* seq */, Mips::SEQIMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_NotCnMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
7797 { 8124 /* seq */, Mips::SEQ, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
7798 { 8128 /* seqi */, Mips::SEQi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantSImm10_01_1, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_ConstantSImm10_0 }, },
7799 { 8128 /* seqi */, Mips::SEQi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantSImm10_01_2, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantSImm10_0 }, },
7800 { 8133 /* sge */, Mips::SGE, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7801 { 8133 /* sge */, Mips::SGEImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm321_1, AMFBS_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm32 }, },
7802 { 8133 /* sge */, Mips::SGEImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, AMFBS_IsGP64bit, { MCK_GPR64AsmReg, MCK_Imm }, },
7803 { 8133 /* sge */, Mips::SGE, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7804 { 8133 /* sge */, Mips::SGEImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm321_2, AMFBS_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32 }, },
7805 { 8133 /* sge */, Mips::SGEImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, AMFBS_IsGP64bit, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, },
7806 { 8137 /* sgeu */, Mips::SGEU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7807 { 8137 /* sgeu */, Mips::SGEUImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm32_Coerced1_1, AMFBS_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_UImm32_Coerced }, },
7808 { 8137 /* sgeu */, Mips::SGEUImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, AMFBS_IsGP64bit, { MCK_GPR64AsmReg, MCK_Imm }, },
7809 { 8137 /* sgeu */, Mips::SGEU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7810 { 8137 /* sgeu */, Mips::SGEUImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm32_Coerced1_2, AMFBS_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm32_Coerced }, },
7811 { 8137 /* sgeu */, Mips::SGEUImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, AMFBS_IsGP64bit, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, },
7812 { 8142 /* sgt */, Mips::SLT, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_0, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7813 { 8142 /* sgt */, Mips::SLT_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_0, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7814 { 8142 /* sgt */, Mips::SGTImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm321_1, AMFBS_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm32 }, },
7815 { 8142 /* sgt */, Mips::SGTImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, AMFBS_IsGP64bit, { MCK_GPR64AsmReg, MCK_Imm }, },
7816 { 8142 /* sgt */, Mips::SLT, Convert__GPR32AsmReg1_0__GPR32AsmReg1_2__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7817 { 8142 /* sgt */, Mips::SLT_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_2__GPR32AsmReg1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7818 { 8142 /* sgt */, Mips::SGTImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm321_2, AMFBS_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32 }, },
7819 { 8142 /* sgt */, Mips::SGTImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, AMFBS_IsGP64bit, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, },
7820 { 8146 /* sgtu */, Mips::SLTu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_0, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7821 { 8146 /* sgtu */, Mips::SLTu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_0, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7822 { 8146 /* sgtu */, Mips::SGTUImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm32_Coerced1_1, AMFBS_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_UImm32_Coerced }, },
7823 { 8146 /* sgtu */, Mips::SGTUImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, AMFBS_IsGP64bit, { MCK_GPR64AsmReg, MCK_Imm }, },
7824 { 8146 /* sgtu */, Mips::SLTu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_2__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7825 { 8146 /* sgtu */, Mips::SLTu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_2__GPR32AsmReg1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7826 { 8146 /* sgtu */, Mips::SGTUImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm32_Coerced1_2, AMFBS_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm32_Coerced }, },
7827 { 8146 /* sgtu */, Mips::SGTUImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, AMFBS_IsGP64bit, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, },
7828 { 8151 /* sh */, Mips::ShRxRyOffMemX16, Convert__Reg1_0__Reg1_3__SImm161_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_SImm16, MCK__40_, MCK_CPU16Regs, MCK__41_ }, },
7829 { 8151 /* sh */, Mips::SH, Convert__GPR32AsmReg1_0__PtrReg1_3__AnyOffset1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_AnyOffset, MCK__40_, MCK_PtrReg, MCK__41_ }, },
7830 { 8151 /* sh */, Mips::SH_MMR6, Convert__GPR32AsmReg1_0__PtrReg1_3__AnyOffset1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_AnyOffset, MCK__40_, MCK_PtrReg, MCK__41_ }, },
7831 { 8151 /* sh */, Mips::SH_MM, Convert__GPR32AsmReg1_0__PtrReg1_3__AnyOffset1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_AnyOffset, MCK__40_, MCK_PtrReg, MCK__41_ }, },
7832 { 8154 /* sh16 */, Mips::SH16_MM, Convert__GPRMM16AsmRegZero1_0__GPRMM16AsmReg1_3__UImmOffset4_101_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPRMM16AsmRegZero, MCK_UImmOffset4_10, MCK__40_, MCK_GPRMM16AsmReg, MCK__41_ }, },
7833 { 8154 /* sh16 */, Mips::SH16_MMR6, Convert__GPRMM16AsmRegZero1_0__GPRMM16AsmReg1_3__UImmOffset4_101_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPRMM16AsmRegZero, MCK_UImmOffset4_10, MCK__40_, MCK_GPRMM16AsmReg, MCK__41_ }, },
7834 { 8159 /* she */, Mips::SHE, Convert__GPR32AsmReg1_0__PtrReg1_3__SImmOffset9_01_1, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImmOffset9_0, MCK__40_, MCK_PtrReg, MCK__41_ }, },
7835 { 8159 /* she */, Mips::SHE_MM, Convert__GPR32AsmReg1_0__PtrReg1_3__SImmOffset9_01_1, AMFBS_InMicroMips_HasEVA, { MCK_GPR32AsmReg, MCK_SImmOffset9_0, MCK__40_, MCK_PtrReg, MCK__41_ }, },
7836 { 8163 /* shf.b */, Mips::SHF_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm8_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm8_0 }, },
7837 { 8169 /* shf.h */, Mips::SHF_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm8_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm8_0 }, },
7838 { 8175 /* shf.w */, Mips::SHF_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm8_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm8_0 }, },
7839 { 8181 /* shilo */, Mips::SHILO_MM, Convert__ACC64DSPAsmReg1_0__ConstantSImm6_01_1__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_ConstantSImm6_0 }, },
7840 { 8181 /* shilo */, Mips::SHILO, Convert__ACC64DSPAsmReg1_0__ConstantSImm6_01_1__Tie0_1_1, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_ConstantSImm6_0 }, },
7841 { 8187 /* shilov */, Mips::SHILOV_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, },
7842 { 8187 /* shilov */, Mips::SHILOV, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__Tie0_1_1, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, },
7843 { 8194 /* shll.ph */, Mips::SHLL_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
7844 { 8194 /* shll.ph */, Mips::SHLL_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
7845 { 8202 /* shll.qb */, Mips::SHLL_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm3_0 }, },
7846 { 8202 /* shll.qb */, Mips::SHLL_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm3_0 }, },
7847 { 8210 /* shll_s.ph */, Mips::SHLL_S_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
7848 { 8210 /* shll_s.ph */, Mips::SHLL_S_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
7849 { 8220 /* shll_s.w */, Mips::SHLL_S_W_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7850 { 8220 /* shll_s.w */, Mips::SHLL_S_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7851 { 8229 /* shllv.ph */, Mips::SHLLV_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7852 { 8229 /* shllv.ph */, Mips::SHLLV_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7853 { 8238 /* shllv.qb */, Mips::SHLLV_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7854 { 8238 /* shllv.qb */, Mips::SHLLV_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7855 { 8247 /* shllv_s.ph */, Mips::SHLLV_S_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7856 { 8247 /* shllv_s.ph */, Mips::SHLLV_S_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7857 { 8258 /* shllv_s.w */, Mips::SHLLV_S_W_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7858 { 8258 /* shllv_s.w */, Mips::SHLLV_S_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7859 { 8268 /* shra.ph */, Mips::SHRA_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
7860 { 8268 /* shra.ph */, Mips::SHRA_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
7861 { 8276 /* shra.qb */, Mips::SHRA_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm3_0 }, },
7862 { 8276 /* shra.qb */, Mips::SHRA_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm3_0 }, },
7863 { 8284 /* shra_r.ph */, Mips::SHRA_R_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
7864 { 8284 /* shra_r.ph */, Mips::SHRA_R_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
7865 { 8294 /* shra_r.qb */, Mips::SHRA_R_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm3_0 }, },
7866 { 8294 /* shra_r.qb */, Mips::SHRA_R_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm3_0 }, },
7867 { 8304 /* shra_r.w */, Mips::SHRA_R_W_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7868 { 8304 /* shra_r.w */, Mips::SHRA_R_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7869 { 8313 /* shrav.ph */, Mips::SHRAV_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7870 { 8313 /* shrav.ph */, Mips::SHRAV_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7871 { 8322 /* shrav.qb */, Mips::SHRAV_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7872 { 8322 /* shrav.qb */, Mips::SHRAV_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7873 { 8331 /* shrav_r.ph */, Mips::SHRAV_R_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7874 { 8331 /* shrav_r.ph */, Mips::SHRAV_R_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7875 { 8342 /* shrav_r.qb */, Mips::SHRAV_R_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7876 { 8342 /* shrav_r.qb */, Mips::SHRAV_R_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7877 { 8353 /* shrav_r.w */, Mips::SHRAV_R_W_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7878 { 8353 /* shrav_r.w */, Mips::SHRAV_R_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7879 { 8363 /* shrl.ph */, Mips::SHRL_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
7880 { 8363 /* shrl.ph */, Mips::SHRL_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
7881 { 8371 /* shrl.qb */, Mips::SHRL_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm3_0 }, },
7882 { 8371 /* shrl.qb */, Mips::SHRL_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm3_0 }, },
7883 { 8379 /* shrlv.ph */, Mips::SHRLV_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7884 { 8379 /* shrlv.ph */, Mips::SHRLV_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7885 { 8388 /* shrlv.qb */, Mips::SHRLV_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7886 { 8388 /* shrlv.qb */, Mips::SHRLV_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7887 { 8397 /* sigrie */, Mips::SIGRIE, Convert__imm_95_0, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { }, },
7888 { 8397 /* sigrie */, Mips::SIGRIE_MMR6, Convert__imm_95_0, AMFBS_InMicroMips_HasMips32r6, { }, },
7889 { 8397 /* sigrie */, Mips::SIGRIE, Convert__UImm161_0, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_UImm16 }, },
7890 { 8397 /* sigrie */, Mips::SIGRIE_MMR6, Convert__UImm161_0, AMFBS_InMicroMips_HasMips32r6, { MCK_UImm16 }, },
7891 { 8404 /* sld.b */, Mips::SLD_B, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__GPR32AsmReg1_3, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_GPR32AsmReg, MCK__93_ }, },
7892 { 8410 /* sld.d */, Mips::SLD_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__GPR32AsmReg1_3, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_GPR32AsmReg, MCK__93_ }, },
7893 { 8416 /* sld.h */, Mips::SLD_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__GPR32AsmReg1_3, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_GPR32AsmReg, MCK__93_ }, },
7894 { 8422 /* sld.w */, Mips::SLD_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__GPR32AsmReg1_3, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_GPR32AsmReg, MCK__93_ }, },
7895 { 8428 /* sldi.b */, Mips::SLDI_B, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm4_01_3, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm4_0, MCK__93_ }, },
7896 { 8435 /* sldi.d */, Mips::SLDI_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm1_01_3, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm1_0, MCK__93_ }, },
7897 { 8442 /* sldi.h */, Mips::SLDI_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm3_01_3, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm3_0, MCK__93_ }, },
7898 { 8449 /* sldi.w */, Mips::SLDI_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm2_01_3, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm2_0, MCK__93_ }, },
7899 { 8456 /* sle */, Mips::SLE, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7900 { 8456 /* sle */, Mips::SLEImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm321_1, AMFBS_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm32 }, },
7901 { 8456 /* sle */, Mips::SLEImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, AMFBS_IsGP64bit, { MCK_GPR64AsmReg, MCK_Imm }, },
7902 { 8456 /* sle */, Mips::SLE, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7903 { 8456 /* sle */, Mips::SLEImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm321_2, AMFBS_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32 }, },
7904 { 8456 /* sle */, Mips::SLEImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, AMFBS_IsGP64bit, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, },
7905 { 8460 /* sleu */, Mips::SLEU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7906 { 8460 /* sleu */, Mips::SLEUImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm32_Coerced1_1, AMFBS_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_UImm32_Coerced }, },
7907 { 8460 /* sleu */, Mips::SLEUImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, AMFBS_IsGP64bit, { MCK_GPR64AsmReg, MCK_Imm }, },
7908 { 8460 /* sleu */, Mips::SLEU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7909 { 8460 /* sleu */, Mips::SLEUImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm32_Coerced1_2, AMFBS_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm32_Coerced }, },
7910 { 8460 /* sleu */, Mips::SLEUImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, AMFBS_IsGP64bit, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, },
7911 { 8465 /* sll */, Mips::SLLV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7912 { 8465 /* sll */, Mips::SLLV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7913 { 8465 /* sll */, Mips::SLL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7914 { 8465 /* sll */, Mips::SLL_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7915 { 8465 /* sll */, Mips::SLL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7916 { 8465 /* sll */, Mips::SLL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7917 { 8465 /* sll */, Mips::SllX16, Convert__Reg1_0__Reg1_1__ConstantUImm5_01_2, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs, MCK_ConstantUImm5_0 }, },
7918 { 8465 /* sll */, Mips::SLLV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7919 { 8465 /* sll */, Mips::SLLV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7920 { 8465 /* sll */, Mips::SLL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7921 { 8465 /* sll */, Mips::SLL_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7922 { 8465 /* sll */, Mips::SLL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7923 { 8469 /* sll.b */, Mips::SLL_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7924 { 8475 /* sll.d */, Mips::SLL_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7925 { 8481 /* sll.h */, Mips::SLL_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7926 { 8487 /* sll.w */, Mips::SLL_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7927 { 8493 /* sll16 */, Mips::SLL16_MM, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Imm1_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_Imm }, },
7928 { 8493 /* sll16 */, Mips::SLL16_MMR6, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Imm1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_Imm }, },
7929 { 8499 /* slli.b */, Mips::SLLI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, },
7930 { 8506 /* slli.d */, Mips::SLLI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, },
7931 { 8513 /* slli.h */, Mips::SLLI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, },
7932 { 8520 /* slli.w */, Mips::SLLI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
7933 { 8527 /* sllv */, Mips::SllvRxRy16, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs }, },
7934 { 8527 /* sllv */, Mips::SLLV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7935 { 8527 /* sllv */, Mips::SLLV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7936 { 8532 /* slt */, Mips::SltRxRy16, Convert__Reg1_0__Reg1_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs }, },
7937 { 8532 /* slt */, Mips::SLTi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
7938 { 8532 /* slt */, Mips::SLTi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
7939 { 8532 /* slt */, Mips::SLTImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, AMFBS_IsGP64bit, { MCK_GPR64AsmReg, MCK_Imm }, },
7940 { 8532 /* slt */, Mips::SLT, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7941 { 8532 /* slt */, Mips::SLT_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7942 { 8532 /* slt */, Mips::SLTi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
7943 { 8532 /* slt */, Mips::SLTi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
7944 { 8532 /* slt */, Mips::SLTImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, AMFBS_IsGP64bit, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, },
7945 { 8536 /* slti */, Mips::SltiRxImmX16, Convert__Reg1_0__SImm161_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_SImm16 }, },
7946 { 8536 /* slti */, Mips::SLTi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16 }, },
7947 { 8536 /* slti */, Mips::SLTi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16 }, },
7948 { 8536 /* slti */, Mips::SltiRxImm16, Convert__Reg1_0__SImm161_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_SImm16, MCK__HASH_, MCK_16, MCK_bit, MCK_inst }, },
7949 { 8541 /* sltiu */, Mips::SltiuRxImmX16, Convert__Reg1_0__SImm161_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_SImm16 }, },
7950 { 8541 /* sltiu */, Mips::SLTiu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16 }, },
7951 { 8541 /* sltiu */, Mips::SLTiu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16 }, },
7952 { 8541 /* sltiu */, Mips::SltiuRxImm16, Convert__Reg1_0__SImm161_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_SImm16, MCK__HASH_, MCK_16, MCK_bit, MCK_inst }, },
7953 { 8547 /* sltu */, Mips::SltuRxRy16, Convert__Reg1_0__Reg1_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs }, },
7954 { 8547 /* sltu */, Mips::SLTiu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
7955 { 8547 /* sltu */, Mips::SLTiu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
7956 { 8547 /* sltu */, Mips::SLTUImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, AMFBS_IsGP64bit, { MCK_GPR64AsmReg, MCK_Imm }, },
7957 { 8547 /* sltu */, Mips::SLTu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7958 { 8547 /* sltu */, Mips::SLTu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7959 { 8547 /* sltu */, Mips::SLTiu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
7960 { 8547 /* sltu */, Mips::SLTiu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
7961 { 8547 /* sltu */, Mips::SLTUImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, AMFBS_IsGP64bit, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, },
7962 { 8552 /* sne */, Mips::SNEMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_NotCnMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7963 { 8552 /* sne */, Mips::SNEIMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm321_1, AMFBS_NotCnMips, { MCK_GPR32AsmReg, MCK_SImm32 }, },
7964 { 8552 /* sne */, Mips::SNE, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
7965 { 8552 /* sne */, Mips::SNEMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_NotCnMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7966 { 8552 /* sne */, Mips::SNEIMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_NotCnMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
7967 { 8552 /* sne */, Mips::SNE, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
7968 { 8556 /* snei */, Mips::SNEi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantSImm10_01_1, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_ConstantSImm10_0 }, },
7969 { 8556 /* snei */, Mips::SNEi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantSImm10_01_2, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantSImm10_0 }, },
7970 { 8561 /* splat.b */, Mips::SPLAT_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__GPR32AsmReg1_3, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_GPR32AsmReg, MCK__93_ }, },
7971 { 8569 /* splat.d */, Mips::SPLAT_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__GPR32AsmReg1_3, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_GPR32AsmReg, MCK__93_ }, },
7972 { 8577 /* splat.h */, Mips::SPLAT_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__GPR32AsmReg1_3, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_GPR32AsmReg, MCK__93_ }, },
7973 { 8585 /* splat.w */, Mips::SPLAT_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__GPR32AsmReg1_3, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_GPR32AsmReg, MCK__93_ }, },
7974 { 8593 /* splati.b */, Mips::SPLATI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_3, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm4_0, MCK__93_ }, },
7975 { 8602 /* splati.d */, Mips::SPLATI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm1_01_3, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm1_0, MCK__93_ }, },
7976 { 8611 /* splati.h */, Mips::SPLATI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_3, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm3_0, MCK__93_ }, },
7977 { 8620 /* splati.w */, Mips::SPLATI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm2_01_3, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm2_0, MCK__93_ }, },
7978 { 8629 /* sqrt.d */, Mips::FSQRT_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
7979 { 8629 /* sqrt.d */, Mips::FSQRT_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
7980 { 8629 /* sqrt.d */, Mips::FSQRT_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7981 { 8629 /* sqrt.d */, Mips::FSQRT_D64_MM, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7982 { 8636 /* sqrt.s */, Mips::FSQRT_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7983 { 8636 /* sqrt.s */, Mips::FSQRT_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7984 { 8643 /* sra */, Mips::SRAV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7985 { 8643 /* sra */, Mips::SRAV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7986 { 8643 /* sra */, Mips::SRA, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7987 { 8643 /* sra */, Mips::SRA_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7988 { 8643 /* sra */, Mips::SRA_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7989 { 8643 /* sra */, Mips::SraX16, Convert__Reg1_0__Reg1_1__ConstantUImm5_01_2, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs, MCK_ConstantUImm5_0 }, },
7990 { 8643 /* sra */, Mips::SRAV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7991 { 8643 /* sra */, Mips::SRAV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7992 { 8643 /* sra */, Mips::SRA, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7993 { 8643 /* sra */, Mips::SRA_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7994 { 8647 /* sra.b */, Mips::SRA_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7995 { 8653 /* sra.d */, Mips::SRA_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7996 { 8659 /* sra.h */, Mips::SRA_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7997 { 8665 /* sra.w */, Mips::SRA_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7998 { 8671 /* srai.b */, Mips::SRAI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, },
7999 { 8678 /* srai.d */, Mips::SRAI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, },
8000 { 8685 /* srai.h */, Mips::SRAI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, },
8001 { 8692 /* srai.w */, Mips::SRAI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
8002 { 8699 /* srar.b */, Mips::SRAR_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
8003 { 8706 /* srar.d */, Mips::SRAR_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
8004 { 8713 /* srar.h */, Mips::SRAR_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
8005 { 8720 /* srar.w */, Mips::SRAR_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
8006 { 8727 /* srari.b */, Mips::SRARI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, },
8007 { 8735 /* srari.d */, Mips::SRARI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, },
8008 { 8743 /* srari.h */, Mips::SRARI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, },
8009 { 8751 /* srari.w */, Mips::SRARI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
8010 { 8759 /* srav */, Mips::SravRxRy16, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs }, },
8011 { 8759 /* srav */, Mips::SRAV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
8012 { 8759 /* srav */, Mips::SRAV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
8013 { 8764 /* srl */, Mips::SRLV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
8014 { 8764 /* srl */, Mips::SRLV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
8015 { 8764 /* srl */, Mips::SRL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
8016 { 8764 /* srl */, Mips::SRL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
8017 { 8764 /* srl */, Mips::SRL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
8018 { 8764 /* srl */, Mips::SrlX16, Convert__Reg1_0__Reg1_1__ConstantUImm5_01_2, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs, MCK_ConstantUImm5_0 }, },
8019 { 8764 /* srl */, Mips::SRLV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
8020 { 8764 /* srl */, Mips::SRLV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
8021 { 8764 /* srl */, Mips::SRL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
8022 { 8764 /* srl */, Mips::SRL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
8023 { 8768 /* srl.b */, Mips::SRL_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
8024 { 8774 /* srl.d */, Mips::SRL_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
8025 { 8780 /* srl.h */, Mips::SRL_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
8026 { 8786 /* srl.w */, Mips::SRL_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
8027 { 8792 /* srl16 */, Mips::SRL16_MM, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Imm1_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_Imm }, },
8028 { 8792 /* srl16 */, Mips::SRL16_MMR6, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Imm1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_Imm }, },
8029 { 8798 /* srli.b */, Mips::SRLI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, },
8030 { 8805 /* srli.d */, Mips::SRLI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, },
8031 { 8812 /* srli.h */, Mips::SRLI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, },
8032 { 8819 /* srli.w */, Mips::SRLI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
8033 { 8826 /* srlr.b */, Mips::SRLR_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
8034 { 8833 /* srlr.d */, Mips::SRLR_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
8035 { 8840 /* srlr.h */, Mips::SRLR_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
8036 { 8847 /* srlr.w */, Mips::SRLR_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
8037 { 8854 /* srlri.b */, Mips::SRLRI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, },
8038 { 8862 /* srlri.d */, Mips::SRLRI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, },
8039 { 8870 /* srlri.h */, Mips::SRLRI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, },
8040 { 8878 /* srlri.w */, Mips::SRLRI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
8041 { 8886 /* srlv */, Mips::SrlvRxRy16, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs }, },
8042 { 8886 /* srlv */, Mips::SRLV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
8043 { 8886 /* srlv */, Mips::SRLV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
8044 { 8891 /* ssnop */, Mips::SSNOP, Convert_NoOperands, AMFBS_HasStdEnc_NotInMicroMips, { }, },
8045 { 8891 /* ssnop */, Mips::SSNOP_MMR6, Convert_NoOperands, AMFBS_InMicroMips_HasMips32r6, { }, },
8046 { 8891 /* ssnop */, Mips::SSNOP_MM, Convert_NoOperands, AMFBS_InMicroMips, { }, },
8047 { 8897 /* st.b */, Mips::ST_B, Convert__MSA128AsmReg1_0__PtrReg1_3__SImmOffset10_01_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_SImmOffset10_0, MCK__40_, MCK_PtrReg, MCK__41_ }, },
8048 { 8902 /* st.d */, Mips::ST_D, Convert__MSA128AsmReg1_0__PtrReg1_3__SImmOffset10_31_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_SImmOffset10_3, MCK__40_, MCK_PtrReg, MCK__41_ }, },
8049 { 8907 /* st.h */, Mips::ST_H, Convert__MSA128AsmReg1_0__PtrReg1_3__SImmOffset10_11_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_SImmOffset10_1, MCK__40_, MCK_PtrReg, MCK__41_ }, },
8050 { 8912 /* st.w */, Mips::ST_W, Convert__MSA128AsmReg1_0__PtrReg1_3__SImmOffset10_21_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_SImmOffset10_2, MCK__40_, MCK_PtrReg, MCK__41_ }, },
8051 { 8917 /* sub */, Mips::SUB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
8052 { 8917 /* sub */, Mips::SUB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
8053 { 8917 /* sub */, Mips::SUB_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
8054 { 8917 /* sub */, Mips::ADDi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__InvNum1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_InvNum }, },
8055 { 8917 /* sub */, Mips::SUB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
8056 { 8917 /* sub */, Mips::SUB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
8057 { 8917 /* sub */, Mips::SUB_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
8058 { 8917 /* sub */, Mips::ADDi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__InvNum1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_InvNum }, },
8059 { 8921 /* sub.d */, Mips::FSUB_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
8060 { 8921 /* sub.d */, Mips::FSUB_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
8061 { 8921 /* sub.d */, Mips::FSUB_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
8062 { 8921 /* sub.d */, Mips::FSUB_D64_MM, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
8063 { 8927 /* sub.ps */, Mips::FSUB_PS64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
8064 { 8934 /* sub.s */, Mips::FSUB_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
8065 { 8934 /* sub.s */, Mips::FSUB_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_2__FGR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
8066 { 8934 /* sub.s */, Mips::FSUB_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
8067 { 8940 /* subq.ph */, Mips::SUBQ_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
8068 { 8940 /* subq.ph */, Mips::SUBQ_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
8069 { 8948 /* subq_s.ph */, Mips::SUBQ_S_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
8070 { 8948 /* subq_s.ph */, Mips::SUBQ_S_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
8071 { 8958 /* subq_s.w */, Mips::SUBQ_S_W_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
8072 { 8958 /* subq_s.w */, Mips::SUBQ_S_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
8073 { 8967 /* subqh.ph */, Mips::SUBQH_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
8074 { 8967 /* subqh.ph */, Mips::SUBQH_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
8075 { 8976 /* subqh.w */, Mips::SUBQH_W_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
8076 { 8976 /* subqh.w */, Mips::SUBQH_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
8077 { 8984 /* subqh_r.ph */, Mips::SUBQH_R_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
8078 { 8984 /* subqh_r.ph */, Mips::SUBQH_R_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
8079 { 8995 /* subqh_r.w */, Mips::SUBQH_R_W_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
8080 { 8995 /* subqh_r.w */, Mips::SUBQH_R_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
8081 { 9005 /* subs_s.b */, Mips::SUBS_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
8082 { 9014 /* subs_s.d */, Mips::SUBS_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
8083 { 9023 /* subs_s.h */, Mips::SUBS_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
8084 { 9032 /* subs_s.w */, Mips::SUBS_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
8085 { 9041 /* subs_u.b */, Mips::SUBS_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
8086 { 9050 /* subs_u.d */, Mips::SUBS_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
8087 { 9059 /* subs_u.h */, Mips::SUBS_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
8088 { 9068 /* subs_u.w */, Mips::SUBS_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
8089 { 9077 /* subsus_u.b */, Mips::SUBSUS_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
8090 { 9088 /* subsus_u.d */, Mips::SUBSUS_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
8091 { 9099 /* subsus_u.h */, Mips::SUBSUS_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
8092 { 9110 /* subsus_u.w */, Mips::SUBSUS_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
8093 { 9121 /* subsuu_s.b */, Mips::SUBSUU_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
8094 { 9132 /* subsuu_s.d */, Mips::SUBSUU_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
8095 { 9143 /* subsuu_s.h */, Mips::SUBSUU_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
8096 { 9154 /* subsuu_s.w */, Mips::SUBSUU_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
8097 { 9165 /* subu */, Mips::SUBU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
8098 { 9165 /* subu */, Mips::SUBu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
8099 { 9165 /* subu */, Mips::SUBu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
8100 { 9165 /* subu */, Mips::ADDiu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__InvNum1_1, AMFBS_None, { MCK_GPR32AsmReg, MCK_InvNum }, },
8101 { 9165 /* subu */, Mips::SubuRxRyRz16, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs, MCK_CPU16Regs }, },
8102 { 9165 /* subu */, Mips::SUBU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
8103 { 9165 /* subu */, Mips::SUBu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
8104 { 9165 /* subu */, Mips::SUBu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
8105 { 9165 /* subu */, Mips::ADDiu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__InvNum1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_InvNum }, },
8106 { 9170 /* subu.ph */, Mips::SUBU_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
8107 { 9170 /* subu.ph */, Mips::SUBU_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
8108 { 9178 /* subu.qb */, Mips::SUBU_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
8109 { 9178 /* subu.qb */, Mips::SUBU_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
8110 { 9186 /* subu16 */, Mips::SUBU16_MM, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__GPRMM16AsmReg1_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, },
8111 { 9186 /* subu16 */, Mips::SUBU16_MMR6, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__GPRMM16AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, },
8112 { 9193 /* subu_s.ph */, Mips::SUBU_S_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
8113 { 9193 /* subu_s.ph */, Mips::SUBU_S_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
8114 { 9203 /* subu_s.qb */, Mips::SUBU_S_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
8115 { 9203 /* subu_s.qb */, Mips::SUBU_S_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
8116 { 9213 /* subuh.qb */, Mips::SUBUH_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
8117 { 9213 /* subuh.qb */, Mips::SUBUH_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
8118 { 9222 /* subuh_r.qb */, Mips::SUBUH_R_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
8119 { 9222 /* subuh_r.qb */, Mips::SUBUH_R_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
8120 { 9233 /* subv.b */, Mips::SUBV_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
8121 { 9240 /* subv.d */, Mips::SUBV_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
8122 { 9247 /* subv.h */, Mips::SUBV_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
8123 { 9254 /* subv.w */, Mips::SUBV_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
8124 { 9261 /* subvi.b */, Mips::SUBVI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
8125 { 9269 /* subvi.d */, Mips::SUBVI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
8126 { 9277 /* subvi.h */, Mips::SUBVI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
8127 { 9285 /* subvi.w */, Mips::SUBVI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
8128 { 9293 /* suxc1 */, Mips::SUXC1, Convert__AFGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
8129 { 9293 /* suxc1 */, Mips::SUXC164, Convert__FGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
8130 { 9293 /* suxc1 */, Mips::SUXC1_MM, Convert__FGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
8131 { 9299 /* sw */, Mips::SwRxRyOffMemX16, Convert__Reg1_0__Reg1_3__SImm161_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_SImm16, MCK__40_, MCK_CPU16Regs, MCK__41_ }, },
8132 { 9299 /* sw */, Mips::SwRxSpImmX16, Convert__Reg1_0__Reg1_3__SImm161_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_SImm16, MCK__40_, MCK_CPU16RegsPlusSP, MCK__41_ }, },
8133 { 9299 /* sw */, Mips::SWSP_MMR6, Convert__GPR32AsmReg1_0__MemBaseSP1_3__UImmOffset5_201_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_UImmOffset5_20, MCK__40_, MCK_MemBaseSP, MCK__41_ }, },
8134 { 9299 /* sw */, Mips::SWSP_MM, Convert__GPR32AsmReg1_0__MemBaseSP1_3__UImmOffset5_201_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_UImmOffset5_20, MCK__40_, MCK_MemBaseSP, MCK__41_ }, },
8135 { 9299 /* sw */, Mips::SW, Convert__GPR32AsmReg1_0__PtrReg1_3__AnyOffset1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_AnyOffset, MCK__40_, MCK_PtrReg, MCK__41_ }, },
8136 { 9299 /* sw */, Mips::SWDSP, Convert__GPR32AsmReg1_0__PtrReg1_3__AnyOffset1_1, AMFBS_NotInMips16Mode_HasDSP, { MCK_GPR32AsmReg, MCK_AnyOffset, MCK__40_, MCK_PtrReg, MCK__41_ }, },
8137 { 9299 /* sw */, Mips::SWDSP_MM, Convert__GPR32AsmReg1_0__PtrReg1_3__AnyOffset1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_AnyOffset, MCK__40_, MCK_PtrReg, MCK__41_ }, },
8138 { 9299 /* sw */, Mips::SW_MMR6, Convert__GPR32AsmReg1_0__PtrReg1_3__AnyOffset1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_AnyOffset, MCK__40_, MCK_PtrReg, MCK__41_ }, },
8139 { 9299 /* sw */, Mips::SW_MM, Convert__GPR32AsmReg1_0__PtrReg1_3__AnyOffset1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_AnyOffset, MCK__40_, MCK_PtrReg, MCK__41_ }, },
8140 { 9302 /* sw16 */, Mips::SW16_MM, Convert__GPRMM16AsmRegZero1_0__GPRMM16AsmReg1_3__UImmOffset4_201_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPRMM16AsmRegZero, MCK_UImmOffset4_20, MCK__40_, MCK_GPRMM16AsmReg, MCK__41_ }, },
8141 { 9302 /* sw16 */, Mips::SW16_MMR6, Convert__GPRMM16AsmRegZero1_0__GPRMM16AsmReg1_3__UImmOffset4_201_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPRMM16AsmRegZero, MCK_UImmOffset4_20, MCK__40_, MCK_GPRMM16AsmReg, MCK__41_ }, },
8142 { 9307 /* swc1 */, Mips::SWC1, Convert__FGR32AsmReg1_0__PtrReg1_3__SImmOffset16_01_1, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_SImmOffset16_0, MCK__40_, MCK_PtrReg, MCK__41_ }, },
8143 { 9307 /* swc1 */, Mips::SWC1_MM, Convert__FGR32AsmReg1_0__PtrReg1_3__SImmOffset16_01_1, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_SImmOffset16_0, MCK__40_, MCK_PtrReg, MCK__41_ }, },
8144 { 9312 /* swc2 */, Mips::SWC2_R6, Convert__COP2AsmReg1_0__PtrReg1_3__SImmOffset11_01_1, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_COP2AsmReg, MCK_SImmOffset11_0, MCK__40_, MCK_PtrReg, MCK__41_ }, },
8145 { 9312 /* swc2 */, Mips::SWC2_MMR6, Convert__COP2AsmReg1_0__PtrReg1_3__SImmOffset11_01_1, AMFBS_InMicroMips_HasMips32r6, { MCK_COP2AsmReg, MCK_SImmOffset11_0, MCK__40_, MCK_PtrReg, MCK__41_ }, },
8146 { 9312 /* swc2 */, Mips::SWC2, Convert__COP2AsmReg1_0__PtrReg1_3__SImmOffset16_01_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_COP2AsmReg, MCK_SImmOffset16_0, MCK__40_, MCK_PtrReg, MCK__41_ }, },
8147 { 9317 /* swc3 */, Mips::SWC3, Convert__COP3AsmReg1_0__PtrReg1_3__AnyOffset1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_NotCnMips_NotInMicroMips, { MCK_COP3AsmReg, MCK_AnyOffset, MCK__40_, MCK_PtrReg, MCK__41_ }, },
8148 { 9322 /* swe */, Mips::SWE, Convert__GPR32AsmReg1_0__PtrReg1_3__SImmOffset9_01_1, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImmOffset9_0, MCK__40_, MCK_PtrReg, MCK__41_ }, },
8149 { 9322 /* swe */, Mips::SWE_MM, Convert__GPR32AsmReg1_0__PtrReg1_3__SImmOffset9_01_1, AMFBS_InMicroMips_HasEVA, { MCK_GPR32AsmReg, MCK_SImmOffset9_0, MCK__40_, MCK_PtrReg, MCK__41_ }, },
8150 { 9326 /* swl */, Mips::SWL, Convert__GPR32AsmReg1_0__PtrReg1_3__AnyOffset1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_AnyOffset, MCK__40_, MCK_PtrReg, MCK__41_ }, },
8151 { 9326 /* swl */, Mips::SWL_MM, Convert__GPR32AsmReg1_0__PtrReg1_3__AnyOffset1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_AnyOffset, MCK__40_, MCK_PtrReg, MCK__41_ }, },
8152 { 9330 /* swle */, Mips::SWLE, Convert__GPR32AsmReg1_0__PtrReg1_3__SImmOffset9_01_1, AMFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImmOffset9_0, MCK__40_, MCK_PtrReg, MCK__41_ }, },
8153 { 9330 /* swle */, Mips::SWLE_MM, Convert__GPR32AsmReg1_0__PtrReg1_3__SImmOffset9_01_1, AMFBS_InMicroMips_NotMips32r6_HasEVA, { MCK_GPR32AsmReg, MCK_SImmOffset9_0, MCK__40_, MCK_PtrReg, MCK__41_ }, },
8154 { 9335 /* swm */, Mips::SWM_MM, Convert__RegList1_0__PtrReg1_3__AnyOffset1_1, AMFBS_InMicroMips, { MCK_RegList, MCK_AnyOffset, MCK__40_, MCK_PtrReg, MCK__41_ }, },
8155 { 9339 /* swm16 */, Mips::SWM16_MMR6, Convert__RegList161_0__MemBaseSP1_3__UImmOffset4_201_1, AMFBS_InMicroMips_HasMips32r6, { MCK_RegList16, MCK_UImmOffset4_20, MCK__40_, MCK_MemBaseSP, MCK__41_ }, },
8156 { 9339 /* swm16 */, Mips::SWM16_MM, Convert__RegList161_0__MemBaseSP1_3__UImmOffset6_001_1, AMFBS_InMicroMips_NotMips32r6, { MCK_RegList16, MCK_UImmOffset6_00, MCK__40_, MCK_MemBaseSP, MCK__41_ }, },
8157 { 9345 /* swm32 */, Mips::SWM32_MM, Convert__RegList1_0__PtrReg1_3__AnyOffset1_1, AMFBS_InMicroMips, { MCK_RegList, MCK_AnyOffset, MCK__40_, MCK_PtrReg, MCK__41_ }, },
8158 { 9351 /* swp */, Mips::SWP_MM, ConvertCustom_ConvertXWPOperands, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_SImmOffset12_0, MCK__40_, MCK_PtrReg, MCK__41_ }, },
8159 { 9355 /* swr */, Mips::SWR, Convert__GPR32AsmReg1_0__PtrReg1_3__AnyOffset1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_AnyOffset, MCK__40_, MCK_PtrReg, MCK__41_ }, },
8160 { 9355 /* swr */, Mips::SWR_MM, Convert__GPR32AsmReg1_0__PtrReg1_3__AnyOffset1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_AnyOffset, MCK__40_, MCK_PtrReg, MCK__41_ }, },
8161 { 9359 /* swre */, Mips::SWRE, Convert__GPR32AsmReg1_0__PtrReg1_3__SImmOffset9_01_1, AMFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImmOffset9_0, MCK__40_, MCK_PtrReg, MCK__41_ }, },
8162 { 9359 /* swre */, Mips::SWRE_MM, Convert__GPR32AsmReg1_0__PtrReg1_3__SImmOffset9_01_1, AMFBS_InMicroMips_NotMips32r6_HasEVA, { MCK_GPR32AsmReg, MCK_SImmOffset9_0, MCK__40_, MCK_PtrReg, MCK__41_ }, },
8163 { 9364 /* swsp */, Mips::SWSP_MM, Convert__GPR32AsmReg1_0__MemBaseSP1_3__UImmOffset5_201_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_UImmOffset5_20, MCK__40_, MCK_MemBaseSP, MCK__41_ }, },
8164 { 9369 /* swxc1 */, Mips::SWXC1, Convert__FGR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
8165 { 9369 /* swxc1 */, Mips::SWXC1_MM, Convert__FGR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
8166 { 9375 /* sync */, Mips::SYNC, Convert__imm_95_0, AMFBS_HasStdEnc_HasMips2_NotInMicroMips, { }, },
8167 { 9375 /* sync */, Mips::SYNC_MMR6, Convert__imm_95_0, AMFBS_InMicroMips_HasMips32r6, { }, },
8168 { 9375 /* sync */, Mips::SYNC_MM, Convert__imm_95_0, AMFBS_InMicroMips, { }, },
8169 { 9375 /* sync */, Mips::SYNC, Convert__ConstantUImm5_01_0, AMFBS_HasStdEnc_HasMips2_NotInMicroMips, { MCK_ConstantUImm5_0 }, },
8170 { 9375 /* sync */, Mips::SYNC_MMR6, Convert__ConstantUImm5_01_0, AMFBS_InMicroMips_HasMips32r6, { MCK_ConstantUImm5_0 }, },
8171 { 9375 /* sync */, Mips::SYNC_MM, Convert__ConstantUImm5_01_0, AMFBS_InMicroMips, { MCK_ConstantUImm5_0 }, },
8172 { 9380 /* sync_acquire */, Mips::SYNC, Convert__imm_95_17, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips, { }, },
8173 { 9393 /* sync_mb */, Mips::SYNC, Convert__imm_95_16, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips, { }, },
8174 { 9401 /* sync_release */, Mips::SYNC, Convert__imm_95_18, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips, { }, },
8175 { 9414 /* sync_rmb */, Mips::SYNC, Convert__imm_95_19, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips, { }, },
8176 { 9423 /* sync_wmb */, Mips::SYNC, Convert__imm_95_4, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips, { }, },
8177 { 9432 /* synci */, Mips::SYNCI, Convert__PtrReg1_2__SImmOffset16_01_0, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips, { MCK_SImmOffset16_0, MCK__40_, MCK_PtrReg, MCK__41_ }, },
8178 { 9432 /* synci */, Mips::SYNCI_MM, Convert__PtrReg1_2__SImmOffset16_01_0, AMFBS_InMicroMips_NotMips32r6, { MCK_SImmOffset16_0, MCK__40_, MCK_PtrReg, MCK__41_ }, },
8179 { 9432 /* synci */, Mips::SYNCI_MMR6, Convert__PtrReg1_2__SImmOffset16_01_0, AMFBS_InMicroMips_HasMips32r6, { MCK_SImmOffset16_0, MCK__40_, MCK_PtrReg, MCK__41_ }, },
8180 { 9438 /* synciobdma */, Mips::SYNC, Convert__imm_95_2, AMFBS_HasMips64_HasCnMips, { }, },
8181 { 9449 /* syncs */, Mips::SYNC, Convert__imm_95_6, AMFBS_HasMips64_HasCnMips, { }, },
8182 { 9455 /* syncw */, Mips::SYNC, Convert__imm_95_4, AMFBS_HasMips64_HasCnMips, { }, },
8183 { 9461 /* syncws */, Mips::SYNC, Convert__imm_95_5, AMFBS_HasMips64_HasCnMips, { }, },
8184 { 9468 /* syscall */, Mips::SYSCALL, Convert__imm_95_0, AMFBS_HasStdEnc_NotInMicroMips, { }, },
8185 { 9468 /* syscall */, Mips::SYSCALL_MM, Convert__imm_95_0, AMFBS_InMicroMips, { }, },
8186 { 9468 /* syscall */, Mips::SYSCALL_MM, Convert__ConstantUImm10_01_0, AMFBS_InMicroMips, { MCK_ConstantUImm10_0 }, },
8187 { 9468 /* syscall */, Mips::SYSCALL, Convert__ConstantUImm20_01_0, AMFBS_HasStdEnc_NotInMicroMips, { MCK_ConstantUImm20_0 }, },
8188 { 9476 /* teq */, Mips::TEQ, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, AMFBS_HasStdEnc_HasMips2_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
8189 { 9476 /* teq */, Mips::TEQ_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
8190 { 9476 /* teq */, Mips::TEQ_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
8191 { 9476 /* teq */, Mips::TEQ, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm10_01_2, AMFBS_HasStdEnc_HasMips2_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm10_0 }, },
8192 { 9480 /* teqi */, Mips::TEQI, Convert__GPR32AsmReg1_0__SImm161_1, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm16 }, },
8193 { 9480 /* teqi */, Mips::TEQI_MM, Convert__GPR32AsmReg1_0__SImm161_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, },
8194 { 9485 /* tge */, Mips::TGE, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, AMFBS_HasStdEnc_HasMips2_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
8195 { 9485 /* tge */, Mips::TGE_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
8196 { 9485 /* tge */, Mips::TGE_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
8197 { 9485 /* tge */, Mips::TGE, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm10_01_2, AMFBS_HasStdEnc_HasMips2_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm10_0 }, },
8198 { 9489 /* tgei */, Mips::TGEI, Convert__GPR32AsmReg1_0__SImm161_1, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm16 }, },
8199 { 9489 /* tgei */, Mips::TGEI_MM, Convert__GPR32AsmReg1_0__SImm161_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, },
8200 { 9494 /* tgeiu */, Mips::TGEIU, Convert__GPR32AsmReg1_0__SImm161_1, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm16 }, },
8201 { 9494 /* tgeiu */, Mips::TGEIU_MM, Convert__GPR32AsmReg1_0__SImm161_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, },
8202 { 9500 /* tgeu */, Mips::TGEU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, AMFBS_HasStdEnc_HasMips2_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
8203 { 9500 /* tgeu */, Mips::TGEU_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
8204 { 9500 /* tgeu */, Mips::TGEU_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
8205 { 9500 /* tgeu */, Mips::TGEU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm10_01_2, AMFBS_HasStdEnc_HasMips2_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm10_0 }, },
8206 { 9505 /* tlbginv */, Mips::TLBGINV, Convert_NoOperands, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, { }, },
8207 { 9505 /* tlbginv */, Mips::TLBGINV_MM, Convert_NoOperands, AMFBS_InMicroMips_HasMips32r5_HasVirt, { }, },
8208 { 9513 /* tlbginvf */, Mips::TLBGINVF, Convert_NoOperands, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, { }, },
8209 { 9513 /* tlbginvf */, Mips::TLBGINVF_MM, Convert_NoOperands, AMFBS_InMicroMips_HasMips32r5_HasVirt, { }, },
8210 { 9522 /* tlbgp */, Mips::TLBGP, Convert_NoOperands, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, { }, },
8211 { 9522 /* tlbgp */, Mips::TLBGP_MM, Convert_NoOperands, AMFBS_InMicroMips_HasMips32r5_HasVirt, { }, },
8212 { 9528 /* tlbgr */, Mips::TLBGR, Convert_NoOperands, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, { }, },
8213 { 9528 /* tlbgr */, Mips::TLBGR_MM, Convert_NoOperands, AMFBS_InMicroMips_HasMips32r5_HasVirt, { }, },
8214 { 9534 /* tlbgwi */, Mips::TLBGWI, Convert_NoOperands, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, { }, },
8215 { 9534 /* tlbgwi */, Mips::TLBGWI_MM, Convert_NoOperands, AMFBS_InMicroMips_HasMips32r5_HasVirt, { }, },
8216 { 9541 /* tlbgwr */, Mips::TLBGWR, Convert_NoOperands, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, { }, },
8217 { 9541 /* tlbgwr */, Mips::TLBGWR_MM, Convert_NoOperands, AMFBS_InMicroMips_HasMips32r5_HasVirt, { }, },
8218 { 9548 /* tlbinv */, Mips::TLBINV, Convert_NoOperands, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, { }, },
8219 { 9548 /* tlbinv */, Mips::TLBINV_MMR6, Convert_NoOperands, AMFBS_InMicroMips_HasMips32r6, { }, },
8220 { 9555 /* tlbinvf */, Mips::TLBINVF, Convert_NoOperands, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, { }, },
8221 { 9555 /* tlbinvf */, Mips::TLBINVF_MMR6, Convert_NoOperands, AMFBS_InMicroMips_HasMips32r6, { }, },
8222 { 9563 /* tlbp */, Mips::TLBP, Convert_NoOperands, AMFBS_HasStdEnc_NotInMicroMips, { }, },
8223 { 9563 /* tlbp */, Mips::TLBP_MM, Convert_NoOperands, AMFBS_InMicroMips, { }, },
8224 { 9568 /* tlbr */, Mips::TLBR, Convert_NoOperands, AMFBS_HasStdEnc_NotInMicroMips, { }, },
8225 { 9568 /* tlbr */, Mips::TLBR_MM, Convert_NoOperands, AMFBS_InMicroMips, { }, },
8226 { 9573 /* tlbwi */, Mips::TLBWI, Convert_NoOperands, AMFBS_HasStdEnc_NotInMicroMips, { }, },
8227 { 9573 /* tlbwi */, Mips::TLBWI_MM, Convert_NoOperands, AMFBS_InMicroMips, { }, },
8228 { 9579 /* tlbwr */, Mips::TLBWR, Convert_NoOperands, AMFBS_HasStdEnc_NotInMicroMips, { }, },
8229 { 9579 /* tlbwr */, Mips::TLBWR_MM, Convert_NoOperands, AMFBS_InMicroMips, { }, },
8230 { 9585 /* tlt */, Mips::TLT, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, AMFBS_HasStdEnc_HasMips2_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
8231 { 9585 /* tlt */, Mips::TLT_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
8232 { 9585 /* tlt */, Mips::TLT_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
8233 { 9585 /* tlt */, Mips::TLT, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm10_01_2, AMFBS_HasStdEnc_HasMips2_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm10_0 }, },
8234 { 9589 /* tlti */, Mips::TLTI, Convert__GPR32AsmReg1_0__SImm161_1, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm16 }, },
8235 { 9589 /* tlti */, Mips::TLTI_MM, Convert__GPR32AsmReg1_0__SImm161_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, },
8236 { 9594 /* tltiu */, Mips::TTLTIU, Convert__GPR32AsmReg1_0__SImm161_1, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm16 }, },
8237 { 9594 /* tltiu */, Mips::TLTIU_MM, Convert__GPR32AsmReg1_0__SImm161_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, },
8238 { 9600 /* tltu */, Mips::TLTU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, AMFBS_HasStdEnc_HasMips2_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
8239 { 9600 /* tltu */, Mips::TLTU_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
8240 { 9600 /* tltu */, Mips::TLTU_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
8241 { 9600 /* tltu */, Mips::TLTU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm10_01_2, AMFBS_HasStdEnc_HasMips2_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm10_0 }, },
8242 { 9605 /* tne */, Mips::TNE, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, AMFBS_HasStdEnc_HasMips2_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
8243 { 9605 /* tne */, Mips::TNE_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
8244 { 9605 /* tne */, Mips::TNE_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
8245 { 9605 /* tne */, Mips::TNE, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm10_01_2, AMFBS_HasStdEnc_HasMips2_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm10_0 }, },
8246 { 9609 /* tnei */, Mips::TNEI, Convert__GPR32AsmReg1_0__SImm161_1, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm16 }, },
8247 { 9609 /* tnei */, Mips::TNEI_MM, Convert__GPR32AsmReg1_0__SImm161_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, },
8248 { 9614 /* trunc.l.d */, Mips::TRUNC_L_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips3_32_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
8249 { 9614 /* trunc.l.d */, Mips::TRUNC_L_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
8250 { 9624 /* trunc.l.s */, Mips::TRUNC_L_S, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, },
8251 { 9624 /* trunc.l.s */, Mips::TRUNC_L_S_MMR6, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, },
8252 { 9634 /* trunc.w.d */, Mips::TRUNC_W_D32, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, },
8253 { 9634 /* trunc.w.d */, Mips::TRUNC_W_MM, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, },
8254 { 9634 /* trunc.w.d */, Mips::TRUNC_W_D64, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg }, },
8255 { 9634 /* trunc.w.d */, Mips::TRUNC_W_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg }, },
8256 { 9634 /* trunc.w.d */, Mips::PseudoTRUNC_W_D32, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1__GPR32AsmReg1_2, AMFBS_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg, MCK_GPR32AsmReg }, },
8257 { 9634 /* trunc.w.d */, Mips::PseudoTRUNC_W_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__GPR32AsmReg1_2, AMFBS_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_GPR32AsmReg }, },
8258 { 9644 /* trunc.w.s */, Mips::TRUNC_W_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_HasMips2_NotR5900_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
8259 { 9644 /* trunc.w.s */, Mips::TRUNC_W_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
8260 { 9644 /* trunc.w.s */, Mips::TRUNC_W_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
8261 { 9644 /* trunc.w.s */, Mips::PseudoTRUNC_W_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_None, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_GPR32AsmReg }, },
8262 { 9654 /* ulh */, Mips::Ulh, Convert__GPR32AsmReg1_0__PtrReg1_3__AnyOffset1_1, AMFBS_None, { MCK_GPR32AsmReg, MCK_AnyOffset, MCK__40_, MCK_PtrReg, MCK__41_ }, },
8263 { 9658 /* ulhu */, Mips::Ulhu, Convert__GPR32AsmReg1_0__PtrReg1_3__AnyOffset1_1, AMFBS_None, { MCK_GPR32AsmReg, MCK_AnyOffset, MCK__40_, MCK_PtrReg, MCK__41_ }, },
8264 { 9663 /* ulw */, Mips::Ulw, Convert__GPR32AsmReg1_0__PtrReg1_3__AnyOffset1_1, AMFBS_None, { MCK_GPR32AsmReg, MCK_AnyOffset, MCK__40_, MCK_PtrReg, MCK__41_ }, },
8265 { 9667 /* ush */, Mips::Ush, Convert__GPR32AsmReg1_0__PtrReg1_3__AnyOffset1_1, AMFBS_None, { MCK_GPR32AsmReg, MCK_AnyOffset, MCK__40_, MCK_PtrReg, MCK__41_ }, },
8266 { 9671 /* usw */, Mips::Usw, Convert__GPR32AsmReg1_0__PtrReg1_3__AnyOffset1_1, AMFBS_None, { MCK_GPR32AsmReg, MCK_AnyOffset, MCK__40_, MCK_PtrReg, MCK__41_ }, },
8267 { 9675 /* v3mulu */, Mips::V3MULU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
8268 { 9675 /* v3mulu */, Mips::V3MULU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
8269 { 9682 /* vmm0 */, Mips::VMM0, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
8270 { 9682 /* vmm0 */, Mips::VMM0, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
8271 { 9687 /* vmulu */, Mips::VMULU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
8272 { 9687 /* vmulu */, Mips::VMULU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
8273 { 9693 /* vshf.b */, Mips::VSHF_B, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
8274 { 9700 /* vshf.d */, Mips::VSHF_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
8275 { 9707 /* vshf.h */, Mips::VSHF_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
8276 { 9714 /* vshf.w */, Mips::VSHF_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
8277 { 9721 /* wait */, Mips::WAIT, Convert_NoOperands, AMFBS_HasStdEnc_HasMips3_32_NotInMicroMips, { }, },
8278 { 9721 /* wait */, Mips::WAIT_MM, Convert__imm_95_0, AMFBS_InMicroMips, { }, },
8279 { 9721 /* wait */, Mips::WAIT_MMR6, Convert__ConstantUImm10_01_0, AMFBS_InMicroMips_HasMips32r6, { MCK_ConstantUImm10_0 }, },
8280 { 9721 /* wait */, Mips::WAIT_MM, Convert__ConstantUImm10_01_0, AMFBS_InMicroMips, { MCK_ConstantUImm10_0 }, },
8281 { 9726 /* wrdsp */, Mips::WRDSP, Convert__GPR32AsmReg1_0__imm_95_31, AMFBS_HasDSP_NotInMicroMips, { MCK_GPR32AsmReg }, },
8282 { 9726 /* wrdsp */, Mips::WRDSP_MM, Convert__GPR32AsmReg1_0__imm_95_31, AMFBS_HasDSP_InMicroMips, { MCK_GPR32AsmReg }, },
8283 { 9726 /* wrdsp */, Mips::WRDSP_MM, Convert__GPR32AsmReg1_0__ConstantUImm7_01_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ConstantUImm7_0 }, },
8284 { 9726 /* wrdsp */, Mips::WRDSP, Convert__GPR32AsmReg1_0__ConstantUImm10_01_1, AMFBS_HasDSP_NotInMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm10_0 }, },
8285 { 9732 /* wrpgpr */, Mips::WRPGPR_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
8286 { 9739 /* wsbh */, Mips::WSBH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
8287 { 9739 /* wsbh */, Mips::WSBH_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
8288 { 9739 /* wsbh */, Mips::WSBH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
8289 { 9744 /* xor */, Mips::XorRxRxRy16, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs }, },
8290 { 9744 /* xor */, Mips::XOR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
8291 { 9744 /* xor */, Mips::XOR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
8292 { 9744 /* xor */, Mips::XOR_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
8293 { 9744 /* xor */, Mips::XORI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_UImm16 }, },
8294 { 9744 /* xor */, Mips::XORi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
8295 { 9744 /* xor */, Mips::XORi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
8296 { 9744 /* xor */, Mips::XORi64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, AMFBS_HasStdEnc_IsGP64bit_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_Imm }, },
8297 { 9744 /* xor */, Mips::XOR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
8298 { 9744 /* xor */, Mips::XOR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
8299 { 9744 /* xor */, Mips::XOR_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
8300 { 9744 /* xor */, Mips::XORI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, },
8301 { 9744 /* xor */, Mips::XORi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
8302 { 9744 /* xor */, Mips::XORi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
8303 { 9744 /* xor */, Mips::XORi64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, AMFBS_HasStdEnc_IsGP64bit_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, },
8304 { 9748 /* xor.v */, Mips::XOR_V, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
8305 { 9754 /* xor16 */, Mips::XOR16_MM, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Tie0_1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, },
8306 { 9754 /* xor16 */, Mips::XOR16_MMR6, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Tie0_1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, },
8307 { 9760 /* xori */, Mips::XORI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_UImm16 }, },
8308 { 9760 /* xori */, Mips::XORi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_UImm16 }, },
8309 { 9760 /* xori */, Mips::XORi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_UImm16 }, },
8310 { 9760 /* xori */, Mips::XORI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, },
8311 { 9760 /* xori */, Mips::XORi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, },
8312 { 9760 /* xori */, Mips::XORi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, },
8313 { 9765 /* xori.b */, Mips::XORI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm8_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm8_0 }, },
8314 { 9772 /* yield */, Mips::YIELD, Convert__regR0__GPR32AsmReg1_0, AMFBS_HasMT_NotInMicroMips, { MCK_GPR32AsmReg }, },
8315 { 9772 /* yield */, Mips::YIELD, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMT_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
8316};
8317
8318#include "llvm/Support/Debug.h"
8319#include "llvm/Support/Format.h"
8320
8321unsigned MipsAsmParser::
8322MatchInstructionImpl(const OperandVector &Operands,
8323 MCInst &Inst,
8324 uint64_t &ErrorInfo,
8325 FeatureBitset &MissingFeatures,
8326 bool matchingInlineAsm, unsigned VariantID) {
8327 // Eliminate obvious mismatches.
8328 if (Operands.size() > 9) {
8329 ErrorInfo = 9;
8330 return Match_InvalidOperand;
8331 }
8332
8333 // Get the current feature set.
8334 const FeatureBitset &AvailableFeatures = getAvailableFeatures();
8335
8336 // Get the instruction mnemonic, which is the first token.
8337 StringRef Mnemonic = ((MipsOperand &)*Operands[0]).getToken();
8338
8339 // Some state to try to produce better error messages.
8340 bool HadMatchOtherThanFeatures = false;
8341 bool HadMatchOtherThanPredicate = false;
8342 unsigned RetCode = Match_InvalidOperand;
8343 MissingFeatures.set();
8344 // Set ErrorInfo to the operand that mismatches if it is
8345 // wrong for all instances of the instruction.
8346 ErrorInfo = ~0ULL;
8347 // Find the appropriate table for this asm variant.
8348 const MatchEntry *Start, *End;
8349 switch (VariantID) {
8350 default: llvm_unreachable("invalid variant!");
8351 case 0: Start = std::begin(MatchTable0); End = std::end(MatchTable0); break;
8352 }
8353 // Search the table.
8354 auto MnemonicRange = std::equal_range(Start, End, Mnemonic, LessOpcode());
8355
8356 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "AsmMatcher: found " <<
8357 std::distance(MnemonicRange.first, MnemonicRange.second) <<
8358 " encodings with mnemonic '" << Mnemonic << "'\n");
8359
8360 // Return a more specific error code if no mnemonics match.
8361 if (MnemonicRange.first == MnemonicRange.second)
8362 return Match_MnemonicFail;
8363
8364 for (const MatchEntry *it = MnemonicRange.first, *ie = MnemonicRange.second;
8365 it != ie; ++it) {
8366 const FeatureBitset &RequiredFeatures = FeatureBitsets[it->RequiredFeaturesIdx];
8367 bool HasRequiredFeatures =
8368 (AvailableFeatures & RequiredFeatures) == RequiredFeatures;
8369 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Trying to match opcode "
8370 << MII.getName(it->Opcode) << "\n");
8371 // equal_range guarantees that instruction mnemonic matches.
8372 assert(Mnemonic == it->getMnemonic());
8373 bool OperandsValid = true;
8374 unsigned ActualIdx = 1;
8375 for (unsigned FormalIdx = 0; FormalIdx != 8; ++FormalIdx) {
8376 auto Formal = static_cast<MatchClassKind>(it->Classes[FormalIdx]);
8377 DEBUG_WITH_TYPE("asm-matcher",
8378 dbgs() << " Matching formal operand class " << getMatchClassName(Formal)
8379 << " against actual operand at index " << ActualIdx);
8380 if (ActualIdx < Operands.size())
8381 DEBUG_WITH_TYPE("asm-matcher", dbgs() << " (";
8382 Operands[ActualIdx]->print(dbgs(), getContext().getAsmInfo()); dbgs() << "): ");
8383 else
8384 DEBUG_WITH_TYPE("asm-matcher", dbgs() << ": ");
8385 if (ActualIdx >= Operands.size()) {
8386 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "actual operand index out of range\n");
8387 if (Formal == InvalidMatchClass) {
8388 break;
8389 }
8390 if (isSubclass(Formal, OptionalMatchClass)) {
8391 continue;
8392 }
8393 OperandsValid = false;
8394 ErrorInfo = ActualIdx;
8395 break;
8396 }
8397 MCParsedAsmOperand &Actual = *Operands[ActualIdx];
8398 unsigned Diag = validateOperandClass(Actual, Formal, *STI);
8399 if (Diag == Match_Success) {
8400 DEBUG_WITH_TYPE("asm-matcher",
8401 dbgs() << "match success using generic matcher\n");
8402 ++ActualIdx;
8403 continue;
8404 }
8405 // If the generic handler indicates an invalid operand
8406 // failure, check for a special case.
8407 if (Diag != Match_Success) {
8408 unsigned TargetDiag = validateTargetOperandClass(Actual, Formal);
8409 if (TargetDiag == Match_Success) {
8410 DEBUG_WITH_TYPE("asm-matcher",
8411 dbgs() << "match success using target matcher\n");
8412 ++ActualIdx;
8413 continue;
8414 }
8415 // If the target matcher returned a specific error code use
8416 // that, else use the one from the generic matcher.
8417 if (TargetDiag != Match_InvalidOperand && HasRequiredFeatures)
8418 Diag = TargetDiag;
8419 }
8420 // If current formal operand wasn't matched and it is optional
8421 // then try to match next formal operand
8422 if (Diag == Match_InvalidOperand && isSubclass(Formal, OptionalMatchClass)) {
8423 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "ignoring optional operand\n");
8424 continue;
8425 }
8426 // If this operand is broken for all of the instances of this
8427 // mnemonic, keep track of it so we can report loc info.
8428 // If we already had a match that only failed due to a
8429 // target predicate, that diagnostic is preferred.
8430 if (!HadMatchOtherThanPredicate &&
8431 (it == MnemonicRange.first || ErrorInfo <= ActualIdx)) {
8432 if (HasRequiredFeatures && (ErrorInfo != ActualIdx || Diag != Match_InvalidOperand))
8433 RetCode = Diag;
8434 ErrorInfo = ActualIdx;
8435 }
8436 // Otherwise, just reject this instance of the mnemonic.
8437 OperandsValid = false;
8438 break;
8439 }
8440
8441 if (!OperandsValid) {
8442 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Opcode result: multiple "
8443 "operand mismatches, ignoring "
8444 "this opcode\n");
8445 continue;
8446 }
8447 if (!HasRequiredFeatures) {
8448 HadMatchOtherThanFeatures = true;
8449 FeatureBitset NewMissingFeatures = RequiredFeatures & ~AvailableFeatures;
8450 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Missing target features:";
8451 for (unsigned I = 0, E = NewMissingFeatures.size(); I != E; ++I)
8452 if (NewMissingFeatures[I])
8453 dbgs() << ' ' << I;
8454 dbgs() << "\n");
8455 if (NewMissingFeatures.count() <=
8456 MissingFeatures.count())
8457 MissingFeatures = NewMissingFeatures;
8458 continue;
8459 }
8460
8461 Inst.clear();
8462
8463 Inst.setOpcode(it->Opcode);
8464 // We have a potential match but have not rendered the operands.
8465 // Check the target predicate to handle any context sensitive
8466 // constraints.
8467 // For example, Ties that are referenced multiple times must be
8468 // checked here to ensure the input is the same for each match
8469 // constraints. If we leave it any later the ties will have been
8470 // canonicalized
8471 unsigned MatchResult;
8472 if ((MatchResult = checkEarlyTargetMatchPredicate(Inst, Operands)) != Match_Success) {
8473 Inst.clear();
8474 DEBUG_WITH_TYPE(
8475 "asm-matcher",
8476 dbgs() << "Early target match predicate failed with diag code "
8477 << MatchResult << "\n");
8478 RetCode = MatchResult;
8479 HadMatchOtherThanPredicate = true;
8480 continue;
8481 }
8482
8483 if (matchingInlineAsm) {
8484 convertToMapAndConstraints(it->ConvertFn, Operands);
8485 if (!checkAsmTiedOperandConstraints(*this, it->ConvertFn, Operands,
8486 ErrorInfo))
8487 return Match_InvalidTiedOperand;
8488
8489 return Match_Success;
8490 }
8491
8492 // We have selected a definite instruction, convert the parsed
8493 // operands into the appropriate MCInst.
8494 convertToMCInst(it->ConvertFn, Inst, it->Opcode, Operands);
8495
8496 // We have a potential match. Check the target predicate to
8497 // handle any context sensitive constraints.
8498 if ((MatchResult = checkTargetMatchPredicate(Inst)) != Match_Success) {
8499 DEBUG_WITH_TYPE("asm-matcher",
8500 dbgs() << "Target match predicate failed with diag code "
8501 << MatchResult << "\n");
8502 Inst.clear();
8503 RetCode = MatchResult;
8504 HadMatchOtherThanPredicate = true;
8505 continue;
8506 }
8507
8508 if (!checkAsmTiedOperandConstraints(*this, it->ConvertFn, Operands,
8509 ErrorInfo))
8510 return Match_InvalidTiedOperand;
8511
8512 DEBUG_WITH_TYPE(
8513 "asm-matcher",
8514 dbgs() << "Opcode result: complete match, selecting this opcode\n");
8515 return Match_Success;
8516 }
8517
8518 // Okay, we had no match. Try to return a useful error code.
8519 if (HadMatchOtherThanPredicate || !HadMatchOtherThanFeatures)
8520 return RetCode;
8521
8522 ErrorInfo = 0;
8523 return Match_MissingFeature;
8524}
8525
8526namespace {
8527 struct OperandMatchEntry {
8528 uint16_t Mnemonic;
8529 uint8_t OperandMask;
8530 uint8_t Class;
8531 uint8_t RequiredFeaturesIdx;
8532
8533 StringRef getMnemonic() const {
8534 return StringRef(MnemonicTable + Mnemonic + 1,
8535 MnemonicTable[Mnemonic]);
8536 }
8537 };
8538
8539 // Predicate for searching for an opcode.
8540 struct LessOpcodeOperand {
8541 bool operator()(const OperandMatchEntry &LHS, StringRef RHS) {
8542 return LHS.getMnemonic() < RHS;
8543 }
8544 bool operator()(StringRef LHS, const OperandMatchEntry &RHS) {
8545 return LHS < RHS.getMnemonic();
8546 }
8547 bool operator()(const OperandMatchEntry &LHS, const OperandMatchEntry &RHS) {
8548 return LHS.getMnemonic() < RHS.getMnemonic();
8549 }
8550 };
8551} // end anonymous namespace
8552
8553static const OperandMatchEntry OperandMatchTable[3469] = {
8554 /* Operand List Mnemonic, Mask, Operand Class, Features */
8555 { 0 /* abs */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_None },
8556 { 4 /* abs.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips },
8557 { 4 /* abs.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat },
8558 { 4 /* abs.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips },
8559 { 4 /* abs.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat },
8560 { 10 /* abs.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips },
8561 { 10 /* abs.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat },
8562 { 16 /* absq_s.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
8563 { 16 /* absq_s.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
8564 { 26 /* absq_s.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
8565 { 26 /* absq_s.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
8566 { 36 /* absq_s.w */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
8567 { 36 /* absq_s.w */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
8568 { 45 /* add */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
8569 { 45 /* add */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
8570 { 45 /* add */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8571 { 45 /* add */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips },
8572 { 45 /* add */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
8573 { 45 /* add */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
8574 { 45 /* add */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
8575 { 45 /* add */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8576 { 45 /* add */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips },
8577 { 45 /* add */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
8578 { 49 /* add.d */, 7 /* 0, 1, 2 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips },
8579 { 49 /* add.d */, 7 /* 0, 1, 2 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat },
8580 { 49 /* add.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips },
8581 { 49 /* add.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat },
8582 { 55 /* add.ps */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
8583 { 62 /* add.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips },
8584 { 62 /* add.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
8585 { 62 /* add.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat },
8586 { 68 /* add_a.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8587 { 76 /* add_a.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8588 { 84 /* add_a.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8589 { 92 /* add_a.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8590 { 100 /* addi */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
8591 { 100 /* addi */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips },
8592 { 100 /* addi */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
8593 { 100 /* addi */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips },
8594 { 105 /* addiu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8595 { 105 /* addiu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
8596 { 105 /* addiu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
8597 { 105 /* addiu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8598 { 105 /* addiu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
8599 { 105 /* addiu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
8600 { 111 /* addiupc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6 },
8601 { 111 /* addiupc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8602 { 111 /* addiupc */, 1 /* 0 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_NotMips32r6 },
8603 { 119 /* addiur1sp */, 1 /* 0 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips },
8604 { 129 /* addiur2 */, 3 /* 0, 1 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips },
8605 { 137 /* addius5 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
8606 { 153 /* addq.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
8607 { 153 /* addq.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
8608 { 161 /* addq_s.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
8609 { 161 /* addq_s.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
8610 { 171 /* addq_s.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
8611 { 171 /* addq_s.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
8612 { 180 /* addqh.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
8613 { 180 /* addqh.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
8614 { 189 /* addqh.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
8615 { 189 /* addqh.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
8616 { 197 /* addqh_r.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
8617 { 197 /* addqh_r.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
8618 { 208 /* addqh_r.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
8619 { 208 /* addqh_r.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
8620 { 218 /* addr.ps */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMips3D },
8621 { 226 /* adds_a.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8622 { 235 /* adds_a.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8623 { 244 /* adds_a.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8624 { 253 /* adds_a.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8625 { 262 /* adds_s.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8626 { 271 /* adds_s.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8627 { 280 /* adds_s.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8628 { 289 /* adds_s.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8629 { 298 /* adds_u.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8630 { 307 /* adds_u.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8631 { 316 /* adds_u.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8632 { 325 /* adds_u.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8633 { 334 /* addsc */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
8634 { 334 /* addsc */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
8635 { 340 /* addu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8636 { 340 /* addu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
8637 { 340 /* addu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
8638 { 340 /* addu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
8639 { 340 /* addu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
8640 { 340 /* addu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8641 { 340 /* addu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
8642 { 340 /* addu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
8643 { 340 /* addu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
8644 { 340 /* addu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
8645 { 345 /* addu.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
8646 { 345 /* addu.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
8647 { 353 /* addu.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
8648 { 353 /* addu.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
8649 { 361 /* addu16 */, 7 /* 0, 1, 2 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_NotMips32r6 },
8650 { 361 /* addu16 */, 7 /* 0, 1, 2 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8651 { 368 /* addu_s.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
8652 { 368 /* addu_s.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
8653 { 378 /* addu_s.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
8654 { 378 /* addu_s.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
8655 { 388 /* adduh.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
8656 { 388 /* adduh.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
8657 { 397 /* adduh_r.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
8658 { 397 /* adduh_r.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
8659 { 408 /* addv.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8660 { 415 /* addv.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8661 { 422 /* addv.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8662 { 429 /* addv.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8663 { 436 /* addvi.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8664 { 444 /* addvi.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8665 { 452 /* addvi.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8666 { 460 /* addvi.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8667 { 468 /* addwc */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
8668 { 468 /* addwc */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
8669 { 474 /* align */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6 },
8670 { 474 /* align */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8671 { 480 /* aluipc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6 },
8672 { 480 /* aluipc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8673 { 487 /* and */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
8674 { 487 /* and */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
8675 { 487 /* and */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8676 { 487 /* and */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8677 { 487 /* and */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips },
8678 { 487 /* and */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
8679 { 487 /* and */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips3_NotInMicroMips },
8680 { 487 /* and */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
8681 { 487 /* and */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
8682 { 487 /* and */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8683 { 487 /* and */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8684 { 487 /* and */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips },
8685 { 487 /* and */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
8686 { 487 /* and */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips3_NotInMicroMips },
8687 { 491 /* and.v */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8688 { 497 /* and16 */, 3 /* 0, 1 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_NotMips32r6 },
8689 { 497 /* and16 */, 3 /* 0, 1 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8690 { 503 /* andi */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8691 { 503 /* andi */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
8692 { 503 /* andi */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
8693 { 503 /* andi */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8694 { 503 /* andi */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
8695 { 503 /* andi */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
8696 { 508 /* andi.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8697 { 515 /* andi16 */, 3 /* 0, 1 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_NotMips32r6 },
8698 { 515 /* andi16 */, 3 /* 0, 1 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8699 { 522 /* append */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
8700 { 522 /* append */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
8701 { 529 /* asub_s.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8702 { 538 /* asub_s.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8703 { 547 /* asub_s.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8704 { 556 /* asub_s.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8705 { 565 /* asub_u.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8706 { 574 /* asub_u.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8707 { 583 /* asub_u.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8708 { 592 /* asub_u.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8709 { 601 /* aui */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6 },
8710 { 601 /* aui */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8711 { 605 /* auipc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6 },
8712 { 605 /* auipc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8713 { 611 /* ave_s.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8714 { 619 /* ave_s.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8715 { 627 /* ave_s.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8716 { 635 /* ave_s.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8717 { 643 /* ave_u.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8718 { 651 /* ave_u.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8719 { 659 /* ave_u.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8720 { 667 /* ave_u.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8721 { 675 /* aver_s.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8722 { 684 /* aver_s.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8723 { 693 /* aver_s.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8724 { 702 /* aver_s.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8725 { 711 /* aver_u.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8726 { 720 /* aver_u.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8727 { 729 /* aver_u.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8728 { 738 /* aver_u.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8729 { 747 /* b */, 1 /* 0 */, MCK_JumpTarget, AMFBS_HasStdEnc_NotInMicroMips },
8730 { 747 /* b */, 1 /* 0 */, MCK_JumpTarget, AMFBS_InMicroMips },
8731 { 747 /* b */, 1 /* 0 */, MCK_JumpTarget, AMFBS_InMips16Mode },
8732 { 747 /* b */, 1 /* 0 */, MCK_JumpTarget, AMFBS_None },
8733 { 747 /* b */, 1 /* 0 */, MCK_JumpTarget, AMFBS_InMips16Mode },
8734 { 749 /* b16 */, 1 /* 0 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 },
8735 { 749 /* b16 */, 1 /* 0 */, MCK_JumpTarget, AMFBS_InMicroMips },
8736 { 753 /* baddu */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasCnMips },
8737 { 753 /* baddu */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasCnMips },
8738 { 759 /* bal */, 1 /* 0 */, MCK_JumpTarget, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips },
8739 { 759 /* bal */, 1 /* 0 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6 },
8740 { 759 /* bal */, 1 /* 0 */, MCK_JumpTarget, AMFBS_InMicroMips_NotMips32r6 },
8741 { 763 /* balc */, 1 /* 0 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6 },
8742 { 763 /* balc */, 1 /* 0 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 },
8743 { 768 /* balign */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
8744 { 768 /* balign */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
8745 { 775 /* bbit0 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasCnMips },
8746 { 775 /* bbit0 */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasCnMips },
8747 { 775 /* bbit0 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasCnMips },
8748 { 775 /* bbit0 */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasCnMips },
8749 { 781 /* bbit032 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasCnMips },
8750 { 781 /* bbit032 */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasCnMips },
8751 { 789 /* bbit1 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasCnMips },
8752 { 789 /* bbit1 */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasCnMips },
8753 { 789 /* bbit1 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasCnMips },
8754 { 789 /* bbit1 */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasCnMips },
8755 { 795 /* bbit132 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasCnMips },
8756 { 795 /* bbit132 */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasCnMips },
8757 { 803 /* bc */, 1 /* 0 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8758 { 803 /* bc */, 1 /* 0 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 },
8759 { 806 /* bc16 */, 1 /* 0 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 },
8760 { 811 /* bc1eqz */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
8761 { 811 /* bc1eqz */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
8762 { 818 /* bc1eqzc */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
8763 { 818 /* bc1eqzc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
8764 { 826 /* bc1f */, 1 /* 0 */, MCK_JumpTarget, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
8765 { 826 /* bc1f */, 1 /* 0 */, MCK_JumpTarget, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
8766 { 826 /* bc1f */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
8767 { 826 /* bc1f */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
8768 { 826 /* bc1f */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
8769 { 826 /* bc1f */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
8770 { 831 /* bc1fl */, 1 /* 0 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
8771 { 831 /* bc1fl */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
8772 { 831 /* bc1fl */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
8773 { 837 /* bc1nez */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
8774 { 837 /* bc1nez */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
8775 { 844 /* bc1nezc */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
8776 { 844 /* bc1nezc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
8777 { 852 /* bc1t */, 1 /* 0 */, MCK_JumpTarget, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
8778 { 852 /* bc1t */, 1 /* 0 */, MCK_JumpTarget, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
8779 { 852 /* bc1t */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
8780 { 852 /* bc1t */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
8781 { 852 /* bc1t */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
8782 { 852 /* bc1t */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
8783 { 857 /* bc1tl */, 1 /* 0 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
8784 { 857 /* bc1tl */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
8785 { 857 /* bc1tl */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
8786 { 863 /* bc2eqz */, 1 /* 0 */, MCK_COP2AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8787 { 863 /* bc2eqz */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8788 { 870 /* bc2eqzc */, 1 /* 0 */, MCK_COP2AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8789 { 870 /* bc2eqzc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 },
8790 { 878 /* bc2nez */, 1 /* 0 */, MCK_COP2AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8791 { 878 /* bc2nez */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8792 { 885 /* bc2nezc */, 1 /* 0 */, MCK_COP2AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8793 { 885 /* bc2nezc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 },
8794 { 893 /* bclr.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8795 { 900 /* bclr.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8796 { 907 /* bclr.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8797 { 914 /* bclr.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8798 { 921 /* bclri.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8799 { 929 /* bclri.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8800 { 937 /* bclri.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8801 { 945 /* bclri.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8802 { 953 /* beq */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None },
8803 { 953 /* beq */, 4 /* 2 */, MCK_JumpTarget, AMFBS_None },
8804 { 953 /* beq */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
8805 { 953 /* beq */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_NotInMicroMips },
8806 { 953 /* beq */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
8807 { 953 /* beq */, 4 /* 2 */, MCK_JumpTarget, AMFBS_InMicroMips_NotMips32r6 },
8808 { 957 /* beqc */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8809 { 957 /* beqc */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8810 { 957 /* beqc */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8811 { 957 /* beqc */, 4 /* 2 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 },
8812 { 957 /* beqc */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 },
8813 { 957 /* beqc */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 },
8814 { 962 /* beql */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 },
8815 { 962 /* beql */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 },
8816 { 962 /* beql */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips },
8817 { 962 /* beql */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips },
8818 { 967 /* beqz */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMips16Mode },
8819 { 967 /* beqz */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
8820 { 967 /* beqz */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_NotInMicroMips },
8821 { 967 /* beqz */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
8822 { 967 /* beqz */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips },
8823 { 967 /* beqz */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMips16Mode },
8824 { 972 /* beqz16 */, 1 /* 0 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_NotMips32r6 },
8825 { 972 /* beqz16 */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_NotMips32r6 },
8826 { 972 /* beqz16 */, 1 /* 0 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8827 { 972 /* beqz16 */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 },
8828 { 979 /* beqzalc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8829 { 979 /* beqzalc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8830 { 979 /* beqzalc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8831 { 979 /* beqzalc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 },
8832 { 987 /* beqzc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8833 { 987 /* beqzc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8834 { 987 /* beqzc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
8835 { 987 /* beqzc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_NotMips32r6 },
8836 { 987 /* beqzc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8837 { 987 /* beqzc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 },
8838 { 987 /* beqzc */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 },
8839 { 987 /* beqzc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 },
8840 { 993 /* beqzc16 */, 1 /* 0 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8841 { 993 /* beqzc16 */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 },
8842 { 1001 /* beqzl */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotInMicroMips },
8843 { 1001 /* beqzl */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotInMicroMips },
8844 { 1007 /* bge */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None },
8845 { 1007 /* bge */, 4 /* 2 */, MCK_JumpTarget, AMFBS_None },
8846 { 1007 /* bge */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_None },
8847 { 1007 /* bge */, 4 /* 2 */, MCK_JumpTarget, AMFBS_None },
8848 { 1011 /* bgec */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8849 { 1011 /* bgec */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8850 { 1011 /* bgec */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8851 { 1011 /* bgec */, 4 /* 2 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 },
8852 { 1011 /* bgec */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 },
8853 { 1011 /* bgec */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 },
8854 { 1016 /* bgel */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 },
8855 { 1016 /* bgel */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 },
8856 { 1016 /* bgel */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 },
8857 { 1016 /* bgel */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 },
8858 { 1021 /* bgeu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None },
8859 { 1021 /* bgeu */, 4 /* 2 */, MCK_JumpTarget, AMFBS_None },
8860 { 1021 /* bgeu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_None },
8861 { 1021 /* bgeu */, 4 /* 2 */, MCK_JumpTarget, AMFBS_None },
8862 { 1026 /* bgeuc */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8863 { 1026 /* bgeuc */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8864 { 1026 /* bgeuc */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8865 { 1026 /* bgeuc */, 4 /* 2 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 },
8866 { 1026 /* bgeuc */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 },
8867 { 1026 /* bgeuc */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 },
8868 { 1032 /* bgeul */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 },
8869 { 1032 /* bgeul */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 },
8870 { 1032 /* bgeul */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 },
8871 { 1032 /* bgeul */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 },
8872 { 1038 /* bgez */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
8873 { 1038 /* bgez */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_NotInMicroMips },
8874 { 1038 /* bgez */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
8875 { 1038 /* bgez */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_NotMips32r6 },
8876 { 1043 /* bgezal */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips },
8877 { 1043 /* bgezal */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips },
8878 { 1043 /* bgezal */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
8879 { 1043 /* bgezal */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_NotMips32r6 },
8880 { 1050 /* bgezalc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8881 { 1050 /* bgezalc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8882 { 1050 /* bgezalc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8883 { 1050 /* bgezalc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 },
8884 { 1058 /* bgezall */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips },
8885 { 1058 /* bgezall */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips },
8886 { 1066 /* bgezals */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
8887 { 1066 /* bgezals */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_NotMips32r6 },
8888 { 1074 /* bgezc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8889 { 1074 /* bgezc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8890 { 1074 /* bgezc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8891 { 1074 /* bgezc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 },
8892 { 1074 /* bgezc */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 },
8893 { 1074 /* bgezc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 },
8894 { 1080 /* bgezl */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips },
8895 { 1080 /* bgezl */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips },
8896 { 1086 /* bgt */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None },
8897 { 1086 /* bgt */, 4 /* 2 */, MCK_JumpTarget, AMFBS_None },
8898 { 1086 /* bgt */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_None },
8899 { 1086 /* bgt */, 4 /* 2 */, MCK_JumpTarget, AMFBS_None },
8900 { 1090 /* bgtl */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 },
8901 { 1090 /* bgtl */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 },
8902 { 1090 /* bgtl */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 },
8903 { 1090 /* bgtl */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 },
8904 { 1095 /* bgtu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None },
8905 { 1095 /* bgtu */, 4 /* 2 */, MCK_JumpTarget, AMFBS_None },
8906 { 1095 /* bgtu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_None },
8907 { 1095 /* bgtu */, 4 /* 2 */, MCK_JumpTarget, AMFBS_None },
8908 { 1100 /* bgtul */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 },
8909 { 1100 /* bgtul */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 },
8910 { 1100 /* bgtul */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 },
8911 { 1100 /* bgtul */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 },
8912 { 1106 /* bgtz */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
8913 { 1106 /* bgtz */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_NotInMicroMips },
8914 { 1106 /* bgtz */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
8915 { 1106 /* bgtz */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_NotMips32r6 },
8916 { 1111 /* bgtzalc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8917 { 1111 /* bgtzalc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8918 { 1111 /* bgtzalc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8919 { 1111 /* bgtzalc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 },
8920 { 1119 /* bgtzc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8921 { 1119 /* bgtzc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8922 { 1119 /* bgtzc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8923 { 1119 /* bgtzc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 },
8924 { 1119 /* bgtzc */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 },
8925 { 1119 /* bgtzc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 },
8926 { 1125 /* bgtzl */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips },
8927 { 1125 /* bgtzl */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips },
8928 { 1131 /* binsl.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8929 { 1139 /* binsl.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8930 { 1147 /* binsl.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8931 { 1155 /* binsl.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8932 { 1163 /* binsli.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8933 { 1172 /* binsli.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8934 { 1181 /* binsli.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8935 { 1190 /* binsli.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8936 { 1199 /* binsr.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8937 { 1207 /* binsr.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8938 { 1215 /* binsr.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8939 { 1223 /* binsr.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8940 { 1231 /* binsri.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8941 { 1240 /* binsri.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8942 { 1249 /* binsri.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8943 { 1258 /* binsri.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8944 { 1267 /* bitrev */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
8945 { 1267 /* bitrev */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
8946 { 1274 /* bitswap */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6 },
8947 { 1274 /* bitswap */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8948 { 1282 /* ble */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None },
8949 { 1282 /* ble */, 4 /* 2 */, MCK_JumpTarget, AMFBS_None },
8950 { 1282 /* ble */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_None },
8951 { 1282 /* ble */, 4 /* 2 */, MCK_JumpTarget, AMFBS_None },
8952 { 1286 /* blel */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 },
8953 { 1286 /* blel */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 },
8954 { 1286 /* blel */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 },
8955 { 1286 /* blel */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 },
8956 { 1291 /* bleu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None },
8957 { 1291 /* bleu */, 4 /* 2 */, MCK_JumpTarget, AMFBS_None },
8958 { 1291 /* bleu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_None },
8959 { 1291 /* bleu */, 4 /* 2 */, MCK_JumpTarget, AMFBS_None },
8960 { 1296 /* bleul */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 },
8961 { 1296 /* bleul */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 },
8962 { 1296 /* bleul */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 },
8963 { 1296 /* bleul */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 },
8964 { 1302 /* blez */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
8965 { 1302 /* blez */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_NotInMicroMips },
8966 { 1302 /* blez */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
8967 { 1302 /* blez */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_NotMips32r6 },
8968 { 1307 /* blezalc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8969 { 1307 /* blezalc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8970 { 1307 /* blezalc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8971 { 1307 /* blezalc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 },
8972 { 1315 /* blezc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8973 { 1315 /* blezc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8974 { 1315 /* blezc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8975 { 1315 /* blezc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 },
8976 { 1315 /* blezc */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 },
8977 { 1315 /* blezc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 },
8978 { 1321 /* blezl */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips },
8979 { 1321 /* blezl */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips },
8980 { 1327 /* blt */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None },
8981 { 1327 /* blt */, 4 /* 2 */, MCK_JumpTarget, AMFBS_None },
8982 { 1327 /* blt */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_None },
8983 { 1327 /* blt */, 4 /* 2 */, MCK_JumpTarget, AMFBS_None },
8984 { 1331 /* bltc */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8985 { 1331 /* bltc */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8986 { 1331 /* bltc */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8987 { 1331 /* bltc */, 4 /* 2 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 },
8988 { 1331 /* bltc */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 },
8989 { 1331 /* bltc */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 },
8990 { 1336 /* bltl */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 },
8991 { 1336 /* bltl */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 },
8992 { 1336 /* bltl */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 },
8993 { 1336 /* bltl */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 },
8994 { 1341 /* bltu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None },
8995 { 1341 /* bltu */, 4 /* 2 */, MCK_JumpTarget, AMFBS_None },
8996 { 1341 /* bltu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_None },
8997 { 1341 /* bltu */, 4 /* 2 */, MCK_JumpTarget, AMFBS_None },
8998 { 1346 /* bltuc */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8999 { 1346 /* bltuc */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
9000 { 1346 /* bltuc */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
9001 { 1346 /* bltuc */, 4 /* 2 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 },
9002 { 1346 /* bltuc */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 },
9003 { 1346 /* bltuc */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 },
9004 { 1352 /* bltul */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 },
9005 { 1352 /* bltul */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 },
9006 { 1352 /* bltul */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 },
9007 { 1352 /* bltul */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 },
9008 { 1358 /* bltz */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
9009 { 1358 /* bltz */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_NotInMicroMips },
9010 { 1358 /* bltz */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
9011 { 1358 /* bltz */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_NotMips32r6 },
9012 { 1363 /* bltzal */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips },
9013 { 1363 /* bltzal */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips },
9014 { 1363 /* bltzal */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
9015 { 1363 /* bltzal */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_NotMips32r6 },
9016 { 1370 /* bltzalc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
9017 { 1370 /* bltzalc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
9018 { 1370 /* bltzalc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
9019 { 1370 /* bltzalc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 },
9020 { 1378 /* bltzall */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips },
9021 { 1378 /* bltzall */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips },
9022 { 1386 /* bltzals */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
9023 { 1386 /* bltzals */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_NotMips32r6 },
9024 { 1394 /* bltzc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
9025 { 1394 /* bltzc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
9026 { 1394 /* bltzc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
9027 { 1394 /* bltzc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 },
9028 { 1394 /* bltzc */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 },
9029 { 1394 /* bltzc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 },
9030 { 1400 /* bltzl */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips },
9031 { 1400 /* bltzl */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips },
9032 { 1406 /* bmnz.v */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9033 { 1413 /* bmnzi.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9034 { 1421 /* bmz.v */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9035 { 1427 /* bmzi.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9036 { 1434 /* bne */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None },
9037 { 1434 /* bne */, 4 /* 2 */, MCK_JumpTarget, AMFBS_None },
9038 { 1434 /* bne */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
9039 { 1434 /* bne */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_NotInMicroMips },
9040 { 1434 /* bne */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
9041 { 1434 /* bne */, 4 /* 2 */, MCK_JumpTarget, AMFBS_InMicroMips_NotMips32r6 },
9042 { 1438 /* bnec */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
9043 { 1438 /* bnec */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
9044 { 1438 /* bnec */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
9045 { 1438 /* bnec */, 4 /* 2 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 },
9046 { 1438 /* bnec */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 },
9047 { 1438 /* bnec */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 },
9048 { 1443 /* bneg.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9049 { 1450 /* bneg.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9050 { 1457 /* bneg.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9051 { 1464 /* bneg.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9052 { 1471 /* bnegi.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9053 { 1479 /* bnegi.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9054 { 1487 /* bnegi.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9055 { 1495 /* bnegi.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9056 { 1503 /* bnel */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 },
9057 { 1503 /* bnel */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 },
9058 { 1503 /* bnel */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips },
9059 { 1503 /* bnel */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips },
9060 { 1508 /* bnez */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMips16Mode },
9061 { 1508 /* bnez */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
9062 { 1508 /* bnez */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_NotInMicroMips },
9063 { 1508 /* bnez */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
9064 { 1508 /* bnez */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips },
9065 { 1508 /* bnez */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMips16Mode },
9066 { 1513 /* bnez16 */, 1 /* 0 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_NotMips32r6 },
9067 { 1513 /* bnez16 */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_NotMips32r6 },
9068 { 1513 /* bnez16 */, 1 /* 0 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_HasMips32r6 },
9069 { 1513 /* bnez16 */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 },
9070 { 1520 /* bnezalc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
9071 { 1520 /* bnezalc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
9072 { 1520 /* bnezalc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
9073 { 1520 /* bnezalc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 },
9074 { 1528 /* bnezc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
9075 { 1528 /* bnezc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
9076 { 1528 /* bnezc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
9077 { 1528 /* bnezc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_NotMips32r6 },
9078 { 1528 /* bnezc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
9079 { 1528 /* bnezc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 },
9080 { 1528 /* bnezc */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 },
9081 { 1528 /* bnezc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 },
9082 { 1534 /* bnezc16 */, 1 /* 0 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_HasMips32r6 },
9083 { 1534 /* bnezc16 */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 },
9084 { 1542 /* bnezl */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotInMicroMips },
9085 { 1542 /* bnezl */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotInMicroMips },
9086 { 1548 /* bnvc */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
9087 { 1548 /* bnvc */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
9088 { 1548 /* bnvc */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
9089 { 1548 /* bnvc */, 4 /* 2 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 },
9090 { 1553 /* bnz.b */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9091 { 1553 /* bnz.b */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMSA },
9092 { 1559 /* bnz.d */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9093 { 1559 /* bnz.d */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMSA },
9094 { 1565 /* bnz.h */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9095 { 1565 /* bnz.h */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMSA },
9096 { 1571 /* bnz.v */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9097 { 1571 /* bnz.v */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMSA },
9098 { 1577 /* bnz.w */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9099 { 1577 /* bnz.w */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMSA },
9100 { 1583 /* bovc */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
9101 { 1583 /* bovc */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
9102 { 1583 /* bovc */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
9103 { 1583 /* bovc */, 4 /* 2 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 },
9104 { 1588 /* bposge32 */, 1 /* 0 */, MCK_JumpTarget, AMFBS_InMicroMips_NotMips32r6_HasDSP },
9105 { 1588 /* bposge32 */, 1 /* 0 */, MCK_JumpTarget, AMFBS_HasDSP_NotInMicroMips },
9106 { 1597 /* bposge32c */, 1 /* 0 */, MCK_JumpTarget, AMFBS_InMicroMips_HasDSPR3 },
9107 { 1621 /* bsel.v */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9108 { 1628 /* bseli.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9109 { 1636 /* bset.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9110 { 1643 /* bset.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9111 { 1650 /* bset.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9112 { 1657 /* bset.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9113 { 1664 /* bseti.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9114 { 1672 /* bseti.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9115 { 1680 /* bseti.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9116 { 1688 /* bseti.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9117 { 1708 /* bz.b */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9118 { 1708 /* bz.b */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMSA },
9119 { 1713 /* bz.d */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9120 { 1713 /* bz.d */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMSA },
9121 { 1718 /* bz.h */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9122 { 1718 /* bz.h */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMSA },
9123 { 1723 /* bz.v */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9124 { 1723 /* bz.v */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMSA },
9125 { 1728 /* bz.w */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9126 { 1728 /* bz.w */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMSA },
9127 { 1733 /* c.eq.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9128 { 1733 /* c.eq.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9129 { 1733 /* c.eq.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9130 { 1733 /* c.eq.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9131 { 1733 /* c.eq.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9132 { 1733 /* c.eq.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9133 { 1733 /* c.eq.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9134 { 1733 /* c.eq.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9135 { 1733 /* c.eq.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9136 { 1733 /* c.eq.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9137 { 1733 /* c.eq.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9138 { 1733 /* c.eq.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9139 { 1740 /* c.eq.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9140 { 1740 /* c.eq.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9141 { 1740 /* c.eq.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9142 { 1740 /* c.eq.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9143 { 1740 /* c.eq.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9144 { 1740 /* c.eq.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9145 { 1747 /* c.f.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9146 { 1747 /* c.f.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9147 { 1747 /* c.f.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9148 { 1747 /* c.f.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9149 { 1747 /* c.f.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9150 { 1747 /* c.f.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9151 { 1747 /* c.f.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9152 { 1747 /* c.f.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9153 { 1747 /* c.f.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9154 { 1747 /* c.f.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9155 { 1747 /* c.f.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9156 { 1747 /* c.f.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9157 { 1753 /* c.f.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9158 { 1753 /* c.f.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9159 { 1753 /* c.f.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9160 { 1753 /* c.f.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9161 { 1753 /* c.f.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9162 { 1753 /* c.f.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9163 { 1759 /* c.le.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9164 { 1759 /* c.le.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9165 { 1759 /* c.le.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9166 { 1759 /* c.le.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9167 { 1759 /* c.le.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9168 { 1759 /* c.le.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9169 { 1759 /* c.le.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9170 { 1759 /* c.le.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9171 { 1759 /* c.le.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9172 { 1759 /* c.le.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9173 { 1759 /* c.le.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9174 { 1759 /* c.le.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9175 { 1766 /* c.le.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips },
9176 { 1766 /* c.le.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9177 { 1766 /* c.le.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips },
9178 { 1766 /* c.le.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips },
9179 { 1766 /* c.le.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9180 { 1766 /* c.le.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9181 { 1773 /* c.lt.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9182 { 1773 /* c.lt.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9183 { 1773 /* c.lt.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9184 { 1773 /* c.lt.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9185 { 1773 /* c.lt.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9186 { 1773 /* c.lt.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9187 { 1773 /* c.lt.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9188 { 1773 /* c.lt.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9189 { 1773 /* c.lt.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9190 { 1773 /* c.lt.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9191 { 1773 /* c.lt.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9192 { 1773 /* c.lt.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9193 { 1780 /* c.lt.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips },
9194 { 1780 /* c.lt.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9195 { 1780 /* c.lt.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips },
9196 { 1780 /* c.lt.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips },
9197 { 1780 /* c.lt.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9198 { 1780 /* c.lt.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9199 { 1787 /* c.nge.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9200 { 1787 /* c.nge.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9201 { 1787 /* c.nge.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9202 { 1787 /* c.nge.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9203 { 1787 /* c.nge.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9204 { 1787 /* c.nge.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9205 { 1787 /* c.nge.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9206 { 1787 /* c.nge.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9207 { 1787 /* c.nge.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9208 { 1787 /* c.nge.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9209 { 1787 /* c.nge.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9210 { 1787 /* c.nge.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9211 { 1795 /* c.nge.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips },
9212 { 1795 /* c.nge.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9213 { 1795 /* c.nge.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips },
9214 { 1795 /* c.nge.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips },
9215 { 1795 /* c.nge.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9216 { 1795 /* c.nge.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9217 { 1803 /* c.ngl.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9218 { 1803 /* c.ngl.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9219 { 1803 /* c.ngl.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9220 { 1803 /* c.ngl.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9221 { 1803 /* c.ngl.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9222 { 1803 /* c.ngl.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9223 { 1803 /* c.ngl.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9224 { 1803 /* c.ngl.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9225 { 1803 /* c.ngl.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9226 { 1803 /* c.ngl.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9227 { 1803 /* c.ngl.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9228 { 1803 /* c.ngl.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9229 { 1811 /* c.ngl.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips },
9230 { 1811 /* c.ngl.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9231 { 1811 /* c.ngl.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips },
9232 { 1811 /* c.ngl.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips },
9233 { 1811 /* c.ngl.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9234 { 1811 /* c.ngl.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9235 { 1819 /* c.ngle.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9236 { 1819 /* c.ngle.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9237 { 1819 /* c.ngle.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9238 { 1819 /* c.ngle.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9239 { 1819 /* c.ngle.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9240 { 1819 /* c.ngle.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9241 { 1819 /* c.ngle.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9242 { 1819 /* c.ngle.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9243 { 1819 /* c.ngle.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9244 { 1819 /* c.ngle.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9245 { 1819 /* c.ngle.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9246 { 1819 /* c.ngle.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9247 { 1828 /* c.ngle.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips },
9248 { 1828 /* c.ngle.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9249 { 1828 /* c.ngle.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips },
9250 { 1828 /* c.ngle.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips },
9251 { 1828 /* c.ngle.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9252 { 1828 /* c.ngle.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9253 { 1837 /* c.ngt.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9254 { 1837 /* c.ngt.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9255 { 1837 /* c.ngt.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9256 { 1837 /* c.ngt.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9257 { 1837 /* c.ngt.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9258 { 1837 /* c.ngt.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9259 { 1837 /* c.ngt.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9260 { 1837 /* c.ngt.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9261 { 1837 /* c.ngt.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9262 { 1837 /* c.ngt.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9263 { 1837 /* c.ngt.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9264 { 1837 /* c.ngt.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9265 { 1845 /* c.ngt.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips },
9266 { 1845 /* c.ngt.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9267 { 1845 /* c.ngt.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips },
9268 { 1845 /* c.ngt.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips },
9269 { 1845 /* c.ngt.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9270 { 1845 /* c.ngt.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9271 { 1853 /* c.ole.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9272 { 1853 /* c.ole.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9273 { 1853 /* c.ole.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9274 { 1853 /* c.ole.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9275 { 1853 /* c.ole.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9276 { 1853 /* c.ole.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9277 { 1853 /* c.ole.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9278 { 1853 /* c.ole.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9279 { 1853 /* c.ole.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9280 { 1853 /* c.ole.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9281 { 1853 /* c.ole.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9282 { 1853 /* c.ole.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9283 { 1861 /* c.ole.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9284 { 1861 /* c.ole.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9285 { 1861 /* c.ole.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9286 { 1861 /* c.ole.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9287 { 1861 /* c.ole.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9288 { 1861 /* c.ole.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9289 { 1869 /* c.olt.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9290 { 1869 /* c.olt.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9291 { 1869 /* c.olt.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9292 { 1869 /* c.olt.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9293 { 1869 /* c.olt.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9294 { 1869 /* c.olt.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9295 { 1869 /* c.olt.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9296 { 1869 /* c.olt.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9297 { 1869 /* c.olt.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9298 { 1869 /* c.olt.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9299 { 1869 /* c.olt.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9300 { 1869 /* c.olt.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9301 { 1877 /* c.olt.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9302 { 1877 /* c.olt.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9303 { 1877 /* c.olt.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9304 { 1877 /* c.olt.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9305 { 1877 /* c.olt.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9306 { 1877 /* c.olt.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9307 { 1885 /* c.seq.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9308 { 1885 /* c.seq.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9309 { 1885 /* c.seq.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9310 { 1885 /* c.seq.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9311 { 1885 /* c.seq.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9312 { 1885 /* c.seq.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9313 { 1885 /* c.seq.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9314 { 1885 /* c.seq.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9315 { 1885 /* c.seq.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9316 { 1885 /* c.seq.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9317 { 1885 /* c.seq.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9318 { 1885 /* c.seq.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9319 { 1893 /* c.seq.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips },
9320 { 1893 /* c.seq.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9321 { 1893 /* c.seq.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips },
9322 { 1893 /* c.seq.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips },
9323 { 1893 /* c.seq.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9324 { 1893 /* c.seq.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9325 { 1901 /* c.sf.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9326 { 1901 /* c.sf.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9327 { 1901 /* c.sf.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9328 { 1901 /* c.sf.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9329 { 1901 /* c.sf.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9330 { 1901 /* c.sf.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9331 { 1901 /* c.sf.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9332 { 1901 /* c.sf.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9333 { 1901 /* c.sf.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9334 { 1901 /* c.sf.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9335 { 1901 /* c.sf.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9336 { 1901 /* c.sf.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9337 { 1908 /* c.sf.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips },
9338 { 1908 /* c.sf.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9339 { 1908 /* c.sf.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips },
9340 { 1908 /* c.sf.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips },
9341 { 1908 /* c.sf.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9342 { 1908 /* c.sf.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9343 { 1915 /* c.ueq.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9344 { 1915 /* c.ueq.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9345 { 1915 /* c.ueq.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9346 { 1915 /* c.ueq.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9347 { 1915 /* c.ueq.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9348 { 1915 /* c.ueq.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9349 { 1915 /* c.ueq.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9350 { 1915 /* c.ueq.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9351 { 1915 /* c.ueq.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9352 { 1915 /* c.ueq.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9353 { 1915 /* c.ueq.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9354 { 1915 /* c.ueq.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9355 { 1923 /* c.ueq.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips },
9356 { 1923 /* c.ueq.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9357 { 1923 /* c.ueq.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips },
9358 { 1923 /* c.ueq.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips },
9359 { 1923 /* c.ueq.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9360 { 1923 /* c.ueq.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9361 { 1931 /* c.ule.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9362 { 1931 /* c.ule.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9363 { 1931 /* c.ule.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9364 { 1931 /* c.ule.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9365 { 1931 /* c.ule.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9366 { 1931 /* c.ule.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9367 { 1931 /* c.ule.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9368 { 1931 /* c.ule.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9369 { 1931 /* c.ule.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9370 { 1931 /* c.ule.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9371 { 1931 /* c.ule.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9372 { 1931 /* c.ule.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9373 { 1939 /* c.ule.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips },
9374 { 1939 /* c.ule.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9375 { 1939 /* c.ule.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips },
9376 { 1939 /* c.ule.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips },
9377 { 1939 /* c.ule.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9378 { 1939 /* c.ule.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9379 { 1947 /* c.ult.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9380 { 1947 /* c.ult.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9381 { 1947 /* c.ult.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9382 { 1947 /* c.ult.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9383 { 1947 /* c.ult.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9384 { 1947 /* c.ult.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9385 { 1947 /* c.ult.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9386 { 1947 /* c.ult.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9387 { 1947 /* c.ult.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9388 { 1947 /* c.ult.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9389 { 1947 /* c.ult.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9390 { 1947 /* c.ult.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9391 { 1955 /* c.ult.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips },
9392 { 1955 /* c.ult.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9393 { 1955 /* c.ult.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips },
9394 { 1955 /* c.ult.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips },
9395 { 1955 /* c.ult.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9396 { 1955 /* c.ult.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9397 { 1963 /* c.un.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9398 { 1963 /* c.un.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9399 { 1963 /* c.un.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9400 { 1963 /* c.un.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9401 { 1963 /* c.un.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9402 { 1963 /* c.un.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9403 { 1963 /* c.un.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9404 { 1963 /* c.un.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9405 { 1963 /* c.un.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9406 { 1963 /* c.un.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9407 { 1963 /* c.un.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9408 { 1963 /* c.un.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9409 { 1970 /* c.un.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips },
9410 { 1970 /* c.un.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9411 { 1970 /* c.un.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips },
9412 { 1970 /* c.un.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips },
9413 { 1970 /* c.un.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9414 { 1970 /* c.un.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9415 { 1977 /* cache */, 2 /* 1 */, MCK_SImmOffset9_0, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
9416 { 1977 /* cache */, 8 /* 3 */, MCK_PtrReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
9417 { 1977 /* cache */, 2 /* 1 */, MCK_SImmPtr, AMFBS_HasStdEnc_HasMips3_32_NotMips32r6_NotMips64r6_NotInMicroMips },
9418 { 1977 /* cache */, 8 /* 3 */, MCK_PtrReg, AMFBS_HasStdEnc_HasMips3_32_NotMips32r6_NotMips64r6_NotInMicroMips },
9419 { 1977 /* cache */, 2 /* 1 */, MCK_AnyOffset, AMFBS_InMicroMips_NotMips32r6 },
9420 { 1977 /* cache */, 8 /* 3 */, MCK_PtrReg, AMFBS_InMicroMips_NotMips32r6 },
9421 { 1977 /* cache */, 2 /* 1 */, MCK_AnyOffset, AMFBS_InMicroMips_HasMips32r6 },
9422 { 1977 /* cache */, 8 /* 3 */, MCK_PtrReg, AMFBS_InMicroMips_HasMips32r6 },
9423 { 1983 /* cachee */, 2 /* 1 */, MCK_SImmOffset9_0, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips },
9424 { 1983 /* cachee */, 8 /* 3 */, MCK_PtrReg, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips },
9425 { 1983 /* cachee */, 2 /* 1 */, MCK_SImmOffset9_0, AMFBS_InMicroMips_HasEVA },
9426 { 1983 /* cachee */, 8 /* 3 */, MCK_PtrReg, AMFBS_InMicroMips_HasEVA },
9427 { 1990 /* ceil.l.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips3_32_IsNotSoftFloat_NotInMicroMips },
9428 { 1990 /* ceil.l.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9429 { 1999 /* ceil.l.s */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips },
9430 { 1999 /* ceil.l.s */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips },
9431 { 1999 /* ceil.l.s */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9432 { 1999 /* ceil.l.s */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9433 { 2008 /* ceil.w.d */, 2 /* 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips },
9434 { 2008 /* ceil.w.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips },
9435 { 2008 /* ceil.w.d */, 2 /* 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat },
9436 { 2008 /* ceil.w.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat },
9437 { 2008 /* ceil.w.d */, 2 /* 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9438 { 2008 /* ceil.w.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9439 { 2008 /* ceil.w.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips },
9440 { 2008 /* ceil.w.d */, 2 /* 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips },
9441 { 2017 /* ceil.w.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotR5900_IsNotSoftFloat_NotInMicroMips },
9442 { 2017 /* ceil.w.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9443 { 2017 /* ceil.w.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat },
9444 { 2026 /* ceq.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9445 { 2032 /* ceq.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9446 { 2038 /* ceq.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9447 { 2044 /* ceq.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9448 { 2050 /* ceqi.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9449 { 2057 /* ceqi.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9450 { 2064 /* ceqi.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9451 { 2071 /* ceqi.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9452 { 2078 /* cfc1 */, 2 /* 1 */, MCK_CCRAsmReg, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips },
9453 { 2078 /* cfc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips },
9454 { 2078 /* cfc1 */, 2 /* 1 */, MCK_CCRAsmReg, AMFBS_InMicroMips_IsNotSoftFloat },
9455 { 2078 /* cfc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat },
9456 { 2083 /* cfc2 */, 2 /* 1 */, MCK_COP2AsmReg, AMFBS_InMicroMips },
9457 { 2083 /* cfc2 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
9458 { 2088 /* cfcmsa */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA },
9459 { 2088 /* cfcmsa */, 2 /* 1 */, MCK_MSACtrlAsmReg, AMFBS_HasStdEnc_HasMSA },
9460 { 2095 /* cftc1 */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_HasMT },
9461 { 2095 /* cftc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT },
9462 { 2101 /* cins */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasMips64_HasCnMips_NotInMicroMips },
9463 { 2101 /* cins */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasMips64_HasCnMips },
9464 { 2101 /* cins */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasMips64_HasCnMips_NotInMicroMips },
9465 { 2101 /* cins */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasMips64_HasCnMips },
9466 { 2106 /* cins32 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasMips64_HasCnMips_NotInMicroMips },
9467 { 2106 /* cins32 */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasMips64_HasCnMips_NotInMicroMips },
9468 { 2113 /* class.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
9469 { 2113 /* class.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6 },
9470 { 2121 /* class.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
9471 { 2121 /* class.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
9472 { 2129 /* cle_s.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9473 { 2137 /* cle_s.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9474 { 2145 /* cle_s.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9475 { 2153 /* cle_s.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9476 { 2161 /* cle_u.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9477 { 2169 /* cle_u.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9478 { 2177 /* cle_u.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9479 { 2185 /* cle_u.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9480 { 2193 /* clei_s.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9481 { 2202 /* clei_s.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9482 { 2211 /* clei_s.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9483 { 2220 /* clei_s.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9484 { 2229 /* clei_u.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9485 { 2238 /* clei_u.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9486 { 2247 /* clei_u.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9487 { 2256 /* clei_u.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9488 { 2265 /* clo */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips },
9489 { 2265 /* clo */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
9490 { 2265 /* clo */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6 },
9491 { 2265 /* clo */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
9492 { 2269 /* clt_s.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9493 { 2277 /* clt_s.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9494 { 2285 /* clt_s.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9495 { 2293 /* clt_s.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9496 { 2301 /* clt_u.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9497 { 2309 /* clt_u.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9498 { 2317 /* clt_u.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9499 { 2325 /* clt_u.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9500 { 2333 /* clti_s.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9501 { 2342 /* clti_s.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9502 { 2351 /* clti_s.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9503 { 2360 /* clti_s.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9504 { 2369 /* clti_u.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9505 { 2378 /* clti_u.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9506 { 2387 /* clti_u.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9507 { 2396 /* clti_u.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9508 { 2405 /* clz */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips },
9509 { 2405 /* clz */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
9510 { 2405 /* clz */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6 },
9511 { 2405 /* clz */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
9512 { 2413 /* cmp.af.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
9513 { 2413 /* cmp.af.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9514 { 2422 /* cmp.af.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
9515 { 2422 /* cmp.af.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9516 { 2431 /* cmp.eq.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
9517 { 2431 /* cmp.eq.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9518 { 2440 /* cmp.eq.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
9519 { 2440 /* cmp.eq.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
9520 { 2450 /* cmp.eq.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
9521 { 2450 /* cmp.eq.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9522 { 2459 /* cmp.le.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
9523 { 2459 /* cmp.le.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9524 { 2468 /* cmp.le.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
9525 { 2468 /* cmp.le.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
9526 { 2478 /* cmp.le.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
9527 { 2478 /* cmp.le.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9528 { 2487 /* cmp.lt.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
9529 { 2487 /* cmp.lt.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9530 { 2496 /* cmp.lt.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
9531 { 2496 /* cmp.lt.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
9532 { 2506 /* cmp.lt.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
9533 { 2506 /* cmp.lt.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9534 { 2515 /* cmp.saf.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
9535 { 2515 /* cmp.saf.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9536 { 2525 /* cmp.saf.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
9537 { 2525 /* cmp.saf.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9538 { 2535 /* cmp.seq.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
9539 { 2535 /* cmp.seq.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9540 { 2545 /* cmp.seq.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
9541 { 2545 /* cmp.seq.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9542 { 2555 /* cmp.sle.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
9543 { 2555 /* cmp.sle.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9544 { 2565 /* cmp.sle.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
9545 { 2565 /* cmp.sle.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9546 { 2575 /* cmp.slt.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
9547 { 2575 /* cmp.slt.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9548 { 2585 /* cmp.slt.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
9549 { 2585 /* cmp.slt.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9550 { 2595 /* cmp.sueq.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
9551 { 2595 /* cmp.sueq.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9552 { 2606 /* cmp.sueq.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
9553 { 2606 /* cmp.sueq.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9554 { 2617 /* cmp.sule.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
9555 { 2617 /* cmp.sule.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9556 { 2628 /* cmp.sule.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
9557 { 2628 /* cmp.sule.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9558 { 2639 /* cmp.sult.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
9559 { 2639 /* cmp.sult.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9560 { 2650 /* cmp.sult.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
9561 { 2650 /* cmp.sult.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9562 { 2661 /* cmp.sun.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
9563 { 2661 /* cmp.sun.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9564 { 2671 /* cmp.sun.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
9565 { 2671 /* cmp.sun.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9566 { 2681 /* cmp.ueq.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
9567 { 2681 /* cmp.ueq.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9568 { 2691 /* cmp.ueq.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
9569 { 2691 /* cmp.ueq.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9570 { 2701 /* cmp.ule.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
9571 { 2701 /* cmp.ule.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9572 { 2711 /* cmp.ule.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
9573 { 2711 /* cmp.ule.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9574 { 2721 /* cmp.ult.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
9575 { 2721 /* cmp.ult.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9576 { 2731 /* cmp.ult.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
9577 { 2731 /* cmp.ult.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9578 { 2741 /* cmp.un.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
9579 { 2741 /* cmp.un.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9580 { 2750 /* cmp.un.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
9581 { 2750 /* cmp.un.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9582 { 2759 /* cmpgdu.eq.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
9583 { 2759 /* cmpgdu.eq.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
9584 { 2772 /* cmpgdu.le.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
9585 { 2772 /* cmpgdu.le.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
9586 { 2785 /* cmpgdu.lt.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
9587 { 2785 /* cmpgdu.lt.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
9588 { 2798 /* cmpgu.eq.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
9589 { 2798 /* cmpgu.eq.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
9590 { 2810 /* cmpgu.le.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
9591 { 2810 /* cmpgu.le.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
9592 { 2822 /* cmpgu.lt.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
9593 { 2822 /* cmpgu.lt.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
9594 { 2839 /* cmpu.eq.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
9595 { 2839 /* cmpu.eq.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
9596 { 2850 /* cmpu.le.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
9597 { 2850 /* cmpu.le.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
9598 { 2861 /* cmpu.lt.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
9599 { 2861 /* cmpu.lt.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
9600 { 2872 /* copy_s.b */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA },
9601 { 2872 /* copy_s.b */, 2 /* 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9602 { 2881 /* copy_s.d */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMSA_HasMips64 },
9603 { 2881 /* copy_s.d */, 2 /* 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA_HasMips64 },
9604 { 2890 /* copy_s.h */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA },
9605 { 2890 /* copy_s.h */, 2 /* 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9606 { 2899 /* copy_s.w */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA },
9607 { 2899 /* copy_s.w */, 2 /* 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9608 { 2908 /* copy_u.b */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA },
9609 { 2908 /* copy_u.b */, 2 /* 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9610 { 2917 /* copy_u.h */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA },
9611 { 2917 /* copy_u.h */, 2 /* 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9612 { 2926 /* copy_u.w */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA_HasMips64 },
9613 { 2926 /* copy_u.w */, 2 /* 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA_HasMips64 },
9614 { 2935 /* crc32b */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips },
9615 { 2942 /* crc32cb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips },
9616 { 2950 /* crc32cd */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips64r6_HasCRC_NotInMicroMips },
9617 { 2958 /* crc32ch */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips },
9618 { 2966 /* crc32cw */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips },
9619 { 2974 /* crc32d */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips64r6_HasCRC_NotInMicroMips },
9620 { 2981 /* crc32h */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips },
9621 { 2988 /* crc32w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips },
9622 { 2995 /* ctc1 */, 2 /* 1 */, MCK_CCRAsmReg, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips },
9623 { 2995 /* ctc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips },
9624 { 2995 /* ctc1 */, 2 /* 1 */, MCK_CCRAsmReg, AMFBS_InMicroMips_IsNotSoftFloat },
9625 { 2995 /* ctc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat },
9626 { 3000 /* ctc2 */, 2 /* 1 */, MCK_COP2AsmReg, AMFBS_InMicroMips },
9627 { 3000 /* ctc2 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
9628 { 3005 /* ctcmsa */, 2 /* 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA },
9629 { 3005 /* ctcmsa */, 1 /* 0 */, MCK_MSACtrlAsmReg, AMFBS_HasStdEnc_HasMSA },
9630 { 3012 /* cttc1 */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_HasMT },
9631 { 3012 /* cttc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT },
9632 { 3018 /* cvt.d.l */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips },
9633 { 3018 /* cvt.d.l */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_HasMips32r6_IsNotSoftFloat },
9634 { 3026 /* cvt.d.s */, 1 /* 0 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips },
9635 { 3026 /* cvt.d.s */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips },
9636 { 3026 /* cvt.d.s */, 1 /* 0 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat },
9637 { 3026 /* cvt.d.s */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat },
9638 { 3026 /* cvt.d.s */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips },
9639 { 3026 /* cvt.d.s */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips },
9640 { 3026 /* cvt.d.s */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat },
9641 { 3026 /* cvt.d.s */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat },
9642 { 3034 /* cvt.d.w */, 1 /* 0 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips },
9643 { 3034 /* cvt.d.w */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips },
9644 { 3034 /* cvt.d.w */, 1 /* 0 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat },
9645 { 3034 /* cvt.d.w */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat },
9646 { 3034 /* cvt.d.w */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips },
9647 { 3034 /* cvt.d.w */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips },
9648 { 3034 /* cvt.d.w */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat },
9649 { 3034 /* cvt.d.w */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat },
9650 { 3042 /* cvt.l.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips },
9651 { 3042 /* cvt.l.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat },
9652 { 3042 /* cvt.l.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9653 { 3050 /* cvt.l.s */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips },
9654 { 3050 /* cvt.l.s */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips },
9655 { 3050 /* cvt.l.s */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat },
9656 { 3050 /* cvt.l.s */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat },
9657 { 3050 /* cvt.l.s */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9658 { 3050 /* cvt.l.s */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9659 { 3058 /* cvt.ps.pw */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMips3D },
9660 { 3068 /* cvt.ps.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9661 { 3068 /* cvt.ps.s */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9662 { 3077 /* cvt.pw.ps */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMips3D },
9663 { 3087 /* cvt.s.d */, 2 /* 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips },
9664 { 3087 /* cvt.s.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips },
9665 { 3087 /* cvt.s.d */, 2 /* 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat },
9666 { 3087 /* cvt.s.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat },
9667 { 3087 /* cvt.s.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips },
9668 { 3087 /* cvt.s.d */, 2 /* 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips },
9669 { 3087 /* cvt.s.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat },
9670 { 3087 /* cvt.s.d */, 2 /* 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat },
9671 { 3095 /* cvt.s.l */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips },
9672 { 3095 /* cvt.s.l */, 2 /* 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips },
9673 { 3095 /* cvt.s.l */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_HasMips32r6_IsNotSoftFloat },
9674 { 3095 /* cvt.s.l */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_HasMips32r6_IsNotSoftFloat },
9675 { 3103 /* cvt.s.pl */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9676 { 3103 /* cvt.s.pl */, 2 /* 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9677 { 3112 /* cvt.s.pu */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9678 { 3112 /* cvt.s.pu */, 2 /* 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9679 { 3121 /* cvt.s.w */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips },
9680 { 3121 /* cvt.s.w */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9681 { 3121 /* cvt.s.w */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat },
9682 { 3129 /* cvt.w.d */, 2 /* 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips },
9683 { 3129 /* cvt.w.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips },
9684 { 3129 /* cvt.w.d */, 2 /* 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat },
9685 { 3129 /* cvt.w.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat },
9686 { 3129 /* cvt.w.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips },
9687 { 3129 /* cvt.w.d */, 2 /* 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips },
9688 { 3129 /* cvt.w.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat },
9689 { 3129 /* cvt.w.d */, 2 /* 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat },
9690 { 3137 /* cvt.w.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips },
9691 { 3137 /* cvt.w.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9692 { 3137 /* cvt.w.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat },
9693 { 3145 /* dadd */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9694 { 3145 /* dadd */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips },
9695 { 3145 /* dadd */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9696 { 3145 /* dadd */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips },
9697 { 3150 /* daddi */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 },
9698 { 3150 /* daddi */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 },
9699 { 3156 /* daddiu */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9700 { 3156 /* daddiu */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9701 { 3163 /* daddu */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9702 { 3163 /* daddu */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9703 { 3163 /* daddu */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9704 { 3163 /* daddu */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9705 { 3169 /* dahi */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips },
9706 { 3174 /* dalign */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips },
9707 { 3181 /* dati */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips },
9708 { 3186 /* daui */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips },
9709 { 3191 /* dbitswap */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips },
9710 { 3200 /* dclo */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips64_NotMips64r6_NotInMicroMips },
9711 { 3200 /* dclo */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips },
9712 { 3205 /* dclz */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips64_NotMips64r6_NotInMicroMips },
9713 { 3205 /* dclz */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips },
9714 { 3210 /* ddiv */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips },
9715 { 3210 /* ddiv */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips },
9716 { 3210 /* ddiv */, 6 /* 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips },
9717 { 3210 /* ddiv */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips },
9718 { 3210 /* ddiv */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips },
9719 { 3210 /* ddiv */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips },
9720 { 3215 /* ddivu */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips },
9721 { 3215 /* ddivu */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips },
9722 { 3215 /* ddivu */, 6 /* 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips },
9723 { 3215 /* ddivu */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips },
9724 { 3215 /* ddivu */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips },
9725 { 3215 /* ddivu */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips },
9726 { 3227 /* dext */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips },
9727 { 3227 /* dext */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips },
9728 { 3227 /* dext */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips },
9729 { 3232 /* dextm */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips },
9730 { 3238 /* dextu */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips },
9731 { 3244 /* di */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips },
9732 { 3244 /* di */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
9733 { 3244 /* di */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
9734 { 3247 /* dins */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips },
9735 { 3247 /* dins */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips },
9736 { 3247 /* dins */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips },
9737 { 3252 /* dinsm */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips },
9738 { 3258 /* dinsu */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips },
9739 { 3264 /* div */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6 },
9740 { 3264 /* div */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 },
9741 { 3264 /* div */, 2 /* 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 },
9742 { 3264 /* div */, 1 /* 0 */, MCK_GPR32NonZeroAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 },
9743 { 3264 /* div */, 2 /* 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 },
9744 { 3264 /* div */, 1 /* 0 */, MCK_GPR32ZeroAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 },
9745 { 3264 /* div */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips },
9746 { 3264 /* div */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
9747 { 3264 /* div */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
9748 { 3264 /* div */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
9749 { 3264 /* div */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 },
9750 { 3264 /* div */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 },
9751 { 3264 /* div */, 1 /* 0 */, MCK_GPR32NonZeroAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 },
9752 { 3268 /* div.d */, 7 /* 0, 1, 2 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips },
9753 { 3268 /* div.d */, 7 /* 0, 1, 2 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat },
9754 { 3268 /* div.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips },
9755 { 3268 /* div.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat },
9756 { 3274 /* div.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips },
9757 { 3274 /* div.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9758 { 3274 /* div.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat },
9759 { 3280 /* div_s.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9760 { 3288 /* div_s.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9761 { 3296 /* div_s.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9762 { 3304 /* div_s.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9763 { 3312 /* div_u.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9764 { 3320 /* div_u.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9765 { 3328 /* div_u.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9766 { 3336 /* div_u.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9767 { 3344 /* divu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6 },
9768 { 3344 /* divu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 },
9769 { 3344 /* divu */, 2 /* 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 },
9770 { 3344 /* divu */, 1 /* 0 */, MCK_GPR32NonZeroAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 },
9771 { 3344 /* divu */, 2 /* 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 },
9772 { 3344 /* divu */, 1 /* 0 */, MCK_GPR32ZeroAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 },
9773 { 3344 /* divu */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips },
9774 { 3344 /* divu */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
9775 { 3344 /* divu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 },
9776 { 3344 /* divu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
9777 { 3344 /* divu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
9778 { 3344 /* divu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 },
9779 { 3349 /* dla */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_None },
9780 { 3349 /* dla */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_None },
9781 { 3349 /* dla */, 2 /* 1 */, MCK_Mem, AMFBS_None },
9782 { 3353 /* dli */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_None },
9783 { 3357 /* dlsa */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMSA_HasMips64 },
9784 { 3357 /* dlsa */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips },
9785 { 3362 /* dmfc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_NotInMicroMips },
9786 { 3362 /* dmfc0 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_NotInMicroMips },
9787 { 3362 /* dmfc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips3 },
9788 { 3362 /* dmfc0 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips3 },
9789 { 3368 /* dmfc1 */, 2 /* 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips3_IsNotSoftFloat_IsNotSingleFloat },
9790 { 3368 /* dmfc1 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_IsNotSoftFloat_IsNotSingleFloat },
9791 { 3374 /* dmfc2 */, 2 /* 1 */, MCK_COP2AsmReg, AMFBS_None },
9792 { 3374 /* dmfc2 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_None },
9793 { 3374 /* dmfc2 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasCnMips },
9794 { 3374 /* dmfc2 */, 2 /* 1 */, MCK_COP2AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips3 },
9795 { 3374 /* dmfc2 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips3 },
9796 { 3380 /* dmfgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasStdEnc_HasMips64r5_HasVirt_NotInMicroMips },
9797 { 3380 /* dmfgc0 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r5_HasVirt_NotInMicroMips },
9798 { 3380 /* dmfgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasStdEnc_HasMips64r5_HasVirt },
9799 { 3380 /* dmfgc0 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r5_HasVirt },
9800 { 3387 /* dmod */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips },
9801 { 3392 /* dmodu */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips },
9802 { 3398 /* dmt */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMT_NotInMicroMips },
9803 { 3402 /* dmtc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_NotInMicroMips },
9804 { 3402 /* dmtc0 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_NotInMicroMips },
9805 { 3402 /* dmtc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips3 },
9806 { 3402 /* dmtc0 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips3 },
9807 { 3408 /* dmtc1 */, 2 /* 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips3_IsNotSoftFloat_IsNotSingleFloat },
9808 { 3408 /* dmtc1 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_IsNotSoftFloat_IsNotSingleFloat },
9809 { 3414 /* dmtc2 */, 2 /* 1 */, MCK_COP2AsmReg, AMFBS_None },
9810 { 3414 /* dmtc2 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_None },
9811 { 3414 /* dmtc2 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasCnMips },
9812 { 3414 /* dmtc2 */, 2 /* 1 */, MCK_COP2AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips3 },
9813 { 3414 /* dmtc2 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips3 },
9814 { 3420 /* dmtgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasStdEnc_HasMips64r5_HasVirt_NotInMicroMips },
9815 { 3420 /* dmtgc0 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r5_HasVirt_NotInMicroMips },
9816 { 3420 /* dmtgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasStdEnc_HasMips64r5_HasVirt },
9817 { 3420 /* dmtgc0 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r5_HasVirt },
9818 { 3427 /* dmuh */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips },
9819 { 3432 /* dmuhu */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips },
9820 { 3438 /* dmul */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasCnMips },
9821 { 3438 /* dmul */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasMips3_NotMips64r6_NotCnMips_NotR5900 },
9822 { 3438 /* dmul */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips },
9823 { 3438 /* dmul */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasCnMips },
9824 { 3438 /* dmul */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900 },
9825 { 3443 /* dmulo */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900 },
9826 { 3449 /* dmulou */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900 },
9827 { 3456 /* dmult */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips },
9828 { 3462 /* dmultu */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips },
9829 { 3469 /* dmulu */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips },
9830 { 3475 /* dneg */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9831 { 3475 /* dneg */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9832 { 3480 /* dnegu */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9833 { 3480 /* dnegu */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9834 { 3486 /* dotp_s.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9835 { 3495 /* dotp_s.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9836 { 3504 /* dotp_s.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9837 { 3513 /* dotp_u.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9838 { 3522 /* dotp_u.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9839 { 3531 /* dotp_u.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9840 { 3540 /* dpa.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSPR2 },
9841 { 3540 /* dpa.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
9842 { 3540 /* dpa.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSPR2 },
9843 { 3540 /* dpa.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
9844 { 3549 /* dpadd_s.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9845 { 3559 /* dpadd_s.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9846 { 3569 /* dpadd_s.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9847 { 3579 /* dpadd_u.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9848 { 3589 /* dpadd_u.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9849 { 3599 /* dpadd_u.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9850 { 3609 /* dpaq_s.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
9851 { 3609 /* dpaq_s.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
9852 { 3609 /* dpaq_s.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
9853 { 3609 /* dpaq_s.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
9854 { 3621 /* dpaq_sa.l.w */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
9855 { 3621 /* dpaq_sa.l.w */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
9856 { 3621 /* dpaq_sa.l.w */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
9857 { 3621 /* dpaq_sa.l.w */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
9858 { 3633 /* dpaqx_s.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSPR2 },
9859 { 3633 /* dpaqx_s.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
9860 { 3633 /* dpaqx_s.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSPR2 },
9861 { 3633 /* dpaqx_s.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
9862 { 3646 /* dpaqx_sa.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSPR2 },
9863 { 3646 /* dpaqx_sa.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
9864 { 3646 /* dpaqx_sa.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSPR2 },
9865 { 3646 /* dpaqx_sa.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
9866 { 3660 /* dpau.h.qbl */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
9867 { 3660 /* dpau.h.qbl */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
9868 { 3660 /* dpau.h.qbl */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
9869 { 3660 /* dpau.h.qbl */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
9870 { 3671 /* dpau.h.qbr */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
9871 { 3671 /* dpau.h.qbr */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
9872 { 3671 /* dpau.h.qbr */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
9873 { 3671 /* dpau.h.qbr */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
9874 { 3682 /* dpax.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSPR2 },
9875 { 3682 /* dpax.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
9876 { 3682 /* dpax.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSPR2 },
9877 { 3682 /* dpax.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
9878 { 3692 /* dpop */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasCnMips },
9879 { 3692 /* dpop */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasCnMips },
9880 { 3697 /* dps.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSPR2 },
9881 { 3697 /* dps.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
9882 { 3697 /* dps.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSPR2 },
9883 { 3697 /* dps.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
9884 { 3706 /* dpsq_s.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
9885 { 3706 /* dpsq_s.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
9886 { 3706 /* dpsq_s.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
9887 { 3706 /* dpsq_s.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
9888 { 3718 /* dpsq_sa.l.w */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
9889 { 3718 /* dpsq_sa.l.w */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
9890 { 3718 /* dpsq_sa.l.w */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
9891 { 3718 /* dpsq_sa.l.w */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
9892 { 3730 /* dpsqx_s.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSPR2 },
9893 { 3730 /* dpsqx_s.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
9894 { 3730 /* dpsqx_s.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSPR2 },
9895 { 3730 /* dpsqx_s.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
9896 { 3743 /* dpsqx_sa.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSPR2 },
9897 { 3743 /* dpsqx_sa.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
9898 { 3743 /* dpsqx_sa.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSPR2 },
9899 { 3743 /* dpsqx_sa.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
9900 { 3757 /* dpsu.h.qbl */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
9901 { 3757 /* dpsu.h.qbl */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
9902 { 3757 /* dpsu.h.qbl */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
9903 { 3757 /* dpsu.h.qbl */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
9904 { 3768 /* dpsu.h.qbr */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
9905 { 3768 /* dpsu.h.qbr */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
9906 { 3768 /* dpsu.h.qbr */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
9907 { 3768 /* dpsu.h.qbr */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
9908 { 3779 /* dpsub_s.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9909 { 3789 /* dpsub_s.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9910 { 3799 /* dpsub_s.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9911 { 3809 /* dpsub_u.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9912 { 3819 /* dpsub_u.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9913 { 3829 /* dpsub_u.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9914 { 3839 /* dpsx.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSPR2 },
9915 { 3839 /* dpsx.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
9916 { 3839 /* dpsx.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSPR2 },
9917 { 3839 /* dpsx.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
9918 { 3849 /* drem */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips },
9919 { 3849 /* drem */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips },
9920 { 3849 /* drem */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips },
9921 { 3849 /* drem */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips },
9922 { 3854 /* dremu */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips },
9923 { 3854 /* dremu */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips },
9924 { 3854 /* dremu */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips },
9925 { 3854 /* dremu */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips },
9926 { 3860 /* drol */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips64 },
9927 { 3860 /* drol */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips64 },
9928 { 3860 /* drol */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips64 },
9929 { 3860 /* drol */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips64 },
9930 { 3865 /* dror */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips64 },
9931 { 3865 /* dror */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips64 },
9932 { 3865 /* dror */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips64 },
9933 { 3865 /* dror */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips64 },
9934 { 3870 /* drotr */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips },
9935 { 3870 /* drotr */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips },
9936 { 3876 /* drotr32 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips },
9937 { 3876 /* drotr32 */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips },
9938 { 3884 /* drotrv */, 4 /* 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips },
9939 { 3884 /* drotrv */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips },
9940 { 3891 /* dsbh */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips },
9941 { 3896 /* dshd */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips },
9942 { 3901 /* dsll */, 2 /* 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9943 { 3901 /* dsll */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9944 { 3901 /* dsll */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9945 { 3901 /* dsll */, 4 /* 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9946 { 3901 /* dsll */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9947 { 3901 /* dsll */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9948 { 3906 /* dsll32 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9949 { 3906 /* dsll32 */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9950 { 3913 /* dsllv */, 4 /* 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9951 { 3913 /* dsllv */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9952 { 3919 /* dsra */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9953 { 3919 /* dsra */, 4 /* 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips3 },
9954 { 3919 /* dsra */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3 },
9955 { 3919 /* dsra */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9956 { 3924 /* dsra32 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9957 { 3924 /* dsra32 */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9958 { 3931 /* dsrav */, 4 /* 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9959 { 3931 /* dsrav */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9960 { 3937 /* dsrl */, 2 /* 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9961 { 3937 /* dsrl */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9962 { 3937 /* dsrl */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9963 { 3937 /* dsrl */, 4 /* 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9964 { 3937 /* dsrl */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9965 { 3937 /* dsrl */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9966 { 3942 /* dsrl32 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9967 { 3942 /* dsrl32 */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9968 { 3949 /* dsrlv */, 4 /* 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9969 { 3949 /* dsrlv */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9970 { 3955 /* dsub */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9971 { 3955 /* dsub */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 },
9972 { 3955 /* dsub */, 2 /* 1 */, MCK_InvNum, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 },
9973 { 3955 /* dsub */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9974 { 3955 /* dsub */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 },
9975 { 3955 /* dsub */, 4 /* 2 */, MCK_InvNum, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 },
9976 { 3960 /* dsubi */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 },
9977 { 3960 /* dsubi */, 2 /* 1 */, MCK_InvNum, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 },
9978 { 3960 /* dsubi */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 },
9979 { 3960 /* dsubi */, 4 /* 2 */, MCK_InvNum, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 },
9980 { 3966 /* dsubu */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9981 { 3966 /* dsubu */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9982 { 3966 /* dsubu */, 2 /* 1 */, MCK_InvNum, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9983 { 3966 /* dsubu */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9984 { 3966 /* dsubu */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9985 { 3966 /* dsubu */, 4 /* 2 */, MCK_InvNum, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9986 { 3972 /* dvp */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6 },
9987 { 3972 /* dvp */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
9988 { 3976 /* dvpe */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMT_NotInMicroMips },
9989 { 3985 /* ei */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips },
9990 { 3985 /* ei */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
9991 { 3985 /* ei */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
9992 { 3988 /* emt */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMT_NotInMicroMips },
9993 { 4004 /* evp */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6 },
9994 { 4004 /* evp */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
9995 { 4008 /* evpe */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMT_NotInMicroMips },
9996 { 4013 /* ext */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips },
9997 { 4013 /* ext */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
9998 { 4013 /* ext */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
9999 { 4017 /* extp */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
10000 { 4017 /* extp */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10001 { 4017 /* extp */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
10002 { 4017 /* extp */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10003 { 4022 /* extpdp */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
10004 { 4022 /* extpdp */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10005 { 4022 /* extpdp */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
10006 { 4022 /* extpdp */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10007 { 4029 /* extpdpv */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
10008 { 4029 /* extpdpv */, 5 /* 0, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10009 { 4029 /* extpdpv */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
10010 { 4029 /* extpdpv */, 5 /* 0, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10011 { 4037 /* extpv */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
10012 { 4037 /* extpv */, 5 /* 0, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10013 { 4037 /* extpv */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
10014 { 4037 /* extpv */, 5 /* 0, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10015 { 4043 /* extr.w */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
10016 { 4043 /* extr.w */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10017 { 4043 /* extr.w */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
10018 { 4043 /* extr.w */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10019 { 4050 /* extr_r.w */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
10020 { 4050 /* extr_r.w */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10021 { 4050 /* extr_r.w */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
10022 { 4050 /* extr_r.w */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10023 { 4059 /* extr_rs.w */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
10024 { 4059 /* extr_rs.w */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10025 { 4059 /* extr_rs.w */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
10026 { 4059 /* extr_rs.w */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10027 { 4069 /* extr_s.h */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
10028 { 4069 /* extr_s.h */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10029 { 4069 /* extr_s.h */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
10030 { 4069 /* extr_s.h */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10031 { 4078 /* extrv.w */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
10032 { 4078 /* extrv.w */, 5 /* 0, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10033 { 4078 /* extrv.w */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
10034 { 4078 /* extrv.w */, 5 /* 0, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10035 { 4086 /* extrv_r.w */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
10036 { 4086 /* extrv_r.w */, 5 /* 0, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10037 { 4086 /* extrv_r.w */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
10038 { 4086 /* extrv_r.w */, 5 /* 0, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10039 { 4096 /* extrv_rs.w */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
10040 { 4096 /* extrv_rs.w */, 5 /* 0, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10041 { 4096 /* extrv_rs.w */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
10042 { 4096 /* extrv_rs.w */, 5 /* 0, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10043 { 4107 /* extrv_s.h */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
10044 { 4107 /* extrv_s.h */, 5 /* 0, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10045 { 4107 /* extrv_s.h */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
10046 { 4107 /* extrv_s.h */, 5 /* 0, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10047 { 4117 /* exts */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasMips64_HasCnMips_NotInMicroMips },
10048 { 4117 /* exts */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasMips64_HasCnMips },
10049 { 4117 /* exts */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasMips64_HasCnMips_NotInMicroMips },
10050 { 4117 /* exts */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasMips64_HasCnMips },
10051 { 4122 /* exts32 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasMips64_HasCnMips_NotInMicroMips },
10052 { 4122 /* exts32 */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasMips64_HasCnMips_NotInMicroMips },
10053 { 4129 /* fadd.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10054 { 4136 /* fadd.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10055 { 4143 /* fcaf.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10056 { 4150 /* fcaf.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10057 { 4157 /* fceq.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10058 { 4164 /* fceq.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10059 { 4171 /* fclass.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10060 { 4180 /* fclass.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10061 { 4189 /* fcle.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10062 { 4196 /* fcle.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10063 { 4203 /* fclt.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10064 { 4210 /* fclt.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10065 { 4217 /* fcne.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10066 { 4224 /* fcne.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10067 { 4231 /* fcor.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10068 { 4238 /* fcor.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10069 { 4245 /* fcueq.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10070 { 4253 /* fcueq.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10071 { 4261 /* fcule.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10072 { 4269 /* fcule.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10073 { 4277 /* fcult.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10074 { 4285 /* fcult.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10075 { 4293 /* fcun.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10076 { 4300 /* fcun.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10077 { 4307 /* fcune.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10078 { 4315 /* fcune.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10079 { 4323 /* fdiv.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10080 { 4330 /* fdiv.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10081 { 4337 /* fexdo.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10082 { 4345 /* fexdo.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10083 { 4353 /* fexp2.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10084 { 4361 /* fexp2.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10085 { 4369 /* fexupl.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10086 { 4378 /* fexupl.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10087 { 4387 /* fexupr.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10088 { 4396 /* fexupr.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10089 { 4405 /* ffint_s.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10090 { 4415 /* ffint_s.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10091 { 4425 /* ffint_u.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10092 { 4435 /* ffint_u.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10093 { 4445 /* ffql.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10094 { 4452 /* ffql.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10095 { 4459 /* ffqr.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10096 { 4466 /* ffqr.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10097 { 4473 /* fill.b */, 2 /* 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA },
10098 { 4473 /* fill.b */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10099 { 4480 /* fill.d */, 2 /* 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMSA_HasMips64 },
10100 { 4480 /* fill.d */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA_HasMips64 },
10101 { 4487 /* fill.h */, 2 /* 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA },
10102 { 4487 /* fill.h */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10103 { 4494 /* fill.w */, 2 /* 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA },
10104 { 4494 /* fill.w */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10105 { 4501 /* flog2.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10106 { 4509 /* flog2.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10107 { 4517 /* floor.l.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips3_32_IsNotSoftFloat_NotInMicroMips },
10108 { 4517 /* floor.l.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
10109 { 4527 /* floor.l.s */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips },
10110 { 4527 /* floor.l.s */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips },
10111 { 4527 /* floor.l.s */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
10112 { 4527 /* floor.l.s */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
10113 { 4537 /* floor.w.d */, 2 /* 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips },
10114 { 4537 /* floor.w.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips },
10115 { 4537 /* floor.w.d */, 2 /* 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat },
10116 { 4537 /* floor.w.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat },
10117 { 4537 /* floor.w.d */, 2 /* 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
10118 { 4537 /* floor.w.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
10119 { 4537 /* floor.w.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips },
10120 { 4537 /* floor.w.d */, 2 /* 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips },
10121 { 4547 /* floor.w.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotR5900_IsNotSoftFloat_NotInMicroMips },
10122 { 4547 /* floor.w.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
10123 { 4547 /* floor.w.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat },
10124 { 4557 /* fmadd.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10125 { 4565 /* fmadd.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10126 { 4573 /* fmax.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10127 { 4580 /* fmax.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10128 { 4587 /* fmax_a.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10129 { 4596 /* fmax_a.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10130 { 4605 /* fmin.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10131 { 4612 /* fmin.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10132 { 4619 /* fmin_a.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10133 { 4628 /* fmin_a.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10134 { 4637 /* fmsub.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10135 { 4645 /* fmsub.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10136 { 4653 /* fmul.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10137 { 4660 /* fmul.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10138 { 4667 /* fork */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMT_NotInMicroMips },
10139 { 4672 /* frcp.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10140 { 4679 /* frcp.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10141 { 4686 /* frint.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10142 { 4694 /* frint.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10143 { 4702 /* frsqrt.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10144 { 4711 /* frsqrt.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10145 { 4720 /* fsaf.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10146 { 4727 /* fsaf.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10147 { 4734 /* fseq.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10148 { 4741 /* fseq.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10149 { 4748 /* fsle.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10150 { 4755 /* fsle.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10151 { 4762 /* fslt.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10152 { 4769 /* fslt.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10153 { 4776 /* fsne.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10154 { 4783 /* fsne.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10155 { 4790 /* fsor.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10156 { 4797 /* fsor.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10157 { 4804 /* fsqrt.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10158 { 4812 /* fsqrt.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10159 { 4820 /* fsub.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10160 { 4827 /* fsub.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10161 { 4834 /* fsueq.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10162 { 4842 /* fsueq.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10163 { 4850 /* fsule.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10164 { 4858 /* fsule.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10165 { 4866 /* fsult.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10166 { 4874 /* fsult.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10167 { 4882 /* fsun.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10168 { 4889 /* fsun.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10169 { 4896 /* fsune.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10170 { 4904 /* fsune.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10171 { 4912 /* ftint_s.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10172 { 4922 /* ftint_s.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10173 { 4932 /* ftint_u.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10174 { 4942 /* ftint_u.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10175 { 4952 /* ftq.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10176 { 4958 /* ftq.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10177 { 4964 /* ftrunc_s.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10178 { 4975 /* ftrunc_s.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10179 { 4986 /* ftrunc_u.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10180 { 4997 /* ftrunc_u.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10181 { 5008 /* ginvi */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_HasGINV_NotInMicroMips },
10182 { 5008 /* ginvi */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6_HasGINV },
10183 { 5014 /* ginvt */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_HasGINV_NotInMicroMips },
10184 { 5014 /* ginvt */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6_HasGINV },
10185 { 5020 /* hadd_s.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10186 { 5029 /* hadd_s.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10187 { 5038 /* hadd_s.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10188 { 5047 /* hadd_u.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10189 { 5056 /* hadd_u.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10190 { 5065 /* hadd_u.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10191 { 5074 /* hsub_s.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10192 { 5083 /* hsub_s.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10193 { 5092 /* hsub_s.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10194 { 5101 /* hsub_u.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10195 { 5110 /* hsub_u.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10196 { 5119 /* hsub_u.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10197 { 5136 /* ilvev.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10198 { 5144 /* ilvev.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10199 { 5152 /* ilvev.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10200 { 5160 /* ilvev.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10201 { 5168 /* ilvl.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10202 { 5175 /* ilvl.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10203 { 5182 /* ilvl.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10204 { 5189 /* ilvl.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10205 { 5196 /* ilvod.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10206 { 5204 /* ilvod.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10207 { 5212 /* ilvod.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10208 { 5220 /* ilvod.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10209 { 5228 /* ilvr.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10210 { 5235 /* ilvr.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10211 { 5242 /* ilvr.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10212 { 5249 /* ilvr.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10213 { 5256 /* ins */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips },
10214 { 5256 /* ins */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10215 { 5256 /* ins */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10216 { 5260 /* insert.b */, 16 /* 4 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA },
10217 { 5260 /* insert.b */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10218 { 5269 /* insert.d */, 16 /* 4 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMSA_HasMips64 },
10219 { 5269 /* insert.d */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA_HasMips64 },
10220 { 5278 /* insert.h */, 16 /* 4 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA },
10221 { 5278 /* insert.h */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10222 { 5287 /* insert.w */, 16 /* 4 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA },
10223 { 5287 /* insert.w */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10224 { 5296 /* insv */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10225 { 5296 /* insv */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10226 { 5301 /* insve.b */, 17 /* 0, 4 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10227 { 5309 /* insve.d */, 17 /* 0, 4 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10228 { 5317 /* insve.h */, 17 /* 0, 4 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10229 { 5325 /* insve.w */, 17 /* 0, 4 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10230 { 5333 /* j */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips },
10231 { 5333 /* j */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
10232 { 5333 /* j */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10233 { 5333 /* j */, 1 /* 0 */, MCK_JumpTarget, AMFBS_HasStdEnc_NotInMicroMips },
10234 { 5335 /* jal */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None },
10235 { 5335 /* jal */, 1 /* 0 */, MCK_JumpTarget, AMFBS_HasStdEnc_NotInMicroMips },
10236 { 5335 /* jal */, 1 /* 0 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 },
10237 { 5335 /* jal */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_None },
10238 { 5339 /* jalr */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10239 { 5339 /* jalr */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10240 { 5339 /* jalr */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_NotInMicroMips },
10241 { 5339 /* jalr */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips_NoIndirectJumpGuards },
10242 { 5339 /* jalr */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10243 { 5339 /* jalr */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_NotInMips16Mode_IsPTR64bit },
10244 { 5344 /* jalr.hb */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32_NotInMicroMips },
10245 { 5344 /* jalr.hb */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10246 { 5344 /* jalr.hb */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64_NotInMicroMips },
10247 { 5344 /* jalr.hb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32 },
10248 { 5344 /* jalr.hb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10249 { 5344 /* jalr.hb */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips },
10250 { 5352 /* jalrc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsGP32bit_HasMips32r6_NotInMicroMips },
10251 { 5352 /* jalrc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10252 { 5352 /* jalrc */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r6 },
10253 { 5352 /* jalrc */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10254 { 5358 /* jalrc.hb */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10255 { 5358 /* jalrc.hb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10256 { 5367 /* jalrs */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10257 { 5373 /* jalrs16 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10258 { 5386 /* jalx */, 1 /* 0 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips },
10259 { 5386 /* jalx */, 1 /* 0 */, MCK_JumpTarget, AMFBS_InMicroMips_NotMips32r6 },
10260 { 5391 /* jialc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6 },
10261 { 5391 /* jialc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6 },
10262 { 5391 /* jialc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10263 { 5391 /* jialc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 },
10264 { 5391 /* jialc */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 },
10265 { 5391 /* jialc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 },
10266 { 5397 /* jic */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6 },
10267 { 5397 /* jic */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6 },
10268 { 5397 /* jic */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10269 { 5397 /* jic */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 },
10270 { 5397 /* jic */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 },
10271 { 5397 /* jic */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 },
10272 { 5401 /* jr */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips },
10273 { 5401 /* jr */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsGP32bit_HasMips32r6_NotInMicroMips },
10274 { 5401 /* jr */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10275 { 5401 /* jr */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_NotInMips16Mode_IsPTR64bit_NotInMicroMips },
10276 { 5401 /* jr */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r6 },
10277 { 5404 /* jr.hb */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6 },
10278 { 5404 /* jr.hb */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10279 { 5404 /* jr.hb */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6 },
10280 { 5404 /* jr.hb */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64_NotMips64r6_NotInMicroMips },
10281 { 5404 /* jr.hb */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips32r6 },
10282 { 5410 /* jr16 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10283 { 5425 /* jrc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsGP32bit_HasMips32r6 },
10284 { 5425 /* jrc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10285 { 5425 /* jrc */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r6 },
10286 { 5429 /* jrc16 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10287 { 5446 /* l.d */, 1 /* 0 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat },
10288 { 5446 /* l.d */, 2 /* 1 */, MCK_SImmOffset16_0, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat },
10289 { 5446 /* l.d */, 8 /* 3 */, MCK_PtrReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat },
10290 { 5446 /* l.d */, 2 /* 1 */, MCK_SImmOffset16_0, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat },
10291 { 5446 /* l.d */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat },
10292 { 5446 /* l.d */, 8 /* 3 */, MCK_PtrReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat },
10293 { 5450 /* l.s */, 2 /* 1 */, MCK_SImmOffset16_0, AMFBS_HasStdEnc_HasMips2_IsNotSoftFloat },
10294 { 5450 /* l.s */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips2_IsNotSoftFloat },
10295 { 5450 /* l.s */, 8 /* 3 */, MCK_PtrReg, AMFBS_HasStdEnc_HasMips2_IsNotSoftFloat },
10296 { 5454 /* la */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None },
10297 { 5454 /* la */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None },
10298 { 5454 /* la */, 2 /* 1 */, MCK_Mem, AMFBS_None },
10299 { 5457 /* lapc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6 },
10300 { 5457 /* lapc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10301 { 5462 /* lb */, 2 /* 1 */, MCK_SImmOffset16_0, AMFBS_InMicroMips_HasMips32r6 },
10302 { 5462 /* lb */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10303 { 5462 /* lb */, 8 /* 3 */, MCK_PtrReg, AMFBS_InMicroMips_HasMips32r6 },
10304 { 5462 /* lb */, 2 /* 1 */, MCK_SImmOffset16_0, AMFBS_InMicroMips },
10305 { 5462 /* lb */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
10306 { 5462 /* lb */, 8 /* 3 */, MCK_PtrReg, AMFBS_InMicroMips },
10307 { 5462 /* lb */, 2 /* 1 */, MCK_SImmPtr, AMFBS_HasStdEnc_NotInMicroMips },
10308 { 5462 /* lb */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
10309 { 5462 /* lb */, 8 /* 3 */, MCK_PtrReg, AMFBS_HasStdEnc_NotInMicroMips },
10310 { 5465 /* lbe */, 2 /* 1 */, MCK_SImmOffset9_0, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips },
10311 { 5465 /* lbe */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips },
10312 { 5465 /* lbe */, 8 /* 3 */, MCK_PtrReg, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips },
10313 { 5465 /* lbe */, 2 /* 1 */, MCK_AnyOffset, AMFBS_InMicroMips_HasEVA },
10314 { 5465 /* lbe */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasEVA },
10315 { 5465 /* lbe */, 8 /* 3 */, MCK_PtrReg, AMFBS_InMicroMips_HasEVA },
10316 { 5469 /* lbu */, 2 /* 1 */, MCK_SImmOffset16_0, AMFBS_InMicroMips_HasMips32r6 },
10317 { 5469 /* lbu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10318 { 5469 /* lbu */, 8 /* 3 */, MCK_PtrReg, AMFBS_InMicroMips_HasMips32r6 },
10319 { 5469 /* lbu */, 2 /* 1 */, MCK_SImmOffset16_0, AMFBS_InMicroMips },
10320 { 5469 /* lbu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
10321 { 5469 /* lbu */, 8 /* 3 */, MCK_PtrReg, AMFBS_InMicroMips },
10322 { 5469 /* lbu */, 2 /* 1 */, MCK_SImmPtr, AMFBS_HasStdEnc_NotInMicroMips },
10323 { 5469 /* lbu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
10324 { 5469 /* lbu */, 8 /* 3 */, MCK_PtrReg, AMFBS_HasStdEnc_NotInMicroMips },
10325 { 5473 /* lbu16 */, 2 /* 1 */, MCK_UImmOffset4_0Minus1, AMFBS_InMicroMips },
10326 { 5473 /* lbu16 */, 9 /* 0, 3 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips },
10327 { 5479 /* lbue */, 2 /* 1 */, MCK_SImmOffset9_0, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips },
10328 { 5479 /* lbue */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips },
10329 { 5479 /* lbue */, 8 /* 3 */, MCK_PtrReg, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips },
10330 { 5479 /* lbue */, 2 /* 1 */, MCK_AnyOffset, AMFBS_InMicroMips_HasEVA },
10331 { 5479 /* lbue */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasEVA },
10332 { 5479 /* lbue */, 8 /* 3 */, MCK_PtrReg, AMFBS_InMicroMips_HasEVA },
10333 { 5484 /* lbux */, 11 /* 0, 1, 3 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10334 { 5484 /* lbux */, 11 /* 0, 1, 3 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10335 { 5489 /* ld */, 2 /* 1 */, MCK_SImmOffset16_0, AMFBS_HasStdEnc_NotMips3 },
10336 { 5489 /* ld */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips3 },
10337 { 5489 /* ld */, 8 /* 3 */, MCK_PtrReg, AMFBS_HasStdEnc_NotMips3 },
10338 { 5489 /* ld */, 2 /* 1 */, MCK_SImmPtr, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
10339 { 5489 /* ld */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
10340 { 5489 /* ld */, 8 /* 3 */, MCK_PtrReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
10341 { 5492 /* ld.b */, 2 /* 1 */, MCK_SImmOffset10_0, AMFBS_HasStdEnc_HasMSA },
10342 { 5492 /* ld.b */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10343 { 5492 /* ld.b */, 8 /* 3 */, MCK_PtrReg, AMFBS_HasStdEnc_HasMSA },
10344 { 5497 /* ld.d */, 2 /* 1 */, MCK_SImmOffset10_3, AMFBS_HasStdEnc_HasMSA },
10345 { 5497 /* ld.d */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10346 { 5497 /* ld.d */, 8 /* 3 */, MCK_PtrReg, AMFBS_HasStdEnc_HasMSA },
10347 { 5502 /* ld.h */, 2 /* 1 */, MCK_SImmOffset10_1, AMFBS_HasStdEnc_HasMSA },
10348 { 5502 /* ld.h */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10349 { 5502 /* ld.h */, 8 /* 3 */, MCK_PtrReg, AMFBS_HasStdEnc_HasMSA },
10350 { 5507 /* ld.w */, 2 /* 1 */, MCK_SImmOffset10_2, AMFBS_HasStdEnc_HasMSA },
10351 { 5507 /* ld.w */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10352 { 5507 /* ld.w */, 8 /* 3 */, MCK_PtrReg, AMFBS_HasStdEnc_HasMSA },
10353 { 5512 /* ldc1 */, 1 /* 0 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips },
10354 { 5512 /* ldc1 */, 2 /* 1 */, MCK_SImmOffset16_0, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips },
10355 { 5512 /* ldc1 */, 8 /* 3 */, MCK_PtrReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips },
10356 { 5512 /* ldc1 */, 1 /* 0 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat },
10357 { 5512 /* ldc1 */, 2 /* 1 */, MCK_SImmOffset16_0, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat },
10358 { 5512 /* ldc1 */, 8 /* 3 */, MCK_PtrReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat },
10359 { 5512 /* ldc1 */, 2 /* 1 */, MCK_SImmOffset16_0, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips },
10360 { 5512 /* ldc1 */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips },
10361 { 5512 /* ldc1 */, 8 /* 3 */, MCK_PtrReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips },
10362 { 5512 /* ldc1 */, 2 /* 1 */, MCK_SImmOffset16_0, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_HasMips32r6_IsNotSoftFloat },
10363 { 5512 /* ldc1 */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_HasMips32r6_IsNotSoftFloat },
10364 { 5512 /* ldc1 */, 8 /* 3 */, MCK_PtrReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_HasMips32r6_IsNotSoftFloat },
10365 { 5512 /* ldc1 */, 2 /* 1 */, MCK_SImmOffset16_0, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat },
10366 { 5512 /* ldc1 */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat },
10367 { 5512 /* ldc1 */, 8 /* 3 */, MCK_PtrReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat },
10368 { 5517 /* ldc2 */, 2 /* 1 */, MCK_SImmOffset11_0, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
10369 { 5517 /* ldc2 */, 1 /* 0 */, MCK_COP2AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
10370 { 5517 /* ldc2 */, 8 /* 3 */, MCK_PtrReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
10371 { 5517 /* ldc2 */, 2 /* 1 */, MCK_SImmOffset11_0, AMFBS_InMicroMips_HasMips32r6 },
10372 { 5517 /* ldc2 */, 1 /* 0 */, MCK_COP2AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10373 { 5517 /* ldc2 */, 8 /* 3 */, MCK_PtrReg, AMFBS_InMicroMips_HasMips32r6 },
10374 { 5517 /* ldc2 */, 2 /* 1 */, MCK_SImmOffset16_0, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips },
10375 { 5517 /* ldc2 */, 1 /* 0 */, MCK_COP2AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips },
10376 { 5517 /* ldc2 */, 8 /* 3 */, MCK_PtrReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips },
10377 { 5522 /* ldc3 */, 2 /* 1 */, MCK_AnyOffset, AMFBS_HasStdEnc_HasMips2_NotR5900_NotCnMips_NotInMicroMips },
10378 { 5522 /* ldc3 */, 1 /* 0 */, MCK_COP3AsmReg, AMFBS_HasStdEnc_HasMips2_NotR5900_NotCnMips_NotInMicroMips },
10379 { 5522 /* ldc3 */, 8 /* 3 */, MCK_PtrReg, AMFBS_HasStdEnc_HasMips2_NotR5900_NotCnMips_NotInMicroMips },
10380 { 5527 /* ldi.b */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10381 { 5533 /* ldi.d */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10382 { 5539 /* ldi.h */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10383 { 5545 /* ldi.w */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10384 { 5551 /* ldl */, 2 /* 1 */, MCK_AnyOffset, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 },
10385 { 5551 /* ldl */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 },
10386 { 5551 /* ldl */, 8 /* 3 */, MCK_PtrReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 },
10387 { 5555 /* ldpc */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r6 },
10388 { 5560 /* ldr */, 2 /* 1 */, MCK_AnyOffset, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 },
10389 { 5560 /* ldr */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 },
10390 { 5560 /* ldr */, 8 /* 3 */, MCK_PtrReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 },
10391 { 5564 /* ldxc1 */, 1 /* 0 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
10392 { 5564 /* ldxc1 */, 10 /* 1, 3 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
10393 { 5564 /* ldxc1 */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat },
10394 { 5564 /* ldxc1 */, 10 /* 1, 3 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat },
10395 { 5570 /* lh */, 2 /* 1 */, MCK_SImmPtr, AMFBS_HasStdEnc_NotInMicroMips },
10396 { 5570 /* lh */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
10397 { 5570 /* lh */, 8 /* 3 */, MCK_PtrReg, AMFBS_HasStdEnc_NotInMicroMips },
10398 { 5570 /* lh */, 2 /* 1 */, MCK_SImmPtr, AMFBS_InMicroMips },
10399 { 5570 /* lh */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
10400 { 5570 /* lh */, 8 /* 3 */, MCK_PtrReg, AMFBS_InMicroMips },
10401 { 5573 /* lhe */, 2 /* 1 */, MCK_SImmOffset9_0, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips },
10402 { 5573 /* lhe */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips },
10403 { 5573 /* lhe */, 8 /* 3 */, MCK_PtrReg, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips },
10404 { 5573 /* lhe */, 2 /* 1 */, MCK_SImmOffset9_0, AMFBS_InMicroMips_HasEVA },
10405 { 5573 /* lhe */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasEVA },
10406 { 5573 /* lhe */, 8 /* 3 */, MCK_PtrReg, AMFBS_InMicroMips_HasEVA },
10407 { 5577 /* lhu */, 2 /* 1 */, MCK_SImmPtr, AMFBS_HasStdEnc_NotInMicroMips },
10408 { 5577 /* lhu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
10409 { 5577 /* lhu */, 8 /* 3 */, MCK_PtrReg, AMFBS_HasStdEnc_NotInMicroMips },
10410 { 5577 /* lhu */, 2 /* 1 */, MCK_SImmPtr, AMFBS_InMicroMips },
10411 { 5577 /* lhu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
10412 { 5577 /* lhu */, 8 /* 3 */, MCK_PtrReg, AMFBS_InMicroMips },
10413 { 5581 /* lhu16 */, 2 /* 1 */, MCK_UImmOffset4_10, AMFBS_InMicroMips },
10414 { 5581 /* lhu16 */, 9 /* 0, 3 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips },
10415 { 5587 /* lhue */, 2 /* 1 */, MCK_SImmOffset9_0, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips },
10416 { 5587 /* lhue */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips },
10417 { 5587 /* lhue */, 8 /* 3 */, MCK_PtrReg, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips },
10418 { 5587 /* lhue */, 2 /* 1 */, MCK_SImmOffset9_0, AMFBS_InMicroMips_HasEVA },
10419 { 5587 /* lhue */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasEVA },
10420 { 5587 /* lhue */, 8 /* 3 */, MCK_PtrReg, AMFBS_InMicroMips_HasEVA },
10421 { 5592 /* lhx */, 11 /* 0, 1, 3 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10422 { 5592 /* lhx */, 11 /* 0, 1, 3 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10423 { 5596 /* li */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None },
10424 { 5599 /* li.d */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None },
10425 { 5599 /* li.d */, 1 /* 0 */, MCK_StrictlyAFGR64AsmReg, AMFBS_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat },
10426 { 5599 /* li.d */, 1 /* 0 */, MCK_StrictlyFGR64AsmReg, AMFBS_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat },
10427 { 5604 /* li.s */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None },
10428 { 5604 /* li.s */, 1 /* 0 */, MCK_StrictlyFGR32AsmReg, AMFBS_IsNotSoftFloat },
10429 { 5609 /* li16 */, 1 /* 0 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10430 { 5609 /* li16 */, 1 /* 0 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10431 { 5614 /* ll */, 2 /* 1 */, MCK_SImmOffset9_0, AMFBS_InMicroMips_HasMips32r6 },
10432 { 5614 /* ll */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10433 { 5614 /* ll */, 8 /* 3 */, MCK_PtrReg, AMFBS_InMicroMips_HasMips32r6 },
10434 { 5614 /* ll */, 2 /* 1 */, MCK_SImmPtr, AMFBS_HasStdEnc_IsPTR64bit_HasMips64r6_NotInMicroMips },
10435 { 5614 /* ll */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsPTR64bit_HasMips64r6_NotInMicroMips },
10436 { 5614 /* ll */, 8 /* 3 */, MCK_PtrReg, AMFBS_HasStdEnc_IsPTR64bit_HasMips64r6_NotInMicroMips },
10437 { 5614 /* ll */, 2 /* 1 */, MCK_SImmPtr, AMFBS_HasStdEnc_IsPTR32bit_HasMips32r6_NotInMicroMips },
10438 { 5614 /* ll */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsPTR32bit_HasMips32r6_NotInMicroMips },
10439 { 5614 /* ll */, 8 /* 3 */, MCK_PtrReg, AMFBS_HasStdEnc_IsPTR32bit_HasMips32r6_NotInMicroMips },
10440 { 5614 /* ll */, 2 /* 1 */, MCK_AnyOffset, AMFBS_HasStdEnc_IsPTR32bit_HasMips2_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips },
10441 { 5614 /* ll */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsPTR32bit_HasMips2_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips },
10442 { 5614 /* ll */, 8 /* 3 */, MCK_PtrReg, AMFBS_HasStdEnc_IsPTR32bit_HasMips2_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips },
10443 { 5614 /* ll */, 2 /* 1 */, MCK_AnyOffset, AMFBS_HasStdEnc_IsPTR64bit_HasMips2_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips },
10444 { 5614 /* ll */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsPTR64bit_HasMips2_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips },
10445 { 5614 /* ll */, 8 /* 3 */, MCK_PtrReg, AMFBS_HasStdEnc_IsPTR64bit_HasMips2_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips },
10446 { 5614 /* ll */, 2 /* 1 */, MCK_AnyOffset, AMFBS_InMicroMips_NotMips32r6 },
10447 { 5614 /* ll */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10448 { 5614 /* ll */, 8 /* 3 */, MCK_PtrReg, AMFBS_InMicroMips_NotMips32r6 },
10449 { 5617 /* lld */, 2 /* 1 */, MCK_SImmPtr, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips },
10450 { 5617 /* lld */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips },
10451 { 5617 /* lld */, 8 /* 3 */, MCK_PtrReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips },
10452 { 5617 /* lld */, 2 /* 1 */, MCK_SImmPtr, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips },
10453 { 5617 /* lld */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips },
10454 { 5617 /* lld */, 8 /* 3 */, MCK_PtrReg, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips },
10455 { 5621 /* lle */, 2 /* 1 */, MCK_SImmOffset9_0, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips },
10456 { 5621 /* lle */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips },
10457 { 5621 /* lle */, 8 /* 3 */, MCK_PtrReg, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips },
10458 { 5621 /* lle */, 2 /* 1 */, MCK_SImmOffset9_0, AMFBS_InMicroMips_HasEVA },
10459 { 5621 /* lle */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasEVA },
10460 { 5621 /* lle */, 8 /* 3 */, MCK_PtrReg, AMFBS_InMicroMips_HasEVA },
10461 { 5625 /* lsa */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA },
10462 { 5625 /* lsa */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10463 { 5625 /* lsa */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6 },
10464 { 5629 /* lui */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10465 { 5629 /* lui */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
10466 { 5629 /* lui */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10467 { 5633 /* luxc1 */, 1 /* 0 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
10468 { 5633 /* luxc1 */, 10 /* 1, 3 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
10469 { 5633 /* luxc1 */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
10470 { 5633 /* luxc1 */, 10 /* 1, 3 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
10471 { 5633 /* luxc1 */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
10472 { 5633 /* luxc1 */, 10 /* 1, 3 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
10473 { 5639 /* lw */, 2 /* 1 */, MCK_UImmOffset5_20, AMFBS_InMicroMips },
10474 { 5639 /* lw */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
10475 { 5639 /* lw */, 8 /* 3 */, MCK_MemBaseSP, AMFBS_InMicroMips },
10476 { 5639 /* lw */, 2 /* 1 */, MCK_AnyOffset, AMFBS_HasStdEnc_NotInMicroMips },
10477 { 5639 /* lw */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
10478 { 5639 /* lw */, 8 /* 3 */, MCK_PtrReg, AMFBS_HasStdEnc_NotInMicroMips },
10479 { 5639 /* lw */, 2 /* 1 */, MCK_AnyOffset, AMFBS_NotInMips16Mode_HasDSP },
10480 { 5639 /* lw */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_NotInMips16Mode_HasDSP },
10481 { 5639 /* lw */, 8 /* 3 */, MCK_PtrReg, AMFBS_NotInMips16Mode_HasDSP },
10482 { 5639 /* lw */, 2 /* 1 */, MCK_AnyOffset, AMFBS_InMicroMips_HasDSP },
10483 { 5639 /* lw */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10484 { 5639 /* lw */, 8 /* 3 */, MCK_PtrReg, AMFBS_InMicroMips_HasDSP },
10485 { 5639 /* lw */, 2 /* 1 */, MCK_AnyOffset, AMFBS_InMicroMips_HasMips32r6 },
10486 { 5639 /* lw */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10487 { 5639 /* lw */, 8 /* 3 */, MCK_PtrReg, AMFBS_InMicroMips_HasMips32r6 },
10488 { 5639 /* lw */, 2 /* 1 */, MCK_AnyOffset, AMFBS_InMicroMips },
10489 { 5639 /* lw */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
10490 { 5639 /* lw */, 8 /* 3 */, MCK_PtrReg, AMFBS_InMicroMips },
10491 { 5639 /* lw */, 2 /* 1 */, MCK_SImmOffset7_2, AMFBS_InMicroMips },
10492 { 5639 /* lw */, 1 /* 0 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips },
10493 { 5639 /* lw */, 8 /* 3 */, MCK_MemBaseGP, AMFBS_InMicroMips },
10494 { 5642 /* lw16 */, 2 /* 1 */, MCK_UImmOffset4_20, AMFBS_InMicroMips },
10495 { 5642 /* lw16 */, 9 /* 0, 3 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips },
10496 { 5647 /* lwc1 */, 2 /* 1 */, MCK_SImmOffset16_0, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips },
10497 { 5647 /* lwc1 */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips },
10498 { 5647 /* lwc1 */, 8 /* 3 */, MCK_PtrReg, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips },
10499 { 5647 /* lwc1 */, 2 /* 1 */, MCK_SImmOffset16_0, AMFBS_InMicroMips_IsNotSoftFloat },
10500 { 5647 /* lwc1 */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat },
10501 { 5647 /* lwc1 */, 8 /* 3 */, MCK_PtrReg, AMFBS_InMicroMips_IsNotSoftFloat },
10502 { 5652 /* lwc2 */, 2 /* 1 */, MCK_SImmOffset11_0, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
10503 { 5652 /* lwc2 */, 1 /* 0 */, MCK_COP2AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
10504 { 5652 /* lwc2 */, 8 /* 3 */, MCK_PtrReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
10505 { 5652 /* lwc2 */, 2 /* 1 */, MCK_SImmOffset11_0, AMFBS_InMicroMips_HasMips32r6 },
10506 { 5652 /* lwc2 */, 1 /* 0 */, MCK_COP2AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10507 { 5652 /* lwc2 */, 8 /* 3 */, MCK_PtrReg, AMFBS_InMicroMips_HasMips32r6 },
10508 { 5652 /* lwc2 */, 2 /* 1 */, MCK_SImmOffset16_0, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips },
10509 { 5652 /* lwc2 */, 1 /* 0 */, MCK_COP2AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips },
10510 { 5652 /* lwc2 */, 8 /* 3 */, MCK_PtrReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips },
10511 { 5657 /* lwc3 */, 2 /* 1 */, MCK_AnyOffset, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_NotCnMips_NotInMicroMips },
10512 { 5657 /* lwc3 */, 1 /* 0 */, MCK_COP3AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_NotCnMips_NotInMicroMips },
10513 { 5657 /* lwc3 */, 8 /* 3 */, MCK_PtrReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_NotCnMips_NotInMicroMips },
10514 { 5662 /* lwe */, 2 /* 1 */, MCK_SImmOffset9_0, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips },
10515 { 5662 /* lwe */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips },
10516 { 5662 /* lwe */, 8 /* 3 */, MCK_PtrReg, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips },
10517 { 5662 /* lwe */, 2 /* 1 */, MCK_SImmOffset9_0, AMFBS_InMicroMips_HasEVA },
10518 { 5662 /* lwe */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasEVA },
10519 { 5662 /* lwe */, 8 /* 3 */, MCK_PtrReg, AMFBS_InMicroMips_HasEVA },
10520 { 5666 /* lwl */, 2 /* 1 */, MCK_AnyOffset, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips },
10521 { 5666 /* lwl */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips },
10522 { 5666 /* lwl */, 8 /* 3 */, MCK_PtrReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips },
10523 { 5666 /* lwl */, 2 /* 1 */, MCK_AnyOffset, AMFBS_InMicroMips_NotMips32r6 },
10524 { 5666 /* lwl */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10525 { 5666 /* lwl */, 8 /* 3 */, MCK_PtrReg, AMFBS_InMicroMips_NotMips32r6 },
10526 { 5670 /* lwle */, 2 /* 1 */, MCK_SImmOffset9_0, AMFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips },
10527 { 5670 /* lwle */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips },
10528 { 5670 /* lwle */, 8 /* 3 */, MCK_PtrReg, AMFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips },
10529 { 5670 /* lwle */, 2 /* 1 */, MCK_SImmOffset9_0, AMFBS_InMicroMips_NotMips32r6_HasEVA },
10530 { 5670 /* lwle */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6_HasEVA },
10531 { 5670 /* lwle */, 8 /* 3 */, MCK_PtrReg, AMFBS_InMicroMips_NotMips32r6_HasEVA },
10532 { 5675 /* lwm */, 2 /* 1 */, MCK_AnyOffset, AMFBS_InMicroMips },
10533 { 5675 /* lwm */, 8 /* 3 */, MCK_PtrReg, AMFBS_InMicroMips },
10534 { 5675 /* lwm */, 1 /* 0 */, MCK_RegList, AMFBS_InMicroMips },
10535 { 5679 /* lwm16 */, 2 /* 1 */, MCK_UImmOffset4_20, AMFBS_InMicroMips_HasMips32r6 },
10536 { 5679 /* lwm16 */, 8 /* 3 */, MCK_MemBaseSP, AMFBS_InMicroMips_HasMips32r6 },
10537 { 5679 /* lwm16 */, 1 /* 0 */, MCK_RegList16, AMFBS_InMicroMips_HasMips32r6 },
10538 { 5679 /* lwm16 */, 2 /* 1 */, MCK_UImmOffset6_00, AMFBS_InMicroMips_NotMips32r6 },
10539 { 5679 /* lwm16 */, 8 /* 3 */, MCK_MemBaseSP, AMFBS_InMicroMips_NotMips32r6 },
10540 { 5679 /* lwm16 */, 1 /* 0 */, MCK_RegList16, AMFBS_InMicroMips_NotMips32r6 },
10541 { 5685 /* lwm32 */, 2 /* 1 */, MCK_AnyOffset, AMFBS_InMicroMips },
10542 { 5685 /* lwm32 */, 8 /* 3 */, MCK_PtrReg, AMFBS_InMicroMips },
10543 { 5685 /* lwm32 */, 1 /* 0 */, MCK_RegList, AMFBS_InMicroMips },
10544 { 5691 /* lwp */, 2 /* 1 */, MCK_SImmOffset12_0, AMFBS_InMicroMips },
10545 { 5691 /* lwp */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
10546 { 5691 /* lwp */, 8 /* 3 */, MCK_PtrReg, AMFBS_InMicroMips },
10547 { 5695 /* lwpc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6 },
10548 { 5695 /* lwpc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10549 { 5700 /* lwr */, 2 /* 1 */, MCK_AnyOffset, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips },
10550 { 5700 /* lwr */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips },
10551 { 5700 /* lwr */, 8 /* 3 */, MCK_PtrReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips },
10552 { 5700 /* lwr */, 2 /* 1 */, MCK_AnyOffset, AMFBS_InMicroMips_NotMips32r6 },
10553 { 5700 /* lwr */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10554 { 5700 /* lwr */, 8 /* 3 */, MCK_PtrReg, AMFBS_InMicroMips_NotMips32r6 },
10555 { 5704 /* lwre */, 2 /* 1 */, MCK_SImmOffset9_0, AMFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips },
10556 { 5704 /* lwre */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips },
10557 { 5704 /* lwre */, 8 /* 3 */, MCK_PtrReg, AMFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips },
10558 { 5704 /* lwre */, 2 /* 1 */, MCK_SImmOffset9_0, AMFBS_InMicroMips_NotMips32r6_HasEVA },
10559 { 5704 /* lwre */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6_HasEVA },
10560 { 5704 /* lwre */, 8 /* 3 */, MCK_PtrReg, AMFBS_InMicroMips_NotMips32r6_HasEVA },
10561 { 5709 /* lwu */, 2 /* 1 */, MCK_SImmOffset12_0, AMFBS_InMicroMips_NotMips32r6 },
10562 { 5709 /* lwu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10563 { 5709 /* lwu */, 8 /* 3 */, MCK_PtrReg, AMFBS_InMicroMips_NotMips32r6 },
10564 { 5709 /* lwu */, 2 /* 1 */, MCK_AnyOffset, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
10565 { 5709 /* lwu */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
10566 { 5709 /* lwu */, 8 /* 3 */, MCK_PtrReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
10567 { 5713 /* lwupc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips64r6 },
10568 { 5719 /* lwx */, 11 /* 0, 1, 3 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10569 { 5719 /* lwx */, 11 /* 0, 1, 3 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10570 { 5723 /* lwxc1 */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat },
10571 { 5723 /* lwxc1 */, 10 /* 1, 3 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat },
10572 { 5723 /* lwxc1 */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
10573 { 5723 /* lwxc1 */, 10 /* 1, 3 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
10574 { 5729 /* lwxs */, 11 /* 0, 1, 3 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
10575 { 5734 /* madd */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips },
10576 { 5734 /* madd */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10577 { 5734 /* madd */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
10578 { 5734 /* madd */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10579 { 5734 /* madd */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
10580 { 5734 /* madd */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10581 { 5739 /* madd.d */, 15 /* 0, 1, 2, 3 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4 },
10582 { 5739 /* madd.d */, 15 /* 0, 1, 2, 3 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat_HasMadd4 },
10583 { 5739 /* madd.d */, 15 /* 0, 1, 2, 3 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4 },
10584 { 5746 /* madd.s */, 15 /* 0, 1, 2, 3 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4 },
10585 { 5746 /* madd.s */, 15 /* 0, 1, 2, 3 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat_HasMadd4 },
10586 { 5753 /* madd_q.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10587 { 5762 /* madd_q.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10588 { 5771 /* maddf.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
10589 { 5771 /* maddf.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
10590 { 5779 /* maddf.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
10591 { 5779 /* maddf.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
10592 { 5787 /* maddr_q.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10593 { 5797 /* maddr_q.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10594 { 5807 /* maddu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips },
10595 { 5807 /* maddu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10596 { 5807 /* maddu */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
10597 { 5807 /* maddu */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10598 { 5807 /* maddu */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
10599 { 5807 /* maddu */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10600 { 5813 /* maddv.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10601 { 5821 /* maddv.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10602 { 5829 /* maddv.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10603 { 5837 /* maddv.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10604 { 5845 /* maq_s.w.phl */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
10605 { 5845 /* maq_s.w.phl */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10606 { 5845 /* maq_s.w.phl */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
10607 { 5845 /* maq_s.w.phl */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10608 { 5857 /* maq_s.w.phr */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
10609 { 5857 /* maq_s.w.phr */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10610 { 5857 /* maq_s.w.phr */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
10611 { 5857 /* maq_s.w.phr */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10612 { 5869 /* maq_sa.w.phl */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
10613 { 5869 /* maq_sa.w.phl */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10614 { 5869 /* maq_sa.w.phl */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
10615 { 5869 /* maq_sa.w.phl */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10616 { 5882 /* maq_sa.w.phr */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
10617 { 5882 /* maq_sa.w.phr */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10618 { 5882 /* maq_sa.w.phr */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
10619 { 5882 /* maq_sa.w.phr */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10620 { 5895 /* max.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
10621 { 5895 /* max.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
10622 { 5901 /* max.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
10623 { 5901 /* max.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
10624 { 5907 /* max_a.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10625 { 5915 /* max_a.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10626 { 5923 /* max_a.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10627 { 5931 /* max_a.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10628 { 5939 /* max_s.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10629 { 5947 /* max_s.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10630 { 5955 /* max_s.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10631 { 5963 /* max_s.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10632 { 5971 /* max_u.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10633 { 5979 /* max_u.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10634 { 5987 /* max_u.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10635 { 5995 /* max_u.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10636 { 6003 /* maxa.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
10637 { 6003 /* maxa.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
10638 { 6010 /* maxa.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
10639 { 6010 /* maxa.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
10640 { 6017 /* maxi_s.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10641 { 6026 /* maxi_s.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10642 { 6035 /* maxi_s.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10643 { 6044 /* maxi_s.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10644 { 6053 /* maxi_u.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10645 { 6062 /* maxi_u.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10646 { 6071 /* maxi_u.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10647 { 6080 /* maxi_u.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10648 { 6089 /* mfc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
10649 { 6089 /* mfc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
10650 { 6089 /* mfc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10651 { 6089 /* mfc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10652 { 6089 /* mfc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10653 { 6089 /* mfc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10654 { 6089 /* mfc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
10655 { 6089 /* mfc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
10656 { 6089 /* mfc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10657 { 6089 /* mfc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10658 { 6089 /* mfc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10659 { 6089 /* mfc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10660 { 6094 /* mfc1 */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips },
10661 { 6094 /* mfc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips },
10662 { 6094 /* mfc1 */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
10663 { 6094 /* mfc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
10664 { 6094 /* mfc1 */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat },
10665 { 6094 /* mfc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat },
10666 { 6094 /* mfc1 */, 2 /* 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips },
10667 { 6094 /* mfc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips },
10668 { 6099 /* mfc2 */, 2 /* 1 */, MCK_COP2AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10669 { 6099 /* mfc2 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10670 { 6099 /* mfc2 */, 2 /* 1 */, MCK_COP2AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
10671 { 6099 /* mfc2 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
10672 { 6099 /* mfc2 */, 2 /* 1 */, MCK_COP2AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
10673 { 6099 /* mfc2 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
10674 { 6104 /* mfgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips },
10675 { 6104 /* mfgc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips },
10676 { 6104 /* mfgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_InMicroMips_HasMips32r5_HasVirt },
10677 { 6104 /* mfgc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r5_HasVirt },
10678 { 6104 /* mfgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips },
10679 { 6104 /* mfgc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips },
10680 { 6104 /* mfgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_InMicroMips_HasMips32r5_HasVirt },
10681 { 6104 /* mfgc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r5_HasVirt },
10682 { 6110 /* mfhc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10683 { 6110 /* mfhc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10684 { 6110 /* mfhc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10685 { 6110 /* mfhc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10686 { 6116 /* mfhc1 */, 2 /* 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips32r2_IsNotSoftFloat_NotInMicroMips },
10687 { 6116 /* mfhc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips32r2_IsNotSoftFloat_NotInMicroMips },
10688 { 6116 /* mfhc1 */, 2 /* 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat },
10689 { 6116 /* mfhc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat },
10690 { 6116 /* mfhc1 */, 2 /* 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips32r2_IsNotSoftFloat_NotInMicroMips },
10691 { 6116 /* mfhc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips32r2_IsNotSoftFloat_NotInMicroMips },
10692 { 6116 /* mfhc1 */, 2 /* 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat },
10693 { 6116 /* mfhc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat },
10694 { 6122 /* mfhc2 */, 2 /* 1 */, MCK_COP2AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10695 { 6122 /* mfhc2 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10696 { 6128 /* mfhgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips },
10697 { 6128 /* mfhgc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips },
10698 { 6128 /* mfhgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_InMicroMips_HasMips32r5_HasVirt },
10699 { 6128 /* mfhgc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r5_HasVirt },
10700 { 6128 /* mfhgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips },
10701 { 6128 /* mfhgc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips },
10702 { 6128 /* mfhgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_InMicroMips_HasMips32r5_HasVirt },
10703 { 6128 /* mfhgc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r5_HasVirt },
10704 { 6135 /* mfhi */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips },
10705 { 6135 /* mfhi */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10706 { 6135 /* mfhi */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
10707 { 6135 /* mfhi */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10708 { 6135 /* mfhi */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
10709 { 6135 /* mfhi */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10710 { 6140 /* mfhi16 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10711 { 6147 /* mflo */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips },
10712 { 6147 /* mflo */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10713 { 6147 /* mflo */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
10714 { 6147 /* mflo */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10715 { 6147 /* mflo */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
10716 { 6147 /* mflo */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10717 { 6152 /* mflo16 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10718 { 6159 /* mftacx */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT_NotInMicroMips },
10719 { 6159 /* mftacx */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasMT },
10720 { 6159 /* mftacx */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT },
10721 { 6166 /* mftc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasMT_NotInMicroMips },
10722 { 6166 /* mftc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT_NotInMicroMips },
10723 { 6166 /* mftc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasMT },
10724 { 6166 /* mftc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT },
10725 { 6172 /* mftc1 */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_HasMT },
10726 { 6172 /* mftc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT },
10727 { 6178 /* mftdsp */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT },
10728 { 6185 /* mftgpr */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasMT },
10729 { 6192 /* mfthc1 */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_HasMT },
10730 { 6192 /* mfthc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT },
10731 { 6199 /* mfthi */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT_NotInMicroMips },
10732 { 6199 /* mfthi */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasMT },
10733 { 6199 /* mfthi */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT },
10734 { 6205 /* mftlo */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT_NotInMicroMips },
10735 { 6205 /* mftlo */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasMT },
10736 { 6205 /* mftlo */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT },
10737 { 6211 /* mftr */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMT_NotInMicroMips },
10738 { 6216 /* min.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
10739 { 6216 /* min.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
10740 { 6222 /* min.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
10741 { 6222 /* min.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
10742 { 6228 /* min_a.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10743 { 6236 /* min_a.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10744 { 6244 /* min_a.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10745 { 6252 /* min_a.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10746 { 6260 /* min_s.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10747 { 6268 /* min_s.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10748 { 6276 /* min_s.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10749 { 6284 /* min_s.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10750 { 6292 /* min_u.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10751 { 6300 /* min_u.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10752 { 6308 /* min_u.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10753 { 6316 /* min_u.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10754 { 6324 /* mina.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
10755 { 6324 /* mina.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
10756 { 6331 /* mina.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
10757 { 6331 /* mina.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
10758 { 6338 /* mini_s.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10759 { 6347 /* mini_s.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10760 { 6356 /* mini_s.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10761 { 6365 /* mini_s.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10762 { 6374 /* mini_u.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10763 { 6383 /* mini_u.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10764 { 6392 /* mini_u.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10765 { 6401 /* mini_u.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10766 { 6410 /* mod */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
10767 { 6410 /* mod */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10768 { 6414 /* mod_s.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10769 { 6422 /* mod_s.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10770 { 6430 /* mod_s.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10771 { 6438 /* mod_s.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10772 { 6446 /* mod_u.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10773 { 6454 /* mod_u.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10774 { 6462 /* mod_u.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10775 { 6470 /* mod_u.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10776 { 6478 /* modsub */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10777 { 6478 /* modsub */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10778 { 6485 /* modu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
10779 { 6485 /* modu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10780 { 6490 /* mov.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips },
10781 { 6490 /* mov.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat },
10782 { 6490 /* mov.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips },
10783 { 6490 /* mov.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat },
10784 { 6490 /* mov.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
10785 { 6496 /* mov.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips },
10786 { 6496 /* mov.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
10787 { 6496 /* mov.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat },
10788 { 6502 /* move */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips },
10789 { 6502 /* move */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips },
10790 { 6502 /* move */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10791 { 6502 /* move */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_IsGP64bit_NotInMicroMips },
10792 { 6502 /* move */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_IsGP64bit_NotInMicroMips },
10793 { 6507 /* move.v */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10794 { 6514 /* move16 */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10795 { 6521 /* movep */, 12 /* 2, 3 */, MCK_GPRMM16AsmRegMoveP, AMFBS_InMicroMips_NotMips32r6 },
10796 { 6521 /* movep */, 1 /* 0 */, MCK_GPRMM16AsmRegMovePPairFirst, AMFBS_InMicroMips_NotMips32r6 },
10797 { 6521 /* movep */, 2 /* 1 */, MCK_GPRMM16AsmRegMovePPairSecond, AMFBS_InMicroMips_NotMips32r6 },
10798 { 6521 /* movep */, 12 /* 2, 3 */, MCK_GPRMM16AsmRegMoveP, AMFBS_InMicroMips_HasMips32r6 },
10799 { 6521 /* movep */, 1 /* 0 */, MCK_GPRMM16AsmRegMovePPairFirst, AMFBS_InMicroMips_HasMips32r6 },
10800 { 6521 /* movep */, 2 /* 1 */, MCK_GPRMM16AsmRegMovePPairSecond, AMFBS_InMicroMips_HasMips32r6 },
10801 { 6527 /* movf */, 4 /* 2 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
10802 { 6527 /* movf */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
10803 { 6527 /* movf */, 4 /* 2 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
10804 { 6527 /* movf */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
10805 { 6532 /* movf.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
10806 { 6532 /* movf.d */, 4 /* 2 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
10807 { 6532 /* movf.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
10808 { 6532 /* movf.d */, 4 /* 2 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
10809 { 6532 /* movf.d */, 4 /* 2 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
10810 { 6532 /* movf.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
10811 { 6539 /* movf.s */, 4 /* 2 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
10812 { 6539 /* movf.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
10813 { 6539 /* movf.s */, 4 /* 2 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
10814 { 6539 /* movf.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
10815 { 6546 /* movn */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips },
10816 { 6546 /* movn */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10817 { 6551 /* movn.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
10818 { 6551 /* movn.d */, 4 /* 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
10819 { 6551 /* movn.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
10820 { 6551 /* movn.d */, 4 /* 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
10821 { 6551 /* movn.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
10822 { 6551 /* movn.d */, 4 /* 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
10823 { 6558 /* movn.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
10824 { 6558 /* movn.s */, 4 /* 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
10825 { 6558 /* movn.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
10826 { 6558 /* movn.s */, 4 /* 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
10827 { 6565 /* movt */, 4 /* 2 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
10828 { 6565 /* movt */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
10829 { 6565 /* movt */, 4 /* 2 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
10830 { 6565 /* movt */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
10831 { 6570 /* movt.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
10832 { 6570 /* movt.d */, 4 /* 2 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
10833 { 6570 /* movt.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
10834 { 6570 /* movt.d */, 4 /* 2 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
10835 { 6570 /* movt.d */, 4 /* 2 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
10836 { 6570 /* movt.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
10837 { 6577 /* movt.s */, 4 /* 2 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
10838 { 6577 /* movt.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
10839 { 6577 /* movt.s */, 4 /* 2 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
10840 { 6577 /* movt.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
10841 { 6584 /* movz */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips },
10842 { 6584 /* movz */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10843 { 6589 /* movz.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
10844 { 6589 /* movz.d */, 4 /* 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
10845 { 6589 /* movz.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
10846 { 6589 /* movz.d */, 4 /* 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
10847 { 6589 /* movz.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
10848 { 6589 /* movz.d */, 4 /* 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
10849 { 6596 /* movz.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
10850 { 6596 /* movz.s */, 4 /* 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
10851 { 6596 /* movz.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
10852 { 6596 /* movz.s */, 4 /* 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
10853 { 6603 /* msub */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips },
10854 { 6603 /* msub */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10855 { 6603 /* msub */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
10856 { 6603 /* msub */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10857 { 6603 /* msub */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
10858 { 6603 /* msub */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10859 { 6608 /* msub.d */, 15 /* 0, 1, 2, 3 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4 },
10860 { 6608 /* msub.d */, 15 /* 0, 1, 2, 3 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat_HasMadd4 },
10861 { 6608 /* msub.d */, 15 /* 0, 1, 2, 3 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4 },
10862 { 6615 /* msub.s */, 15 /* 0, 1, 2, 3 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4 },
10863 { 6615 /* msub.s */, 15 /* 0, 1, 2, 3 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat_HasMadd4 },
10864 { 6622 /* msub_q.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10865 { 6631 /* msub_q.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10866 { 6640 /* msubf.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
10867 { 6640 /* msubf.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
10868 { 6648 /* msubf.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
10869 { 6648 /* msubf.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
10870 { 6656 /* msubr_q.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10871 { 6666 /* msubr_q.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10872 { 6676 /* msubu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips },
10873 { 6676 /* msubu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10874 { 6676 /* msubu */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
10875 { 6676 /* msubu */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10876 { 6676 /* msubu */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
10877 { 6676 /* msubu */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10878 { 6682 /* msubv.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10879 { 6690 /* msubv.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10880 { 6698 /* msubv.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10881 { 6706 /* msubv.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10882 { 6714 /* mtc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
10883 { 6714 /* mtc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
10884 { 6714 /* mtc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10885 { 6714 /* mtc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10886 { 6714 /* mtc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10887 { 6714 /* mtc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10888 { 6714 /* mtc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
10889 { 6714 /* mtc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
10890 { 6714 /* mtc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10891 { 6714 /* mtc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10892 { 6714 /* mtc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10893 { 6714 /* mtc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10894 { 6719 /* mtc1 */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips },
10895 { 6719 /* mtc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips },
10896 { 6719 /* mtc1 */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
10897 { 6719 /* mtc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
10898 { 6719 /* mtc1 */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat },
10899 { 6719 /* mtc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat },
10900 { 6719 /* mtc1 */, 2 /* 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips },
10901 { 6719 /* mtc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips },
10902 { 6719 /* mtc1 */, 2 /* 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat },
10903 { 6719 /* mtc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat },
10904 { 6724 /* mtc2 */, 2 /* 1 */, MCK_COP2AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10905 { 6724 /* mtc2 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10906 { 6724 /* mtc2 */, 2 /* 1 */, MCK_COP2AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
10907 { 6724 /* mtc2 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
10908 { 6724 /* mtc2 */, 2 /* 1 */, MCK_COP2AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
10909 { 6724 /* mtc2 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
10910 { 6729 /* mtgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips },
10911 { 6729 /* mtgc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips },
10912 { 6729 /* mtgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_InMicroMips_HasMips32r5_HasVirt },
10913 { 6729 /* mtgc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r5_HasVirt },
10914 { 6729 /* mtgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips },
10915 { 6729 /* mtgc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips },
10916 { 6729 /* mtgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_InMicroMips_HasMips32r5_HasVirt },
10917 { 6729 /* mtgc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r5_HasVirt },
10918 { 6735 /* mthc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10919 { 6735 /* mthc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10920 { 6735 /* mthc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10921 { 6735 /* mthc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10922 { 6741 /* mthc1 */, 2 /* 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips32r2_IsNotSoftFloat_NotInMicroMips },
10923 { 6741 /* mthc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips32r2_IsNotSoftFloat_NotInMicroMips },
10924 { 6741 /* mthc1 */, 2 /* 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat },
10925 { 6741 /* mthc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat },
10926 { 6741 /* mthc1 */, 2 /* 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips32r2_IsNotSoftFloat_NotInMicroMips },
10927 { 6741 /* mthc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips32r2_IsNotSoftFloat_NotInMicroMips },
10928 { 6741 /* mthc1 */, 2 /* 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat },
10929 { 6741 /* mthc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat },
10930 { 6747 /* mthc2 */, 2 /* 1 */, MCK_COP2AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10931 { 6747 /* mthc2 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10932 { 6753 /* mthgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips },
10933 { 6753 /* mthgc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips },
10934 { 6753 /* mthgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_InMicroMips_HasMips32r5_HasVirt },
10935 { 6753 /* mthgc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r5_HasVirt },
10936 { 6753 /* mthgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips },
10937 { 6753 /* mthgc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips },
10938 { 6753 /* mthgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_InMicroMips_HasMips32r5_HasVirt },
10939 { 6753 /* mthgc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r5_HasVirt },
10940 { 6760 /* mthi */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips },
10941 { 6760 /* mthi */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10942 { 6760 /* mthi */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10943 { 6760 /* mthi */, 2 /* 1 */, MCK_HI32DSPAsmReg, AMFBS_InMicroMips_HasDSP },
10944 { 6760 /* mthi */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10945 { 6760 /* mthi */, 2 /* 1 */, MCK_HI32DSPAsmReg, AMFBS_HasDSP },
10946 { 6765 /* mthlip */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
10947 { 6765 /* mthlip */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10948 { 6765 /* mthlip */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
10949 { 6765 /* mthlip */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10950 { 6772 /* mtlo */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips },
10951 { 6772 /* mtlo */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10952 { 6772 /* mtlo */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10953 { 6772 /* mtlo */, 2 /* 1 */, MCK_LO32DSPAsmReg, AMFBS_InMicroMips_HasDSP },
10954 { 6772 /* mtlo */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10955 { 6772 /* mtlo */, 2 /* 1 */, MCK_LO32DSPAsmReg, AMFBS_HasDSP },
10956 { 6777 /* mtm0 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasCnMips },
10957 { 6782 /* mtm1 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasCnMips },
10958 { 6787 /* mtm2 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasCnMips },
10959 { 6792 /* mtp0 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasCnMips },
10960 { 6797 /* mtp1 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasCnMips },
10961 { 6802 /* mtp2 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasCnMips },
10962 { 6807 /* mttacx */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT_NotInMicroMips },
10963 { 6807 /* mttacx */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasMT },
10964 { 6807 /* mttacx */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT },
10965 { 6814 /* mttc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasMT_NotInMicroMips },
10966 { 6814 /* mttc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT_NotInMicroMips },
10967 { 6814 /* mttc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasMT },
10968 { 6814 /* mttc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT },
10969 { 6820 /* mttc1 */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_HasMT },
10970 { 6820 /* mttc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT },
10971 { 6826 /* mttdsp */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT },
10972 { 6833 /* mttgpr */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasMT },
10973 { 6840 /* mtthc1 */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_HasMT },
10974 { 6840 /* mtthc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT },
10975 { 6847 /* mtthi */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT_NotInMicroMips },
10976 { 6847 /* mtthi */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasMT },
10977 { 6847 /* mtthi */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT },
10978 { 6853 /* mttlo */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT_NotInMicroMips },
10979 { 6853 /* mttlo */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasMT },
10980 { 6853 /* mttlo */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT },
10981 { 6859 /* mttr */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMT_NotInMicroMips },
10982 { 6864 /* muh */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10983 { 6864 /* muh */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
10984 { 6864 /* muh */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10985 { 6868 /* muhu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10986 { 6868 /* muhu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
10987 { 6868 /* muhu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10988 { 6873 /* mul */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips },
10989 { 6873 /* mul */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10990 { 6873 /* mul */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10991 { 6873 /* mul */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips },
10992 { 6873 /* mul */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
10993 { 6873 /* mul */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10994 { 6873 /* mul */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10995 { 6873 /* mul */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 },
10996 { 6877 /* mul.d */, 7 /* 0, 1, 2 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips },
10997 { 6877 /* mul.d */, 7 /* 0, 1, 2 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat },
10998 { 6877 /* mul.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips },
10999 { 6877 /* mul.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat },
11000 { 6883 /* mul.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
11001 { 6883 /* mul.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
11002 { 6890 /* mul.ps */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
11003 { 6897 /* mul.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips },
11004 { 6897 /* mul.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
11005 { 6897 /* mul.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat },
11006 { 6903 /* mul_q.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11007 { 6911 /* mul_q.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11008 { 6919 /* mul_s.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
11009 { 6919 /* mul_s.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
11010 { 6928 /* muleq_s.w.phl */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11011 { 6928 /* muleq_s.w.phl */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
11012 { 6942 /* muleq_s.w.phr */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11013 { 6942 /* muleq_s.w.phr */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
11014 { 6956 /* muleu_s.ph.qbl */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11015 { 6956 /* muleu_s.ph.qbl */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
11016 { 6971 /* muleu_s.ph.qbr */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11017 { 6971 /* muleu_s.ph.qbr */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
11018 { 6986 /* mulo */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 },
11019 { 6986 /* mulo */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 },
11020 { 6991 /* mulou */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 },
11021 { 6991 /* mulou */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 },
11022 { 6997 /* mulq_rs.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11023 { 6997 /* mulq_rs.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
11024 { 7008 /* mulq_rs.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
11025 { 7008 /* mulq_rs.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
11026 { 7018 /* mulq_s.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
11027 { 7018 /* mulq_s.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
11028 { 7028 /* mulq_s.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
11029 { 7028 /* mulq_s.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
11030 { 7037 /* mulr.ps */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMips3D },
11031 { 7045 /* mulr_q.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11032 { 7054 /* mulr_q.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11033 { 7063 /* mulsa.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSPR2 },
11034 { 7063 /* mulsa.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
11035 { 7063 /* mulsa.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSPR2 },
11036 { 7063 /* mulsa.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
11037 { 7074 /* mulsaq_s.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
11038 { 7074 /* mulsaq_s.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11039 { 7074 /* mulsaq_s.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
11040 { 7074 /* mulsaq_s.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
11041 { 7088 /* mult */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips },
11042 { 7088 /* mult */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
11043 { 7088 /* mult */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
11044 { 7088 /* mult */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11045 { 7088 /* mult */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
11046 { 7088 /* mult */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
11047 { 7093 /* multu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips },
11048 { 7093 /* multu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
11049 { 7093 /* multu */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
11050 { 7093 /* multu */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11051 { 7093 /* multu */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
11052 { 7093 /* multu */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
11053 { 7099 /* mulu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11054 { 7099 /* mulu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
11055 { 7099 /* mulu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11056 { 7104 /* mulv.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11057 { 7111 /* mulv.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11058 { 7118 /* mulv.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11059 { 7125 /* mulv.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11060 { 7136 /* neg */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
11061 { 7136 /* neg */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
11062 { 7136 /* neg */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11063 { 7136 /* neg */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
11064 { 7136 /* neg */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
11065 { 7136 /* neg */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11066 { 7140 /* neg.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips },
11067 { 7140 /* neg.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat },
11068 { 7140 /* neg.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips },
11069 { 7140 /* neg.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat },
11070 { 7146 /* neg.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
11071 { 7146 /* neg.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsNotSoftFloat },
11072 { 7146 /* neg.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat },
11073 { 7152 /* negu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
11074 { 7152 /* negu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
11075 { 7152 /* negu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11076 { 7152 /* negu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
11077 { 7152 /* negu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
11078 { 7152 /* negu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11079 { 7157 /* nloc.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11080 { 7164 /* nloc.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11081 { 7171 /* nloc.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11082 { 7178 /* nloc.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11083 { 7185 /* nlzc.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11084 { 7192 /* nlzc.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11085 { 7199 /* nlzc.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11086 { 7206 /* nlzc.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11087 { 7213 /* nmadd.d */, 15 /* 0, 1, 2, 3 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips },
11088 { 7213 /* nmadd.d */, 15 /* 0, 1, 2, 3 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat_HasMadd4 },
11089 { 7213 /* nmadd.d */, 15 /* 0, 1, 2, 3 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips },
11090 { 7221 /* nmadd.s */, 15 /* 0, 1, 2, 3 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips },
11091 { 7221 /* nmadd.s */, 15 /* 0, 1, 2, 3 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat_HasMadd4 },
11092 { 7229 /* nmsub.d */, 15 /* 0, 1, 2, 3 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips },
11093 { 7229 /* nmsub.d */, 15 /* 0, 1, 2, 3 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat_HasMadd4 },
11094 { 7229 /* nmsub.d */, 15 /* 0, 1, 2, 3 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips },
11095 { 7237 /* nmsub.s */, 15 /* 0, 1, 2, 3 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips },
11096 { 7237 /* nmsub.s */, 15 /* 0, 1, 2, 3 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat_HasMadd4 },
11097 { 7249 /* nor */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_IsGP32bit },
11098 { 7249 /* nor */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_IsGP64bit },
11099 { 7249 /* nor */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
11100 { 7249 /* nor */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
11101 { 7249 /* nor */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11102 { 7249 /* nor */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_IsGP32bit },
11103 { 7249 /* nor */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_IsGP64bit },
11104 { 7253 /* nor.v */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11105 { 7259 /* nori.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11106 { 7266 /* not */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
11107 { 7266 /* not */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
11108 { 7266 /* not */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11109 { 7266 /* not */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
11110 { 7266 /* not */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
11111 { 7266 /* not */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11112 { 7270 /* not16 */, 3 /* 0, 1 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_NotMips32r6 },
11113 { 7270 /* not16 */, 3 /* 0, 1 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11114 { 7276 /* or */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
11115 { 7276 /* or */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
11116 { 7276 /* or */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11117 { 7276 /* or */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11118 { 7276 /* or */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips },
11119 { 7276 /* or */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11120 { 7276 /* or */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips3_NotInMicroMips },
11121 { 7276 /* or */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
11122 { 7276 /* or */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
11123 { 7276 /* or */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11124 { 7276 /* or */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11125 { 7276 /* or */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips },
11126 { 7276 /* or */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11127 { 7276 /* or */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips3_NotInMicroMips },
11128 { 7279 /* or.v */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11129 { 7284 /* or16 */, 3 /* 0, 1 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_NotMips32r6 },
11130 { 7284 /* or16 */, 3 /* 0, 1 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11131 { 7289 /* ori */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11132 { 7289 /* ori */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
11133 { 7289 /* ori */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
11134 { 7289 /* ori */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11135 { 7289 /* ori */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
11136 { 7289 /* ori */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
11137 { 7293 /* ori.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11138 { 7299 /* packrl.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11139 { 7299 /* packrl.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
11140 { 7315 /* pckev.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11141 { 7323 /* pckev.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11142 { 7331 /* pckev.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11143 { 7339 /* pckev.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11144 { 7347 /* pckod.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11145 { 7355 /* pckod.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11146 { 7363 /* pckod.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11147 { 7371 /* pckod.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11148 { 7379 /* pcnt.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11149 { 7386 /* pcnt.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11150 { 7393 /* pcnt.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11151 { 7400 /* pcnt.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11152 { 7407 /* pick.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11153 { 7407 /* pick.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
11154 { 7415 /* pick.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11155 { 7415 /* pick.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
11156 { 7423 /* pll.ps */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
11157 { 7430 /* plu.ps */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
11158 { 7437 /* pop */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasCnMips },
11159 { 7437 /* pop */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasCnMips },
11160 { 7441 /* preceq.w.phl */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11161 { 7441 /* preceq.w.phl */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
11162 { 7454 /* preceq.w.phr */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11163 { 7454 /* preceq.w.phr */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
11164 { 7467 /* precequ.ph.qbl */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11165 { 7467 /* precequ.ph.qbl */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
11166 { 7482 /* precequ.ph.qbla */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11167 { 7482 /* precequ.ph.qbla */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
11168 { 7498 /* precequ.ph.qbr */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11169 { 7498 /* precequ.ph.qbr */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
11170 { 7513 /* precequ.ph.qbra */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11171 { 7513 /* precequ.ph.qbra */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
11172 { 7529 /* preceu.ph.qbl */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11173 { 7529 /* preceu.ph.qbl */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
11174 { 7543 /* preceu.ph.qbla */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11175 { 7543 /* preceu.ph.qbla */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
11176 { 7558 /* preceu.ph.qbr */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11177 { 7558 /* preceu.ph.qbr */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
11178 { 7572 /* preceu.ph.qbra */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11179 { 7572 /* preceu.ph.qbra */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
11180 { 7587 /* precr.qb.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
11181 { 7587 /* precr.qb.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
11182 { 7599 /* precr_sra.ph.w */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
11183 { 7599 /* precr_sra.ph.w */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
11184 { 7614 /* precr_sra_r.ph.w */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
11185 { 7614 /* precr_sra_r.ph.w */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
11186 { 7631 /* precrq.ph.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11187 { 7631 /* precrq.ph.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
11188 { 7643 /* precrq.qb.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11189 { 7643 /* precrq.qb.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
11190 { 7656 /* precrq_rs.ph.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11191 { 7656 /* precrq_rs.ph.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
11192 { 7671 /* precrqu_s.qb.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11193 { 7671 /* precrqu_s.qb.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
11194 { 7687 /* pref */, 2 /* 1 */, MCK_SImmOffset9_0, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
11195 { 7687 /* pref */, 8 /* 3 */, MCK_PtrReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
11196 { 7687 /* pref */, 2 /* 1 */, MCK_SImmPtr, AMFBS_HasStdEnc_HasMips3_32_NotMips32r6_NotMips64r6_NotInMicroMips },
11197 { 7687 /* pref */, 8 /* 3 */, MCK_PtrReg, AMFBS_HasStdEnc_HasMips3_32_NotMips32r6_NotMips64r6_NotInMicroMips },
11198 { 7687 /* pref */, 2 /* 1 */, MCK_AnyOffset, AMFBS_InMicroMips_NotMips32r6 },
11199 { 7687 /* pref */, 8 /* 3 */, MCK_PtrReg, AMFBS_InMicroMips_NotMips32r6 },
11200 { 7687 /* pref */, 2 /* 1 */, MCK_AnyOffset, AMFBS_InMicroMips_HasMips32r6 },
11201 { 7687 /* pref */, 8 /* 3 */, MCK_PtrReg, AMFBS_InMicroMips_HasMips32r6 },
11202 { 7692 /* prefe */, 2 /* 1 */, MCK_SImmOffset9_0, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips },
11203 { 7692 /* prefe */, 8 /* 3 */, MCK_PtrReg, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips },
11204 { 7692 /* prefe */, 2 /* 1 */, MCK_SImmOffset9_0, AMFBS_InMicroMips_HasEVA },
11205 { 7692 /* prefe */, 8 /* 3 */, MCK_PtrReg, AMFBS_InMicroMips_HasEVA },
11206 { 7698 /* prefx */, 10 /* 1, 3 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
11207 { 7704 /* prepend */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
11208 { 7704 /* prepend */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
11209 { 7712 /* pul.ps */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
11210 { 7719 /* puu.ps */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
11211 { 7726 /* raddu.w.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11212 { 7726 /* raddu.w.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
11213 { 7737 /* rddsp */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11214 { 7737 /* rddsp */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
11215 { 7743 /* rdhwr */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
11216 { 7743 /* rdhwr */, 2 /* 1 */, MCK_HWRegsAsmReg, AMFBS_HasStdEnc_NotInMicroMips },
11217 { 7743 /* rdhwr */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
11218 { 7743 /* rdhwr */, 2 /* 1 */, MCK_HWRegsAsmReg, AMFBS_InMicroMips_NotMips32r6 },
11219 { 7743 /* rdhwr */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11220 { 7743 /* rdhwr */, 2 /* 1 */, MCK_HWRegsAsmReg, AMFBS_InMicroMips_HasMips32r6 },
11221 { 7743 /* rdhwr */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_IsGP64bit },
11222 { 7743 /* rdhwr */, 2 /* 1 */, MCK_HWRegsAsmReg, AMFBS_IsGP64bit },
11223 { 7743 /* rdhwr */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11224 { 7743 /* rdhwr */, 2 /* 1 */, MCK_HWRegsAsmReg, AMFBS_InMicroMips_HasMips32r6 },
11225 { 7743 /* rdhwr */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
11226 { 7743 /* rdhwr */, 2 /* 1 */, MCK_HWRegsAsmReg, AMFBS_HasStdEnc_NotInMicroMips },
11227 { 7743 /* rdhwr */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
11228 { 7743 /* rdhwr */, 2 /* 1 */, MCK_HWRegsAsmReg, AMFBS_InMicroMips_NotMips32r6 },
11229 { 7749 /* rdpgpr */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11230 { 7756 /* recip.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips },
11231 { 7756 /* recip.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat },
11232 { 7756 /* recip.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips },
11233 { 7756 /* recip.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat },
11234 { 7764 /* recip.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips },
11235 { 7764 /* recip.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat },
11236 { 7772 /* rem */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 },
11237 { 7772 /* rem */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 },
11238 { 7772 /* rem */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 },
11239 { 7772 /* rem */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 },
11240 { 7776 /* remu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 },
11241 { 7776 /* remu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 },
11242 { 7776 /* remu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 },
11243 { 7776 /* remu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 },
11244 { 7781 /* repl.ph */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11245 { 7781 /* repl.ph */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
11246 { 7789 /* repl.qb */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11247 { 7789 /* repl.qb */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
11248 { 7797 /* replv.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11249 { 7797 /* replv.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
11250 { 7806 /* replv.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11251 { 7806 /* replv.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
11252 { 7815 /* rint.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
11253 { 7815 /* rint.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11254 { 7822 /* rint.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
11255 { 7822 /* rint.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11256 { 7829 /* rol */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_None },
11257 { 7829 /* rol */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None },
11258 { 7829 /* rol */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_None },
11259 { 7829 /* rol */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_None },
11260 { 7833 /* ror */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_None },
11261 { 7833 /* ror */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None },
11262 { 7833 /* ror */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_None },
11263 { 7833 /* ror */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_None },
11264 { 7837 /* rotr */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips },
11265 { 7837 /* rotr */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11266 { 7837 /* rotr */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11267 { 7837 /* rotr */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips },
11268 { 7837 /* rotr */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11269 { 7842 /* rotrv */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips },
11270 { 7842 /* rotrv */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11271 { 7848 /* round.l.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips3_32_IsNotSoftFloat_NotInMicroMips },
11272 { 7848 /* round.l.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
11273 { 7858 /* round.l.s */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips },
11274 { 7858 /* round.l.s */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips },
11275 { 7858 /* round.l.s */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
11276 { 7858 /* round.l.s */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
11277 { 7868 /* round.w.d */, 2 /* 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips },
11278 { 7868 /* round.w.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips },
11279 { 7868 /* round.w.d */, 2 /* 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat },
11280 { 7868 /* round.w.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat },
11281 { 7868 /* round.w.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips },
11282 { 7868 /* round.w.d */, 2 /* 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips },
11283 { 7868 /* round.w.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
11284 { 7878 /* round.w.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotR5900_IsNotSoftFloat_NotInMicroMips },
11285 { 7878 /* round.w.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
11286 { 7878 /* round.w.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat },
11287 { 7888 /* rsqrt.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips },
11288 { 7888 /* rsqrt.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat },
11289 { 7888 /* rsqrt.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips },
11290 { 7888 /* rsqrt.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat },
11291 { 7896 /* rsqrt.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips },
11292 { 7896 /* rsqrt.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat },
11293 { 7904 /* s.d */, 1 /* 0 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat },
11294 { 7904 /* s.d */, 2 /* 1 */, MCK_SImmOffset16_0, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat },
11295 { 7904 /* s.d */, 8 /* 3 */, MCK_PtrReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat },
11296 { 7904 /* s.d */, 1 /* 0 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat },
11297 { 7904 /* s.d */, 2 /* 1 */, MCK_SImmOffset16_0, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat },
11298 { 7904 /* s.d */, 8 /* 3 */, MCK_PtrReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat },
11299 { 7904 /* s.d */, 1 /* 0 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat },
11300 { 7904 /* s.d */, 2 /* 1 */, MCK_SImmOffset16_0, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat },
11301 { 7904 /* s.d */, 8 /* 3 */, MCK_PtrReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat },
11302 { 7904 /* s.d */, 2 /* 1 */, MCK_SImmOffset16_0, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat },
11303 { 7904 /* s.d */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat },
11304 { 7904 /* s.d */, 8 /* 3 */, MCK_PtrReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat },
11305 { 7908 /* s.s */, 2 /* 1 */, MCK_SImmOffset16_0, AMFBS_HasStdEnc_HasMips2_IsNotSoftFloat },
11306 { 7908 /* s.s */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips2_IsNotSoftFloat },
11307 { 7908 /* s.s */, 8 /* 3 */, MCK_PtrReg, AMFBS_HasStdEnc_HasMips2_IsNotSoftFloat },
11308 { 7912 /* saa */, 5 /* 0, 2 */, MCK_GPR64AsmReg, AMFBS_HasCnMipsP },
11309 { 7912 /* saa */, 2 /* 1 */, MCK_AnyOffset, AMFBS_HasCnMipsP },
11310 { 7912 /* saa */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasCnMipsP },
11311 { 7912 /* saa */, 8 /* 3 */, MCK_PtrReg, AMFBS_HasCnMipsP },
11312 { 7916 /* saad */, 5 /* 0, 2 */, MCK_GPR64AsmReg, AMFBS_HasCnMipsP },
11313 { 7916 /* saad */, 2 /* 1 */, MCK_AnyOffset, AMFBS_HasCnMipsP },
11314 { 7916 /* saad */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasCnMipsP },
11315 { 7916 /* saad */, 8 /* 3 */, MCK_PtrReg, AMFBS_HasCnMipsP },
11316 { 7921 /* sat_s.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11317 { 7929 /* sat_s.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11318 { 7937 /* sat_s.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11319 { 7945 /* sat_s.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11320 { 7953 /* sat_u.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11321 { 7961 /* sat_u.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11322 { 7969 /* sat_u.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11323 { 7977 /* sat_u.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11324 { 7985 /* sb */, 2 /* 1 */, MCK_AnyOffset, AMFBS_HasStdEnc_NotInMicroMips },
11325 { 7985 /* sb */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
11326 { 7985 /* sb */, 8 /* 3 */, MCK_PtrReg, AMFBS_HasStdEnc_NotInMicroMips },
11327 { 7985 /* sb */, 2 /* 1 */, MCK_AnyOffset, AMFBS_InMicroMips_HasMips32r6 },
11328 { 7985 /* sb */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11329 { 7985 /* sb */, 8 /* 3 */, MCK_PtrReg, AMFBS_InMicroMips_HasMips32r6 },
11330 { 7985 /* sb */, 2 /* 1 */, MCK_AnyOffset, AMFBS_InMicroMips },
11331 { 7985 /* sb */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11332 { 7985 /* sb */, 8 /* 3 */, MCK_PtrReg, AMFBS_InMicroMips },
11333 { 7988 /* sb16 */, 2 /* 1 */, MCK_UImmOffset4_00, AMFBS_InMicroMips_NotMips32r6 },
11334 { 7988 /* sb16 */, 8 /* 3 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_NotMips32r6 },
11335 { 7988 /* sb16 */, 1 /* 0 */, MCK_GPRMM16AsmRegZero, AMFBS_InMicroMips_NotMips32r6 },
11336 { 7988 /* sb16 */, 2 /* 1 */, MCK_UImmOffset4_00, AMFBS_InMicroMips_HasMips32r6 },
11337 { 7988 /* sb16 */, 8 /* 3 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11338 { 7988 /* sb16 */, 1 /* 0 */, MCK_GPRMM16AsmRegZero, AMFBS_InMicroMips_HasMips32r6 },
11339 { 7993 /* sbe */, 2 /* 1 */, MCK_SImmOffset9_0, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips },
11340 { 7993 /* sbe */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips },
11341 { 7993 /* sbe */, 8 /* 3 */, MCK_PtrReg, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips },
11342 { 7993 /* sbe */, 2 /* 1 */, MCK_SImmOffset9_0, AMFBS_InMicroMips_HasEVA },
11343 { 7993 /* sbe */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasEVA },
11344 { 7993 /* sbe */, 8 /* 3 */, MCK_PtrReg, AMFBS_InMicroMips_HasEVA },
11345 { 7997 /* sc */, 2 /* 1 */, MCK_SImmOffset9_0, AMFBS_InMicroMips_HasMips32r6 },
11346 { 7997 /* sc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11347 { 7997 /* sc */, 8 /* 3 */, MCK_PtrReg, AMFBS_InMicroMips_HasMips32r6 },
11348 { 7997 /* sc */, 2 /* 1 */, MCK_SImmPtr, AMFBS_HasStdEnc_IsPTR64bit_HasMips64r6_NotInMicroMips },
11349 { 7997 /* sc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsPTR64bit_HasMips64r6_NotInMicroMips },
11350 { 7997 /* sc */, 8 /* 3 */, MCK_PtrReg, AMFBS_HasStdEnc_IsPTR64bit_HasMips64r6_NotInMicroMips },
11351 { 7997 /* sc */, 2 /* 1 */, MCK_SImmPtr, AMFBS_HasStdEnc_IsPTR32bit_HasMips32r6_NotInMicroMips },
11352 { 7997 /* sc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsPTR32bit_HasMips32r6_NotInMicroMips },
11353 { 7997 /* sc */, 8 /* 3 */, MCK_PtrReg, AMFBS_HasStdEnc_IsPTR32bit_HasMips32r6_NotInMicroMips },
11354 { 7997 /* sc */, 2 /* 1 */, MCK_AnyOffset, AMFBS_HasStdEnc_IsPTR32bit_HasMips2_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips },
11355 { 7997 /* sc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsPTR32bit_HasMips2_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips },
11356 { 7997 /* sc */, 8 /* 3 */, MCK_PtrReg, AMFBS_HasStdEnc_IsPTR32bit_HasMips2_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips },
11357 { 7997 /* sc */, 2 /* 1 */, MCK_AnyOffset, AMFBS_HasStdEnc_IsPTR64bit_HasMips2_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips },
11358 { 7997 /* sc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsPTR64bit_HasMips2_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips },
11359 { 7997 /* sc */, 8 /* 3 */, MCK_PtrReg, AMFBS_HasStdEnc_IsPTR64bit_HasMips2_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips },
11360 { 7997 /* sc */, 2 /* 1 */, MCK_AnyOffset, AMFBS_InMicroMips_NotMips32r6 },
11361 { 7997 /* sc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
11362 { 7997 /* sc */, 8 /* 3 */, MCK_PtrReg, AMFBS_InMicroMips_NotMips32r6 },
11363 { 8000 /* scd */, 2 /* 1 */, MCK_SImmPtr, AMFBS_HasStdEnc_HasMips32r6 },
11364 { 8000 /* scd */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips32r6 },
11365 { 8000 /* scd */, 8 /* 3 */, MCK_PtrReg, AMFBS_HasStdEnc_HasMips32r6 },
11366 { 8000 /* scd */, 2 /* 1 */, MCK_AnyOffset, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900 },
11367 { 8000 /* scd */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900 },
11368 { 8000 /* scd */, 8 /* 3 */, MCK_PtrReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900 },
11369 { 8004 /* sce */, 2 /* 1 */, MCK_SImmOffset9_0, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips },
11370 { 8004 /* sce */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips },
11371 { 8004 /* sce */, 8 /* 3 */, MCK_PtrReg, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips },
11372 { 8004 /* sce */, 2 /* 1 */, MCK_SImmOffset9_0, AMFBS_InMicroMips_HasEVA },
11373 { 8004 /* sce */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasEVA },
11374 { 8004 /* sce */, 8 /* 3 */, MCK_PtrReg, AMFBS_InMicroMips_HasEVA },
11375 { 8008 /* sd */, 2 /* 1 */, MCK_SImmOffset16_0, AMFBS_HasStdEnc_NotMips3 },
11376 { 8008 /* sd */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips3 },
11377 { 8008 /* sd */, 8 /* 3 */, MCK_PtrReg, AMFBS_HasStdEnc_NotMips3 },
11378 { 8008 /* sd */, 2 /* 1 */, MCK_SImmPtr, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
11379 { 8008 /* sd */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
11380 { 8008 /* sd */, 8 /* 3 */, MCK_PtrReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
11381 { 8025 /* sdc1 */, 1 /* 0 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips },
11382 { 8025 /* sdc1 */, 2 /* 1 */, MCK_SImmOffset16_0, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips },
11383 { 8025 /* sdc1 */, 8 /* 3 */, MCK_PtrReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips },
11384 { 8025 /* sdc1 */, 1 /* 0 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat },
11385 { 8025 /* sdc1 */, 2 /* 1 */, MCK_SImmOffset16_0, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat },
11386 { 8025 /* sdc1 */, 8 /* 3 */, MCK_PtrReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat },
11387 { 8025 /* sdc1 */, 2 /* 1 */, MCK_SImmOffset16_0, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips },
11388 { 8025 /* sdc1 */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips },
11389 { 8025 /* sdc1 */, 8 /* 3 */, MCK_PtrReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips },
11390 { 8025 /* sdc1 */, 2 /* 1 */, MCK_SImmOffset16_0, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_HasMips32r6_IsNotSoftFloat },
11391 { 8025 /* sdc1 */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_HasMips32r6_IsNotSoftFloat },
11392 { 8025 /* sdc1 */, 8 /* 3 */, MCK_PtrReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_HasMips32r6_IsNotSoftFloat },
11393 { 8025 /* sdc1 */, 2 /* 1 */, MCK_SImmOffset16_0, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat },
11394 { 8025 /* sdc1 */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat },
11395 { 8025 /* sdc1 */, 8 /* 3 */, MCK_PtrReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat },
11396 { 8030 /* sdc2 */, 2 /* 1 */, MCK_SImmOffset11_0, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
11397 { 8030 /* sdc2 */, 1 /* 0 */, MCK_COP2AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
11398 { 8030 /* sdc2 */, 8 /* 3 */, MCK_PtrReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
11399 { 8030 /* sdc2 */, 2 /* 1 */, MCK_SImmOffset11_0, AMFBS_InMicroMips_HasMips32r6 },
11400 { 8030 /* sdc2 */, 1 /* 0 */, MCK_COP2AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11401 { 8030 /* sdc2 */, 8 /* 3 */, MCK_PtrReg, AMFBS_InMicroMips_HasMips32r6 },
11402 { 8030 /* sdc2 */, 2 /* 1 */, MCK_SImmOffset16_0, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips },
11403 { 8030 /* sdc2 */, 1 /* 0 */, MCK_COP2AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips },
11404 { 8030 /* sdc2 */, 8 /* 3 */, MCK_PtrReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips },
11405 { 8035 /* sdc3 */, 2 /* 1 */, MCK_AnyOffset, AMFBS_HasStdEnc_HasMips2_NotR5900_NotCnMips_NotInMicroMips },
11406 { 8035 /* sdc3 */, 1 /* 0 */, MCK_COP3AsmReg, AMFBS_HasStdEnc_HasMips2_NotR5900_NotCnMips_NotInMicroMips },
11407 { 8035 /* sdc3 */, 8 /* 3 */, MCK_PtrReg, AMFBS_HasStdEnc_HasMips2_NotR5900_NotCnMips_NotInMicroMips },
11408 { 8040 /* sdl */, 2 /* 1 */, MCK_AnyOffset, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 },
11409 { 8040 /* sdl */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 },
11410 { 8040 /* sdl */, 8 /* 3 */, MCK_PtrReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 },
11411 { 8044 /* sdr */, 2 /* 1 */, MCK_AnyOffset, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 },
11412 { 8044 /* sdr */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 },
11413 { 8044 /* sdr */, 8 /* 3 */, MCK_PtrReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 },
11414 { 8048 /* sdxc1 */, 1 /* 0 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
11415 { 8048 /* sdxc1 */, 10 /* 1, 3 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
11416 { 8048 /* sdxc1 */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat },
11417 { 8048 /* sdxc1 */, 10 /* 1, 3 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat },
11418 { 8054 /* seb */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips },
11419 { 8054 /* seb */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11420 { 8054 /* seb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips },
11421 { 8054 /* seb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11422 { 8058 /* seh */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips },
11423 { 8058 /* seh */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11424 { 8058 /* seh */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips },
11425 { 8058 /* seh */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11426 { 8062 /* sel.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
11427 { 8062 /* sel.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11428 { 8068 /* sel.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
11429 { 8068 /* sel.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11430 { 8074 /* seleqz */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsGP32bit_HasMips32r6_NotInMicroMips },
11431 { 8074 /* seleqz */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11432 { 8074 /* seleqz */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips32r6 },
11433 { 8081 /* seleqz.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
11434 { 8081 /* seleqz.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11435 { 8090 /* seleqz.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
11436 { 8090 /* seleqz.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11437 { 8099 /* selnez */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsGP32bit_HasMips32r6_NotInMicroMips },
11438 { 8099 /* selnez */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11439 { 8099 /* selnez */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips32r6 },
11440 { 8106 /* selnez.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
11441 { 8106 /* selnez.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11442 { 8115 /* selnez.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
11443 { 8115 /* selnez.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11444 { 8124 /* seq */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_NotCnMips },
11445 { 8124 /* seq */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_NotCnMips },
11446 { 8124 /* seq */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasCnMips },
11447 { 8124 /* seq */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_NotCnMips },
11448 { 8124 /* seq */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_NotCnMips },
11449 { 8124 /* seq */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasCnMips },
11450 { 8128 /* seqi */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasCnMips },
11451 { 8128 /* seqi */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasCnMips },
11452 { 8133 /* sge */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
11453 { 8133 /* sge */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_IsGP32bit_NotInMicroMips },
11454 { 8133 /* sge */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_IsGP64bit },
11455 { 8133 /* sge */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
11456 { 8133 /* sge */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_IsGP32bit_NotInMicroMips },
11457 { 8133 /* sge */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_IsGP64bit },
11458 { 8137 /* sgeu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
11459 { 8137 /* sgeu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_IsGP32bit_NotInMicroMips },
11460 { 8137 /* sgeu */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_IsGP64bit },
11461 { 8137 /* sgeu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
11462 { 8137 /* sgeu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_IsGP32bit_NotInMicroMips },
11463 { 8137 /* sgeu */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_IsGP64bit },
11464 { 8142 /* sgt */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
11465 { 8142 /* sgt */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11466 { 8142 /* sgt */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_IsGP32bit_NotInMicroMips },
11467 { 8142 /* sgt */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_IsGP64bit },
11468 { 8142 /* sgt */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
11469 { 8142 /* sgt */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11470 { 8142 /* sgt */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_IsGP32bit_NotInMicroMips },
11471 { 8142 /* sgt */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_IsGP64bit },
11472 { 8146 /* sgtu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
11473 { 8146 /* sgtu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11474 { 8146 /* sgtu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_IsGP32bit_NotInMicroMips },
11475 { 8146 /* sgtu */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_IsGP64bit },
11476 { 8146 /* sgtu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
11477 { 8146 /* sgtu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11478 { 8146 /* sgtu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_IsGP32bit_NotInMicroMips },
11479 { 8146 /* sgtu */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_IsGP64bit },
11480 { 8151 /* sh */, 2 /* 1 */, MCK_AnyOffset, AMFBS_HasStdEnc_NotInMicroMips },
11481 { 8151 /* sh */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
11482 { 8151 /* sh */, 8 /* 3 */, MCK_PtrReg, AMFBS_HasStdEnc_NotInMicroMips },
11483 { 8151 /* sh */, 2 /* 1 */, MCK_AnyOffset, AMFBS_InMicroMips_HasMips32r6 },
11484 { 8151 /* sh */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11485 { 8151 /* sh */, 8 /* 3 */, MCK_PtrReg, AMFBS_InMicroMips_HasMips32r6 },
11486 { 8151 /* sh */, 2 /* 1 */, MCK_AnyOffset, AMFBS_InMicroMips },
11487 { 8151 /* sh */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11488 { 8151 /* sh */, 8 /* 3 */, MCK_PtrReg, AMFBS_InMicroMips },
11489 { 8154 /* sh16 */, 2 /* 1 */, MCK_UImmOffset4_10, AMFBS_InMicroMips_NotMips32r6 },
11490 { 8154 /* sh16 */, 8 /* 3 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_NotMips32r6 },
11491 { 8154 /* sh16 */, 1 /* 0 */, MCK_GPRMM16AsmRegZero, AMFBS_InMicroMips_NotMips32r6 },
11492 { 8154 /* sh16 */, 2 /* 1 */, MCK_UImmOffset4_10, AMFBS_InMicroMips_HasMips32r6 },
11493 { 8154 /* sh16 */, 8 /* 3 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11494 { 8154 /* sh16 */, 1 /* 0 */, MCK_GPRMM16AsmRegZero, AMFBS_InMicroMips_HasMips32r6 },
11495 { 8159 /* she */, 2 /* 1 */, MCK_SImmOffset9_0, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips },
11496 { 8159 /* she */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips },
11497 { 8159 /* she */, 8 /* 3 */, MCK_PtrReg, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips },
11498 { 8159 /* she */, 2 /* 1 */, MCK_SImmOffset9_0, AMFBS_InMicroMips_HasEVA },
11499 { 8159 /* she */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasEVA },
11500 { 8159 /* she */, 8 /* 3 */, MCK_PtrReg, AMFBS_InMicroMips_HasEVA },
11501 { 8163 /* shf.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11502 { 8169 /* shf.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11503 { 8175 /* shf.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11504 { 8181 /* shilo */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
11505 { 8181 /* shilo */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
11506 { 8187 /* shilov */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
11507 { 8187 /* shilov */, 2 /* 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11508 { 8187 /* shilov */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
11509 { 8187 /* shilov */, 2 /* 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
11510 { 8194 /* shll.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11511 { 8194 /* shll.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
11512 { 8202 /* shll.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11513 { 8202 /* shll.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
11514 { 8210 /* shll_s.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11515 { 8210 /* shll_s.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
11516 { 8220 /* shll_s.w */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11517 { 8220 /* shll_s.w */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
11518 { 8229 /* shllv.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11519 { 8229 /* shllv.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
11520 { 8238 /* shllv.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11521 { 8238 /* shllv.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
11522 { 8247 /* shllv_s.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11523 { 8247 /* shllv_s.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
11524 { 8258 /* shllv_s.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11525 { 8258 /* shllv_s.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
11526 { 8268 /* shra.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11527 { 8268 /* shra.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
11528 { 8276 /* shra.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
11529 { 8276 /* shra.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
11530 { 8284 /* shra_r.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11531 { 8284 /* shra_r.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
11532 { 8294 /* shra_r.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
11533 { 8294 /* shra_r.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
11534 { 8304 /* shra_r.w */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11535 { 8304 /* shra_r.w */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
11536 { 8313 /* shrav.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11537 { 8313 /* shrav.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
11538 { 8322 /* shrav.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
11539 { 8322 /* shrav.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
11540 { 8331 /* shrav_r.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11541 { 8331 /* shrav_r.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
11542 { 8342 /* shrav_r.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
11543 { 8342 /* shrav_r.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
11544 { 8353 /* shrav_r.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11545 { 8353 /* shrav_r.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
11546 { 8363 /* shrl.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
11547 { 8363 /* shrl.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
11548 { 8371 /* shrl.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11549 { 8371 /* shrl.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
11550 { 8379 /* shrlv.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
11551 { 8379 /* shrlv.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
11552 { 8388 /* shrlv.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11553 { 8388 /* shrlv.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
11554 { 8404 /* sld.b */, 8 /* 3 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA },
11555 { 8404 /* sld.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11556 { 8410 /* sld.d */, 8 /* 3 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA },
11557 { 8410 /* sld.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11558 { 8416 /* sld.h */, 8 /* 3 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA },
11559 { 8416 /* sld.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11560 { 8422 /* sld.w */, 8 /* 3 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA },
11561 { 8422 /* sld.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11562 { 8428 /* sldi.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11563 { 8435 /* sldi.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11564 { 8442 /* sldi.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11565 { 8449 /* sldi.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11566 { 8456 /* sle */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
11567 { 8456 /* sle */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_IsGP32bit_NotInMicroMips },
11568 { 8456 /* sle */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_IsGP64bit },
11569 { 8456 /* sle */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
11570 { 8456 /* sle */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_IsGP32bit_NotInMicroMips },
11571 { 8456 /* sle */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_IsGP64bit },
11572 { 8460 /* sleu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
11573 { 8460 /* sleu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_IsGP32bit_NotInMicroMips },
11574 { 8460 /* sleu */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_IsGP64bit },
11575 { 8460 /* sleu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
11576 { 8460 /* sleu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_IsGP32bit_NotInMicroMips },
11577 { 8460 /* sleu */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_IsGP64bit },
11578 { 8465 /* sll */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_NotInMicroMips },
11579 { 8465 /* sll */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11580 { 8465 /* sll */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
11581 { 8465 /* sll */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11582 { 8465 /* sll */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11583 { 8465 /* sll */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11584 { 8465 /* sll */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_NotInMicroMips },
11585 { 8465 /* sll */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11586 { 8465 /* sll */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
11587 { 8465 /* sll */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11588 { 8465 /* sll */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11589 { 8469 /* sll.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11590 { 8475 /* sll.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11591 { 8481 /* sll.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11592 { 8487 /* sll.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11593 { 8493 /* sll16 */, 3 /* 0, 1 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_NotMips32r6 },
11594 { 8493 /* sll16 */, 3 /* 0, 1 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11595 { 8499 /* slli.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11596 { 8506 /* slli.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11597 { 8513 /* slli.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11598 { 8520 /* slli.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11599 { 8527 /* sllv */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
11600 { 8527 /* sllv */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11601 { 8532 /* slt */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips },
11602 { 8532 /* slt */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11603 { 8532 /* slt */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_IsGP64bit },
11604 { 8532 /* slt */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
11605 { 8532 /* slt */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11606 { 8532 /* slt */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips },
11607 { 8532 /* slt */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11608 { 8532 /* slt */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_IsGP64bit },
11609 { 8536 /* slti */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
11610 { 8536 /* slti */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11611 { 8541 /* sltiu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
11612 { 8541 /* sltiu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11613 { 8547 /* sltu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips },
11614 { 8547 /* sltu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11615 { 8547 /* sltu */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_IsGP64bit },
11616 { 8547 /* sltu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
11617 { 8547 /* sltu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11618 { 8547 /* sltu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips },
11619 { 8547 /* sltu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11620 { 8547 /* sltu */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_IsGP64bit },
11621 { 8552 /* sne */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_NotCnMips },
11622 { 8552 /* sne */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_NotCnMips },
11623 { 8552 /* sne */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasCnMips },
11624 { 8552 /* sne */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_NotCnMips },
11625 { 8552 /* sne */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_NotCnMips },
11626 { 8552 /* sne */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasCnMips },
11627 { 8556 /* snei */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasCnMips },
11628 { 8556 /* snei */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasCnMips },
11629 { 8561 /* splat.b */, 8 /* 3 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA },
11630 { 8561 /* splat.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11631 { 8569 /* splat.d */, 8 /* 3 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA },
11632 { 8569 /* splat.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11633 { 8577 /* splat.h */, 8 /* 3 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA },
11634 { 8577 /* splat.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11635 { 8585 /* splat.w */, 8 /* 3 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA },
11636 { 8585 /* splat.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11637 { 8593 /* splati.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11638 { 8602 /* splati.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11639 { 8611 /* splati.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11640 { 8620 /* splati.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11641 { 8629 /* sqrt.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips },
11642 { 8629 /* sqrt.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat },
11643 { 8629 /* sqrt.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips },
11644 { 8629 /* sqrt.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat },
11645 { 8636 /* sqrt.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips2_IsNotSoftFloat_NotInMicroMips },
11646 { 8636 /* sqrt.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat },
11647 { 8643 /* sra */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_NotInMicroMips },
11648 { 8643 /* sra */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11649 { 8643 /* sra */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
11650 { 8643 /* sra */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11651 { 8643 /* sra */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11652 { 8643 /* sra */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_NotInMicroMips },
11653 { 8643 /* sra */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11654 { 8643 /* sra */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
11655 { 8643 /* sra */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11656 { 8647 /* sra.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11657 { 8653 /* sra.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11658 { 8659 /* sra.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11659 { 8665 /* sra.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11660 { 8671 /* srai.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11661 { 8678 /* srai.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11662 { 8685 /* srai.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11663 { 8692 /* srai.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11664 { 8699 /* srar.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11665 { 8706 /* srar.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11666 { 8713 /* srar.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11667 { 8720 /* srar.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11668 { 8727 /* srari.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11669 { 8735 /* srari.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11670 { 8743 /* srari.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11671 { 8751 /* srari.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11672 { 8759 /* srav */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
11673 { 8759 /* srav */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11674 { 8764 /* srl */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_NotInMicroMips },
11675 { 8764 /* srl */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11676 { 8764 /* srl */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
11677 { 8764 /* srl */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11678 { 8764 /* srl */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11679 { 8764 /* srl */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_NotInMicroMips },
11680 { 8764 /* srl */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11681 { 8764 /* srl */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
11682 { 8764 /* srl */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11683 { 8768 /* srl.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11684 { 8774 /* srl.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11685 { 8780 /* srl.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11686 { 8786 /* srl.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11687 { 8792 /* srl16 */, 3 /* 0, 1 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_NotMips32r6 },
11688 { 8792 /* srl16 */, 3 /* 0, 1 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11689 { 8798 /* srli.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11690 { 8805 /* srli.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11691 { 8812 /* srli.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11692 { 8819 /* srli.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11693 { 8826 /* srlr.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11694 { 8833 /* srlr.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11695 { 8840 /* srlr.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11696 { 8847 /* srlr.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11697 { 8854 /* srlri.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11698 { 8862 /* srlri.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11699 { 8870 /* srlri.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11700 { 8878 /* srlri.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11701 { 8886 /* srlv */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
11702 { 8886 /* srlv */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11703 { 8897 /* st.b */, 2 /* 1 */, MCK_SImmOffset10_0, AMFBS_HasStdEnc_HasMSA },
11704 { 8897 /* st.b */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11705 { 8897 /* st.b */, 8 /* 3 */, MCK_PtrReg, AMFBS_HasStdEnc_HasMSA },
11706 { 8902 /* st.d */, 2 /* 1 */, MCK_SImmOffset10_3, AMFBS_HasStdEnc_HasMSA },
11707 { 8902 /* st.d */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11708 { 8902 /* st.d */, 8 /* 3 */, MCK_PtrReg, AMFBS_HasStdEnc_HasMSA },
11709 { 8907 /* st.h */, 2 /* 1 */, MCK_SImmOffset10_1, AMFBS_HasStdEnc_HasMSA },
11710 { 8907 /* st.h */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11711 { 8907 /* st.h */, 8 /* 3 */, MCK_PtrReg, AMFBS_HasStdEnc_HasMSA },
11712 { 8912 /* st.w */, 2 /* 1 */, MCK_SImmOffset10_2, AMFBS_HasStdEnc_HasMSA },
11713 { 8912 /* st.w */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11714 { 8912 /* st.w */, 8 /* 3 */, MCK_PtrReg, AMFBS_HasStdEnc_HasMSA },
11715 { 8917 /* sub */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
11716 { 8917 /* sub */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
11717 { 8917 /* sub */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11718 { 8917 /* sub */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 },
11719 { 8917 /* sub */, 2 /* 1 */, MCK_InvNum, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 },
11720 { 8917 /* sub */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
11721 { 8917 /* sub */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
11722 { 8917 /* sub */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11723 { 8917 /* sub */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 },
11724 { 8917 /* sub */, 4 /* 2 */, MCK_InvNum, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 },
11725 { 8921 /* sub.d */, 7 /* 0, 1, 2 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips },
11726 { 8921 /* sub.d */, 7 /* 0, 1, 2 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat },
11727 { 8921 /* sub.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips },
11728 { 8921 /* sub.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat },
11729 { 8927 /* sub.ps */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
11730 { 8934 /* sub.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips },
11731 { 8934 /* sub.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
11732 { 8934 /* sub.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat },
11733 { 8940 /* subq.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11734 { 8940 /* subq.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
11735 { 8948 /* subq_s.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11736 { 8948 /* subq_s.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
11737 { 8958 /* subq_s.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11738 { 8958 /* subq_s.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
11739 { 8967 /* subqh.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
11740 { 8967 /* subqh.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
11741 { 8976 /* subqh.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
11742 { 8976 /* subqh.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
11743 { 8984 /* subqh_r.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
11744 { 8984 /* subqh_r.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
11745 { 8995 /* subqh_r.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
11746 { 8995 /* subqh_r.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
11747 { 9005 /* subs_s.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11748 { 9014 /* subs_s.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11749 { 9023 /* subs_s.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11750 { 9032 /* subs_s.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11751 { 9041 /* subs_u.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11752 { 9050 /* subs_u.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11753 { 9059 /* subs_u.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11754 { 9068 /* subs_u.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11755 { 9077 /* subsus_u.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11756 { 9088 /* subsus_u.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11757 { 9099 /* subsus_u.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11758 { 9110 /* subsus_u.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11759 { 9121 /* subsuu_s.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11760 { 9132 /* subsuu_s.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11761 { 9143 /* subsuu_s.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11762 { 9154 /* subsuu_s.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11763 { 9165 /* subu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11764 { 9165 /* subu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
11765 { 9165 /* subu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
11766 { 9165 /* subu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None },
11767 { 9165 /* subu */, 2 /* 1 */, MCK_InvNum, AMFBS_None },
11768 { 9165 /* subu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11769 { 9165 /* subu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
11770 { 9165 /* subu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
11771 { 9165 /* subu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_None },
11772 { 9165 /* subu */, 4 /* 2 */, MCK_InvNum, AMFBS_None },
11773 { 9170 /* subu.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
11774 { 9170 /* subu.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
11775 { 9178 /* subu.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11776 { 9178 /* subu.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
11777 { 9186 /* subu16 */, 7 /* 0, 1, 2 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_NotMips32r6 },
11778 { 9186 /* subu16 */, 7 /* 0, 1, 2 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11779 { 9193 /* subu_s.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
11780 { 9193 /* subu_s.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
11781 { 9203 /* subu_s.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11782 { 9203 /* subu_s.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
11783 { 9213 /* subuh.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
11784 { 9213 /* subuh.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
11785 { 9222 /* subuh_r.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
11786 { 9222 /* subuh_r.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
11787 { 9233 /* subv.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11788 { 9240 /* subv.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11789 { 9247 /* subv.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11790 { 9254 /* subv.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11791 { 9261 /* subvi.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11792 { 9269 /* subvi.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11793 { 9277 /* subvi.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11794 { 9285 /* subvi.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11795 { 9293 /* suxc1 */, 1 /* 0 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
11796 { 9293 /* suxc1 */, 10 /* 1, 3 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
11797 { 9293 /* suxc1 */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
11798 { 9293 /* suxc1 */, 10 /* 1, 3 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
11799 { 9293 /* suxc1 */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
11800 { 9293 /* suxc1 */, 10 /* 1, 3 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
11801 { 9299 /* sw */, 2 /* 1 */, MCK_UImmOffset5_20, AMFBS_InMicroMips_HasMips32r6 },
11802 { 9299 /* sw */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11803 { 9299 /* sw */, 8 /* 3 */, MCK_MemBaseSP, AMFBS_InMicroMips_HasMips32r6 },
11804 { 9299 /* sw */, 2 /* 1 */, MCK_UImmOffset5_20, AMFBS_InMicroMips },
11805 { 9299 /* sw */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11806 { 9299 /* sw */, 8 /* 3 */, MCK_MemBaseSP, AMFBS_InMicroMips },
11807 { 9299 /* sw */, 2 /* 1 */, MCK_AnyOffset, AMFBS_HasStdEnc_NotInMicroMips },
11808 { 9299 /* sw */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
11809 { 9299 /* sw */, 8 /* 3 */, MCK_PtrReg, AMFBS_HasStdEnc_NotInMicroMips },
11810 { 9299 /* sw */, 2 /* 1 */, MCK_AnyOffset, AMFBS_NotInMips16Mode_HasDSP },
11811 { 9299 /* sw */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_NotInMips16Mode_HasDSP },
11812 { 9299 /* sw */, 8 /* 3 */, MCK_PtrReg, AMFBS_NotInMips16Mode_HasDSP },
11813 { 9299 /* sw */, 2 /* 1 */, MCK_AnyOffset, AMFBS_InMicroMips_HasDSP },
11814 { 9299 /* sw */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11815 { 9299 /* sw */, 8 /* 3 */, MCK_PtrReg, AMFBS_InMicroMips_HasDSP },
11816 { 9299 /* sw */, 2 /* 1 */, MCK_AnyOffset, AMFBS_InMicroMips_HasMips32r6 },
11817 { 9299 /* sw */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11818 { 9299 /* sw */, 8 /* 3 */, MCK_PtrReg, AMFBS_InMicroMips_HasMips32r6 },
11819 { 9299 /* sw */, 2 /* 1 */, MCK_AnyOffset, AMFBS_InMicroMips },
11820 { 9299 /* sw */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11821 { 9299 /* sw */, 8 /* 3 */, MCK_PtrReg, AMFBS_InMicroMips },
11822 { 9302 /* sw16 */, 2 /* 1 */, MCK_UImmOffset4_20, AMFBS_InMicroMips_NotMips32r6 },
11823 { 9302 /* sw16 */, 8 /* 3 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_NotMips32r6 },
11824 { 9302 /* sw16 */, 1 /* 0 */, MCK_GPRMM16AsmRegZero, AMFBS_InMicroMips_NotMips32r6 },
11825 { 9302 /* sw16 */, 2 /* 1 */, MCK_UImmOffset4_20, AMFBS_InMicroMips_HasMips32r6 },
11826 { 9302 /* sw16 */, 8 /* 3 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11827 { 9302 /* sw16 */, 1 /* 0 */, MCK_GPRMM16AsmRegZero, AMFBS_InMicroMips_HasMips32r6 },
11828 { 9307 /* swc1 */, 2 /* 1 */, MCK_SImmOffset16_0, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips },
11829 { 9307 /* swc1 */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips },
11830 { 9307 /* swc1 */, 8 /* 3 */, MCK_PtrReg, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips },
11831 { 9307 /* swc1 */, 2 /* 1 */, MCK_SImmOffset16_0, AMFBS_InMicroMips_IsNotSoftFloat },
11832 { 9307 /* swc1 */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat },
11833 { 9307 /* swc1 */, 8 /* 3 */, MCK_PtrReg, AMFBS_InMicroMips_IsNotSoftFloat },
11834 { 9312 /* swc2 */, 2 /* 1 */, MCK_SImmOffset11_0, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
11835 { 9312 /* swc2 */, 1 /* 0 */, MCK_COP2AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
11836 { 9312 /* swc2 */, 8 /* 3 */, MCK_PtrReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
11837 { 9312 /* swc2 */, 2 /* 1 */, MCK_SImmOffset11_0, AMFBS_InMicroMips_HasMips32r6 },
11838 { 9312 /* swc2 */, 1 /* 0 */, MCK_COP2AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11839 { 9312 /* swc2 */, 8 /* 3 */, MCK_PtrReg, AMFBS_InMicroMips_HasMips32r6 },
11840 { 9312 /* swc2 */, 2 /* 1 */, MCK_SImmOffset16_0, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips },
11841 { 9312 /* swc2 */, 1 /* 0 */, MCK_COP2AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips },
11842 { 9312 /* swc2 */, 8 /* 3 */, MCK_PtrReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips },
11843 { 9317 /* swc3 */, 2 /* 1 */, MCK_AnyOffset, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_NotCnMips_NotInMicroMips },
11844 { 9317 /* swc3 */, 1 /* 0 */, MCK_COP3AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_NotCnMips_NotInMicroMips },
11845 { 9317 /* swc3 */, 8 /* 3 */, MCK_PtrReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_NotCnMips_NotInMicroMips },
11846 { 9322 /* swe */, 2 /* 1 */, MCK_SImmOffset9_0, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips },
11847 { 9322 /* swe */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips },
11848 { 9322 /* swe */, 8 /* 3 */, MCK_PtrReg, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips },
11849 { 9322 /* swe */, 2 /* 1 */, MCK_SImmOffset9_0, AMFBS_InMicroMips_HasEVA },
11850 { 9322 /* swe */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasEVA },
11851 { 9322 /* swe */, 8 /* 3 */, MCK_PtrReg, AMFBS_InMicroMips_HasEVA },
11852 { 9326 /* swl */, 2 /* 1 */, MCK_AnyOffset, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips },
11853 { 9326 /* swl */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips },
11854 { 9326 /* swl */, 8 /* 3 */, MCK_PtrReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips },
11855 { 9326 /* swl */, 2 /* 1 */, MCK_AnyOffset, AMFBS_InMicroMips_NotMips32r6 },
11856 { 9326 /* swl */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
11857 { 9326 /* swl */, 8 /* 3 */, MCK_PtrReg, AMFBS_InMicroMips_NotMips32r6 },
11858 { 9330 /* swle */, 2 /* 1 */, MCK_SImmOffset9_0, AMFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips },
11859 { 9330 /* swle */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips },
11860 { 9330 /* swle */, 8 /* 3 */, MCK_PtrReg, AMFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips },
11861 { 9330 /* swle */, 2 /* 1 */, MCK_SImmOffset9_0, AMFBS_InMicroMips_NotMips32r6_HasEVA },
11862 { 9330 /* swle */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6_HasEVA },
11863 { 9330 /* swle */, 8 /* 3 */, MCK_PtrReg, AMFBS_InMicroMips_NotMips32r6_HasEVA },
11864 { 9335 /* swm */, 2 /* 1 */, MCK_AnyOffset, AMFBS_InMicroMips },
11865 { 9335 /* swm */, 8 /* 3 */, MCK_PtrReg, AMFBS_InMicroMips },
11866 { 9335 /* swm */, 1 /* 0 */, MCK_RegList, AMFBS_InMicroMips },
11867 { 9339 /* swm16 */, 2 /* 1 */, MCK_UImmOffset4_20, AMFBS_InMicroMips_HasMips32r6 },
11868 { 9339 /* swm16 */, 8 /* 3 */, MCK_MemBaseSP, AMFBS_InMicroMips_HasMips32r6 },
11869 { 9339 /* swm16 */, 1 /* 0 */, MCK_RegList16, AMFBS_InMicroMips_HasMips32r6 },
11870 { 9339 /* swm16 */, 2 /* 1 */, MCK_UImmOffset6_00, AMFBS_InMicroMips_NotMips32r6 },
11871 { 9339 /* swm16 */, 8 /* 3 */, MCK_MemBaseSP, AMFBS_InMicroMips_NotMips32r6 },
11872 { 9339 /* swm16 */, 1 /* 0 */, MCK_RegList16, AMFBS_InMicroMips_NotMips32r6 },
11873 { 9345 /* swm32 */, 2 /* 1 */, MCK_AnyOffset, AMFBS_InMicroMips },
11874 { 9345 /* swm32 */, 8 /* 3 */, MCK_PtrReg, AMFBS_InMicroMips },
11875 { 9345 /* swm32 */, 1 /* 0 */, MCK_RegList, AMFBS_InMicroMips },
11876 { 9351 /* swp */, 2 /* 1 */, MCK_SImmOffset12_0, AMFBS_InMicroMips },
11877 { 9351 /* swp */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11878 { 9351 /* swp */, 8 /* 3 */, MCK_PtrReg, AMFBS_InMicroMips },
11879 { 9355 /* swr */, 2 /* 1 */, MCK_AnyOffset, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips },
11880 { 9355 /* swr */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips },
11881 { 9355 /* swr */, 8 /* 3 */, MCK_PtrReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips },
11882 { 9355 /* swr */, 2 /* 1 */, MCK_AnyOffset, AMFBS_InMicroMips_NotMips32r6 },
11883 { 9355 /* swr */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
11884 { 9355 /* swr */, 8 /* 3 */, MCK_PtrReg, AMFBS_InMicroMips_NotMips32r6 },
11885 { 9359 /* swre */, 2 /* 1 */, MCK_SImmOffset9_0, AMFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips },
11886 { 9359 /* swre */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips },
11887 { 9359 /* swre */, 8 /* 3 */, MCK_PtrReg, AMFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips },
11888 { 9359 /* swre */, 2 /* 1 */, MCK_SImmOffset9_0, AMFBS_InMicroMips_NotMips32r6_HasEVA },
11889 { 9359 /* swre */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6_HasEVA },
11890 { 9359 /* swre */, 8 /* 3 */, MCK_PtrReg, AMFBS_InMicroMips_NotMips32r6_HasEVA },
11891 { 9364 /* swsp */, 2 /* 1 */, MCK_UImmOffset5_20, AMFBS_InMicroMips_NotMips32r6 },
11892 { 9364 /* swsp */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
11893 { 9364 /* swsp */, 8 /* 3 */, MCK_MemBaseSP, AMFBS_InMicroMips_NotMips32r6 },
11894 { 9369 /* swxc1 */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat },
11895 { 9369 /* swxc1 */, 10 /* 1, 3 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat },
11896 { 9369 /* swxc1 */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
11897 { 9369 /* swxc1 */, 10 /* 1, 3 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
11898 { 9432 /* synci */, 1 /* 0 */, MCK_SImmOffset16_0, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips },
11899 { 9432 /* synci */, 4 /* 2 */, MCK_PtrReg, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips },
11900 { 9432 /* synci */, 1 /* 0 */, MCK_SImmOffset16_0, AMFBS_InMicroMips_NotMips32r6 },
11901 { 9432 /* synci */, 4 /* 2 */, MCK_PtrReg, AMFBS_InMicroMips_NotMips32r6 },
11902 { 9432 /* synci */, 1 /* 0 */, MCK_SImmOffset16_0, AMFBS_InMicroMips_HasMips32r6 },
11903 { 9432 /* synci */, 4 /* 2 */, MCK_PtrReg, AMFBS_InMicroMips_HasMips32r6 },
11904 { 9476 /* teq */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotInMicroMips },
11905 { 9476 /* teq */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11906 { 9476 /* teq */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11907 { 9476 /* teq */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotInMicroMips },
11908 { 9480 /* teqi */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips },
11909 { 9480 /* teqi */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
11910 { 9485 /* tge */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotInMicroMips },
11911 { 9485 /* tge */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11912 { 9485 /* tge */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11913 { 9485 /* tge */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotInMicroMips },
11914 { 9489 /* tgei */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips },
11915 { 9489 /* tgei */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
11916 { 9494 /* tgeiu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips },
11917 { 9494 /* tgeiu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
11918 { 9500 /* tgeu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotInMicroMips },
11919 { 9500 /* tgeu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11920 { 9500 /* tgeu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11921 { 9500 /* tgeu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotInMicroMips },
11922 { 9585 /* tlt */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotInMicroMips },
11923 { 9585 /* tlt */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11924 { 9585 /* tlt */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11925 { 9585 /* tlt */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotInMicroMips },
11926 { 9589 /* tlti */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips },
11927 { 9589 /* tlti */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
11928 { 9594 /* tltiu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips },
11929 { 9594 /* tltiu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
11930 { 9600 /* tltu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotInMicroMips },
11931 { 9600 /* tltu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11932 { 9600 /* tltu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11933 { 9600 /* tltu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotInMicroMips },
11934 { 9605 /* tne */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotInMicroMips },
11935 { 9605 /* tne */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11936 { 9605 /* tne */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11937 { 9605 /* tne */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotInMicroMips },
11938 { 9609 /* tnei */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips },
11939 { 9609 /* tnei */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
11940 { 9614 /* trunc.l.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips3_32_IsNotSoftFloat_NotInMicroMips },
11941 { 9614 /* trunc.l.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
11942 { 9624 /* trunc.l.s */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips },
11943 { 9624 /* trunc.l.s */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips },
11944 { 9624 /* trunc.l.s */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
11945 { 9624 /* trunc.l.s */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
11946 { 9634 /* trunc.w.d */, 2 /* 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips },
11947 { 9634 /* trunc.w.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips },
11948 { 9634 /* trunc.w.d */, 2 /* 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat },
11949 { 9634 /* trunc.w.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat },
11950 { 9634 /* trunc.w.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips },
11951 { 9634 /* trunc.w.d */, 2 /* 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips },
11952 { 9634 /* trunc.w.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
11953 { 9634 /* trunc.w.d */, 2 /* 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
11954 { 9634 /* trunc.w.d */, 2 /* 1 */, MCK_AFGR64AsmReg, AMFBS_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat },
11955 { 9634 /* trunc.w.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat },
11956 { 9634 /* trunc.w.d */, 4 /* 2 */, MCK_GPR32AsmReg, AMFBS_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat },
11957 { 9634 /* trunc.w.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat },
11958 { 9634 /* trunc.w.d */, 2 /* 1 */, MCK_FGR64AsmReg, AMFBS_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat },
11959 { 9634 /* trunc.w.d */, 4 /* 2 */, MCK_GPR32AsmReg, AMFBS_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat },
11960 { 9644 /* trunc.w.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotR5900_IsNotSoftFloat_NotInMicroMips },
11961 { 9644 /* trunc.w.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
11962 { 9644 /* trunc.w.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat },
11963 { 9644 /* trunc.w.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_None },
11964 { 9644 /* trunc.w.s */, 4 /* 2 */, MCK_GPR32AsmReg, AMFBS_None },
11965 { 9654 /* ulh */, 2 /* 1 */, MCK_AnyOffset, AMFBS_None },
11966 { 9654 /* ulh */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None },
11967 { 9654 /* ulh */, 8 /* 3 */, MCK_PtrReg, AMFBS_None },
11968 { 9658 /* ulhu */, 2 /* 1 */, MCK_AnyOffset, AMFBS_None },
11969 { 9658 /* ulhu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None },
11970 { 9658 /* ulhu */, 8 /* 3 */, MCK_PtrReg, AMFBS_None },
11971 { 9663 /* ulw */, 2 /* 1 */, MCK_AnyOffset, AMFBS_None },
11972 { 9663 /* ulw */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None },
11973 { 9663 /* ulw */, 8 /* 3 */, MCK_PtrReg, AMFBS_None },
11974 { 9667 /* ush */, 2 /* 1 */, MCK_AnyOffset, AMFBS_None },
11975 { 9667 /* ush */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None },
11976 { 9667 /* ush */, 8 /* 3 */, MCK_PtrReg, AMFBS_None },
11977 { 9671 /* usw */, 2 /* 1 */, MCK_AnyOffset, AMFBS_None },
11978 { 9671 /* usw */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None },
11979 { 9671 /* usw */, 8 /* 3 */, MCK_PtrReg, AMFBS_None },
11980 { 9675 /* v3mulu */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasCnMips },
11981 { 9675 /* v3mulu */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasCnMips },
11982 { 9682 /* vmm0 */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasCnMips },
11983 { 9682 /* vmm0 */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasCnMips },
11984 { 9687 /* vmulu */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasCnMips },
11985 { 9687 /* vmulu */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasCnMips },
11986 { 9693 /* vshf.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11987 { 9700 /* vshf.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11988 { 9707 /* vshf.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11989 { 9714 /* vshf.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11990 { 9726 /* wrdsp */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasDSP_NotInMicroMips },
11991 { 9726 /* wrdsp */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasDSP_InMicroMips },
11992 { 9726 /* wrdsp */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11993 { 9726 /* wrdsp */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasDSP_NotInMicroMips },
11994 { 9732 /* wrpgpr */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11995 { 9739 /* wsbh */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips },
11996 { 9739 /* wsbh */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11997 { 9739 /* wsbh */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11998 { 9744 /* xor */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
11999 { 9744 /* xor */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
12000 { 9744 /* xor */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
12001 { 9744 /* xor */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
12002 { 9744 /* xor */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips },
12003 { 9744 /* xor */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
12004 { 9744 /* xor */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips3_NotInMicroMips },
12005 { 9744 /* xor */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
12006 { 9744 /* xor */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
12007 { 9744 /* xor */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
12008 { 9744 /* xor */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
12009 { 9744 /* xor */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips },
12010 { 9744 /* xor */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
12011 { 9744 /* xor */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips3_NotInMicroMips },
12012 { 9748 /* xor.v */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
12013 { 9754 /* xor16 */, 3 /* 0, 1 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_NotMips32r6 },
12014 { 9754 /* xor16 */, 3 /* 0, 1 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_HasMips32r6 },
12015 { 9760 /* xori */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
12016 { 9760 /* xori */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
12017 { 9760 /* xori */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
12018 { 9760 /* xori */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
12019 { 9760 /* xori */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
12020 { 9760 /* xori */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
12021 { 9765 /* xori.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
12022 { 9772 /* yield */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT_NotInMicroMips },
12023 { 9772 /* yield */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMT_NotInMicroMips },
12024};
12025
12026ParseStatus MipsAsmParser::
12027tryCustomParseOperand(OperandVector &Operands,
12028 unsigned MCK) {
12029
12030 switch(MCK) {
12031 case MCK_ACC64DSPAsmReg:
12032 return parseAnyRegister(Operands);
12033 case MCK_AFGR64AsmReg:
12034 return parseAnyRegister(Operands);
12035 case MCK_SImmOffset9_0:
12036 return parseMemOffsetOperand(Operands);
12037 case MCK_SImmOffset10_0:
12038 return parseMemOffsetOperand(Operands);
12039 case MCK_SImmOffset11_0:
12040 return parseMemOffsetOperand(Operands);
12041 case MCK_SImmOffset12_0:
12042 return parseMemOffsetOperand(Operands);
12043 case MCK_SImmOffset16_0:
12044 return parseMemOffsetOperand(Operands);
12045 case MCK_SImmOffset10_1:
12046 return parseMemOffsetOperand(Operands);
12047 case MCK_SImmOffset10_2:
12048 return parseMemOffsetOperand(Operands);
12049 case MCK_SImmOffset10_3:
12050 return parseMemOffsetOperand(Operands);
12051 case MCK_UImmOffset4_00:
12052 return parseMemOffsetOperand(Operands);
12053 case MCK_UImmOffset4_10:
12054 return parseMemOffsetOperand(Operands);
12055 case MCK_UImmOffset4_20:
12056 return parseMemOffsetOperand(Operands);
12057 case MCK_UImmOffset4_0Minus1:
12058 return parseMemOffsetOperand(Operands);
12059 case MCK_UImmOffset5_20:
12060 return parseMemOffsetOperand(Operands);
12061 case MCK_SImmOffset7_2:
12062 return parseMemOffsetOperand(Operands);
12063 case MCK_UImmOffset6_00:
12064 return parseMemOffsetOperand(Operands);
12065 case MCK_SImmPtr:
12066 return parseMemOffsetOperand(Operands);
12067 case MCK_AnyOffset:
12068 return parseMemOffsetOperand(Operands);
12069 case MCK_CCRAsmReg:
12070 return parseAnyRegister(Operands);
12071 case MCK_COP0AsmReg:
12072 return parseAnyRegister(Operands);
12073 case MCK_COP2AsmReg:
12074 return parseAnyRegister(Operands);
12075 case MCK_COP3AsmReg:
12076 return parseAnyRegister(Operands);
12077 case MCK_FCCAsmReg:
12078 return parseAnyRegister(Operands);
12079 case MCK_FGR32AsmReg:
12080 return parseAnyRegister(Operands);
12081 case MCK_FGR64AsmReg:
12082 return parseAnyRegister(Operands);
12083 case MCK_GPR32AsmReg:
12084 return parseAnyRegister(Operands);
12085 case MCK_GPR32NonZeroAsmReg:
12086 return parseAnyRegister(Operands);
12087 case MCK_GPR32ZeroAsmReg:
12088 return parseAnyRegister(Operands);
12089 case MCK_GPR64AsmReg:
12090 return parseAnyRegister(Operands);
12091 case MCK_GPRMM16AsmReg:
12092 return parseAnyRegister(Operands);
12093 case MCK_GPRMM16AsmRegMoveP:
12094 return parseAnyRegister(Operands);
12095 case MCK_GPRMM16AsmRegMovePPairFirst:
12096 return parseAnyRegister(Operands);
12097 case MCK_GPRMM16AsmRegMovePPairSecond:
12098 return parseAnyRegister(Operands);
12099 case MCK_GPRMM16AsmRegZero:
12100 return parseAnyRegister(Operands);
12101 case MCK_HI32DSPAsmReg:
12102 return parseAnyRegister(Operands);
12103 case MCK_HWRegsAsmReg:
12104 return parseAnyRegister(Operands);
12105 case MCK_LO32DSPAsmReg:
12106 return parseAnyRegister(Operands);
12107 case MCK_MSA128AsmReg:
12108 return parseAnyRegister(Operands);
12109 case MCK_MSACtrlAsmReg:
12110 return parseAnyRegister(Operands);
12111 case MCK_InvNum:
12112 return parseInvNum(Operands);
12113 case MCK_JumpTarget:
12114 return parseJumpTarget(Operands);
12115 case MCK_Mem:
12116 return parseMemOperand(Operands);
12117 case MCK_MemBaseGP:
12118 return parseAnyRegister(Operands);
12119 case MCK_MemBaseSP:
12120 return parseAnyRegister(Operands);
12121 case MCK_PtrReg:
12122 return parseAnyRegister(Operands);
12123 case MCK_RegList16:
12124 return parseRegisterList(Operands);
12125 case MCK_RegList:
12126 return parseRegisterList(Operands);
12127 case MCK_StrictlyAFGR64AsmReg:
12128 return parseAnyRegister(Operands);
12129 case MCK_StrictlyFGR32AsmReg:
12130 return parseAnyRegister(Operands);
12131 case MCK_StrictlyFGR64AsmReg:
12132 return parseAnyRegister(Operands);
12133 default:
12134 return ParseStatus::NoMatch;
12135 }
12136 return ParseStatus::NoMatch;
12137}
12138
12139ParseStatus MipsAsmParser::
12140MatchOperandParserImpl(OperandVector &Operands,
12141 StringRef Mnemonic,
12142 bool ParseForAllFeatures) {
12143 // Get the current feature set.
12144 const FeatureBitset &AvailableFeatures = getAvailableFeatures();
12145
12146 // Get the next operand index.
12147 unsigned NextOpNum = Operands.size() - 1;
12148 // Search the table.
12149 auto MnemonicRange =
12150 std::equal_range(std::begin(OperandMatchTable), std::end(OperandMatchTable),
12151 Mnemonic, LessOpcodeOperand());
12152
12153 if (MnemonicRange.first == MnemonicRange.second)
12154 return ParseStatus::NoMatch;
12155
12156 for (const OperandMatchEntry *it = MnemonicRange.first,
12157 *ie = MnemonicRange.second; it != ie; ++it) {
12158 // equal_range guarantees that instruction mnemonic matches.
12159 assert(Mnemonic == it->getMnemonic());
12160
12161 // check if the available features match
12162 const FeatureBitset &RequiredFeatures = FeatureBitsets[it->RequiredFeaturesIdx];
12163 if (!ParseForAllFeatures && (AvailableFeatures & RequiredFeatures) != RequiredFeatures)
12164 continue;
12165
12166 // check if the operand in question has a custom parser.
12167 if (!(it->OperandMask & (1 << NextOpNum)))
12168 continue;
12169
12170 // call custom parse method to handle the operand
12171 ParseStatus Result = tryCustomParseOperand(Operands, it->Class);
12172 if (!Result.isNoMatch())
12173 return Result;
12174 }
12175
12176 // Okay, we had no match.
12177 return ParseStatus::NoMatch;
12178}
12179
12180#endif // GET_MATCHER_IMPLEMENTATION
12181
12182
12183#ifdef GET_MNEMONIC_SPELL_CHECKER
12184#undef GET_MNEMONIC_SPELL_CHECKER
12185
12186static std::string MipsMnemonicSpellCheck(StringRef S, const FeatureBitset &FBS, unsigned VariantID) {
12187 const unsigned MaxEditDist = 2;
12188 std::vector<StringRef> Candidates;
12189 StringRef Prev = "";
12190
12191 // Find the appropriate table for this asm variant.
12192 const MatchEntry *Start, *End;
12193 switch (VariantID) {
12194 default: llvm_unreachable("invalid variant!");
12195 case 0: Start = std::begin(MatchTable0); End = std::end(MatchTable0); break;
12196 }
12197
12198 for (auto I = Start; I < End; I++) {
12199 // Ignore unsupported instructions.
12200 const FeatureBitset &RequiredFeatures = FeatureBitsets[I->RequiredFeaturesIdx];
12201 if ((FBS & RequiredFeatures) != RequiredFeatures)
12202 continue;
12203
12204 StringRef T = I->getMnemonic();
12205 // Avoid recomputing the edit distance for the same string.
12206 if (T == Prev)
12207 continue;
12208
12209 Prev = T;
12210 unsigned Dist = S.edit_distance(T, false, MaxEditDist);
12211 if (Dist <= MaxEditDist)
12212 Candidates.push_back(T);
12213 }
12214
12215 if (Candidates.empty())
12216 return "";
12217
12218 std::string Res = ", did you mean: ";
12219 unsigned i = 0;
12220 for (; i < Candidates.size() - 1; i++)
12221 Res += Candidates[i].str() + ", ";
12222 return Res + Candidates[i].str() + "?";
12223}
12224
12225#endif // GET_MNEMONIC_SPELL_CHECKER
12226
12227
12228#ifdef GET_MNEMONIC_CHECKER
12229#undef GET_MNEMONIC_CHECKER
12230
12231static bool MipsCheckMnemonic(StringRef Mnemonic,
12232 const FeatureBitset &AvailableFeatures,
12233 unsigned VariantID) {
12234 // Find the appropriate table for this asm variant.
12235 const MatchEntry *Start, *End;
12236 switch (VariantID) {
12237 default: llvm_unreachable("invalid variant!");
12238 case 0: Start = std::begin(MatchTable0); End = std::end(MatchTable0); break;
12239 }
12240
12241 // Search the table.
12242 auto MnemonicRange = std::equal_range(Start, End, Mnemonic, LessOpcode());
12243
12244 if (MnemonicRange.first == MnemonicRange.second)
12245 return false;
12246
12247 for (const MatchEntry *it = MnemonicRange.first, *ie = MnemonicRange.second;
12248 it != ie; ++it) {
12249 const FeatureBitset &RequiredFeatures =
12250 FeatureBitsets[it->RequiredFeaturesIdx];
12251 if ((AvailableFeatures & RequiredFeatures) == RequiredFeatures)
12252 return true;
12253 }
12254 return false;
12255}
12256
12257#endif // GET_MNEMONIC_CHECKER
12258
12259