1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Assembly Matcher Source Fragment *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* From: Mips.td *|
7|* *|
8\*===----------------------------------------------------------------------===*/
9
10
11#ifdef GET_ASSEMBLER_HEADER
12#undef GET_ASSEMBLER_HEADER
13 // This should be included into the middle of the declaration of
14 // your subclasses implementation of MCTargetAsmParser.
15 FeatureBitset ComputeAvailableFeatures(const FeatureBitset &FB) const;
16 void convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode,
17 const OperandVector &Operands);
18 void convertToMapAndConstraints(unsigned Kind,
19 const OperandVector &Operands) override;
20 unsigned MatchInstructionImpl(const OperandVector &Operands,
21 MCInst &Inst,
22 uint64_t &ErrorInfo,
23 FeatureBitset &MissingFeatures,
24 bool matchingInlineAsm,
25 unsigned VariantID = 0);
26 unsigned MatchInstructionImpl(const OperandVector &Operands,
27 MCInst &Inst,
28 uint64_t &ErrorInfo,
29 bool matchingInlineAsm,
30 unsigned VariantID = 0) {
31 FeatureBitset MissingFeatures;
32 return MatchInstructionImpl(Operands, Inst, ErrorInfo, MissingFeatures,
33 matchingInlineAsm, VariantID);
34 }
35
36 ParseStatus MatchOperandParserImpl(
37 OperandVector &Operands,
38 StringRef Mnemonic,
39 bool ParseForAllFeatures = false);
40 ParseStatus tryCustomParseOperand(
41 OperandVector &Operands,
42 unsigned MCK);
43
44#endif // GET_ASSEMBLER_HEADER
45
46
47#ifdef GET_OPERAND_DIAGNOSTIC_TYPES
48#undef GET_OPERAND_DIAGNOSTIC_TYPES
49
50 Match_Immz,
51 Match_MemSImm10,
52 Match_MemSImm10Lsl1,
53 Match_MemSImm10Lsl2,
54 Match_MemSImm10Lsl3,
55 Match_MemSImm11,
56 Match_MemSImm12,
57 Match_MemSImm16,
58 Match_MemSImm9,
59 Match_MemSImmPtr,
60 Match_SImm10_0,
61 Match_SImm10_Lsl1,
62 Match_SImm10_Lsl2,
63 Match_SImm10_Lsl3,
64 Match_SImm11_0,
65 Match_SImm16,
66 Match_SImm16_Relaxed,
67 Match_SImm18_Lsl3,
68 Match_SImm19_Lsl2,
69 Match_SImm32,
70 Match_SImm32_Relaxed,
71 Match_SImm4_0,
72 Match_SImm5_0,
73 Match_SImm6_0,
74 Match_SImm7_Lsl2,
75 Match_SImm9_0,
76 Match_UImm10_0,
77 Match_UImm16,
78 Match_UImm16_AltRelaxed,
79 Match_UImm16_Relaxed,
80 Match_UImm1_0,
81 Match_UImm20_0,
82 Match_UImm26_0,
83 Match_UImm2_0,
84 Match_UImm2_1,
85 Match_UImm32_Coerced,
86 Match_UImm3_0,
87 Match_UImm4_0,
88 Match_UImm5_0,
89 Match_UImm5_0_Report_UImm6,
90 Match_UImm5_1,
91 Match_UImm5_32,
92 Match_UImm5_33,
93 Match_UImm5_Lsl2,
94 Match_UImm6_0,
95 Match_UImm6_Lsl2,
96 Match_UImm7_0,
97 Match_UImm7_N1,
98 Match_UImm8_0,
99 Match_UImmRange2_64,
100 END_OPERAND_DIAGNOSTIC_TYPES
101#endif // GET_OPERAND_DIAGNOSTIC_TYPES
102
103
104#ifdef GET_REGISTER_MATCHER
105#undef GET_REGISTER_MATCHER
106
107// Bits for subtarget features that participate in instruction matching.
108enum SubtargetFeatureBits : uint8_t {
109 Feature_IsPTR64bitBit = 37,
110 Feature_IsPTR32bitBit = 36,
111 Feature_UseCompactBranchesBit = 54,
112 Feature_HasMips2Bit = 11,
113 Feature_HasMips3_32Bit = 14,
114 Feature_HasMips3_32r2Bit = 15,
115 Feature_HasMips3Bit = 12,
116 Feature_NotMips3Bit = 48,
117 Feature_HasMips4_32Bit = 16,
118 Feature_NotMips4_32Bit = 49,
119 Feature_HasMips4_32r2Bit = 17,
120 Feature_HasMips5_32r2Bit = 18,
121 Feature_HasMips32Bit = 19,
122 Feature_HasMips32r2Bit = 20,
123 Feature_HasMips32r5Bit = 21,
124 Feature_HasMips32r6Bit = 22,
125 Feature_NotMips32r6Bit = 50,
126 Feature_IsGP64bitBit = 33,
127 Feature_IsGP32bitBit = 32,
128 Feature_HasMips64Bit = 23,
129 Feature_NotMips64Bit = 51,
130 Feature_HasMips64r2Bit = 24,
131 Feature_HasMips64r5Bit = 25,
132 Feature_HasMips64r6Bit = 26,
133 Feature_NotMips64r6Bit = 52,
134 Feature_InMips16ModeBit = 30,
135 Feature_NotInMips16ModeBit = 47,
136 Feature_HasCnMipsBit = 1,
137 Feature_NotCnMipsBit = 43,
138 Feature_HasCnMipsPBit = 2,
139 Feature_NotCnMipsPBit = 44,
140 Feature_IsSym32Bit = 40,
141 Feature_IsSym64Bit = 41,
142 Feature_HasStdEncBit = 27,
143 Feature_InMicroMipsBit = 29,
144 Feature_NotInMicroMipsBit = 46,
145 Feature_HasEVABit = 6,
146 Feature_HasMSABit = 8,
147 Feature_HasMadd4Bit = 10,
148 Feature_HasMTBit = 9,
149 Feature_UseIndirectJumpsHazardBit = 55,
150 Feature_NoIndirectJumpGuardsBit = 42,
151 Feature_IsR5900Bit = 38,
152 Feature_NotR5900Bit = 53,
153 Feature_HasCRCBit = 0,
154 Feature_HasVirtBit = 28,
155 Feature_HasGINVBit = 7,
156 Feature_IsFP64bitBit = 31,
157 Feature_NotFP64bitBit = 45,
158 Feature_IsSingleFloatBit = 39,
159 Feature_IsNotSingleFloatBit = 34,
160 Feature_IsNotSoftFloatBit = 35,
161 Feature_HasMips3DBit = 13,
162 Feature_HasDSPBit = 3,
163 Feature_HasDSPR2Bit = 4,
164 Feature_HasDSPR3Bit = 5,
165};
166
167[[maybe_unused]] static MCRegister MatchRegisterName(StringRef Name) {
168 switch (Name.size()) {
169 default: break;
170 case 1: // 74 strings to match.
171 switch (Name[0]) {
172 default: break;
173 case '0': // 5 strings to match.
174 return Mips::MSAIR; // "0"
175 case '1': // 7 strings to match.
176 return Mips::AT; // "1"
177 case '2': // 7 strings to match.
178 return Mips::MSAAccess; // "2"
179 case '3': // 7 strings to match.
180 return Mips::MSASave; // "3"
181 case '4': // 8 strings to match.
182 return Mips::MSAModify; // "4"
183 case '5': // 8 strings to match.
184 return Mips::MSARequest; // "5"
185 case '6': // 8 strings to match.
186 return Mips::MSAMap; // "6"
187 case '7': // 8 strings to match.
188 return Mips::MSAUnmap; // "7"
189 case '8': // 8 strings to match.
190 return Mips::COP08; // "8"
191 case '9': // 8 strings to match.
192 return Mips::COP09; // "9"
193 }
194 break;
195 case 2: // 227 strings to match.
196 switch (Name[0]) {
197 default: break;
198 case '1': // 80 strings to match.
199 switch (Name[1]) {
200 default: break;
201 case '0': // 8 strings to match.
202 return Mips::COP010; // "10"
203 case '1': // 8 strings to match.
204 return Mips::COP011; // "11"
205 case '2': // 8 strings to match.
206 return Mips::COP012; // "12"
207 case '3': // 8 strings to match.
208 return Mips::COP013; // "13"
209 case '4': // 8 strings to match.
210 return Mips::COP014; // "14"
211 case '5': // 8 strings to match.
212 return Mips::COP015; // "15"
213 case '6': // 8 strings to match.
214 return Mips::COP016; // "16"
215 case '7': // 8 strings to match.
216 return Mips::COP017; // "17"
217 case '8': // 8 strings to match.
218 return Mips::COP018; // "18"
219 case '9': // 8 strings to match.
220 return Mips::COP019; // "19"
221 }
222 break;
223 case '2': // 76 strings to match.
224 switch (Name[1]) {
225 default: break;
226 case '0': // 8 strings to match.
227 return Mips::COP020; // "20"
228 case '1': // 8 strings to match.
229 return Mips::COP021; // "21"
230 case '2': // 8 strings to match.
231 return Mips::COP022; // "22"
232 case '3': // 8 strings to match.
233 return Mips::COP023; // "23"
234 case '4': // 8 strings to match.
235 return Mips::COP024; // "24"
236 case '5': // 8 strings to match.
237 return Mips::COP025; // "25"
238 case '6': // 8 strings to match.
239 return Mips::COP026; // "26"
240 case '7': // 8 strings to match.
241 return Mips::COP027; // "27"
242 case '8': // 6 strings to match.
243 return Mips::COP028; // "28"
244 case '9': // 6 strings to match.
245 return Mips::COP029; // "29"
246 }
247 break;
248 case '3': // 12 strings to match.
249 switch (Name[1]) {
250 default: break;
251 case '0': // 6 strings to match.
252 return Mips::COP030; // "30"
253 case '1': // 6 strings to match.
254 return Mips::COP031; // "31"
255 }
256 break;
257 case 'f': // 37 strings to match.
258 switch (Name[1]) {
259 default: break;
260 case '0': // 4 strings to match.
261 return Mips::D0; // "f0"
262 case '1': // 3 strings to match.
263 return Mips::F1; // "f1"
264 case '2': // 4 strings to match.
265 return Mips::D1; // "f2"
266 case '3': // 3 strings to match.
267 return Mips::F3; // "f3"
268 case '4': // 4 strings to match.
269 return Mips::D2; // "f4"
270 case '5': // 3 strings to match.
271 return Mips::F5; // "f5"
272 case '6': // 4 strings to match.
273 return Mips::D3; // "f6"
274 case '7': // 3 strings to match.
275 return Mips::F7; // "f7"
276 case '8': // 4 strings to match.
277 return Mips::D4; // "f8"
278 case '9': // 3 strings to match.
279 return Mips::F9; // "f9"
280 case 'p': // 2 strings to match.
281 return Mips::FP; // "fp"
282 }
283 break;
284 case 'g': // 2 strings to match.
285 if (Name[1] != 'p')
286 break;
287 return Mips::GP; // "gp"
288 case 'h': // 1 string to match.
289 if (Name[1] != 'i')
290 break;
291 return Mips::HI0_64; // "hi"
292 case 'l': // 1 string to match.
293 if (Name[1] != 'o')
294 break;
295 return Mips::LO0_64; // "lo"
296 case 'p': // 4 strings to match.
297 switch (Name[1]) {
298 default: break;
299 case '0': // 1 string to match.
300 return Mips::P0; // "p0"
301 case '1': // 1 string to match.
302 return Mips::P1; // "p1"
303 case '2': // 1 string to match.
304 return Mips::P2; // "p2"
305 case 'c': // 1 string to match.
306 return Mips::PC; // "pc"
307 }
308 break;
309 case 'r': // 2 strings to match.
310 if (Name[1] != 'a')
311 break;
312 return Mips::RA; // "ra"
313 case 's': // 2 strings to match.
314 if (Name[1] != 'p')
315 break;
316 return Mips::SP; // "sp"
317 case 'w': // 10 strings to match.
318 switch (Name[1]) {
319 default: break;
320 case '0': // 1 string to match.
321 return Mips::W0; // "w0"
322 case '1': // 1 string to match.
323 return Mips::W1; // "w1"
324 case '2': // 1 string to match.
325 return Mips::W2; // "w2"
326 case '3': // 1 string to match.
327 return Mips::W3; // "w3"
328 case '4': // 1 string to match.
329 return Mips::W4; // "w4"
330 case '5': // 1 string to match.
331 return Mips::W5; // "w5"
332 case '6': // 1 string to match.
333 return Mips::W6; // "w6"
334 case '7': // 1 string to match.
335 return Mips::W7; // "w7"
336 case '8': // 1 string to match.
337 return Mips::W8; // "w8"
338 case '9': // 1 string to match.
339 return Mips::W9; // "w9"
340 }
341 break;
342 }
343 break;
344 case 3: // 112 strings to match.
345 switch (Name[0]) {
346 default: break;
347 case 'a': // 13 strings to match.
348 if (Name[1] != 'c')
349 break;
350 switch (Name[2]) {
351 default: break;
352 case '0': // 4 strings to match.
353 return Mips::AC0; // "ac0"
354 case '1': // 3 strings to match.
355 return Mips::AC1; // "ac1"
356 case '2': // 3 strings to match.
357 return Mips::AC2; // "ac2"
358 case '3': // 3 strings to match.
359 return Mips::AC3; // "ac3"
360 }
361 break;
362 case 'f': // 77 strings to match.
363 switch (Name[1]) {
364 default: break;
365 case '1': // 35 strings to match.
366 switch (Name[2]) {
367 default: break;
368 case '0': // 4 strings to match.
369 return Mips::D5; // "f10"
370 case '1': // 3 strings to match.
371 return Mips::F11; // "f11"
372 case '2': // 4 strings to match.
373 return Mips::D6; // "f12"
374 case '3': // 3 strings to match.
375 return Mips::F13; // "f13"
376 case '4': // 4 strings to match.
377 return Mips::D7; // "f14"
378 case '5': // 3 strings to match.
379 return Mips::F15; // "f15"
380 case '6': // 4 strings to match.
381 return Mips::D8; // "f16"
382 case '7': // 3 strings to match.
383 return Mips::F17; // "f17"
384 case '8': // 4 strings to match.
385 return Mips::D9; // "f18"
386 case '9': // 3 strings to match.
387 return Mips::F19; // "f19"
388 }
389 break;
390 case '2': // 35 strings to match.
391 switch (Name[2]) {
392 default: break;
393 case '0': // 4 strings to match.
394 return Mips::D10; // "f20"
395 case '1': // 3 strings to match.
396 return Mips::F21; // "f21"
397 case '2': // 4 strings to match.
398 return Mips::D11; // "f22"
399 case '3': // 3 strings to match.
400 return Mips::F23; // "f23"
401 case '4': // 4 strings to match.
402 return Mips::D12; // "f24"
403 case '5': // 3 strings to match.
404 return Mips::F25; // "f25"
405 case '6': // 4 strings to match.
406 return Mips::D13; // "f26"
407 case '7': // 3 strings to match.
408 return Mips::F27; // "f27"
409 case '8': // 4 strings to match.
410 return Mips::D14; // "f28"
411 case '9': // 3 strings to match.
412 return Mips::F29; // "f29"
413 }
414 break;
415 case '3': // 7 strings to match.
416 switch (Name[2]) {
417 default: break;
418 case '0': // 4 strings to match.
419 return Mips::D15; // "f30"
420 case '1': // 3 strings to match.
421 return Mips::F31; // "f31"
422 }
423 break;
424 }
425 break;
426 case 'w': // 22 strings to match.
427 switch (Name[1]) {
428 default: break;
429 case '1': // 10 strings to match.
430 switch (Name[2]) {
431 default: break;
432 case '0': // 1 string to match.
433 return Mips::W10; // "w10"
434 case '1': // 1 string to match.
435 return Mips::W11; // "w11"
436 case '2': // 1 string to match.
437 return Mips::W12; // "w12"
438 case '3': // 1 string to match.
439 return Mips::W13; // "w13"
440 case '4': // 1 string to match.
441 return Mips::W14; // "w14"
442 case '5': // 1 string to match.
443 return Mips::W15; // "w15"
444 case '6': // 1 string to match.
445 return Mips::W16; // "w16"
446 case '7': // 1 string to match.
447 return Mips::W17; // "w17"
448 case '8': // 1 string to match.
449 return Mips::W18; // "w18"
450 case '9': // 1 string to match.
451 return Mips::W19; // "w19"
452 }
453 break;
454 case '2': // 10 strings to match.
455 switch (Name[2]) {
456 default: break;
457 case '0': // 1 string to match.
458 return Mips::W20; // "w20"
459 case '1': // 1 string to match.
460 return Mips::W21; // "w21"
461 case '2': // 1 string to match.
462 return Mips::W22; // "w22"
463 case '3': // 1 string to match.
464 return Mips::W23; // "w23"
465 case '4': // 1 string to match.
466 return Mips::W24; // "w24"
467 case '5': // 1 string to match.
468 return Mips::W25; // "w25"
469 case '6': // 1 string to match.
470 return Mips::W26; // "w26"
471 case '7': // 1 string to match.
472 return Mips::W27; // "w27"
473 case '8': // 1 string to match.
474 return Mips::W28; // "w28"
475 case '9': // 1 string to match.
476 return Mips::W29; // "w29"
477 }
478 break;
479 case '3': // 2 strings to match.
480 switch (Name[2]) {
481 default: break;
482 case '0': // 1 string to match.
483 return Mips::W30; // "w30"
484 case '1': // 1 string to match.
485 return Mips::W31; // "w31"
486 }
487 break;
488 }
489 break;
490 }
491 break;
492 case 4: // 13 strings to match.
493 switch (Name[0]) {
494 default: break;
495 case 'f': // 8 strings to match.
496 if (memcmp(Name.data()+1, "cc", 2) != 0)
497 break;
498 switch (Name[3]) {
499 default: break;
500 case '0': // 1 string to match.
501 return Mips::FCC0; // "fcc0"
502 case '1': // 1 string to match.
503 return Mips::FCC1; // "fcc1"
504 case '2': // 1 string to match.
505 return Mips::FCC2; // "fcc2"
506 case '3': // 1 string to match.
507 return Mips::FCC3; // "fcc3"
508 case '4': // 1 string to match.
509 return Mips::FCC4; // "fcc4"
510 case '5': // 1 string to match.
511 return Mips::FCC5; // "fcc5"
512 case '6': // 1 string to match.
513 return Mips::FCC6; // "fcc6"
514 case '7': // 1 string to match.
515 return Mips::FCC7; // "fcc7"
516 }
517 break;
518 case 'm': // 3 strings to match.
519 if (memcmp(Name.data()+1, "pl", 2) != 0)
520 break;
521 switch (Name[3]) {
522 default: break;
523 case '0': // 1 string to match.
524 return Mips::MPL0; // "mpl0"
525 case '1': // 1 string to match.
526 return Mips::MPL1; // "mpl1"
527 case '2': // 1 string to match.
528 return Mips::MPL2; // "mpl2"
529 }
530 break;
531 case 'z': // 2 strings to match.
532 if (memcmp(Name.data()+1, "ero", 3) != 0)
533 break;
534 return Mips::ZERO; // "zero"
535 }
536 break;
537 case 6: // 1 string to match.
538 if (memcmp(Name.data()+0, "hwr_cc", 6) != 0)
539 break;
540 return Mips::HWR2; // "hwr_cc"
541 case 9: // 1 string to match.
542 if (memcmp(Name.data()+0, "hwr_ccres", 9) != 0)
543 break;
544 return Mips::HWR3; // "hwr_ccres"
545 case 10: // 1 string to match.
546 if (memcmp(Name.data()+0, "hwr_cpunum", 10) != 0)
547 break;
548 return Mips::HWR0; // "hwr_cpunum"
549 case 14: // 1 string to match.
550 if (memcmp(Name.data()+0, "hwr_synci_step", 14) != 0)
551 break;
552 return Mips::HWR1; // "hwr_synci_step"
553 }
554 return Mips::NoRegister;
555}
556
557[[maybe_unused]] static MCRegister MatchRegisterAltName(StringRef Name, unsigned AltIdx) {
558 switch (AltIdx) {
559 default: break;
560 case Mips::NABIRegAltName: {
561 switch (Name.size()) {
562 default: break;
563 case 2: // 62 strings to match.
564 switch (Name[0]) {
565 default: break;
566 case 'a': // 18 strings to match.
567 switch (Name[1]) {
568 default: break;
569 case '0': // 2 strings to match.
570 return Mips::A0; // "a0"
571 case '1': // 2 strings to match.
572 return Mips::A1; // "a1"
573 case '2': // 2 strings to match.
574 return Mips::A2; // "a2"
575 case '3': // 2 strings to match.
576 return Mips::A3; // "a3"
577 case '4': // 2 strings to match.
578 return Mips::T0; // "a4"
579 case '5': // 2 strings to match.
580 return Mips::T1; // "a5"
581 case '6': // 2 strings to match.
582 return Mips::T2; // "a6"
583 case '7': // 2 strings to match.
584 return Mips::T3; // "a7"
585 case 't': // 2 strings to match.
586 return Mips::AT; // "at"
587 }
588 break;
589 case 'f': // 2 strings to match.
590 if (Name[1] != 'p')
591 break;
592 return Mips::FP; // "fp"
593 case 'g': // 2 strings to match.
594 if (Name[1] != 'p')
595 break;
596 return Mips::GP; // "gp"
597 case 'k': // 4 strings to match.
598 switch (Name[1]) {
599 default: break;
600 case '0': // 2 strings to match.
601 return Mips::K0; // "k0"
602 case '1': // 2 strings to match.
603 return Mips::K1; // "k1"
604 }
605 break;
606 case 'r': // 2 strings to match.
607 if (Name[1] != 'a')
608 break;
609 return Mips::RA; // "ra"
610 case 's': // 18 strings to match.
611 switch (Name[1]) {
612 default: break;
613 case '0': // 2 strings to match.
614 return Mips::S0; // "s0"
615 case '1': // 2 strings to match.
616 return Mips::S1; // "s1"
617 case '2': // 2 strings to match.
618 return Mips::S2; // "s2"
619 case '3': // 2 strings to match.
620 return Mips::S3; // "s3"
621 case '4': // 2 strings to match.
622 return Mips::S4; // "s4"
623 case '5': // 2 strings to match.
624 return Mips::S5; // "s5"
625 case '6': // 2 strings to match.
626 return Mips::S6; // "s6"
627 case '7': // 2 strings to match.
628 return Mips::S7; // "s7"
629 case 'p': // 2 strings to match.
630 return Mips::SP; // "sp"
631 }
632 break;
633 case 't': // 12 strings to match.
634 switch (Name[1]) {
635 default: break;
636 case '0': // 2 strings to match.
637 return Mips::T4; // "t0"
638 case '1': // 2 strings to match.
639 return Mips::T5; // "t1"
640 case '2': // 2 strings to match.
641 return Mips::T6; // "t2"
642 case '3': // 2 strings to match.
643 return Mips::T7; // "t3"
644 case '8': // 2 strings to match.
645 return Mips::T8; // "t8"
646 case '9': // 2 strings to match.
647 return Mips::T9; // "t9"
648 }
649 break;
650 case 'v': // 4 strings to match.
651 switch (Name[1]) {
652 default: break;
653 case '0': // 2 strings to match.
654 return Mips::V0; // "v0"
655 case '1': // 2 strings to match.
656 return Mips::V1; // "v1"
657 }
658 break;
659 }
660 break;
661 case 4: // 2 strings to match.
662 if (memcmp(Name.data()+0, "zero", 4) != 0)
663 break;
664 return Mips::ZERO; // "zero"
665 }
666 break;
667 }
668 case Mips::OABIRegAltName: {
669 switch (Name.size()) {
670 default: break;
671 case 2: // 62 strings to match.
672 switch (Name[0]) {
673 default: break;
674 case 'a': // 10 strings to match.
675 switch (Name[1]) {
676 default: break;
677 case '0': // 2 strings to match.
678 return Mips::A0; // "a0"
679 case '1': // 2 strings to match.
680 return Mips::A1; // "a1"
681 case '2': // 2 strings to match.
682 return Mips::A2; // "a2"
683 case '3': // 2 strings to match.
684 return Mips::A3; // "a3"
685 case 't': // 2 strings to match.
686 return Mips::AT; // "at"
687 }
688 break;
689 case 'f': // 2 strings to match.
690 if (Name[1] != 'p')
691 break;
692 return Mips::FP; // "fp"
693 case 'g': // 2 strings to match.
694 if (Name[1] != 'p')
695 break;
696 return Mips::GP; // "gp"
697 case 'k': // 4 strings to match.
698 switch (Name[1]) {
699 default: break;
700 case '0': // 2 strings to match.
701 return Mips::K0; // "k0"
702 case '1': // 2 strings to match.
703 return Mips::K1; // "k1"
704 }
705 break;
706 case 'r': // 2 strings to match.
707 if (Name[1] != 'a')
708 break;
709 return Mips::RA; // "ra"
710 case 's': // 18 strings to match.
711 switch (Name[1]) {
712 default: break;
713 case '0': // 2 strings to match.
714 return Mips::S0; // "s0"
715 case '1': // 2 strings to match.
716 return Mips::S1; // "s1"
717 case '2': // 2 strings to match.
718 return Mips::S2; // "s2"
719 case '3': // 2 strings to match.
720 return Mips::S3; // "s3"
721 case '4': // 2 strings to match.
722 return Mips::S4; // "s4"
723 case '5': // 2 strings to match.
724 return Mips::S5; // "s5"
725 case '6': // 2 strings to match.
726 return Mips::S6; // "s6"
727 case '7': // 2 strings to match.
728 return Mips::S7; // "s7"
729 case 'p': // 2 strings to match.
730 return Mips::SP; // "sp"
731 }
732 break;
733 case 't': // 20 strings to match.
734 switch (Name[1]) {
735 default: break;
736 case '0': // 2 strings to match.
737 return Mips::T0; // "t0"
738 case '1': // 2 strings to match.
739 return Mips::T1; // "t1"
740 case '2': // 2 strings to match.
741 return Mips::T2; // "t2"
742 case '3': // 2 strings to match.
743 return Mips::T3; // "t3"
744 case '4': // 2 strings to match.
745 return Mips::T4; // "t4"
746 case '5': // 2 strings to match.
747 return Mips::T5; // "t5"
748 case '6': // 2 strings to match.
749 return Mips::T6; // "t6"
750 case '7': // 2 strings to match.
751 return Mips::T7; // "t7"
752 case '8': // 2 strings to match.
753 return Mips::T8; // "t8"
754 case '9': // 2 strings to match.
755 return Mips::T9; // "t9"
756 }
757 break;
758 case 'v': // 4 strings to match.
759 switch (Name[1]) {
760 default: break;
761 case '0': // 2 strings to match.
762 return Mips::V0; // "v0"
763 case '1': // 2 strings to match.
764 return Mips::V1; // "v1"
765 }
766 break;
767 }
768 break;
769 case 4: // 2 strings to match.
770 if (memcmp(Name.data()+0, "zero", 4) != 0)
771 break;
772 return Mips::ZERO; // "zero"
773 }
774 break;
775 }
776 case Mips::PABIRegAltName: {
777 switch (Name.size()) {
778 default: break;
779 case 2: // 62 strings to match.
780 switch (Name[0]) {
781 default: break;
782 case 'a': // 18 strings to match.
783 switch (Name[1]) {
784 default: break;
785 case '0': // 2 strings to match.
786 return Mips::A0; // "a0"
787 case '1': // 2 strings to match.
788 return Mips::A1; // "a1"
789 case '2': // 2 strings to match.
790 return Mips::A2; // "a2"
791 case '3': // 2 strings to match.
792 return Mips::A3; // "a3"
793 case '4': // 2 strings to match.
794 return Mips::T0; // "a4"
795 case '5': // 2 strings to match.
796 return Mips::T1; // "a5"
797 case '6': // 2 strings to match.
798 return Mips::T2; // "a6"
799 case '7': // 2 strings to match.
800 return Mips::T3; // "a7"
801 case 't': // 2 strings to match.
802 return Mips::AT; // "at"
803 }
804 break;
805 case 'f': // 2 strings to match.
806 if (Name[1] != 'p')
807 break;
808 return Mips::FP; // "fp"
809 case 'g': // 2 strings to match.
810 if (Name[1] != 'p')
811 break;
812 return Mips::GP; // "gp"
813 case 'k': // 4 strings to match.
814 switch (Name[1]) {
815 default: break;
816 case '0': // 2 strings to match.
817 return Mips::K0; // "k0"
818 case '1': // 2 strings to match.
819 return Mips::K1; // "k1"
820 }
821 break;
822 case 'r': // 2 strings to match.
823 if (Name[1] != 'a')
824 break;
825 return Mips::RA; // "ra"
826 case 's': // 18 strings to match.
827 switch (Name[1]) {
828 default: break;
829 case '0': // 2 strings to match.
830 return Mips::S0; // "s0"
831 case '1': // 2 strings to match.
832 return Mips::S1; // "s1"
833 case '2': // 2 strings to match.
834 return Mips::S2; // "s2"
835 case '3': // 2 strings to match.
836 return Mips::S3; // "s3"
837 case '4': // 2 strings to match.
838 return Mips::S4; // "s4"
839 case '5': // 2 strings to match.
840 return Mips::S5; // "s5"
841 case '6': // 2 strings to match.
842 return Mips::S6; // "s6"
843 case '7': // 2 strings to match.
844 return Mips::S7; // "s7"
845 case 'p': // 2 strings to match.
846 return Mips::SP; // "sp"
847 }
848 break;
849 case 't': // 16 strings to match.
850 switch (Name[1]) {
851 default: break;
852 case '0': // 2 strings to match.
853 return Mips::T4; // "t0"
854 case '1': // 2 strings to match.
855 return Mips::T5; // "t1"
856 case '2': // 2 strings to match.
857 return Mips::T6; // "t2"
858 case '3': // 2 strings to match.
859 return Mips::T7; // "t3"
860 case '4': // 2 strings to match.
861 return Mips::V0; // "t4"
862 case '5': // 2 strings to match.
863 return Mips::V1; // "t5"
864 case '8': // 2 strings to match.
865 return Mips::T8; // "t8"
866 case '9': // 2 strings to match.
867 return Mips::T9; // "t9"
868 }
869 break;
870 }
871 break;
872 case 4: // 2 strings to match.
873 if (memcmp(Name.data()+0, "zero", 4) != 0)
874 break;
875 return Mips::ZERO; // "zero"
876 }
877 break;
878 }
879 case Mips::RegAliasName: {
880 switch (Name.size()) {
881 default: break;
882 case 2: // 2 strings to match.
883 switch (Name[0]) {
884 default: break;
885 case 'h': // 1 string to match.
886 if (Name[1] != 'i')
887 break;
888 return Mips::HI0; // "hi"
889 case 'l': // 1 string to match.
890 if (Name[1] != 'o')
891 break;
892 return Mips::LO0; // "lo"
893 }
894 break;
895 case 5: // 1 string to match.
896 if (memcmp(Name.data()+0, "msair", 5) != 0)
897 break;
898 return Mips::MSAIR; // "msair"
899 case 6: // 2 strings to match.
900 if (memcmp(Name.data()+0, "msa", 3) != 0)
901 break;
902 switch (Name[3]) {
903 default: break;
904 case 'c': // 1 string to match.
905 if (memcmp(Name.data()+4, "sr", 2) != 0)
906 break;
907 return Mips::MSACSR; // "msacsr"
908 case 'm': // 1 string to match.
909 if (memcmp(Name.data()+4, "ap", 2) != 0)
910 break;
911 return Mips::MSAMap; // "msamap"
912 }
913 break;
914 case 7: // 2 strings to match.
915 switch (Name[0]) {
916 default: break;
917 case 'h': // 1 string to match.
918 if (memcmp(Name.data()+1, "wr_ulr", 6) != 0)
919 break;
920 return Mips::HWR29; // "hwr_ulr"
921 case 'm': // 1 string to match.
922 if (memcmp(Name.data()+1, "sasave", 6) != 0)
923 break;
924 return Mips::MSASave; // "msasave"
925 }
926 break;
927 case 8: // 1 string to match.
928 if (memcmp(Name.data()+0, "msaunmap", 8) != 0)
929 break;
930 return Mips::MSAUnmap; // "msaunmap"
931 case 9: // 2 strings to match.
932 if (memcmp(Name.data()+0, "msa", 3) != 0)
933 break;
934 switch (Name[3]) {
935 default: break;
936 case 'a': // 1 string to match.
937 if (memcmp(Name.data()+4, "ccess", 5) != 0)
938 break;
939 return Mips::MSAAccess; // "msaaccess"
940 case 'm': // 1 string to match.
941 if (memcmp(Name.data()+4, "odify", 5) != 0)
942 break;
943 return Mips::MSAModify; // "msamodify"
944 }
945 break;
946 case 10: // 1 string to match.
947 if (memcmp(Name.data()+0, "msarequest", 10) != 0)
948 break;
949 return Mips::MSARequest; // "msarequest"
950 }
951 break;
952 }
953 }
954 return Mips::NoRegister;
955}
956
957#endif // GET_REGISTER_MATCHER
958
959
960#ifdef GET_SUBTARGET_FEATURE_NAME
961#undef GET_SUBTARGET_FEATURE_NAME
962
963// User-level names for subtarget features that participate in
964// instruction matching.
965static const char *getSubtargetFeatureName(uint64_t Val) {
966 switch(Val) {
967 case Feature_IsPTR64bitBit: return "";
968 case Feature_IsPTR32bitBit: return "";
969 case Feature_UseCompactBranchesBit: return "";
970 case Feature_HasMips2Bit: return "";
971 case Feature_HasMips3_32Bit: return "";
972 case Feature_HasMips3_32r2Bit: return "";
973 case Feature_HasMips3Bit: return "";
974 case Feature_NotMips3Bit: return "";
975 case Feature_HasMips4_32Bit: return "";
976 case Feature_NotMips4_32Bit: return "";
977 case Feature_HasMips4_32r2Bit: return "";
978 case Feature_HasMips5_32r2Bit: return "";
979 case Feature_HasMips32Bit: return "";
980 case Feature_HasMips32r2Bit: return "";
981 case Feature_HasMips32r5Bit: return "";
982 case Feature_HasMips32r6Bit: return "";
983 case Feature_NotMips32r6Bit: return "";
984 case Feature_IsGP64bitBit: return "";
985 case Feature_IsGP32bitBit: return "";
986 case Feature_HasMips64Bit: return "";
987 case Feature_NotMips64Bit: return "";
988 case Feature_HasMips64r2Bit: return "";
989 case Feature_HasMips64r5Bit: return "";
990 case Feature_HasMips64r6Bit: return "";
991 case Feature_NotMips64r6Bit: return "";
992 case Feature_InMips16ModeBit: return "";
993 case Feature_NotInMips16ModeBit: return "";
994 case Feature_HasCnMipsBit: return "";
995 case Feature_NotCnMipsBit: return "";
996 case Feature_HasCnMipsPBit: return "";
997 case Feature_NotCnMipsPBit: return "";
998 case Feature_IsSym32Bit: return "";
999 case Feature_IsSym64Bit: return "";
1000 case Feature_HasStdEncBit: return "";
1001 case Feature_InMicroMipsBit: return "";
1002 case Feature_NotInMicroMipsBit: return "";
1003 case Feature_HasEVABit: return "";
1004 case Feature_HasMSABit: return "";
1005 case Feature_HasMadd4Bit: return "";
1006 case Feature_HasMTBit: return "";
1007 case Feature_UseIndirectJumpsHazardBit: return "";
1008 case Feature_NoIndirectJumpGuardsBit: return "";
1009 case Feature_IsR5900Bit: return "";
1010 case Feature_NotR5900Bit: return "";
1011 case Feature_HasCRCBit: return "";
1012 case Feature_HasVirtBit: return "";
1013 case Feature_HasGINVBit: return "";
1014 case Feature_IsFP64bitBit: return "";
1015 case Feature_NotFP64bitBit: return "";
1016 case Feature_IsSingleFloatBit: return "";
1017 case Feature_IsNotSingleFloatBit: return "";
1018 case Feature_IsNotSoftFloatBit: return "";
1019 case Feature_HasMips3DBit: return "";
1020 case Feature_HasDSPBit: return "";
1021 case Feature_HasDSPR2Bit: return "";
1022 case Feature_HasDSPR3Bit: return "";
1023 default: return "(unknown)";
1024 }
1025}
1026
1027#endif // GET_SUBTARGET_FEATURE_NAME
1028
1029
1030#ifdef GET_MATCHER_IMPLEMENTATION
1031#undef GET_MATCHER_IMPLEMENTATION
1032
1033enum {
1034 Tie0_1_1,
1035 Tie0_1_2,
1036};
1037
1038static const uint8_t TiedAsmOperandTable[][3] = {
1039 /* Tie0_1_1 */ { 0, 1, 1 },
1040 /* Tie0_1_2 */ { 0, 1, 2 },
1041};
1042
1043namespace {
1044enum OperatorConversionKind {
1045 CVT_Done,
1046 CVT_Reg,
1047 CVT_Tied,
1048 CVT_95_addGPR32AsmRegOperands,
1049 CVT_95_addAFGR64AsmRegOperands,
1050 CVT_95_addFGR64AsmRegOperands,
1051 CVT_95_addFGR32AsmRegOperands,
1052 CVT_95_addSImmOperands_LT_32_GT_,
1053 CVT_95_addMSA128AsmRegOperands,
1054 CVT_95_addSImmOperands_LT_16_GT_,
1055 CVT_95_Reg,
1056 CVT_95_addImmOperands,
1057 CVT_95_addGPRMM16AsmRegOperands,
1058 CVT_95_addConstantSImmOperands_LT_4_44__32_0_GT_,
1059 CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_,
1060 CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_,
1061 CVT_95_addUImmOperands_LT_16_GT_,
1062 CVT_95_addGPR64AsmRegOperands,
1063 CVT_95_addConstantUImmOperands_LT_8_44__32_0_GT_,
1064 CVT_regZERO,
1065 CVT_95_addConstantUImmOperands_LT_5_44__32_32_44__32__MINUS_32_GT_,
1066 CVT_regFCC0,
1067 CVT_95_addFCCAsmRegOperands,
1068 CVT_95_addCOP2AsmRegOperands,
1069 CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_,
1070 CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_,
1071 CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_,
1072 CVT_imm_95_0,
1073 CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_,
1074 CVT_95_addMemOperands,
1075 CVT_95_addConstantSImmOperands_LT_5_44__32_0_GT_,
1076 CVT_95_addCCRAsmRegOperands,
1077 CVT_95_addMSACtrlAsmRegOperands,
1078 CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_,
1079 CVT_95_addConstantUImmOperands_LT_5_44__32_33_GT_,
1080 CVT_95_addConstantUImmOperands_LT_5_44__32_32_GT_,
1081 CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_,
1082 CVT_95_addGPR32NonZeroAsmRegOperands,
1083 CVT_95_addGPR32ZeroAsmRegOperands,
1084 CVT_95_addConstantUImmOperands_LT_2_44__32_1_GT_,
1085 CVT_95_addCOP0AsmRegOperands,
1086 CVT_regZERO_64,
1087 CVT_95_addACC64DSPAsmRegOperands,
1088 CVT_95_addConstantUImmOperands_LT_1_GT_,
1089 CVT_regRA,
1090 CVT_regRA_64,
1091 CVT_95_addMicroMipsMemOperands,
1092 CVT_95_addCOP3AsmRegOperands,
1093 CVT_95_addConstantSImmOperands_LT_10_44__32_0_GT_,
1094 CVT_95_addConstantUImmOperands_LT_32_GT_,
1095 CVT_95_addStrictlyAFGR64AsmRegOperands,
1096 CVT_95_addStrictlyFGR64AsmRegOperands,
1097 CVT_95_addStrictlyFGR32AsmRegOperands,
1098 CVT_95_addConstantUImmOperands_LT_7_44__32__MINUS_1_GT_,
1099 CVT_95_addRegListOperands,
1100 CVT_ConvertXWPOperands,
1101 CVT_regAC0,
1102 CVT_95_addGPRMM16AsmRegMovePPairFirstOperands,
1103 CVT_95_addGPRMM16AsmRegMovePPairSecondOperands,
1104 CVT_95_addGPRMM16AsmRegMovePOperands,
1105 CVT_95_addHI32DSPAsmRegOperands,
1106 CVT_95_addLO32DSPAsmRegOperands,
1107 CVT_regS0,
1108 CVT_95_addConstantUImmOperands_LT_7_44__32_0_GT_,
1109 CVT_95_addHWRegsAsmRegOperands,
1110 CVT_95_addGPRMM16AsmRegZeroOperands,
1111 CVT_95_addConstantUImmOperands_LT_20_44__32_0_GT_,
1112 CVT_95_addConstantSImmOperands_LT_6_44__32_0_GT_,
1113 CVT_imm_95_17,
1114 CVT_imm_95_16,
1115 CVT_imm_95_18,
1116 CVT_imm_95_19,
1117 CVT_imm_95_4,
1118 CVT_imm_95_2,
1119 CVT_imm_95_6,
1120 CVT_imm_95_5,
1121 CVT_imm_95_31,
1122 CVT_NUM_CONVERTERS
1123};
1124
1125enum InstructionConversionKind {
1126 Convert__GPR32AsmReg1_0__GPR32AsmReg1_1,
1127 Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1,
1128 Convert__FGR64AsmReg1_0__FGR64AsmReg1_1,
1129 Convert__FGR32AsmReg1_0__FGR32AsmReg1_1,
1130 Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1,
1131 Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1,
1132 Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2,
1133 Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2,
1134 Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2,
1135 Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2,
1136 Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2,
1137 Convert__FGR32AsmReg1_0__FGR32AsmReg1_2__FGR32AsmReg1_1,
1138 Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2,
1139 Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm161_1,
1140 Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm16_Relaxed1_1,
1141 Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2,
1142 Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm16_Relaxed1_2,
1143 Convert__SImm161_1,
1144 Convert__Reg1_0__SImm161_1,
1145 Convert__Reg1_0__SImm161_2,
1146 Convert__Reg1_0__Reg1_1__SImm161_2,
1147 Convert__Reg1_0__Tie0_1_1__SImm161_1,
1148 Convert__GPR32AsmReg1_0__Simm19_Lsl21_1,
1149 Convert__GPRMM16AsmReg1_0__Imm1_1,
1150 Convert__GPRMM16AsmReg1_0__UImm6Lsl21_1,
1151 Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Imm1_2,
1152 Convert__GPR32AsmReg1_0__Tie0_1_1__ConstantSImm4_01_1,
1153 Convert__Imm1_0,
1154 Convert__Reg1_0__Reg1_1__Reg1_2,
1155 Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__GPRMM16AsmReg1_2,
1156 Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2,
1157 Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__ConstantUImm2_01_3,
1158 Convert__GPR32AsmReg1_0__SImm161_1,
1159 Convert__Reg1_0__Tie0_1_1__Reg1_1,
1160 Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1,
1161 Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1,
1162 Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2,
1163 Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2,
1164 Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Tie0_1_1,
1165 Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm8_01_2,
1166 Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Tie0_1_1,
1167 Convert__regZERO__regZERO__JumpTarget1_0,
1168 Convert__JumpTarget1_0,
1169 Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1,
1170 Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2,
1171 Convert__regZERO__JumpTarget1_0,
1172 Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm2_01_2__Tie0_1_1,
1173 Convert__GPR64AsmReg1_0__ConstantUImm5_32_Norm1_1__JumpTarget1_2,
1174 Convert__GPR64AsmReg1_0__ConstantUImm5_0_Report_UImm61_1__JumpTarget1_2,
1175 Convert__GPR64AsmReg1_0__ConstantUImm5_01_1__JumpTarget1_2,
1176 Convert__FGR64AsmReg1_0__JumpTarget1_1,
1177 Convert__regFCC0__JumpTarget1_0,
1178 Convert__FCCAsmReg1_0__JumpTarget1_1,
1179 Convert__COP2AsmReg1_0__JumpTarget1_1,
1180 Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2,
1181 Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2,
1182 Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2,
1183 Convert__GPR32AsmReg1_0__ConstantImm1_1__JumpTarget1_2,
1184 Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2,
1185 Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__JumpTarget1_2,
1186 Convert__Reg1_0__JumpTarget1_1,
1187 Convert__GPR32AsmReg1_0__regZERO__JumpTarget1_1,
1188 Convert__GPRMM16AsmReg1_0__JumpTarget1_1,
1189 Convert__GPR32AsmReg1_0__JumpTarget1_1,
1190 Convert__GPR64AsmReg1_0__JumpTarget1_1,
1191 Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2,
1192 Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm3_01_2,
1193 Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm6_01_2,
1194 Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm4_01_2,
1195 Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm5_01_2,
1196 Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm8_01_2,
1197 Convert__MSA128AsmReg1_0__JumpTarget1_1,
1198 Convert__imm_95_0__imm_95_0,
1199 Convert_NoOperands,
1200 Convert__ConstantUImm10_01_0__imm_95_0,
1201 Convert__ConstantUImm10_01_0__ConstantUImm10_01_1,
1202 Convert__ConstantUImm4_01_0,
1203 Convert__SImm161_0,
1204 Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1,
1205 Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1,
1206 Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2,
1207 Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2,
1208 Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1,
1209 Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2,
1210 Convert__MemOffsetSimm9_02_1__ConstantUImm5_01_0,
1211 Convert__Mem2_1__ConstantUImm5_01_0,
1212 Convert__FGR64AsmReg1_0__FGR32AsmReg1_1,
1213 Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1,
1214 Convert__FGR32AsmReg1_0__FGR64AsmReg1_1,
1215 Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2,
1216 Convert__GPR32AsmReg1_0__CCRAsmReg1_1,
1217 Convert__GPR32AsmReg1_0__COP2AsmReg1_1,
1218 Convert__GPR32AsmReg1_0__MSACtrlAsmReg1_1,
1219 Convert__GPR32AsmReg1_0__FGR32AsmReg1_1,
1220 Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1__ConstantUImm5_01_2,
1221 Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_32_Norm1_1__ConstantUImm5_01_2,
1222 Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_01_3,
1223 Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_32_Norm1_2__ConstantUImm5_01_3,
1224 Convert__Reg1_0__Reg1_1,
1225 Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_3,
1226 Convert__GPR64AsmReg1_0__MSA128AsmReg1_1__ConstantUImm1_01_3,
1227 Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_3,
1228 Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm2_01_3,
1229 Convert__CCRAsmReg1_1__GPR32AsmReg1_0,
1230 Convert__COP2AsmReg1_1__GPR32AsmReg1_0,
1231 Convert__MSACtrlAsmReg1_0__GPR32AsmReg1_1,
1232 Convert__FGR32AsmReg1_1__GPR32AsmReg1_0,
1233 Convert__AFGR64AsmReg1_0__FGR32AsmReg1_1,
1234 Convert__FGR64AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2,
1235 Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__SImm161_1,
1236 Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm161_2,
1237 Convert__GPR64AsmReg1_0__Tie0_1_2__UImm16_AltRelaxed1_2,
1238 Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2__ConstantUImm3_01_3,
1239 Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__UImm161_2,
1240 Convert__GPR64AsmReg1_0__GPR64AsmReg1_1,
1241 Convert__GPR64AsmReg1_1__GPR64AsmReg1_2,
1242 Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_331_3,
1243 Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_321_2__ConstantUImm5_11_3,
1244 Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_0_Report_UImm61_2__ConstantUImm5_Plus1_Report_UImm61_3,
1245 Convert__regZERO,
1246 Convert__GPR32AsmReg1_0,
1247 Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImmRange2_641_3__Tie0_1_1,
1248 Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_321_2__ConstantUImm5_11_3__Tie0_1_1,
1249 Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2__ConstantUImm5_11_3__Tie0_1_1,
1250 Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm321_1,
1251 Convert__GPR32NonZeroAsmReg1_0__GPR32NonZeroAsmReg1_0__GPR32AsmReg1_1,
1252 Convert__GPR32ZeroAsmReg1_0__GPR32AsmReg1_1,
1253 Convert__Reg1_1__Reg1_2,
1254 Convert__GPR32AsmReg1_1__GPR32AsmReg1_2,
1255 Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm321_2,
1256 Convert__GPR32NonZeroAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2,
1257 Convert__GPR64AsmReg1_0__Imm1_1,
1258 Convert__GPR64AsmReg1_0__Mem2_1,
1259 Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2__ConstantUImm2_11_3,
1260 Convert__GPR64AsmReg1_0__COP0AsmReg1_1__imm_95_0,
1261 Convert__GPR64AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2,
1262 Convert__GPR64AsmReg1_0__FGR64AsmReg1_1,
1263 Convert__GPR64AsmReg1_0__COP2AsmReg1_1__imm_95_0,
1264 Convert__GPR64AsmReg1_0__UImm161_1,
1265 Convert__GPR64AsmReg1_0__COP2AsmReg1_1__ConstantUImm3_01_2,
1266 Convert__COP0AsmReg1_1__GPR64AsmReg1_0__imm_95_0,
1267 Convert__COP0AsmReg1_1__GPR64AsmReg1_0__ConstantUImm3_01_2,
1268 Convert__FGR64AsmReg1_1__GPR64AsmReg1_0,
1269 Convert__COP2AsmReg1_1__GPR64AsmReg1_0__imm_95_0,
1270 Convert__COP2AsmReg1_1__GPR64AsmReg1_0__ConstantUImm3_01_2,
1271 Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm32_Relaxed1_2,
1272 Convert__GPR64AsmReg1_0__regZERO_64__GPR64AsmReg1_0,
1273 Convert__GPR64AsmReg1_0__regZERO_64__GPR64AsmReg1_1,
1274 Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1,
1275 Convert__GPR64AsmReg1_0__GPR64AsmReg1_0,
1276 Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__SImm32_Relaxed1_1,
1277 Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm6_01_1,
1278 Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2,
1279 Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1,
1280 Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2,
1281 Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2,
1282 Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR32AsmReg1_1,
1283 Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__InvNum1_1,
1284 Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__InvNum1_2,
1285 Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3,
1286 Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2,
1287 Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2,
1288 Convert__MSA128AsmReg1_0__MSA128AsmReg1_1,
1289 Convert__MSA128AsmReg1_0__GPR32AsmReg1_1,
1290 Convert__MSA128AsmReg1_0__GPR64AsmReg1_1,
1291 Convert__GPR32AsmReg1_1__GPR32AsmReg1_0__GPR32AsmReg1_2,
1292 Convert__GPR32AsmReg1_0__ConstantUImm2_01_1,
1293 Convert__imm_95_0,
1294 Convert__ConstantUImm10_01_0,
1295 Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3__Tie0_1_1,
1296 Convert__MSA128AsmReg1_0__Tie0_1_1__GPR32AsmReg1_4__ConstantUImm4_01_2,
1297 Convert__MSA128AsmReg1_0__Tie0_1_1__GPR64AsmReg1_4__ConstantUImm1_01_2,
1298 Convert__MSA128AsmReg1_0__Tie0_1_1__GPR32AsmReg1_4__ConstantUImm3_01_2,
1299 Convert__MSA128AsmReg1_0__Tie0_1_1__GPR32AsmReg1_4__ConstantUImm2_01_2,
1300 Convert__GPR32AsmReg1_0__Tie0_1_1__GPR32AsmReg1_1,
1301 Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm4_01_2__MSA128AsmReg1_4__ConstantImmz1_6,
1302 Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm1_01_2__MSA128AsmReg1_4__ConstantImmz1_6,
1303 Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm3_01_2__MSA128AsmReg1_4__ConstantImmz1_6,
1304 Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm2_01_2__MSA128AsmReg1_4__ConstantImmz1_6,
1305 Convert__regRA__GPR32AsmReg1_0,
1306 Convert__regRA_64__GPR64AsmReg1_0,
1307 Convert__Reg1_0,
1308 Convert__GPR32AsmReg1_0__imm_95_0,
1309 Convert__GPR64AsmReg1_0__imm_95_0,
1310 Convert__regZERO__GPR32AsmReg1_0,
1311 Convert__GPR64AsmReg1_0,
1312 Convert__regZERO_64__GPR64AsmReg1_0,
1313 Convert__UImm5Lsl21_0,
1314 Convert__AFGR64AsmReg1_0__MemOffsetSimm16_02_1,
1315 Convert__FGR64AsmReg1_0__MemOffsetSimm16_02_1,
1316 Convert__FGR32AsmReg1_0__MemOffsetSimm16_02_1,
1317 Convert__GPR32AsmReg1_0__Imm1_1,
1318 Convert__GPR32AsmReg1_0__Mem2_1,
1319 Convert__GPR32AsmReg1_0__MemOffsetSimmPtr2_1,
1320 Convert__GPR32AsmReg1_0__MemOffsetSimm16_02_1,
1321 Convert__GPR32AsmReg1_0__MemOffsetSimm9_02_1,
1322 Convert__GPRMM16AsmReg1_0__MicroMipsMem2_1,
1323 Convert__GPR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1,
1324 Convert__GPR64AsmReg1_0__MemOffsetSimmPtr2_1,
1325 Convert__MSA128AsmReg1_0__MemOffsetSimm10_02_1,
1326 Convert__MSA128AsmReg1_0__MemOffsetSimm10_32_1,
1327 Convert__MSA128AsmReg1_0__MemOffsetSimm10_12_1,
1328 Convert__MSA128AsmReg1_0__MemOffsetSimm10_22_1,
1329 Convert__COP2AsmReg1_0__MemOffsetSimm11_02_1,
1330 Convert__COP2AsmReg1_0__MemOffsetSimm16_02_1,
1331 Convert__COP3AsmReg1_0__Mem2_1,
1332 Convert__MSA128AsmReg1_0__ConstantSImm10_01_1,
1333 Convert__GPR64AsmReg1_0__Mem2_1__Tie0_1_1,
1334 Convert__GPR64AsmReg1_0__Simm18_Lsl31_1,
1335 Convert__AFGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1,
1336 Convert__FGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1,
1337 Convert__GPR32AsmReg1_0__UImm32_Coerced1_1,
1338 Convert__StrictlyAFGR64AsmReg1_0__Imm1_1,
1339 Convert__StrictlyFGR64AsmReg1_0__Imm1_1,
1340 Convert__StrictlyFGR32AsmReg1_0__Imm1_1,
1341 Convert__GPRMM16AsmReg1_0__UImm7_N11_1,
1342 Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__ConstantUImm2_11_3,
1343 Convert__GPR32AsmReg1_2__GPR32AsmReg1_1__GPR32AsmReg1_0__ConstantUImm2_11_3,
1344 Convert__GPR32AsmReg1_0__UImm161_1,
1345 Convert__GPR32AsmReg1_0__UImm16_Relaxed1_1,
1346 Convert__Reg1_0__Imm1_1,
1347 Convert__GPR32AsmReg1_0__MicroMipsMemSP2_1,
1348 Convert__GPRMM16AsmReg1_0__MicroMipsMemGP2_1,
1349 Convert__GPR32AsmReg1_0__Mem2_1__Tie0_1_1,
1350 Convert__GPR32AsmReg1_0__MemOffsetSimm9_02_1__Tie0_1_1,
1351 Convert__RegList1_0__Mem2_1,
1352 Convert__RegList161_0__MemOffsetUimm42_1,
1353 ConvertCustom_ConvertXWPOperands,
1354 Convert__GPR32AsmReg1_0__MemOffsetSimm12_02_1,
1355 Convert__FGR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1,
1356 Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2__AFGR64AsmReg1_3,
1357 Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2__FGR64AsmReg1_3,
1358 Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2__FGR32AsmReg1_3,
1359 Convert__FGR64AsmReg1_0__Tie0_1_1__FGR64AsmReg1_1__FGR64AsmReg1_2,
1360 Convert__FGR32AsmReg1_0__Tie0_1_1__FGR32AsmReg1_1__FGR32AsmReg1_2,
1361 Convert__GPR32AsmReg1_0__COP0AsmReg1_1__imm_95_0,
1362 Convert__GPR32AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2,
1363 Convert__GPR32AsmReg1_0__FGR64AsmReg1_1,
1364 Convert__GPR32AsmReg1_0__COP2AsmReg1_1__imm_95_0,
1365 Convert__GPR32AsmReg1_0__COP2AsmReg1_1__ConstantUImm3_01_2,
1366 Convert__GPR32AsmReg1_0__AFGR64AsmReg1_1,
1367 Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1,
1368 Convert__GPR32AsmReg1_0__regAC0,
1369 Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0,
1370 Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm1_01_2__ConstantUImm3_01_3__ConstantUImm1_01_4,
1371 Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__regZERO,
1372 Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__regZERO_64,
1373 Convert__GPRMM16AsmRegMovePPairFirst1_0__GPRMM16AsmRegMovePPairSecond1_1__GPRMM16AsmRegMoveP1_2__GPRMM16AsmRegMoveP1_3,
1374 Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1,
1375 Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__FCCAsmReg1_2__Tie0_1_1,
1376 Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FCCAsmReg1_2__Tie0_1_1,
1377 Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1,
1378 Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1,
1379 Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1,
1380 Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1,
1381 Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1,
1382 Convert__COP0AsmReg1_1__GPR32AsmReg1_0__imm_95_0,
1383 Convert__COP0AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2,
1384 Convert__FGR64AsmReg1_1__GPR32AsmReg1_0,
1385 Convert__COP2AsmReg1_1__GPR32AsmReg1_0__imm_95_0,
1386 Convert__COP2AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2,
1387 Convert__AFGR64AsmReg1_1__Tie0_1_1__GPR32AsmReg1_0,
1388 Convert__FGR64AsmReg1_1__Tie0_1_1__GPR32AsmReg1_0,
1389 Convert__HI32DSPAsmReg1_1__GPR32AsmReg1_0,
1390 Convert__ACC64DSPAsmReg1_1__GPR32AsmReg1_0__Tie0_1_1,
1391 Convert__LO32DSPAsmReg1_1__GPR32AsmReg1_0,
1392 Convert__regAC0__GPR32AsmReg1_0,
1393 Convert__ACC64DSPAsmReg1_1__GPR32AsmReg1_0,
1394 Convert__GPR32AsmReg1_1__GPR32AsmReg1_0,
1395 Convert__GPR32AsmReg1_1__GPR32AsmReg1_0__ConstantUImm1_01_2__ConstantUImm3_01_3__ConstantUImm1_01_4,
1396 Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2,
1397 Convert__regZERO__imm_95_0,
1398 Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_0,
1399 Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_1,
1400 Convert__regZERO__regZERO__imm_95_0,
1401 Convert__regZERO__regS0,
1402 Convert__regZERO__regZERO,
1403 Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__regZERO,
1404 Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1,
1405 Convert__GPR32AsmReg1_0__GPR32AsmReg1_0,
1406 Convert__GPR32AsmReg1_3__GPR32AsmReg1_1__ConstantUImm5_01_0,
1407 Convert__GPR32AsmReg1_0__ConstantUImm7_01_1,
1408 Convert__GPR32AsmReg1_0__ConstantUImm10_01_1,
1409 Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__imm_95_0,
1410 Convert__GPR64AsmReg1_0__HWRegsAsmReg1_1__imm_95_0,
1411 Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__ConstantUImm3_01_2,
1412 Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__ConstantUImm8_01_2,
1413 Convert__GPR32AsmReg1_0__ConstantSImm10_01_1,
1414 Convert__GPR32AsmReg1_0__ConstantUImm8_01_1,
1415 Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1,
1416 Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2,
1417 Convert__GPR64AsmReg1_0__GPR64AsmReg1_2,
1418 Convert__GPRMM16AsmRegZero1_0__MicroMipsMem2_1,
1419 Convert__GPR32AsmReg1_0__Tie0_1_1__MemOffsetSimmPtr2_1,
1420 Convert__GPR32AsmReg1_0__Tie0_1_1__MemOffsetSimm9_02_1,
1421 Convert__GPR32AsmReg1_0__Tie0_1_1__Mem2_1,
1422 Convert__GPR64AsmReg1_0__Tie0_1_1__MemOffsetSimmPtr2_1,
1423 Convert__GPR64AsmReg1_0__Tie0_1_1__Mem2_1,
1424 Convert__ConstantUImm20_01_0,
1425 Convert__Reg1_0__Tie0_1_1,
1426 Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantSImm10_01_1,
1427 Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantSImm10_01_2,
1428 Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm32_Coerced1_1,
1429 Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm32_Coerced1_2,
1430 Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_0,
1431 Convert__GPR32AsmReg1_0__GPR32AsmReg1_2__GPR32AsmReg1_1,
1432 Convert__ACC64DSPAsmReg1_0__ConstantSImm6_01_1__Tie0_1_1,
1433 Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__Tie0_1_1,
1434 Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2,
1435 Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2,
1436 Convert__UImm161_0,
1437 Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__GPR32AsmReg1_3,
1438 Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm4_01_3,
1439 Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm1_01_3,
1440 Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm3_01_3,
1441 Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm2_01_3,
1442 Convert__Reg1_0__Reg1_1__ConstantUImm5_01_2,
1443 Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__GPR32AsmReg1_3,
1444 Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_3,
1445 Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm1_01_3,
1446 Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_3,
1447 Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm2_01_3,
1448 Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__InvNum1_1,
1449 Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__InvNum1_2,
1450 Convert__ConstantUImm5_01_0,
1451 Convert__imm_95_17,
1452 Convert__imm_95_16,
1453 Convert__imm_95_18,
1454 Convert__imm_95_19,
1455 Convert__imm_95_4,
1456 Convert__MemOffsetSimm16_02_0,
1457 Convert__imm_95_2,
1458 Convert__imm_95_6,
1459 Convert__imm_95_5,
1460 Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm10_01_2,
1461 Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1__GPR32AsmReg1_2,
1462 Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__GPR32AsmReg1_2,
1463 Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__GPR32AsmReg1_2,
1464 Convert__GPR32AsmReg1_0__imm_95_31,
1465 CVT_NUM_SIGNATURES
1466};
1467
1468} // end anonymous namespace
1469
1470static const uint8_t ConversionTable[CVT_NUM_SIGNATURES][11] = {
1471 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1
1472 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
1473 // Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1
1474 { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_Done },
1475 // Convert__FGR64AsmReg1_0__FGR64AsmReg1_1
1476 { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_Done },
1477 // Convert__FGR32AsmReg1_0__FGR32AsmReg1_1
1478 { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_Done },
1479 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1
1480 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
1481 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1
1482 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addSImmOperands_LT_32_GT_, 2, CVT_Done },
1483 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2
1484 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done },
1485 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2
1486 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addSImmOperands_LT_32_GT_, 3, CVT_Done },
1487 // Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2
1488 { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_95_addAFGR64AsmRegOperands, 3, CVT_Done },
1489 // Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2
1490 { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addFGR64AsmRegOperands, 3, CVT_Done },
1491 // Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2
1492 { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addFGR32AsmRegOperands, 3, CVT_Done },
1493 // Convert__FGR32AsmReg1_0__FGR32AsmReg1_2__FGR32AsmReg1_1
1494 { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 3, CVT_95_addFGR32AsmRegOperands, 2, CVT_Done },
1495 // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2
1496 { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addMSA128AsmRegOperands, 3, CVT_Done },
1497 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm161_1
1498 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addSImmOperands_LT_16_GT_, 2, CVT_Done },
1499 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm16_Relaxed1_1
1500 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addSImmOperands_LT_16_GT_, 2, CVT_Done },
1501 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2
1502 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addSImmOperands_LT_16_GT_, 3, CVT_Done },
1503 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm16_Relaxed1_2
1504 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addSImmOperands_LT_16_GT_, 3, CVT_Done },
1505 // Convert__SImm161_1
1506 { CVT_95_addSImmOperands_LT_16_GT_, 2, CVT_Done },
1507 // Convert__Reg1_0__SImm161_1
1508 { CVT_95_Reg, 1, CVT_95_addSImmOperands_LT_16_GT_, 2, CVT_Done },
1509 // Convert__Reg1_0__SImm161_2
1510 { CVT_95_Reg, 1, CVT_95_addSImmOperands_LT_16_GT_, 3, CVT_Done },
1511 // Convert__Reg1_0__Reg1_1__SImm161_2
1512 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addSImmOperands_LT_16_GT_, 3, CVT_Done },
1513 // Convert__Reg1_0__Tie0_1_1__SImm161_1
1514 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addSImmOperands_LT_16_GT_, 2, CVT_Done },
1515 // Convert__GPR32AsmReg1_0__Simm19_Lsl21_1
1516 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
1517 // Convert__GPRMM16AsmReg1_0__Imm1_1
1518 { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
1519 // Convert__GPRMM16AsmReg1_0__UImm6Lsl21_1
1520 { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
1521 // Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Imm1_2
1522 { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addGPRMM16AsmRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
1523 // Convert__GPR32AsmReg1_0__Tie0_1_1__ConstantSImm4_01_1
1524 { CVT_95_addGPR32AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addConstantSImmOperands_LT_4_44__32_0_GT_, 2, CVT_Done },
1525 // Convert__Imm1_0
1526 { CVT_95_addImmOperands, 1, CVT_Done },
1527 // Convert__Reg1_0__Reg1_1__Reg1_2
1528 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Done },
1529 // Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__GPRMM16AsmReg1_2
1530 { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addGPRMM16AsmRegOperands, 2, CVT_95_addGPRMM16AsmRegOperands, 3, CVT_Done },
1531 // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2
1532 { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done },
1533 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__ConstantUImm2_01_3
1534 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 4, CVT_Done },
1535 // Convert__GPR32AsmReg1_0__SImm161_1
1536 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addSImmOperands_LT_16_GT_, 2, CVT_Done },
1537 // Convert__Reg1_0__Tie0_1_1__Reg1_1
1538 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_Done },
1539 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1
1540 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addUImmOperands_LT_16_GT_, 2, CVT_Done },
1541 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1
1542 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
1543 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2
1544 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addUImmOperands_LT_16_GT_, 3, CVT_Done },
1545 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2
1546 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
1547 // Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Tie0_1_1
1548 { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addGPRMM16AsmRegOperands, 2, CVT_Tied, Tie0_1_1, CVT_Done },
1549 // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm8_01_2
1550 { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_8_44__32_0_GT_, 3, CVT_Done },
1551 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Tie0_1_1
1552 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Tied, Tie0_1_1, CVT_Done },
1553 // Convert__regZERO__regZERO__JumpTarget1_0
1554 { CVT_regZERO, 0, CVT_regZERO, 0, CVT_95_addImmOperands, 1, CVT_Done },
1555 // Convert__JumpTarget1_0
1556 { CVT_95_addImmOperands, 1, CVT_Done },
1557 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1
1558 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_Done },
1559 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2
1560 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 3, CVT_Done },
1561 // Convert__regZERO__JumpTarget1_0
1562 { CVT_regZERO, 0, CVT_95_addImmOperands, 1, CVT_Done },
1563 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm2_01_2__Tie0_1_1
1564 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 3, CVT_Tied, Tie0_1_1, CVT_Done },
1565 // Convert__GPR64AsmReg1_0__ConstantUImm5_32_Norm1_1__JumpTarget1_2
1566 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_5_44__32_32_44__32__MINUS_32_GT_, 2, CVT_95_addImmOperands, 3, CVT_Done },
1567 // Convert__GPR64AsmReg1_0__ConstantUImm5_0_Report_UImm61_1__JumpTarget1_2
1568 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 2, CVT_95_addImmOperands, 3, CVT_Done },
1569 // Convert__GPR64AsmReg1_0__ConstantUImm5_01_1__JumpTarget1_2
1570 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 2, CVT_95_addImmOperands, 3, CVT_Done },
1571 // Convert__FGR64AsmReg1_0__JumpTarget1_1
1572 { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
1573 // Convert__regFCC0__JumpTarget1_0
1574 { CVT_regFCC0, 0, CVT_95_addImmOperands, 1, CVT_Done },
1575 // Convert__FCCAsmReg1_0__JumpTarget1_1
1576 { CVT_95_addFCCAsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
1577 // Convert__COP2AsmReg1_0__JumpTarget1_1
1578 { CVT_95_addCOP2AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
1579 // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2
1580 { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
1581 // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2
1582 { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_, 3, CVT_Done },
1583 // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2
1584 { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 3, CVT_Done },
1585 // Convert__GPR32AsmReg1_0__ConstantImm1_1__JumpTarget1_2
1586 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
1587 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2
1588 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
1589 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__JumpTarget1_2
1590 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
1591 // Convert__Reg1_0__JumpTarget1_1
1592 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
1593 // Convert__GPR32AsmReg1_0__regZERO__JumpTarget1_1
1594 { CVT_95_addGPR32AsmRegOperands, 1, CVT_regZERO, 0, CVT_95_addImmOperands, 2, CVT_Done },
1595 // Convert__GPRMM16AsmReg1_0__JumpTarget1_1
1596 { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
1597 // Convert__GPR32AsmReg1_0__JumpTarget1_1
1598 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
1599 // Convert__GPR64AsmReg1_0__JumpTarget1_1
1600 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
1601 // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2
1602 { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addMSA128AsmRegOperands, 3, CVT_Done },
1603 // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm3_01_2
1604 { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
1605 // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm6_01_2
1606 { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_, 3, CVT_Done },
1607 // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm4_01_2
1608 { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 3, CVT_Done },
1609 // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm5_01_2
1610 { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done },
1611 // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm8_01_2
1612 { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_8_44__32_0_GT_, 3, CVT_Done },
1613 // Convert__MSA128AsmReg1_0__JumpTarget1_1
1614 { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
1615 // Convert__imm_95_0__imm_95_0
1616 { CVT_imm_95_0, 0, CVT_imm_95_0, 0, CVT_Done },
1617 // Convert_NoOperands
1618 { CVT_Done },
1619 // Convert__ConstantUImm10_01_0__imm_95_0
1620 { CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_, 1, CVT_imm_95_0, 0, CVT_Done },
1621 // Convert__ConstantUImm10_01_0__ConstantUImm10_01_1
1622 { CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_, 1, CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_, 2, CVT_Done },
1623 // Convert__ConstantUImm4_01_0
1624 { CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 1, CVT_Done },
1625 // Convert__SImm161_0
1626 { CVT_95_addSImmOperands_LT_16_GT_, 1, CVT_Done },
1627 // Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1
1628 { CVT_regFCC0, 0, CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_Done },
1629 // Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1
1630 { CVT_regFCC0, 0, CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_Done },
1631 // Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2
1632 { CVT_95_addFCCAsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_95_addAFGR64AsmRegOperands, 3, CVT_Done },
1633 // Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2
1634 { CVT_95_addFCCAsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addFGR64AsmRegOperands, 3, CVT_Done },
1635 // Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1
1636 { CVT_regFCC0, 0, CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_Done },
1637 // Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2
1638 { CVT_95_addFCCAsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addFGR32AsmRegOperands, 3, CVT_Done },
1639 // Convert__MemOffsetSimm9_02_1__ConstantUImm5_01_0
1640 { CVT_95_addMemOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 1, CVT_Done },
1641 // Convert__Mem2_1__ConstantUImm5_01_0
1642 { CVT_95_addMemOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 1, CVT_Done },
1643 // Convert__FGR64AsmReg1_0__FGR32AsmReg1_1
1644 { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_Done },
1645 // Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1
1646 { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_Done },
1647 // Convert__FGR32AsmReg1_0__FGR64AsmReg1_1
1648 { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_Done },
1649 // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2
1650 { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantSImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done },
1651 // Convert__GPR32AsmReg1_0__CCRAsmReg1_1
1652 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addCCRAsmRegOperands, 2, CVT_Done },
1653 // Convert__GPR32AsmReg1_0__COP2AsmReg1_1
1654 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addCOP2AsmRegOperands, 2, CVT_Done },
1655 // Convert__GPR32AsmReg1_0__MSACtrlAsmReg1_1
1656 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMSACtrlAsmRegOperands, 2, CVT_Done },
1657 // Convert__GPR32AsmReg1_0__FGR32AsmReg1_1
1658 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_Done },
1659 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1__ConstantUImm5_01_2
1660 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done },
1661 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_32_Norm1_1__ConstantUImm5_01_2
1662 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_5_44__32_32_44__32__MINUS_32_GT_, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done },
1663 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_01_3
1664 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 4, CVT_Done },
1665 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_32_Norm1_2__ConstantUImm5_01_3
1666 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_32_44__32__MINUS_32_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 4, CVT_Done },
1667 // Convert__Reg1_0__Reg1_1
1668 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Done },
1669 // Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_3
1670 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 4, CVT_Done },
1671 // Convert__GPR64AsmReg1_0__MSA128AsmReg1_1__ConstantUImm1_01_3
1672 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 4, CVT_Done },
1673 // Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_3
1674 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 4, CVT_Done },
1675 // Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm2_01_3
1676 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 4, CVT_Done },
1677 // Convert__CCRAsmReg1_1__GPR32AsmReg1_0
1678 { CVT_95_addCCRAsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
1679 // Convert__COP2AsmReg1_1__GPR32AsmReg1_0
1680 { CVT_95_addCOP2AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
1681 // Convert__MSACtrlAsmReg1_0__GPR32AsmReg1_1
1682 { CVT_95_addMSACtrlAsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
1683 // Convert__FGR32AsmReg1_1__GPR32AsmReg1_0
1684 { CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
1685 // Convert__AFGR64AsmReg1_0__FGR32AsmReg1_1
1686 { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_Done },
1687 // Convert__FGR64AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2
1688 { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addFGR32AsmRegOperands, 3, CVT_Done },
1689 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__SImm161_1
1690 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addSImmOperands_LT_16_GT_, 2, CVT_Done },
1691 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm161_2
1692 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addSImmOperands_LT_16_GT_, 3, CVT_Done },
1693 // Convert__GPR64AsmReg1_0__Tie0_1_2__UImm16_AltRelaxed1_2
1694 { CVT_95_addGPR64AsmRegOperands, 1, CVT_Tied, Tie0_1_2, CVT_95_addSImmOperands_LT_16_GT_, 3, CVT_Done },
1695 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2__ConstantUImm3_01_3
1696 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 3, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 4, CVT_Done },
1697 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__UImm161_2
1698 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addUImmOperands_LT_16_GT_, 3, CVT_Done },
1699 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1
1700 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_Done },
1701 // Convert__GPR64AsmReg1_1__GPR64AsmReg1_2
1702 { CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 3, CVT_Done },
1703 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_331_3
1704 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_33_GT_, 4, CVT_Done },
1705 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_321_2__ConstantUImm5_11_3
1706 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_32_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_, 4, CVT_Done },
1707 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_0_Report_UImm61_2__ConstantUImm5_Plus1_Report_UImm61_3
1708 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_, 4, CVT_Done },
1709 // Convert__regZERO
1710 { CVT_regZERO, 0, CVT_Done },
1711 // Convert__GPR32AsmReg1_0
1712 { CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
1713 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImmRange2_641_3__Tie0_1_1
1714 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_95_addImmOperands, 4, CVT_Tied, Tie0_1_1, CVT_Done },
1715 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_321_2__ConstantUImm5_11_3__Tie0_1_1
1716 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_32_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_, 4, CVT_Tied, Tie0_1_1, CVT_Done },
1717 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2__ConstantUImm5_11_3__Tie0_1_1
1718 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_, 4, CVT_Tied, Tie0_1_1, CVT_Done },
1719 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm321_1
1720 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addSImmOperands_LT_32_GT_, 2, CVT_Done },
1721 // Convert__GPR32NonZeroAsmReg1_0__GPR32NonZeroAsmReg1_0__GPR32AsmReg1_1
1722 { CVT_95_addGPR32NonZeroAsmRegOperands, 1, CVT_95_addGPR32NonZeroAsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
1723 // Convert__GPR32ZeroAsmReg1_0__GPR32AsmReg1_1
1724 { CVT_95_addGPR32ZeroAsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
1725 // Convert__Reg1_1__Reg1_2
1726 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Done },
1727 // Convert__GPR32AsmReg1_1__GPR32AsmReg1_2
1728 { CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done },
1729 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm321_2
1730 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addSImmOperands_LT_32_GT_, 3, CVT_Done },
1731 // Convert__GPR32NonZeroAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2
1732 { CVT_95_addGPR32NonZeroAsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done },
1733 // Convert__GPR64AsmReg1_0__Imm1_1
1734 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
1735 // Convert__GPR64AsmReg1_0__Mem2_1
1736 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1737 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2__ConstantUImm2_11_3
1738 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 3, CVT_95_addConstantUImmOperands_LT_2_44__32_1_GT_, 4, CVT_Done },
1739 // Convert__GPR64AsmReg1_0__COP0AsmReg1_1__imm_95_0
1740 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addCOP0AsmRegOperands, 2, CVT_imm_95_0, 0, CVT_Done },
1741 // Convert__GPR64AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2
1742 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addCOP0AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
1743 // Convert__GPR64AsmReg1_0__FGR64AsmReg1_1
1744 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_Done },
1745 // Convert__GPR64AsmReg1_0__COP2AsmReg1_1__imm_95_0
1746 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addCOP2AsmRegOperands, 2, CVT_imm_95_0, 0, CVT_Done },
1747 // Convert__GPR64AsmReg1_0__UImm161_1
1748 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addUImmOperands_LT_16_GT_, 2, CVT_Done },
1749 // Convert__GPR64AsmReg1_0__COP2AsmReg1_1__ConstantUImm3_01_2
1750 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addCOP2AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
1751 // Convert__COP0AsmReg1_1__GPR64AsmReg1_0__imm_95_0
1752 { CVT_95_addCOP0AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 1, CVT_imm_95_0, 0, CVT_Done },
1753 // Convert__COP0AsmReg1_1__GPR64AsmReg1_0__ConstantUImm3_01_2
1754 { CVT_95_addCOP0AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
1755 // Convert__FGR64AsmReg1_1__GPR64AsmReg1_0
1756 { CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 1, CVT_Done },
1757 // Convert__COP2AsmReg1_1__GPR64AsmReg1_0__imm_95_0
1758 { CVT_95_addCOP2AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 1, CVT_imm_95_0, 0, CVT_Done },
1759 // Convert__COP2AsmReg1_1__GPR64AsmReg1_0__ConstantUImm3_01_2
1760 { CVT_95_addCOP2AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
1761 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm32_Relaxed1_2
1762 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addSImmOperands_LT_32_GT_, 3, CVT_Done },
1763 // Convert__GPR64AsmReg1_0__regZERO_64__GPR64AsmReg1_0
1764 { CVT_95_addGPR64AsmRegOperands, 1, CVT_regZERO_64, 0, CVT_95_addGPR64AsmRegOperands, 1, CVT_Done },
1765 // Convert__GPR64AsmReg1_0__regZERO_64__GPR64AsmReg1_1
1766 { CVT_95_addGPR64AsmRegOperands, 1, CVT_regZERO_64, 0, CVT_95_addGPR64AsmRegOperands, 2, CVT_Done },
1767 // Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1
1768 { CVT_95_addACC64DSPAsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done },
1769 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0
1770 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_Done },
1771 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__SImm32_Relaxed1_1
1772 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addSImmOperands_LT_32_GT_, 2, CVT_Done },
1773 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm6_01_1
1774 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_, 2, CVT_Done },
1775 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2
1776 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_, 3, CVT_Done },
1777 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1
1778 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 2, CVT_Done },
1779 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2
1780 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done },
1781 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2
1782 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done },
1783 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR32AsmReg1_1
1784 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
1785 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__InvNum1_1
1786 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
1787 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__InvNum1_2
1788 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
1789 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3
1790 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_, 4, CVT_Done },
1791 // Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2
1792 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addACC64DSPAsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done },
1793 // Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2
1794 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addACC64DSPAsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done },
1795 // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1
1796 { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_Done },
1797 // Convert__MSA128AsmReg1_0__GPR32AsmReg1_1
1798 { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
1799 // Convert__MSA128AsmReg1_0__GPR64AsmReg1_1
1800 { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_Done },
1801 // Convert__GPR32AsmReg1_1__GPR32AsmReg1_0__GPR32AsmReg1_2
1802 { CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done },
1803 // Convert__GPR32AsmReg1_0__ConstantUImm2_01_1
1804 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 2, CVT_Done },
1805 // Convert__imm_95_0
1806 { CVT_imm_95_0, 0, CVT_Done },
1807 // Convert__ConstantUImm10_01_0
1808 { CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_, 1, CVT_Done },
1809 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3__Tie0_1_1
1810 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_, 4, CVT_Tied, Tie0_1_1, CVT_Done },
1811 // Convert__MSA128AsmReg1_0__Tie0_1_1__GPR32AsmReg1_4__ConstantUImm4_01_2
1812 { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addGPR32AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 3, CVT_Done },
1813 // Convert__MSA128AsmReg1_0__Tie0_1_1__GPR64AsmReg1_4__ConstantUImm1_01_2
1814 { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addGPR64AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 3, CVT_Done },
1815 // Convert__MSA128AsmReg1_0__Tie0_1_1__GPR32AsmReg1_4__ConstantUImm3_01_2
1816 { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addGPR32AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
1817 // Convert__MSA128AsmReg1_0__Tie0_1_1__GPR32AsmReg1_4__ConstantUImm2_01_2
1818 { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addGPR32AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 3, CVT_Done },
1819 // Convert__GPR32AsmReg1_0__Tie0_1_1__GPR32AsmReg1_1
1820 { CVT_95_addGPR32AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
1821 // Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm4_01_2__MSA128AsmReg1_4__ConstantImmz1_6
1822 { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 3, CVT_95_addMSA128AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_1_GT_, 7, CVT_Done },
1823 // Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm1_01_2__MSA128AsmReg1_4__ConstantImmz1_6
1824 { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 3, CVT_95_addMSA128AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_1_GT_, 7, CVT_Done },
1825 // Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm3_01_2__MSA128AsmReg1_4__ConstantImmz1_6
1826 { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_95_addMSA128AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_1_GT_, 7, CVT_Done },
1827 // Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm2_01_2__MSA128AsmReg1_4__ConstantImmz1_6
1828 { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 3, CVT_95_addMSA128AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_1_GT_, 7, CVT_Done },
1829 // Convert__regRA__GPR32AsmReg1_0
1830 { CVT_regRA, 0, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
1831 // Convert__regRA_64__GPR64AsmReg1_0
1832 { CVT_regRA_64, 0, CVT_95_addGPR64AsmRegOperands, 1, CVT_Done },
1833 // Convert__Reg1_0
1834 { CVT_95_Reg, 1, CVT_Done },
1835 // Convert__GPR32AsmReg1_0__imm_95_0
1836 { CVT_95_addGPR32AsmRegOperands, 1, CVT_imm_95_0, 0, CVT_Done },
1837 // Convert__GPR64AsmReg1_0__imm_95_0
1838 { CVT_95_addGPR64AsmRegOperands, 1, CVT_imm_95_0, 0, CVT_Done },
1839 // Convert__regZERO__GPR32AsmReg1_0
1840 { CVT_regZERO, 0, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
1841 // Convert__GPR64AsmReg1_0
1842 { CVT_95_addGPR64AsmRegOperands, 1, CVT_Done },
1843 // Convert__regZERO_64__GPR64AsmReg1_0
1844 { CVT_regZERO_64, 0, CVT_95_addGPR64AsmRegOperands, 1, CVT_Done },
1845 // Convert__UImm5Lsl21_0
1846 { CVT_95_addImmOperands, 1, CVT_Done },
1847 // Convert__AFGR64AsmReg1_0__MemOffsetSimm16_02_1
1848 { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1849 // Convert__FGR64AsmReg1_0__MemOffsetSimm16_02_1
1850 { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1851 // Convert__FGR32AsmReg1_0__MemOffsetSimm16_02_1
1852 { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1853 // Convert__GPR32AsmReg1_0__Imm1_1
1854 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
1855 // Convert__GPR32AsmReg1_0__Mem2_1
1856 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1857 // Convert__GPR32AsmReg1_0__MemOffsetSimmPtr2_1
1858 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1859 // Convert__GPR32AsmReg1_0__MemOffsetSimm16_02_1
1860 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1861 // Convert__GPR32AsmReg1_0__MemOffsetSimm9_02_1
1862 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1863 // Convert__GPRMM16AsmReg1_0__MicroMipsMem2_1
1864 { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addMicroMipsMemOperands, 2, CVT_Done },
1865 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1
1866 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 4, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
1867 // Convert__GPR64AsmReg1_0__MemOffsetSimmPtr2_1
1868 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1869 // Convert__MSA128AsmReg1_0__MemOffsetSimm10_02_1
1870 { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1871 // Convert__MSA128AsmReg1_0__MemOffsetSimm10_32_1
1872 { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1873 // Convert__MSA128AsmReg1_0__MemOffsetSimm10_12_1
1874 { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1875 // Convert__MSA128AsmReg1_0__MemOffsetSimm10_22_1
1876 { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1877 // Convert__COP2AsmReg1_0__MemOffsetSimm11_02_1
1878 { CVT_95_addCOP2AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1879 // Convert__COP2AsmReg1_0__MemOffsetSimm16_02_1
1880 { CVT_95_addCOP2AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1881 // Convert__COP3AsmReg1_0__Mem2_1
1882 { CVT_95_addCOP3AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1883 // Convert__MSA128AsmReg1_0__ConstantSImm10_01_1
1884 { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addConstantSImmOperands_LT_10_44__32_0_GT_, 2, CVT_Done },
1885 // Convert__GPR64AsmReg1_0__Mem2_1__Tie0_1_1
1886 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Tied, Tie0_1_1, CVT_Done },
1887 // Convert__GPR64AsmReg1_0__Simm18_Lsl31_1
1888 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
1889 // Convert__AFGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1
1890 { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 4, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
1891 // Convert__FGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1
1892 { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 4, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
1893 // Convert__GPR32AsmReg1_0__UImm32_Coerced1_1
1894 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_32_GT_, 2, CVT_Done },
1895 // Convert__StrictlyAFGR64AsmReg1_0__Imm1_1
1896 { CVT_95_addStrictlyAFGR64AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
1897 // Convert__StrictlyFGR64AsmReg1_0__Imm1_1
1898 { CVT_95_addStrictlyFGR64AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
1899 // Convert__StrictlyFGR32AsmReg1_0__Imm1_1
1900 { CVT_95_addStrictlyFGR32AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
1901 // Convert__GPRMM16AsmReg1_0__UImm7_N11_1
1902 { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_7_44__32__MINUS_1_GT_, 2, CVT_Done },
1903 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__ConstantUImm2_11_3
1904 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_95_addConstantUImmOperands_LT_2_44__32_1_GT_, 4, CVT_Done },
1905 // Convert__GPR32AsmReg1_2__GPR32AsmReg1_1__GPR32AsmReg1_0__ConstantUImm2_11_3
1906 { CVT_95_addGPR32AsmRegOperands, 3, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_2_44__32_1_GT_, 4, CVT_Done },
1907 // Convert__GPR32AsmReg1_0__UImm161_1
1908 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addUImmOperands_LT_16_GT_, 2, CVT_Done },
1909 // Convert__GPR32AsmReg1_0__UImm16_Relaxed1_1
1910 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addUImmOperands_LT_16_GT_, 2, CVT_Done },
1911 // Convert__Reg1_0__Imm1_1
1912 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
1913 // Convert__GPR32AsmReg1_0__MicroMipsMemSP2_1
1914 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1915 // Convert__GPRMM16AsmReg1_0__MicroMipsMemGP2_1
1916 { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1917 // Convert__GPR32AsmReg1_0__Mem2_1__Tie0_1_1
1918 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Tied, Tie0_1_1, CVT_Done },
1919 // Convert__GPR32AsmReg1_0__MemOffsetSimm9_02_1__Tie0_1_1
1920 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Tied, Tie0_1_1, CVT_Done },
1921 // Convert__RegList1_0__Mem2_1
1922 { CVT_95_addRegListOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1923 // Convert__RegList161_0__MemOffsetUimm42_1
1924 { CVT_95_addRegListOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1925 // ConvertCustom_ConvertXWPOperands
1926 { CVT_ConvertXWPOperands, 0, CVT_Done },
1927 // Convert__GPR32AsmReg1_0__MemOffsetSimm12_02_1
1928 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1929 // Convert__FGR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1
1930 { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 4, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
1931 // Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2__AFGR64AsmReg1_3
1932 { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_95_addAFGR64AsmRegOperands, 3, CVT_95_addAFGR64AsmRegOperands, 4, CVT_Done },
1933 // Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2__FGR64AsmReg1_3
1934 { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addFGR64AsmRegOperands, 3, CVT_95_addFGR64AsmRegOperands, 4, CVT_Done },
1935 // Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2__FGR32AsmReg1_3
1936 { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addFGR32AsmRegOperands, 3, CVT_95_addFGR32AsmRegOperands, 4, CVT_Done },
1937 // Convert__FGR64AsmReg1_0__Tie0_1_1__FGR64AsmReg1_1__FGR64AsmReg1_2
1938 { CVT_95_addFGR64AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addFGR64AsmRegOperands, 3, CVT_Done },
1939 // Convert__FGR32AsmReg1_0__Tie0_1_1__FGR32AsmReg1_1__FGR32AsmReg1_2
1940 { CVT_95_addFGR32AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addFGR32AsmRegOperands, 3, CVT_Done },
1941 // Convert__GPR32AsmReg1_0__COP0AsmReg1_1__imm_95_0
1942 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addCOP0AsmRegOperands, 2, CVT_imm_95_0, 0, CVT_Done },
1943 // Convert__GPR32AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2
1944 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addCOP0AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
1945 // Convert__GPR32AsmReg1_0__FGR64AsmReg1_1
1946 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_Done },
1947 // Convert__GPR32AsmReg1_0__COP2AsmReg1_1__imm_95_0
1948 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addCOP2AsmRegOperands, 2, CVT_imm_95_0, 0, CVT_Done },
1949 // Convert__GPR32AsmReg1_0__COP2AsmReg1_1__ConstantUImm3_01_2
1950 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addCOP2AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
1951 // Convert__GPR32AsmReg1_0__AFGR64AsmReg1_1
1952 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_Done },
1953 // Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1
1954 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addACC64DSPAsmRegOperands, 2, CVT_Done },
1955 // Convert__GPR32AsmReg1_0__regAC0
1956 { CVT_95_addGPR32AsmRegOperands, 1, CVT_regAC0, 0, CVT_Done },
1957 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0
1958 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_imm_95_0, 0, CVT_Done },
1959 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm1_01_2__ConstantUImm3_01_3__ConstantUImm1_01_4
1960 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 4, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 5, CVT_Done },
1961 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__regZERO
1962 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_regZERO, 0, CVT_Done },
1963 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__regZERO_64
1964 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_regZERO_64, 0, CVT_Done },
1965 // Convert__GPRMM16AsmRegMovePPairFirst1_0__GPRMM16AsmRegMovePPairSecond1_1__GPRMM16AsmRegMoveP1_2__GPRMM16AsmRegMoveP1_3
1966 { CVT_95_addGPRMM16AsmRegMovePPairFirstOperands, 1, CVT_95_addGPRMM16AsmRegMovePPairSecondOperands, 2, CVT_95_addGPRMM16AsmRegMovePOperands, 3, CVT_95_addGPRMM16AsmRegMovePOperands, 4, CVT_Done },
1967 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1
1968 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addFCCAsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done },
1969 // Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__FCCAsmReg1_2__Tie0_1_1
1970 { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_95_addFCCAsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done },
1971 // Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FCCAsmReg1_2__Tie0_1_1
1972 { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addFCCAsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done },
1973 // Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1
1974 { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addFCCAsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done },
1975 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1
1976 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done },
1977 // Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1
1978 { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done },
1979 // Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1
1980 { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done },
1981 // Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1
1982 { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done },
1983 // Convert__COP0AsmReg1_1__GPR32AsmReg1_0__imm_95_0
1984 { CVT_95_addCOP0AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_imm_95_0, 0, CVT_Done },
1985 // Convert__COP0AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2
1986 { CVT_95_addCOP0AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
1987 // Convert__FGR64AsmReg1_1__GPR32AsmReg1_0
1988 { CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
1989 // Convert__COP2AsmReg1_1__GPR32AsmReg1_0__imm_95_0
1990 { CVT_95_addCOP2AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_imm_95_0, 0, CVT_Done },
1991 // Convert__COP2AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2
1992 { CVT_95_addCOP2AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
1993 // Convert__AFGR64AsmReg1_1__Tie0_1_1__GPR32AsmReg1_0
1994 { CVT_95_addAFGR64AsmRegOperands, 2, CVT_Tied, Tie0_1_1, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
1995 // Convert__FGR64AsmReg1_1__Tie0_1_1__GPR32AsmReg1_0
1996 { CVT_95_addFGR64AsmRegOperands, 2, CVT_Tied, Tie0_1_1, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
1997 // Convert__HI32DSPAsmReg1_1__GPR32AsmReg1_0
1998 { CVT_95_addHI32DSPAsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
1999 // Convert__ACC64DSPAsmReg1_1__GPR32AsmReg1_0__Tie0_1_1
2000 { CVT_95_addACC64DSPAsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_Done },
2001 // Convert__LO32DSPAsmReg1_1__GPR32AsmReg1_0
2002 { CVT_95_addLO32DSPAsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
2003 // Convert__regAC0__GPR32AsmReg1_0
2004 { CVT_regAC0, 0, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
2005 // Convert__ACC64DSPAsmReg1_1__GPR32AsmReg1_0
2006 { CVT_95_addACC64DSPAsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
2007 // Convert__GPR32AsmReg1_1__GPR32AsmReg1_0
2008 { CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
2009 // Convert__GPR32AsmReg1_1__GPR32AsmReg1_0__ConstantUImm1_01_2__ConstantUImm3_01_3__ConstantUImm1_01_4
2010 { CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 4, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 5, CVT_Done },
2011 // Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2
2012 { CVT_95_addACC64DSPAsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done },
2013 // Convert__regZERO__imm_95_0
2014 { CVT_regZERO, 0, CVT_imm_95_0, 0, CVT_Done },
2015 // Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_0
2016 { CVT_95_addGPR32AsmRegOperands, 1, CVT_regZERO, 0, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
2017 // Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_1
2018 { CVT_95_addGPR32AsmRegOperands, 1, CVT_regZERO, 0, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
2019 // Convert__regZERO__regZERO__imm_95_0
2020 { CVT_regZERO, 0, CVT_regZERO, 0, CVT_imm_95_0, 0, CVT_Done },
2021 // Convert__regZERO__regS0
2022 { CVT_regZERO, 0, CVT_regS0, 0, CVT_Done },
2023 // Convert__regZERO__regZERO
2024 { CVT_regZERO, 0, CVT_regZERO, 0, CVT_Done },
2025 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__regZERO
2026 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_regZERO, 0, CVT_Done },
2027 // Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1
2028 { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addGPRMM16AsmRegOperands, 2, CVT_Done },
2029 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0
2030 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
2031 // Convert__GPR32AsmReg1_3__GPR32AsmReg1_1__ConstantUImm5_01_0
2032 { CVT_95_addGPR32AsmRegOperands, 4, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 1, CVT_Done },
2033 // Convert__GPR32AsmReg1_0__ConstantUImm7_01_1
2034 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_7_44__32_0_GT_, 2, CVT_Done },
2035 // Convert__GPR32AsmReg1_0__ConstantUImm10_01_1
2036 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_, 2, CVT_Done },
2037 // Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__imm_95_0
2038 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addHWRegsAsmRegOperands, 2, CVT_imm_95_0, 0, CVT_Done },
2039 // Convert__GPR64AsmReg1_0__HWRegsAsmReg1_1__imm_95_0
2040 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addHWRegsAsmRegOperands, 2, CVT_imm_95_0, 0, CVT_Done },
2041 // Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__ConstantUImm3_01_2
2042 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addHWRegsAsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
2043 // Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__ConstantUImm8_01_2
2044 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addHWRegsAsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_8_44__32_0_GT_, 3, CVT_Done },
2045 // Convert__GPR32AsmReg1_0__ConstantSImm10_01_1
2046 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantSImmOperands_LT_10_44__32_0_GT_, 2, CVT_Done },
2047 // Convert__GPR32AsmReg1_0__ConstantUImm8_01_1
2048 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_8_44__32_0_GT_, 2, CVT_Done },
2049 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1
2050 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 2, CVT_Done },
2051 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2
2052 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done },
2053 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_2
2054 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 3, CVT_Done },
2055 // Convert__GPRMM16AsmRegZero1_0__MicroMipsMem2_1
2056 { CVT_95_addGPRMM16AsmRegZeroOperands, 1, CVT_95_addMicroMipsMemOperands, 2, CVT_Done },
2057 // Convert__GPR32AsmReg1_0__Tie0_1_1__MemOffsetSimmPtr2_1
2058 { CVT_95_addGPR32AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 2, CVT_Done },
2059 // Convert__GPR32AsmReg1_0__Tie0_1_1__MemOffsetSimm9_02_1
2060 { CVT_95_addGPR32AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 2, CVT_Done },
2061 // Convert__GPR32AsmReg1_0__Tie0_1_1__Mem2_1
2062 { CVT_95_addGPR32AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 2, CVT_Done },
2063 // Convert__GPR64AsmReg1_0__Tie0_1_1__MemOffsetSimmPtr2_1
2064 { CVT_95_addGPR64AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 2, CVT_Done },
2065 // Convert__GPR64AsmReg1_0__Tie0_1_1__Mem2_1
2066 { CVT_95_addGPR64AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 2, CVT_Done },
2067 // Convert__ConstantUImm20_01_0
2068 { CVT_95_addConstantUImmOperands_LT_20_44__32_0_GT_, 1, CVT_Done },
2069 // Convert__Reg1_0__Tie0_1_1
2070 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_Done },
2071 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantSImm10_01_1
2072 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantSImmOperands_LT_10_44__32_0_GT_, 2, CVT_Done },
2073 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantSImm10_01_2
2074 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantSImmOperands_LT_10_44__32_0_GT_, 3, CVT_Done },
2075 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm32_Coerced1_1
2076 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_32_GT_, 2, CVT_Done },
2077 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm32_Coerced1_2
2078 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_32_GT_, 3, CVT_Done },
2079 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_0
2080 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
2081 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_2__GPR32AsmReg1_1
2082 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 3, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
2083 // Convert__ACC64DSPAsmReg1_0__ConstantSImm6_01_1__Tie0_1_1
2084 { CVT_95_addACC64DSPAsmRegOperands, 1, CVT_95_addConstantSImmOperands_LT_6_44__32_0_GT_, 2, CVT_Tied, Tie0_1_1, CVT_Done },
2085 // Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__Tie0_1_1
2086 { CVT_95_addACC64DSPAsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Tied, Tie0_1_1, CVT_Done },
2087 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2
2088 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 3, CVT_Done },
2089 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2
2090 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
2091 // Convert__UImm161_0
2092 { CVT_95_addUImmOperands_LT_16_GT_, 1, CVT_Done },
2093 // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__GPR32AsmReg1_3
2094 { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 4, CVT_Done },
2095 // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm4_01_3
2096 { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 4, CVT_Done },
2097 // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm1_01_3
2098 { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 4, CVT_Done },
2099 // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm3_01_3
2100 { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 4, CVT_Done },
2101 // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm2_01_3
2102 { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 4, CVT_Done },
2103 // Convert__Reg1_0__Reg1_1__ConstantUImm5_01_2
2104 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done },
2105 // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__GPR32AsmReg1_3
2106 { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 4, CVT_Done },
2107 // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_3
2108 { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 4, CVT_Done },
2109 // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm1_01_3
2110 { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 4, CVT_Done },
2111 // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_3
2112 { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 4, CVT_Done },
2113 // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm2_01_3
2114 { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 4, CVT_Done },
2115 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__InvNum1_1
2116 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
2117 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__InvNum1_2
2118 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
2119 // Convert__ConstantUImm5_01_0
2120 { CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 1, CVT_Done },
2121 // Convert__imm_95_17
2122 { CVT_imm_95_17, 0, CVT_Done },
2123 // Convert__imm_95_16
2124 { CVT_imm_95_16, 0, CVT_Done },
2125 // Convert__imm_95_18
2126 { CVT_imm_95_18, 0, CVT_Done },
2127 // Convert__imm_95_19
2128 { CVT_imm_95_19, 0, CVT_Done },
2129 // Convert__imm_95_4
2130 { CVT_imm_95_4, 0, CVT_Done },
2131 // Convert__MemOffsetSimm16_02_0
2132 { CVT_95_addMemOperands, 1, CVT_Done },
2133 // Convert__imm_95_2
2134 { CVT_imm_95_2, 0, CVT_Done },
2135 // Convert__imm_95_6
2136 { CVT_imm_95_6, 0, CVT_Done },
2137 // Convert__imm_95_5
2138 { CVT_imm_95_5, 0, CVT_Done },
2139 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm10_01_2
2140 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_, 3, CVT_Done },
2141 // Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1__GPR32AsmReg1_2
2142 { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done },
2143 // Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__GPR32AsmReg1_2
2144 { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done },
2145 // Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__GPR32AsmReg1_2
2146 { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done },
2147 // Convert__GPR32AsmReg1_0__imm_95_31
2148 { CVT_95_addGPR32AsmRegOperands, 1, CVT_imm_95_31, 0, CVT_Done },
2149};
2150
2151void MipsAsmParser::
2152convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode,
2153 const OperandVector &Operands) {
2154 assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!");
2155 const uint8_t *Converter = ConversionTable[Kind];
2156 Inst.setOpcode(Opcode);
2157 for (const uint8_t *p = Converter; *p; p += 2) {
2158 unsigned OpIdx = *(p + 1);
2159 switch (*p) {
2160 default: llvm_unreachable("invalid conversion entry!");
2161 case CVT_Reg:
2162 static_cast<MipsOperand &>(*Operands[OpIdx]).addRegOperands(Inst, 1);
2163 break;
2164 case CVT_Tied: {
2165 assert(*(p + 1) < (size_t)(std::end(TiedAsmOperandTable) -
2166 std::begin(TiedAsmOperandTable)) &&
2167 "Tied operand not found");
2168 unsigned TiedResOpnd = TiedAsmOperandTable[*(p + 1)][0];
2169 if (TiedResOpnd != (uint8_t)-1)
2170 Inst.addOperand(Inst.getOperand(TiedResOpnd));
2171 break;
2172 }
2173 case CVT_95_addGPR32AsmRegOperands:
2174 static_cast<MipsOperand &>(*Operands[OpIdx]).addGPR32AsmRegOperands(Inst, 1);
2175 break;
2176 case CVT_95_addAFGR64AsmRegOperands:
2177 static_cast<MipsOperand &>(*Operands[OpIdx]).addAFGR64AsmRegOperands(Inst, 1);
2178 break;
2179 case CVT_95_addFGR64AsmRegOperands:
2180 static_cast<MipsOperand &>(*Operands[OpIdx]).addFGR64AsmRegOperands(Inst, 1);
2181 break;
2182 case CVT_95_addFGR32AsmRegOperands:
2183 static_cast<MipsOperand &>(*Operands[OpIdx]).addFGR32AsmRegOperands(Inst, 1);
2184 break;
2185 case CVT_95_addSImmOperands_LT_32_GT_:
2186 static_cast<MipsOperand &>(*Operands[OpIdx]).addSImmOperands<32>(Inst, 1);
2187 break;
2188 case CVT_95_addMSA128AsmRegOperands:
2189 static_cast<MipsOperand &>(*Operands[OpIdx]).addMSA128AsmRegOperands(Inst, 1);
2190 break;
2191 case CVT_95_addSImmOperands_LT_16_GT_:
2192 static_cast<MipsOperand &>(*Operands[OpIdx]).addSImmOperands<16>(Inst, 1);
2193 break;
2194 case CVT_95_Reg:
2195 static_cast<MipsOperand &>(*Operands[OpIdx]).addRegOperands(Inst, 1);
2196 break;
2197 case CVT_95_addImmOperands:
2198 static_cast<MipsOperand &>(*Operands[OpIdx]).addImmOperands(Inst, 1);
2199 break;
2200 case CVT_95_addGPRMM16AsmRegOperands:
2201 static_cast<MipsOperand &>(*Operands[OpIdx]).addGPRMM16AsmRegOperands(Inst, 1);
2202 break;
2203 case CVT_95_addConstantSImmOperands_LT_4_44__32_0_GT_:
2204 static_cast<MipsOperand &>(*Operands[OpIdx]).addConstantSImmOperands<4, 0>(Inst, 1);
2205 break;
2206 case CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_:
2207 static_cast<MipsOperand &>(*Operands[OpIdx]).addConstantUImmOperands<5, 0>(Inst, 1);
2208 break;
2209 case CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_:
2210 static_cast<MipsOperand &>(*Operands[OpIdx]).addConstantUImmOperands<2, 0>(Inst, 1);
2211 break;
2212 case CVT_95_addUImmOperands_LT_16_GT_:
2213 static_cast<MipsOperand &>(*Operands[OpIdx]).addUImmOperands<16>(Inst, 1);
2214 break;
2215 case CVT_95_addGPR64AsmRegOperands:
2216 static_cast<MipsOperand &>(*Operands[OpIdx]).addGPR64AsmRegOperands(Inst, 1);
2217 break;
2218 case CVT_95_addConstantUImmOperands_LT_8_44__32_0_GT_:
2219 static_cast<MipsOperand &>(*Operands[OpIdx]).addConstantUImmOperands<8, 0>(Inst, 1);
2220 break;
2221 case CVT_regZERO:
2222 Inst.addOperand(MCOperand::createReg(Mips::ZERO));
2223 break;
2224 case CVT_95_addConstantUImmOperands_LT_5_44__32_32_44__32__MINUS_32_GT_:
2225 static_cast<MipsOperand &>(*Operands[OpIdx]).addConstantUImmOperands<5, 32, -32>(Inst, 1);
2226 break;
2227 case CVT_regFCC0:
2228 Inst.addOperand(MCOperand::createReg(Mips::FCC0));
2229 break;
2230 case CVT_95_addFCCAsmRegOperands:
2231 static_cast<MipsOperand &>(*Operands[OpIdx]).addFCCAsmRegOperands(Inst, 1);
2232 break;
2233 case CVT_95_addCOP2AsmRegOperands:
2234 static_cast<MipsOperand &>(*Operands[OpIdx]).addCOP2AsmRegOperands(Inst, 1);
2235 break;
2236 case CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_:
2237 static_cast<MipsOperand &>(*Operands[OpIdx]).addConstantUImmOperands<3, 0>(Inst, 1);
2238 break;
2239 case CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_:
2240 static_cast<MipsOperand &>(*Operands[OpIdx]).addConstantUImmOperands<6, 0>(Inst, 1);
2241 break;
2242 case CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_:
2243 static_cast<MipsOperand &>(*Operands[OpIdx]).addConstantUImmOperands<4, 0>(Inst, 1);
2244 break;
2245 case CVT_imm_95_0:
2246 Inst.addOperand(MCOperand::createImm(0));
2247 break;
2248 case CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_:
2249 static_cast<MipsOperand &>(*Operands[OpIdx]).addConstantUImmOperands<10, 0>(Inst, 1);
2250 break;
2251 case CVT_95_addMemOperands:
2252 static_cast<MipsOperand &>(*Operands[OpIdx]).addMemOperands(Inst, 2);
2253 break;
2254 case CVT_95_addConstantSImmOperands_LT_5_44__32_0_GT_:
2255 static_cast<MipsOperand &>(*Operands[OpIdx]).addConstantSImmOperands<5, 0>(Inst, 1);
2256 break;
2257 case CVT_95_addCCRAsmRegOperands:
2258 static_cast<MipsOperand &>(*Operands[OpIdx]).addCCRAsmRegOperands(Inst, 1);
2259 break;
2260 case CVT_95_addMSACtrlAsmRegOperands:
2261 static_cast<MipsOperand &>(*Operands[OpIdx]).addMSACtrlAsmRegOperands(Inst, 1);
2262 break;
2263 case CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_:
2264 static_cast<MipsOperand &>(*Operands[OpIdx]).addConstantUImmOperands<1, 0>(Inst, 1);
2265 break;
2266 case CVT_95_addConstantUImmOperands_LT_5_44__32_33_GT_:
2267 static_cast<MipsOperand &>(*Operands[OpIdx]).addConstantUImmOperands<5, 33>(Inst, 1);
2268 break;
2269 case CVT_95_addConstantUImmOperands_LT_5_44__32_32_GT_:
2270 static_cast<MipsOperand &>(*Operands[OpIdx]).addConstantUImmOperands<5, 32>(Inst, 1);
2271 break;
2272 case CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_:
2273 static_cast<MipsOperand &>(*Operands[OpIdx]).addConstantUImmOperands<5, 1>(Inst, 1);
2274 break;
2275 case CVT_95_addGPR32NonZeroAsmRegOperands:
2276 static_cast<MipsOperand &>(*Operands[OpIdx]).addGPR32NonZeroAsmRegOperands(Inst, 1);
2277 break;
2278 case CVT_95_addGPR32ZeroAsmRegOperands:
2279 static_cast<MipsOperand &>(*Operands[OpIdx]).addGPR32ZeroAsmRegOperands(Inst, 1);
2280 break;
2281 case CVT_95_addConstantUImmOperands_LT_2_44__32_1_GT_:
2282 static_cast<MipsOperand &>(*Operands[OpIdx]).addConstantUImmOperands<2, 1>(Inst, 1);
2283 break;
2284 case CVT_95_addCOP0AsmRegOperands:
2285 static_cast<MipsOperand &>(*Operands[OpIdx]).addCOP0AsmRegOperands(Inst, 1);
2286 break;
2287 case CVT_regZERO_64:
2288 Inst.addOperand(MCOperand::createReg(Mips::ZERO_64));
2289 break;
2290 case CVT_95_addACC64DSPAsmRegOperands:
2291 static_cast<MipsOperand &>(*Operands[OpIdx]).addACC64DSPAsmRegOperands(Inst, 1);
2292 break;
2293 case CVT_95_addConstantUImmOperands_LT_1_GT_:
2294 static_cast<MipsOperand &>(*Operands[OpIdx]).addConstantUImmOperands<1>(Inst, 1);
2295 break;
2296 case CVT_regRA:
2297 Inst.addOperand(MCOperand::createReg(Mips::RA));
2298 break;
2299 case CVT_regRA_64:
2300 Inst.addOperand(MCOperand::createReg(Mips::RA_64));
2301 break;
2302 case CVT_95_addMicroMipsMemOperands:
2303 static_cast<MipsOperand &>(*Operands[OpIdx]).addMicroMipsMemOperands(Inst, 2);
2304 break;
2305 case CVT_95_addCOP3AsmRegOperands:
2306 static_cast<MipsOperand &>(*Operands[OpIdx]).addCOP3AsmRegOperands(Inst, 1);
2307 break;
2308 case CVT_95_addConstantSImmOperands_LT_10_44__32_0_GT_:
2309 static_cast<MipsOperand &>(*Operands[OpIdx]).addConstantSImmOperands<10, 0>(Inst, 1);
2310 break;
2311 case CVT_95_addConstantUImmOperands_LT_32_GT_:
2312 static_cast<MipsOperand &>(*Operands[OpIdx]).addConstantUImmOperands<32>(Inst, 1);
2313 break;
2314 case CVT_95_addStrictlyAFGR64AsmRegOperands:
2315 static_cast<MipsOperand &>(*Operands[OpIdx]).addStrictlyAFGR64AsmRegOperands(Inst, 1);
2316 break;
2317 case CVT_95_addStrictlyFGR64AsmRegOperands:
2318 static_cast<MipsOperand &>(*Operands[OpIdx]).addStrictlyFGR64AsmRegOperands(Inst, 1);
2319 break;
2320 case CVT_95_addStrictlyFGR32AsmRegOperands:
2321 static_cast<MipsOperand &>(*Operands[OpIdx]).addStrictlyFGR32AsmRegOperands(Inst, 1);
2322 break;
2323 case CVT_95_addConstantUImmOperands_LT_7_44__32__MINUS_1_GT_:
2324 static_cast<MipsOperand &>(*Operands[OpIdx]).addConstantUImmOperands<7, -1>(Inst, 1);
2325 break;
2326 case CVT_95_addRegListOperands:
2327 static_cast<MipsOperand &>(*Operands[OpIdx]).addRegListOperands(Inst, 1);
2328 break;
2329 case CVT_ConvertXWPOperands:
2330 ConvertXWPOperands(Inst, Operands);
2331 break;
2332 case CVT_regAC0:
2333 Inst.addOperand(MCOperand::createReg(Mips::AC0));
2334 break;
2335 case CVT_95_addGPRMM16AsmRegMovePPairFirstOperands:
2336 static_cast<MipsOperand &>(*Operands[OpIdx]).addGPRMM16AsmRegMovePPairFirstOperands(Inst, 1);
2337 break;
2338 case CVT_95_addGPRMM16AsmRegMovePPairSecondOperands:
2339 static_cast<MipsOperand &>(*Operands[OpIdx]).addGPRMM16AsmRegMovePPairSecondOperands(Inst, 1);
2340 break;
2341 case CVT_95_addGPRMM16AsmRegMovePOperands:
2342 static_cast<MipsOperand &>(*Operands[OpIdx]).addGPRMM16AsmRegMovePOperands(Inst, 1);
2343 break;
2344 case CVT_95_addHI32DSPAsmRegOperands:
2345 static_cast<MipsOperand &>(*Operands[OpIdx]).addHI32DSPAsmRegOperands(Inst, 1);
2346 break;
2347 case CVT_95_addLO32DSPAsmRegOperands:
2348 static_cast<MipsOperand &>(*Operands[OpIdx]).addLO32DSPAsmRegOperands(Inst, 1);
2349 break;
2350 case CVT_regS0:
2351 Inst.addOperand(MCOperand::createReg(Mips::S0));
2352 break;
2353 case CVT_95_addConstantUImmOperands_LT_7_44__32_0_GT_:
2354 static_cast<MipsOperand &>(*Operands[OpIdx]).addConstantUImmOperands<7, 0>(Inst, 1);
2355 break;
2356 case CVT_95_addHWRegsAsmRegOperands:
2357 static_cast<MipsOperand &>(*Operands[OpIdx]).addHWRegsAsmRegOperands(Inst, 1);
2358 break;
2359 case CVT_95_addGPRMM16AsmRegZeroOperands:
2360 static_cast<MipsOperand &>(*Operands[OpIdx]).addGPRMM16AsmRegZeroOperands(Inst, 1);
2361 break;
2362 case CVT_95_addConstantUImmOperands_LT_20_44__32_0_GT_:
2363 static_cast<MipsOperand &>(*Operands[OpIdx]).addConstantUImmOperands<20, 0>(Inst, 1);
2364 break;
2365 case CVT_95_addConstantSImmOperands_LT_6_44__32_0_GT_:
2366 static_cast<MipsOperand &>(*Operands[OpIdx]).addConstantSImmOperands<6, 0>(Inst, 1);
2367 break;
2368 case CVT_imm_95_17:
2369 Inst.addOperand(MCOperand::createImm(17));
2370 break;
2371 case CVT_imm_95_16:
2372 Inst.addOperand(MCOperand::createImm(16));
2373 break;
2374 case CVT_imm_95_18:
2375 Inst.addOperand(MCOperand::createImm(18));
2376 break;
2377 case CVT_imm_95_19:
2378 Inst.addOperand(MCOperand::createImm(19));
2379 break;
2380 case CVT_imm_95_4:
2381 Inst.addOperand(MCOperand::createImm(4));
2382 break;
2383 case CVT_imm_95_2:
2384 Inst.addOperand(MCOperand::createImm(2));
2385 break;
2386 case CVT_imm_95_6:
2387 Inst.addOperand(MCOperand::createImm(6));
2388 break;
2389 case CVT_imm_95_5:
2390 Inst.addOperand(MCOperand::createImm(5));
2391 break;
2392 case CVT_imm_95_31:
2393 Inst.addOperand(MCOperand::createImm(31));
2394 break;
2395 }
2396 }
2397}
2398
2399void MipsAsmParser::
2400convertToMapAndConstraints(unsigned Kind,
2401 const OperandVector &Operands) {
2402 assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!");
2403 unsigned NumMCOperands = 0;
2404 const uint8_t *Converter = ConversionTable[Kind];
2405 for (const uint8_t *p = Converter; *p; p += 2) {
2406 switch (*p) {
2407 default: llvm_unreachable("invalid conversion entry!");
2408 case CVT_Reg:
2409 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2410 Operands[*(p + 1)]->setConstraint("r");
2411 ++NumMCOperands;
2412 break;
2413 case CVT_Tied:
2414 ++NumMCOperands;
2415 break;
2416 case CVT_95_addGPR32AsmRegOperands:
2417 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2418 Operands[*(p + 1)]->setConstraint("m");
2419 NumMCOperands += 1;
2420 break;
2421 case CVT_95_addAFGR64AsmRegOperands:
2422 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2423 Operands[*(p + 1)]->setConstraint("m");
2424 NumMCOperands += 1;
2425 break;
2426 case CVT_95_addFGR64AsmRegOperands:
2427 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2428 Operands[*(p + 1)]->setConstraint("m");
2429 NumMCOperands += 1;
2430 break;
2431 case CVT_95_addFGR32AsmRegOperands:
2432 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2433 Operands[*(p + 1)]->setConstraint("m");
2434 NumMCOperands += 1;
2435 break;
2436 case CVT_95_addSImmOperands_LT_32_GT_:
2437 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2438 Operands[*(p + 1)]->setConstraint("m");
2439 NumMCOperands += 1;
2440 break;
2441 case CVT_95_addMSA128AsmRegOperands:
2442 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2443 Operands[*(p + 1)]->setConstraint("m");
2444 NumMCOperands += 1;
2445 break;
2446 case CVT_95_addSImmOperands_LT_16_GT_:
2447 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2448 Operands[*(p + 1)]->setConstraint("m");
2449 NumMCOperands += 1;
2450 break;
2451 case CVT_95_Reg:
2452 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2453 Operands[*(p + 1)]->setConstraint("r");
2454 NumMCOperands += 1;
2455 break;
2456 case CVT_95_addImmOperands:
2457 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2458 Operands[*(p + 1)]->setConstraint("m");
2459 NumMCOperands += 1;
2460 break;
2461 case CVT_95_addGPRMM16AsmRegOperands:
2462 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2463 Operands[*(p + 1)]->setConstraint("m");
2464 NumMCOperands += 1;
2465 break;
2466 case CVT_95_addConstantSImmOperands_LT_4_44__32_0_GT_:
2467 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2468 Operands[*(p + 1)]->setConstraint("m");
2469 NumMCOperands += 1;
2470 break;
2471 case CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_:
2472 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2473 Operands[*(p + 1)]->setConstraint("m");
2474 NumMCOperands += 1;
2475 break;
2476 case CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_:
2477 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2478 Operands[*(p + 1)]->setConstraint("m");
2479 NumMCOperands += 1;
2480 break;
2481 case CVT_95_addUImmOperands_LT_16_GT_:
2482 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2483 Operands[*(p + 1)]->setConstraint("m");
2484 NumMCOperands += 1;
2485 break;
2486 case CVT_95_addGPR64AsmRegOperands:
2487 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2488 Operands[*(p + 1)]->setConstraint("m");
2489 NumMCOperands += 1;
2490 break;
2491 case CVT_95_addConstantUImmOperands_LT_8_44__32_0_GT_:
2492 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2493 Operands[*(p + 1)]->setConstraint("m");
2494 NumMCOperands += 1;
2495 break;
2496 case CVT_regZERO:
2497 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2498 Operands[*(p + 1)]->setConstraint("m");
2499 ++NumMCOperands;
2500 break;
2501 case CVT_95_addConstantUImmOperands_LT_5_44__32_32_44__32__MINUS_32_GT_:
2502 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2503 Operands[*(p + 1)]->setConstraint("m");
2504 NumMCOperands += 1;
2505 break;
2506 case CVT_regFCC0:
2507 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2508 Operands[*(p + 1)]->setConstraint("m");
2509 ++NumMCOperands;
2510 break;
2511 case CVT_95_addFCCAsmRegOperands:
2512 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2513 Operands[*(p + 1)]->setConstraint("m");
2514 NumMCOperands += 1;
2515 break;
2516 case CVT_95_addCOP2AsmRegOperands:
2517 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2518 Operands[*(p + 1)]->setConstraint("m");
2519 NumMCOperands += 1;
2520 break;
2521 case CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_:
2522 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2523 Operands[*(p + 1)]->setConstraint("m");
2524 NumMCOperands += 1;
2525 break;
2526 case CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_:
2527 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2528 Operands[*(p + 1)]->setConstraint("m");
2529 NumMCOperands += 1;
2530 break;
2531 case CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_:
2532 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2533 Operands[*(p + 1)]->setConstraint("m");
2534 NumMCOperands += 1;
2535 break;
2536 case CVT_imm_95_0:
2537 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2538 Operands[*(p + 1)]->setConstraint("");
2539 ++NumMCOperands;
2540 break;
2541 case CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_:
2542 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2543 Operands[*(p + 1)]->setConstraint("m");
2544 NumMCOperands += 1;
2545 break;
2546 case CVT_95_addMemOperands:
2547 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2548 Operands[*(p + 1)]->setConstraint("m");
2549 NumMCOperands += 2;
2550 break;
2551 case CVT_95_addConstantSImmOperands_LT_5_44__32_0_GT_:
2552 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2553 Operands[*(p + 1)]->setConstraint("m");
2554 NumMCOperands += 1;
2555 break;
2556 case CVT_95_addCCRAsmRegOperands:
2557 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2558 Operands[*(p + 1)]->setConstraint("m");
2559 NumMCOperands += 1;
2560 break;
2561 case CVT_95_addMSACtrlAsmRegOperands:
2562 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2563 Operands[*(p + 1)]->setConstraint("m");
2564 NumMCOperands += 1;
2565 break;
2566 case CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_:
2567 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2568 Operands[*(p + 1)]->setConstraint("m");
2569 NumMCOperands += 1;
2570 break;
2571 case CVT_95_addConstantUImmOperands_LT_5_44__32_33_GT_:
2572 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2573 Operands[*(p + 1)]->setConstraint("m");
2574 NumMCOperands += 1;
2575 break;
2576 case CVT_95_addConstantUImmOperands_LT_5_44__32_32_GT_:
2577 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2578 Operands[*(p + 1)]->setConstraint("m");
2579 NumMCOperands += 1;
2580 break;
2581 case CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_:
2582 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2583 Operands[*(p + 1)]->setConstraint("m");
2584 NumMCOperands += 1;
2585 break;
2586 case CVT_95_addGPR32NonZeroAsmRegOperands:
2587 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2588 Operands[*(p + 1)]->setConstraint("m");
2589 NumMCOperands += 1;
2590 break;
2591 case CVT_95_addGPR32ZeroAsmRegOperands:
2592 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2593 Operands[*(p + 1)]->setConstraint("m");
2594 NumMCOperands += 1;
2595 break;
2596 case CVT_95_addConstantUImmOperands_LT_2_44__32_1_GT_:
2597 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2598 Operands[*(p + 1)]->setConstraint("m");
2599 NumMCOperands += 1;
2600 break;
2601 case CVT_95_addCOP0AsmRegOperands:
2602 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2603 Operands[*(p + 1)]->setConstraint("m");
2604 NumMCOperands += 1;
2605 break;
2606 case CVT_regZERO_64:
2607 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2608 Operands[*(p + 1)]->setConstraint("m");
2609 ++NumMCOperands;
2610 break;
2611 case CVT_95_addACC64DSPAsmRegOperands:
2612 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2613 Operands[*(p + 1)]->setConstraint("m");
2614 NumMCOperands += 1;
2615 break;
2616 case CVT_95_addConstantUImmOperands_LT_1_GT_:
2617 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2618 Operands[*(p + 1)]->setConstraint("m");
2619 NumMCOperands += 1;
2620 break;
2621 case CVT_regRA:
2622 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2623 Operands[*(p + 1)]->setConstraint("m");
2624 ++NumMCOperands;
2625 break;
2626 case CVT_regRA_64:
2627 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2628 Operands[*(p + 1)]->setConstraint("m");
2629 ++NumMCOperands;
2630 break;
2631 case CVT_95_addMicroMipsMemOperands:
2632 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2633 Operands[*(p + 1)]->setConstraint("m");
2634 NumMCOperands += 2;
2635 break;
2636 case CVT_95_addCOP3AsmRegOperands:
2637 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2638 Operands[*(p + 1)]->setConstraint("m");
2639 NumMCOperands += 1;
2640 break;
2641 case CVT_95_addConstantSImmOperands_LT_10_44__32_0_GT_:
2642 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2643 Operands[*(p + 1)]->setConstraint("m");
2644 NumMCOperands += 1;
2645 break;
2646 case CVT_95_addConstantUImmOperands_LT_32_GT_:
2647 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2648 Operands[*(p + 1)]->setConstraint("m");
2649 NumMCOperands += 1;
2650 break;
2651 case CVT_95_addStrictlyAFGR64AsmRegOperands:
2652 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2653 Operands[*(p + 1)]->setConstraint("m");
2654 NumMCOperands += 1;
2655 break;
2656 case CVT_95_addStrictlyFGR64AsmRegOperands:
2657 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2658 Operands[*(p + 1)]->setConstraint("m");
2659 NumMCOperands += 1;
2660 break;
2661 case CVT_95_addStrictlyFGR32AsmRegOperands:
2662 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2663 Operands[*(p + 1)]->setConstraint("m");
2664 NumMCOperands += 1;
2665 break;
2666 case CVT_95_addConstantUImmOperands_LT_7_44__32__MINUS_1_GT_:
2667 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2668 Operands[*(p + 1)]->setConstraint("m");
2669 NumMCOperands += 1;
2670 break;
2671 case CVT_95_addRegListOperands:
2672 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2673 Operands[*(p + 1)]->setConstraint("m");
2674 NumMCOperands += 1;
2675 break;
2676 case CVT_regAC0:
2677 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2678 Operands[*(p + 1)]->setConstraint("m");
2679 ++NumMCOperands;
2680 break;
2681 case CVT_95_addGPRMM16AsmRegMovePPairFirstOperands:
2682 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2683 Operands[*(p + 1)]->setConstraint("m");
2684 NumMCOperands += 1;
2685 break;
2686 case CVT_95_addGPRMM16AsmRegMovePPairSecondOperands:
2687 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2688 Operands[*(p + 1)]->setConstraint("m");
2689 NumMCOperands += 1;
2690 break;
2691 case CVT_95_addGPRMM16AsmRegMovePOperands:
2692 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2693 Operands[*(p + 1)]->setConstraint("m");
2694 NumMCOperands += 1;
2695 break;
2696 case CVT_95_addHI32DSPAsmRegOperands:
2697 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2698 Operands[*(p + 1)]->setConstraint("m");
2699 NumMCOperands += 1;
2700 break;
2701 case CVT_95_addLO32DSPAsmRegOperands:
2702 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2703 Operands[*(p + 1)]->setConstraint("m");
2704 NumMCOperands += 1;
2705 break;
2706 case CVT_regS0:
2707 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2708 Operands[*(p + 1)]->setConstraint("m");
2709 ++NumMCOperands;
2710 break;
2711 case CVT_95_addConstantUImmOperands_LT_7_44__32_0_GT_:
2712 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2713 Operands[*(p + 1)]->setConstraint("m");
2714 NumMCOperands += 1;
2715 break;
2716 case CVT_95_addHWRegsAsmRegOperands:
2717 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2718 Operands[*(p + 1)]->setConstraint("m");
2719 NumMCOperands += 1;
2720 break;
2721 case CVT_95_addGPRMM16AsmRegZeroOperands:
2722 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2723 Operands[*(p + 1)]->setConstraint("m");
2724 NumMCOperands += 1;
2725 break;
2726 case CVT_95_addConstantUImmOperands_LT_20_44__32_0_GT_:
2727 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2728 Operands[*(p + 1)]->setConstraint("m");
2729 NumMCOperands += 1;
2730 break;
2731 case CVT_95_addConstantSImmOperands_LT_6_44__32_0_GT_:
2732 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2733 Operands[*(p + 1)]->setConstraint("m");
2734 NumMCOperands += 1;
2735 break;
2736 case CVT_imm_95_17:
2737 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2738 Operands[*(p + 1)]->setConstraint("");
2739 ++NumMCOperands;
2740 break;
2741 case CVT_imm_95_16:
2742 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2743 Operands[*(p + 1)]->setConstraint("");
2744 ++NumMCOperands;
2745 break;
2746 case CVT_imm_95_18:
2747 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2748 Operands[*(p + 1)]->setConstraint("");
2749 ++NumMCOperands;
2750 break;
2751 case CVT_imm_95_19:
2752 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2753 Operands[*(p + 1)]->setConstraint("");
2754 ++NumMCOperands;
2755 break;
2756 case CVT_imm_95_4:
2757 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2758 Operands[*(p + 1)]->setConstraint("");
2759 ++NumMCOperands;
2760 break;
2761 case CVT_imm_95_2:
2762 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2763 Operands[*(p + 1)]->setConstraint("");
2764 ++NumMCOperands;
2765 break;
2766 case CVT_imm_95_6:
2767 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2768 Operands[*(p + 1)]->setConstraint("");
2769 ++NumMCOperands;
2770 break;
2771 case CVT_imm_95_5:
2772 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2773 Operands[*(p + 1)]->setConstraint("");
2774 ++NumMCOperands;
2775 break;
2776 case CVT_imm_95_31:
2777 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2778 Operands[*(p + 1)]->setConstraint("");
2779 ++NumMCOperands;
2780 break;
2781 }
2782 }
2783}
2784
2785namespace {
2786
2787/// MatchClassKind - The kinds of classes which participate in
2788/// instruction matching.
2789enum MatchClassKind {
2790 InvalidMatchClass = 0,
2791 OptionalMatchClass = 1,
2792 MCK__HASH_, // '#'
2793 MCK__40_, // '('
2794 MCK__41_, // ')'
2795 MCK_0, // '0'
2796 MCK_16, // '16'
2797 MCK__91_, // '['
2798 MCK__93_, // ']'
2799 MCK_bit, // 'bit'
2800 MCK_inst, // 'inst'
2801 MCK_LAST_TOKEN = MCK_inst,
2802 MCK_Reg37, // derived register class
2803 MCK_Reg19, // derived register class
2804 MCK_ACC128, // register class 'ACC128'
2805 MCK_ACC64, // register class 'ACC64'
2806 MCK_CPURAReg, // register class 'CPURAReg,RA'
2807 MCK_CPUSPReg, // register class 'CPUSPReg,SP32,SP'
2808 MCK_DSPCC, // register class 'DSPCC'
2809 MCK_GP32, // register class 'GP32'
2810 MCK_GP64, // register class 'GP64'
2811 MCK_GPR32ZERO, // register class 'GPR32ZERO,ZERO'
2812 MCK_HI32, // register class 'HI32'
2813 MCK_HI64, // register class 'HI64'
2814 MCK_LO32, // register class 'LO32'
2815 MCK_LO64, // register class 'LO64'
2816 MCK_PC, // register class 'PC'
2817 MCK_SP64, // register class 'SP64'
2818 MCK_Reg32, // derived register class
2819 MCK_Reg13, // derived register class
2820 MCK_Reg33, // derived register class
2821 MCK_Reg31, // derived register class
2822 MCK_Reg30, // derived register class
2823 MCK_Reg14, // derived register class
2824 MCK_Reg11, // derived register class
2825 MCK_GPRMM16MovePPairFirst, // register class 'GPRMM16MovePPairFirst'
2826 MCK_OCTEON_MPL, // register class 'OCTEON_MPL'
2827 MCK_OCTEON_P, // register class 'OCTEON_P'
2828 MCK_Reg28, // derived register class
2829 MCK_Reg23, // derived register class
2830 MCK_Reg9, // derived register class
2831 MCK_Reg4, // derived register class
2832 MCK_ACC64DSP, // register class 'ACC64DSP'
2833 MCK_HI32DSP, // register class 'HI32DSP'
2834 MCK_LO32DSP, // register class 'LO32DSP'
2835 MCK_Reg34, // derived register class
2836 MCK_GPRMM16MovePPairSecond, // register class 'GPRMM16MovePPairSecond'
2837 MCK_Reg29, // derived register class
2838 MCK_Reg27, // derived register class
2839 MCK_Reg10, // derived register class
2840 MCK_Reg8, // derived register class
2841 MCK_Reg25, // derived register class
2842 MCK_Reg22, // derived register class
2843 MCK_Reg21, // derived register class
2844 MCK_CPU16Regs, // register class 'CPU16Regs,GPRMM16'
2845 MCK_FCC, // register class 'FCC'
2846 MCK_GPRMM16MoveP, // register class 'GPRMM16MoveP'
2847 MCK_GPRMM16Zero, // register class 'GPRMM16Zero'
2848 MCK_Reg26, // derived register class
2849 MCK_CPU16RegsPlusSP, // register class 'CPU16RegsPlusSP'
2850 MCK_AFGR64, // register class 'AFGR64'
2851 MCK_MSA128WEvens, // register class 'MSA128WEvens'
2852 MCK_Reg24, // derived register class
2853 MCK_GPR32NONZERO, // register class 'GPR32NONZERO'
2854 MCK_CCR, // register class 'CCR'
2855 MCK_COP0, // register class 'COP0'
2856 MCK_COP2, // register class 'COP2'
2857 MCK_COP3, // register class 'COP3'
2858 MCK_DSPR, // register class 'DSPR,GPR32'
2859 MCK_FGR32, // register class 'FGR32,FGR32CC'
2860 MCK_FGR64CC, // register class 'FGR64CC,FGR64'
2861 MCK_GPR64, // register class 'GPR64'
2862 MCK_HWRegs, // register class 'HWRegs'
2863 MCK_MSA128B, // register class 'MSA128B,MSA128D,MSA128H,MSA128W'
2864 MCK_MSACtrl, // register class 'MSACtrl'
2865 MCK_LAST_REGISTER = MCK_MSACtrl,
2866 MCK_RegByHwMode_mips_ptr_rc, // register class by hwmode
2867 MCK_RegByHwMode_ptr_gp_rc, // register class by hwmode
2868 MCK_RegByHwMode_ptr_gpr16mm_rc, // register class by hwmode
2869 MCK_RegByHwMode_ptr_sp_rc, // register class by hwmode
2870 MCK_LAST_REGCLASS_BY_HWMODE = MCK_RegByHwMode_ptr_sp_rc,
2871 MCK_ACC64DSPAsmReg, // user defined class 'ACC64DSPAsmOperand'
2872 MCK_AFGR64AsmReg, // user defined class 'AFGR64AsmOperand'
2873 MCK_CCRAsmReg, // user defined class 'CCRAsmOperand'
2874 MCK_COP0AsmReg, // user defined class 'COP0AsmOperand'
2875 MCK_COP2AsmReg, // user defined class 'COP2AsmOperand'
2876 MCK_COP3AsmReg, // user defined class 'COP3AsmOperand'
2877 MCK_ConstantImm, // user defined class 'ConstantImmAsmOperandClass'
2878 MCK_FCCAsmReg, // user defined class 'FCCRegsAsmOperand'
2879 MCK_FGR32AsmReg, // user defined class 'FGR32AsmOperand'
2880 MCK_FGR64AsmReg, // user defined class 'FGR64AsmOperand'
2881 MCK_GPR32AsmReg, // user defined class 'GPR32AsmOperand'
2882 MCK_GPR32NonZeroAsmReg, // user defined class 'GPR32NonZeroAsmOperand'
2883 MCK_GPR32ZeroAsmReg, // user defined class 'GPR32ZeroAsmOperand'
2884 MCK_GPR64AsmReg, // user defined class 'GPR64AsmOperand'
2885 MCK_GPRMM16AsmReg, // user defined class 'GPRMM16AsmOperand'
2886 MCK_GPRMM16AsmRegMoveP, // user defined class 'GPRMM16AsmOperandMoveP'
2887 MCK_GPRMM16AsmRegMovePPairFirst, // user defined class 'GPRMM16AsmOperandMovePPairFirst'
2888 MCK_GPRMM16AsmRegMovePPairSecond, // user defined class 'GPRMM16AsmOperandMovePPairSecond'
2889 MCK_GPRMM16AsmRegZero, // user defined class 'GPRMM16AsmOperandZero'
2890 MCK_HI32DSPAsmReg, // user defined class 'HI32DSPAsmOperand'
2891 MCK_HWRegsAsmReg, // user defined class 'HWRegsAsmOperand'
2892 MCK_Imm, // user defined class 'ImmAsmOperand'
2893 MCK_LO32DSPAsmReg, // user defined class 'LO32DSPAsmOperand'
2894 MCK_MSA128AsmReg, // user defined class 'MSA128AsmOperand'
2895 MCK_MSACtrlAsmReg, // user defined class 'MSACtrlAsmOperand'
2896 MCK_MicroMipsMemGP, // user defined class 'MicroMipsMemGPAsmOperand'
2897 MCK_MicroMipsMem, // user defined class 'MicroMipsMemGPRMM16AsmOperand'
2898 MCK_MicroMipsMemSP, // user defined class 'MicroMipsMemSPAsmOperand'
2899 MCK_InvNum, // user defined class 'MipsInvertedImmoperand'
2900 MCK_JumpTarget, // user defined class 'MipsJumpTargetAsmOperand'
2901 MCK_MemOffsetSimmPtr, // user defined class 'MipsMemSimmPtrAsmOperand'
2902 MCK_MemOffsetUimm4, // user defined class 'MipsMemUimm4AsmOperand'
2903 MCK_MemOffsetSimm9_0, // user defined class 'anonymous_14695'
2904 MCK_MemOffsetSimm10_0, // user defined class 'anonymous_14696'
2905 MCK_MemOffsetSimm11_0, // user defined class 'anonymous_14697'
2906 MCK_MemOffsetSimm12_0, // user defined class 'anonymous_14698'
2907 MCK_MemOffsetSimm16_0, // user defined class 'anonymous_14699'
2908 MCK_MemOffsetSimm10_1, // user defined class 'anonymous_14700'
2909 MCK_MemOffsetSimm10_2, // user defined class 'anonymous_14701'
2910 MCK_MemOffsetSimm10_3, // user defined class 'anonymous_14702'
2911 MCK_Mem, // user defined class 'MipsMemAsmOperand'
2912 MCK_RegList16, // user defined class 'RegList16AsmOperand'
2913 MCK_RegList, // user defined class 'RegListAsmOperand'
2914 MCK_Simm18_Lsl3, // user defined class 'Simm18Lsl3AsmOperand'
2915 MCK_Simm19_Lsl2, // user defined class 'Simm19Lsl2AsmOperand'
2916 MCK_StrictlyAFGR64AsmReg, // user defined class 'StrictlyAFGR64AsmOperand'
2917 MCK_StrictlyFGR32AsmReg, // user defined class 'StrictlyFGR32AsmOperand'
2918 MCK_StrictlyFGR64AsmReg, // user defined class 'StrictlyFGR64AsmOperand'
2919 MCK_ConstantImmz, // user defined class 'ConstantImmzAsmOperandClass'
2920 MCK_ConstantUImm1_0, // user defined class 'ConstantUImm1AsmOperandClass'
2921 MCK_ConstantUImm2_0, // user defined class 'ConstantUImm2AsmOperandClass'
2922 MCK_ConstantUImm2_1, // user defined class 'ConstantUImm2Plus1AsmOperandClass'
2923 MCK_ConstantUImm3_0, // user defined class 'ConstantUImm3AsmOperandClass'
2924 MCK_ConstantSImm4_0, // user defined class 'ConstantSImm4AsmOperandClass'
2925 MCK_ConstantUImm4_0, // user defined class 'ConstantUImm4AsmOperandClass'
2926 MCK_ConstantSImm5_0, // user defined class 'ConstantSImm5AsmOperandClass'
2927 MCK_ConstantUImm5_0, // user defined class 'ConstantUImm5AsmOperandClass'
2928 MCK_ConstantUImm5_1, // user defined class 'ConstantUImm5Plus1AsmOperandClass'
2929 MCK_ConstantUImm5_Plus1_Report_UImm6, // user defined class 'ConstantUImm5Plus1ReportUImm6AsmOperandClass'
2930 MCK_ConstantUImm5_32_Norm, // user defined class 'ConstantUImm5Plus32NormalizeAsmOperandClass'
2931 MCK_ConstantUImm5_32, // user defined class 'ConstantUImm5Plus32AsmOperandClass'
2932 MCK_ConstantUImm5_0_Report_UImm6, // user defined class 'ConstantUImm5ReportUImm6AsmOperandClass'
2933 MCK_ConstantUImm5_33, // user defined class 'ConstantUImm5Plus33AsmOperandClass'
2934 MCK_ConstantUImmRange2_64, // user defined class 'ConstantUImm5_Range2_64AsmOperandClass'
2935 MCK_UImm5Lsl2, // user defined class 'ConstantUImm5Lsl2AsmOperandClass'
2936 MCK_ConstantSImm6_0, // user defined class 'ConstantSImm6AsmOperandClass'
2937 MCK_ConstantUImm6_0, // user defined class 'ConstantUImm6AsmOperandClass'
2938 MCK_UImm6Lsl2, // user defined class 'ConstantUImm6Lsl2AsmOperandClass'
2939 MCK_ConstantUImm7_0, // user defined class 'ConstantUImm7AsmOperandClass'
2940 MCK_UImm7_N1, // user defined class 'ConstantUImm7Sub1AsmOperandClass'
2941 MCK_ConstantUImm8_0, // user defined class 'ConstantUImm8AsmOperandClass'
2942 MCK_SImm7Lsl2, // user defined class 'ConstantSImm7Lsl2AsmOperandClass'
2943 MCK_ConstantSImm9_0, // user defined class 'ConstantSImm9AsmOperandClass'
2944 MCK_ConstantSImm10_0, // user defined class 'ConstantSImm10AsmOperandClass'
2945 MCK_ConstantUImm10_0, // user defined class 'ConstantUImm10AsmOperandClass'
2946 MCK_SImm10Lsl1, // user defined class 'ConstantSImm10Lsl1AsmOperandClass'
2947 MCK_ConstantSImm11_0, // user defined class 'ConstantSImm11AsmOperandClass'
2948 MCK_SImm10Lsl2, // user defined class 'ConstantSImm10Lsl2AsmOperandClass'
2949 MCK_SImm10Lsl3, // user defined class 'ConstantSImm10Lsl3AsmOperandClass'
2950 MCK_SImm16, // user defined class 'SImm16AsmOperandClass'
2951 MCK_SImm16_Relaxed, // user defined class 'SImm16RelaxedAsmOperandClass'
2952 MCK_UImm16_AltRelaxed, // user defined class 'UImm16AltRelaxedAsmOperandClass'
2953 MCK_UImm16, // user defined class 'UImm16AsmOperandClass'
2954 MCK_SImm19Lsl2, // user defined class 'ConstantSImm19Lsl2AsmOperandClass'
2955 MCK_UImm16_Relaxed, // user defined class 'UImm16RelaxedAsmOperandClass'
2956 MCK_ConstantUImm20_0, // user defined class 'ConstantUImm20AsmOperandClass'
2957 MCK_ConstantUImm26_0, // user defined class 'ConstantUImm26AsmOperandClass'
2958 MCK_SImm32, // user defined class 'SImm32AsmOperandClass'
2959 MCK_SImm32_Relaxed, // user defined class 'SImm32RelaxedAsmOperandClass'
2960 MCK_UImm32_Coerced, // user defined class 'UImm32CoercedAsmOperandClass'
2961 NumMatchClassKinds
2962};
2963
2964} // end anonymous namespace
2965
2966static unsigned getDiagKindFromRegisterClass(MatchClassKind RegisterClass) {
2967 return MCTargetAsmParser::Match_InvalidOperand;
2968}
2969
2970[[maybe_unused]] static const MCRegisterClass *getRegClassFromMatchKind(MatchClassKind Kind) {
2971 switch (Kind) {
2972 case MCK_ACC128:
2973 return &getMipsMCRegisterClass(Mips::ACC128RegClassID);
2974 case MCK_ACC64:
2975 return &getMipsMCRegisterClass(Mips::ACC64RegClassID);
2976 case MCK_CPURAReg:
2977 return &getMipsMCRegisterClass(Mips::CPURARegRegClassID);
2978 case MCK_CPUSPReg:
2979 return &getMipsMCRegisterClass(Mips::CPUSPRegRegClassID);
2980 case MCK_DSPCC:
2981 return &getMipsMCRegisterClass(Mips::DSPCCRegClassID);
2982 case MCK_GP32:
2983 return &getMipsMCRegisterClass(Mips::GP32RegClassID);
2984 case MCK_GP64:
2985 return &getMipsMCRegisterClass(Mips::GP64RegClassID);
2986 case MCK_GPR32ZERO:
2987 return &getMipsMCRegisterClass(Mips::GPR32ZERORegClassID);
2988 case MCK_HI32:
2989 return &getMipsMCRegisterClass(Mips::HI32RegClassID);
2990 case MCK_HI64:
2991 return &getMipsMCRegisterClass(Mips::HI64RegClassID);
2992 case MCK_LO32:
2993 return &getMipsMCRegisterClass(Mips::LO32RegClassID);
2994 case MCK_LO64:
2995 return &getMipsMCRegisterClass(Mips::LO64RegClassID);
2996 case MCK_SP64:
2997 return &getMipsMCRegisterClass(Mips::SP64RegClassID);
2998 case MCK_GPRMM16MovePPairFirst:
2999 return &getMipsMCRegisterClass(Mips::GPRMM16MovePPairFirstRegClassID);
3000 case MCK_OCTEON_MPL:
3001 return &getMipsMCRegisterClass(Mips::OCTEON_MPLRegClassID);
3002 case MCK_OCTEON_P:
3003 return &getMipsMCRegisterClass(Mips::OCTEON_PRegClassID);
3004 case MCK_ACC64DSP:
3005 return &getMipsMCRegisterClass(Mips::ACC64DSPRegClassID);
3006 case MCK_HI32DSP:
3007 return &getMipsMCRegisterClass(Mips::HI32DSPRegClassID);
3008 case MCK_LO32DSP:
3009 return &getMipsMCRegisterClass(Mips::LO32DSPRegClassID);
3010 case MCK_GPRMM16MovePPairSecond:
3011 return &getMipsMCRegisterClass(Mips::GPRMM16MovePPairSecondRegClassID);
3012 case MCK_CPU16Regs:
3013 return &getMipsMCRegisterClass(Mips::CPU16RegsRegClassID);
3014 case MCK_FCC:
3015 return &getMipsMCRegisterClass(Mips::FCCRegClassID);
3016 case MCK_GPRMM16MoveP:
3017 return &getMipsMCRegisterClass(Mips::GPRMM16MovePRegClassID);
3018 case MCK_GPRMM16Zero:
3019 return &getMipsMCRegisterClass(Mips::GPRMM16ZeroRegClassID);
3020 case MCK_CPU16RegsPlusSP:
3021 return &getMipsMCRegisterClass(Mips::CPU16RegsPlusSPRegClassID);
3022 case MCK_AFGR64:
3023 return &getMipsMCRegisterClass(Mips::AFGR64RegClassID);
3024 case MCK_MSA128WEvens:
3025 return &getMipsMCRegisterClass(Mips::MSA128WEvensRegClassID);
3026 case MCK_GPR32NONZERO:
3027 return &getMipsMCRegisterClass(Mips::GPR32NONZERORegClassID);
3028 case MCK_CCR:
3029 return &getMipsMCRegisterClass(Mips::CCRRegClassID);
3030 case MCK_COP0:
3031 return &getMipsMCRegisterClass(Mips::COP0RegClassID);
3032 case MCK_COP2:
3033 return &getMipsMCRegisterClass(Mips::COP2RegClassID);
3034 case MCK_COP3:
3035 return &getMipsMCRegisterClass(Mips::COP3RegClassID);
3036 case MCK_DSPR:
3037 return &getMipsMCRegisterClass(Mips::DSPRRegClassID);
3038 case MCK_FGR32:
3039 return &getMipsMCRegisterClass(Mips::FGR32RegClassID);
3040 case MCK_FGR64CC:
3041 return &getMipsMCRegisterClass(Mips::FGR64CCRegClassID);
3042 case MCK_GPR64:
3043 return &getMipsMCRegisterClass(Mips::GPR64RegClassID);
3044 case MCK_HWRegs:
3045 return &getMipsMCRegisterClass(Mips::HWRegsRegClassID);
3046 case MCK_MSA128B:
3047 return &getMipsMCRegisterClass(Mips::MSA128BRegClassID);
3048 case MCK_MSACtrl:
3049 return &getMipsMCRegisterClass(Mips::MSACtrlRegClassID);
3050 case MCK_ACC64DSPAsmReg:
3051 return &getMipsMCRegisterClass(Mips::ACC64DSPRegClassID);
3052 case MCK_AFGR64AsmReg:
3053 return &getMipsMCRegisterClass(Mips::AFGR64RegClassID);
3054 case MCK_CCRAsmReg:
3055 return &getMipsMCRegisterClass(Mips::CCRRegClassID);
3056 case MCK_COP0AsmReg:
3057 return &getMipsMCRegisterClass(Mips::COP0RegClassID);
3058 case MCK_COP2AsmReg:
3059 return &getMipsMCRegisterClass(Mips::COP2RegClassID);
3060 case MCK_COP3AsmReg:
3061 return &getMipsMCRegisterClass(Mips::COP3RegClassID);
3062 case MCK_FCCAsmReg:
3063 return &getMipsMCRegisterClass(Mips::FCCRegClassID);
3064 case MCK_FGR32AsmReg:
3065 return &getMipsMCRegisterClass(Mips::FGR32RegClassID);
3066 case MCK_FGR64AsmReg:
3067 return &getMipsMCRegisterClass(Mips::FGR64CCRegClassID);
3068 case MCK_GPR32AsmReg:
3069 return &getMipsMCRegisterClass(Mips::DSPRRegClassID);
3070 case MCK_GPR32NonZeroAsmReg:
3071 return &getMipsMCRegisterClass(Mips::GPR32NONZERORegClassID);
3072 case MCK_GPR32ZeroAsmReg:
3073 return &getMipsMCRegisterClass(Mips::GPR32ZERORegClassID);
3074 case MCK_GPR64AsmReg:
3075 return &getMipsMCRegisterClass(Mips::GPR64RegClassID);
3076 case MCK_GPRMM16AsmReg:
3077 return &getMipsMCRegisterClass(Mips::CPU16RegsRegClassID);
3078 case MCK_GPRMM16AsmRegMoveP:
3079 return &getMipsMCRegisterClass(Mips::GPRMM16MovePRegClassID);
3080 case MCK_GPRMM16AsmRegMovePPairFirst:
3081 return &getMipsMCRegisterClass(Mips::GPRMM16MovePPairFirstRegClassID);
3082 case MCK_GPRMM16AsmRegMovePPairSecond:
3083 return &getMipsMCRegisterClass(Mips::GPRMM16MovePPairSecondRegClassID);
3084 case MCK_GPRMM16AsmRegZero:
3085 return &getMipsMCRegisterClass(Mips::GPRMM16ZeroRegClassID);
3086 case MCK_HI32DSPAsmReg:
3087 return &getMipsMCRegisterClass(Mips::HI32DSPRegClassID);
3088 case MCK_HWRegsAsmReg:
3089 return &getMipsMCRegisterClass(Mips::HWRegsRegClassID);
3090 case MCK_LO32DSPAsmReg:
3091 return &getMipsMCRegisterClass(Mips::LO32DSPRegClassID);
3092 case MCK_MSA128AsmReg:
3093 return &getMipsMCRegisterClass(Mips::MSA128BRegClassID);
3094 case MCK_MSACtrlAsmReg:
3095 return &getMipsMCRegisterClass(Mips::MSACtrlRegClassID);
3096 case MCK_StrictlyAFGR64AsmReg:
3097 return &getMipsMCRegisterClass(Mips::AFGR64RegClassID);
3098 case MCK_StrictlyFGR32AsmReg:
3099 return &getMipsMCRegisterClass(Mips::FGR32RegClassID);
3100 case MCK_StrictlyFGR64AsmReg:
3101 return &getMipsMCRegisterClass(Mips::FGR64CCRegClassID);
3102 default:
3103 return nullptr;
3104 }
3105}
3106
3107static MatchClassKind matchTokenString(StringRef Name) {
3108 switch (Name.size()) {
3109 default: break;
3110 case 1: // 6 strings to match.
3111 switch (Name[0]) {
3112 default: break;
3113 case '#': // 1 string to match.
3114 return MCK__HASH_; // "#"
3115 case '(': // 1 string to match.
3116 return MCK__40_; // "("
3117 case ')': // 1 string to match.
3118 return MCK__41_; // ")"
3119 case '0': // 1 string to match.
3120 return MCK_0; // "0"
3121 case '[': // 1 string to match.
3122 return MCK__91_; // "["
3123 case ']': // 1 string to match.
3124 return MCK__93_; // "]"
3125 }
3126 break;
3127 case 2: // 1 string to match.
3128 if (memcmp(Name.data()+0, "16", 2) != 0)
3129 break;
3130 return MCK_16; // "16"
3131 case 3: // 1 string to match.
3132 if (memcmp(Name.data()+0, "bit", 3) != 0)
3133 break;
3134 return MCK_bit; // "bit"
3135 case 4: // 1 string to match.
3136 if (memcmp(Name.data()+0, "inst", 4) != 0)
3137 break;
3138 return MCK_inst; // "inst"
3139 }
3140 return InvalidMatchClass;
3141}
3142
3143/// isSubclass - Compute whether \p A is a subclass of \p B.
3144static bool isSubclass(MatchClassKind A, MatchClassKind B) {
3145 if (A == B)
3146 return true;
3147
3148 [[maybe_unused]] static constexpr struct {
3149 uint32_t Offset;
3150 uint16_t Start;
3151 uint16_t Length;
3152 } Table[] = {
3153 {0, 0, 0},
3154 {0, 0, 0},
3155 {0, 0, 0},
3156 {0, 0, 0},
3157 {0, 0, 0},
3158 {0, 0, 0},
3159 {0, 0, 0},
3160 {0, 0, 0},
3161 {0, 0, 0},
3162 {0, 0, 0},
3163 {0, 0, 0},
3164 {0, 61, 10},
3165 {10, 38, 33},
3166 {43, 0, 0},
3167 {43, 41, 1},
3168 {44, 62, 6},
3169 {50, 58, 10},
3170 {60, 0, 0},
3171 {60, 62, 6},
3172 {66, 61, 10},
3173 {76, 40, 28},
3174 {104, 42, 1},
3175 {105, 0, 0},
3176 {105, 43, 1},
3177 {106, 0, 0},
3178 {106, 0, 0},
3179 {106, 57, 14},
3180 {120, 29, 42},
3181 {162, 32, 36},
3182 {198, 44, 27},
3183 {225, 47, 24},
3184 {249, 37, 34},
3185 {283, 45, 23},
3186 {306, 39, 29},
3187 {335, 49, 19},
3188 {354, 0, 0},
3189 {354, 0, 0},
3190 {354, 46, 25},
3191 {379, 51, 20},
3192 {399, 48, 20},
3193 {419, 55, 13},
3194 {432, 0, 0},
3195 {432, 0, 0},
3196 {432, 0, 0},
3197 {432, 61, 10},
3198 {442, 62, 6},
3199 {448, 51, 20},
3200 {468, 50, 21},
3201 {489, 55, 13},
3202 {502, 53, 15},
3203 {517, 57, 14},
3204 {531, 70, 1},
3205 {532, 70, 1},
3206 {533, 58, 10},
3207 {543, 0, 0},
3208 {543, 67, 1},
3209 {544, 67, 1},
3210 {545, 61, 10},
3211 {555, 62, 6},
3212 {561, 0, 0},
3213 {561, 72, 1},
3214 {562, 70, 1},
3215 {563, 67, 1},
3216 {564, 0, 0},
3217 {564, 0, 0},
3218 {564, 0, 0},
3219 {564, 0, 0},
3220 {564, 0, 0},
3221 {564, 0, 0},
3222 {564, 0, 0},
3223 {564, 0, 0},
3224 {564, 0, 0},
3225 {564, 0, 0},
3226 {564, 0, 0},
3227 {564, 0, 0},
3228 {564, 0, 0},
3229 {564, 0, 0},
3230 {564, 0, 0},
3231 {564, 0, 0},
3232 {564, 0, 0},
3233 {564, 0, 0},
3234 {564, 0, 0},
3235 {564, 0, 0},
3236 {564, 0, 0},
3237 {564, 0, 0},
3238 {564, 0, 0},
3239 {564, 0, 0},
3240 {564, 0, 0},
3241 {564, 0, 0},
3242 {564, 0, 0},
3243 {564, 0, 0},
3244 {564, 0, 0},
3245 {564, 0, 0},
3246 {564, 0, 0},
3247 {564, 0, 0},
3248 {564, 0, 0},
3249 {564, 0, 0},
3250 {564, 0, 0},
3251 {564, 0, 0},
3252 {564, 0, 0},
3253 {564, 0, 0},
3254 {564, 0, 0},
3255 {564, 0, 0},
3256 {564, 0, 0},
3257 {564, 0, 0},
3258 {564, 0, 0},
3259 {564, 0, 0},
3260 {564, 0, 0},
3261 {564, 118, 1},
3262 {565, 118, 1},
3263 {566, 118, 1},
3264 {567, 118, 1},
3265 {568, 118, 1},
3266 {569, 118, 1},
3267 {570, 118, 1},
3268 {571, 118, 1},
3269 {572, 118, 1},
3270 {573, 118, 1},
3271 {574, 0, 0},
3272 {574, 0, 0},
3273 {574, 0, 0},
3274 {574, 0, 0},
3275 {574, 0, 0},
3276 {574, 0, 0},
3277 {574, 0, 0},
3278 {574, 0, 0},
3279 {574, 127, 41},
3280 {615, 128, 40},
3281 {655, 130, 38},
3282 {693, 130, 38},
3283 {731, 131, 37},
3284 {768, 132, 36},
3285 {804, 133, 35},
3286 {839, 134, 34},
3287 {873, 135, 33},
3288 {906, 136, 32},
3289 {938, 137, 31},
3290 {969, 138, 30},
3291 {999, 139, 29},
3292 {1028, 140, 28},
3293 {1056, 141, 27},
3294 {1083, 142, 26},
3295 {1109, 143, 25},
3296 {1134, 144, 24},
3297 {1158, 145, 23},
3298 {1181, 146, 22},
3299 {1203, 147, 21},
3300 {1224, 148, 20},
3301 {1244, 149, 19},
3302 {1263, 150, 18},
3303 {1281, 151, 17},
3304 {1298, 152, 16},
3305 {1314, 153, 15},
3306 {1329, 154, 14},
3307 {1343, 155, 13},
3308 {1356, 156, 12},
3309 {1368, 157, 11},
3310 {1379, 158, 10},
3311 {1389, 162, 6},
3312 {1395, 162, 6},
3313 {1401, 162, 6},
3314 {1407, 163, 5},
3315 {1412, 163, 5},
3316 {1417, 164, 4},
3317 {1421, 165, 3},
3318 {1424, 166, 2},
3319 {1426, 167, 1},
3320 {1427, 0, 0},
3321 };
3322
3323 static constexpr uint8_t Data[] = {
3324 0x01,
3325 0x06,
3326 0x80,
3327 0x01,
3328 0x00,
3329 0x1C,
3330 0x46,
3331 0x18,
3332 0x06,
3333 0x18,
3334 0x00,
3335 0x18,
3336 0x80,
3337 0x47,
3338 0x80,
3339 0x03,
3340 0x80,
3341 0xA4,
3342 0x10,
3343 0x01,
3344 0x16,
3345 0x80,
3346 0x88,
3347 0x14,
3348 0x61,
3349 0x52,
3350 0x88,
3351 0x00,
3352 0x53,
3353 0x88,
3354 0x00,
3355 0x07,
3356 0xCC,
3357 0x21,
3358 0x02,
3359 0x8C,
3360 0x48,
3361 0x11,
3362 0x0E,
3363 0x18,
3364 0x2D,
3365 0xC2,
3366 0x48,
3367 0x11,
3368 0xC6,
3369 0x20,
3370 0x02,
3371 0x1C,
3372 0x00,
3373 0xC0,
3374 0x50,
3375 0x22,
3376 0x1C,
3377 0x80,
3378 0x01,
3379 0x86,
3380 0x01,
3381 0x04,
3382 0x58,
3383 0x88,
3384 0x00,
3385 0x03,
3386 0x61,
3387 0x8A,
3388 0x30,
3389 0x02,
3390 0x3C,
3391 0xC2,
3392 0x03,
3393 0x0C,
3394 0xFF,
3395 0xFF,
3396 0xFE,
3397 0xFF,
3398 0xFF,
3399 0x3F,
3400 0xFE,
3401 0xFE,
3402 0xFF,
3403 0xFF,
3404 0x3F,
3405 0xFE,
3406 0xFF,
3407 0xFF,
3408 0xFF,
3409 0x8F,
3410 0xFF,
3411 0xFF,
3412 0xFF,
3413 0xFF,
3414 0xE3,
3415 0xFF,
3416 0xFF,
3417 0xFF,
3418 0x7F,
3419 0xFC,
3420 0xFF,
3421 0xFF,
3422 0xFF,
3423 0xC7,
3424 0xFF,
3425 0xFF,
3426 0xFF,
3427 0x3F,
3428 0xFE,
3429 0xFF,
3430 0xFF,
3431 0xFF,
3432 0xF8,
3433 0xFF,
3434 0xFF,
3435 0xFF,
3436 0xF1,
3437 0xFF,
3438 0xFF,
3439 0xFF,
3440 0xF1,
3441 0xFF,
3442 0xFF,
3443 0xFF,
3444 0xF8,
3445 0xFF,
3446 0xFF,
3447 0x3F,
3448 0xFE,
3449 0xFF,
3450 0xFF,
3451 0xC7,
3452 0xFF,
3453 0xFF,
3454 0x7F,
3455 0xFC,
3456 0xFF,
3457 0xFF,
3458 0xE3,
3459 0xFF,
3460 0xFF,
3461 0x8F,
3462 0xFF,
3463 0xFF,
3464 0x1F,
3465 0xFF,
3466 0xFF,
3467 0x1F,
3468 0xFF,
3469 0xFF,
3470 0x8F,
3471 0xFF,
3472 0xFF,
3473 0xE3,
3474 0xFF,
3475 0x7F,
3476 0xFC,
3477 0xFF,
3478 0xC7,
3479 0xFF,
3480 0x3F,
3481 0xFE,
3482 0xFF,
3483 0xF8,
3484 0xFF,
3485 0xF1,
3486 0xFF,
3487 0xF1,
3488 0xFF,
3489 0xF8,
3490 0x3F,
3491 0xFE,
3492 0xC7,
3493 0x7F,
3494 0xFC,
3495 0xE3,
3496 0x8F,
3497 0xFF,
3498 0xFF,
3499 0xFF,
3500 0xFF,
3501 0xFF,
3502 0x07,
3503 };
3504
3505 auto &Entry = Table[A];
3506 unsigned Idx = B - Entry.Start;
3507 if (Idx >= Entry.Length)
3508 return false;
3509 Idx += Entry.Offset;
3510 return (Data[Idx / 8] >> (Idx % 8)) & 1;
3511}
3512
3513static constexpr MatchClassKind RegClassByHwModeMatchTable[2][4] = {
3514 { // DefaultMode
3515 MCK_DSPR, // mips_ptr_rc
3516 MCK_GP32, // ptr_gp_rc
3517 MCK_CPU16Regs, // ptr_gpr16mm_rc
3518 MCK_CPUSPReg, // ptr_sp_rc
3519 },
3520 { // MIPS64
3521 MCK_GPR64, // mips_ptr_rc
3522 MCK_GP64, // ptr_gp_rc
3523 MCK_CPU16Regs, // ptr_gpr16mm_rc
3524 MCK_SP64, // ptr_sp_rc
3525 },
3526};
3527
3528static_assert(MCK_LAST_REGCLASS_BY_HWMODE - MCK_LAST_REGISTER == 4);
3529
3530[[maybe_unused]] static inline MatchClassKind
3531remapRegClassByHwMode(unsigned Kind, const MCSubtargetInfo &STI) {
3532 if (Kind > MCK_LAST_REGISTER && Kind <= MCK_LAST_REGCLASS_BY_HWMODE) {
3533 unsigned HwMode = STI.getHwMode(MCSubtargetInfo::HwMode_RegInfo);
3534 assert(HwMode < 2 && "Invalid HwMode");
3535 return RegClassByHwModeMatchTable[HwMode][Kind - (MCK_LAST_REGISTER + 1)];
3536 }
3537 return static_cast<MatchClassKind>(Kind);
3538}
3539
3540static unsigned validateOperandClass(MCParsedAsmOperand &GOp, MatchClassKind Kind, const MCSubtargetInfo &STI) {
3541 MipsOperand &Operand = (MipsOperand &)GOp;
3542 if (Kind == InvalidMatchClass)
3543 return MCTargetAsmParser::Match_InvalidOperand;
3544
3545 if (Kind <= MCK_LAST_TOKEN) {
3546 if (Operand.isToken() &&
3547 isSubclass(matchTokenString(Operand.getToken()), Kind))
3548 return MCTargetAsmParser::Match_Success;
3549 return MCTargetAsmParser::Match_InvalidOperand;
3550 }
3551
3552 switch (Kind) {
3553 default: break;
3554 case MCK_ACC64DSPAsmReg: {
3555 DiagnosticPredicate DP(Operand.isACCAsmReg());
3556 if (DP.isMatch())
3557 return MCTargetAsmParser::Match_Success;
3558 break;
3559 }
3560 case MCK_AFGR64AsmReg: {
3561 DiagnosticPredicate DP(Operand.isFGRAsmReg());
3562 if (DP.isMatch())
3563 return MCTargetAsmParser::Match_Success;
3564 break;
3565 }
3566 case MCK_CCRAsmReg: {
3567 DiagnosticPredicate DP(Operand.isCCRAsmReg());
3568 if (DP.isMatch())
3569 return MCTargetAsmParser::Match_Success;
3570 break;
3571 }
3572 case MCK_COP0AsmReg: {
3573 DiagnosticPredicate DP(Operand.isCOP0AsmReg());
3574 if (DP.isMatch())
3575 return MCTargetAsmParser::Match_Success;
3576 break;
3577 }
3578 case MCK_COP2AsmReg: {
3579 DiagnosticPredicate DP(Operand.isCOP2AsmReg());
3580 if (DP.isMatch())
3581 return MCTargetAsmParser::Match_Success;
3582 break;
3583 }
3584 case MCK_COP3AsmReg: {
3585 DiagnosticPredicate DP(Operand.isCOP3AsmReg());
3586 if (DP.isMatch())
3587 return MCTargetAsmParser::Match_Success;
3588 break;
3589 }
3590 case MCK_ConstantImm: {
3591 DiagnosticPredicate DP(Operand.isConstantImm());
3592 if (DP.isMatch())
3593 return MCTargetAsmParser::Match_Success;
3594 break;
3595 }
3596 case MCK_FCCAsmReg: {
3597 DiagnosticPredicate DP(Operand.isFCCAsmReg());
3598 if (DP.isMatch())
3599 return MCTargetAsmParser::Match_Success;
3600 break;
3601 }
3602 case MCK_FGR32AsmReg: {
3603 DiagnosticPredicate DP(Operand.isFGRAsmReg());
3604 if (DP.isMatch())
3605 return MCTargetAsmParser::Match_Success;
3606 break;
3607 }
3608 case MCK_FGR64AsmReg: {
3609 DiagnosticPredicate DP(Operand.isFGRAsmReg());
3610 if (DP.isMatch())
3611 return MCTargetAsmParser::Match_Success;
3612 break;
3613 }
3614 case MCK_GPR32AsmReg: {
3615 DiagnosticPredicate DP(Operand.isGPRAsmReg());
3616 if (DP.isMatch())
3617 return MCTargetAsmParser::Match_Success;
3618 break;
3619 }
3620 case MCK_GPR32NonZeroAsmReg: {
3621 DiagnosticPredicate DP(Operand.isGPRNonZeroAsmReg());
3622 if (DP.isMatch())
3623 return MCTargetAsmParser::Match_Success;
3624 break;
3625 }
3626 case MCK_GPR32ZeroAsmReg: {
3627 DiagnosticPredicate DP(Operand.isGPRZeroAsmReg());
3628 if (DP.isMatch())
3629 return MCTargetAsmParser::Match_Success;
3630 break;
3631 }
3632 case MCK_GPR64AsmReg: {
3633 DiagnosticPredicate DP(Operand.isGPRAsmReg());
3634 if (DP.isMatch())
3635 return MCTargetAsmParser::Match_Success;
3636 break;
3637 }
3638 case MCK_GPRMM16AsmReg: {
3639 DiagnosticPredicate DP(Operand.isMM16AsmReg());
3640 if (DP.isMatch())
3641 return MCTargetAsmParser::Match_Success;
3642 break;
3643 }
3644 case MCK_GPRMM16AsmRegMoveP: {
3645 DiagnosticPredicate DP(Operand.isMM16AsmRegMoveP());
3646 if (DP.isMatch())
3647 return MCTargetAsmParser::Match_Success;
3648 break;
3649 }
3650 case MCK_GPRMM16AsmRegMovePPairFirst: {
3651 DiagnosticPredicate DP(Operand.isMM16AsmRegMovePPairFirst());
3652 if (DP.isMatch())
3653 return MCTargetAsmParser::Match_Success;
3654 break;
3655 }
3656 case MCK_GPRMM16AsmRegMovePPairSecond: {
3657 DiagnosticPredicate DP(Operand.isMM16AsmRegMovePPairSecond());
3658 if (DP.isMatch())
3659 return MCTargetAsmParser::Match_Success;
3660 break;
3661 }
3662 case MCK_GPRMM16AsmRegZero: {
3663 DiagnosticPredicate DP(Operand.isMM16AsmRegZero());
3664 if (DP.isMatch())
3665 return MCTargetAsmParser::Match_Success;
3666 break;
3667 }
3668 case MCK_HI32DSPAsmReg: {
3669 DiagnosticPredicate DP(Operand.isACCAsmReg());
3670 if (DP.isMatch())
3671 return MCTargetAsmParser::Match_Success;
3672 break;
3673 }
3674 case MCK_HWRegsAsmReg: {
3675 DiagnosticPredicate DP(Operand.isHWRegsAsmReg());
3676 if (DP.isMatch())
3677 return MCTargetAsmParser::Match_Success;
3678 break;
3679 }
3680 case MCK_Imm: {
3681 DiagnosticPredicate DP(Operand.isImm());
3682 if (DP.isMatch())
3683 return MCTargetAsmParser::Match_Success;
3684 break;
3685 }
3686 case MCK_LO32DSPAsmReg: {
3687 DiagnosticPredicate DP(Operand.isACCAsmReg());
3688 if (DP.isMatch())
3689 return MCTargetAsmParser::Match_Success;
3690 break;
3691 }
3692 case MCK_MSA128AsmReg: {
3693 DiagnosticPredicate DP(Operand.isMSA128AsmReg());
3694 if (DP.isMatch())
3695 return MCTargetAsmParser::Match_Success;
3696 break;
3697 }
3698 case MCK_MSACtrlAsmReg: {
3699 DiagnosticPredicate DP(Operand.isMSACtrlAsmReg());
3700 if (DP.isMatch())
3701 return MCTargetAsmParser::Match_Success;
3702 break;
3703 }
3704 case MCK_MicroMipsMemGP: {
3705 DiagnosticPredicate DP(Operand.isMemWithSimmWordAlignedOffsetGP<9>());
3706 if (DP.isMatch())
3707 return MCTargetAsmParser::Match_Success;
3708 break;
3709 }
3710 case MCK_MicroMipsMem: {
3711 DiagnosticPredicate DP(Operand.isMemWithGRPMM16Base());
3712 if (DP.isMatch())
3713 return MCTargetAsmParser::Match_Success;
3714 break;
3715 }
3716 case MCK_MicroMipsMemSP: {
3717 DiagnosticPredicate DP(Operand.isMemWithUimmWordAlignedOffsetSP<7>());
3718 if (DP.isMatch())
3719 return MCTargetAsmParser::Match_Success;
3720 break;
3721 }
3722 case MCK_InvNum: {
3723 DiagnosticPredicate DP(Operand.isInvNum());
3724 if (DP.isMatch())
3725 return MCTargetAsmParser::Match_Success;
3726 break;
3727 }
3728 case MCK_JumpTarget: {
3729 DiagnosticPredicate DP(Operand.isImm());
3730 if (DP.isMatch())
3731 return MCTargetAsmParser::Match_Success;
3732 break;
3733 }
3734 case MCK_MemOffsetSimmPtr: {
3735 DiagnosticPredicate DP(Operand.isMemWithPtrSizeOffset());
3736 if (DP.isMatch())
3737 return MCTargetAsmParser::Match_Success;
3738 if (DP.isNearMatch())
3739 return MipsAsmParser::Match_MemSImmPtr;
3740 break;
3741 }
3742 case MCK_MemOffsetUimm4: {
3743 DiagnosticPredicate DP(Operand.isMemWithUimmOffsetSP<6>());
3744 if (DP.isMatch())
3745 return MCTargetAsmParser::Match_Success;
3746 break;
3747 }
3748 case MCK_MemOffsetSimm9_0: {
3749 DiagnosticPredicate DP(Operand.isMemWithSimmOffset<9, 0>());
3750 if (DP.isMatch())
3751 return MCTargetAsmParser::Match_Success;
3752 if (DP.isNearMatch())
3753 return MipsAsmParser::Match_MemSImm9;
3754 break;
3755 }
3756 case MCK_MemOffsetSimm10_0: {
3757 DiagnosticPredicate DP(Operand.isMemWithSimmOffset<10, 0>());
3758 if (DP.isMatch())
3759 return MCTargetAsmParser::Match_Success;
3760 if (DP.isNearMatch())
3761 return MipsAsmParser::Match_MemSImm10;
3762 break;
3763 }
3764 case MCK_MemOffsetSimm11_0: {
3765 DiagnosticPredicate DP(Operand.isMemWithSimmOffset<11, 0>());
3766 if (DP.isMatch())
3767 return MCTargetAsmParser::Match_Success;
3768 if (DP.isNearMatch())
3769 return MipsAsmParser::Match_MemSImm11;
3770 break;
3771 }
3772 case MCK_MemOffsetSimm12_0: {
3773 DiagnosticPredicate DP(Operand.isMemWithSimmOffset<12, 0>());
3774 if (DP.isMatch())
3775 return MCTargetAsmParser::Match_Success;
3776 if (DP.isNearMatch())
3777 return MipsAsmParser::Match_MemSImm12;
3778 break;
3779 }
3780 case MCK_MemOffsetSimm16_0: {
3781 DiagnosticPredicate DP(Operand.isMemWithSimmOffset<16, 0>());
3782 if (DP.isMatch())
3783 return MCTargetAsmParser::Match_Success;
3784 if (DP.isNearMatch())
3785 return MipsAsmParser::Match_MemSImm16;
3786 break;
3787 }
3788 case MCK_MemOffsetSimm10_1: {
3789 DiagnosticPredicate DP(Operand.isMemWithSimmOffset<10, 1>());
3790 if (DP.isMatch())
3791 return MCTargetAsmParser::Match_Success;
3792 if (DP.isNearMatch())
3793 return MipsAsmParser::Match_MemSImm10Lsl1;
3794 break;
3795 }
3796 case MCK_MemOffsetSimm10_2: {
3797 DiagnosticPredicate DP(Operand.isMemWithSimmOffset<10, 2>());
3798 if (DP.isMatch())
3799 return MCTargetAsmParser::Match_Success;
3800 if (DP.isNearMatch())
3801 return MipsAsmParser::Match_MemSImm10Lsl2;
3802 break;
3803 }
3804 case MCK_MemOffsetSimm10_3: {
3805 DiagnosticPredicate DP(Operand.isMemWithSimmOffset<10, 3>());
3806 if (DP.isMatch())
3807 return MCTargetAsmParser::Match_Success;
3808 if (DP.isNearMatch())
3809 return MipsAsmParser::Match_MemSImm10Lsl3;
3810 break;
3811 }
3812 case MCK_Mem: {
3813 DiagnosticPredicate DP(Operand.isMem());
3814 if (DP.isMatch())
3815 return MCTargetAsmParser::Match_Success;
3816 break;
3817 }
3818 case MCK_RegList16: {
3819 DiagnosticPredicate DP(Operand.isRegList16());
3820 if (DP.isMatch())
3821 return MCTargetAsmParser::Match_Success;
3822 break;
3823 }
3824 case MCK_RegList: {
3825 DiagnosticPredicate DP(Operand.isRegList());
3826 if (DP.isMatch())
3827 return MCTargetAsmParser::Match_Success;
3828 break;
3829 }
3830 case MCK_Simm18_Lsl3: {
3831 DiagnosticPredicate DP(Operand.isScaledSImm<18, 3>());
3832 if (DP.isMatch())
3833 return MCTargetAsmParser::Match_Success;
3834 if (DP.isNearMatch())
3835 return MipsAsmParser::Match_SImm18_Lsl3;
3836 break;
3837 }
3838 case MCK_Simm19_Lsl2: {
3839 DiagnosticPredicate DP(Operand.isScaledSImm<19, 2>());
3840 if (DP.isMatch())
3841 return MCTargetAsmParser::Match_Success;
3842 if (DP.isNearMatch())
3843 return MipsAsmParser::Match_SImm19_Lsl2;
3844 break;
3845 }
3846 case MCK_StrictlyAFGR64AsmReg: {
3847 DiagnosticPredicate DP(Operand.isStrictlyFGRAsmReg());
3848 if (DP.isMatch())
3849 return MCTargetAsmParser::Match_Success;
3850 break;
3851 }
3852 case MCK_StrictlyFGR32AsmReg: {
3853 DiagnosticPredicate DP(Operand.isStrictlyFGRAsmReg());
3854 if (DP.isMatch())
3855 return MCTargetAsmParser::Match_Success;
3856 break;
3857 }
3858 case MCK_StrictlyFGR64AsmReg: {
3859 DiagnosticPredicate DP(Operand.isStrictlyFGRAsmReg());
3860 if (DP.isMatch())
3861 return MCTargetAsmParser::Match_Success;
3862 break;
3863 }
3864 case MCK_ConstantImmz: {
3865 DiagnosticPredicate DP(Operand.isConstantImmz());
3866 if (DP.isMatch())
3867 return MCTargetAsmParser::Match_Success;
3868 if (DP.isNearMatch())
3869 return MipsAsmParser::Match_Immz;
3870 break;
3871 }
3872 case MCK_ConstantUImm1_0: {
3873 DiagnosticPredicate DP(Operand.isConstantUImm<1, 0>());
3874 if (DP.isMatch())
3875 return MCTargetAsmParser::Match_Success;
3876 if (DP.isNearMatch())
3877 return MipsAsmParser::Match_UImm1_0;
3878 break;
3879 }
3880 case MCK_ConstantUImm2_0: {
3881 DiagnosticPredicate DP(Operand.isConstantUImm<2, 0>());
3882 if (DP.isMatch())
3883 return MCTargetAsmParser::Match_Success;
3884 if (DP.isNearMatch())
3885 return MipsAsmParser::Match_UImm2_0;
3886 break;
3887 }
3888 case MCK_ConstantUImm2_1: {
3889 DiagnosticPredicate DP(Operand.isConstantUImm<2, 1>());
3890 if (DP.isMatch())
3891 return MCTargetAsmParser::Match_Success;
3892 if (DP.isNearMatch())
3893 return MipsAsmParser::Match_UImm2_1;
3894 break;
3895 }
3896 case MCK_ConstantUImm3_0: {
3897 DiagnosticPredicate DP(Operand.isConstantUImm<3, 0>());
3898 if (DP.isMatch())
3899 return MCTargetAsmParser::Match_Success;
3900 if (DP.isNearMatch())
3901 return MipsAsmParser::Match_UImm3_0;
3902 break;
3903 }
3904 case MCK_ConstantSImm4_0: {
3905 DiagnosticPredicate DP(Operand.isConstantSImm<4, 0>());
3906 if (DP.isMatch())
3907 return MCTargetAsmParser::Match_Success;
3908 if (DP.isNearMatch())
3909 return MipsAsmParser::Match_SImm4_0;
3910 break;
3911 }
3912 case MCK_ConstantUImm4_0: {
3913 DiagnosticPredicate DP(Operand.isConstantUImm<4, 0>());
3914 if (DP.isMatch())
3915 return MCTargetAsmParser::Match_Success;
3916 if (DP.isNearMatch())
3917 return MipsAsmParser::Match_UImm4_0;
3918 break;
3919 }
3920 case MCK_ConstantSImm5_0: {
3921 DiagnosticPredicate DP(Operand.isConstantSImm<5, 0>());
3922 if (DP.isMatch())
3923 return MCTargetAsmParser::Match_Success;
3924 if (DP.isNearMatch())
3925 return MipsAsmParser::Match_SImm5_0;
3926 break;
3927 }
3928 case MCK_ConstantUImm5_0: {
3929 DiagnosticPredicate DP(Operand.isConstantUImm<5, 0>());
3930 if (DP.isMatch())
3931 return MCTargetAsmParser::Match_Success;
3932 if (DP.isNearMatch())
3933 return MipsAsmParser::Match_UImm5_0;
3934 break;
3935 }
3936 case MCK_ConstantUImm5_1: {
3937 DiagnosticPredicate DP(Operand.isConstantUImm<5, 1>());
3938 if (DP.isMatch())
3939 return MCTargetAsmParser::Match_Success;
3940 if (DP.isNearMatch())
3941 return MipsAsmParser::Match_UImm5_1;
3942 break;
3943 }
3944 case MCK_ConstantUImm5_Plus1_Report_UImm6: {
3945 DiagnosticPredicate DP(Operand.isConstantUImm<5, 1>());
3946 if (DP.isMatch())
3947 return MCTargetAsmParser::Match_Success;
3948 if (DP.isNearMatch())
3949 return MipsAsmParser::Match_UImm5_1;
3950 break;
3951 }
3952 case MCK_ConstantUImm5_32_Norm: {
3953 DiagnosticPredicate DP(Operand.isConstantUImm<5, 32>());
3954 if (DP.isMatch())
3955 return MCTargetAsmParser::Match_Success;
3956 if (DP.isNearMatch())
3957 return MipsAsmParser::Match_UImm5_32;
3958 break;
3959 }
3960 case MCK_ConstantUImm5_32: {
3961 DiagnosticPredicate DP(Operand.isConstantUImm<5, 32>());
3962 if (DP.isMatch())
3963 return MCTargetAsmParser::Match_Success;
3964 if (DP.isNearMatch())
3965 return MipsAsmParser::Match_UImm5_32;
3966 break;
3967 }
3968 case MCK_ConstantUImm5_0_Report_UImm6: {
3969 DiagnosticPredicate DP(Operand.isConstantUImm<5, 0>());
3970 if (DP.isMatch())
3971 return MCTargetAsmParser::Match_Success;
3972 if (DP.isNearMatch())
3973 return MipsAsmParser::Match_UImm5_0_Report_UImm6;
3974 break;
3975 }
3976 case MCK_ConstantUImm5_33: {
3977 DiagnosticPredicate DP(Operand.isConstantUImm<5, 33>());
3978 if (DP.isMatch())
3979 return MCTargetAsmParser::Match_Success;
3980 if (DP.isNearMatch())
3981 return MipsAsmParser::Match_UImm5_33;
3982 break;
3983 }
3984 case MCK_ConstantUImmRange2_64: {
3985 DiagnosticPredicate DP(Operand.isConstantUImmRange<2, 64>());
3986 if (DP.isMatch())
3987 return MCTargetAsmParser::Match_Success;
3988 if (DP.isNearMatch())
3989 return MipsAsmParser::Match_UImmRange2_64;
3990 break;
3991 }
3992 case MCK_UImm5Lsl2: {
3993 DiagnosticPredicate DP(Operand.isScaledUImm<5, 2>());
3994 if (DP.isMatch())
3995 return MCTargetAsmParser::Match_Success;
3996 if (DP.isNearMatch())
3997 return MipsAsmParser::Match_UImm5_Lsl2;
3998 break;
3999 }
4000 case MCK_ConstantSImm6_0: {
4001 DiagnosticPredicate DP(Operand.isConstantSImm<6, 0>());
4002 if (DP.isMatch())
4003 return MCTargetAsmParser::Match_Success;
4004 if (DP.isNearMatch())
4005 return MipsAsmParser::Match_SImm6_0;
4006 break;
4007 }
4008 case MCK_ConstantUImm6_0: {
4009 DiagnosticPredicate DP(Operand.isConstantUImm<6, 0>());
4010 if (DP.isMatch())
4011 return MCTargetAsmParser::Match_Success;
4012 if (DP.isNearMatch())
4013 return MipsAsmParser::Match_UImm6_0;
4014 break;
4015 }
4016 case MCK_UImm6Lsl2: {
4017 DiagnosticPredicate DP(Operand.isScaledUImm<6, 2>());
4018 if (DP.isMatch())
4019 return MCTargetAsmParser::Match_Success;
4020 if (DP.isNearMatch())
4021 return MipsAsmParser::Match_UImm6_Lsl2;
4022 break;
4023 }
4024 case MCK_ConstantUImm7_0: {
4025 DiagnosticPredicate DP(Operand.isConstantUImm<7, 0>());
4026 if (DP.isMatch())
4027 return MCTargetAsmParser::Match_Success;
4028 if (DP.isNearMatch())
4029 return MipsAsmParser::Match_UImm7_0;
4030 break;
4031 }
4032 case MCK_UImm7_N1: {
4033 DiagnosticPredicate DP(Operand.isConstantUImm<7, -1>());
4034 if (DP.isMatch())
4035 return MCTargetAsmParser::Match_Success;
4036 if (DP.isNearMatch())
4037 return MipsAsmParser::Match_UImm7_N1;
4038 break;
4039 }
4040 case MCK_ConstantUImm8_0: {
4041 DiagnosticPredicate DP(Operand.isConstantUImm<8, 0>());
4042 if (DP.isMatch())
4043 return MCTargetAsmParser::Match_Success;
4044 if (DP.isNearMatch())
4045 return MipsAsmParser::Match_UImm8_0;
4046 break;
4047 }
4048 case MCK_SImm7Lsl2: {
4049 DiagnosticPredicate DP(Operand.isScaledSImm<7, 2>());
4050 if (DP.isMatch())
4051 return MCTargetAsmParser::Match_Success;
4052 if (DP.isNearMatch())
4053 return MipsAsmParser::Match_SImm7_Lsl2;
4054 break;
4055 }
4056 case MCK_ConstantSImm9_0: {
4057 DiagnosticPredicate DP(Operand.isConstantSImm<9, 0>());
4058 if (DP.isMatch())
4059 return MCTargetAsmParser::Match_Success;
4060 if (DP.isNearMatch())
4061 return MipsAsmParser::Match_SImm9_0;
4062 break;
4063 }
4064 case MCK_ConstantSImm10_0: {
4065 DiagnosticPredicate DP(Operand.isConstantSImm<10, 0>());
4066 if (DP.isMatch())
4067 return MCTargetAsmParser::Match_Success;
4068 if (DP.isNearMatch())
4069 return MipsAsmParser::Match_SImm10_0;
4070 break;
4071 }
4072 case MCK_ConstantUImm10_0: {
4073 DiagnosticPredicate DP(Operand.isConstantUImm<10, 0>());
4074 if (DP.isMatch())
4075 return MCTargetAsmParser::Match_Success;
4076 if (DP.isNearMatch())
4077 return MipsAsmParser::Match_UImm10_0;
4078 break;
4079 }
4080 case MCK_SImm10Lsl1: {
4081 DiagnosticPredicate DP(Operand.isScaledSImm<10, 1>());
4082 if (DP.isMatch())
4083 return MCTargetAsmParser::Match_Success;
4084 if (DP.isNearMatch())
4085 return MipsAsmParser::Match_SImm10_Lsl1;
4086 break;
4087 }
4088 case MCK_ConstantSImm11_0: {
4089 DiagnosticPredicate DP(Operand.isConstantSImm<11, 0>());
4090 if (DP.isMatch())
4091 return MCTargetAsmParser::Match_Success;
4092 if (DP.isNearMatch())
4093 return MipsAsmParser::Match_SImm11_0;
4094 break;
4095 }
4096 case MCK_SImm10Lsl2: {
4097 DiagnosticPredicate DP(Operand.isScaledSImm<10, 2>());
4098 if (DP.isMatch())
4099 return MCTargetAsmParser::Match_Success;
4100 if (DP.isNearMatch())
4101 return MipsAsmParser::Match_SImm10_Lsl2;
4102 break;
4103 }
4104 case MCK_SImm10Lsl3: {
4105 DiagnosticPredicate DP(Operand.isScaledSImm<10, 3>());
4106 if (DP.isMatch())
4107 return MCTargetAsmParser::Match_Success;
4108 if (DP.isNearMatch())
4109 return MipsAsmParser::Match_SImm10_Lsl3;
4110 break;
4111 }
4112 case MCK_SImm16: {
4113 DiagnosticPredicate DP(Operand.isSImm<16>());
4114 if (DP.isMatch())
4115 return MCTargetAsmParser::Match_Success;
4116 if (DP.isNearMatch())
4117 return MipsAsmParser::Match_SImm16;
4118 break;
4119 }
4120 case MCK_SImm16_Relaxed: {
4121 DiagnosticPredicate DP(Operand.isAnyImm<16>());
4122 if (DP.isMatch())
4123 return MCTargetAsmParser::Match_Success;
4124 if (DP.isNearMatch())
4125 return MipsAsmParser::Match_SImm16_Relaxed;
4126 break;
4127 }
4128 case MCK_UImm16_AltRelaxed: {
4129 DiagnosticPredicate DP(Operand.isUImm<16>());
4130 if (DP.isMatch())
4131 return MCTargetAsmParser::Match_Success;
4132 if (DP.isNearMatch())
4133 return MipsAsmParser::Match_UImm16_AltRelaxed;
4134 break;
4135 }
4136 case MCK_UImm16: {
4137 DiagnosticPredicate DP(Operand.isUImm<16>());
4138 if (DP.isMatch())
4139 return MCTargetAsmParser::Match_Success;
4140 if (DP.isNearMatch())
4141 return MipsAsmParser::Match_UImm16;
4142 break;
4143 }
4144 case MCK_SImm19Lsl2: {
4145 DiagnosticPredicate DP(Operand.isScaledSImm<19, 2>());
4146 if (DP.isMatch())
4147 return MCTargetAsmParser::Match_Success;
4148 if (DP.isNearMatch())
4149 return MipsAsmParser::Match_SImm19_Lsl2;
4150 break;
4151 }
4152 case MCK_UImm16_Relaxed: {
4153 DiagnosticPredicate DP(Operand.isAnyImm<16>());
4154 if (DP.isMatch())
4155 return MCTargetAsmParser::Match_Success;
4156 if (DP.isNearMatch())
4157 return MipsAsmParser::Match_UImm16_Relaxed;
4158 break;
4159 }
4160 case MCK_ConstantUImm20_0: {
4161 DiagnosticPredicate DP(Operand.isConstantUImm<20, 0>());
4162 if (DP.isMatch())
4163 return MCTargetAsmParser::Match_Success;
4164 if (DP.isNearMatch())
4165 return MipsAsmParser::Match_UImm20_0;
4166 break;
4167 }
4168 case MCK_ConstantUImm26_0: {
4169 DiagnosticPredicate DP(Operand.isConstantUImm<26, 0>());
4170 if (DP.isMatch())
4171 return MCTargetAsmParser::Match_Success;
4172 if (DP.isNearMatch())
4173 return MipsAsmParser::Match_UImm26_0;
4174 break;
4175 }
4176 case MCK_SImm32: {
4177 DiagnosticPredicate DP(Operand.isSImm<32>());
4178 if (DP.isMatch())
4179 return MCTargetAsmParser::Match_Success;
4180 if (DP.isNearMatch())
4181 return MipsAsmParser::Match_SImm32;
4182 break;
4183 }
4184 case MCK_SImm32_Relaxed: {
4185 DiagnosticPredicate DP(Operand.isAnyImm<33>());
4186 if (DP.isMatch())
4187 return MCTargetAsmParser::Match_Success;
4188 if (DP.isNearMatch())
4189 return MipsAsmParser::Match_SImm32_Relaxed;
4190 break;
4191 }
4192 case MCK_UImm32_Coerced: {
4193 DiagnosticPredicate DP(Operand.isSImm<33>());
4194 if (DP.isMatch())
4195 return MCTargetAsmParser::Match_Success;
4196 if (DP.isNearMatch())
4197 return MipsAsmParser::Match_UImm32_Coerced;
4198 break;
4199 }
4200 } // end switch (Kind)
4201
4202 Kind = remapRegClassByHwMode(Kind, STI);
4203
4204 if (Operand.isReg()) {
4205 static constexpr uint16_t Table[Mips::NUM_TARGET_REGS] = {
4206 InvalidMatchClass,
4207 MCK_GPR32NONZERO,
4208 MCK_DSPCC,
4209 InvalidMatchClass,
4210 InvalidMatchClass,
4211 InvalidMatchClass,
4212 InvalidMatchClass,
4213 InvalidMatchClass,
4214 MCK_GPR32NONZERO,
4215 MCK_GP32,
4216 MCK_MSACtrl,
4217 MCK_MSACtrl,
4218 MCK_MSACtrl,
4219 MCK_MSACtrl,
4220 MCK_MSACtrl,
4221 MCK_MSACtrl,
4222 MCK_MSACtrl,
4223 MCK_MSACtrl,
4224 MCK_PC,
4225 MCK_CPURAReg,
4226 MCK_CPUSPReg,
4227 MCK_GPR32ZERO,
4228 MCK_GPRMM16MovePPairFirst,
4229 MCK_Reg13,
4230 MCK_Reg13,
4231 MCK_Reg14,
4232 MCK_ACC64,
4233 MCK_ACC64DSP,
4234 MCK_ACC64DSP,
4235 MCK_ACC64DSP,
4236 MCK_Reg24,
4237 MCK_COP0,
4238 MCK_COP0,
4239 MCK_COP0,
4240 MCK_COP0,
4241 MCK_COP0,
4242 MCK_COP0,
4243 MCK_COP0,
4244 MCK_COP0,
4245 MCK_COP0,
4246 MCK_COP0,
4247 MCK_COP2,
4248 MCK_COP2,
4249 MCK_COP2,
4250 MCK_COP2,
4251 MCK_COP2,
4252 MCK_COP2,
4253 MCK_COP2,
4254 MCK_COP2,
4255 MCK_COP2,
4256 MCK_COP2,
4257 MCK_COP3,
4258 MCK_COP3,
4259 MCK_COP3,
4260 MCK_COP3,
4261 MCK_COP3,
4262 MCK_COP3,
4263 MCK_COP3,
4264 MCK_COP3,
4265 MCK_COP3,
4266 MCK_COP3,
4267 MCK_COP0,
4268 MCK_COP0,
4269 MCK_COP0,
4270 MCK_COP0,
4271 MCK_COP0,
4272 MCK_COP0,
4273 MCK_COP0,
4274 MCK_COP0,
4275 MCK_COP0,
4276 MCK_COP0,
4277 MCK_COP0,
4278 MCK_COP0,
4279 MCK_COP0,
4280 MCK_COP0,
4281 MCK_COP0,
4282 MCK_COP0,
4283 MCK_COP0,
4284 MCK_COP0,
4285 MCK_COP0,
4286 MCK_COP0,
4287 MCK_COP0,
4288 MCK_COP0,
4289 MCK_COP2,
4290 MCK_COP2,
4291 MCK_COP2,
4292 MCK_COP2,
4293 MCK_COP2,
4294 MCK_COP2,
4295 MCK_COP2,
4296 MCK_COP2,
4297 MCK_COP2,
4298 MCK_COP2,
4299 MCK_COP2,
4300 MCK_COP2,
4301 MCK_COP2,
4302 MCK_COP2,
4303 MCK_COP2,
4304 MCK_COP2,
4305 MCK_COP2,
4306 MCK_COP2,
4307 MCK_COP2,
4308 MCK_COP2,
4309 MCK_COP2,
4310 MCK_COP2,
4311 MCK_COP3,
4312 MCK_COP3,
4313 MCK_COP3,
4314 MCK_COP3,
4315 MCK_COP3,
4316 MCK_COP3,
4317 MCK_COP3,
4318 MCK_COP3,
4319 MCK_COP3,
4320 MCK_COP3,
4321 MCK_COP3,
4322 MCK_COP3,
4323 MCK_COP3,
4324 MCK_COP3,
4325 MCK_COP3,
4326 MCK_COP3,
4327 MCK_COP3,
4328 MCK_COP3,
4329 MCK_COP3,
4330 MCK_COP3,
4331 MCK_COP3,
4332 MCK_COP3,
4333 MCK_AFGR64,
4334 MCK_AFGR64,
4335 MCK_AFGR64,
4336 MCK_AFGR64,
4337 MCK_AFGR64,
4338 MCK_AFGR64,
4339 MCK_AFGR64,
4340 MCK_AFGR64,
4341 MCK_AFGR64,
4342 MCK_AFGR64,
4343 MCK_AFGR64,
4344 MCK_AFGR64,
4345 MCK_AFGR64,
4346 MCK_AFGR64,
4347 MCK_AFGR64,
4348 MCK_AFGR64,
4349 InvalidMatchClass,
4350 InvalidMatchClass,
4351 InvalidMatchClass,
4352 InvalidMatchClass,
4353 MCK_FGR32,
4354 MCK_FGR32,
4355 MCK_FGR32,
4356 MCK_FGR32,
4357 MCK_FGR32,
4358 MCK_FGR32,
4359 MCK_FGR32,
4360 MCK_FGR32,
4361 MCK_FGR32,
4362 MCK_FGR32,
4363 MCK_FGR32,
4364 MCK_FGR32,
4365 MCK_FGR32,
4366 MCK_FGR32,
4367 MCK_FGR32,
4368 MCK_FGR32,
4369 MCK_FGR32,
4370 MCK_FGR32,
4371 MCK_FGR32,
4372 MCK_FGR32,
4373 MCK_FGR32,
4374 MCK_FGR32,
4375 MCK_FGR32,
4376 MCK_FGR32,
4377 MCK_FGR32,
4378 MCK_FGR32,
4379 MCK_FGR32,
4380 MCK_FGR32,
4381 MCK_FGR32,
4382 MCK_FGR32,
4383 MCK_FGR32,
4384 MCK_FGR32,
4385 MCK_FCC,
4386 MCK_FCC,
4387 MCK_FCC,
4388 MCK_FCC,
4389 MCK_FCC,
4390 MCK_FCC,
4391 MCK_FCC,
4392 MCK_FCC,
4393 MCK_CCR,
4394 MCK_CCR,
4395 MCK_CCR,
4396 MCK_CCR,
4397 MCK_CCR,
4398 MCK_CCR,
4399 MCK_CCR,
4400 MCK_CCR,
4401 MCK_CCR,
4402 MCK_CCR,
4403 MCK_CCR,
4404 MCK_CCR,
4405 MCK_CCR,
4406 MCK_CCR,
4407 MCK_CCR,
4408 MCK_CCR,
4409 MCK_CCR,
4410 MCK_CCR,
4411 MCK_CCR,
4412 MCK_CCR,
4413 MCK_CCR,
4414 MCK_CCR,
4415 MCK_CCR,
4416 MCK_CCR,
4417 MCK_CCR,
4418 MCK_CCR,
4419 MCK_CCR,
4420 MCK_CCR,
4421 MCK_CCR,
4422 MCK_CCR,
4423 MCK_CCR,
4424 MCK_CCR,
4425 MCK_Reg24,
4426 InvalidMatchClass,
4427 InvalidMatchClass,
4428 InvalidMatchClass,
4429 InvalidMatchClass,
4430 InvalidMatchClass,
4431 InvalidMatchClass,
4432 InvalidMatchClass,
4433 InvalidMatchClass,
4434 InvalidMatchClass,
4435 InvalidMatchClass,
4436 InvalidMatchClass,
4437 InvalidMatchClass,
4438 InvalidMatchClass,
4439 InvalidMatchClass,
4440 InvalidMatchClass,
4441 InvalidMatchClass,
4442 InvalidMatchClass,
4443 InvalidMatchClass,
4444 InvalidMatchClass,
4445 InvalidMatchClass,
4446 InvalidMatchClass,
4447 InvalidMatchClass,
4448 InvalidMatchClass,
4449 InvalidMatchClass,
4450 InvalidMatchClass,
4451 InvalidMatchClass,
4452 InvalidMatchClass,
4453 InvalidMatchClass,
4454 InvalidMatchClass,
4455 InvalidMatchClass,
4456 InvalidMatchClass,
4457 InvalidMatchClass,
4458 MCK_GP64,
4459 MCK_HI32,
4460 MCK_HI32DSP,
4461 MCK_HI32DSP,
4462 MCK_HI32DSP,
4463 MCK_HWRegs,
4464 MCK_HWRegs,
4465 MCK_HWRegs,
4466 MCK_HWRegs,
4467 MCK_HWRegs,
4468 MCK_HWRegs,
4469 MCK_HWRegs,
4470 MCK_HWRegs,
4471 MCK_HWRegs,
4472 MCK_HWRegs,
4473 MCK_HWRegs,
4474 MCK_HWRegs,
4475 MCK_HWRegs,
4476 MCK_HWRegs,
4477 MCK_HWRegs,
4478 MCK_HWRegs,
4479 MCK_HWRegs,
4480 MCK_HWRegs,
4481 MCK_HWRegs,
4482 MCK_HWRegs,
4483 MCK_HWRegs,
4484 MCK_HWRegs,
4485 MCK_HWRegs,
4486 MCK_HWRegs,
4487 MCK_HWRegs,
4488 MCK_HWRegs,
4489 MCK_HWRegs,
4490 MCK_HWRegs,
4491 MCK_HWRegs,
4492 MCK_HWRegs,
4493 MCK_HWRegs,
4494 MCK_HWRegs,
4495 MCK_GPR32NONZERO,
4496 MCK_GPR32NONZERO,
4497 MCK_LO32,
4498 MCK_LO32DSP,
4499 MCK_LO32DSP,
4500 MCK_LO32DSP,
4501 MCK_OCTEON_MPL,
4502 MCK_OCTEON_MPL,
4503 MCK_OCTEON_MPL,
4504 MCK_MSACtrl,
4505 MCK_MSACtrl,
4506 MCK_MSACtrl,
4507 MCK_MSACtrl,
4508 MCK_MSACtrl,
4509 MCK_MSACtrl,
4510 MCK_MSACtrl,
4511 MCK_MSACtrl,
4512 MCK_MSACtrl,
4513 MCK_MSACtrl,
4514 MCK_MSACtrl,
4515 MCK_MSACtrl,
4516 MCK_MSACtrl,
4517 MCK_MSACtrl,
4518 MCK_MSACtrl,
4519 MCK_MSACtrl,
4520 MCK_MSACtrl,
4521 MCK_MSACtrl,
4522 MCK_MSACtrl,
4523 MCK_MSACtrl,
4524 MCK_MSACtrl,
4525 MCK_MSACtrl,
4526 MCK_MSACtrl,
4527 MCK_MSACtrl,
4528 MCK_OCTEON_P,
4529 MCK_OCTEON_P,
4530 MCK_OCTEON_P,
4531 MCK_Reg37,
4532 MCK_Reg9,
4533 MCK_Reg11,
4534 MCK_Reg10,
4535 MCK_Reg10,
4536 MCK_Reg10,
4537 MCK_GPRMM16MovePPairSecond,
4538 MCK_GPRMM16MovePPairSecond,
4539 MCK_GPR32NONZERO,
4540 MCK_SP64,
4541 MCK_GPR32NONZERO,
4542 MCK_GPR32NONZERO,
4543 MCK_GPR32NONZERO,
4544 MCK_GPR32NONZERO,
4545 MCK_GPR32NONZERO,
4546 MCK_GPR32NONZERO,
4547 MCK_GPR32NONZERO,
4548 MCK_GPR32NONZERO,
4549 MCK_GPR32NONZERO,
4550 MCK_GPR32NONZERO,
4551 MCK_Reg11,
4552 MCK_Reg11,
4553 MCK_MSA128WEvens,
4554 MCK_MSA128B,
4555 MCK_MSA128WEvens,
4556 MCK_MSA128B,
4557 MCK_MSA128WEvens,
4558 MCK_MSA128B,
4559 MCK_MSA128WEvens,
4560 MCK_MSA128B,
4561 MCK_MSA128WEvens,
4562 MCK_MSA128B,
4563 MCK_MSA128WEvens,
4564 MCK_MSA128B,
4565 MCK_MSA128WEvens,
4566 MCK_MSA128B,
4567 MCK_MSA128WEvens,
4568 MCK_MSA128B,
4569 MCK_MSA128WEvens,
4570 MCK_MSA128B,
4571 MCK_MSA128WEvens,
4572 MCK_MSA128B,
4573 MCK_MSA128WEvens,
4574 MCK_MSA128B,
4575 MCK_MSA128WEvens,
4576 MCK_MSA128B,
4577 MCK_MSA128WEvens,
4578 MCK_MSA128B,
4579 MCK_MSA128WEvens,
4580 MCK_MSA128B,
4581 MCK_MSA128WEvens,
4582 MCK_MSA128B,
4583 MCK_MSA128WEvens,
4584 MCK_MSA128B,
4585 MCK_Reg19,
4586 MCK_Reg31,
4587 MCK_Reg32,
4588 MCK_Reg32,
4589 MCK_Reg33,
4590 MCK_ACC128,
4591 MCK_FGR64CC,
4592 MCK_FGR64CC,
4593 MCK_FGR64CC,
4594 MCK_FGR64CC,
4595 MCK_FGR64CC,
4596 MCK_FGR64CC,
4597 MCK_FGR64CC,
4598 MCK_FGR64CC,
4599 MCK_FGR64CC,
4600 MCK_FGR64CC,
4601 MCK_FGR64CC,
4602 MCK_FGR64CC,
4603 MCK_FGR64CC,
4604 MCK_FGR64CC,
4605 MCK_FGR64CC,
4606 MCK_FGR64CC,
4607 MCK_FGR64CC,
4608 MCK_FGR64CC,
4609 MCK_FGR64CC,
4610 MCK_FGR64CC,
4611 MCK_FGR64CC,
4612 MCK_FGR64CC,
4613 MCK_FGR64CC,
4614 MCK_FGR64CC,
4615 MCK_FGR64CC,
4616 MCK_FGR64CC,
4617 MCK_FGR64CC,
4618 MCK_FGR64CC,
4619 MCK_FGR64CC,
4620 MCK_FGR64CC,
4621 MCK_FGR64CC,
4622 MCK_FGR64CC,
4623 InvalidMatchClass,
4624 MCK_HI64,
4625 MCK_Reg24,
4626 MCK_Reg24,
4627 MCK_LO64,
4628 MCK_Reg28,
4629 MCK_Reg30,
4630 MCK_Reg29,
4631 MCK_Reg29,
4632 MCK_Reg29,
4633 MCK_Reg34,
4634 MCK_Reg34,
4635 MCK_Reg24,
4636 MCK_Reg24,
4637 MCK_Reg24,
4638 MCK_Reg24,
4639 MCK_Reg24,
4640 MCK_Reg24,
4641 MCK_Reg24,
4642 MCK_Reg24,
4643 MCK_Reg24,
4644 MCK_Reg24,
4645 MCK_Reg24,
4646 MCK_Reg30,
4647 MCK_Reg30,
4648 };
4649
4650 MCRegister Reg = Operand.getReg();
4651 MatchClassKind OpKind = Reg.isPhysical() ? (MatchClassKind)Table[Reg.id()] : InvalidMatchClass;
4652 return isSubclass(OpKind, Kind) ? (unsigned)MCTargetAsmParser::Match_Success :
4653 getDiagKindFromRegisterClass(Kind);
4654 }
4655
4656 if (Kind > MCK_LAST_TOKEN && Kind <= MCK_LAST_REGISTER)
4657 return getDiagKindFromRegisterClass(Kind);
4658
4659 return MCTargetAsmParser::Match_InvalidOperand;
4660}
4661
4662#ifndef NDEBUG
4663const char *getMatchClassName(MatchClassKind Kind) {
4664 switch (Kind) {
4665 case InvalidMatchClass: return "InvalidMatchClass";
4666 case OptionalMatchClass: return "OptionalMatchClass";
4667 case MCK__HASH_: return "MCK__HASH_";
4668 case MCK__40_: return "MCK__40_";
4669 case MCK__41_: return "MCK__41_";
4670 case MCK_0: return "MCK_0";
4671 case MCK_16: return "MCK_16";
4672 case MCK__91_: return "MCK__91_";
4673 case MCK__93_: return "MCK__93_";
4674 case MCK_bit: return "MCK_bit";
4675 case MCK_inst: return "MCK_inst";
4676 case MCK_Reg37: return "MCK_Reg37";
4677 case MCK_Reg19: return "MCK_Reg19";
4678 case MCK_ACC128: return "MCK_ACC128";
4679 case MCK_ACC64: return "MCK_ACC64";
4680 case MCK_CPURAReg: return "MCK_CPURAReg";
4681 case MCK_CPUSPReg: return "MCK_CPUSPReg";
4682 case MCK_DSPCC: return "MCK_DSPCC";
4683 case MCK_GP32: return "MCK_GP32";
4684 case MCK_GP64: return "MCK_GP64";
4685 case MCK_GPR32ZERO: return "MCK_GPR32ZERO";
4686 case MCK_HI32: return "MCK_HI32";
4687 case MCK_HI64: return "MCK_HI64";
4688 case MCK_LO32: return "MCK_LO32";
4689 case MCK_LO64: return "MCK_LO64";
4690 case MCK_PC: return "MCK_PC";
4691 case MCK_SP64: return "MCK_SP64";
4692 case MCK_Reg32: return "MCK_Reg32";
4693 case MCK_Reg13: return "MCK_Reg13";
4694 case MCK_Reg33: return "MCK_Reg33";
4695 case MCK_Reg31: return "MCK_Reg31";
4696 case MCK_Reg30: return "MCK_Reg30";
4697 case MCK_Reg14: return "MCK_Reg14";
4698 case MCK_Reg11: return "MCK_Reg11";
4699 case MCK_GPRMM16MovePPairFirst: return "MCK_GPRMM16MovePPairFirst";
4700 case MCK_OCTEON_MPL: return "MCK_OCTEON_MPL";
4701 case MCK_OCTEON_P: return "MCK_OCTEON_P";
4702 case MCK_Reg28: return "MCK_Reg28";
4703 case MCK_Reg23: return "MCK_Reg23";
4704 case MCK_Reg9: return "MCK_Reg9";
4705 case MCK_Reg4: return "MCK_Reg4";
4706 case MCK_ACC64DSP: return "MCK_ACC64DSP";
4707 case MCK_HI32DSP: return "MCK_HI32DSP";
4708 case MCK_LO32DSP: return "MCK_LO32DSP";
4709 case MCK_Reg34: return "MCK_Reg34";
4710 case MCK_GPRMM16MovePPairSecond: return "MCK_GPRMM16MovePPairSecond";
4711 case MCK_Reg29: return "MCK_Reg29";
4712 case MCK_Reg27: return "MCK_Reg27";
4713 case MCK_Reg10: return "MCK_Reg10";
4714 case MCK_Reg8: return "MCK_Reg8";
4715 case MCK_Reg25: return "MCK_Reg25";
4716 case MCK_Reg22: return "MCK_Reg22";
4717 case MCK_Reg21: return "MCK_Reg21";
4718 case MCK_CPU16Regs: return "MCK_CPU16Regs";
4719 case MCK_FCC: return "MCK_FCC";
4720 case MCK_GPRMM16MoveP: return "MCK_GPRMM16MoveP";
4721 case MCK_GPRMM16Zero: return "MCK_GPRMM16Zero";
4722 case MCK_Reg26: return "MCK_Reg26";
4723 case MCK_CPU16RegsPlusSP: return "MCK_CPU16RegsPlusSP";
4724 case MCK_AFGR64: return "MCK_AFGR64";
4725 case MCK_MSA128WEvens: return "MCK_MSA128WEvens";
4726 case MCK_Reg24: return "MCK_Reg24";
4727 case MCK_GPR32NONZERO: return "MCK_GPR32NONZERO";
4728 case MCK_CCR: return "MCK_CCR";
4729 case MCK_COP0: return "MCK_COP0";
4730 case MCK_COP2: return "MCK_COP2";
4731 case MCK_COP3: return "MCK_COP3";
4732 case MCK_DSPR: return "MCK_DSPR";
4733 case MCK_FGR32: return "MCK_FGR32";
4734 case MCK_FGR64CC: return "MCK_FGR64CC";
4735 case MCK_GPR64: return "MCK_GPR64";
4736 case MCK_HWRegs: return "MCK_HWRegs";
4737 case MCK_MSA128B: return "MCK_MSA128B";
4738 case MCK_MSACtrl: return "MCK_MSACtrl";
4739 case MCK_RegByHwMode_mips_ptr_rc: return "MCK_RegByHwMode_mips_ptr_rc";
4740 case MCK_RegByHwMode_ptr_gp_rc: return "MCK_RegByHwMode_ptr_gp_rc";
4741 case MCK_RegByHwMode_ptr_gpr16mm_rc: return "MCK_RegByHwMode_ptr_gpr16mm_rc";
4742 case MCK_RegByHwMode_ptr_sp_rc: return "MCK_RegByHwMode_ptr_sp_rc";
4743 case MCK_ACC64DSPAsmReg: return "MCK_ACC64DSPAsmReg";
4744 case MCK_AFGR64AsmReg: return "MCK_AFGR64AsmReg";
4745 case MCK_CCRAsmReg: return "MCK_CCRAsmReg";
4746 case MCK_COP0AsmReg: return "MCK_COP0AsmReg";
4747 case MCK_COP2AsmReg: return "MCK_COP2AsmReg";
4748 case MCK_COP3AsmReg: return "MCK_COP3AsmReg";
4749 case MCK_ConstantImm: return "MCK_ConstantImm";
4750 case MCK_FCCAsmReg: return "MCK_FCCAsmReg";
4751 case MCK_FGR32AsmReg: return "MCK_FGR32AsmReg";
4752 case MCK_FGR64AsmReg: return "MCK_FGR64AsmReg";
4753 case MCK_GPR32AsmReg: return "MCK_GPR32AsmReg";
4754 case MCK_GPR32NonZeroAsmReg: return "MCK_GPR32NonZeroAsmReg";
4755 case MCK_GPR32ZeroAsmReg: return "MCK_GPR32ZeroAsmReg";
4756 case MCK_GPR64AsmReg: return "MCK_GPR64AsmReg";
4757 case MCK_GPRMM16AsmReg: return "MCK_GPRMM16AsmReg";
4758 case MCK_GPRMM16AsmRegMoveP: return "MCK_GPRMM16AsmRegMoveP";
4759 case MCK_GPRMM16AsmRegMovePPairFirst: return "MCK_GPRMM16AsmRegMovePPairFirst";
4760 case MCK_GPRMM16AsmRegMovePPairSecond: return "MCK_GPRMM16AsmRegMovePPairSecond";
4761 case MCK_GPRMM16AsmRegZero: return "MCK_GPRMM16AsmRegZero";
4762 case MCK_HI32DSPAsmReg: return "MCK_HI32DSPAsmReg";
4763 case MCK_HWRegsAsmReg: return "MCK_HWRegsAsmReg";
4764 case MCK_Imm: return "MCK_Imm";
4765 case MCK_LO32DSPAsmReg: return "MCK_LO32DSPAsmReg";
4766 case MCK_MSA128AsmReg: return "MCK_MSA128AsmReg";
4767 case MCK_MSACtrlAsmReg: return "MCK_MSACtrlAsmReg";
4768 case MCK_MicroMipsMemGP: return "MCK_MicroMipsMemGP";
4769 case MCK_MicroMipsMem: return "MCK_MicroMipsMem";
4770 case MCK_MicroMipsMemSP: return "MCK_MicroMipsMemSP";
4771 case MCK_InvNum: return "MCK_InvNum";
4772 case MCK_JumpTarget: return "MCK_JumpTarget";
4773 case MCK_MemOffsetSimmPtr: return "MCK_MemOffsetSimmPtr";
4774 case MCK_MemOffsetUimm4: return "MCK_MemOffsetUimm4";
4775 case MCK_MemOffsetSimm9_0: return "MCK_MemOffsetSimm9_0";
4776 case MCK_MemOffsetSimm10_0: return "MCK_MemOffsetSimm10_0";
4777 case MCK_MemOffsetSimm11_0: return "MCK_MemOffsetSimm11_0";
4778 case MCK_MemOffsetSimm12_0: return "MCK_MemOffsetSimm12_0";
4779 case MCK_MemOffsetSimm16_0: return "MCK_MemOffsetSimm16_0";
4780 case MCK_MemOffsetSimm10_1: return "MCK_MemOffsetSimm10_1";
4781 case MCK_MemOffsetSimm10_2: return "MCK_MemOffsetSimm10_2";
4782 case MCK_MemOffsetSimm10_3: return "MCK_MemOffsetSimm10_3";
4783 case MCK_Mem: return "MCK_Mem";
4784 case MCK_RegList16: return "MCK_RegList16";
4785 case MCK_RegList: return "MCK_RegList";
4786 case MCK_Simm18_Lsl3: return "MCK_Simm18_Lsl3";
4787 case MCK_Simm19_Lsl2: return "MCK_Simm19_Lsl2";
4788 case MCK_StrictlyAFGR64AsmReg: return "MCK_StrictlyAFGR64AsmReg";
4789 case MCK_StrictlyFGR32AsmReg: return "MCK_StrictlyFGR32AsmReg";
4790 case MCK_StrictlyFGR64AsmReg: return "MCK_StrictlyFGR64AsmReg";
4791 case MCK_ConstantImmz: return "MCK_ConstantImmz";
4792 case MCK_ConstantUImm1_0: return "MCK_ConstantUImm1_0";
4793 case MCK_ConstantUImm2_0: return "MCK_ConstantUImm2_0";
4794 case MCK_ConstantUImm2_1: return "MCK_ConstantUImm2_1";
4795 case MCK_ConstantUImm3_0: return "MCK_ConstantUImm3_0";
4796 case MCK_ConstantSImm4_0: return "MCK_ConstantSImm4_0";
4797 case MCK_ConstantUImm4_0: return "MCK_ConstantUImm4_0";
4798 case MCK_ConstantSImm5_0: return "MCK_ConstantSImm5_0";
4799 case MCK_ConstantUImm5_0: return "MCK_ConstantUImm5_0";
4800 case MCK_ConstantUImm5_1: return "MCK_ConstantUImm5_1";
4801 case MCK_ConstantUImm5_Plus1_Report_UImm6: return "MCK_ConstantUImm5_Plus1_Report_UImm6";
4802 case MCK_ConstantUImm5_32_Norm: return "MCK_ConstantUImm5_32_Norm";
4803 case MCK_ConstantUImm5_32: return "MCK_ConstantUImm5_32";
4804 case MCK_ConstantUImm5_0_Report_UImm6: return "MCK_ConstantUImm5_0_Report_UImm6";
4805 case MCK_ConstantUImm5_33: return "MCK_ConstantUImm5_33";
4806 case MCK_ConstantUImmRange2_64: return "MCK_ConstantUImmRange2_64";
4807 case MCK_UImm5Lsl2: return "MCK_UImm5Lsl2";
4808 case MCK_ConstantSImm6_0: return "MCK_ConstantSImm6_0";
4809 case MCK_ConstantUImm6_0: return "MCK_ConstantUImm6_0";
4810 case MCK_UImm6Lsl2: return "MCK_UImm6Lsl2";
4811 case MCK_ConstantUImm7_0: return "MCK_ConstantUImm7_0";
4812 case MCK_UImm7_N1: return "MCK_UImm7_N1";
4813 case MCK_ConstantUImm8_0: return "MCK_ConstantUImm8_0";
4814 case MCK_SImm7Lsl2: return "MCK_SImm7Lsl2";
4815 case MCK_ConstantSImm9_0: return "MCK_ConstantSImm9_0";
4816 case MCK_ConstantSImm10_0: return "MCK_ConstantSImm10_0";
4817 case MCK_ConstantUImm10_0: return "MCK_ConstantUImm10_0";
4818 case MCK_SImm10Lsl1: return "MCK_SImm10Lsl1";
4819 case MCK_ConstantSImm11_0: return "MCK_ConstantSImm11_0";
4820 case MCK_SImm10Lsl2: return "MCK_SImm10Lsl2";
4821 case MCK_SImm10Lsl3: return "MCK_SImm10Lsl3";
4822 case MCK_SImm16: return "MCK_SImm16";
4823 case MCK_SImm16_Relaxed: return "MCK_SImm16_Relaxed";
4824 case MCK_UImm16_AltRelaxed: return "MCK_UImm16_AltRelaxed";
4825 case MCK_UImm16: return "MCK_UImm16";
4826 case MCK_SImm19Lsl2: return "MCK_SImm19Lsl2";
4827 case MCK_UImm16_Relaxed: return "MCK_UImm16_Relaxed";
4828 case MCK_ConstantUImm20_0: return "MCK_ConstantUImm20_0";
4829 case MCK_ConstantUImm26_0: return "MCK_ConstantUImm26_0";
4830 case MCK_SImm32: return "MCK_SImm32";
4831 case MCK_SImm32_Relaxed: return "MCK_SImm32_Relaxed";
4832 case MCK_UImm32_Coerced: return "MCK_UImm32_Coerced";
4833 case NumMatchClassKinds: return "NumMatchClassKinds";
4834 }
4835 llvm_unreachable("unhandled MatchClassKind!");
4836}
4837
4838#endif // NDEBUG
4839FeatureBitset MipsAsmParser::
4840ComputeAvailableFeatures(const FeatureBitset &FB) const {
4841 FeatureBitset Features;
4842 if (FB[Mips::FeaturePTR64Bit])
4843 Features.set(Feature_IsPTR64bitBit);
4844 if (!(FB[Mips::FeaturePTR64Bit]))
4845 Features.set(Feature_IsPTR32bitBit);
4846 if (FB[Mips::FeatureUseCompactBranches])
4847 Features.set(Feature_UseCompactBranchesBit);
4848 if (FB[Mips::FeatureMips2])
4849 Features.set(Feature_HasMips2Bit);
4850 if (FB[Mips::FeatureMips3_32])
4851 Features.set(Feature_HasMips3_32Bit);
4852 if (FB[Mips::FeatureMips3_32r2])
4853 Features.set(Feature_HasMips3_32r2Bit);
4854 if (FB[Mips::FeatureMips3])
4855 Features.set(Feature_HasMips3Bit);
4856 if (!(FB[Mips::FeatureMips3]))
4857 Features.set(Feature_NotMips3Bit);
4858 if (FB[Mips::FeatureMips4_32])
4859 Features.set(Feature_HasMips4_32Bit);
4860 if (!(FB[Mips::FeatureMips4_32]))
4861 Features.set(Feature_NotMips4_32Bit);
4862 if (FB[Mips::FeatureMips4_32r2])
4863 Features.set(Feature_HasMips4_32r2Bit);
4864 if (FB[Mips::FeatureMips5_32r2])
4865 Features.set(Feature_HasMips5_32r2Bit);
4866 if (FB[Mips::FeatureMips32])
4867 Features.set(Feature_HasMips32Bit);
4868 if (FB[Mips::FeatureMips32r2])
4869 Features.set(Feature_HasMips32r2Bit);
4870 if (FB[Mips::FeatureMips32r5])
4871 Features.set(Feature_HasMips32r5Bit);
4872 if (FB[Mips::FeatureMips32r6])
4873 Features.set(Feature_HasMips32r6Bit);
4874 if (!(FB[Mips::FeatureMips32r6]))
4875 Features.set(Feature_NotMips32r6Bit);
4876 if (FB[Mips::FeatureGP64Bit])
4877 Features.set(Feature_IsGP64bitBit);
4878 if (!(FB[Mips::FeatureGP64Bit]))
4879 Features.set(Feature_IsGP32bitBit);
4880 if (FB[Mips::FeatureMips64])
4881 Features.set(Feature_HasMips64Bit);
4882 if (!(FB[Mips::FeatureMips64]))
4883 Features.set(Feature_NotMips64Bit);
4884 if (FB[Mips::FeatureMips64r2])
4885 Features.set(Feature_HasMips64r2Bit);
4886 if (FB[Mips::FeatureMips64r5])
4887 Features.set(Feature_HasMips64r5Bit);
4888 if (FB[Mips::FeatureMips64r6])
4889 Features.set(Feature_HasMips64r6Bit);
4890 if (!(FB[Mips::FeatureMips64r6]))
4891 Features.set(Feature_NotMips64r6Bit);
4892 if (FB[Mips::FeatureMips16])
4893 Features.set(Feature_InMips16ModeBit);
4894 if (!(FB[Mips::FeatureMips16]))
4895 Features.set(Feature_NotInMips16ModeBit);
4896 if (FB[Mips::FeatureCnMips])
4897 Features.set(Feature_HasCnMipsBit);
4898 if (!(FB[Mips::FeatureCnMips]))
4899 Features.set(Feature_NotCnMipsBit);
4900 if (FB[Mips::FeatureCnMipsP])
4901 Features.set(Feature_HasCnMipsPBit);
4902 if (!(FB[Mips::FeatureCnMipsP]))
4903 Features.set(Feature_NotCnMipsPBit);
4904 if (FB[Mips::FeatureSym32])
4905 Features.set(Feature_IsSym32Bit);
4906 if (!(FB[Mips::FeatureSym32]))
4907 Features.set(Feature_IsSym64Bit);
4908 if (!(FB[Mips::FeatureMips16]))
4909 Features.set(Feature_HasStdEncBit);
4910 if (FB[Mips::FeatureMicroMips])
4911 Features.set(Feature_InMicroMipsBit);
4912 if (!(FB[Mips::FeatureMicroMips]))
4913 Features.set(Feature_NotInMicroMipsBit);
4914 if (FB[Mips::FeatureEVA])
4915 Features.set(Feature_HasEVABit);
4916 if (FB[Mips::FeatureMSA])
4917 Features.set(Feature_HasMSABit);
4918 if (!(FB[Mips::FeatureNoMadd4]))
4919 Features.set(Feature_HasMadd4Bit);
4920 if (FB[Mips::FeatureMT])
4921 Features.set(Feature_HasMTBit);
4922 if (FB[Mips::FeatureUseIndirectJumpsHazard])
4923 Features.set(Feature_UseIndirectJumpsHazardBit);
4924 if (!(FB[Mips::FeatureUseIndirectJumpsHazard]))
4925 Features.set(Feature_NoIndirectJumpGuardsBit);
4926 if (FB[Mips::FeatureR5900])
4927 Features.set(Feature_IsR5900Bit);
4928 if (!(FB[Mips::FeatureR5900]))
4929 Features.set(Feature_NotR5900Bit);
4930 if (FB[Mips::FeatureCRC])
4931 Features.set(Feature_HasCRCBit);
4932 if (FB[Mips::FeatureVirt])
4933 Features.set(Feature_HasVirtBit);
4934 if (FB[Mips::FeatureGINV])
4935 Features.set(Feature_HasGINVBit);
4936 if (FB[Mips::FeatureFP64Bit])
4937 Features.set(Feature_IsFP64bitBit);
4938 if (!(FB[Mips::FeatureFP64Bit]))
4939 Features.set(Feature_NotFP64bitBit);
4940 if (FB[Mips::FeatureSingleFloat])
4941 Features.set(Feature_IsSingleFloatBit);
4942 if (!(FB[Mips::FeatureSingleFloat]))
4943 Features.set(Feature_IsNotSingleFloatBit);
4944 if (!(FB[Mips::FeatureSoftFloat]))
4945 Features.set(Feature_IsNotSoftFloatBit);
4946 if (FB[Mips::FeatureMips3D])
4947 Features.set(Feature_HasMips3DBit);
4948 if (FB[Mips::FeatureDSP])
4949 Features.set(Feature_HasDSPBit);
4950 if (FB[Mips::FeatureDSPR2])
4951 Features.set(Feature_HasDSPR2Bit);
4952 if (FB[Mips::FeatureDSPR3])
4953 Features.set(Feature_HasDSPR3Bit);
4954 return Features;
4955}
4956
4957static bool checkAsmTiedOperandConstraints(const MipsAsmParser&AsmParser,
4958 unsigned Kind, const OperandVector &Operands,
4959 uint64_t &ErrorInfo) {
4960 assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!");
4961 const uint8_t *Converter = ConversionTable[Kind];
4962 for (const uint8_t *p = Converter; *p; p += 2) {
4963 switch (*p) {
4964 case CVT_Tied: {
4965 unsigned OpIdx = *(p + 1);
4966 assert(OpIdx < (size_t)(std::end(TiedAsmOperandTable) -
4967 std::begin(TiedAsmOperandTable)) &&
4968 "Tied operand not found");
4969 unsigned OpndNum1 = TiedAsmOperandTable[OpIdx][1];
4970 unsigned OpndNum2 = TiedAsmOperandTable[OpIdx][2];
4971 if (OpndNum1 != OpndNum2) {
4972 auto &SrcOp1 = Operands[OpndNum1];
4973 auto &SrcOp2 = Operands[OpndNum2];
4974 if (!AsmParser.areEqualRegs(*SrcOp1, *SrcOp2)) {
4975 ErrorInfo = OpndNum2;
4976 return false;
4977 }
4978 }
4979 break;
4980 }
4981 default:
4982 break;
4983 }
4984 }
4985 return true;
4986}
4987
4988static const char MnemonicTable[] =
4989 "\003abs\005abs.d\005abs.s\tabsq_s.ph\tabsq_s.qb\010absq_s.w\003add\005a"
4990 "dd.d\006add.ps\005add.s\007add_a.b\007add_a.d\007add_a.h\007add_a.w\004"
4991 "addi\005addiu\007addiupc\taddiur1sp\007addiur2\007addius5\007addiusp\007"
4992 "addq.ph\taddq_s.ph\010addq_s.w\010addqh.ph\007addqh.w\naddqh_r.ph\taddq"
4993 "h_r.w\007addr.ps\010adds_a.b\010adds_a.d\010adds_a.h\010adds_a.w\010add"
4994 "s_s.b\010adds_s.d\010adds_s.h\010adds_s.w\010adds_u.b\010adds_u.d\010ad"
4995 "ds_u.h\010adds_u.w\005addsc\004addu\007addu.ph\007addu.qb\006addu16\tad"
4996 "du_s.ph\taddu_s.qb\010adduh.qb\nadduh_r.qb\006addv.b\006addv.d\006addv."
4997 "h\006addv.w\007addvi.b\007addvi.d\007addvi.h\007addvi.w\005addwc\005ali"
4998 "gn\006aluipc\003and\005and.v\005and16\004andi\006andi.b\006andi16\006ap"
4999 "pend\010asub_s.b\010asub_s.d\010asub_s.h\010asub_s.w\010asub_u.b\010asu"
5000 "b_u.d\010asub_u.h\010asub_u.w\003aui\005auipc\007ave_s.b\007ave_s.d\007"
5001 "ave_s.h\007ave_s.w\007ave_u.b\007ave_u.d\007ave_u.h\007ave_u.w\010aver_"
5002 "s.b\010aver_s.d\010aver_s.h\010aver_s.w\010aver_u.b\010aver_u.d\010aver"
5003 "_u.h\010aver_u.w\001b\003b16\005baddu\003bal\004balc\006balign\005bbit0"
5004 "\007bbit032\005bbit1\007bbit132\002bc\004bc16\006bc1eqz\007bc1eqzc\004b"
5005 "c1f\005bc1fl\006bc1nez\007bc1nezc\004bc1t\005bc1tl\006bc2eqz\007bc2eqzc"
5006 "\006bc2nez\007bc2nezc\006bclr.b\006bclr.d\006bclr.h\006bclr.w\007bclri."
5007 "b\007bclri.d\007bclri.h\007bclri.w\003beq\004beqc\004beql\004beqz\006be"
5008 "qz16\007beqzalc\005beqzc\007beqzc16\005beqzl\003bge\004bgec\004bgel\004"
5009 "bgeu\005bgeuc\005bgeul\004bgez\006bgezal\007bgezalc\007bgezall\007bgeza"
5010 "ls\005bgezc\005bgezl\003bgt\004bgtl\004bgtu\005bgtul\004bgtz\007bgtzalc"
5011 "\005bgtzc\005bgtzl\007binsl.b\007binsl.d\007binsl.h\007binsl.w\010binsl"
5012 "i.b\010binsli.d\010binsli.h\010binsli.w\007binsr.b\007binsr.d\007binsr."
5013 "h\007binsr.w\010binsri.b\010binsri.d\010binsri.h\010binsri.w\006bitrev\007"
5014 "bitswap\003ble\004blel\004bleu\005bleul\004blez\007blezalc\005blezc\005"
5015 "blezl\003blt\004bltc\004bltl\004bltu\005bltuc\005bltul\004bltz\006bltza"
5016 "l\007bltzalc\007bltzall\007bltzals\005bltzc\005bltzl\006bmnz.v\007bmnzi"
5017 ".b\005bmz.v\006bmzi.b\003bne\004bnec\006bneg.b\006bneg.d\006bneg.h\006b"
5018 "neg.w\007bnegi.b\007bnegi.d\007bnegi.h\007bnegi.w\004bnel\004bnez\006bn"
5019 "ez16\007bnezalc\005bnezc\007bnezc16\005bnezl\004bnvc\005bnz.b\005bnz.d\005"
5020 "bnz.h\005bnz.v\005bnz.w\004bovc\010bposge32\tbposge32c\005break\007brea"
5021 "k16\006bsel.v\007bseli.b\006bset.b\006bset.d\006bset.h\006bset.w\007bse"
5022 "ti.b\007bseti.d\007bseti.h\007bseti.w\005bteqz\005btnez\004bz.b\004bz.d"
5023 "\004bz.h\004bz.v\004bz.w\006c.eq.d\006c.eq.s\005c.f.d\005c.f.s\006c.le."
5024 "d\006c.le.s\006c.lt.d\006c.lt.s\007c.nge.d\007c.nge.s\007c.ngl.d\007c.n"
5025 "gl.s\010c.ngle.d\010c.ngle.s\007c.ngt.d\007c.ngt.s\007c.ole.d\007c.ole."
5026 "s\007c.olt.d\007c.olt.s\007c.seq.d\007c.seq.s\006c.sf.d\006c.sf.s\007c."
5027 "ueq.d\007c.ueq.s\007c.ule.d\007c.ule.s\007c.ult.d\007c.ult.s\006c.un.d\006"
5028 "c.un.s\005cache\006cachee\010ceil.l.d\010ceil.l.s\010ceil.w.d\010ceil.w"
5029 ".s\005ceq.b\005ceq.d\005ceq.h\005ceq.w\006ceqi.b\006ceqi.d\006ceqi.h\006"
5030 "ceqi.w\004cfc1\004cfc2\006cfcmsa\005cftc1\004cins\006cins32\007class.d\007"
5031 "class.s\007cle_s.b\007cle_s.d\007cle_s.h\007cle_s.w\007cle_u.b\007cle_u"
5032 ".d\007cle_u.h\007cle_u.w\010clei_s.b\010clei_s.d\010clei_s.h\010clei_s."
5033 "w\010clei_u.b\010clei_u.d\010clei_u.h\010clei_u.w\003clo\007clt_s.b\007"
5034 "clt_s.d\007clt_s.h\007clt_s.w\007clt_u.b\007clt_u.d\007clt_u.h\007clt_u"
5035 ".w\010clti_s.b\010clti_s.d\010clti_s.h\010clti_s.w\010clti_u.b\010clti_"
5036 "u.d\010clti_u.h\010clti_u.w\003clz\003cmp\010cmp.af.d\010cmp.af.s\010cm"
5037 "p.eq.d\tcmp.eq.ph\010cmp.eq.s\010cmp.le.d\tcmp.le.ph\010cmp.le.s\010cmp"
5038 ".lt.d\tcmp.lt.ph\010cmp.lt.s\tcmp.saf.d\tcmp.saf.s\tcmp.seq.d\tcmp.seq."
5039 "s\tcmp.sle.d\tcmp.sle.s\tcmp.slt.d\tcmp.slt.s\ncmp.sueq.d\ncmp.sueq.s\n"
5040 "cmp.sule.d\ncmp.sule.s\ncmp.sult.d\ncmp.sult.s\tcmp.sun.d\tcmp.sun.s\tc"
5041 "mp.ueq.d\tcmp.ueq.s\tcmp.ule.d\tcmp.ule.s\tcmp.ult.d\tcmp.ult.s\010cmp."
5042 "un.d\010cmp.un.s\014cmpgdu.eq.qb\014cmpgdu.le.qb\014cmpgdu.lt.qb\013cmp"
5043 "gu.eq.qb\013cmpgu.le.qb\013cmpgu.lt.qb\004cmpi\ncmpu.eq.qb\ncmpu.le.qb\n"
5044 "cmpu.lt.qb\010copy_s.b\010copy_s.d\010copy_s.h\010copy_s.w\010copy_u.b\010"
5045 "copy_u.h\010copy_u.w\006crc32b\007crc32cb\007crc32cd\007crc32ch\007crc3"
5046 "2cw\006crc32d\006crc32h\006crc32w\004ctc1\004ctc2\006ctcmsa\005cttc1\007"
5047 "cvt.d.l\007cvt.d.s\007cvt.d.w\007cvt.l.d\007cvt.l.s\tcvt.ps.pw\010cvt.p"
5048 "s.s\tcvt.pw.ps\007cvt.s.d\007cvt.s.l\010cvt.s.pl\010cvt.s.pu\007cvt.s.w"
5049 "\007cvt.w.d\007cvt.w.s\004dadd\005daddi\006daddiu\005daddu\004dahi\006d"
5050 "align\004dati\004daui\010dbitswap\004dclo\004dclz\004ddiv\005ddivu\005d"
5051 "eret\004dext\005dextm\005dextu\002di\004dins\005dinsm\005dinsu\003div\005"
5052 "div.d\005div.s\007div_s.b\007div_s.d\007div_s.h\007div_s.w\007div_u.b\007"
5053 "div_u.d\007div_u.h\007div_u.w\004divu\003dla\003dli\004dlsa\005dmfc0\005"
5054 "dmfc1\005dmfc2\006dmfgc0\004dmod\005dmodu\003dmt\005dmtc0\005dmtc1\005d"
5055 "mtc2\006dmtgc0\004dmuh\005dmuhu\004dmul\005dmulo\006dmulou\005dmult\006"
5056 "dmultu\005dmulu\004dneg\005dnegu\010dotp_s.d\010dotp_s.h\010dotp_s.w\010"
5057 "dotp_u.d\010dotp_u.h\010dotp_u.w\010dpa.w.ph\tdpadd_s.d\tdpadd_s.h\tdpa"
5058 "dd_s.w\tdpadd_u.d\tdpadd_u.h\tdpadd_u.w\013dpaq_s.w.ph\013dpaq_sa.l.w\014"
5059 "dpaqx_s.w.ph\015dpaqx_sa.w.ph\ndpau.h.qbl\ndpau.h.qbr\tdpax.w.ph\004dpo"
5060 "p\010dps.w.ph\013dpsq_s.w.ph\013dpsq_sa.l.w\014dpsqx_s.w.ph\015dpsqx_sa"
5061 ".w.ph\ndpsu.h.qbl\ndpsu.h.qbr\tdpsub_s.d\tdpsub_s.h\tdpsub_s.w\tdpsub_u"
5062 ".d\tdpsub_u.h\tdpsub_u.w\tdpsx.w.ph\004drem\005dremu\004drol\004dror\005"
5063 "drotr\007drotr32\006drotrv\004dsbh\004dshd\004dsll\006dsll32\005dsllv\004"
5064 "dsra\006dsra32\005dsrav\004dsrl\006dsrl32\005dsrlv\004dsub\005dsubi\005"
5065 "dsubu\003dvp\004dvpe\003ehb\002ei\003emt\004eret\006eretnc\003evp\004ev"
5066 "pe\003ext\004extp\006extpdp\007extpdpv\005extpv\006extr.w\010extr_r.w\t"
5067 "extr_rs.w\010extr_s.h\007extrv.w\textrv_r.w\nextrv_rs.w\textrv_s.h\004e"
5068 "xts\006exts32\006fadd.d\006fadd.w\006fcaf.d\006fcaf.w\006fceq.d\006fceq"
5069 ".w\010fclass.d\010fclass.w\006fcle.d\006fcle.w\006fclt.d\006fclt.w\006f"
5070 "cne.d\006fcne.w\006fcor.d\006fcor.w\007fcueq.d\007fcueq.w\007fcule.d\007"
5071 "fcule.w\007fcult.d\007fcult.w\006fcun.d\006fcun.w\007fcune.d\007fcune.w"
5072 "\006fdiv.d\006fdiv.w\007fexdo.h\007fexdo.w\007fexp2.d\007fexp2.w\010fex"
5073 "upl.d\010fexupl.w\010fexupr.d\010fexupr.w\tffint_s.d\tffint_s.w\tffint_"
5074 "u.d\tffint_u.w\006ffql.d\006ffql.w\006ffqr.d\006ffqr.w\006fill.b\006fil"
5075 "l.d\006fill.h\006fill.w\007flog2.d\007flog2.w\tfloor.l.d\tfloor.l.s\tfl"
5076 "oor.w.d\tfloor.w.s\007fmadd.d\007fmadd.w\006fmax.d\006fmax.w\010fmax_a."
5077 "d\010fmax_a.w\006fmin.d\006fmin.w\010fmin_a.d\010fmin_a.w\007fmsub.d\007"
5078 "fmsub.w\006fmul.d\006fmul.w\004fork\006frcp.d\006frcp.w\007frint.d\007f"
5079 "rint.w\010frsqrt.d\010frsqrt.w\006fsaf.d\006fsaf.w\006fseq.d\006fseq.w\006"
5080 "fsle.d\006fsle.w\006fslt.d\006fslt.w\006fsne.d\006fsne.w\006fsor.d\006f"
5081 "sor.w\007fsqrt.d\007fsqrt.w\006fsub.d\006fsub.w\007fsueq.d\007fsueq.w\007"
5082 "fsule.d\007fsule.w\007fsult.d\007fsult.w\006fsun.d\006fsun.w\007fsune.d"
5083 "\007fsune.w\tftint_s.d\tftint_s.w\tftint_u.d\tftint_u.w\005ftq.h\005ftq"
5084 ".w\nftrunc_s.d\nftrunc_s.w\nftrunc_u.d\nftrunc_u.w\005ginvi\005ginvt\010"
5085 "hadd_s.d\010hadd_s.h\010hadd_s.w\010hadd_u.d\010hadd_u.h\010hadd_u.w\010"
5086 "hsub_s.d\010hsub_s.h\010hsub_s.w\010hsub_u.d\010hsub_u.h\010hsub_u.w\007"
5087 "hypcall\007ilvev.b\007ilvev.d\007ilvev.h\007ilvev.w\006ilvl.b\006ilvl.d"
5088 "\006ilvl.h\006ilvl.w\007ilvod.b\007ilvod.d\007ilvod.h\007ilvod.w\006ilv"
5089 "r.b\006ilvr.d\006ilvr.h\006ilvr.w\003ins\010insert.b\010insert.d\010ins"
5090 "ert.h\010insert.w\004insv\007insve.b\007insve.d\007insve.h\007insve.w\001"
5091 "j\003jal\004jalr\007jalr.hb\005jalrc\010jalrc.hb\005jalrs\007jalrs16\004"
5092 "jals\004jalx\005jialc\003jic\002jr\005jr.hb\004jr16\tjraddiusp\003jrc\005"
5093 "jrc16\njrcaddiusp\003l.d\003l.s\002la\004lapc\002lb\003lbe\003lbu\005lb"
5094 "u16\004lbue\004lbux\002ld\004ld.b\004ld.d\004ld.h\004ld.w\004ldc1\004ld"
5095 "c2\004ldc3\005ldi.b\005ldi.d\005ldi.h\005ldi.w\003ldl\004ldpc\003ldr\005"
5096 "ldxc1\002lh\003lhe\003lhu\005lhu16\004lhue\003lhx\002li\004li.d\004li.s"
5097 "\004li16\002ll\003lld\003lle\003lsa\003lui\005luxc1\002lw\004lw16\004lw"
5098 "c1\004lwc2\004lwc3\003lwe\003lwl\004lwle\003lwm\005lwm16\005lwm32\003lw"
5099 "p\004lwpc\003lwr\004lwre\003lwu\005lwupc\003lwx\005lwxc1\004lwxs\004mad"
5100 "d\006madd.d\006madd.s\010madd_q.h\010madd_q.w\007maddf.d\007maddf.s\tma"
5101 "ddr_q.h\tmaddr_q.w\005maddu\007maddv.b\007maddv.d\007maddv.h\007maddv.w"
5102 "\013maq_s.w.phl\013maq_s.w.phr\014maq_sa.w.phl\014maq_sa.w.phr\005max.d"
5103 "\005max.s\007max_a.b\007max_a.d\007max_a.h\007max_a.w\007max_s.b\007max"
5104 "_s.d\007max_s.h\007max_s.w\007max_u.b\007max_u.d\007max_u.h\007max_u.w\006"
5105 "maxa.d\006maxa.s\010maxi_s.b\010maxi_s.d\010maxi_s.h\010maxi_s.w\010max"
5106 "i_u.b\010maxi_u.d\010maxi_u.h\010maxi_u.w\004mfc0\004mfc1\004mfc2\005mf"
5107 "gc0\005mfhc0\005mfhc1\005mfhc2\006mfhgc0\004mfhi\006mfhi16\004mflo\006m"
5108 "flo16\006mftacx\005mftc0\005mftc1\006mftdsp\006mftgpr\006mfthc1\005mfth"
5109 "i\005mftlo\004mftr\005min.d\005min.s\007min_a.b\007min_a.d\007min_a.h\007"
5110 "min_a.w\007min_s.b\007min_s.d\007min_s.h\007min_s.w\007min_u.b\007min_u"
5111 ".d\007min_u.h\007min_u.w\006mina.d\006mina.s\010mini_s.b\010mini_s.d\010"
5112 "mini_s.h\010mini_s.w\010mini_u.b\010mini_u.d\010mini_u.h\010mini_u.w\003"
5113 "mod\007mod_s.b\007mod_s.d\007mod_s.h\007mod_s.w\007mod_u.b\007mod_u.d\007"
5114 "mod_u.h\007mod_u.w\006modsub\004modu\005mov.d\005mov.s\004move\006move."
5115 "v\006move16\005movep\004movf\006movf.d\006movf.s\004movn\006movn.d\006m"
5116 "ovn.s\004movt\006movt.d\006movt.s\004movz\006movz.d\006movz.s\004msub\006"
5117 "msub.d\006msub.s\010msub_q.h\010msub_q.w\007msubf.d\007msubf.s\tmsubr_q"
5118 ".h\tmsubr_q.w\005msubu\007msubv.b\007msubv.d\007msubv.h\007msubv.w\004m"
5119 "tc0\004mtc1\004mtc2\005mtgc0\005mthc0\005mthc1\005mthc2\006mthgc0\004mt"
5120 "hi\006mthlip\004mtlo\004mtm0\004mtm1\004mtm2\004mtp0\004mtp1\004mtp2\006"
5121 "mttacx\005mttc0\005mttc1\006mttdsp\006mttgpr\006mtthc1\005mtthi\005mttl"
5122 "o\004mttr\003muh\004muhu\003mul\005mul.d\006mul.ph\006mul.ps\005mul.s\007"
5123 "mul_q.h\007mul_q.w\010mul_s.ph\015muleq_s.w.phl\015muleq_s.w.phr\016mul"
5124 "eu_s.ph.qbl\016muleu_s.ph.qbr\004mulo\005mulou\nmulq_rs.ph\tmulq_rs.w\t"
5125 "mulq_s.ph\010mulq_s.w\007mulr.ps\010mulr_q.h\010mulr_q.w\nmulsa.w.ph\015"
5126 "mulsaq_s.w.ph\004mult\005multu\004mulu\006mulv.b\006mulv.d\006mulv.h\006"
5127 "mulv.w\003nal\003neg\005neg.d\005neg.s\004negu\006nloc.b\006nloc.d\006n"
5128 "loc.h\006nloc.w\006nlzc.b\006nlzc.d\006nlzc.h\006nlzc.w\007nmadd.d\007n"
5129 "madd.s\007nmsub.d\007nmsub.s\003nop\003nor\005nor.v\006nori.b\003not\005"
5130 "not16\002or\004or.v\004or16\003ori\005ori.b\tpackrl.ph\005pause\007pcke"
5131 "v.b\007pckev.d\007pckev.h\007pckev.w\007pckod.b\007pckod.d\007pckod.h\007"
5132 "pckod.w\006pcnt.b\006pcnt.d\006pcnt.h\006pcnt.w\007pick.ph\007pick.qb\006"
5133 "pll.ps\006plu.ps\003pop\014preceq.w.phl\014preceq.w.phr\016precequ.ph.q"
5134 "bl\017precequ.ph.qbla\016precequ.ph.qbr\017precequ.ph.qbra\015preceu.ph"
5135 ".qbl\016preceu.ph.qbla\015preceu.ph.qbr\016preceu.ph.qbra\013precr.qb.p"
5136 "h\016precr_sra.ph.w\020precr_sra_r.ph.w\013precrq.ph.w\014precrq.qb.ph\016"
5137 "precrq_rs.ph.w\017precrqu_s.qb.ph\004pref\005prefe\005prefx\007prepend\006"
5138 "pul.ps\006puu.ps\nraddu.w.qb\005rddsp\005rdhwr\006rdpgpr\007recip.d\007"
5139 "recip.s\003rem\004remu\007repl.ph\007repl.qb\010replv.ph\010replv.qb\006"
5140 "rint.d\006rint.s\003rol\003ror\004rotr\005rotrv\tround.l.d\tround.l.s\t"
5141 "round.w.d\tround.w.s\007rsqrt.d\007rsqrt.s\003s.d\003s.s\003saa\004saad"
5142 "\007sat_s.b\007sat_s.d\007sat_s.h\007sat_s.w\007sat_u.b\007sat_u.d\007s"
5143 "at_u.h\007sat_u.w\002sb\004sb16\003sbe\002sc\003scd\003sce\002sd\005sdb"
5144 "bp\007sdbbp16\004sdc1\004sdc2\004sdc3\003sdl\003sdr\005sdxc1\003seb\003"
5145 "seh\005sel.d\005sel.s\006seleqz\010seleqz.d\010seleqz.s\006selnez\010se"
5146 "lnez.d\010selnez.s\003seq\004seqi\003sge\004sgeu\003sgt\004sgtu\002sh\004"
5147 "sh16\003she\005shf.b\005shf.h\005shf.w\005shilo\006shilov\007shll.ph\007"
5148 "shll.qb\tshll_s.ph\010shll_s.w\010shllv.ph\010shllv.qb\nshllv_s.ph\tshl"
5149 "lv_s.w\007shra.ph\007shra.qb\tshra_r.ph\tshra_r.qb\010shra_r.w\010shrav"
5150 ".ph\010shrav.qb\nshrav_r.ph\nshrav_r.qb\tshrav_r.w\007shrl.ph\007shrl.q"
5151 "b\010shrlv.ph\010shrlv.qb\006sigrie\005sld.b\005sld.d\005sld.h\005sld.w"
5152 "\006sldi.b\006sldi.d\006sldi.h\006sldi.w\003sle\004sleu\003sll\005sll.b"
5153 "\005sll.d\005sll.h\005sll.w\005sll16\006slli.b\006slli.d\006slli.h\006s"
5154 "lli.w\004sllv\003slt\004slti\005sltiu\004sltu\003sne\004snei\007splat.b"
5155 "\007splat.d\007splat.h\007splat.w\010splati.b\010splati.d\010splati.h\010"
5156 "splati.w\006sqrt.d\006sqrt.s\003sra\005sra.b\005sra.d\005sra.h\005sra.w"
5157 "\006srai.b\006srai.d\006srai.h\006srai.w\006srar.b\006srar.d\006srar.h\006"
5158 "srar.w\007srari.b\007srari.d\007srari.h\007srari.w\004srav\003srl\005sr"
5159 "l.b\005srl.d\005srl.h\005srl.w\005srl16\006srli.b\006srli.d\006srli.h\006"
5160 "srli.w\006srlr.b\006srlr.d\006srlr.h\006srlr.w\007srlri.b\007srlri.d\007"
5161 "srlri.h\007srlri.w\004srlv\005ssnop\004st.b\004st.d\004st.h\004st.w\003"
5162 "sub\005sub.d\006sub.ps\005sub.s\007subq.ph\tsubq_s.ph\010subq_s.w\010su"
5163 "bqh.ph\007subqh.w\nsubqh_r.ph\tsubqh_r.w\010subs_s.b\010subs_s.d\010sub"
5164 "s_s.h\010subs_s.w\010subs_u.b\010subs_u.d\010subs_u.h\010subs_u.w\nsubs"
5165 "us_u.b\nsubsus_u.d\nsubsus_u.h\nsubsus_u.w\nsubsuu_s.b\nsubsuu_s.d\nsub"
5166 "suu_s.h\nsubsuu_s.w\004subu\007subu.ph\007subu.qb\006subu16\tsubu_s.ph\t"
5167 "subu_s.qb\010subuh.qb\nsubuh_r.qb\006subv.b\006subv.d\006subv.h\006subv"
5168 ".w\007subvi.b\007subvi.d\007subvi.h\007subvi.w\005suxc1\002sw\004sw16\004"
5169 "swc1\004swc2\004swc3\003swe\003swl\004swle\003swm\005swm16\005swm32\003"
5170 "swp\003swr\004swre\004swsp\005swxc1\004sync\014sync_acquire\007sync_mb\014"
5171 "sync_release\010sync_rmb\010sync_wmb\005synci\nsynciobdma\005syncs\005s"
5172 "yncw\006syncws\007syscall\003teq\004teqi\003tge\004tgei\005tgeiu\004tge"
5173 "u\007tlbginv\010tlbginvf\005tlbgp\005tlbgr\006tlbgwi\006tlbgwr\006tlbin"
5174 "v\007tlbinvf\004tlbp\004tlbr\005tlbwi\005tlbwr\003tlt\004tlti\005tltiu\004"
5175 "tltu\003tne\004tnei\ttrunc.l.d\ttrunc.l.s\ttrunc.w.d\ttrunc.w.s\003ulh\004"
5176 "ulhu\003ulw\003ush\003usw\006v3mulu\004vmm0\005vmulu\006vshf.b\006vshf."
5177 "d\006vshf.h\006vshf.w\004wait\005wrdsp\006wrpgpr\004wsbh\003xor\005xor."
5178 "v\005xor16\004xori\006xori.b\005yield";
5179
5180// Feature bitsets.
5181enum : uint8_t {
5182 AMFBS_None,
5183 AMFBS_HasCnMips,
5184 AMFBS_HasCnMipsP,
5185 AMFBS_HasDSP,
5186 AMFBS_HasDSPR2,
5187 AMFBS_HasMT,
5188 AMFBS_InMicroMips,
5189 AMFBS_InMips16Mode,
5190 AMFBS_IsGP32bit,
5191 AMFBS_IsGP64bit,
5192 AMFBS_IsNotSoftFloat,
5193 AMFBS_NotCnMips,
5194 AMFBS_NotInMicroMips,
5195 AMFBS_HasDSP_InMicroMips,
5196 AMFBS_HasDSP_NotInMicroMips,
5197 AMFBS_HasMT_NotInMicroMips,
5198 AMFBS_HasMips64_HasCnMips,
5199 AMFBS_HasStdEnc_HasMSA,
5200 AMFBS_HasStdEnc_HasMips3,
5201 AMFBS_HasStdEnc_HasMips32,
5202 AMFBS_HasStdEnc_HasMips32r6,
5203 AMFBS_HasStdEnc_HasMips64,
5204 AMFBS_HasStdEnc_HasMips64r6,
5205 AMFBS_HasStdEnc_IsNotSoftFloat,
5206 AMFBS_HasStdEnc_NotInMicroMips,
5207 AMFBS_HasStdEnc_NotMips3,
5208 AMFBS_InMicroMips_HasDSP,
5209 AMFBS_InMicroMips_HasDSPR2,
5210 AMFBS_InMicroMips_HasDSPR3,
5211 AMFBS_InMicroMips_HasEVA,
5212 AMFBS_InMicroMips_HasMips32r6,
5213 AMFBS_InMicroMips_IsNotSoftFloat,
5214 AMFBS_InMicroMips_NotMips32r6,
5215 AMFBS_IsGP32bit_NotInMicroMips,
5216 AMFBS_IsGP64bit_NotInMicroMips,
5217 AMFBS_NotInMips16Mode_HasDSP,
5218 AMFBS_NotInMips16Mode_IsPTR64bit,
5219 AMFBS_HasMips64_HasCnMips_NotInMicroMips,
5220 AMFBS_HasStdEnc_HasMSA_HasMips64,
5221 AMFBS_HasStdEnc_HasMT_NotInMicroMips,
5222 AMFBS_HasStdEnc_HasMips2_IsNotSoftFloat,
5223 AMFBS_HasStdEnc_HasMips2_NotInMicroMips,
5224 AMFBS_HasStdEnc_HasMips3_NotInMicroMips,
5225 AMFBS_HasStdEnc_HasMips32_NotInMicroMips,
5226 AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips,
5227 AMFBS_HasStdEnc_HasMips32r5_NotInMicroMips,
5228 AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips,
5229 AMFBS_HasStdEnc_HasMips3_32_NotInMicroMips,
5230 AMFBS_HasStdEnc_HasMips64_NotInMicroMips,
5231 AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips,
5232 AMFBS_HasStdEnc_HasMips64r5_HasVirt,
5233 AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips,
5234 AMFBS_HasStdEnc_IsGP32bit_HasMips32r6,
5235 AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips,
5236 AMFBS_HasStdEnc_IsGP64bit_HasMips3,
5237 AMFBS_HasStdEnc_IsGP64bit_HasMips32r6,
5238 AMFBS_HasStdEnc_IsGP64bit_HasMips64r6,
5239 AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
5240 AMFBS_HasStdEnc_NotInMicroMips_NoIndirectJumpGuards,
5241 AMFBS_HasStdEnc_NotMips32r6_NotMips64r6,
5242 AMFBS_InMicroMips_HasMips32r5_HasVirt,
5243 AMFBS_InMicroMips_HasMips32r6_HasGINV,
5244 AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat,
5245 AMFBS_InMicroMips_NotMips32r6_HasDSP,
5246 AMFBS_InMicroMips_NotMips32r6_HasEVA,
5247 AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat,
5248 AMFBS_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat,
5249 AMFBS_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat,
5250 AMFBS_NotInMips16Mode_IsPTR64bit_NotInMicroMips,
5251 AMFBS_HasMips3_NotMips64r6_NotCnMips_NotR5900,
5252 AMFBS_HasStdEnc_HasMips2_IsNotSoftFloat_NotInMicroMips,
5253 AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6,
5254 AMFBS_HasStdEnc_HasMips3_IsNotSoftFloat_IsNotSingleFloat,
5255 AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6,
5256 AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6,
5257 AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips,
5258 AMFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6,
5259 AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips,
5260 AMFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips,
5261 AMFBS_HasStdEnc_HasMips32r6_HasGINV_NotInMicroMips,
5262 AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips,
5263 AMFBS_HasStdEnc_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips,
5264 AMFBS_HasStdEnc_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips,
5265 AMFBS_HasStdEnc_HasMips64_NotMips64r6_NotInMicroMips,
5266 AMFBS_HasStdEnc_HasMips64r5_HasVirt_NotInMicroMips,
5267 AMFBS_HasStdEnc_HasMips64r6_HasCRC_NotInMicroMips,
5268 AMFBS_HasStdEnc_IsGP32bit_HasMips32r6_NotInMicroMips,
5269 AMFBS_HasStdEnc_IsGP64bit_HasMips3_NotInMicroMips,
5270 AMFBS_HasStdEnc_IsPTR32bit_HasMips32r6_NotInMicroMips,
5271 AMFBS_HasStdEnc_IsPTR64bit_HasMips64r6_NotInMicroMips,
5272 AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat,
5273 AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips,
5274 AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat,
5275 AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat,
5276 AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat_HasMadd4,
5277 AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips,
5278 AMFBS_HasStdEnc_HasMips2_NotR5900_IsNotSoftFloat_NotInMicroMips,
5279 AMFBS_HasStdEnc_HasMips2_NotR5900_NotCnMips_NotInMicroMips,
5280 AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips,
5281 AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900,
5282 AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips,
5283 AMFBS_HasStdEnc_HasMips3_32_NotMips32r6_NotMips64r6_NotInMicroMips,
5284 AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips,
5285 AMFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat,
5286 AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat,
5287 AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips,
5288 AMFBS_HasStdEnc_IsGP64bit_HasMips64_NotMips64r6_NotInMicroMips,
5289 AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat,
5290 AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips,
5291 AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips,
5292 AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_HasMips32r6_IsNotSoftFloat,
5293 AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat,
5294 AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat,
5295 AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips,
5296 AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips,
5297 AMFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips,
5298 AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips,
5299 AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips,
5300 AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips32r2_IsNotSoftFloat_NotInMicroMips,
5301 AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips3_32_IsNotSoftFloat_NotInMicroMips,
5302 AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips,
5303 AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips,
5304 AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips,
5305 AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips32r2_IsNotSoftFloat_NotInMicroMips,
5306 AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips,
5307 AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips,
5308 AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_NotCnMips_NotInMicroMips,
5309 AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat_HasMadd4,
5310 AMFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips,
5311 AMFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4,
5312 AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat,
5313 AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips,
5314 AMFBS_HasStdEnc_IsPTR32bit_HasMips2_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips,
5315 AMFBS_HasStdEnc_IsPTR64bit_HasMips2_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips,
5316 AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips,
5317 AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMips3D,
5318 AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips,
5319 AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips,
5320 AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips,
5321 AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips,
5322 AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips,
5323 AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips,
5324 AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips,
5325 AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4,
5326 AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips,
5327 AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4,
5328};
5329
5330static constexpr FeatureBitset FeatureBitsets[] = {
5331 {}, // AMFBS_None
5332 {Feature_HasCnMipsBit, }, // AMFBS_HasCnMips
5333 {Feature_HasCnMipsPBit, }, // AMFBS_HasCnMipsP
5334 {Feature_HasDSPBit, }, // AMFBS_HasDSP
5335 {Feature_HasDSPR2Bit, }, // AMFBS_HasDSPR2
5336 {Feature_HasMTBit, }, // AMFBS_HasMT
5337 {Feature_InMicroMipsBit, }, // AMFBS_InMicroMips
5338 {Feature_InMips16ModeBit, }, // AMFBS_InMips16Mode
5339 {Feature_IsGP32bitBit, }, // AMFBS_IsGP32bit
5340 {Feature_IsGP64bitBit, }, // AMFBS_IsGP64bit
5341 {Feature_IsNotSoftFloatBit, }, // AMFBS_IsNotSoftFloat
5342 {Feature_NotCnMipsBit, }, // AMFBS_NotCnMips
5343 {Feature_NotInMicroMipsBit, }, // AMFBS_NotInMicroMips
5344 {Feature_HasDSPBit, Feature_InMicroMipsBit, }, // AMFBS_HasDSP_InMicroMips
5345 {Feature_HasDSPBit, Feature_NotInMicroMipsBit, }, // AMFBS_HasDSP_NotInMicroMips
5346 {Feature_HasMTBit, Feature_NotInMicroMipsBit, }, // AMFBS_HasMT_NotInMicroMips
5347 {Feature_HasMips64Bit, Feature_HasCnMipsBit, }, // AMFBS_HasMips64_HasCnMips
5348 {Feature_HasStdEncBit, Feature_HasMSABit, }, // AMFBS_HasStdEnc_HasMSA
5349 {Feature_HasStdEncBit, Feature_HasMips3Bit, }, // AMFBS_HasStdEnc_HasMips3
5350 {Feature_HasStdEncBit, Feature_HasMips32Bit, }, // AMFBS_HasStdEnc_HasMips32
5351 {Feature_HasStdEncBit, Feature_HasMips32r6Bit, }, // AMFBS_HasStdEnc_HasMips32r6
5352 {Feature_HasStdEncBit, Feature_HasMips64Bit, }, // AMFBS_HasStdEnc_HasMips64
5353 {Feature_HasStdEncBit, Feature_HasMips64r6Bit, }, // AMFBS_HasStdEnc_HasMips64r6
5354 {Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, }, // AMFBS_HasStdEnc_IsNotSoftFloat
5355 {Feature_HasStdEncBit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_NotInMicroMips
5356 {Feature_HasStdEncBit, Feature_NotMips3Bit, }, // AMFBS_HasStdEnc_NotMips3
5357 {Feature_InMicroMipsBit, Feature_HasDSPBit, }, // AMFBS_InMicroMips_HasDSP
5358 {Feature_InMicroMipsBit, Feature_HasDSPR2Bit, }, // AMFBS_InMicroMips_HasDSPR2
5359 {Feature_InMicroMipsBit, Feature_HasDSPR3Bit, }, // AMFBS_InMicroMips_HasDSPR3
5360 {Feature_InMicroMipsBit, Feature_HasEVABit, }, // AMFBS_InMicroMips_HasEVA
5361 {Feature_InMicroMipsBit, Feature_HasMips32r6Bit, }, // AMFBS_InMicroMips_HasMips32r6
5362 {Feature_InMicroMipsBit, Feature_IsNotSoftFloatBit, }, // AMFBS_InMicroMips_IsNotSoftFloat
5363 {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, }, // AMFBS_InMicroMips_NotMips32r6
5364 {Feature_IsGP32bitBit, Feature_NotInMicroMipsBit, }, // AMFBS_IsGP32bit_NotInMicroMips
5365 {Feature_IsGP64bitBit, Feature_NotInMicroMipsBit, }, // AMFBS_IsGP64bit_NotInMicroMips
5366 {Feature_NotInMips16ModeBit, Feature_HasDSPBit, }, // AMFBS_NotInMips16Mode_HasDSP
5367 {Feature_NotInMips16ModeBit, Feature_IsPTR64bitBit, }, // AMFBS_NotInMips16Mode_IsPTR64bit
5368 {Feature_HasMips64Bit, Feature_HasCnMipsBit, Feature_NotInMicroMipsBit, }, // AMFBS_HasMips64_HasCnMips_NotInMicroMips
5369 {Feature_HasStdEncBit, Feature_HasMSABit, Feature_HasMips64Bit, }, // AMFBS_HasStdEnc_HasMSA_HasMips64
5370 {Feature_HasStdEncBit, Feature_HasMTBit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_HasMT_NotInMicroMips
5371 {Feature_HasStdEncBit, Feature_HasMips2Bit, Feature_IsNotSoftFloatBit, }, // AMFBS_HasStdEnc_HasMips2_IsNotSoftFloat
5372 {Feature_HasStdEncBit, Feature_HasMips2Bit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_HasMips2_NotInMicroMips
5373 {Feature_HasStdEncBit, Feature_HasMips3Bit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_HasMips3_NotInMicroMips
5374 {Feature_HasStdEncBit, Feature_HasMips32Bit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_HasMips32_NotInMicroMips
5375 {Feature_HasStdEncBit, Feature_HasMips32r2Bit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips
5376 {Feature_HasStdEncBit, Feature_HasMips32r5Bit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_HasMips32r5_NotInMicroMips
5377 {Feature_HasStdEncBit, Feature_HasMips32r6Bit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips
5378 {Feature_HasStdEncBit, Feature_HasMips3_32Bit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_HasMips3_32_NotInMicroMips
5379 {Feature_HasStdEncBit, Feature_HasMips64Bit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_HasMips64_NotInMicroMips
5380 {Feature_HasStdEncBit, Feature_HasMips64r2Bit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips
5381 {Feature_HasStdEncBit, Feature_HasMips64r5Bit, Feature_HasVirtBit, }, // AMFBS_HasStdEnc_HasMips64r5_HasVirt
5382 {Feature_HasStdEncBit, Feature_HasMips64r6Bit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips
5383 {Feature_HasStdEncBit, Feature_IsGP32bitBit, Feature_HasMips32r6Bit, }, // AMFBS_HasStdEnc_IsGP32bit_HasMips32r6
5384 {Feature_HasStdEncBit, Feature_IsGP32bitBit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips
5385 {Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_HasMips3Bit, }, // AMFBS_HasStdEnc_IsGP64bit_HasMips3
5386 {Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_HasMips32r6Bit, }, // AMFBS_HasStdEnc_IsGP64bit_HasMips32r6
5387 {Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_HasMips64r6Bit, }, // AMFBS_HasStdEnc_IsGP64bit_HasMips64r6
5388 {Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips
5389 {Feature_HasStdEncBit, Feature_NotInMicroMipsBit, Feature_NoIndirectJumpGuardsBit, }, // AMFBS_HasStdEnc_NotInMicroMips_NoIndirectJumpGuards
5390 {Feature_HasStdEncBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, }, // AMFBS_HasStdEnc_NotMips32r6_NotMips64r6
5391 {Feature_InMicroMipsBit, Feature_HasMips32r5Bit, Feature_HasVirtBit, }, // AMFBS_InMicroMips_HasMips32r5_HasVirt
5392 {Feature_InMicroMipsBit, Feature_HasMips32r6Bit, Feature_HasGINVBit, }, // AMFBS_InMicroMips_HasMips32r6_HasGINV
5393 {Feature_InMicroMipsBit, Feature_HasMips32r6Bit, Feature_IsNotSoftFloatBit, }, // AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat
5394 {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_HasDSPBit, }, // AMFBS_InMicroMips_NotMips32r6_HasDSP
5395 {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_HasEVABit, }, // AMFBS_InMicroMips_NotMips32r6_HasEVA
5396 {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_IsNotSoftFloatBit, }, // AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat
5397 {Feature_IsFP64bitBit, Feature_IsNotSingleFloatBit, Feature_IsNotSoftFloatBit, }, // AMFBS_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat
5398 {Feature_NotFP64bitBit, Feature_IsNotSingleFloatBit, Feature_IsNotSoftFloatBit, }, // AMFBS_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat
5399 {Feature_NotInMips16ModeBit, Feature_IsPTR64bitBit, Feature_NotInMicroMipsBit, }, // AMFBS_NotInMips16Mode_IsPTR64bit_NotInMicroMips
5400 {Feature_HasMips3Bit, Feature_NotMips64r6Bit, Feature_NotCnMipsBit, Feature_NotR5900Bit, }, // AMFBS_HasMips3_NotMips64r6_NotCnMips_NotR5900
5401 {Feature_HasStdEncBit, Feature_HasMips2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_HasMips2_IsNotSoftFloat_NotInMicroMips
5402 {Feature_HasStdEncBit, Feature_HasMips2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, }, // AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6
5403 {Feature_HasStdEncBit, Feature_HasMips3Bit, Feature_IsNotSoftFloatBit, Feature_IsNotSingleFloatBit, }, // AMFBS_HasStdEnc_HasMips3_IsNotSoftFloat_IsNotSingleFloat
5404 {Feature_HasStdEncBit, Feature_HasMips3Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, }, // AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6
5405 {Feature_HasStdEncBit, Feature_HasMips32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, }, // AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6
5406 {Feature_HasStdEncBit, Feature_HasMips32r2Bit, Feature_HasEVABit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips
5407 {Feature_HasStdEncBit, Feature_HasMips32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, }, // AMFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6
5408 {Feature_HasStdEncBit, Feature_HasMips32r5Bit, Feature_HasVirtBit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips
5409 {Feature_HasStdEncBit, Feature_HasMips32r6Bit, Feature_HasCRCBit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips
5410 {Feature_HasStdEncBit, Feature_HasMips32r6Bit, Feature_HasGINVBit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_HasMips32r6_HasGINV_NotInMicroMips
5411 {Feature_HasStdEncBit, Feature_HasMips32r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips
5412 {Feature_HasStdEncBit, Feature_HasMips3_32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips
5413 {Feature_HasStdEncBit, Feature_HasMips4_32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips
5414 {Feature_HasStdEncBit, Feature_HasMips64Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_HasMips64_NotMips64r6_NotInMicroMips
5415 {Feature_HasStdEncBit, Feature_HasMips64r5Bit, Feature_HasVirtBit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_HasMips64r5_HasVirt_NotInMicroMips
5416 {Feature_HasStdEncBit, Feature_HasMips64r6Bit, Feature_HasCRCBit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_HasMips64r6_HasCRC_NotInMicroMips
5417 {Feature_HasStdEncBit, Feature_IsGP32bitBit, Feature_HasMips32r6Bit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_IsGP32bit_HasMips32r6_NotInMicroMips
5418 {Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_HasMips3Bit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_IsGP64bit_HasMips3_NotInMicroMips
5419 {Feature_HasStdEncBit, Feature_IsPTR32bitBit, Feature_HasMips32r6Bit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_IsPTR32bit_HasMips32r6_NotInMicroMips
5420 {Feature_HasStdEncBit, Feature_IsPTR64bitBit, Feature_HasMips64r6Bit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_IsPTR64bit_HasMips64r6_NotInMicroMips
5421 {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_IsNotSingleFloatBit, Feature_IsNotSoftFloatBit, }, // AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat
5422 {Feature_HasStdEncBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips
5423 {Feature_InMicroMipsBit, Feature_IsFP64bitBit, Feature_IsNotSingleFloatBit, Feature_IsNotSoftFloatBit, }, // AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat
5424 {Feature_InMicroMipsBit, Feature_NotFP64bitBit, Feature_IsNotSingleFloatBit, Feature_IsNotSoftFloatBit, }, // AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat
5425 {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_IsNotSoftFloatBit, Feature_HasMadd4Bit, }, // AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat_HasMadd4
5426 {Feature_HasStdEncBit, Feature_HasMips2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips
5427 {Feature_HasStdEncBit, Feature_HasMips2Bit, Feature_NotR5900Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_HasMips2_NotR5900_IsNotSoftFloat_NotInMicroMips
5428 {Feature_HasStdEncBit, Feature_HasMips2Bit, Feature_NotR5900Bit, Feature_NotCnMipsBit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_HasMips2_NotR5900_NotCnMips_NotInMicroMips
5429 {Feature_HasStdEncBit, Feature_HasMips3Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips
5430 {Feature_HasStdEncBit, Feature_HasMips3Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotR5900Bit, }, // AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900
5431 {Feature_HasStdEncBit, Feature_HasMips32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips
5432 {Feature_HasStdEncBit, Feature_HasMips3_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_HasMips3_32_NotMips32r6_NotMips64r6_NotInMicroMips
5433 {Feature_HasStdEncBit, Feature_HasMips4_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips
5434 {Feature_HasStdEncBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, }, // AMFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat
5435 {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSingleFloatBit, Feature_HasMips2Bit, Feature_IsNotSoftFloatBit, }, // AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat
5436 {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSingleFloatBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips
5437 {Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_HasMips64Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_IsGP64bit_HasMips64_NotMips64r6_NotInMicroMips
5438 {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_IsNotSingleFloatBit, Feature_HasMips2Bit, Feature_IsNotSoftFloatBit, }, // AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat
5439 {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_IsNotSingleFloatBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips
5440 {Feature_HasStdEncBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips
5441 {Feature_InMicroMipsBit, Feature_IsFP64bitBit, Feature_IsNotSingleFloatBit, Feature_HasMips32r6Bit, Feature_IsNotSoftFloatBit, }, // AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_HasMips32r6_IsNotSoftFloat
5442 {Feature_InMicroMipsBit, Feature_IsFP64bitBit, Feature_IsNotSingleFloatBit, Feature_NotMips32r6Bit, Feature_IsNotSoftFloatBit, }, // AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat
5443 {Feature_InMicroMipsBit, Feature_NotFP64bitBit, Feature_IsNotSingleFloatBit, Feature_NotMips32r6Bit, Feature_IsNotSoftFloatBit, }, // AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat
5444 {Feature_HasStdEncBit, Feature_HasMips2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips
5445 {Feature_HasStdEncBit, Feature_HasMips3Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotR5900Bit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips
5446 {Feature_HasStdEncBit, Feature_HasMips32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_HasEVABit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips
5447 {Feature_HasStdEncBit, Feature_HasMips4_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips
5448 {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSingleFloatBit, Feature_HasMips2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips
5449 {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSingleFloatBit, Feature_HasMips32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips32r2_IsNotSoftFloat_NotInMicroMips
5450 {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSingleFloatBit, Feature_HasMips3_32Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips3_32_IsNotSoftFloat_NotInMicroMips
5451 {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSingleFloatBit, Feature_HasMips3_32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips
5452 {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSingleFloatBit, Feature_HasMips4_32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips
5453 {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_IsNotSingleFloatBit, Feature_HasMips2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips
5454 {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_IsNotSingleFloatBit, Feature_HasMips32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips32r2_IsNotSoftFloat_NotInMicroMips
5455 {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_IsNotSingleFloatBit, Feature_HasMips4_32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips
5456 {Feature_HasStdEncBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotR5900Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips
5457 {Feature_HasStdEncBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotR5900Bit, Feature_NotCnMipsBit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_NotCnMips_NotInMicroMips
5458 {Feature_InMicroMipsBit, Feature_NotFP64bitBit, Feature_IsNotSingleFloatBit, Feature_NotMips32r6Bit, Feature_IsNotSoftFloatBit, Feature_HasMadd4Bit, }, // AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat_HasMadd4
5459 {Feature_HasStdEncBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_HasMadd4Bit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips
5460 {Feature_HasStdEncBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, Feature_HasMadd4Bit, }, // AMFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4
5461 {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSingleFloatBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, }, // AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat
5462 {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSingleFloatBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips
5463 {Feature_HasStdEncBit, Feature_IsPTR32bitBit, Feature_HasMips2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotR5900Bit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_IsPTR32bit_HasMips2_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips
5464 {Feature_HasStdEncBit, Feature_IsPTR64bitBit, Feature_HasMips2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotR5900Bit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_IsPTR64bit_HasMips2_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips
5465 {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_IsNotSingleFloatBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips
5466 {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSingleFloatBit, Feature_HasMips32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_HasMips3DBit, }, // AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMips3D
5467 {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSingleFloatBit, Feature_HasMips32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips
5468 {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSingleFloatBit, Feature_HasMips4_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips
5469 {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSingleFloatBit, Feature_HasMips5_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips
5470 {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_IsNotSingleFloatBit, Feature_HasMips4_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips
5471 {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_IsNotSingleFloatBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips
5472 {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_IsNotSingleFloatBit, Feature_HasMips5_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips
5473 {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSingleFloatBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_HasMadd4Bit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips
5474 {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSingleFloatBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, Feature_HasMadd4Bit, }, // AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4
5475 {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_IsNotSingleFloatBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_HasMadd4Bit, Feature_NotInMicroMipsBit, }, // AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips
5476 {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_IsNotSingleFloatBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, Feature_HasMadd4Bit, }, // AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4
5477};
5478
5479namespace {
5480 struct MatchEntry {
5481 uint16_t Mnemonic;
5482 uint32_t Opcode;
5483 uint16_t ConvertFn;
5484 uint8_t RequiredFeaturesIdx;
5485 uint8_t Classes[8];
5486 StringRef getMnemonic() const {
5487 return StringRef(MnemonicTable + Mnemonic + 1,
5488 MnemonicTable[Mnemonic]);
5489 }
5490 };
5491
5492 // Predicate for searching for an opcode.
5493 struct LessOpcode {
5494 bool operator()(const MatchEntry &LHS, StringRef RHS) {
5495 return LHS.getMnemonic() < RHS;
5496 }
5497 bool operator()(StringRef LHS, const MatchEntry &RHS) {
5498 return LHS < RHS.getMnemonic();
5499 }
5500 bool operator()(const MatchEntry &LHS, const MatchEntry &RHS) {
5501 return LHS.getMnemonic() < RHS.getMnemonic();
5502 }
5503 };
5504} // end anonymous namespace
5505
5506static const MatchEntry MatchTable0[] = {
5507 { 0 /* abs */, Mips::ABSMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_None, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5508 { 4 /* abs.d */, Mips::FABS_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5509 { 4 /* abs.d */, Mips::FABS_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5510 { 4 /* abs.d */, Mips::FABS_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5511 { 4 /* abs.d */, Mips::FABS_D64_MM, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5512 { 10 /* abs.s */, Mips::FABS_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5513 { 10 /* abs.s */, Mips::FABS_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5514 { 16 /* absq_s.ph */, Mips::ABSQ_S_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5515 { 16 /* absq_s.ph */, Mips::ABSQ_S_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5516 { 26 /* absq_s.qb */, Mips::ABSQ_S_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5517 { 26 /* absq_s.qb */, Mips::ABSQ_S_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5518 { 36 /* absq_s.w */, Mips::ABSQ_S_W_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5519 { 36 /* absq_s.w */, Mips::ABSQ_S_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5520 { 45 /* add */, Mips::ADD, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5521 { 45 /* add */, Mips::ADD_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5522 { 45 /* add */, Mips::ADD_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5523 { 45 /* add */, Mips::ADDi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
5524 { 45 /* add */, Mips::ADDi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
5525 { 45 /* add */, Mips::ADD, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5526 { 45 /* add */, Mips::ADD_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5527 { 45 /* add */, Mips::ADD_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5528 { 45 /* add */, Mips::ADDi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
5529 { 45 /* add */, Mips::ADDi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
5530 { 49 /* add.d */, Mips::FADD_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5531 { 49 /* add.d */, Mips::FADD_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5532 { 49 /* add.d */, Mips::FADD_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5533 { 49 /* add.d */, Mips::FADD_D64_MM, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5534 { 55 /* add.ps */, Mips::FADD_PS64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5535 { 62 /* add.s */, Mips::FADD_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5536 { 62 /* add.s */, Mips::FADD_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_2__FGR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5537 { 62 /* add.s */, Mips::FADD_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5538 { 68 /* add_a.b */, Mips::ADD_A_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5539 { 76 /* add_a.d */, Mips::ADD_A_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5540 { 84 /* add_a.h */, Mips::ADD_A_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5541 { 92 /* add_a.w */, Mips::ADD_A_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5542 { 100 /* addi */, Mips::ADDi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm161_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, },
5543 { 100 /* addi */, Mips::ADDi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm16_Relaxed1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm16_Relaxed }, },
5544 { 100 /* addi */, Mips::ADDi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16 }, },
5545 { 100 /* addi */, Mips::ADDi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm16_Relaxed1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16_Relaxed }, },
5546 { 105 /* addiu */, Mips::AddiuSpImmX16, Convert__SImm161_1, AMFBS_InMips16Mode, { MCK_CPUSPReg, MCK_SImm16 }, },
5547 { 105 /* addiu */, Mips::AddiuRxImmX16, Convert__Reg1_0__SImm161_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_SImm16 }, },
5548 { 105 /* addiu */, Mips::ADDIU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm161_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, },
5549 { 105 /* addiu */, Mips::ADDiu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm161_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, },
5550 { 105 /* addiu */, Mips::ADDiu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm16_Relaxed1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm16_Relaxed }, },
5551 { 105 /* addiu */, Mips::AddiuRxPcImmX16, Convert__Reg1_0__SImm161_2, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_PC, MCK_SImm16 }, },
5552 { 105 /* addiu */, Mips::AddiuRxRyOffMemX16, Convert__Reg1_0__Reg1_1__SImm161_2, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16RegsPlusSP, MCK_SImm16 }, },
5553 { 105 /* addiu */, Mips::ADDIU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16 }, },
5554 { 105 /* addiu */, Mips::ADDiu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16 }, },
5555 { 105 /* addiu */, Mips::ADDiu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm16_Relaxed1_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16_Relaxed }, },
5556 { 105 /* addiu */, Mips::AddiuSpImm16, Convert__SImm161_1, AMFBS_InMips16Mode, { MCK_CPUSPReg, MCK_SImm16, MCK__HASH_, MCK_16, MCK_bit, MCK_inst }, },
5557 { 105 /* addiu */, Mips::AddiuRxRxImm16, Convert__Reg1_0__Tie0_1_1__SImm161_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_SImm16, MCK__HASH_, MCK_16, MCK_bit, MCK_inst }, },
5558 { 111 /* addiupc */, Mips::ADDIUPC, Convert__GPR32AsmReg1_0__Simm19_Lsl21_1, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR32AsmReg, MCK_Simm19_Lsl2 }, },
5559 { 111 /* addiupc */, Mips::ADDIUPC_MMR6, Convert__GPR32AsmReg1_0__Simm19_Lsl21_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_Simm19_Lsl2 }, },
5560 { 111 /* addiupc */, Mips::ADDIUPC_MM, Convert__GPRMM16AsmReg1_0__Imm1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_Imm }, },
5561 { 119 /* addiur1sp */, Mips::ADDIUR1SP_MM, Convert__GPRMM16AsmReg1_0__UImm6Lsl21_1, AMFBS_InMicroMips, { MCK_GPRMM16AsmReg, MCK_UImm6Lsl2 }, },
5562 { 129 /* addiur2 */, Mips::ADDIUR2_MM, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Imm1_2, AMFBS_InMicroMips, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_Imm }, },
5563 { 137 /* addius5 */, Mips::ADDIUS5_MM, Convert__GPR32AsmReg1_0__Tie0_1_1__ConstantSImm4_01_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_ConstantSImm4_0 }, },
5564 { 145 /* addiusp */, Mips::ADDIUSP_MM, Convert__Imm1_0, AMFBS_InMicroMips, { MCK_Imm }, },
5565 { 153 /* addq.ph */, Mips::ADDQ_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5566 { 153 /* addq.ph */, Mips::ADDQ_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5567 { 161 /* addq_s.ph */, Mips::ADDQ_S_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5568 { 161 /* addq_s.ph */, Mips::ADDQ_S_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5569 { 171 /* addq_s.w */, Mips::ADDQ_S_W_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5570 { 171 /* addq_s.w */, Mips::ADDQ_S_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5571 { 180 /* addqh.ph */, Mips::ADDQH_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5572 { 180 /* addqh.ph */, Mips::ADDQH_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5573 { 189 /* addqh.w */, Mips::ADDQH_W_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5574 { 189 /* addqh.w */, Mips::ADDQH_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5575 { 197 /* addqh_r.ph */, Mips::ADDQH_R_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5576 { 197 /* addqh_r.ph */, Mips::ADDQH_R_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5577 { 208 /* addqh_r.w */, Mips::ADDQH_R_W_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5578 { 208 /* addqh_r.w */, Mips::ADDQH_R_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5579 { 218 /* addr.ps */, Mips::ADDR_PS64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMips3D, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5580 { 226 /* adds_a.b */, Mips::ADDS_A_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5581 { 235 /* adds_a.d */, Mips::ADDS_A_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5582 { 244 /* adds_a.h */, Mips::ADDS_A_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5583 { 253 /* adds_a.w */, Mips::ADDS_A_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5584 { 262 /* adds_s.b */, Mips::ADDS_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5585 { 271 /* adds_s.d */, Mips::ADDS_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5586 { 280 /* adds_s.h */, Mips::ADDS_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5587 { 289 /* adds_s.w */, Mips::ADDS_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5588 { 298 /* adds_u.b */, Mips::ADDS_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5589 { 307 /* adds_u.d */, Mips::ADDS_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5590 { 316 /* adds_u.h */, Mips::ADDS_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5591 { 325 /* adds_u.w */, Mips::ADDS_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5592 { 334 /* addsc */, Mips::ADDSC_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5593 { 334 /* addsc */, Mips::ADDSC, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5594 { 340 /* addu */, Mips::ADDU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5595 { 340 /* addu */, Mips::ADDu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5596 { 340 /* addu */, Mips::ADDu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5597 { 340 /* addu */, Mips::ADDiu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
5598 { 340 /* addu */, Mips::ADDiu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
5599 { 340 /* addu */, Mips::AdduRxRyRz16, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs, MCK_CPU16Regs }, },
5600 { 340 /* addu */, Mips::ADDU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5601 { 340 /* addu */, Mips::ADDu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5602 { 340 /* addu */, Mips::ADDu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5603 { 340 /* addu */, Mips::ADDiu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
5604 { 340 /* addu */, Mips::ADDiu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
5605 { 345 /* addu.ph */, Mips::ADDU_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5606 { 345 /* addu.ph */, Mips::ADDU_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5607 { 353 /* addu.qb */, Mips::ADDU_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5608 { 353 /* addu.qb */, Mips::ADDU_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5609 { 361 /* addu16 */, Mips::ADDU16_MM, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__GPRMM16AsmReg1_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, },
5610 { 361 /* addu16 */, Mips::ADDU16_MMR6, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__GPRMM16AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, },
5611 { 368 /* addu_s.ph */, Mips::ADDU_S_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5612 { 368 /* addu_s.ph */, Mips::ADDU_S_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5613 { 378 /* addu_s.qb */, Mips::ADDU_S_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5614 { 378 /* addu_s.qb */, Mips::ADDU_S_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5615 { 388 /* adduh.qb */, Mips::ADDUH_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5616 { 388 /* adduh.qb */, Mips::ADDUH_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5617 { 397 /* adduh_r.qb */, Mips::ADDUH_R_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5618 { 397 /* adduh_r.qb */, Mips::ADDUH_R_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5619 { 408 /* addv.b */, Mips::ADDV_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5620 { 415 /* addv.d */, Mips::ADDV_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5621 { 422 /* addv.h */, Mips::ADDV_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5622 { 429 /* addv.w */, Mips::ADDV_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5623 { 436 /* addvi.b */, Mips::ADDVI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
5624 { 444 /* addvi.d */, Mips::ADDVI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
5625 { 452 /* addvi.h */, Mips::ADDVI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
5626 { 460 /* addvi.w */, Mips::ADDVI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
5627 { 468 /* addwc */, Mips::ADDWC_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5628 { 468 /* addwc */, Mips::ADDWC, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5629 { 474 /* align */, Mips::ALIGN, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__ConstantUImm2_01_3, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm2_0 }, },
5630 { 474 /* align */, Mips::ALIGN_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__ConstantUImm2_01_3, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm2_0 }, },
5631 { 480 /* aluipc */, Mips::ALUIPC, Convert__GPR32AsmReg1_0__SImm161_1, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, },
5632 { 480 /* aluipc */, Mips::ALUIPC_MMR6, Convert__GPR32AsmReg1_0__SImm161_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, },
5633 { 487 /* and */, Mips::AndRxRxRy16, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs }, },
5634 { 487 /* and */, Mips::AND, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5635 { 487 /* and */, Mips::AND_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5636 { 487 /* and */, Mips::AND_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5637 { 487 /* and */, Mips::ANDI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_UImm16 }, },
5638 { 487 /* and */, Mips::ANDi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
5639 { 487 /* and */, Mips::ANDi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
5640 { 487 /* and */, Mips::ANDi64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, AMFBS_HasStdEnc_IsGP64bit_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_Imm }, },
5641 { 487 /* and */, Mips::AND, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5642 { 487 /* and */, Mips::AND_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5643 { 487 /* and */, Mips::AND_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5644 { 487 /* and */, Mips::ANDI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, },
5645 { 487 /* and */, Mips::ANDi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
5646 { 487 /* and */, Mips::ANDi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
5647 { 487 /* and */, Mips::ANDi64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, AMFBS_HasStdEnc_IsGP64bit_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, },
5648 { 491 /* and.v */, Mips::AND_V, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5649 { 497 /* and16 */, Mips::AND16_MM, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Tie0_1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, },
5650 { 497 /* and16 */, Mips::AND16_MMR6, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Tie0_1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, },
5651 { 503 /* andi */, Mips::ANDI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_UImm16 }, },
5652 { 503 /* andi */, Mips::ANDi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_UImm16 }, },
5653 { 503 /* andi */, Mips::ANDi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_UImm16 }, },
5654 { 503 /* andi */, Mips::ANDI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, },
5655 { 503 /* andi */, Mips::ANDi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, },
5656 { 503 /* andi */, Mips::ANDi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, },
5657 { 508 /* andi.b */, Mips::ANDI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm8_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm8_0 }, },
5658 { 515 /* andi16 */, Mips::ANDI16_MM, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Imm1_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_Imm }, },
5659 { 515 /* andi16 */, Mips::ANDI16_MMR6, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Imm1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_Imm }, },
5660 { 522 /* append */, Mips::APPEND_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Tie0_1_1, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
5661 { 522 /* append */, Mips::APPEND, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Tie0_1_1, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
5662 { 529 /* asub_s.b */, Mips::ASUB_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5663 { 538 /* asub_s.d */, Mips::ASUB_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5664 { 547 /* asub_s.h */, Mips::ASUB_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5665 { 556 /* asub_s.w */, Mips::ASUB_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5666 { 565 /* asub_u.b */, Mips::ASUB_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5667 { 574 /* asub_u.d */, Mips::ASUB_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5668 { 583 /* asub_u.h */, Mips::ASUB_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5669 { 592 /* asub_u.w */, Mips::ASUB_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5670 { 601 /* aui */, Mips::AUI, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, },
5671 { 601 /* aui */, Mips::AUI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, },
5672 { 605 /* auipc */, Mips::AUIPC, Convert__GPR32AsmReg1_0__SImm161_1, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, },
5673 { 605 /* auipc */, Mips::AUIPC_MMR6, Convert__GPR32AsmReg1_0__SImm161_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, },
5674 { 611 /* ave_s.b */, Mips::AVE_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5675 { 619 /* ave_s.d */, Mips::AVE_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5676 { 627 /* ave_s.h */, Mips::AVE_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5677 { 635 /* ave_s.w */, Mips::AVE_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5678 { 643 /* ave_u.b */, Mips::AVE_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5679 { 651 /* ave_u.d */, Mips::AVE_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5680 { 659 /* ave_u.h */, Mips::AVE_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5681 { 667 /* ave_u.w */, Mips::AVE_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5682 { 675 /* aver_s.b */, Mips::AVER_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5683 { 684 /* aver_s.d */, Mips::AVER_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5684 { 693 /* aver_s.h */, Mips::AVER_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5685 { 702 /* aver_s.w */, Mips::AVER_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5686 { 711 /* aver_u.b */, Mips::AVER_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5687 { 720 /* aver_u.d */, Mips::AVER_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5688 { 729 /* aver_u.h */, Mips::AVER_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5689 { 738 /* aver_u.w */, Mips::AVER_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5690 { 747 /* b */, Mips::BEQ, Convert__regZERO__regZERO__JumpTarget1_0, AMFBS_HasStdEnc_NotInMicroMips, { MCK_JumpTarget }, },
5691 { 747 /* b */, Mips::B_MM_Pseudo, Convert__JumpTarget1_0, AMFBS_InMicroMips, { MCK_JumpTarget }, },
5692 { 747 /* b */, Mips::BimmX16, Convert__JumpTarget1_0, AMFBS_InMips16Mode, { MCK_JumpTarget }, },
5693 { 747 /* b */, Mips::B_MMR6_Pseudo, Convert__JumpTarget1_0, AMFBS_None, { MCK_JumpTarget }, },
5694 { 747 /* b */, Mips::Bimm16, Convert__JumpTarget1_0, AMFBS_InMips16Mode, { MCK_JumpTarget, MCK__HASH_, MCK_16, MCK_bit, MCK_inst }, },
5695 { 749 /* b16 */, Mips::BC16_MMR6, Convert__JumpTarget1_0, AMFBS_InMicroMips_HasMips32r6, { MCK_JumpTarget }, },
5696 { 749 /* b16 */, Mips::B16_MM, Convert__JumpTarget1_0, AMFBS_InMicroMips, { MCK_JumpTarget }, },
5697 { 753 /* baddu */, Mips::BADDu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
5698 { 753 /* baddu */, Mips::BADDu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
5699 { 759 /* bal */, Mips::BGEZAL, Convert__regZERO__JumpTarget1_0, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_JumpTarget }, },
5700 { 759 /* bal */, Mips::BAL, Convert__JumpTarget1_0, AMFBS_HasStdEnc_HasMips32r6, { MCK_JumpTarget }, },
5701 { 759 /* bal */, Mips::BGEZAL_MM, Convert__regZERO__JumpTarget1_0, AMFBS_InMicroMips_NotMips32r6, { MCK_JumpTarget }, },
5702 { 763 /* balc */, Mips::BALC, Convert__JumpTarget1_0, AMFBS_HasStdEnc_HasMips32r6, { MCK_JumpTarget }, },
5703 { 763 /* balc */, Mips::BALC_MMR6, Convert__JumpTarget1_0, AMFBS_InMicroMips_HasMips32r6, { MCK_JumpTarget }, },
5704 { 768 /* balign */, Mips::BALIGN_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm2_01_2__Tie0_1_1, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm2_0 }, },
5705 { 768 /* balign */, Mips::BALIGN, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm2_01_2__Tie0_1_1, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm2_0 }, },
5706 { 775 /* bbit0 */, Mips::BBIT032, Convert__GPR64AsmReg1_0__ConstantUImm5_32_Norm1_1__JumpTarget1_2, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_32_Norm, MCK_JumpTarget }, },
5707 { 775 /* bbit0 */, Mips::BBIT0, Convert__GPR64AsmReg1_0__ConstantUImm5_0_Report_UImm61_1__JumpTarget1_2, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0_Report_UImm6, MCK_JumpTarget }, },
5708 { 781 /* bbit032 */, Mips::BBIT032, Convert__GPR64AsmReg1_0__ConstantUImm5_01_1__JumpTarget1_2, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_JumpTarget }, },
5709 { 789 /* bbit1 */, Mips::BBIT132, Convert__GPR64AsmReg1_0__ConstantUImm5_32_Norm1_1__JumpTarget1_2, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_32_Norm, MCK_JumpTarget }, },
5710 { 789 /* bbit1 */, Mips::BBIT1, Convert__GPR64AsmReg1_0__ConstantUImm5_0_Report_UImm61_1__JumpTarget1_2, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0_Report_UImm6, MCK_JumpTarget }, },
5711 { 795 /* bbit132 */, Mips::BBIT132, Convert__GPR64AsmReg1_0__ConstantUImm5_01_1__JumpTarget1_2, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_JumpTarget }, },
5712 { 803 /* bc */, Mips::BC, Convert__JumpTarget1_0, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_JumpTarget }, },
5713 { 803 /* bc */, Mips::BC_MMR6, Convert__JumpTarget1_0, AMFBS_InMicroMips_HasMips32r6, { MCK_JumpTarget }, },
5714 { 806 /* bc16 */, Mips::BC16_MMR6, Convert__JumpTarget1_0, AMFBS_InMicroMips_HasMips32r6, { MCK_JumpTarget }, },
5715 { 811 /* bc1eqz */, Mips::BC1EQZ, Convert__FGR64AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_JumpTarget }, },
5716 { 818 /* bc1eqzc */, Mips::BC1EQZC_MMR6, Convert__FGR64AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_JumpTarget }, },
5717 { 826 /* bc1f */, Mips::BC1F, Convert__regFCC0__JumpTarget1_0, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_JumpTarget }, },
5718 { 826 /* bc1f */, Mips::BC1F_MM, Convert__regFCC0__JumpTarget1_0, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_JumpTarget }, },
5719 { 826 /* bc1f */, Mips::BC1F, Convert__FCCAsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_JumpTarget }, },
5720 { 826 /* bc1f */, Mips::BC1F_MM, Convert__FCCAsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_JumpTarget }, },
5721 { 831 /* bc1fl */, Mips::BC1FL, Convert__regFCC0__JumpTarget1_0, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_JumpTarget }, },
5722 { 831 /* bc1fl */, Mips::BC1FL, Convert__FCCAsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_JumpTarget }, },
5723 { 837 /* bc1nez */, Mips::BC1NEZ, Convert__FGR64AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_JumpTarget }, },
5724 { 844 /* bc1nezc */, Mips::BC1NEZC_MMR6, Convert__FGR64AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_JumpTarget }, },
5725 { 852 /* bc1t */, Mips::BC1T, Convert__regFCC0__JumpTarget1_0, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_JumpTarget }, },
5726 { 852 /* bc1t */, Mips::BC1T_MM, Convert__regFCC0__JumpTarget1_0, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_JumpTarget }, },
5727 { 852 /* bc1t */, Mips::BC1T, Convert__FCCAsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_JumpTarget }, },
5728 { 852 /* bc1t */, Mips::BC1T_MM, Convert__FCCAsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_JumpTarget }, },
5729 { 857 /* bc1tl */, Mips::BC1TL, Convert__regFCC0__JumpTarget1_0, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_JumpTarget }, },
5730 { 857 /* bc1tl */, Mips::BC1TL, Convert__FCCAsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_JumpTarget }, },
5731 { 863 /* bc2eqz */, Mips::BC2EQZ, Convert__COP2AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_COP2AsmReg, MCK_JumpTarget }, },
5732 { 870 /* bc2eqzc */, Mips::BC2EQZC_MMR6, Convert__COP2AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_COP2AsmReg, MCK_JumpTarget }, },
5733 { 878 /* bc2nez */, Mips::BC2NEZ, Convert__COP2AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_COP2AsmReg, MCK_JumpTarget }, },
5734 { 885 /* bc2nezc */, Mips::BC2NEZC_MMR6, Convert__COP2AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_COP2AsmReg, MCK_JumpTarget }, },
5735 { 893 /* bclr.b */, Mips::BCLR_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5736 { 900 /* bclr.d */, Mips::BCLR_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5737 { 907 /* bclr.h */, Mips::BCLR_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5738 { 914 /* bclr.w */, Mips::BCLR_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5739 { 921 /* bclri.b */, Mips::BCLRI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, },
5740 { 929 /* bclri.d */, Mips::BCLRI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, },
5741 { 937 /* bclri.h */, Mips::BCLRI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, },
5742 { 945 /* bclri.w */, Mips::BCLRI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
5743 { 953 /* beq */, Mips::BeqImm, Convert__GPR32AsmReg1_0__ConstantImm1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_ConstantImm, MCK_JumpTarget }, },
5744 { 953 /* beq */, Mips::BEQ, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5745 { 953 /* beq */, Mips::BEQ_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5746 { 957 /* beqc */, Mips::BEQC, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5747 { 957 /* beqc */, Mips::BEQC_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5748 { 957 /* beqc */, Mips::BEQC64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_JumpTarget }, },
5749 { 962 /* beql */, Mips::BEQLImmMacro, Convert__GPR32AsmReg1_0__ConstantImm1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_ConstantImm, MCK_JumpTarget }, },
5750 { 962 /* beql */, Mips::BEQL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5751 { 967 /* beqz */, Mips::BeqzRxImmX16, Convert__Reg1_0__JumpTarget1_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_JumpTarget }, },
5752 { 967 /* beqz */, Mips::BEQ, Convert__GPR32AsmReg1_0__regZERO__JumpTarget1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5753 { 967 /* beqz */, Mips::BEQ_MM, Convert__GPR32AsmReg1_0__regZERO__JumpTarget1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5754 { 967 /* beqz */, Mips::BeqzRxImm16, Convert__Reg1_0__JumpTarget1_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_JumpTarget, MCK__HASH_, MCK_16, MCK_bit, MCK_inst }, },
5755 { 972 /* beqz16 */, Mips::BEQZ16_MM, Convert__GPRMM16AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_JumpTarget }, },
5756 { 972 /* beqz16 */, Mips::BEQZC16_MMR6, Convert__GPRMM16AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_JumpTarget }, },
5757 { 979 /* beqzalc */, Mips::BEQZALC, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5758 { 979 /* beqzalc */, Mips::BEQZALC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5759 { 987 /* beqzc */, Mips::BEQZC, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5760 { 987 /* beqzc */, Mips::BEQZC_MM, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5761 { 987 /* beqzc */, Mips::BEQZC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5762 { 987 /* beqzc */, Mips::BEQZC64, Convert__GPR64AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6, { MCK_GPR64AsmReg, MCK_JumpTarget }, },
5763 { 993 /* beqzc16 */, Mips::BEQZC16_MMR6, Convert__GPRMM16AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_JumpTarget }, },
5764 { 1001 /* beqzl */, Mips::BEQL, Convert__GPR32AsmReg1_0__regZERO__JumpTarget1_1, AMFBS_HasStdEnc_HasMips2_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5765 { 1007 /* bge */, Mips::BGEImmMacro, Convert__GPR32AsmReg1_0__ConstantImm1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_ConstantImm, MCK_JumpTarget }, },
5766 { 1007 /* bge */, Mips::BGE, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5767 { 1011 /* bgec */, Mips::BGEC, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5768 { 1011 /* bgec */, Mips::BGEC_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5769 { 1011 /* bgec */, Mips::BGEC64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_JumpTarget }, },
5770 { 1016 /* bgel */, Mips::BGELImmMacro, Convert__GPR32AsmReg1_0__ConstantImm1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_ConstantImm, MCK_JumpTarget }, },
5771 { 1016 /* bgel */, Mips::BGEL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5772 { 1021 /* bgeu */, Mips::BGEUImmMacro, Convert__GPR32AsmReg1_0__ConstantImm1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_ConstantImm, MCK_JumpTarget }, },
5773 { 1021 /* bgeu */, Mips::BGEU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5774 { 1026 /* bgeuc */, Mips::BGEUC, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5775 { 1026 /* bgeuc */, Mips::BGEUC_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5776 { 1026 /* bgeuc */, Mips::BGEUC64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_JumpTarget }, },
5777 { 1032 /* bgeul */, Mips::BGEULImmMacro, Convert__GPR32AsmReg1_0__ConstantImm1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_ConstantImm, MCK_JumpTarget }, },
5778 { 1032 /* bgeul */, Mips::BGEUL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5779 { 1038 /* bgez */, Mips::BGEZ, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5780 { 1038 /* bgez */, Mips::BGEZ_MM, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5781 { 1043 /* bgezal */, Mips::BGEZAL, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5782 { 1043 /* bgezal */, Mips::BGEZAL_MM, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5783 { 1050 /* bgezalc */, Mips::BGEZALC, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5784 { 1050 /* bgezalc */, Mips::BGEZALC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5785 { 1058 /* bgezall */, Mips::BGEZALL, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5786 { 1066 /* bgezals */, Mips::BGEZALS_MM, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5787 { 1074 /* bgezc */, Mips::BGEZC, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5788 { 1074 /* bgezc */, Mips::BGEZC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5789 { 1074 /* bgezc */, Mips::BGEZC64, Convert__GPR64AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6, { MCK_GPR64AsmReg, MCK_JumpTarget }, },
5790 { 1080 /* bgezl */, Mips::BGEZL, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5791 { 1086 /* bgt */, Mips::BGTImmMacro, Convert__GPR32AsmReg1_0__ConstantImm1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_ConstantImm, MCK_JumpTarget }, },
5792 { 1086 /* bgt */, Mips::BGT, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5793 { 1090 /* bgtl */, Mips::BGTLImmMacro, Convert__GPR32AsmReg1_0__ConstantImm1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_ConstantImm, MCK_JumpTarget }, },
5794 { 1090 /* bgtl */, Mips::BGTL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5795 { 1095 /* bgtu */, Mips::BGTUImmMacro, Convert__GPR32AsmReg1_0__ConstantImm1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_ConstantImm, MCK_JumpTarget }, },
5796 { 1095 /* bgtu */, Mips::BGTU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5797 { 1100 /* bgtul */, Mips::BGTULImmMacro, Convert__GPR32AsmReg1_0__ConstantImm1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_ConstantImm, MCK_JumpTarget }, },
5798 { 1100 /* bgtul */, Mips::BGTUL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5799 { 1106 /* bgtz */, Mips::BGTZ, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5800 { 1106 /* bgtz */, Mips::BGTZ_MM, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5801 { 1111 /* bgtzalc */, Mips::BGTZALC, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5802 { 1111 /* bgtzalc */, Mips::BGTZALC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5803 { 1119 /* bgtzc */, Mips::BGTZC, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5804 { 1119 /* bgtzc */, Mips::BGTZC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5805 { 1119 /* bgtzc */, Mips::BGTZC64, Convert__GPR64AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6, { MCK_GPR64AsmReg, MCK_JumpTarget }, },
5806 { 1125 /* bgtzl */, Mips::BGTZL, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5807 { 1131 /* binsl.b */, Mips::BINSL_B, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5808 { 1139 /* binsl.d */, Mips::BINSL_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5809 { 1147 /* binsl.h */, Mips::BINSL_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5810 { 1155 /* binsl.w */, Mips::BINSL_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5811 { 1163 /* binsli.b */, Mips::BINSLI_B, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, },
5812 { 1172 /* binsli.d */, Mips::BINSLI_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm6_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, },
5813 { 1181 /* binsli.h */, Mips::BINSLI_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm4_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, },
5814 { 1190 /* binsli.w */, Mips::BINSLI_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
5815 { 1199 /* binsr.b */, Mips::BINSR_B, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5816 { 1207 /* binsr.d */, Mips::BINSR_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5817 { 1215 /* binsr.h */, Mips::BINSR_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5818 { 1223 /* binsr.w */, Mips::BINSR_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5819 { 1231 /* binsri.b */, Mips::BINSRI_B, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, },
5820 { 1240 /* binsri.d */, Mips::BINSRI_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm6_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, },
5821 { 1249 /* binsri.h */, Mips::BINSRI_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm4_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, },
5822 { 1258 /* binsri.w */, Mips::BINSRI_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
5823 { 1267 /* bitrev */, Mips::BITREV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5824 { 1267 /* bitrev */, Mips::BITREV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5825 { 1274 /* bitswap */, Mips::BITSWAP, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5826 { 1274 /* bitswap */, Mips::BITSWAP_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5827 { 1282 /* ble */, Mips::BLEImmMacro, Convert__GPR32AsmReg1_0__ConstantImm1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_ConstantImm, MCK_JumpTarget }, },
5828 { 1282 /* ble */, Mips::BLE, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5829 { 1286 /* blel */, Mips::BLELImmMacro, Convert__GPR32AsmReg1_0__ConstantImm1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_ConstantImm, MCK_JumpTarget }, },
5830 { 1286 /* blel */, Mips::BLEL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5831 { 1291 /* bleu */, Mips::BLEUImmMacro, Convert__GPR32AsmReg1_0__ConstantImm1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_ConstantImm, MCK_JumpTarget }, },
5832 { 1291 /* bleu */, Mips::BLEU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5833 { 1296 /* bleul */, Mips::BLEULImmMacro, Convert__GPR32AsmReg1_0__ConstantImm1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_ConstantImm, MCK_JumpTarget }, },
5834 { 1296 /* bleul */, Mips::BLEUL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5835 { 1302 /* blez */, Mips::BLEZ, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5836 { 1302 /* blez */, Mips::BLEZ_MM, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5837 { 1307 /* blezalc */, Mips::BLEZALC, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5838 { 1307 /* blezalc */, Mips::BLEZALC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5839 { 1315 /* blezc */, Mips::BLEZC, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5840 { 1315 /* blezc */, Mips::BLEZC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5841 { 1315 /* blezc */, Mips::BLEZC64, Convert__GPR64AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6, { MCK_GPR64AsmReg, MCK_JumpTarget }, },
5842 { 1321 /* blezl */, Mips::BLEZL, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5843 { 1327 /* blt */, Mips::BLTImmMacro, Convert__GPR32AsmReg1_0__ConstantImm1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_ConstantImm, MCK_JumpTarget }, },
5844 { 1327 /* blt */, Mips::BLT, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5845 { 1331 /* bltc */, Mips::BLTC, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5846 { 1331 /* bltc */, Mips::BLTC_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5847 { 1331 /* bltc */, Mips::BLTC64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_JumpTarget }, },
5848 { 1336 /* bltl */, Mips::BLTLImmMacro, Convert__GPR32AsmReg1_0__ConstantImm1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_ConstantImm, MCK_JumpTarget }, },
5849 { 1336 /* bltl */, Mips::BLTL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5850 { 1341 /* bltu */, Mips::BLTUImmMacro, Convert__GPR32AsmReg1_0__ConstantImm1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_ConstantImm, MCK_JumpTarget }, },
5851 { 1341 /* bltu */, Mips::BLTU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5852 { 1346 /* bltuc */, Mips::BLTUC, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5853 { 1346 /* bltuc */, Mips::BLTUC_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5854 { 1346 /* bltuc */, Mips::BLTUC64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_JumpTarget }, },
5855 { 1352 /* bltul */, Mips::BLTULImmMacro, Convert__GPR32AsmReg1_0__ConstantImm1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_ConstantImm, MCK_JumpTarget }, },
5856 { 1352 /* bltul */, Mips::BLTUL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5857 { 1358 /* bltz */, Mips::BLTZ, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5858 { 1358 /* bltz */, Mips::BLTZ_MM, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5859 { 1363 /* bltzal */, Mips::BLTZAL, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5860 { 1363 /* bltzal */, Mips::BLTZAL_MM, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5861 { 1370 /* bltzalc */, Mips::BLTZALC, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5862 { 1370 /* bltzalc */, Mips::BLTZALC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5863 { 1378 /* bltzall */, Mips::BLTZALL, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5864 { 1386 /* bltzals */, Mips::BLTZALS_MM, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5865 { 1394 /* bltzc */, Mips::BLTZC, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5866 { 1394 /* bltzc */, Mips::BLTZC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5867 { 1394 /* bltzc */, Mips::BLTZC64, Convert__GPR64AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6, { MCK_GPR64AsmReg, MCK_JumpTarget }, },
5868 { 1400 /* bltzl */, Mips::BLTZL, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5869 { 1406 /* bmnz.v */, Mips::BMNZ_V, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5870 { 1413 /* bmnzi.b */, Mips::BMNZI_B, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm8_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm8_0 }, },
5871 { 1421 /* bmz.v */, Mips::BMZ_V, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5872 { 1427 /* bmzi.b */, Mips::BMZI_B, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm8_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm8_0 }, },
5873 { 1434 /* bne */, Mips::BneImm, Convert__GPR32AsmReg1_0__ConstantImm1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_ConstantImm, MCK_JumpTarget }, },
5874 { 1434 /* bne */, Mips::BNE, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5875 { 1434 /* bne */, Mips::BNE_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5876 { 1438 /* bnec */, Mips::BNEC, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5877 { 1438 /* bnec */, Mips::BNEC_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5878 { 1438 /* bnec */, Mips::BNEC64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_JumpTarget }, },
5879 { 1443 /* bneg.b */, Mips::BNEG_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5880 { 1450 /* bneg.d */, Mips::BNEG_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5881 { 1457 /* bneg.h */, Mips::BNEG_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5882 { 1464 /* bneg.w */, Mips::BNEG_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5883 { 1471 /* bnegi.b */, Mips::BNEGI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, },
5884 { 1479 /* bnegi.d */, Mips::BNEGI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, },
5885 { 1487 /* bnegi.h */, Mips::BNEGI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, },
5886 { 1495 /* bnegi.w */, Mips::BNEGI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
5887 { 1503 /* bnel */, Mips::BNELImmMacro, Convert__GPR32AsmReg1_0__ConstantImm1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_ConstantImm, MCK_JumpTarget }, },
5888 { 1503 /* bnel */, Mips::BNEL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5889 { 1508 /* bnez */, Mips::BnezRxImmX16, Convert__Reg1_0__JumpTarget1_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_JumpTarget }, },
5890 { 1508 /* bnez */, Mips::BNE, Convert__GPR32AsmReg1_0__regZERO__JumpTarget1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5891 { 1508 /* bnez */, Mips::BNE_MM, Convert__GPR32AsmReg1_0__regZERO__JumpTarget1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5892 { 1508 /* bnez */, Mips::BnezRxImm16, Convert__Reg1_0__JumpTarget1_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_JumpTarget, MCK__HASH_, MCK_16, MCK_bit, MCK_inst }, },
5893 { 1513 /* bnez16 */, Mips::BNEZ16_MM, Convert__GPRMM16AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_JumpTarget }, },
5894 { 1513 /* bnez16 */, Mips::BNEZC16_MMR6, Convert__GPRMM16AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_JumpTarget }, },
5895 { 1520 /* bnezalc */, Mips::BNEZALC, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5896 { 1520 /* bnezalc */, Mips::BNEZALC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5897 { 1528 /* bnezc */, Mips::BNEZC, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5898 { 1528 /* bnezc */, Mips::BNEZC_MM, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5899 { 1528 /* bnezc */, Mips::BNEZC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5900 { 1528 /* bnezc */, Mips::BNEZC64, Convert__GPR64AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6, { MCK_GPR64AsmReg, MCK_JumpTarget }, },
5901 { 1534 /* bnezc16 */, Mips::BNEZC16_MMR6, Convert__GPRMM16AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_JumpTarget }, },
5902 { 1542 /* bnezl */, Mips::BNEL, Convert__GPR32AsmReg1_0__regZERO__JumpTarget1_1, AMFBS_HasStdEnc_HasMips2_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5903 { 1548 /* bnvc */, Mips::BNVC, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5904 { 1548 /* bnvc */, Mips::BNVC_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5905 { 1553 /* bnz.b */, Mips::BNZ_B, Convert__MSA128AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_JumpTarget }, },
5906 { 1559 /* bnz.d */, Mips::BNZ_D, Convert__MSA128AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_JumpTarget }, },
5907 { 1565 /* bnz.h */, Mips::BNZ_H, Convert__MSA128AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_JumpTarget }, },
5908 { 1571 /* bnz.v */, Mips::BNZ_V, Convert__MSA128AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_JumpTarget }, },
5909 { 1577 /* bnz.w */, Mips::BNZ_W, Convert__MSA128AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_JumpTarget }, },
5910 { 1583 /* bovc */, Mips::BOVC, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5911 { 1583 /* bovc */, Mips::BOVC_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5912 { 1588 /* bposge32 */, Mips::BPOSGE32_MM, Convert__JumpTarget1_0, AMFBS_InMicroMips_NotMips32r6_HasDSP, { MCK_JumpTarget }, },
5913 { 1588 /* bposge32 */, Mips::BPOSGE32, Convert__JumpTarget1_0, AMFBS_HasDSP_NotInMicroMips, { MCK_JumpTarget }, },
5914 { 1597 /* bposge32c */, Mips::BPOSGE32C_MMR3, Convert__JumpTarget1_0, AMFBS_InMicroMips_HasDSPR3, { MCK_JumpTarget }, },
5915 { 1607 /* break */, Mips::BREAK, Convert__imm_95_0__imm_95_0, AMFBS_HasStdEnc_NotInMicroMips, { }, },
5916 { 1607 /* break */, Mips::BREAK_MM, Convert__imm_95_0__imm_95_0, AMFBS_InMicroMips, { }, },
5917 { 1607 /* break */, Mips::Break16, Convert_NoOperands, AMFBS_InMips16Mode, { MCK_0 }, },
5918 { 1607 /* break */, Mips::BREAK, Convert__ConstantUImm10_01_0__imm_95_0, AMFBS_HasStdEnc_NotInMicroMips, { MCK_ConstantUImm10_0 }, },
5919 { 1607 /* break */, Mips::BREAK_MM, Convert__ConstantUImm10_01_0__imm_95_0, AMFBS_InMicroMips, { MCK_ConstantUImm10_0 }, },
5920 { 1607 /* break */, Mips::BREAK, Convert__ConstantUImm10_01_0__ConstantUImm10_01_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_ConstantUImm10_0, MCK_ConstantUImm10_0 }, },
5921 { 1607 /* break */, Mips::BREAK_MMR6, Convert__ConstantUImm10_01_0__ConstantUImm10_01_1, AMFBS_InMicroMips_HasMips32r6, { MCK_ConstantUImm10_0, MCK_ConstantUImm10_0 }, },
5922 { 1607 /* break */, Mips::BREAK_MM, Convert__ConstantUImm10_01_0__ConstantUImm10_01_1, AMFBS_InMicroMips, { MCK_ConstantUImm10_0, MCK_ConstantUImm10_0 }, },
5923 { 1613 /* break16 */, Mips::BREAK16_MM, Convert__ConstantUImm4_01_0, AMFBS_InMicroMips_NotMips32r6, { MCK_ConstantUImm4_0 }, },
5924 { 1613 /* break16 */, Mips::BREAK16_MMR6, Convert__ConstantUImm4_01_0, AMFBS_InMicroMips_HasMips32r6, { MCK_ConstantUImm4_0 }, },
5925 { 1621 /* bsel.v */, Mips::BSEL_V, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5926 { 1628 /* bseli.b */, Mips::BSELI_B, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm8_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm8_0 }, },
5927 { 1636 /* bset.b */, Mips::BSET_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5928 { 1643 /* bset.d */, Mips::BSET_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5929 { 1650 /* bset.h */, Mips::BSET_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5930 { 1657 /* bset.w */, Mips::BSET_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5931 { 1664 /* bseti.b */, Mips::BSETI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, },
5932 { 1672 /* bseti.d */, Mips::BSETI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, },
5933 { 1680 /* bseti.h */, Mips::BSETI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, },
5934 { 1688 /* bseti.w */, Mips::BSETI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
5935 { 1696 /* bteqz */, Mips::BteqzX16, Convert__SImm161_0, AMFBS_InMips16Mode, { MCK_SImm16 }, },
5936 { 1696 /* bteqz */, Mips::Bteqz16, Convert__SImm161_0, AMFBS_InMips16Mode, { MCK_SImm16, MCK__HASH_, MCK_16, MCK_bit, MCK_inst }, },
5937 { 1702 /* btnez */, Mips::BtnezX16, Convert__SImm161_0, AMFBS_InMips16Mode, { MCK_SImm16 }, },
5938 { 1702 /* btnez */, Mips::Btnez16, Convert__SImm161_0, AMFBS_InMips16Mode, { MCK_SImm16, MCK__HASH_, MCK_16, MCK_bit, MCK_inst }, },
5939 { 1708 /* bz.b */, Mips::BZ_B, Convert__MSA128AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_JumpTarget }, },
5940 { 1713 /* bz.d */, Mips::BZ_D, Convert__MSA128AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_JumpTarget }, },
5941 { 1718 /* bz.h */, Mips::BZ_H, Convert__MSA128AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_JumpTarget }, },
5942 { 1723 /* bz.v */, Mips::BZ_V, Convert__MSA128AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_JumpTarget }, },
5943 { 1728 /* bz.w */, Mips::BZ_W, Convert__MSA128AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_JumpTarget }, },
5944 { 1733 /* c.eq.d */, Mips::C_EQ_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5945 { 1733 /* c.eq.d */, Mips::C_EQ_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5946 { 1733 /* c.eq.d */, Mips::C_EQ_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5947 { 1733 /* c.eq.d */, Mips::C_EQ_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5948 { 1733 /* c.eq.d */, Mips::C_EQ_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5949 { 1733 /* c.eq.d */, Mips::C_EQ_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5950 { 1733 /* c.eq.d */, Mips::C_EQ_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5951 { 1733 /* c.eq.d */, Mips::C_EQ_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5952 { 1740 /* c.eq.s */, Mips::C_EQ_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5953 { 1740 /* c.eq.s */, Mips::C_EQ_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5954 { 1740 /* c.eq.s */, Mips::C_EQ_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5955 { 1740 /* c.eq.s */, Mips::C_EQ_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5956 { 1747 /* c.f.d */, Mips::C_F_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5957 { 1747 /* c.f.d */, Mips::C_F_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5958 { 1747 /* c.f.d */, Mips::C_F_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5959 { 1747 /* c.f.d */, Mips::C_F_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5960 { 1747 /* c.f.d */, Mips::C_F_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5961 { 1747 /* c.f.d */, Mips::C_F_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5962 { 1747 /* c.f.d */, Mips::C_F_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5963 { 1747 /* c.f.d */, Mips::C_F_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5964 { 1753 /* c.f.s */, Mips::C_F_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5965 { 1753 /* c.f.s */, Mips::C_F_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5966 { 1753 /* c.f.s */, Mips::C_F_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5967 { 1753 /* c.f.s */, Mips::C_F_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5968 { 1759 /* c.le.d */, Mips::C_LE_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5969 { 1759 /* c.le.d */, Mips::C_LE_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5970 { 1759 /* c.le.d */, Mips::C_LE_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5971 { 1759 /* c.le.d */, Mips::C_LE_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5972 { 1759 /* c.le.d */, Mips::C_LE_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5973 { 1759 /* c.le.d */, Mips::C_LE_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5974 { 1759 /* c.le.d */, Mips::C_LE_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5975 { 1759 /* c.le.d */, Mips::C_LE_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5976 { 1766 /* c.le.s */, Mips::C_LE_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5977 { 1766 /* c.le.s */, Mips::C_LE_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5978 { 1766 /* c.le.s */, Mips::C_LE_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5979 { 1766 /* c.le.s */, Mips::C_LE_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5980 { 1773 /* c.lt.d */, Mips::C_LT_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5981 { 1773 /* c.lt.d */, Mips::C_LT_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5982 { 1773 /* c.lt.d */, Mips::C_LT_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5983 { 1773 /* c.lt.d */, Mips::C_LT_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5984 { 1773 /* c.lt.d */, Mips::C_LT_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5985 { 1773 /* c.lt.d */, Mips::C_LT_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5986 { 1773 /* c.lt.d */, Mips::C_LT_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5987 { 1773 /* c.lt.d */, Mips::C_LT_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5988 { 1780 /* c.lt.s */, Mips::C_LT_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5989 { 1780 /* c.lt.s */, Mips::C_LT_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5990 { 1780 /* c.lt.s */, Mips::C_LT_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5991 { 1780 /* c.lt.s */, Mips::C_LT_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5992 { 1787 /* c.nge.d */, Mips::C_NGE_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5993 { 1787 /* c.nge.d */, Mips::C_NGE_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5994 { 1787 /* c.nge.d */, Mips::C_NGE_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5995 { 1787 /* c.nge.d */, Mips::C_NGE_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5996 { 1787 /* c.nge.d */, Mips::C_NGE_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5997 { 1787 /* c.nge.d */, Mips::C_NGE_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5998 { 1787 /* c.nge.d */, Mips::C_NGE_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5999 { 1787 /* c.nge.d */, Mips::C_NGE_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6000 { 1795 /* c.nge.s */, Mips::C_NGE_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6001 { 1795 /* c.nge.s */, Mips::C_NGE_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6002 { 1795 /* c.nge.s */, Mips::C_NGE_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6003 { 1795 /* c.nge.s */, Mips::C_NGE_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6004 { 1803 /* c.ngl.d */, Mips::C_NGL_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6005 { 1803 /* c.ngl.d */, Mips::C_NGL_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6006 { 1803 /* c.ngl.d */, Mips::C_NGL_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6007 { 1803 /* c.ngl.d */, Mips::C_NGL_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6008 { 1803 /* c.ngl.d */, Mips::C_NGL_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6009 { 1803 /* c.ngl.d */, Mips::C_NGL_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6010 { 1803 /* c.ngl.d */, Mips::C_NGL_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6011 { 1803 /* c.ngl.d */, Mips::C_NGL_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6012 { 1811 /* c.ngl.s */, Mips::C_NGL_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6013 { 1811 /* c.ngl.s */, Mips::C_NGL_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6014 { 1811 /* c.ngl.s */, Mips::C_NGL_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6015 { 1811 /* c.ngl.s */, Mips::C_NGL_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6016 { 1819 /* c.ngle.d */, Mips::C_NGLE_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6017 { 1819 /* c.ngle.d */, Mips::C_NGLE_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6018 { 1819 /* c.ngle.d */, Mips::C_NGLE_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6019 { 1819 /* c.ngle.d */, Mips::C_NGLE_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6020 { 1819 /* c.ngle.d */, Mips::C_NGLE_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6021 { 1819 /* c.ngle.d */, Mips::C_NGLE_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6022 { 1819 /* c.ngle.d */, Mips::C_NGLE_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6023 { 1819 /* c.ngle.d */, Mips::C_NGLE_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6024 { 1828 /* c.ngle.s */, Mips::C_NGLE_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6025 { 1828 /* c.ngle.s */, Mips::C_NGLE_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6026 { 1828 /* c.ngle.s */, Mips::C_NGLE_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6027 { 1828 /* c.ngle.s */, Mips::C_NGLE_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6028 { 1837 /* c.ngt.d */, Mips::C_NGT_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6029 { 1837 /* c.ngt.d */, Mips::C_NGT_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6030 { 1837 /* c.ngt.d */, Mips::C_NGT_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6031 { 1837 /* c.ngt.d */, Mips::C_NGT_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6032 { 1837 /* c.ngt.d */, Mips::C_NGT_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6033 { 1837 /* c.ngt.d */, Mips::C_NGT_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6034 { 1837 /* c.ngt.d */, Mips::C_NGT_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6035 { 1837 /* c.ngt.d */, Mips::C_NGT_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6036 { 1845 /* c.ngt.s */, Mips::C_NGT_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6037 { 1845 /* c.ngt.s */, Mips::C_NGT_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6038 { 1845 /* c.ngt.s */, Mips::C_NGT_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6039 { 1845 /* c.ngt.s */, Mips::C_NGT_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6040 { 1853 /* c.ole.d */, Mips::C_OLE_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6041 { 1853 /* c.ole.d */, Mips::C_OLE_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6042 { 1853 /* c.ole.d */, Mips::C_OLE_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6043 { 1853 /* c.ole.d */, Mips::C_OLE_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6044 { 1853 /* c.ole.d */, Mips::C_OLE_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6045 { 1853 /* c.ole.d */, Mips::C_OLE_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6046 { 1853 /* c.ole.d */, Mips::C_OLE_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6047 { 1853 /* c.ole.d */, Mips::C_OLE_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6048 { 1861 /* c.ole.s */, Mips::C_OLE_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6049 { 1861 /* c.ole.s */, Mips::C_OLE_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6050 { 1861 /* c.ole.s */, Mips::C_OLE_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6051 { 1861 /* c.ole.s */, Mips::C_OLE_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6052 { 1869 /* c.olt.d */, Mips::C_OLT_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6053 { 1869 /* c.olt.d */, Mips::C_OLT_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6054 { 1869 /* c.olt.d */, Mips::C_OLT_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6055 { 1869 /* c.olt.d */, Mips::C_OLT_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6056 { 1869 /* c.olt.d */, Mips::C_OLT_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6057 { 1869 /* c.olt.d */, Mips::C_OLT_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6058 { 1869 /* c.olt.d */, Mips::C_OLT_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6059 { 1869 /* c.olt.d */, Mips::C_OLT_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6060 { 1877 /* c.olt.s */, Mips::C_OLT_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6061 { 1877 /* c.olt.s */, Mips::C_OLT_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6062 { 1877 /* c.olt.s */, Mips::C_OLT_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6063 { 1877 /* c.olt.s */, Mips::C_OLT_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6064 { 1885 /* c.seq.d */, Mips::C_SEQ_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6065 { 1885 /* c.seq.d */, Mips::C_SEQ_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6066 { 1885 /* c.seq.d */, Mips::C_SEQ_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6067 { 1885 /* c.seq.d */, Mips::C_SEQ_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6068 { 1885 /* c.seq.d */, Mips::C_SEQ_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6069 { 1885 /* c.seq.d */, Mips::C_SEQ_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6070 { 1885 /* c.seq.d */, Mips::C_SEQ_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6071 { 1885 /* c.seq.d */, Mips::C_SEQ_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6072 { 1893 /* c.seq.s */, Mips::C_SEQ_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6073 { 1893 /* c.seq.s */, Mips::C_SEQ_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6074 { 1893 /* c.seq.s */, Mips::C_SEQ_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6075 { 1893 /* c.seq.s */, Mips::C_SEQ_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6076 { 1901 /* c.sf.d */, Mips::C_SF_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6077 { 1901 /* c.sf.d */, Mips::C_SF_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6078 { 1901 /* c.sf.d */, Mips::C_SF_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6079 { 1901 /* c.sf.d */, Mips::C_SF_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6080 { 1901 /* c.sf.d */, Mips::C_SF_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6081 { 1901 /* c.sf.d */, Mips::C_SF_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6082 { 1901 /* c.sf.d */, Mips::C_SF_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6083 { 1901 /* c.sf.d */, Mips::C_SF_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6084 { 1908 /* c.sf.s */, Mips::C_SF_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6085 { 1908 /* c.sf.s */, Mips::C_SF_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6086 { 1908 /* c.sf.s */, Mips::C_SF_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6087 { 1908 /* c.sf.s */, Mips::C_SF_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6088 { 1915 /* c.ueq.d */, Mips::C_UEQ_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6089 { 1915 /* c.ueq.d */, Mips::C_UEQ_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6090 { 1915 /* c.ueq.d */, Mips::C_UEQ_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6091 { 1915 /* c.ueq.d */, Mips::C_UEQ_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6092 { 1915 /* c.ueq.d */, Mips::C_UEQ_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6093 { 1915 /* c.ueq.d */, Mips::C_UEQ_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6094 { 1915 /* c.ueq.d */, Mips::C_UEQ_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6095 { 1915 /* c.ueq.d */, Mips::C_UEQ_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6096 { 1923 /* c.ueq.s */, Mips::C_UEQ_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6097 { 1923 /* c.ueq.s */, Mips::C_UEQ_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6098 { 1923 /* c.ueq.s */, Mips::C_UEQ_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6099 { 1923 /* c.ueq.s */, Mips::C_UEQ_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6100 { 1931 /* c.ule.d */, Mips::C_ULE_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6101 { 1931 /* c.ule.d */, Mips::C_ULE_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6102 { 1931 /* c.ule.d */, Mips::C_ULE_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6103 { 1931 /* c.ule.d */, Mips::C_ULE_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6104 { 1931 /* c.ule.d */, Mips::C_ULE_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6105 { 1931 /* c.ule.d */, Mips::C_ULE_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6106 { 1931 /* c.ule.d */, Mips::C_ULE_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6107 { 1931 /* c.ule.d */, Mips::C_ULE_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6108 { 1939 /* c.ule.s */, Mips::C_ULE_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6109 { 1939 /* c.ule.s */, Mips::C_ULE_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6110 { 1939 /* c.ule.s */, Mips::C_ULE_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6111 { 1939 /* c.ule.s */, Mips::C_ULE_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6112 { 1947 /* c.ult.d */, Mips::C_ULT_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6113 { 1947 /* c.ult.d */, Mips::C_ULT_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6114 { 1947 /* c.ult.d */, Mips::C_ULT_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6115 { 1947 /* c.ult.d */, Mips::C_ULT_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6116 { 1947 /* c.ult.d */, Mips::C_ULT_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6117 { 1947 /* c.ult.d */, Mips::C_ULT_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6118 { 1947 /* c.ult.d */, Mips::C_ULT_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6119 { 1947 /* c.ult.d */, Mips::C_ULT_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6120 { 1955 /* c.ult.s */, Mips::C_ULT_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6121 { 1955 /* c.ult.s */, Mips::C_ULT_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6122 { 1955 /* c.ult.s */, Mips::C_ULT_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6123 { 1955 /* c.ult.s */, Mips::C_ULT_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6124 { 1963 /* c.un.d */, Mips::C_UN_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6125 { 1963 /* c.un.d */, Mips::C_UN_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6126 { 1963 /* c.un.d */, Mips::C_UN_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6127 { 1963 /* c.un.d */, Mips::C_UN_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6128 { 1963 /* c.un.d */, Mips::C_UN_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6129 { 1963 /* c.un.d */, Mips::C_UN_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6130 { 1963 /* c.un.d */, Mips::C_UN_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6131 { 1963 /* c.un.d */, Mips::C_UN_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6132 { 1970 /* c.un.s */, Mips::C_UN_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6133 { 1970 /* c.un.s */, Mips::C_UN_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6134 { 1970 /* c.un.s */, Mips::C_UN_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6135 { 1970 /* c.un.s */, Mips::C_UN_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6136 { 1977 /* cache */, Mips::CACHE_R6, Convert__MemOffsetSimm9_02_1__ConstantUImm5_01_0, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_ConstantUImm5_0, MCK_MemOffsetSimm9_0 }, },
6137 { 1977 /* cache */, Mips::CACHE, Convert__Mem2_1__ConstantUImm5_01_0, AMFBS_HasStdEnc_HasMips3_32_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_ConstantUImm5_0, MCK_Mem }, },
6138 { 1977 /* cache */, Mips::CACHE_MM, Convert__Mem2_1__ConstantUImm5_01_0, AMFBS_InMicroMips_NotMips32r6, { MCK_ConstantUImm5_0, MCK_Mem }, },
6139 { 1977 /* cache */, Mips::CACHE_MMR6, Convert__Mem2_1__ConstantUImm5_01_0, AMFBS_InMicroMips_HasMips32r6, { MCK_ConstantUImm5_0, MCK_Mem }, },
6140 { 1983 /* cachee */, Mips::CACHEE, Convert__MemOffsetSimm9_02_1__ConstantUImm5_01_0, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, { MCK_ConstantUImm5_0, MCK_MemOffsetSimm9_0 }, },
6141 { 1983 /* cachee */, Mips::CACHEE_MM, Convert__MemOffsetSimm9_02_1__ConstantUImm5_01_0, AMFBS_InMicroMips_HasEVA, { MCK_ConstantUImm5_0, MCK_MemOffsetSimm9_0 }, },
6142 { 1990 /* ceil.l.d */, Mips::CEIL_L_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips3_32_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6143 { 1990 /* ceil.l.d */, Mips::CEIL_L_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6144 { 1999 /* ceil.l.s */, Mips::CEIL_L_S, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, },
6145 { 1999 /* ceil.l.s */, Mips::CEIL_L_S_MMR6, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, },
6146 { 2008 /* ceil.w.d */, Mips::CEIL_W_D32, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, },
6147 { 2008 /* ceil.w.d */, Mips::CEIL_W_MM, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, },
6148 { 2008 /* ceil.w.d */, Mips::CEIL_W_D_MMR6, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, },
6149 { 2008 /* ceil.w.d */, Mips::CEIL_W_D64, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg }, },
6150 { 2017 /* ceil.w.s */, Mips::CEIL_W_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_HasMips2_NotR5900_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6151 { 2017 /* ceil.w.s */, Mips::CEIL_W_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6152 { 2017 /* ceil.w.s */, Mips::CEIL_W_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6153 { 2026 /* ceq.b */, Mips::CEQ_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6154 { 2032 /* ceq.d */, Mips::CEQ_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6155 { 2038 /* ceq.h */, Mips::CEQ_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6156 { 2044 /* ceq.w */, Mips::CEQ_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6157 { 2050 /* ceqi.b */, Mips::CEQI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
6158 { 2057 /* ceqi.d */, Mips::CEQI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
6159 { 2064 /* ceqi.h */, Mips::CEQI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
6160 { 2071 /* ceqi.w */, Mips::CEQI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
6161 { 2078 /* cfc1 */, Mips::CFC1, Convert__GPR32AsmReg1_0__CCRAsmReg1_1, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, { MCK_GPR32AsmReg, MCK_CCRAsmReg }, },
6162 { 2078 /* cfc1 */, Mips::CFC1_MM, Convert__GPR32AsmReg1_0__CCRAsmReg1_1, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_CCRAsmReg }, },
6163 { 2083 /* cfc2 */, Mips::CFC2_MM, Convert__GPR32AsmReg1_0__COP2AsmReg1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_COP2AsmReg }, },
6164 { 2088 /* cfcmsa */, Mips::CFCMSA, Convert__GPR32AsmReg1_0__MSACtrlAsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_GPR32AsmReg, MCK_MSACtrlAsmReg }, },
6165 { 2095 /* cftc1 */, Mips::CFTC1, Convert__GPR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasMT, { MCK_GPR32AsmReg, MCK_FGR32AsmReg }, },
6166 { 2101 /* cins */, Mips::CINS, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1__ConstantUImm5_01_2, AMFBS_HasMips64_HasCnMips_NotInMicroMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_0 }, },
6167 { 2101 /* cins */, Mips::CINS32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_32_Norm1_1__ConstantUImm5_01_2, AMFBS_HasMips64_HasCnMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_32_Norm, MCK_ConstantUImm5_0 }, },
6168 { 2101 /* cins */, Mips::CINS, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_01_3, AMFBS_HasMips64_HasCnMips_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_0 }, },
6169 { 2101 /* cins */, Mips::CINS32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_32_Norm1_2__ConstantUImm5_01_3, AMFBS_HasMips64_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_32_Norm, MCK_ConstantUImm5_0 }, },
6170 { 2106 /* cins32 */, Mips::CINS32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1__ConstantUImm5_01_2, AMFBS_HasMips64_HasCnMips_NotInMicroMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_0 }, },
6171 { 2106 /* cins32 */, Mips::CINS32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_01_3, AMFBS_HasMips64_HasCnMips_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_0 }, },
6172 { 2113 /* class.d */, Mips::CLASS_D, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6173 { 2113 /* class.d */, Mips::CLASS_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6174 { 2121 /* class.s */, Mips::CLASS_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6175 { 2121 /* class.s */, Mips::CLASS_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6176 { 2129 /* cle_s.b */, Mips::CLE_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6177 { 2137 /* cle_s.d */, Mips::CLE_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6178 { 2145 /* cle_s.h */, Mips::CLE_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6179 { 2153 /* cle_s.w */, Mips::CLE_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6180 { 2161 /* cle_u.b */, Mips::CLE_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6181 { 2169 /* cle_u.d */, Mips::CLE_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6182 { 2177 /* cle_u.h */, Mips::CLE_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6183 { 2185 /* cle_u.w */, Mips::CLE_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6184 { 2193 /* clei_s.b */, Mips::CLEI_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
6185 { 2202 /* clei_s.d */, Mips::CLEI_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
6186 { 2211 /* clei_s.h */, Mips::CLEI_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
6187 { 2220 /* clei_s.w */, Mips::CLEI_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
6188 { 2229 /* clei_u.b */, Mips::CLEI_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
6189 { 2238 /* clei_u.d */, Mips::CLEI_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
6190 { 2247 /* clei_u.h */, Mips::CLEI_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
6191 { 2256 /* clei_u.w */, Mips::CLEI_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
6192 { 2265 /* clo */, Mips::CLO, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6193 { 2265 /* clo */, Mips::CLO_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6194 { 2265 /* clo */, Mips::CLO_R6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6195 { 2265 /* clo */, Mips::CLO_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6196 { 2269 /* clt_s.b */, Mips::CLT_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6197 { 2277 /* clt_s.d */, Mips::CLT_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6198 { 2285 /* clt_s.h */, Mips::CLT_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6199 { 2293 /* clt_s.w */, Mips::CLT_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6200 { 2301 /* clt_u.b */, Mips::CLT_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6201 { 2309 /* clt_u.d */, Mips::CLT_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6202 { 2317 /* clt_u.h */, Mips::CLT_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6203 { 2325 /* clt_u.w */, Mips::CLT_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6204 { 2333 /* clti_s.b */, Mips::CLTI_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
6205 { 2342 /* clti_s.d */, Mips::CLTI_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
6206 { 2351 /* clti_s.h */, Mips::CLTI_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
6207 { 2360 /* clti_s.w */, Mips::CLTI_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
6208 { 2369 /* clti_u.b */, Mips::CLTI_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
6209 { 2378 /* clti_u.d */, Mips::CLTI_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
6210 { 2387 /* clti_u.h */, Mips::CLTI_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
6211 { 2396 /* clti_u.w */, Mips::CLTI_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
6212 { 2405 /* clz */, Mips::CLZ, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6213 { 2405 /* clz */, Mips::CLZ_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6214 { 2405 /* clz */, Mips::CLZ_R6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6215 { 2405 /* clz */, Mips::CLZ_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6216 { 2409 /* cmp */, Mips::CmpRxRy16, Convert__Reg1_0__Reg1_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs }, },
6217 { 2413 /* cmp.af.d */, Mips::CMP_F_D, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6218 { 2413 /* cmp.af.d */, Mips::CMP_AF_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6219 { 2422 /* cmp.af.s */, Mips::CMP_F_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6220 { 2422 /* cmp.af.s */, Mips::CMP_AF_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6221 { 2431 /* cmp.eq.d */, Mips::CMP_EQ_D, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6222 { 2431 /* cmp.eq.d */, Mips::CMP_EQ_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6223 { 2440 /* cmp.eq.ph */, Mips::CMP_EQ_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6224 { 2440 /* cmp.eq.ph */, Mips::CMP_EQ_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6225 { 2450 /* cmp.eq.s */, Mips::CMP_EQ_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6226 { 2450 /* cmp.eq.s */, Mips::CMP_EQ_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6227 { 2459 /* cmp.le.d */, Mips::CMP_LE_D, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6228 { 2459 /* cmp.le.d */, Mips::CMP_LE_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6229 { 2468 /* cmp.le.ph */, Mips::CMP_LE_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6230 { 2468 /* cmp.le.ph */, Mips::CMP_LE_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6231 { 2478 /* cmp.le.s */, Mips::CMP_LE_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6232 { 2478 /* cmp.le.s */, Mips::CMP_LE_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6233 { 2487 /* cmp.lt.d */, Mips::CMP_LT_D, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6234 { 2487 /* cmp.lt.d */, Mips::CMP_LT_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6235 { 2496 /* cmp.lt.ph */, Mips::CMP_LT_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6236 { 2496 /* cmp.lt.ph */, Mips::CMP_LT_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6237 { 2506 /* cmp.lt.s */, Mips::CMP_LT_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6238 { 2506 /* cmp.lt.s */, Mips::CMP_LT_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6239 { 2515 /* cmp.saf.d */, Mips::CMP_SAF_D, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6240 { 2515 /* cmp.saf.d */, Mips::CMP_SAF_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6241 { 2525 /* cmp.saf.s */, Mips::CMP_SAF_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6242 { 2525 /* cmp.saf.s */, Mips::CMP_SAF_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6243 { 2535 /* cmp.seq.d */, Mips::CMP_SEQ_D, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6244 { 2535 /* cmp.seq.d */, Mips::CMP_SEQ_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6245 { 2545 /* cmp.seq.s */, Mips::CMP_SEQ_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6246 { 2545 /* cmp.seq.s */, Mips::CMP_SEQ_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6247 { 2555 /* cmp.sle.d */, Mips::CMP_SLE_D, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6248 { 2555 /* cmp.sle.d */, Mips::CMP_SLE_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6249 { 2565 /* cmp.sle.s */, Mips::CMP_SLE_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6250 { 2565 /* cmp.sle.s */, Mips::CMP_SLE_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6251 { 2575 /* cmp.slt.d */, Mips::CMP_SLT_D, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6252 { 2575 /* cmp.slt.d */, Mips::CMP_SLT_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6253 { 2585 /* cmp.slt.s */, Mips::CMP_SLT_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6254 { 2585 /* cmp.slt.s */, Mips::CMP_SLT_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6255 { 2595 /* cmp.sueq.d */, Mips::CMP_SUEQ_D, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6256 { 2595 /* cmp.sueq.d */, Mips::CMP_SUEQ_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6257 { 2606 /* cmp.sueq.s */, Mips::CMP_SUEQ_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6258 { 2606 /* cmp.sueq.s */, Mips::CMP_SUEQ_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6259 { 2617 /* cmp.sule.d */, Mips::CMP_SULE_D, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6260 { 2617 /* cmp.sule.d */, Mips::CMP_SULE_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6261 { 2628 /* cmp.sule.s */, Mips::CMP_SULE_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6262 { 2628 /* cmp.sule.s */, Mips::CMP_SULE_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6263 { 2639 /* cmp.sult.d */, Mips::CMP_SULT_D, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6264 { 2639 /* cmp.sult.d */, Mips::CMP_SULT_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6265 { 2650 /* cmp.sult.s */, Mips::CMP_SULT_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6266 { 2650 /* cmp.sult.s */, Mips::CMP_SULT_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6267 { 2661 /* cmp.sun.d */, Mips::CMP_SUN_D, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6268 { 2661 /* cmp.sun.d */, Mips::CMP_SUN_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6269 { 2671 /* cmp.sun.s */, Mips::CMP_SUN_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6270 { 2671 /* cmp.sun.s */, Mips::CMP_SUN_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6271 { 2681 /* cmp.ueq.d */, Mips::CMP_UEQ_D, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6272 { 2681 /* cmp.ueq.d */, Mips::CMP_UEQ_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6273 { 2691 /* cmp.ueq.s */, Mips::CMP_UEQ_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6274 { 2691 /* cmp.ueq.s */, Mips::CMP_UEQ_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6275 { 2701 /* cmp.ule.d */, Mips::CMP_ULE_D, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6276 { 2701 /* cmp.ule.d */, Mips::CMP_ULE_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6277 { 2711 /* cmp.ule.s */, Mips::CMP_ULE_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6278 { 2711 /* cmp.ule.s */, Mips::CMP_ULE_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6279 { 2721 /* cmp.ult.d */, Mips::CMP_ULT_D, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6280 { 2721 /* cmp.ult.d */, Mips::CMP_ULT_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6281 { 2731 /* cmp.ult.s */, Mips::CMP_ULT_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6282 { 2731 /* cmp.ult.s */, Mips::CMP_ULT_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6283 { 2741 /* cmp.un.d */, Mips::CMP_UN_D, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6284 { 2741 /* cmp.un.d */, Mips::CMP_UN_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6285 { 2750 /* cmp.un.s */, Mips::CMP_UN_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6286 { 2750 /* cmp.un.s */, Mips::CMP_UN_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6287 { 2759 /* cmpgdu.eq.qb */, Mips::CMPGDU_EQ_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6288 { 2759 /* cmpgdu.eq.qb */, Mips::CMPGDU_EQ_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6289 { 2772 /* cmpgdu.le.qb */, Mips::CMPGDU_LE_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6290 { 2772 /* cmpgdu.le.qb */, Mips::CMPGDU_LE_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6291 { 2785 /* cmpgdu.lt.qb */, Mips::CMPGDU_LT_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6292 { 2785 /* cmpgdu.lt.qb */, Mips::CMPGDU_LT_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6293 { 2798 /* cmpgu.eq.qb */, Mips::CMPGU_EQ_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6294 { 2798 /* cmpgu.eq.qb */, Mips::CMPGU_EQ_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6295 { 2810 /* cmpgu.le.qb */, Mips::CMPGU_LE_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6296 { 2810 /* cmpgu.le.qb */, Mips::CMPGU_LE_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6297 { 2822 /* cmpgu.lt.qb */, Mips::CMPGU_LT_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6298 { 2822 /* cmpgu.lt.qb */, Mips::CMPGU_LT_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6299 { 2834 /* cmpi */, Mips::CmpiRxImmX16, Convert__Reg1_0__SImm161_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_SImm16 }, },
6300 { 2834 /* cmpi */, Mips::CmpiRxImm16, Convert__Reg1_0__SImm161_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_SImm16, MCK__HASH_, MCK_16, MCK_bit, MCK_inst }, },
6301 { 2839 /* cmpu.eq.qb */, Mips::CMPU_EQ_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6302 { 2839 /* cmpu.eq.qb */, Mips::CMPU_EQ_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6303 { 2850 /* cmpu.le.qb */, Mips::CMPU_LE_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6304 { 2850 /* cmpu.le.qb */, Mips::CMPU_LE_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6305 { 2861 /* cmpu.lt.qb */, Mips::CMPU_LT_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6306 { 2861 /* cmpu.lt.qb */, Mips::CMPU_LT_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6307 { 2872 /* copy_s.b */, Mips::COPY_S_B, Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_3, AMFBS_HasStdEnc_HasMSA, { MCK_GPR32AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm4_0, MCK__93_ }, },
6308 { 2881 /* copy_s.d */, Mips::COPY_S_D, Convert__GPR64AsmReg1_0__MSA128AsmReg1_1__ConstantUImm1_01_3, AMFBS_HasStdEnc_HasMSA_HasMips64, { MCK_GPR64AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm1_0, MCK__93_ }, },
6309 { 2890 /* copy_s.h */, Mips::COPY_S_H, Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_3, AMFBS_HasStdEnc_HasMSA, { MCK_GPR32AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm3_0, MCK__93_ }, },
6310 { 2899 /* copy_s.w */, Mips::COPY_S_W, Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm2_01_3, AMFBS_HasStdEnc_HasMSA, { MCK_GPR32AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm2_0, MCK__93_ }, },
6311 { 2908 /* copy_u.b */, Mips::COPY_U_B, Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_3, AMFBS_HasStdEnc_HasMSA, { MCK_GPR32AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm4_0, MCK__93_ }, },
6312 { 2917 /* copy_u.h */, Mips::COPY_U_H, Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_3, AMFBS_HasStdEnc_HasMSA, { MCK_GPR32AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm3_0, MCK__93_ }, },
6313 { 2926 /* copy_u.w */, Mips::COPY_U_W, Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm2_01_3, AMFBS_HasStdEnc_HasMSA_HasMips64, { MCK_GPR32AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm2_0, MCK__93_ }, },
6314 { 2935 /* crc32b */, Mips::CRC32B, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6315 { 2942 /* crc32cb */, Mips::CRC32CB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6316 { 2950 /* crc32cd */, Mips::CRC32CD, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips64r6_HasCRC_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6317 { 2958 /* crc32ch */, Mips::CRC32CH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6318 { 2966 /* crc32cw */, Mips::CRC32CW, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6319 { 2974 /* crc32d */, Mips::CRC32D, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips64r6_HasCRC_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6320 { 2981 /* crc32h */, Mips::CRC32H, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6321 { 2988 /* crc32w */, Mips::CRC32W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6322 { 2995 /* ctc1 */, Mips::CTC1, Convert__CCRAsmReg1_1__GPR32AsmReg1_0, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, { MCK_GPR32AsmReg, MCK_CCRAsmReg }, },
6323 { 2995 /* ctc1 */, Mips::CTC1_MM, Convert__CCRAsmReg1_1__GPR32AsmReg1_0, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_CCRAsmReg }, },
6324 { 3000 /* ctc2 */, Mips::CTC2_MM, Convert__COP2AsmReg1_1__GPR32AsmReg1_0, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_COP2AsmReg }, },
6325 { 3005 /* ctcmsa */, Mips::CTCMSA, Convert__MSACtrlAsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSACtrlAsmReg, MCK_GPR32AsmReg }, },
6326 { 3012 /* cttc1 */, Mips::CTTC1, Convert__FGR32AsmReg1_1__GPR32AsmReg1_0, AMFBS_HasMT, { MCK_GPR32AsmReg, MCK_FGR32AsmReg }, },
6327 { 3018 /* cvt.d.l */, Mips::CVT_D64_L, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6328 { 3018 /* cvt.d.l */, Mips::CVT_D_L_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6329 { 3026 /* cvt.d.s */, Mips::CVT_D32_S, Convert__AFGR64AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_FGR32AsmReg }, },
6330 { 3026 /* cvt.d.s */, Mips::CVT_D32_S_MM, Convert__AFGR64AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_FGR32AsmReg }, },
6331 { 3026 /* cvt.d.s */, Mips::CVT_D64_S, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, },
6332 { 3026 /* cvt.d.s */, Mips::CVT_D64_S_MM, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, },
6333 { 3034 /* cvt.d.w */, Mips::CVT_D32_W, Convert__AFGR64AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_FGR32AsmReg }, },
6334 { 3034 /* cvt.d.w */, Mips::CVT_D32_W_MM, Convert__AFGR64AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_FGR32AsmReg }, },
6335 { 3034 /* cvt.d.w */, Mips::CVT_D64_W, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, },
6336 { 3034 /* cvt.d.w */, Mips::CVT_D64_W_MM, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, },
6337 { 3042 /* cvt.l.d */, Mips::CVT_L_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6338 { 3042 /* cvt.l.d */, Mips::CVT_L_D64_MM, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6339 { 3042 /* cvt.l.d */, Mips::CVT_L_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6340 { 3050 /* cvt.l.s */, Mips::CVT_L_S, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, },
6341 { 3050 /* cvt.l.s */, Mips::CVT_L_S_MM, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, },
6342 { 3050 /* cvt.l.s */, Mips::CVT_L_S_MMR6, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, },
6343 { 3058 /* cvt.ps.pw */, Mips::CVT_PS_PW64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMips3D, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6344 { 3068 /* cvt.ps.s */, Mips::CVT_PS_S64, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6345 { 3077 /* cvt.pw.ps */, Mips::CVT_PW_PS64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMips3D, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6346 { 3087 /* cvt.s.d */, Mips::CVT_S_D32, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, },
6347 { 3087 /* cvt.s.d */, Mips::CVT_S_D32_MM, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, },
6348 { 3087 /* cvt.s.d */, Mips::CVT_S_D64, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg }, },
6349 { 3087 /* cvt.s.d */, Mips::CVT_S_D64_MM, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg }, },
6350 { 3095 /* cvt.s.l */, Mips::CVT_S_L, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg }, },
6351 { 3095 /* cvt.s.l */, Mips::CVT_S_L_MMR6, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, },
6352 { 3103 /* cvt.s.pl */, Mips::CVT_S_PL64, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg }, },
6353 { 3112 /* cvt.s.pu */, Mips::CVT_S_PU64, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg }, },
6354 { 3121 /* cvt.s.w */, Mips::CVT_S_W, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6355 { 3121 /* cvt.s.w */, Mips::CVT_S_W_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6356 { 3121 /* cvt.s.w */, Mips::CVT_S_W_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6357 { 3129 /* cvt.w.d */, Mips::CVT_W_D32, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, },
6358 { 3129 /* cvt.w.d */, Mips::CVT_W_D32_MM, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, },
6359 { 3129 /* cvt.w.d */, Mips::CVT_W_D64, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg }, },
6360 { 3129 /* cvt.w.d */, Mips::CVT_W_D64_MM, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg }, },
6361 { 3137 /* cvt.w.s */, Mips::CVT_W_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6362 { 3137 /* cvt.w.s */, Mips::CVT_W_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6363 { 3137 /* cvt.w.s */, Mips::CVT_W_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6364 { 3145 /* dadd */, Mips::DADD, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6365 { 3145 /* dadd */, Mips::DADDi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__SImm161_1, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_SImm16 }, },
6366 { 3145 /* dadd */, Mips::DADD, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6367 { 3145 /* dadd */, Mips::DADDi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm161_2, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_SImm16 }, },
6368 { 3150 /* daddi */, Mips::DADDi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__SImm161_1, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, { MCK_GPR64AsmReg, MCK_SImm16 }, },
6369 { 3150 /* daddi */, Mips::DADDi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm161_2, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_SImm16 }, },
6370 { 3156 /* daddiu */, Mips::DADDiu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__SImm161_1, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_SImm16 }, },
6371 { 3156 /* daddiu */, Mips::DADDiu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm161_2, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_SImm16 }, },
6372 { 3163 /* daddu */, Mips::DADDu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6373 { 3163 /* daddu */, Mips::DADDiu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__SImm161_1, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_SImm16 }, },
6374 { 3163 /* daddu */, Mips::DADDu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6375 { 3163 /* daddu */, Mips::DADDiu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm161_2, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_SImm16 }, },
6376 { 3169 /* dahi */, Mips::DAHI, Convert__GPR64AsmReg1_0__Tie0_1_2__UImm16_AltRelaxed1_2, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_UImm16_AltRelaxed }, },
6377 { 3174 /* dalign */, Mips::DALIGN, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2__ConstantUImm3_01_3, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm3_0 }, },
6378 { 3181 /* dati */, Mips::DATI, Convert__GPR64AsmReg1_0__Tie0_1_2__UImm16_AltRelaxed1_2, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_UImm16_AltRelaxed }, },
6379 { 3186 /* daui */, Mips::DAUI, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__UImm161_2, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_UImm16 }, },
6380 { 3191 /* dbitswap */, Mips::DBITSWAP, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6381 { 3200 /* dclo */, Mips::DCLO, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasStdEnc_IsGP64bit_HasMips64_NotMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6382 { 3200 /* dclo */, Mips::DCLO_R6, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6383 { 3205 /* dclz */, Mips::DCLZ, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasStdEnc_IsGP64bit_HasMips64_NotMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6384 { 3205 /* dclz */, Mips::DCLZ_R6, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6385 { 3210 /* ddiv */, Mips::DSDivMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6386 { 3210 /* ddiv */, Mips::DSDivIMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips, { MCK_GPR64AsmReg, MCK_Imm }, },
6387 { 3210 /* ddiv */, Mips::DSDIV, Convert__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips, { MCK_GPR32ZERO, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6388 { 3210 /* ddiv */, Mips::DSDivMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6389 { 3210 /* ddiv */, Mips::DDIV, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6390 { 3210 /* ddiv */, Mips::DSDivIMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, },
6391 { 3215 /* ddivu */, Mips::DUDivMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6392 { 3215 /* ddivu */, Mips::DUDivIMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips, { MCK_GPR64AsmReg, MCK_Imm }, },
6393 { 3215 /* ddivu */, Mips::DUDIV, Convert__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips, { MCK_GPR32ZERO, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6394 { 3215 /* ddivu */, Mips::DUDivMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6395 { 3215 /* ddivu */, Mips::DDIVU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6396 { 3215 /* ddivu */, Mips::DUDivIMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, },
6397 { 3221 /* deret */, Mips::DERET, Convert_NoOperands, AMFBS_HasStdEnc_HasMips32_NotInMicroMips, { }, },
6398 { 3221 /* deret */, Mips::DERET_MMR6, Convert_NoOperands, AMFBS_InMicroMips_HasMips32r6, { }, },
6399 { 3221 /* deret */, Mips::DERET_MM, Convert_NoOperands, AMFBS_InMicroMips, { }, },
6400 { 3227 /* dext */, Mips::DEXTM, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_331_3, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_33 }, },
6401 { 3227 /* dext */, Mips::DEXTU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_321_2__ConstantUImm5_11_3, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_32, MCK_ConstantUImm5_1 }, },
6402 { 3227 /* dext */, Mips::DEXT, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_0_Report_UImm61_2__ConstantUImm5_Plus1_Report_UImm61_3, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0_Report_UImm6, MCK_ConstantUImm5_Plus1_Report_UImm6 }, },
6403 { 3232 /* dextm */, Mips::DEXTM, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_331_3, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_33 }, },
6404 { 3238 /* dextu */, Mips::DEXTU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_321_2__ConstantUImm5_11_3, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_32, MCK_ConstantUImm5_1 }, },
6405 { 3244 /* di */, Mips::DI, Convert__regZERO, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips, { }, },
6406 { 3244 /* di */, Mips::DI_MMR6, Convert__regZERO, AMFBS_InMicroMips_HasMips32r6, { }, },
6407 { 3244 /* di */, Mips::DI_MM, Convert__regZERO, AMFBS_InMicroMips, { }, },
6408 { 3244 /* di */, Mips::DI, Convert__GPR32AsmReg1_0, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips, { MCK_GPR32AsmReg }, },
6409 { 3244 /* di */, Mips::DI_MMR6, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg }, },
6410 { 3244 /* di */, Mips::DI_MM, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips, { MCK_GPR32AsmReg }, },
6411 { 3247 /* dins */, Mips::DINSM, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImmRange2_641_3__Tie0_1_1, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImmRange2_64 }, },
6412 { 3247 /* dins */, Mips::DINSU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_321_2__ConstantUImm5_11_3__Tie0_1_1, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_32, MCK_ConstantUImm5_1 }, },
6413 { 3247 /* dins */, Mips::DINS, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2__ConstantUImm5_11_3__Tie0_1_1, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm6_0, MCK_ConstantUImm5_1 }, },
6414 { 3252 /* dinsm */, Mips::DINSM, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImmRange2_641_3__Tie0_1_1, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImmRange2_64 }, },
6415 { 3258 /* dinsu */, Mips::DINSU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_321_2__ConstantUImm5_11_3__Tie0_1_1, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_32, MCK_ConstantUImm5_1 }, },
6416 { 3264 /* div */, Mips::DIV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6417 { 3264 /* div */, Mips::SDivIMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm321_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_SImm32 }, },
6418 { 3264 /* div */, Mips::SDivMacro, Convert__GPR32NonZeroAsmReg1_0__GPR32NonZeroAsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32NonZeroAsmReg, MCK_GPR32AsmReg }, },
6419 { 3264 /* div */, Mips::SDIV, Convert__GPR32ZeroAsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32ZeroAsmReg, MCK_GPR32AsmReg }, },
6420 { 3264 /* div */, Mips::DivRxRy16, Convert__Reg1_1__Reg1_2, AMFBS_InMips16Mode, { MCK_GPR32ZERO, MCK_CPU16Regs, MCK_CPU16Regs }, },
6421 { 3264 /* div */, Mips::SDIV, Convert__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32ZERO, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6422 { 3264 /* div */, Mips::SDIV_MM, Convert__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32ZERO, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6423 { 3264 /* div */, Mips::DIV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6424 { 3264 /* div */, Mips::DIV_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6425 { 3264 /* div */, Mips::SDivIMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm321_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32 }, },
6426 { 3264 /* div */, Mips::SDivMacro, Convert__GPR32NonZeroAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32NonZeroAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6427 { 3268 /* div.d */, Mips::FDIV_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6428 { 3268 /* div.d */, Mips::FDIV_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6429 { 3268 /* div.d */, Mips::FDIV_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6430 { 3268 /* div.d */, Mips::FDIV_D64_MM, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6431 { 3274 /* div.s */, Mips::FDIV_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6432 { 3274 /* div.s */, Mips::FDIV_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_2__FGR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6433 { 3274 /* div.s */, Mips::FDIV_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6434 { 3280 /* div_s.b */, Mips::DIV_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6435 { 3288 /* div_s.d */, Mips::DIV_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6436 { 3296 /* div_s.h */, Mips::DIV_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6437 { 3304 /* div_s.w */, Mips::DIV_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6438 { 3312 /* div_u.b */, Mips::DIV_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6439 { 3320 /* div_u.d */, Mips::DIV_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6440 { 3328 /* div_u.h */, Mips::DIV_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6441 { 3336 /* div_u.w */, Mips::DIV_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6442 { 3344 /* divu */, Mips::DIVU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6443 { 3344 /* divu */, Mips::UDivIMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm321_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_SImm32 }, },
6444 { 3344 /* divu */, Mips::UDivMacro, Convert__GPR32NonZeroAsmReg1_0__GPR32NonZeroAsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32NonZeroAsmReg, MCK_GPR32AsmReg }, },
6445 { 3344 /* divu */, Mips::UDIV, Convert__GPR32ZeroAsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32ZeroAsmReg, MCK_GPR32AsmReg }, },
6446 { 3344 /* divu */, Mips::DivuRxRy16, Convert__Reg1_1__Reg1_2, AMFBS_InMips16Mode, { MCK_GPR32ZERO, MCK_CPU16Regs, MCK_CPU16Regs }, },
6447 { 3344 /* divu */, Mips::UDIV, Convert__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32ZERO, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6448 { 3344 /* divu */, Mips::UDIV_MM, Convert__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32ZERO, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6449 { 3344 /* divu */, Mips::UDivMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6450 { 3344 /* divu */, Mips::DIVU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6451 { 3344 /* divu */, Mips::DIVU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6452 { 3344 /* divu */, Mips::UDivIMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm321_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32 }, },
6453 { 3349 /* dla */, Mips::LoadAddrImm64, Convert__GPR64AsmReg1_0__Imm1_1, AMFBS_None, { MCK_GPR64AsmReg, MCK_Imm }, },
6454 { 3349 /* dla */, Mips::LoadAddrReg64, Convert__GPR64AsmReg1_0__Mem2_1, AMFBS_None, { MCK_GPR64AsmReg, MCK_Mem }, },
6455 { 3353 /* dli */, Mips::LoadImm64, Convert__GPR64AsmReg1_0__Imm1_1, AMFBS_None, { MCK_GPR64AsmReg, MCK_Imm }, },
6456 { 3357 /* dlsa */, Mips::DLSA, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2__ConstantUImm2_11_3, AMFBS_HasStdEnc_HasMSA_HasMips64, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm2_1 }, },
6457 { 3357 /* dlsa */, Mips::DLSA_R6, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2__ConstantUImm2_11_3, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm2_1 }, },
6458 { 3362 /* dmfc0 */, Mips::DMFC0, Convert__GPR64AsmReg1_0__COP0AsmReg1_1__imm_95_0, AMFBS_NotInMicroMips, { MCK_GPR64AsmReg, MCK_COP0AsmReg }, },
6459 { 3362 /* dmfc0 */, Mips::DMFC0, Convert__GPR64AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasStdEnc_IsGP64bit_HasMips3, { MCK_GPR64AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
6460 { 3368 /* dmfc1 */, Mips::DMFC1, Convert__GPR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_HasMips3_IsNotSoftFloat_IsNotSingleFloat, { MCK_GPR64AsmReg, MCK_FGR64AsmReg }, },
6461 { 3374 /* dmfc2 */, Mips::DMFC2, Convert__GPR64AsmReg1_0__COP2AsmReg1_1__imm_95_0, AMFBS_None, { MCK_GPR64AsmReg, MCK_COP2AsmReg }, },
6462 { 3374 /* dmfc2 */, Mips::DMFC2_OCTEON, Convert__GPR64AsmReg1_0__UImm161_1, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_UImm16 }, },
6463 { 3374 /* dmfc2 */, Mips::DMFC2, Convert__GPR64AsmReg1_0__COP2AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasStdEnc_IsGP64bit_HasMips3, { MCK_GPR64AsmReg, MCK_COP2AsmReg, MCK_ConstantUImm3_0 }, },
6464 { 3380 /* dmfgc0 */, Mips::DMFGC0, Convert__GPR64AsmReg1_0__COP0AsmReg1_1__imm_95_0, AMFBS_HasStdEnc_HasMips64r5_HasVirt_NotInMicroMips, { MCK_GPR64AsmReg, MCK_COP0AsmReg }, },
6465 { 3380 /* dmfgc0 */, Mips::DMFGC0, Convert__GPR64AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasStdEnc_HasMips64r5_HasVirt, { MCK_GPR64AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
6466 { 3387 /* dmod */, Mips::DMOD, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6467 { 3392 /* dmodu */, Mips::DMODU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6468 { 3398 /* dmt */, Mips::DMT, Convert__regZERO, AMFBS_HasMT_NotInMicroMips, { }, },
6469 { 3398 /* dmt */, Mips::DMT, Convert__GPR32AsmReg1_0, AMFBS_HasStdEnc_HasMT_NotInMicroMips, { MCK_GPR32AsmReg }, },
6470 { 3402 /* dmtc0 */, Mips::DMTC0, Convert__COP0AsmReg1_1__GPR64AsmReg1_0__imm_95_0, AMFBS_NotInMicroMips, { MCK_GPR64AsmReg, MCK_COP0AsmReg }, },
6471 { 3402 /* dmtc0 */, Mips::DMTC0, Convert__COP0AsmReg1_1__GPR64AsmReg1_0__ConstantUImm3_01_2, AMFBS_HasStdEnc_IsGP64bit_HasMips3, { MCK_GPR64AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
6472 { 3408 /* dmtc1 */, Mips::DMTC1, Convert__FGR64AsmReg1_1__GPR64AsmReg1_0, AMFBS_HasStdEnc_HasMips3_IsNotSoftFloat_IsNotSingleFloat, { MCK_GPR64AsmReg, MCK_FGR64AsmReg }, },
6473 { 3414 /* dmtc2 */, Mips::DMTC2, Convert__COP2AsmReg1_1__GPR64AsmReg1_0__imm_95_0, AMFBS_None, { MCK_GPR64AsmReg, MCK_COP2AsmReg }, },
6474 { 3414 /* dmtc2 */, Mips::DMTC2_OCTEON, Convert__GPR64AsmReg1_0__UImm161_1, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_UImm16 }, },
6475 { 3414 /* dmtc2 */, Mips::DMTC2, Convert__COP2AsmReg1_1__GPR64AsmReg1_0__ConstantUImm3_01_2, AMFBS_HasStdEnc_IsGP64bit_HasMips3, { MCK_GPR64AsmReg, MCK_COP2AsmReg, MCK_ConstantUImm3_0 }, },
6476 { 3420 /* dmtgc0 */, Mips::DMTGC0, Convert__COP0AsmReg1_1__GPR64AsmReg1_0__imm_95_0, AMFBS_HasStdEnc_HasMips64r5_HasVirt_NotInMicroMips, { MCK_GPR64AsmReg, MCK_COP0AsmReg }, },
6477 { 3420 /* dmtgc0 */, Mips::DMTGC0, Convert__COP0AsmReg1_1__GPR64AsmReg1_0__ConstantUImm3_01_2, AMFBS_HasStdEnc_HasMips64r5_HasVirt, { MCK_GPR64AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
6478 { 3427 /* dmuh */, Mips::DMUH, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6479 { 3432 /* dmuhu */, Mips::DMUHU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6480 { 3438 /* dmul */, Mips::DMUL, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6481 { 3438 /* dmul */, Mips::DMULMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasMips3_NotMips64r6_NotCnMips_NotR5900, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6482 { 3438 /* dmul */, Mips::DMUL_R6, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6483 { 3438 /* dmul */, Mips::DMUL, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6484 { 3438 /* dmul */, Mips::DMULImmMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm32_Relaxed1_2, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_SImm32_Relaxed }, },
6485 { 3443 /* dmulo */, Mips::DMULOMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6486 { 3449 /* dmulou */, Mips::DMULOUMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6487 { 3456 /* dmult */, Mips::DMULT, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6488 { 3462 /* dmultu */, Mips::DMULTu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6489 { 3469 /* dmulu */, Mips::DMULU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6490 { 3475 /* dneg */, Mips::DSUB, Convert__GPR64AsmReg1_0__regZERO_64__GPR64AsmReg1_0, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg }, },
6491 { 3475 /* dneg */, Mips::DSUB, Convert__GPR64AsmReg1_0__regZERO_64__GPR64AsmReg1_1, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6492 { 3480 /* dnegu */, Mips::DSUBu, Convert__GPR64AsmReg1_0__regZERO_64__GPR64AsmReg1_0, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg }, },
6493 { 3480 /* dnegu */, Mips::DSUBu, Convert__GPR64AsmReg1_0__regZERO_64__GPR64AsmReg1_1, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6494 { 3486 /* dotp_s.d */, Mips::DOTP_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6495 { 3495 /* dotp_s.h */, Mips::DOTP_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6496 { 3504 /* dotp_s.w */, Mips::DOTP_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6497 { 3513 /* dotp_u.d */, Mips::DOTP_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6498 { 3522 /* dotp_u.h */, Mips::DOTP_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6499 { 3531 /* dotp_u.w */, Mips::DOTP_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6500 { 3540 /* dpa.w.ph */, Mips::DPA_W_PH_MMR2, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6501 { 3540 /* dpa.w.ph */, Mips::DPA_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6502 { 3549 /* dpadd_s.d */, Mips::DPADD_S_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6503 { 3559 /* dpadd_s.h */, Mips::DPADD_S_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6504 { 3569 /* dpadd_s.w */, Mips::DPADD_S_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6505 { 3579 /* dpadd_u.d */, Mips::DPADD_U_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6506 { 3589 /* dpadd_u.h */, Mips::DPADD_U_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6507 { 3599 /* dpadd_u.w */, Mips::DPADD_U_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6508 { 3609 /* dpaq_s.w.ph */, Mips::DPAQ_S_W_PH_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6509 { 3609 /* dpaq_s.w.ph */, Mips::DPAQ_S_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6510 { 3621 /* dpaq_sa.l.w */, Mips::DPAQ_SA_L_W_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6511 { 3621 /* dpaq_sa.l.w */, Mips::DPAQ_SA_L_W, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6512 { 3633 /* dpaqx_s.w.ph */, Mips::DPAQX_S_W_PH_MMR2, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6513 { 3633 /* dpaqx_s.w.ph */, Mips::DPAQX_S_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6514 { 3646 /* dpaqx_sa.w.ph */, Mips::DPAQX_SA_W_PH_MMR2, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6515 { 3646 /* dpaqx_sa.w.ph */, Mips::DPAQX_SA_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6516 { 3660 /* dpau.h.qbl */, Mips::DPAU_H_QBL_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6517 { 3660 /* dpau.h.qbl */, Mips::DPAU_H_QBL, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6518 { 3671 /* dpau.h.qbr */, Mips::DPAU_H_QBR_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6519 { 3671 /* dpau.h.qbr */, Mips::DPAU_H_QBR, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6520 { 3682 /* dpax.w.ph */, Mips::DPAX_W_PH_MMR2, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6521 { 3682 /* dpax.w.ph */, Mips::DPAX_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6522 { 3692 /* dpop */, Mips::DPOP, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0, AMFBS_HasCnMips, { MCK_GPR64AsmReg }, },
6523 { 3692 /* dpop */, Mips::DPOP, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6524 { 3697 /* dps.w.ph */, Mips::DPS_W_PH_MMR2, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6525 { 3697 /* dps.w.ph */, Mips::DPS_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6526 { 3706 /* dpsq_s.w.ph */, Mips::DPSQ_S_W_PH_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6527 { 3706 /* dpsq_s.w.ph */, Mips::DPSQ_S_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6528 { 3718 /* dpsq_sa.l.w */, Mips::DPSQ_SA_L_W_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6529 { 3718 /* dpsq_sa.l.w */, Mips::DPSQ_SA_L_W, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6530 { 3730 /* dpsqx_s.w.ph */, Mips::DPSQX_S_W_PH_MMR2, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6531 { 3730 /* dpsqx_s.w.ph */, Mips::DPSQX_S_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6532 { 3743 /* dpsqx_sa.w.ph */, Mips::DPSQX_SA_W_PH_MMR2, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6533 { 3743 /* dpsqx_sa.w.ph */, Mips::DPSQX_SA_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6534 { 3757 /* dpsu.h.qbl */, Mips::DPSU_H_QBL_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6535 { 3757 /* dpsu.h.qbl */, Mips::DPSU_H_QBL, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6536 { 3768 /* dpsu.h.qbr */, Mips::DPSU_H_QBR_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6537 { 3768 /* dpsu.h.qbr */, Mips::DPSU_H_QBR, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6538 { 3779 /* dpsub_s.d */, Mips::DPSUB_S_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6539 { 3789 /* dpsub_s.h */, Mips::DPSUB_S_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6540 { 3799 /* dpsub_s.w */, Mips::DPSUB_S_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6541 { 3809 /* dpsub_u.d */, Mips::DPSUB_U_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6542 { 3819 /* dpsub_u.h */, Mips::DPSUB_U_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6543 { 3829 /* dpsub_u.w */, Mips::DPSUB_U_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6544 { 3839 /* dpsx.w.ph */, Mips::DPSX_W_PH_MMR2, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6545 { 3839 /* dpsx.w.ph */, Mips::DPSX_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6546 { 3849 /* drem */, Mips::DSRemMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6547 { 3849 /* drem */, Mips::DSRemIMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__SImm32_Relaxed1_1, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips, { MCK_GPR64AsmReg, MCK_SImm32_Relaxed }, },
6548 { 3849 /* drem */, Mips::DSRemMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6549 { 3849 /* drem */, Mips::DSRemIMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm32_Relaxed1_2, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_SImm32_Relaxed }, },
6550 { 3854 /* dremu */, Mips::DURemMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6551 { 3854 /* dremu */, Mips::DURemIMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__SImm32_Relaxed1_1, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips, { MCK_GPR64AsmReg, MCK_SImm32_Relaxed }, },
6552 { 3854 /* dremu */, Mips::DURemMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6553 { 3854 /* dremu */, Mips::DURemIMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm32_Relaxed1_2, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_SImm32_Relaxed }, },
6554 { 3860 /* drol */, Mips::DROL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips64, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6555 { 3860 /* drol */, Mips::DROLImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm161_1, AMFBS_HasStdEnc_HasMips64, { MCK_GPR32AsmReg, MCK_SImm16 }, },
6556 { 3860 /* drol */, Mips::DROL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips64, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6557 { 3860 /* drol */, Mips::DROLImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, AMFBS_HasStdEnc_HasMips64, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16 }, },
6558 { 3865 /* dror */, Mips::DROR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips64, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6559 { 3865 /* dror */, Mips::DRORImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm161_1, AMFBS_HasStdEnc_HasMips64, { MCK_GPR32AsmReg, MCK_SImm16 }, },
6560 { 3865 /* dror */, Mips::DROR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips64, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6561 { 3865 /* dror */, Mips::DRORImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, AMFBS_HasStdEnc_HasMips64, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16 }, },
6562 { 3870 /* drotr */, Mips::DROTR, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm6_01_1, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips, { MCK_GPR64AsmReg, MCK_ConstantUImm6_0 }, },
6563 { 3870 /* drotr */, Mips::DROTR, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm6_0 }, },
6564 { 3876 /* drotr32 */, Mips::DROTR32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0 }, },
6565 { 3876 /* drotr32 */, Mips::DROTR32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0 }, },
6566 { 3884 /* drotrv */, Mips::DROTRV, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR32AsmReg }, },
6567 { 3891 /* dsbh */, Mips::DSBH, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6568 { 3896 /* dshd */, Mips::DSHD, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6569 { 3901 /* dsll */, Mips::DSLLV, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR32AsmReg }, },
6570 { 3901 /* dsll */, Mips::DSLL, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm6_01_1, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_ConstantUImm6_0 }, },
6571 { 3901 /* dsll */, Mips::DSLLV, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR32AsmReg }, },
6572 { 3901 /* dsll */, Mips::DSLL, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm6_0 }, },
6573 { 3906 /* dsll32 */, Mips::DSLL32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0 }, },
6574 { 3906 /* dsll32 */, Mips::DSLL32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0 }, },
6575 { 3913 /* dsllv */, Mips::DSLLV, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR32AsmReg }, },
6576 { 3919 /* dsra */, Mips::DSRA, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm6_01_1, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_ConstantUImm6_0 }, },
6577 { 3919 /* dsra */, Mips::DSRAV, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips3, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR32AsmReg }, },
6578 { 3919 /* dsra */, Mips::DSRA, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm6_0 }, },
6579 { 3924 /* dsra32 */, Mips::DSRA32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0 }, },
6580 { 3924 /* dsra32 */, Mips::DSRA32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0 }, },
6581 { 3931 /* dsrav */, Mips::DSRAV, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR32AsmReg }, },
6582 { 3937 /* dsrl */, Mips::DSRLV, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR32AsmReg }, },
6583 { 3937 /* dsrl */, Mips::DSRL, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm6_01_1, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_ConstantUImm6_0 }, },
6584 { 3937 /* dsrl */, Mips::DSRLV, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR32AsmReg }, },
6585 { 3937 /* dsrl */, Mips::DSRL, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm6_0 }, },
6586 { 3942 /* dsrl32 */, Mips::DSRL32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0 }, },
6587 { 3942 /* dsrl32 */, Mips::DSRL32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0 }, },
6588 { 3949 /* dsrlv */, Mips::DSRLV, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR32AsmReg }, },
6589 { 3955 /* dsub */, Mips::DSUB, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6590 { 3955 /* dsub */, Mips::DADDi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__InvNum1_1, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, { MCK_GPR64AsmReg, MCK_InvNum }, },
6591 { 3955 /* dsub */, Mips::DSUB, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6592 { 3955 /* dsub */, Mips::DADDi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__InvNum1_2, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_InvNum }, },
6593 { 3960 /* dsubi */, Mips::DADDi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__InvNum1_1, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, { MCK_GPR64AsmReg, MCK_InvNum }, },
6594 { 3960 /* dsubi */, Mips::DADDi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__InvNum1_2, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_InvNum }, },
6595 { 3966 /* dsubu */, Mips::DSUBu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6596 { 3966 /* dsubu */, Mips::DADDiu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__InvNum1_1, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_InvNum }, },
6597 { 3966 /* dsubu */, Mips::DSUBu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6598 { 3966 /* dsubu */, Mips::DADDiu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__InvNum1_2, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_InvNum }, },
6599 { 3972 /* dvp */, Mips::DVP, Convert__regZERO, AMFBS_HasStdEnc_HasMips32r6, { }, },
6600 { 3972 /* dvp */, Mips::DVP_MMR6, Convert__regZERO, AMFBS_InMicroMips_HasMips32r6, { }, },
6601 { 3972 /* dvp */, Mips::DVP, Convert__GPR32AsmReg1_0, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR32AsmReg }, },
6602 { 3972 /* dvp */, Mips::DVP_MMR6, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg }, },
6603 { 3976 /* dvpe */, Mips::DVPE, Convert__regZERO, AMFBS_HasMT_NotInMicroMips, { }, },
6604 { 3976 /* dvpe */, Mips::DVPE, Convert__GPR32AsmReg1_0, AMFBS_HasStdEnc_HasMT_NotInMicroMips, { MCK_GPR32AsmReg }, },
6605 { 3981 /* ehb */, Mips::EHB, Convert_NoOperands, AMFBS_HasStdEnc_NotInMicroMips, { }, },
6606 { 3981 /* ehb */, Mips::EHB_MMR6, Convert_NoOperands, AMFBS_InMicroMips_HasMips32r6, { }, },
6607 { 3981 /* ehb */, Mips::EHB_MM, Convert_NoOperands, AMFBS_InMicroMips, { }, },
6608 { 3985 /* ei */, Mips::EI, Convert__regZERO, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips, { }, },
6609 { 3985 /* ei */, Mips::EI_MMR6, Convert__regZERO, AMFBS_InMicroMips_HasMips32r6, { }, },
6610 { 3985 /* ei */, Mips::EI_MM, Convert__regZERO, AMFBS_InMicroMips, { }, },
6611 { 3985 /* ei */, Mips::EI, Convert__GPR32AsmReg1_0, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips, { MCK_GPR32AsmReg }, },
6612 { 3985 /* ei */, Mips::EI_MMR6, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg }, },
6613 { 3985 /* ei */, Mips::EI_MM, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips, { MCK_GPR32AsmReg }, },
6614 { 3988 /* emt */, Mips::EMT, Convert__regZERO, AMFBS_HasMT_NotInMicroMips, { }, },
6615 { 3988 /* emt */, Mips::EMT, Convert__GPR32AsmReg1_0, AMFBS_HasStdEnc_HasMT_NotInMicroMips, { MCK_GPR32AsmReg }, },
6616 { 3992 /* eret */, Mips::ERET, Convert_NoOperands, AMFBS_HasStdEnc_HasMips3_32_NotInMicroMips, { }, },
6617 { 3992 /* eret */, Mips::ERET_MMR6, Convert_NoOperands, AMFBS_InMicroMips_HasMips32r6, { }, },
6618 { 3992 /* eret */, Mips::ERET_MM, Convert_NoOperands, AMFBS_InMicroMips, { }, },
6619 { 3997 /* eretnc */, Mips::ERETNC, Convert_NoOperands, AMFBS_HasStdEnc_HasMips32r5_NotInMicroMips, { }, },
6620 { 3997 /* eretnc */, Mips::ERETNC_MMR6, Convert_NoOperands, AMFBS_InMicroMips_HasMips32r6, { }, },
6621 { 4004 /* evp */, Mips::EVP, Convert__regZERO, AMFBS_HasStdEnc_HasMips32r6, { }, },
6622 { 4004 /* evp */, Mips::EVP_MMR6, Convert__regZERO, AMFBS_InMicroMips_HasMips32r6, { }, },
6623 { 4004 /* evp */, Mips::EVP, Convert__GPR32AsmReg1_0, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR32AsmReg }, },
6624 { 4004 /* evp */, Mips::EVP_MMR6, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg }, },
6625 { 4008 /* evpe */, Mips::EVPE, Convert__regZERO, AMFBS_HasMT_NotInMicroMips, { }, },
6626 { 4008 /* evpe */, Mips::EVPE, Convert__GPR32AsmReg1_0, AMFBS_HasStdEnc_HasMT_NotInMicroMips, { MCK_GPR32AsmReg }, },
6627 { 4013 /* ext */, Mips::EXT, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_1 }, },
6628 { 4013 /* ext */, Mips::EXT_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_1 }, },
6629 { 4013 /* ext */, Mips::EXT_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_1 }, },
6630 { 4017 /* extp */, Mips::EXTP_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, },
6631 { 4017 /* extp */, Mips::EXTP, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, },
6632 { 4022 /* extpdp */, Mips::EXTPDP_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, },
6633 { 4022 /* extpdp */, Mips::EXTPDP, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, },
6634 { 4029 /* extpdpv */, Mips::EXTPDPV_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, },
6635 { 4029 /* extpdpv */, Mips::EXTPDPV, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, },
6636 { 4037 /* extpv */, Mips::EXTPV_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, },
6637 { 4037 /* extpv */, Mips::EXTPV, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, },
6638 { 4043 /* extr.w */, Mips::EXTR_W_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, },
6639 { 4043 /* extr.w */, Mips::EXTR_W, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, },
6640 { 4050 /* extr_r.w */, Mips::EXTR_R_W_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, },
6641 { 4050 /* extr_r.w */, Mips::EXTR_R_W, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, },
6642 { 4059 /* extr_rs.w */, Mips::EXTR_RS_W_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, },
6643 { 4059 /* extr_rs.w */, Mips::EXTR_RS_W, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, },
6644 { 4069 /* extr_s.h */, Mips::EXTR_S_H_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, },
6645 { 4069 /* extr_s.h */, Mips::EXTR_S_H, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, },
6646 { 4078 /* extrv.w */, Mips::EXTRV_W_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, },
6647 { 4078 /* extrv.w */, Mips::EXTRV_W, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, },
6648 { 4086 /* extrv_r.w */, Mips::EXTRV_R_W_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, },
6649 { 4086 /* extrv_r.w */, Mips::EXTRV_R_W, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, },
6650 { 4096 /* extrv_rs.w */, Mips::EXTRV_RS_W_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, },
6651 { 4096 /* extrv_rs.w */, Mips::EXTRV_RS_W, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, },
6652 { 4107 /* extrv_s.h */, Mips::EXTRV_S_H_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, },
6653 { 4107 /* extrv_s.h */, Mips::EXTRV_S_H, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, },
6654 { 4117 /* exts */, Mips::EXTS, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1__ConstantUImm5_01_2, AMFBS_HasMips64_HasCnMips_NotInMicroMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_0 }, },
6655 { 4117 /* exts */, Mips::EXTS32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_32_Norm1_1__ConstantUImm5_01_2, AMFBS_HasMips64_HasCnMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_32_Norm, MCK_ConstantUImm5_0 }, },
6656 { 4117 /* exts */, Mips::EXTS, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_01_3, AMFBS_HasMips64_HasCnMips_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_0 }, },
6657 { 4117 /* exts */, Mips::EXTS32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_32_Norm1_2__ConstantUImm5_01_3, AMFBS_HasMips64_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_32_Norm, MCK_ConstantUImm5_0 }, },
6658 { 4122 /* exts32 */, Mips::EXTS32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1__ConstantUImm5_01_2, AMFBS_HasMips64_HasCnMips_NotInMicroMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_0 }, },
6659 { 4122 /* exts32 */, Mips::EXTS32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_01_3, AMFBS_HasMips64_HasCnMips_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_0 }, },
6660 { 4129 /* fadd.d */, Mips::FADD_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6661 { 4136 /* fadd.w */, Mips::FADD_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6662 { 4143 /* fcaf.d */, Mips::FCAF_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6663 { 4150 /* fcaf.w */, Mips::FCAF_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6664 { 4157 /* fceq.d */, Mips::FCEQ_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6665 { 4164 /* fceq.w */, Mips::FCEQ_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6666 { 4171 /* fclass.d */, Mips::FCLASS_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6667 { 4180 /* fclass.w */, Mips::FCLASS_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6668 { 4189 /* fcle.d */, Mips::FCLE_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6669 { 4196 /* fcle.w */, Mips::FCLE_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6670 { 4203 /* fclt.d */, Mips::FCLT_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6671 { 4210 /* fclt.w */, Mips::FCLT_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6672 { 4217 /* fcne.d */, Mips::FCNE_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6673 { 4224 /* fcne.w */, Mips::FCNE_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6674 { 4231 /* fcor.d */, Mips::FCOR_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6675 { 4238 /* fcor.w */, Mips::FCOR_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6676 { 4245 /* fcueq.d */, Mips::FCUEQ_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6677 { 4253 /* fcueq.w */, Mips::FCUEQ_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6678 { 4261 /* fcule.d */, Mips::FCULE_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6679 { 4269 /* fcule.w */, Mips::FCULE_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6680 { 4277 /* fcult.d */, Mips::FCULT_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6681 { 4285 /* fcult.w */, Mips::FCULT_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6682 { 4293 /* fcun.d */, Mips::FCUN_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6683 { 4300 /* fcun.w */, Mips::FCUN_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6684 { 4307 /* fcune.d */, Mips::FCUNE_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6685 { 4315 /* fcune.w */, Mips::FCUNE_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6686 { 4323 /* fdiv.d */, Mips::FDIV_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6687 { 4330 /* fdiv.w */, Mips::FDIV_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6688 { 4337 /* fexdo.h */, Mips::FEXDO_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6689 { 4345 /* fexdo.w */, Mips::FEXDO_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6690 { 4353 /* fexp2.d */, Mips::FEXP2_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6691 { 4361 /* fexp2.w */, Mips::FEXP2_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6692 { 4369 /* fexupl.d */, Mips::FEXUPL_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6693 { 4378 /* fexupl.w */, Mips::FEXUPL_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6694 { 4387 /* fexupr.d */, Mips::FEXUPR_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6695 { 4396 /* fexupr.w */, Mips::FEXUPR_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6696 { 4405 /* ffint_s.d */, Mips::FFINT_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6697 { 4415 /* ffint_s.w */, Mips::FFINT_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6698 { 4425 /* ffint_u.d */, Mips::FFINT_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6699 { 4435 /* ffint_u.w */, Mips::FFINT_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6700 { 4445 /* ffql.d */, Mips::FFQL_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6701 { 4452 /* ffql.w */, Mips::FFQL_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6702 { 4459 /* ffqr.d */, Mips::FFQR_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6703 { 4466 /* ffqr.w */, Mips::FFQR_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6704 { 4473 /* fill.b */, Mips::FILL_B, Convert__MSA128AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_GPR32AsmReg }, },
6705 { 4480 /* fill.d */, Mips::FILL_D, Convert__MSA128AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasStdEnc_HasMSA_HasMips64, { MCK_MSA128AsmReg, MCK_GPR64AsmReg }, },
6706 { 4487 /* fill.h */, Mips::FILL_H, Convert__MSA128AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_GPR32AsmReg }, },
6707 { 4494 /* fill.w */, Mips::FILL_W, Convert__MSA128AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_GPR32AsmReg }, },
6708 { 4501 /* flog2.d */, Mips::FLOG2_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6709 { 4509 /* flog2.w */, Mips::FLOG2_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6710 { 4517 /* floor.l.d */, Mips::FLOOR_L_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips3_32_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6711 { 4517 /* floor.l.d */, Mips::FLOOR_L_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6712 { 4527 /* floor.l.s */, Mips::FLOOR_L_S, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, },
6713 { 4527 /* floor.l.s */, Mips::FLOOR_L_S_MMR6, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, },
6714 { 4537 /* floor.w.d */, Mips::FLOOR_W_D32, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, },
6715 { 4537 /* floor.w.d */, Mips::FLOOR_W_MM, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, },
6716 { 4537 /* floor.w.d */, Mips::FLOOR_W_D_MMR6, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, },
6717 { 4537 /* floor.w.d */, Mips::FLOOR_W_D64, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg }, },
6718 { 4547 /* floor.w.s */, Mips::FLOOR_W_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_HasMips2_NotR5900_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6719 { 4547 /* floor.w.s */, Mips::FLOOR_W_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6720 { 4547 /* floor.w.s */, Mips::FLOOR_W_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6721 { 4557 /* fmadd.d */, Mips::FMADD_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6722 { 4565 /* fmadd.w */, Mips::FMADD_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6723 { 4573 /* fmax.d */, Mips::FMAX_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6724 { 4580 /* fmax.w */, Mips::FMAX_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6725 { 4587 /* fmax_a.d */, Mips::FMAX_A_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6726 { 4596 /* fmax_a.w */, Mips::FMAX_A_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6727 { 4605 /* fmin.d */, Mips::FMIN_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6728 { 4612 /* fmin.w */, Mips::FMIN_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6729 { 4619 /* fmin_a.d */, Mips::FMIN_A_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6730 { 4628 /* fmin_a.w */, Mips::FMIN_A_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6731 { 4637 /* fmsub.d */, Mips::FMSUB_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6732 { 4645 /* fmsub.w */, Mips::FMSUB_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6733 { 4653 /* fmul.d */, Mips::FMUL_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6734 { 4660 /* fmul.w */, Mips::FMUL_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6735 { 4667 /* fork */, Mips::FORK, Convert__GPR32AsmReg1_1__GPR32AsmReg1_0__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMT_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6736 { 4672 /* frcp.d */, Mips::FRCP_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6737 { 4679 /* frcp.w */, Mips::FRCP_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6738 { 4686 /* frint.d */, Mips::FRINT_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6739 { 4694 /* frint.w */, Mips::FRINT_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6740 { 4702 /* frsqrt.d */, Mips::FRSQRT_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6741 { 4711 /* frsqrt.w */, Mips::FRSQRT_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6742 { 4720 /* fsaf.d */, Mips::FSAF_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6743 { 4727 /* fsaf.w */, Mips::FSAF_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6744 { 4734 /* fseq.d */, Mips::FSEQ_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6745 { 4741 /* fseq.w */, Mips::FSEQ_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6746 { 4748 /* fsle.d */, Mips::FSLE_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6747 { 4755 /* fsle.w */, Mips::FSLE_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6748 { 4762 /* fslt.d */, Mips::FSLT_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6749 { 4769 /* fslt.w */, Mips::FSLT_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6750 { 4776 /* fsne.d */, Mips::FSNE_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6751 { 4783 /* fsne.w */, Mips::FSNE_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6752 { 4790 /* fsor.d */, Mips::FSOR_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6753 { 4797 /* fsor.w */, Mips::FSOR_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6754 { 4804 /* fsqrt.d */, Mips::FSQRT_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6755 { 4812 /* fsqrt.w */, Mips::FSQRT_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6756 { 4820 /* fsub.d */, Mips::FSUB_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6757 { 4827 /* fsub.w */, Mips::FSUB_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6758 { 4834 /* fsueq.d */, Mips::FSUEQ_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6759 { 4842 /* fsueq.w */, Mips::FSUEQ_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6760 { 4850 /* fsule.d */, Mips::FSULE_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6761 { 4858 /* fsule.w */, Mips::FSULE_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6762 { 4866 /* fsult.d */, Mips::FSULT_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6763 { 4874 /* fsult.w */, Mips::FSULT_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6764 { 4882 /* fsun.d */, Mips::FSUN_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6765 { 4889 /* fsun.w */, Mips::FSUN_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6766 { 4896 /* fsune.d */, Mips::FSUNE_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6767 { 4904 /* fsune.w */, Mips::FSUNE_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6768 { 4912 /* ftint_s.d */, Mips::FTINT_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6769 { 4922 /* ftint_s.w */, Mips::FTINT_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6770 { 4932 /* ftint_u.d */, Mips::FTINT_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6771 { 4942 /* ftint_u.w */, Mips::FTINT_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6772 { 4952 /* ftq.h */, Mips::FTQ_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6773 { 4958 /* ftq.w */, Mips::FTQ_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6774 { 4964 /* ftrunc_s.d */, Mips::FTRUNC_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6775 { 4975 /* ftrunc_s.w */, Mips::FTRUNC_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6776 { 4986 /* ftrunc_u.d */, Mips::FTRUNC_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6777 { 4997 /* ftrunc_u.w */, Mips::FTRUNC_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6778 { 5008 /* ginvi */, Mips::GINVI, Convert__GPR32AsmReg1_0, AMFBS_HasStdEnc_HasMips32r6_HasGINV_NotInMicroMips, { MCK_GPR32AsmReg }, },
6779 { 5008 /* ginvi */, Mips::GINVI_MMR6, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips_HasMips32r6_HasGINV, { MCK_GPR32AsmReg }, },
6780 { 5014 /* ginvt */, Mips::GINVT, Convert__GPR32AsmReg1_0__ConstantUImm2_01_1, AMFBS_HasStdEnc_HasMips32r6_HasGINV_NotInMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm2_0 }, },
6781 { 5014 /* ginvt */, Mips::GINVT_MMR6, Convert__GPR32AsmReg1_0__ConstantUImm2_01_1, AMFBS_InMicroMips_HasMips32r6_HasGINV, { MCK_GPR32AsmReg, MCK_ConstantUImm2_0 }, },
6782 { 5020 /* hadd_s.d */, Mips::HADD_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6783 { 5029 /* hadd_s.h */, Mips::HADD_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6784 { 5038 /* hadd_s.w */, Mips::HADD_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6785 { 5047 /* hadd_u.d */, Mips::HADD_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6786 { 5056 /* hadd_u.h */, Mips::HADD_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6787 { 5065 /* hadd_u.w */, Mips::HADD_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6788 { 5074 /* hsub_s.d */, Mips::HSUB_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6789 { 5083 /* hsub_s.h */, Mips::HSUB_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6790 { 5092 /* hsub_s.w */, Mips::HSUB_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6791 { 5101 /* hsub_u.d */, Mips::HSUB_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6792 { 5110 /* hsub_u.h */, Mips::HSUB_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6793 { 5119 /* hsub_u.w */, Mips::HSUB_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6794 { 5128 /* hypcall */, Mips::HYPCALL, Convert__imm_95_0, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, { }, },
6795 { 5128 /* hypcall */, Mips::HYPCALL_MM, Convert__imm_95_0, AMFBS_InMicroMips_HasMips32r5_HasVirt, { }, },
6796 { 5128 /* hypcall */, Mips::HYPCALL, Convert__ConstantUImm10_01_0, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, { MCK_ConstantUImm10_0 }, },
6797 { 5128 /* hypcall */, Mips::HYPCALL_MM, Convert__ConstantUImm10_01_0, AMFBS_InMicroMips_HasMips32r5_HasVirt, { MCK_ConstantUImm10_0 }, },
6798 { 5136 /* ilvev.b */, Mips::ILVEV_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6799 { 5144 /* ilvev.d */, Mips::ILVEV_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6800 { 5152 /* ilvev.h */, Mips::ILVEV_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6801 { 5160 /* ilvev.w */, Mips::ILVEV_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6802 { 5168 /* ilvl.b */, Mips::ILVL_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6803 { 5175 /* ilvl.d */, Mips::ILVL_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6804 { 5182 /* ilvl.h */, Mips::ILVL_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6805 { 5189 /* ilvl.w */, Mips::ILVL_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6806 { 5196 /* ilvod.b */, Mips::ILVOD_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6807 { 5204 /* ilvod.d */, Mips::ILVOD_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6808 { 5212 /* ilvod.h */, Mips::ILVOD_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6809 { 5220 /* ilvod.w */, Mips::ILVOD_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6810 { 5228 /* ilvr.b */, Mips::ILVR_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6811 { 5235 /* ilvr.d */, Mips::ILVR_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6812 { 5242 /* ilvr.h */, Mips::ILVR_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6813 { 5249 /* ilvr.w */, Mips::ILVR_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6814 { 5256 /* ins */, Mips::INS, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3__Tie0_1_1, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_1 }, },
6815 { 5256 /* ins */, Mips::INS_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3__Tie0_1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_1 }, },
6816 { 5256 /* ins */, Mips::INS_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3__Tie0_1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_1 }, },
6817 { 5260 /* insert.b */, Mips::INSERT_B, Convert__MSA128AsmReg1_0__Tie0_1_1__GPR32AsmReg1_4__ConstantUImm4_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm4_0, MCK__93_, MCK_GPR32AsmReg }, },
6818 { 5269 /* insert.d */, Mips::INSERT_D, Convert__MSA128AsmReg1_0__Tie0_1_1__GPR64AsmReg1_4__ConstantUImm1_01_2, AMFBS_HasStdEnc_HasMSA_HasMips64, { MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm1_0, MCK__93_, MCK_GPR64AsmReg }, },
6819 { 5278 /* insert.h */, Mips::INSERT_H, Convert__MSA128AsmReg1_0__Tie0_1_1__GPR32AsmReg1_4__ConstantUImm3_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm3_0, MCK__93_, MCK_GPR32AsmReg }, },
6820 { 5287 /* insert.w */, Mips::INSERT_W, Convert__MSA128AsmReg1_0__Tie0_1_1__GPR32AsmReg1_4__ConstantUImm2_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm2_0, MCK__93_, MCK_GPR32AsmReg }, },
6821 { 5296 /* insv */, Mips::INSV_MM, Convert__GPR32AsmReg1_0__Tie0_1_1__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6822 { 5296 /* insv */, Mips::INSV, Convert__GPR32AsmReg1_0__Tie0_1_1__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6823 { 5301 /* insve.b */, Mips::INSVE_B, Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm4_01_2__MSA128AsmReg1_4__ConstantImmz1_6, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm4_0, MCK__93_, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantImmz, MCK__93_ }, },
6824 { 5309 /* insve.d */, Mips::INSVE_D, Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm1_01_2__MSA128AsmReg1_4__ConstantImmz1_6, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm1_0, MCK__93_, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantImmz, MCK__93_ }, },
6825 { 5317 /* insve.h */, Mips::INSVE_H, Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm3_01_2__MSA128AsmReg1_4__ConstantImmz1_6, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm3_0, MCK__93_, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantImmz, MCK__93_ }, },
6826 { 5325 /* insve.w */, Mips::INSVE_W, Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm2_01_2__MSA128AsmReg1_4__ConstantImmz1_6, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm2_0, MCK__93_, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantImmz, MCK__93_ }, },
6827 { 5333 /* j */, Mips::JR, Convert__GPR32AsmReg1_0, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg }, },
6828 { 5333 /* j */, Mips::JALR, Convert__regRA__GPR32AsmReg1_0, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg }, },
6829 { 5333 /* j */, Mips::JR_MM, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg }, },
6830 { 5333 /* j */, Mips::J_MM, Convert__Imm1_0, AMFBS_InMicroMips_NotMips32r6, { MCK_Imm }, },
6831 { 5333 /* j */, Mips::J, Convert__JumpTarget1_0, AMFBS_HasStdEnc_NotInMicroMips, { MCK_JumpTarget }, },
6832 { 5335 /* jal */, Mips::JalOneReg, Convert__GPR32AsmReg1_0, AMFBS_None, { MCK_GPR32AsmReg }, },
6833 { 5335 /* jal */, Mips::JAL_MM, Convert__Imm1_0, AMFBS_InMicroMips_NotMips32r6, { MCK_Imm }, },
6834 { 5335 /* jal */, Mips::JAL, Convert__JumpTarget1_0, AMFBS_HasStdEnc_NotInMicroMips, { MCK_JumpTarget }, },
6835 { 5335 /* jal */, Mips::BALC_MMR6, Convert__JumpTarget1_0, AMFBS_InMicroMips_HasMips32r6, { MCK_JumpTarget }, },
6836 { 5335 /* jal */, Mips::JalTwoReg, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_None, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6837 { 5339 /* jalr */, Mips::JALR16_MM, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg }, },
6838 { 5339 /* jalr */, Mips::JALRC16_MMR6, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg }, },
6839 { 5339 /* jalr */, Mips::JALR, Convert__regRA__GPR32AsmReg1_0, AMFBS_NotInMicroMips, { MCK_GPR32AsmReg }, },
6840 { 5339 /* jalr */, Mips::JALR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotInMicroMips_NoIndirectJumpGuards, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6841 { 5339 /* jalr */, Mips::JALR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6842 { 5339 /* jalr */, Mips::JALR64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_NotInMips16Mode_IsPTR64bit, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6843 { 5344 /* jalr.hb */, Mips::JALR_HB, Convert__regRA__GPR32AsmReg1_0, AMFBS_HasStdEnc_HasMips32_NotInMicroMips, { MCK_GPR32AsmReg }, },
6844 { 5344 /* jalr.hb */, Mips::JALR_HB_MM, Convert__regRA__GPR32AsmReg1_0, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg }, },
6845 { 5344 /* jalr.hb */, Mips::JALR_HB64, Convert__regRA_64__GPR64AsmReg1_0, AMFBS_HasStdEnc_HasMips64_NotInMicroMips, { MCK_GPR64AsmReg }, },
6846 { 5344 /* jalr.hb */, Mips::JALR_HB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips32, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6847 { 5344 /* jalr.hb */, Mips::JALR_HB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6848 { 5344 /* jalr.hb */, Mips::JALR_HB64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6849 { 5352 /* jalrc */, Mips::JumpLinkReg16, Convert__Reg1_0, AMFBS_InMips16Mode, { MCK_CPU16Regs }, },
6850 { 5352 /* jalrc */, Mips::JIALC, Convert__GPR32AsmReg1_0__imm_95_0, AMFBS_HasStdEnc_IsGP32bit_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg }, },
6851 { 5352 /* jalrc */, Mips::JALRC_MMR6, Convert__regRA__GPR32AsmReg1_0, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg }, },
6852 { 5352 /* jalrc */, Mips::JIALC64, Convert__GPR64AsmReg1_0__imm_95_0, AMFBS_HasStdEnc_HasMips64r6, { MCK_GPR64AsmReg }, },
6853 { 5352 /* jalrc */, Mips::JALRC_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6854 { 5358 /* jalrc.hb */, Mips::JALRC_HB_MMR6, Convert__regRA__GPR32AsmReg1_0, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg }, },
6855 { 5358 /* jalrc.hb */, Mips::JALRC_HB_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6856 { 5367 /* jalrs */, Mips::JALRS_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6857 { 5373 /* jalrs16 */, Mips::JALRS16_MM, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg }, },
6858 { 5381 /* jals */, Mips::JALS_MM, Convert__Imm1_0, AMFBS_InMicroMips_NotMips32r6, { MCK_Imm }, },
6859 { 5386 /* jalx */, Mips::JALX, Convert__JumpTarget1_0, AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_JumpTarget }, },
6860 { 5386 /* jalx */, Mips::JALX_MM, Convert__JumpTarget1_0, AMFBS_InMicroMips_NotMips32r6, { MCK_JumpTarget }, },
6861 { 5391 /* jialc */, Mips::JIALC, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
6862 { 5391 /* jialc */, Mips::JIALC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
6863 { 5391 /* jialc */, Mips::JIALC64, Convert__GPR64AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6, { MCK_GPR64AsmReg, MCK_JumpTarget }, },
6864 { 5397 /* jic */, Mips::JIC, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
6865 { 5397 /* jic */, Mips::JIC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
6866 { 5397 /* jic */, Mips::JIC64, Convert__GPR64AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6, { MCK_GPR64AsmReg, MCK_JumpTarget }, },
6867 { 5401 /* jr */, Mips::JrRa16, Convert_NoOperands, AMFBS_InMips16Mode, { MCK_CPURAReg }, },
6868 { 5401 /* jr */, Mips::JR, Convert__GPR32AsmReg1_0, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg }, },
6869 { 5401 /* jr */, Mips::JALR, Convert__regZERO__GPR32AsmReg1_0, AMFBS_HasStdEnc_IsGP32bit_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg }, },
6870 { 5401 /* jr */, Mips::JR_MM, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg }, },
6871 { 5401 /* jr */, Mips::JR64, Convert__GPR64AsmReg1_0, AMFBS_NotInMips16Mode_IsPTR64bit_NotInMicroMips, { MCK_GPR64AsmReg }, },
6872 { 5401 /* jr */, Mips::JALR64, Convert__regZERO_64__GPR64AsmReg1_0, AMFBS_HasStdEnc_HasMips64r6, { MCK_GPR64AsmReg }, },
6873 { 5404 /* jr.hb */, Mips::JR_HB, Convert__GPR32AsmReg1_0, AMFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg }, },
6874 { 5404 /* jr.hb */, Mips::JR_HB_MM, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg }, },
6875 { 5404 /* jr.hb */, Mips::JR_HB_R6, Convert__GPR32AsmReg1_0, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR32AsmReg }, },
6876 { 5404 /* jr.hb */, Mips::JR_HB64, Convert__GPR64AsmReg1_0, AMFBS_HasStdEnc_HasMips64_NotMips64r6_NotInMicroMips, { MCK_GPR64AsmReg }, },
6877 { 5404 /* jr.hb */, Mips::JR_HB64_R6, Convert__GPR64AsmReg1_0, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR64AsmReg }, },
6878 { 5410 /* jr16 */, Mips::JR16_MM, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg }, },
6879 { 5415 /* jraddiusp */, Mips::JRADDIUSP, Convert__UImm5Lsl21_0, AMFBS_InMicroMips_NotMips32r6, { MCK_UImm5Lsl2 }, },
6880 { 5425 /* jrc */, Mips::JrcRa16, Convert_NoOperands, AMFBS_InMips16Mode, { MCK_CPURAReg }, },
6881 { 5425 /* jrc */, Mips::JrcRx16, Convert__Reg1_0, AMFBS_InMips16Mode, { MCK_CPU16Regs }, },
6882 { 5425 /* jrc */, Mips::JIC, Convert__GPR32AsmReg1_0__imm_95_0, AMFBS_HasStdEnc_IsGP32bit_HasMips32r6, { MCK_GPR32AsmReg }, },
6883 { 5425 /* jrc */, Mips::JRC16_MM, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg }, },
6884 { 5425 /* jrc */, Mips::JIC64, Convert__GPR64AsmReg1_0__imm_95_0, AMFBS_HasStdEnc_HasMips64r6, { MCK_GPR64AsmReg }, },
6885 { 5429 /* jrc16 */, Mips::JRC16_MMR6, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg }, },
6886 { 5435 /* jrcaddiusp */, Mips::JRCADDIUSP_MMR6, Convert__UImm5Lsl21_0, AMFBS_InMicroMips_HasMips32r6, { MCK_UImm5Lsl2 }, },
6887 { 5446 /* l.d */, Mips::LDC1, Convert__AFGR64AsmReg1_0__MemOffsetSimm16_02_1, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_MemOffsetSimm16_0 }, },
6888 { 5446 /* l.d */, Mips::LDC164, Convert__FGR64AsmReg1_0__MemOffsetSimm16_02_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_MemOffsetSimm16_0 }, },
6889 { 5450 /* l.s */, Mips::LWC1, Convert__FGR32AsmReg1_0__MemOffsetSimm16_02_1, AMFBS_HasStdEnc_HasMips2_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_MemOffsetSimm16_0 }, },
6890 { 5454 /* la */, Mips::LoadAddrImm32, Convert__GPR32AsmReg1_0__Imm1_1, AMFBS_None, { MCK_GPR32AsmReg, MCK_Imm }, },
6891 { 5454 /* la */, Mips::LoadAddrReg32, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_None, { MCK_GPR32AsmReg, MCK_Mem }, },
6892 { 5457 /* lapc */, Mips::ADDIUPC, Convert__GPR32AsmReg1_0__Simm19_Lsl21_1, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR32AsmReg, MCK_Simm19_Lsl2 }, },
6893 { 5457 /* lapc */, Mips::ADDIUPC_MMR6, Convert__GPR32AsmReg1_0__Simm19_Lsl21_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_Simm19_Lsl2 }, },
6894 { 5462 /* lb */, Mips::LB, Convert__GPR32AsmReg1_0__MemOffsetSimmPtr2_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimmPtr }, },
6895 { 5462 /* lb */, Mips::LB_MMR6, Convert__GPR32AsmReg1_0__MemOffsetSimm16_02_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_MemOffsetSimm16_0 }, },
6896 { 5462 /* lb */, Mips::LB_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm16_02_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm16_0 }, },
6897 { 5465 /* lbe */, Mips::LBE, Convert__GPR32AsmReg1_0__MemOffsetSimm9_02_1, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9_0 }, },
6898 { 5465 /* lbe */, Mips::LBE_MM, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_InMicroMips_HasEVA, { MCK_GPR32AsmReg, MCK_Mem }, },
6899 { 5469 /* lbu */, Mips::LBu, Convert__GPR32AsmReg1_0__MemOffsetSimmPtr2_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimmPtr }, },
6900 { 5469 /* lbu */, Mips::LBU_MMR6, Convert__GPR32AsmReg1_0__MemOffsetSimm16_02_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_MemOffsetSimm16_0 }, },
6901 { 5469 /* lbu */, Mips::LBu_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm16_02_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm16_0 }, },
6902 { 5473 /* lbu16 */, Mips::LBU16_MM, Convert__GPRMM16AsmReg1_0__MicroMipsMem2_1, AMFBS_InMicroMips, { MCK_GPRMM16AsmReg, MCK_MicroMipsMem }, },
6903 { 5479 /* lbue */, Mips::LBuE, Convert__GPR32AsmReg1_0__MemOffsetSimm9_02_1, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9_0 }, },
6904 { 5479 /* lbue */, Mips::LBuE_MM, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_InMicroMips_HasEVA, { MCK_GPR32AsmReg, MCK_Mem }, },
6905 { 5484 /* lbux */, Mips::LBUX_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
6906 { 5484 /* lbux */, Mips::LBUX, Convert__GPR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
6907 { 5489 /* ld */, Mips::LDMacro, Convert__GPR32AsmReg1_0__MemOffsetSimm16_02_1, AMFBS_HasStdEnc_NotMips3, { MCK_GPR32AsmReg, MCK_MemOffsetSimm16_0 }, },
6908 { 5489 /* ld */, Mips::LD, Convert__GPR64AsmReg1_0__MemOffsetSimmPtr2_1, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_MemOffsetSimmPtr }, },
6909 { 5492 /* ld.b */, Mips::LD_B, Convert__MSA128AsmReg1_0__MemOffsetSimm10_02_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MemOffsetSimm10_0 }, },
6910 { 5497 /* ld.d */, Mips::LD_D, Convert__MSA128AsmReg1_0__MemOffsetSimm10_32_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MemOffsetSimm10_3 }, },
6911 { 5502 /* ld.h */, Mips::LD_H, Convert__MSA128AsmReg1_0__MemOffsetSimm10_12_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MemOffsetSimm10_1 }, },
6912 { 5507 /* ld.w */, Mips::LD_W, Convert__MSA128AsmReg1_0__MemOffsetSimm10_22_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MemOffsetSimm10_2 }, },
6913 { 5512 /* ldc1 */, Mips::LDC1, Convert__AFGR64AsmReg1_0__MemOffsetSimm16_02_1, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_MemOffsetSimm16_0 }, },
6914 { 5512 /* ldc1 */, Mips::LDC1_MM_D32, Convert__AFGR64AsmReg1_0__MemOffsetSimm16_02_1, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_MemOffsetSimm16_0 }, },
6915 { 5512 /* ldc1 */, Mips::LDC164, Convert__FGR64AsmReg1_0__MemOffsetSimm16_02_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_MemOffsetSimm16_0 }, },
6916 { 5512 /* ldc1 */, Mips::LDC1_D64_MMR6, Convert__FGR64AsmReg1_0__MemOffsetSimm16_02_1, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_MemOffsetSimm16_0 }, },
6917 { 5512 /* ldc1 */, Mips::LDC1_MM_D64, Convert__FGR64AsmReg1_0__MemOffsetSimm16_02_1, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_MemOffsetSimm16_0 }, },
6918 { 5517 /* ldc2 */, Mips::LDC2_R6, Convert__COP2AsmReg1_0__MemOffsetSimm11_02_1, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_COP2AsmReg, MCK_MemOffsetSimm11_0 }, },
6919 { 5517 /* ldc2 */, Mips::LDC2_MMR6, Convert__COP2AsmReg1_0__MemOffsetSimm11_02_1, AMFBS_InMicroMips_HasMips32r6, { MCK_COP2AsmReg, MCK_MemOffsetSimm11_0 }, },
6920 { 5517 /* ldc2 */, Mips::LDC2, Convert__COP2AsmReg1_0__MemOffsetSimm16_02_1, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_COP2AsmReg, MCK_MemOffsetSimm16_0 }, },
6921 { 5522 /* ldc3 */, Mips::LDC3, Convert__COP3AsmReg1_0__Mem2_1, AMFBS_HasStdEnc_HasMips2_NotR5900_NotCnMips_NotInMicroMips, { MCK_COP3AsmReg, MCK_Mem }, },
6922 { 5527 /* ldi.b */, Mips::LDI_B, Convert__MSA128AsmReg1_0__ConstantSImm10_01_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_ConstantSImm10_0 }, },
6923 { 5533 /* ldi.d */, Mips::LDI_D, Convert__MSA128AsmReg1_0__ConstantSImm10_01_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_ConstantSImm10_0 }, },
6924 { 5539 /* ldi.h */, Mips::LDI_H, Convert__MSA128AsmReg1_0__ConstantSImm10_01_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_ConstantSImm10_0 }, },
6925 { 5545 /* ldi.w */, Mips::LDI_W, Convert__MSA128AsmReg1_0__ConstantSImm10_01_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_ConstantSImm10_0 }, },
6926 { 5551 /* ldl */, Mips::LDL, Convert__GPR64AsmReg1_0__Mem2_1__Tie0_1_1, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, { MCK_GPR64AsmReg, MCK_Mem }, },
6927 { 5555 /* ldpc */, Mips::LDPC, Convert__GPR64AsmReg1_0__Simm18_Lsl31_1, AMFBS_HasStdEnc_HasMips64r6, { MCK_GPR64AsmReg, MCK_Simm18_Lsl3 }, },
6928 { 5560 /* ldr */, Mips::LDR, Convert__GPR64AsmReg1_0__Mem2_1__Tie0_1_1, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, { MCK_GPR64AsmReg, MCK_Mem }, },
6929 { 5564 /* ldxc1 */, Mips::LDXC1, Convert__AFGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
6930 { 5564 /* ldxc1 */, Mips::LDXC164, Convert__FGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
6931 { 5570 /* lh */, Mips::LH, Convert__GPR32AsmReg1_0__MemOffsetSimmPtr2_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimmPtr }, },
6932 { 5570 /* lh */, Mips::LH_MM, Convert__GPR32AsmReg1_0__MemOffsetSimmPtr2_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimmPtr }, },
6933 { 5573 /* lhe */, Mips::LHE, Convert__GPR32AsmReg1_0__MemOffsetSimm9_02_1, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9_0 }, },
6934 { 5573 /* lhe */, Mips::LHE_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm9_02_1, AMFBS_InMicroMips_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9_0 }, },
6935 { 5577 /* lhu */, Mips::LHu, Convert__GPR32AsmReg1_0__MemOffsetSimmPtr2_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimmPtr }, },
6936 { 5577 /* lhu */, Mips::LHu_MM, Convert__GPR32AsmReg1_0__MemOffsetSimmPtr2_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimmPtr }, },
6937 { 5581 /* lhu16 */, Mips::LHU16_MM, Convert__GPRMM16AsmReg1_0__MicroMipsMem2_1, AMFBS_InMicroMips, { MCK_GPRMM16AsmReg, MCK_MicroMipsMem }, },
6938 { 5587 /* lhue */, Mips::LHuE, Convert__GPR32AsmReg1_0__MemOffsetSimm9_02_1, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9_0 }, },
6939 { 5587 /* lhue */, Mips::LHuE_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm9_02_1, AMFBS_InMicroMips_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9_0 }, },
6940 { 5592 /* lhx */, Mips::LHX_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
6941 { 5592 /* lhx */, Mips::LHX, Convert__GPR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
6942 { 5596 /* li */, Mips::LiRxImmX16, Convert__Reg1_0__SImm161_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_SImm16 }, },
6943 { 5596 /* li */, Mips::LoadImm32, Convert__GPR32AsmReg1_0__UImm32_Coerced1_1, AMFBS_None, { MCK_GPR32AsmReg, MCK_UImm32_Coerced }, },
6944 { 5596 /* li */, Mips::LiRxImm16, Convert__Reg1_0__SImm161_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_SImm16, MCK__HASH_, MCK_16, MCK_bit, MCK_inst }, },
6945 { 5599 /* li.d */, Mips::LoadImmDoubleGPR, Convert__GPR32AsmReg1_0__Imm1_1, AMFBS_None, { MCK_GPR32AsmReg, MCK_Imm }, },
6946 { 5599 /* li.d */, Mips::LoadImmDoubleFGR_32, Convert__StrictlyAFGR64AsmReg1_0__Imm1_1, AMFBS_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat, { MCK_StrictlyAFGR64AsmReg, MCK_Imm }, },
6947 { 5599 /* li.d */, Mips::LoadImmDoubleFGR, Convert__StrictlyFGR64AsmReg1_0__Imm1_1, AMFBS_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat, { MCK_StrictlyFGR64AsmReg, MCK_Imm }, },
6948 { 5604 /* li.s */, Mips::LoadImmSingleGPR, Convert__GPR32AsmReg1_0__Imm1_1, AMFBS_None, { MCK_GPR32AsmReg, MCK_Imm }, },
6949 { 5604 /* li.s */, Mips::LoadImmSingleFGR, Convert__StrictlyFGR32AsmReg1_0__Imm1_1, AMFBS_IsNotSoftFloat, { MCK_StrictlyFGR32AsmReg, MCK_Imm }, },
6950 { 5609 /* li16 */, Mips::LI16_MM, Convert__GPRMM16AsmReg1_0__UImm7_N11_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_UImm7_N1 }, },
6951 { 5609 /* li16 */, Mips::LI16_MMR6, Convert__GPRMM16AsmReg1_0__UImm7_N11_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_UImm7_N1 }, },
6952 { 5614 /* ll */, Mips::LL64_R6, Convert__GPR32AsmReg1_0__MemOffsetSimmPtr2_1, AMFBS_HasStdEnc_IsPTR64bit_HasMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimmPtr }, },
6953 { 5614 /* ll */, Mips::LL_R6, Convert__GPR32AsmReg1_0__MemOffsetSimmPtr2_1, AMFBS_HasStdEnc_IsPTR32bit_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimmPtr }, },
6954 { 5614 /* ll */, Mips::LL_MMR6, Convert__GPR32AsmReg1_0__MemOffsetSimm9_02_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9_0 }, },
6955 { 5614 /* ll */, Mips::LL, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_HasStdEnc_IsPTR32bit_HasMips2_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
6956 { 5614 /* ll */, Mips::LL64, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_HasStdEnc_IsPTR64bit_HasMips2_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
6957 { 5614 /* ll */, Mips::LL_MM, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_Mem }, },
6958 { 5617 /* lld */, Mips::LLD, Convert__GPR64AsmReg1_0__MemOffsetSimmPtr2_1, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips, { MCK_GPR64AsmReg, MCK_MemOffsetSimmPtr }, },
6959 { 5617 /* lld */, Mips::LLD_R6, Convert__GPR64AsmReg1_0__MemOffsetSimmPtr2_1, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_MemOffsetSimmPtr }, },
6960 { 5621 /* lle */, Mips::LLE, Convert__GPR32AsmReg1_0__MemOffsetSimm9_02_1, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9_0 }, },
6961 { 5621 /* lle */, Mips::LLE_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm9_02_1, AMFBS_InMicroMips_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9_0 }, },
6962 { 5625 /* lsa */, Mips::LSA, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__ConstantUImm2_11_3, AMFBS_HasStdEnc_HasMSA, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm2_1 }, },
6963 { 5625 /* lsa */, Mips::LSA_MMR6, Convert__GPR32AsmReg1_2__GPR32AsmReg1_1__GPR32AsmReg1_0__ConstantUImm2_11_3, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm2_1 }, },
6964 { 5625 /* lsa */, Mips::LSA_R6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__ConstantUImm2_11_3, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm2_1 }, },
6965 { 5629 /* lui */, Mips::LUI_MMR6, Convert__GPR32AsmReg1_0__UImm161_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_UImm16 }, },
6966 { 5629 /* lui */, Mips::LUi, Convert__GPR32AsmReg1_0__UImm16_Relaxed1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_UImm16_Relaxed }, },
6967 { 5629 /* lui */, Mips::LUi_MM, Convert__GPR32AsmReg1_0__UImm16_Relaxed1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_UImm16_Relaxed }, },
6968 { 5633 /* luxc1 */, Mips::LUXC1, Convert__AFGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
6969 { 5633 /* luxc1 */, Mips::LUXC164, Convert__FGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
6970 { 5633 /* luxc1 */, Mips::LUXC1_MM, Convert__FGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
6971 { 5639 /* lw */, Mips::LwRxPcTcpX16, Convert__Reg1_0__Imm1_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_Imm }, },
6972 { 5639 /* lw */, Mips::LWSP_MM, Convert__GPR32AsmReg1_0__MicroMipsMemSP2_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_MicroMipsMemSP }, },
6973 { 5639 /* lw */, Mips::LW, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
6974 { 5639 /* lw */, Mips::LWDSP, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_NotInMips16Mode_HasDSP, { MCK_GPR32AsmReg, MCK_Mem }, },
6975 { 5639 /* lw */, Mips::LWDSP_MM, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_Mem }, },
6976 { 5639 /* lw */, Mips::LW_MMR6, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_Mem }, },
6977 { 5639 /* lw */, Mips::LW_MM, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
6978 { 5639 /* lw */, Mips::LWGP_MM, Convert__GPRMM16AsmReg1_0__MicroMipsMemGP2_1, AMFBS_InMicroMips, { MCK_GPRMM16AsmReg, MCK_MicroMipsMemGP }, },
6979 { 5639 /* lw */, Mips::LwRxSpImmX16, Convert__Reg1_0__Reg1_1__SImm161_2, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16RegsPlusSP, MCK_SImm16 }, },
6980 { 5639 /* lw */, Mips::LwRxPcTcp16, Convert__Reg1_0__Imm1_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_Imm, MCK__HASH_, MCK_16, MCK_bit, MCK_inst }, },
6981 { 5642 /* lw16 */, Mips::LW16_MM, Convert__GPRMM16AsmReg1_0__MicroMipsMem2_1, AMFBS_InMicroMips, { MCK_GPRMM16AsmReg, MCK_MicroMipsMem }, },
6982 { 5647 /* lwc1 */, Mips::LWC1, Convert__FGR32AsmReg1_0__MemOffsetSimm16_02_1, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_MemOffsetSimm16_0 }, },
6983 { 5647 /* lwc1 */, Mips::LWC1_MM, Convert__FGR32AsmReg1_0__MemOffsetSimm16_02_1, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_MemOffsetSimm16_0 }, },
6984 { 5652 /* lwc2 */, Mips::LWC2_R6, Convert__COP2AsmReg1_0__MemOffsetSimm11_02_1, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_COP2AsmReg, MCK_MemOffsetSimm11_0 }, },
6985 { 5652 /* lwc2 */, Mips::LWC2_MMR6, Convert__COP2AsmReg1_0__MemOffsetSimm11_02_1, AMFBS_InMicroMips_HasMips32r6, { MCK_COP2AsmReg, MCK_MemOffsetSimm11_0 }, },
6986 { 5652 /* lwc2 */, Mips::LWC2, Convert__COP2AsmReg1_0__MemOffsetSimm16_02_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_COP2AsmReg, MCK_MemOffsetSimm16_0 }, },
6987 { 5657 /* lwc3 */, Mips::LWC3, Convert__COP3AsmReg1_0__Mem2_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_NotCnMips_NotInMicroMips, { MCK_COP3AsmReg, MCK_Mem }, },
6988 { 5662 /* lwe */, Mips::LWE, Convert__GPR32AsmReg1_0__MemOffsetSimm9_02_1, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9_0 }, },
6989 { 5662 /* lwe */, Mips::LWE_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm9_02_1, AMFBS_InMicroMips_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9_0 }, },
6990 { 5666 /* lwl */, Mips::LWL, Convert__GPR32AsmReg1_0__Mem2_1__Tie0_1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
6991 { 5666 /* lwl */, Mips::LWL_MM, Convert__GPR32AsmReg1_0__Mem2_1__Tie0_1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_Mem }, },
6992 { 5670 /* lwle */, Mips::LWLE, Convert__GPR32AsmReg1_0__MemOffsetSimm9_02_1__Tie0_1_1, AMFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9_0 }, },
6993 { 5670 /* lwle */, Mips::LWLE_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm9_02_1__Tie0_1_1, AMFBS_InMicroMips_NotMips32r6_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9_0 }, },
6994 { 5675 /* lwm */, Mips::LWM_MM, Convert__RegList1_0__Mem2_1, AMFBS_InMicroMips, { MCK_RegList, MCK_Mem }, },
6995 { 5679 /* lwm16 */, Mips::LWM16_MM, Convert__RegList161_0__MemOffsetUimm42_1, AMFBS_InMicroMips_NotMips32r6, { MCK_RegList16, MCK_MemOffsetUimm4 }, },
6996 { 5679 /* lwm16 */, Mips::LWM16_MMR6, Convert__RegList161_0__MemOffsetUimm42_1, AMFBS_InMicroMips_HasMips32r6, { MCK_RegList16, MCK_MemOffsetUimm4 }, },
6997 { 5685 /* lwm32 */, Mips::LWM32_MM, Convert__RegList1_0__Mem2_1, AMFBS_InMicroMips, { MCK_RegList, MCK_Mem }, },
6998 { 5691 /* lwp */, Mips::LWP_MM, ConvertCustom_ConvertXWPOperands, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm12_0 }, },
6999 { 5695 /* lwpc */, Mips::LWPC, Convert__GPR32AsmReg1_0__Simm19_Lsl21_1, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR32AsmReg, MCK_Simm19_Lsl2 }, },
7000 { 5695 /* lwpc */, Mips::LWPC_MMR6, Convert__GPR32AsmReg1_0__Simm19_Lsl21_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_Simm19_Lsl2 }, },
7001 { 5700 /* lwr */, Mips::LWR, Convert__GPR32AsmReg1_0__Mem2_1__Tie0_1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
7002 { 5700 /* lwr */, Mips::LWR_MM, Convert__GPR32AsmReg1_0__Mem2_1__Tie0_1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_Mem }, },
7003 { 5704 /* lwre */, Mips::LWRE, Convert__GPR32AsmReg1_0__MemOffsetSimm9_02_1__Tie0_1_1, AMFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9_0 }, },
7004 { 5704 /* lwre */, Mips::LWRE_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm9_02_1__Tie0_1_1, AMFBS_InMicroMips_NotMips32r6_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9_0 }, },
7005 { 5709 /* lwu */, Mips::LWU_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm12_02_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_MemOffsetSimm12_0 }, },
7006 { 5709 /* lwu */, Mips::LWu, Convert__GPR64AsmReg1_0__Mem2_1, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_Mem }, },
7007 { 5713 /* lwupc */, Mips::LWUPC, Convert__GPR32AsmReg1_0__Simm19_Lsl21_1, AMFBS_HasStdEnc_HasMips64r6, { MCK_GPR32AsmReg, MCK_Simm19_Lsl2 }, },
7008 { 5719 /* lwx */, Mips::LWX_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
7009 { 5719 /* lwx */, Mips::LWX, Convert__GPR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
7010 { 5723 /* lwxc1 */, Mips::LWXC1, Convert__FGR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
7011 { 5723 /* lwxc1 */, Mips::LWXC1_MM, Convert__FGR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
7012 { 5729 /* lwxs */, Mips::LWXS_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
7013 { 5734 /* madd */, Mips::MADD, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7014 { 5734 /* madd */, Mips::MADD_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7015 { 5734 /* madd */, Mips::MADD_DSP_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7016 { 5734 /* madd */, Mips::MADD_DSP, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7017 { 5739 /* madd.d */, Mips::MADD_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2__AFGR64AsmReg1_3, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
7018 { 5739 /* madd.d */, Mips::MADD_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2__AFGR64AsmReg1_3, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat_HasMadd4, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
7019 { 5739 /* madd.d */, Mips::MADD_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2__FGR64AsmReg1_3, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7020 { 5746 /* madd.s */, Mips::MADD_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2__FGR32AsmReg1_3, AMFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7021 { 5746 /* madd.s */, Mips::MADD_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2__FGR32AsmReg1_3, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat_HasMadd4, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7022 { 5753 /* madd_q.h */, Mips::MADD_Q_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7023 { 5762 /* madd_q.w */, Mips::MADD_Q_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7024 { 5771 /* maddf.d */, Mips::MADDF_D, Convert__FGR64AsmReg1_0__Tie0_1_1__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7025 { 5771 /* maddf.d */, Mips::MADDF_D_MMR6, Convert__FGR64AsmReg1_0__Tie0_1_1__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7026 { 5779 /* maddf.s */, Mips::MADDF_S, Convert__FGR32AsmReg1_0__Tie0_1_1__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7027 { 5779 /* maddf.s */, Mips::MADDF_S_MMR6, Convert__FGR32AsmReg1_0__Tie0_1_1__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7028 { 5787 /* maddr_q.h */, Mips::MADDR_Q_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7029 { 5797 /* maddr_q.w */, Mips::MADDR_Q_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7030 { 5807 /* maddu */, Mips::MADDU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7031 { 5807 /* maddu */, Mips::MADDU_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7032 { 5807 /* maddu */, Mips::MADDU_DSP_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7033 { 5807 /* maddu */, Mips::MADDU_DSP, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7034 { 5813 /* maddv.b */, Mips::MADDV_B, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7035 { 5821 /* maddv.d */, Mips::MADDV_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7036 { 5829 /* maddv.h */, Mips::MADDV_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7037 { 5837 /* maddv.w */, Mips::MADDV_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7038 { 5845 /* maq_s.w.phl */, Mips::MAQ_S_W_PHL_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7039 { 5845 /* maq_s.w.phl */, Mips::MAQ_S_W_PHL, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7040 { 5857 /* maq_s.w.phr */, Mips::MAQ_S_W_PHR_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7041 { 5857 /* maq_s.w.phr */, Mips::MAQ_S_W_PHR, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7042 { 5869 /* maq_sa.w.phl */, Mips::MAQ_SA_W_PHL_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7043 { 5869 /* maq_sa.w.phl */, Mips::MAQ_SA_W_PHL, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7044 { 5882 /* maq_sa.w.phr */, Mips::MAQ_SA_W_PHR_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7045 { 5882 /* maq_sa.w.phr */, Mips::MAQ_SA_W_PHR, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7046 { 5895 /* max.d */, Mips::MAX_D, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7047 { 5895 /* max.d */, Mips::MAX_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7048 { 5901 /* max.s */, Mips::MAX_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7049 { 5901 /* max.s */, Mips::MAX_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7050 { 5907 /* max_a.b */, Mips::MAX_A_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7051 { 5915 /* max_a.d */, Mips::MAX_A_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7052 { 5923 /* max_a.h */, Mips::MAX_A_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7053 { 5931 /* max_a.w */, Mips::MAX_A_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7054 { 5939 /* max_s.b */, Mips::MAX_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7055 { 5947 /* max_s.d */, Mips::MAX_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7056 { 5955 /* max_s.h */, Mips::MAX_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7057 { 5963 /* max_s.w */, Mips::MAX_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7058 { 5971 /* max_u.b */, Mips::MAX_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7059 { 5979 /* max_u.d */, Mips::MAX_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7060 { 5987 /* max_u.h */, Mips::MAX_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7061 { 5995 /* max_u.w */, Mips::MAX_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7062 { 6003 /* maxa.d */, Mips::MAXA_D, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7063 { 6003 /* maxa.d */, Mips::MAXA_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7064 { 6010 /* maxa.s */, Mips::MAXA_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7065 { 6010 /* maxa.s */, Mips::MAXA_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7066 { 6017 /* maxi_s.b */, Mips::MAXI_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
7067 { 6026 /* maxi_s.d */, Mips::MAXI_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
7068 { 6035 /* maxi_s.h */, Mips::MAXI_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
7069 { 6044 /* maxi_s.w */, Mips::MAXI_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
7070 { 6053 /* maxi_u.b */, Mips::MAXI_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
7071 { 6062 /* maxi_u.d */, Mips::MAXI_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
7072 { 6071 /* maxi_u.h */, Mips::MAXI_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
7073 { 6080 /* maxi_u.w */, Mips::MAXI_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
7074 { 6089 /* mfc0 */, Mips::MFC0, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__imm_95_0, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, },
7075 { 6089 /* mfc0 */, Mips::MFC0_MM, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__imm_95_0, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, },
7076 { 6089 /* mfc0 */, Mips::MFC0_MMR6, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__imm_95_0, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, },
7077 { 6089 /* mfc0 */, Mips::MFC0, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
7078 { 6089 /* mfc0 */, Mips::MFC0_MM, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
7079 { 6089 /* mfc0 */, Mips::MFC0_MMR6, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
7080 { 6094 /* mfc1 */, Mips::MFC1, Convert__GPR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, { MCK_GPR32AsmReg, MCK_FGR32AsmReg }, },
7081 { 6094 /* mfc1 */, Mips::MFC1_MMR6, Convert__GPR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_FGR32AsmReg }, },
7082 { 6094 /* mfc1 */, Mips::MFC1_MM, Convert__GPR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_FGR32AsmReg }, },
7083 { 6094 /* mfc1 */, Mips::MFC1_D64, Convert__GPR32AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips, { MCK_GPR32AsmReg, MCK_FGR64AsmReg }, },
7084 { 6099 /* mfc2 */, Mips::MFC2_MMR6, Convert__GPR32AsmReg1_0__COP2AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP2AsmReg }, },
7085 { 6099 /* mfc2 */, Mips::MFC2, Convert__GPR32AsmReg1_0__COP2AsmReg1_1__imm_95_0, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP2AsmReg }, },
7086 { 6099 /* mfc2 */, Mips::MFC2, Convert__GPR32AsmReg1_0__COP2AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP2AsmReg, MCK_ConstantUImm3_0 }, },
7087 { 6104 /* mfgc0 */, Mips::MFGC0, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__imm_95_0, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, },
7088 { 6104 /* mfgc0 */, Mips::MFGC0_MM, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__imm_95_0, AMFBS_InMicroMips_HasMips32r5_HasVirt, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, },
7089 { 6104 /* mfgc0 */, Mips::MFGC0, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
7090 { 6104 /* mfgc0 */, Mips::MFGC0_MM, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2, AMFBS_InMicroMips_HasMips32r5_HasVirt, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
7091 { 6110 /* mfhc0 */, Mips::MFHC0_MMR6, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__imm_95_0, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, },
7092 { 6110 /* mfhc0 */, Mips::MFHC0_MMR6, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
7093 { 6116 /* mfhc1 */, Mips::MFHC1_D32, Convert__GPR32AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips32r2_IsNotSoftFloat_NotInMicroMips, { MCK_GPR32AsmReg, MCK_AFGR64AsmReg }, },
7094 { 6116 /* mfhc1 */, Mips::MFHC1_D32_MM, Convert__GPR32AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_AFGR64AsmReg }, },
7095 { 6116 /* mfhc1 */, Mips::MFHC1_D64, Convert__GPR32AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips32r2_IsNotSoftFloat_NotInMicroMips, { MCK_GPR32AsmReg, MCK_FGR64AsmReg }, },
7096 { 6116 /* mfhc1 */, Mips::MFHC1_D64_MM, Convert__GPR32AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_FGR64AsmReg }, },
7097 { 6122 /* mfhc2 */, Mips::MFHC2_MMR6, Convert__GPR32AsmReg1_0__COP2AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP2AsmReg }, },
7098 { 6128 /* mfhgc0 */, Mips::MFHGC0, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__imm_95_0, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, },
7099 { 6128 /* mfhgc0 */, Mips::MFHGC0_MM, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__imm_95_0, AMFBS_InMicroMips_HasMips32r5_HasVirt, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, },
7100 { 6128 /* mfhgc0 */, Mips::MFHGC0, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
7101 { 6128 /* mfhgc0 */, Mips::MFHGC0_MM, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2, AMFBS_InMicroMips_HasMips32r5_HasVirt, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
7102 { 6135 /* mfhi */, Mips::Mfhi16, Convert__Reg1_0, AMFBS_InMips16Mode, { MCK_CPU16Regs }, },
7103 { 6135 /* mfhi */, Mips::MFHI, Convert__GPR32AsmReg1_0, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg }, },
7104 { 6135 /* mfhi */, Mips::MFHI_MM, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg }, },
7105 { 6135 /* mfhi */, Mips::MFHI_DSP_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, },
7106 { 6135 /* mfhi */, Mips::MFHI_DSP, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, },
7107 { 6140 /* mfhi16 */, Mips::MFHI16_MM, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg }, },
7108 { 6147 /* mflo */, Mips::Mflo16, Convert__Reg1_0, AMFBS_InMips16Mode, { MCK_CPU16Regs }, },
7109 { 6147 /* mflo */, Mips::MFLO, Convert__GPR32AsmReg1_0, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg }, },
7110 { 6147 /* mflo */, Mips::MFLO_MM, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg }, },
7111 { 6147 /* mflo */, Mips::MFLO_DSP_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, },
7112 { 6147 /* mflo */, Mips::MFLO_DSP, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, },
7113 { 6152 /* mflo16 */, Mips::MFLO16_MM, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg }, },
7114 { 6159 /* mftacx */, Mips::MFTACX, Convert__GPR32AsmReg1_0__regAC0, AMFBS_HasMT_NotInMicroMips, { MCK_GPR32AsmReg }, },
7115 { 6159 /* mftacx */, Mips::MFTACX, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1, AMFBS_HasMT, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, },
7116 { 6166 /* mftc0 */, Mips::MFTC0, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__imm_95_0, AMFBS_HasMT_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, },
7117 { 6166 /* mftc0 */, Mips::MFTC0, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasMT, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
7118 { 6172 /* mftc1 */, Mips::MFTC1, Convert__GPR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasMT, { MCK_GPR32AsmReg, MCK_FGR32AsmReg }, },
7119 { 6178 /* mftdsp */, Mips::MFTDSP, Convert__GPR32AsmReg1_0, AMFBS_HasMT, { MCK_GPR32AsmReg }, },
7120 { 6185 /* mftgpr */, Mips::MFTGPR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, AMFBS_HasMT, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7121 { 6192 /* mfthc1 */, Mips::MFTHC1, Convert__GPR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasMT, { MCK_GPR32AsmReg, MCK_FGR32AsmReg }, },
7122 { 6199 /* mfthi */, Mips::MFTHI, Convert__GPR32AsmReg1_0__regAC0, AMFBS_HasMT_NotInMicroMips, { MCK_GPR32AsmReg }, },
7123 { 6199 /* mfthi */, Mips::MFTHI, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1, AMFBS_HasMT, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, },
7124 { 6205 /* mftlo */, Mips::MFTLO, Convert__GPR32AsmReg1_0__regAC0, AMFBS_HasMT_NotInMicroMips, { MCK_GPR32AsmReg }, },
7125 { 6205 /* mftlo */, Mips::MFTLO, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1, AMFBS_HasMT, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, },
7126 { 6211 /* mftr */, Mips::MFTR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm1_01_2__ConstantUImm3_01_3__ConstantUImm1_01_4, AMFBS_HasStdEnc_HasMT_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm1_0, MCK_ConstantUImm3_0, MCK_ConstantUImm1_0 }, },
7127 { 6216 /* min.d */, Mips::MIN_D, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7128 { 6216 /* min.d */, Mips::MIN_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7129 { 6222 /* min.s */, Mips::MIN_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7130 { 6222 /* min.s */, Mips::MIN_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7131 { 6228 /* min_a.b */, Mips::MIN_A_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7132 { 6236 /* min_a.d */, Mips::MIN_A_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7133 { 6244 /* min_a.h */, Mips::MIN_A_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7134 { 6252 /* min_a.w */, Mips::MIN_A_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7135 { 6260 /* min_s.b */, Mips::MIN_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7136 { 6268 /* min_s.d */, Mips::MIN_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7137 { 6276 /* min_s.h */, Mips::MIN_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7138 { 6284 /* min_s.w */, Mips::MIN_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7139 { 6292 /* min_u.b */, Mips::MIN_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7140 { 6300 /* min_u.d */, Mips::MIN_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7141 { 6308 /* min_u.h */, Mips::MIN_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7142 { 6316 /* min_u.w */, Mips::MIN_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7143 { 6324 /* mina.d */, Mips::MINA_D, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7144 { 6324 /* mina.d */, Mips::MINA_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7145 { 6331 /* mina.s */, Mips::MINA_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7146 { 6331 /* mina.s */, Mips::MINA_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7147 { 6338 /* mini_s.b */, Mips::MINI_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
7148 { 6347 /* mini_s.d */, Mips::MINI_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
7149 { 6356 /* mini_s.h */, Mips::MINI_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
7150 { 6365 /* mini_s.w */, Mips::MINI_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
7151 { 6374 /* mini_u.b */, Mips::MINI_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
7152 { 6383 /* mini_u.d */, Mips::MINI_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
7153 { 6392 /* mini_u.h */, Mips::MINI_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
7154 { 6401 /* mini_u.w */, Mips::MINI_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
7155 { 6410 /* mod */, Mips::MOD, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7156 { 6410 /* mod */, Mips::MOD_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7157 { 6414 /* mod_s.b */, Mips::MOD_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7158 { 6422 /* mod_s.d */, Mips::MOD_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7159 { 6430 /* mod_s.h */, Mips::MOD_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7160 { 6438 /* mod_s.w */, Mips::MOD_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7161 { 6446 /* mod_u.b */, Mips::MOD_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7162 { 6454 /* mod_u.d */, Mips::MOD_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7163 { 6462 /* mod_u.h */, Mips::MOD_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7164 { 6470 /* mod_u.w */, Mips::MOD_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7165 { 6478 /* modsub */, Mips::MODSUB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7166 { 6478 /* modsub */, Mips::MODSUB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7167 { 6485 /* modu */, Mips::MODU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7168 { 6485 /* modu */, Mips::MODU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7169 { 6490 /* mov.d */, Mips::FMOV_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
7170 { 6490 /* mov.d */, Mips::FMOV_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
7171 { 6490 /* mov.d */, Mips::FMOV_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7172 { 6490 /* mov.d */, Mips::FMOV_D64_MM, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7173 { 6490 /* mov.d */, Mips::FMOV_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7174 { 6496 /* mov.s */, Mips::FMOV_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7175 { 6496 /* mov.s */, Mips::FMOV_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7176 { 6496 /* mov.s */, Mips::FMOV_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7177 { 6502 /* move */, Mips::MoveR3216, Convert__Reg1_0__Reg1_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_DSPR }, },
7178 { 6502 /* move */, Mips::Move32R16, Convert__Reg1_0__Reg1_1, AMFBS_InMips16Mode, { MCK_DSPR, MCK_CPU16Regs }, },
7179 { 6502 /* move */, Mips::OR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__regZERO, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7180 { 6502 /* move */, Mips::ADDu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__regZERO, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7181 { 6502 /* move */, Mips::MOVE16_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7182 { 6502 /* move */, Mips::OR64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__regZERO_64, AMFBS_IsGP64bit_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
7183 { 6502 /* move */, Mips::DADDu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__regZERO_64, AMFBS_IsGP64bit_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
7184 { 6507 /* move.v */, Mips::MOVE_V, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7185 { 6514 /* move16 */, Mips::MOVE16_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7186 { 6521 /* movep */, Mips::MOVEP_MM, Convert__GPRMM16AsmRegMovePPairFirst1_0__GPRMM16AsmRegMovePPairSecond1_1__GPRMM16AsmRegMoveP1_2__GPRMM16AsmRegMoveP1_3, AMFBS_InMicroMips_NotMips32r6, { MCK_GPRMM16AsmRegMovePPairFirst, MCK_GPRMM16AsmRegMovePPairSecond, MCK_GPRMM16AsmRegMoveP, MCK_GPRMM16AsmRegMoveP }, },
7187 { 6521 /* movep */, Mips::MOVEP_MMR6, Convert__GPRMM16AsmRegMovePPairFirst1_0__GPRMM16AsmRegMovePPairSecond1_1__GPRMM16AsmRegMoveP1_2__GPRMM16AsmRegMoveP1_3, AMFBS_InMicroMips_HasMips32r6, { MCK_GPRMM16AsmRegMovePPairFirst, MCK_GPRMM16AsmRegMovePPairSecond, MCK_GPRMM16AsmRegMoveP, MCK_GPRMM16AsmRegMoveP }, },
7188 { 6527 /* movf */, Mips::MOVF_I, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_FCCAsmReg }, },
7189 { 6527 /* movf */, Mips::MOVF_I_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_FCCAsmReg }, },
7190 { 6532 /* movf.d */, Mips::MOVF_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_FCCAsmReg }, },
7191 { 6532 /* movf.d */, Mips::MOVF_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_FCCAsmReg }, },
7192 { 6532 /* movf.d */, Mips::MOVF_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FCCAsmReg }, },
7193 { 6539 /* movf.s */, Mips::MOVF_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FCCAsmReg }, },
7194 { 6539 /* movf.s */, Mips::MOVF_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FCCAsmReg }, },
7195 { 6546 /* movn */, Mips::MOVN_I_I, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7196 { 6546 /* movn */, Mips::MOVN_I_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7197 { 6551 /* movn.d */, Mips::MOVN_I_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_GPR32AsmReg }, },
7198 { 6551 /* movn.d */, Mips::MOVN_I_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_GPR32AsmReg }, },
7199 { 6551 /* movn.d */, Mips::MOVN_I_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_GPR32AsmReg }, },
7200 { 6558 /* movn.s */, Mips::MOVN_I_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_GPR32AsmReg }, },
7201 { 6558 /* movn.s */, Mips::MOVN_I_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_GPR32AsmReg }, },
7202 { 6565 /* movt */, Mips::MOVT_I, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_FCCAsmReg }, },
7203 { 6565 /* movt */, Mips::MOVT_I_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_FCCAsmReg }, },
7204 { 6570 /* movt.d */, Mips::MOVT_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_FCCAsmReg }, },
7205 { 6570 /* movt.d */, Mips::MOVT_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_FCCAsmReg }, },
7206 { 6570 /* movt.d */, Mips::MOVT_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FCCAsmReg }, },
7207 { 6577 /* movt.s */, Mips::MOVT_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FCCAsmReg }, },
7208 { 6577 /* movt.s */, Mips::MOVT_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FCCAsmReg }, },
7209 { 6584 /* movz */, Mips::MOVZ_I_I, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7210 { 6584 /* movz */, Mips::MOVZ_I_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7211 { 6589 /* movz.d */, Mips::MOVZ_I_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_GPR32AsmReg }, },
7212 { 6589 /* movz.d */, Mips::MOVZ_I_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_GPR32AsmReg }, },
7213 { 6589 /* movz.d */, Mips::MOVZ_I_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_GPR32AsmReg }, },
7214 { 6596 /* movz.s */, Mips::MOVZ_I_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_GPR32AsmReg }, },
7215 { 6596 /* movz.s */, Mips::MOVZ_I_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_GPR32AsmReg }, },
7216 { 6603 /* msub */, Mips::MSUB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7217 { 6603 /* msub */, Mips::MSUB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7218 { 6603 /* msub */, Mips::MSUB_DSP_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7219 { 6603 /* msub */, Mips::MSUB_DSP, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7220 { 6608 /* msub.d */, Mips::MSUB_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2__AFGR64AsmReg1_3, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
7221 { 6608 /* msub.d */, Mips::MSUB_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2__AFGR64AsmReg1_3, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat_HasMadd4, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
7222 { 6608 /* msub.d */, Mips::MSUB_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2__FGR64AsmReg1_3, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7223 { 6615 /* msub.s */, Mips::MSUB_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2__FGR32AsmReg1_3, AMFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7224 { 6615 /* msub.s */, Mips::MSUB_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2__FGR32AsmReg1_3, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat_HasMadd4, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7225 { 6622 /* msub_q.h */, Mips::MSUB_Q_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7226 { 6631 /* msub_q.w */, Mips::MSUB_Q_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7227 { 6640 /* msubf.d */, Mips::MSUBF_D, Convert__FGR64AsmReg1_0__Tie0_1_1__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7228 { 6640 /* msubf.d */, Mips::MSUBF_D_MMR6, Convert__FGR64AsmReg1_0__Tie0_1_1__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7229 { 6648 /* msubf.s */, Mips::MSUBF_S, Convert__FGR32AsmReg1_0__Tie0_1_1__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7230 { 6648 /* msubf.s */, Mips::MSUBF_S_MMR6, Convert__FGR32AsmReg1_0__Tie0_1_1__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7231 { 6656 /* msubr_q.h */, Mips::MSUBR_Q_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7232 { 6666 /* msubr_q.w */, Mips::MSUBR_Q_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7233 { 6676 /* msubu */, Mips::MSUBU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7234 { 6676 /* msubu */, Mips::MSUBU_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7235 { 6676 /* msubu */, Mips::MSUBU_DSP_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7236 { 6676 /* msubu */, Mips::MSUBU_DSP, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7237 { 6682 /* msubv.b */, Mips::MSUBV_B, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7238 { 6690 /* msubv.d */, Mips::MSUBV_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7239 { 6698 /* msubv.h */, Mips::MSUBV_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7240 { 6706 /* msubv.w */, Mips::MSUBV_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7241 { 6714 /* mtc0 */, Mips::MTC0, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__imm_95_0, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, },
7242 { 6714 /* mtc0 */, Mips::MTC0_MM, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__imm_95_0, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, },
7243 { 6714 /* mtc0 */, Mips::MTC0_MMR6, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__imm_95_0, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, },
7244 { 6714 /* mtc0 */, Mips::MTC0, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
7245 { 6714 /* mtc0 */, Mips::MTC0_MM, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
7246 { 6714 /* mtc0 */, Mips::MTC0_MMR6, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
7247 { 6719 /* mtc1 */, Mips::MTC1, Convert__FGR32AsmReg1_1__GPR32AsmReg1_0, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, { MCK_GPR32AsmReg, MCK_FGR32AsmReg }, },
7248 { 6719 /* mtc1 */, Mips::MTC1_MMR6, Convert__FGR32AsmReg1_1__GPR32AsmReg1_0, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_FGR32AsmReg }, },
7249 { 6719 /* mtc1 */, Mips::MTC1_MM, Convert__FGR32AsmReg1_1__GPR32AsmReg1_0, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_FGR32AsmReg }, },
7250 { 6719 /* mtc1 */, Mips::MTC1_D64, Convert__FGR64AsmReg1_1__GPR32AsmReg1_0, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips, { MCK_GPR32AsmReg, MCK_FGR64AsmReg }, },
7251 { 6719 /* mtc1 */, Mips::MTC1_D64_MM, Convert__FGR64AsmReg1_1__GPR32AsmReg1_0, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_FGR64AsmReg }, },
7252 { 6724 /* mtc2 */, Mips::MTC2_MMR6, Convert__COP2AsmReg1_1__GPR32AsmReg1_0, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP2AsmReg }, },
7253 { 6724 /* mtc2 */, Mips::MTC2, Convert__COP2AsmReg1_1__GPR32AsmReg1_0__imm_95_0, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP2AsmReg }, },
7254 { 6724 /* mtc2 */, Mips::MTC2, Convert__COP2AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP2AsmReg, MCK_ConstantUImm3_0 }, },
7255 { 6729 /* mtgc0 */, Mips::MTGC0, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__imm_95_0, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, },
7256 { 6729 /* mtgc0 */, Mips::MTGC0_MM, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__imm_95_0, AMFBS_InMicroMips_HasMips32r5_HasVirt, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, },
7257 { 6729 /* mtgc0 */, Mips::MTGC0, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
7258 { 6729 /* mtgc0 */, Mips::MTGC0_MM, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2, AMFBS_InMicroMips_HasMips32r5_HasVirt, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
7259 { 6735 /* mthc0 */, Mips::MTHC0_MMR6, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__imm_95_0, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, },
7260 { 6735 /* mthc0 */, Mips::MTHC0_MMR6, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
7261 { 6741 /* mthc1 */, Mips::MTHC1_D32, Convert__AFGR64AsmReg1_1__Tie0_1_1__GPR32AsmReg1_0, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips32r2_IsNotSoftFloat_NotInMicroMips, { MCK_GPR32AsmReg, MCK_AFGR64AsmReg }, },
7262 { 6741 /* mthc1 */, Mips::MTHC1_D32_MM, Convert__AFGR64AsmReg1_1__Tie0_1_1__GPR32AsmReg1_0, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_AFGR64AsmReg }, },
7263 { 6741 /* mthc1 */, Mips::MTHC1_D64, Convert__FGR64AsmReg1_1__Tie0_1_1__GPR32AsmReg1_0, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips32r2_IsNotSoftFloat_NotInMicroMips, { MCK_GPR32AsmReg, MCK_FGR64AsmReg }, },
7264 { 6741 /* mthc1 */, Mips::MTHC1_D64_MM, Convert__FGR64AsmReg1_1__Tie0_1_1__GPR32AsmReg1_0, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_FGR64AsmReg }, },
7265 { 6747 /* mthc2 */, Mips::MTHC2_MMR6, Convert__COP2AsmReg1_1__GPR32AsmReg1_0, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP2AsmReg }, },
7266 { 6753 /* mthgc0 */, Mips::MTHGC0, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__imm_95_0, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, },
7267 { 6753 /* mthgc0 */, Mips::MTHGC0_MM, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__imm_95_0, AMFBS_InMicroMips_HasMips32r5_HasVirt, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, },
7268 { 6753 /* mthgc0 */, Mips::MTHGC0, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
7269 { 6753 /* mthgc0 */, Mips::MTHGC0_MM, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2, AMFBS_InMicroMips_HasMips32r5_HasVirt, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
7270 { 6760 /* mthi */, Mips::MTHI, Convert__GPR32AsmReg1_0, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg }, },
7271 { 6760 /* mthi */, Mips::MTHI_MM, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg }, },
7272 { 6760 /* mthi */, Mips::MTHI_DSP_MM, Convert__HI32DSPAsmReg1_1__GPR32AsmReg1_0, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_HI32DSPAsmReg }, },
7273 { 6760 /* mthi */, Mips::MTHI_DSP, Convert__HI32DSPAsmReg1_1__GPR32AsmReg1_0, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_HI32DSPAsmReg }, },
7274 { 6765 /* mthlip */, Mips::MTHLIP_MM, Convert__ACC64DSPAsmReg1_1__GPR32AsmReg1_0__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, },
7275 { 6765 /* mthlip */, Mips::MTHLIP, Convert__ACC64DSPAsmReg1_1__GPR32AsmReg1_0__Tie0_1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, },
7276 { 6772 /* mtlo */, Mips::MTLO, Convert__GPR32AsmReg1_0, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg }, },
7277 { 6772 /* mtlo */, Mips::MTLO_MM, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg }, },
7278 { 6772 /* mtlo */, Mips::MTLO_DSP_MM, Convert__LO32DSPAsmReg1_1__GPR32AsmReg1_0, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_LO32DSPAsmReg }, },
7279 { 6772 /* mtlo */, Mips::MTLO_DSP, Convert__LO32DSPAsmReg1_1__GPR32AsmReg1_0, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_LO32DSPAsmReg }, },
7280 { 6777 /* mtm0 */, Mips::MTM0, Convert__GPR64AsmReg1_0, AMFBS_HasCnMips, { MCK_GPR64AsmReg }, },
7281 { 6782 /* mtm1 */, Mips::MTM1, Convert__GPR64AsmReg1_0, AMFBS_HasCnMips, { MCK_GPR64AsmReg }, },
7282 { 6787 /* mtm2 */, Mips::MTM2, Convert__GPR64AsmReg1_0, AMFBS_HasCnMips, { MCK_GPR64AsmReg }, },
7283 { 6792 /* mtp0 */, Mips::MTP0, Convert__GPR64AsmReg1_0, AMFBS_HasCnMips, { MCK_GPR64AsmReg }, },
7284 { 6797 /* mtp1 */, Mips::MTP1, Convert__GPR64AsmReg1_0, AMFBS_HasCnMips, { MCK_GPR64AsmReg }, },
7285 { 6802 /* mtp2 */, Mips::MTP2, Convert__GPR64AsmReg1_0, AMFBS_HasCnMips, { MCK_GPR64AsmReg }, },
7286 { 6807 /* mttacx */, Mips::MTTACX, Convert__regAC0__GPR32AsmReg1_0, AMFBS_HasMT_NotInMicroMips, { MCK_GPR32AsmReg }, },
7287 { 6807 /* mttacx */, Mips::MTTACX, Convert__ACC64DSPAsmReg1_1__GPR32AsmReg1_0, AMFBS_HasMT, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, },
7288 { 6814 /* mttc0 */, Mips::MTTC0, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__imm_95_0, AMFBS_HasMT_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, },
7289 { 6814 /* mttc0 */, Mips::MTTC0, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2, AMFBS_HasMT, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
7290 { 6820 /* mttc1 */, Mips::MTTC1, Convert__FGR32AsmReg1_1__GPR32AsmReg1_0, AMFBS_HasMT, { MCK_GPR32AsmReg, MCK_FGR32AsmReg }, },
7291 { 6826 /* mttdsp */, Mips::MTTDSP, Convert__GPR32AsmReg1_0, AMFBS_HasMT, { MCK_GPR32AsmReg }, },
7292 { 6833 /* mttgpr */, Mips::MTTGPR, Convert__GPR32AsmReg1_1__GPR32AsmReg1_0, AMFBS_HasMT, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7293 { 6840 /* mtthc1 */, Mips::MTTHC1, Convert__FGR32AsmReg1_1__GPR32AsmReg1_0, AMFBS_HasMT, { MCK_GPR32AsmReg, MCK_FGR32AsmReg }, },
7294 { 6847 /* mtthi */, Mips::MTTHI, Convert__regAC0__GPR32AsmReg1_0, AMFBS_HasMT_NotInMicroMips, { MCK_GPR32AsmReg }, },
7295 { 6847 /* mtthi */, Mips::MTTHI, Convert__ACC64DSPAsmReg1_1__GPR32AsmReg1_0, AMFBS_HasMT, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, },
7296 { 6853 /* mttlo */, Mips::MTTLO, Convert__regAC0__GPR32AsmReg1_0, AMFBS_HasMT_NotInMicroMips, { MCK_GPR32AsmReg }, },
7297 { 6853 /* mttlo */, Mips::MTTLO, Convert__ACC64DSPAsmReg1_1__GPR32AsmReg1_0, AMFBS_HasMT, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, },
7298 { 6859 /* mttr */, Mips::MTTR, Convert__GPR32AsmReg1_1__GPR32AsmReg1_0__ConstantUImm1_01_2__ConstantUImm3_01_3__ConstantUImm1_01_4, AMFBS_HasStdEnc_HasMT_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm1_0, MCK_ConstantUImm3_0, MCK_ConstantUImm1_0 }, },
7299 { 6864 /* muh */, Mips::MUH_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7300 { 6864 /* muh */, Mips::MUH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7301 { 6864 /* muh */, Mips::MUH_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7302 { 6868 /* muhu */, Mips::MUHU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7303 { 6868 /* muhu */, Mips::MUHU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7304 { 6868 /* muhu */, Mips::MUHU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7305 { 6873 /* mul */, Mips::MUL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7306 { 6873 /* mul */, Mips::MUL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7307 { 6873 /* mul */, Mips::MUL_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7308 { 6873 /* mul */, Mips::MUL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7309 { 6873 /* mul */, Mips::MUL_R6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7310 { 6873 /* mul */, Mips::MUL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7311 { 6873 /* mul */, Mips::MUL_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7312 { 6873 /* mul */, Mips::MULImmMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
7313 { 6877 /* mul.d */, Mips::FMUL_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
7314 { 6877 /* mul.d */, Mips::FMUL_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
7315 { 6877 /* mul.d */, Mips::FMUL_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7316 { 6877 /* mul.d */, Mips::FMUL_D64_MM, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7317 { 6883 /* mul.ph */, Mips::MUL_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7318 { 6883 /* mul.ph */, Mips::MUL_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7319 { 6890 /* mul.ps */, Mips::FMUL_PS64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7320 { 6897 /* mul.s */, Mips::FMUL_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7321 { 6897 /* mul.s */, Mips::FMUL_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_2__FGR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7322 { 6897 /* mul.s */, Mips::FMUL_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7323 { 6903 /* mul_q.h */, Mips::MUL_Q_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7324 { 6911 /* mul_q.w */, Mips::MUL_Q_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7325 { 6919 /* mul_s.ph */, Mips::MUL_S_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7326 { 6919 /* mul_s.ph */, Mips::MUL_S_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7327 { 6928 /* muleq_s.w.phl */, Mips::MULEQ_S_W_PHL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7328 { 6928 /* muleq_s.w.phl */, Mips::MULEQ_S_W_PHL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7329 { 6942 /* muleq_s.w.phr */, Mips::MULEQ_S_W_PHR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7330 { 6942 /* muleq_s.w.phr */, Mips::MULEQ_S_W_PHR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7331 { 6956 /* muleu_s.ph.qbl */, Mips::MULEU_S_PH_QBL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7332 { 6956 /* muleu_s.ph.qbl */, Mips::MULEU_S_PH_QBL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7333 { 6971 /* muleu_s.ph.qbr */, Mips::MULEU_S_PH_QBR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7334 { 6971 /* muleu_s.ph.qbr */, Mips::MULEU_S_PH_QBR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7335 { 6986 /* mulo */, Mips::MULOMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7336 { 6986 /* mulo */, Mips::MULOMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7337 { 6991 /* mulou */, Mips::MULOUMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7338 { 6991 /* mulou */, Mips::MULOUMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7339 { 6997 /* mulq_rs.ph */, Mips::MULQ_RS_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7340 { 6997 /* mulq_rs.ph */, Mips::MULQ_RS_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7341 { 7008 /* mulq_rs.w */, Mips::MULQ_RS_W_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7342 { 7008 /* mulq_rs.w */, Mips::MULQ_RS_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7343 { 7018 /* mulq_s.ph */, Mips::MULQ_S_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7344 { 7018 /* mulq_s.ph */, Mips::MULQ_S_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7345 { 7028 /* mulq_s.w */, Mips::MULQ_S_W_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7346 { 7028 /* mulq_s.w */, Mips::MULQ_S_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7347 { 7037 /* mulr.ps */, Mips::MULR_PS64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMips3D, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7348 { 7045 /* mulr_q.h */, Mips::MULR_Q_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7349 { 7054 /* mulr_q.w */, Mips::MULR_Q_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7350 { 7063 /* mulsa.w.ph */, Mips::MULSA_W_PH_MMR2, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7351 { 7063 /* mulsa.w.ph */, Mips::MULSA_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7352 { 7074 /* mulsaq_s.w.ph */, Mips::MULSAQ_S_W_PH_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7353 { 7074 /* mulsaq_s.w.ph */, Mips::MULSAQ_S_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7354 { 7088 /* mult */, Mips::MULT, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7355 { 7088 /* mult */, Mips::MULT_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7356 { 7088 /* mult */, Mips::MULT_DSP_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7357 { 7088 /* mult */, Mips::MULT_DSP, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7358 { 7093 /* multu */, Mips::MULTu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7359 { 7093 /* multu */, Mips::MULTu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7360 { 7093 /* multu */, Mips::MULTU_DSP_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7361 { 7093 /* multu */, Mips::MULTU_DSP, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7362 { 7099 /* mulu */, Mips::MULU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7363 { 7099 /* mulu */, Mips::MULU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7364 { 7099 /* mulu */, Mips::MULU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7365 { 7104 /* mulv.b */, Mips::MULV_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7366 { 7111 /* mulv.d */, Mips::MULV_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7367 { 7118 /* mulv.h */, Mips::MULV_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7368 { 7125 /* mulv.w */, Mips::MULV_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7369 { 7132 /* nal */, Mips::BLTZAL, Convert__regZERO__imm_95_0, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { }, },
7370 { 7132 /* nal */, Mips::NAL, Convert_NoOperands, AMFBS_HasStdEnc_HasMips32r6, { }, },
7371 { 7136 /* neg */, Mips::SUB, Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_0, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg }, },
7372 { 7136 /* neg */, Mips::SUB_MM, Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_0, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg }, },
7373 { 7136 /* neg */, Mips::SUB_MMR6, Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_0, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg }, },
7374 { 7136 /* neg */, Mips::NegRxRy16, Convert__Reg1_0__Reg1_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs }, },
7375 { 7136 /* neg */, Mips::SUB, Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7376 { 7136 /* neg */, Mips::SUB_MM, Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7377 { 7136 /* neg */, Mips::SUB_MMR6, Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7378 { 7140 /* neg.d */, Mips::FNEG_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
7379 { 7140 /* neg.d */, Mips::FNEG_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
7380 { 7140 /* neg.d */, Mips::FNEG_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7381 { 7140 /* neg.d */, Mips::FNEG_D64_MM, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7382 { 7146 /* neg.s */, Mips::FNEG_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7383 { 7146 /* neg.s */, Mips::FNEG_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7384 { 7146 /* neg.s */, Mips::FNEG_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7385 { 7152 /* negu */, Mips::SUBu, Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_0, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg }, },
7386 { 7152 /* negu */, Mips::SUBu_MM, Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_0, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg }, },
7387 { 7152 /* negu */, Mips::SUBU_MMR6, Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_0, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg }, },
7388 { 7152 /* negu */, Mips::SUBu, Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7389 { 7152 /* negu */, Mips::SUBu_MM, Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7390 { 7152 /* negu */, Mips::SUBU_MMR6, Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7391 { 7157 /* nloc.b */, Mips::NLOC_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7392 { 7164 /* nloc.d */, Mips::NLOC_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7393 { 7171 /* nloc.h */, Mips::NLOC_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7394 { 7178 /* nloc.w */, Mips::NLOC_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7395 { 7185 /* nlzc.b */, Mips::NLZC_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7396 { 7192 /* nlzc.d */, Mips::NLZC_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7397 { 7199 /* nlzc.h */, Mips::NLZC_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7398 { 7206 /* nlzc.w */, Mips::NLZC_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7399 { 7213 /* nmadd.d */, Mips::NMADD_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2__AFGR64AsmReg1_3, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
7400 { 7213 /* nmadd.d */, Mips::NMADD_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2__AFGR64AsmReg1_3, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat_HasMadd4, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
7401 { 7213 /* nmadd.d */, Mips::NMADD_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2__FGR64AsmReg1_3, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7402 { 7221 /* nmadd.s */, Mips::NMADD_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2__FGR32AsmReg1_3, AMFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7403 { 7221 /* nmadd.s */, Mips::NMADD_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2__FGR32AsmReg1_3, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat_HasMadd4, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7404 { 7229 /* nmsub.d */, Mips::NMSUB_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2__AFGR64AsmReg1_3, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
7405 { 7229 /* nmsub.d */, Mips::NMSUB_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2__AFGR64AsmReg1_3, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat_HasMadd4, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
7406 { 7229 /* nmsub.d */, Mips::NMSUB_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2__FGR64AsmReg1_3, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7407 { 7237 /* nmsub.s */, Mips::NMSUB_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2__FGR32AsmReg1_3, AMFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7408 { 7237 /* nmsub.s */, Mips::NMSUB_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2__FGR32AsmReg1_3, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat_HasMadd4, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7409 { 7245 /* nop */, Mips::SLL, Convert__regZERO__regZERO__imm_95_0, AMFBS_HasStdEnc_NotInMicroMips, { }, },
7410 { 7245 /* nop */, Mips::SLL_MMR6, Convert__regZERO__regZERO__imm_95_0, AMFBS_InMicroMips_HasMips32r6, { }, },
7411 { 7245 /* nop */, Mips::Move32R16, Convert__regZERO__regS0, AMFBS_InMips16Mode, { }, },
7412 { 7245 /* nop */, Mips::SLL_MM, Convert__regZERO__regZERO__imm_95_0, AMFBS_InMicroMips, { }, },
7413 { 7245 /* nop */, Mips::MOVE16_MM, Convert__regZERO__regZERO, AMFBS_InMicroMips, { }, },
7414 { 7249 /* nor */, Mips::NORImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, AMFBS_IsGP32bit, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
7415 { 7249 /* nor */, Mips::NORImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, AMFBS_IsGP64bit, { MCK_GPR64AsmReg, MCK_Imm }, },
7416 { 7249 /* nor */, Mips::NOR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7417 { 7249 /* nor */, Mips::NOR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7418 { 7249 /* nor */, Mips::NOR_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7419 { 7249 /* nor */, Mips::NORImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_IsGP32bit, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
7420 { 7249 /* nor */, Mips::NORImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, AMFBS_IsGP64bit, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, },
7421 { 7253 /* nor.v */, Mips::NOR_V, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7422 { 7259 /* nori.b */, Mips::NORI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm8_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm8_0 }, },
7423 { 7266 /* not */, Mips::NOR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__regZERO, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg }, },
7424 { 7266 /* not */, Mips::NOR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__regZERO, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg }, },
7425 { 7266 /* not */, Mips::NOR_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__regZERO, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg }, },
7426 { 7266 /* not */, Mips::NotRxRy16, Convert__Reg1_0__Reg1_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs }, },
7427 { 7266 /* not */, Mips::NOR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__regZERO, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7428 { 7266 /* not */, Mips::NOR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__regZERO, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7429 { 7266 /* not */, Mips::NOR_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__regZERO, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7430 { 7270 /* not16 */, Mips::NOT16_MM, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, },
7431 { 7270 /* not16 */, Mips::NOT16_MMR6, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, },
7432 { 7276 /* or */, Mips::OrRxRxRy16, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs }, },
7433 { 7276 /* or */, Mips::OR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7434 { 7276 /* or */, Mips::OR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7435 { 7276 /* or */, Mips::OR_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7436 { 7276 /* or */, Mips::ORI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_UImm16 }, },
7437 { 7276 /* or */, Mips::ORi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
7438 { 7276 /* or */, Mips::ORi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
7439 { 7276 /* or */, Mips::ORi64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, AMFBS_HasStdEnc_IsGP64bit_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_Imm }, },
7440 { 7276 /* or */, Mips::OR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7441 { 7276 /* or */, Mips::OR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7442 { 7276 /* or */, Mips::OR_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7443 { 7276 /* or */, Mips::ORI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, },
7444 { 7276 /* or */, Mips::ORi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
7445 { 7276 /* or */, Mips::ORi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
7446 { 7276 /* or */, Mips::ORi64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, AMFBS_HasStdEnc_IsGP64bit_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, },
7447 { 7279 /* or.v */, Mips::OR_V, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7448 { 7284 /* or16 */, Mips::OR16_MM, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Tie0_1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, },
7449 { 7284 /* or16 */, Mips::OR16_MMR6, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Tie0_1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, },
7450 { 7289 /* ori */, Mips::ORI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_UImm16 }, },
7451 { 7289 /* ori */, Mips::ORi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_UImm16 }, },
7452 { 7289 /* ori */, Mips::ORi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_UImm16 }, },
7453 { 7289 /* ori */, Mips::ORI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, },
7454 { 7289 /* ori */, Mips::ORi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, },
7455 { 7289 /* ori */, Mips::ORi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, },
7456 { 7293 /* ori.b */, Mips::ORI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm8_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm8_0 }, },
7457 { 7299 /* packrl.ph */, Mips::PACKRL_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7458 { 7299 /* packrl.ph */, Mips::PACKRL_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7459 { 7309 /* pause */, Mips::PAUSE, Convert_NoOperands, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips, { }, },
7460 { 7309 /* pause */, Mips::PAUSE_MMR6, Convert_NoOperands, AMFBS_InMicroMips_HasMips32r6, { }, },
7461 { 7309 /* pause */, Mips::PAUSE_MM, Convert_NoOperands, AMFBS_InMicroMips, { }, },
7462 { 7315 /* pckev.b */, Mips::PCKEV_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7463 { 7323 /* pckev.d */, Mips::PCKEV_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7464 { 7331 /* pckev.h */, Mips::PCKEV_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7465 { 7339 /* pckev.w */, Mips::PCKEV_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7466 { 7347 /* pckod.b */, Mips::PCKOD_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7467 { 7355 /* pckod.d */, Mips::PCKOD_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7468 { 7363 /* pckod.h */, Mips::PCKOD_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7469 { 7371 /* pckod.w */, Mips::PCKOD_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7470 { 7379 /* pcnt.b */, Mips::PCNT_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7471 { 7386 /* pcnt.d */, Mips::PCNT_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7472 { 7393 /* pcnt.h */, Mips::PCNT_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7473 { 7400 /* pcnt.w */, Mips::PCNT_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7474 { 7407 /* pick.ph */, Mips::PICK_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7475 { 7407 /* pick.ph */, Mips::PICK_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7476 { 7415 /* pick.qb */, Mips::PICK_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7477 { 7415 /* pick.qb */, Mips::PICK_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7478 { 7423 /* pll.ps */, Mips::PLL_PS64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7479 { 7430 /* plu.ps */, Mips::PLU_PS64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7480 { 7437 /* pop */, Mips::POP, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0, AMFBS_HasCnMips, { MCK_GPR32AsmReg }, },
7481 { 7437 /* pop */, Mips::POP, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasCnMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7482 { 7441 /* preceq.w.phl */, Mips::PRECEQ_W_PHL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7483 { 7441 /* preceq.w.phl */, Mips::PRECEQ_W_PHL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7484 { 7454 /* preceq.w.phr */, Mips::PRECEQ_W_PHR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7485 { 7454 /* preceq.w.phr */, Mips::PRECEQ_W_PHR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7486 { 7467 /* precequ.ph.qbl */, Mips::PRECEQU_PH_QBL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7487 { 7467 /* precequ.ph.qbl */, Mips::PRECEQU_PH_QBL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7488 { 7482 /* precequ.ph.qbla */, Mips::PRECEQU_PH_QBLA_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7489 { 7482 /* precequ.ph.qbla */, Mips::PRECEQU_PH_QBLA, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7490 { 7498 /* precequ.ph.qbr */, Mips::PRECEQU_PH_QBR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7491 { 7498 /* precequ.ph.qbr */, Mips::PRECEQU_PH_QBR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7492 { 7513 /* precequ.ph.qbra */, Mips::PRECEQU_PH_QBRA_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7493 { 7513 /* precequ.ph.qbra */, Mips::PRECEQU_PH_QBRA, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7494 { 7529 /* preceu.ph.qbl */, Mips::PRECEU_PH_QBL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7495 { 7529 /* preceu.ph.qbl */, Mips::PRECEU_PH_QBL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7496 { 7543 /* preceu.ph.qbla */, Mips::PRECEU_PH_QBLA_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7497 { 7543 /* preceu.ph.qbla */, Mips::PRECEU_PH_QBLA, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7498 { 7558 /* preceu.ph.qbr */, Mips::PRECEU_PH_QBR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7499 { 7558 /* preceu.ph.qbr */, Mips::PRECEU_PH_QBR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7500 { 7572 /* preceu.ph.qbra */, Mips::PRECEU_PH_QBRA_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7501 { 7572 /* preceu.ph.qbra */, Mips::PRECEU_PH_QBRA, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7502 { 7587 /* precr.qb.ph */, Mips::PRECR_QB_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7503 { 7587 /* precr.qb.ph */, Mips::PRECR_QB_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7504 { 7599 /* precr_sra.ph.w */, Mips::PRECR_SRA_PH_W_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Tie0_1_1, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7505 { 7599 /* precr_sra.ph.w */, Mips::PRECR_SRA_PH_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Tie0_1_1, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7506 { 7614 /* precr_sra_r.ph.w */, Mips::PRECR_SRA_R_PH_W_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Tie0_1_1, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7507 { 7614 /* precr_sra_r.ph.w */, Mips::PRECR_SRA_R_PH_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Tie0_1_1, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7508 { 7631 /* precrq.ph.w */, Mips::PRECRQ_PH_W_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7509 { 7631 /* precrq.ph.w */, Mips::PRECRQ_PH_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7510 { 7643 /* precrq.qb.ph */, Mips::PRECRQ_QB_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7511 { 7643 /* precrq.qb.ph */, Mips::PRECRQ_QB_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7512 { 7656 /* precrq_rs.ph.w */, Mips::PRECRQ_RS_PH_W_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7513 { 7656 /* precrq_rs.ph.w */, Mips::PRECRQ_RS_PH_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7514 { 7671 /* precrqu_s.qb.ph */, Mips::PRECRQU_S_QB_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7515 { 7671 /* precrqu_s.qb.ph */, Mips::PRECRQU_S_QB_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7516 { 7687 /* pref */, Mips::PREF_R6, Convert__MemOffsetSimm9_02_1__ConstantUImm5_01_0, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_ConstantUImm5_0, MCK_MemOffsetSimm9_0 }, },
7517 { 7687 /* pref */, Mips::PREF, Convert__Mem2_1__ConstantUImm5_01_0, AMFBS_HasStdEnc_HasMips3_32_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_ConstantUImm5_0, MCK_Mem }, },
7518 { 7687 /* pref */, Mips::PREF_MM, Convert__Mem2_1__ConstantUImm5_01_0, AMFBS_InMicroMips_NotMips32r6, { MCK_ConstantUImm5_0, MCK_Mem }, },
7519 { 7687 /* pref */, Mips::PREF_MMR6, Convert__Mem2_1__ConstantUImm5_01_0, AMFBS_InMicroMips_HasMips32r6, { MCK_ConstantUImm5_0, MCK_Mem }, },
7520 { 7692 /* prefe */, Mips::PREFE, Convert__MemOffsetSimm9_02_1__ConstantUImm5_01_0, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, { MCK_ConstantUImm5_0, MCK_MemOffsetSimm9_0 }, },
7521 { 7692 /* prefe */, Mips::PREFE_MM, Convert__MemOffsetSimm9_02_1__ConstantUImm5_01_0, AMFBS_InMicroMips_HasEVA, { MCK_ConstantUImm5_0, MCK_MemOffsetSimm9_0 }, },
7522 { 7698 /* prefx */, Mips::PREFX_MM, Convert__GPR32AsmReg1_3__GPR32AsmReg1_1__ConstantUImm5_01_0, AMFBS_InMicroMips_NotMips32r6, { MCK_ConstantUImm5_0, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
7523 { 7704 /* prepend */, Mips::PREPEND_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Tie0_1_1, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7524 { 7704 /* prepend */, Mips::PREPEND, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Tie0_1_1, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7525 { 7712 /* pul.ps */, Mips::PUL_PS64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7526 { 7719 /* puu.ps */, Mips::PUU_PS64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7527 { 7726 /* raddu.w.qb */, Mips::RADDU_W_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7528 { 7726 /* raddu.w.qb */, Mips::RADDU_W_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7529 { 7737 /* rddsp */, Mips::RDDSP_MM, Convert__GPR32AsmReg1_0__ConstantUImm7_01_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ConstantUImm7_0 }, },
7530 { 7737 /* rddsp */, Mips::RDDSP, Convert__GPR32AsmReg1_0__ConstantUImm10_01_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_ConstantUImm10_0 }, },
7531 { 7743 /* rdhwr */, Mips::RDHWR, Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__imm_95_0, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_HWRegsAsmReg }, },
7532 { 7743 /* rdhwr */, Mips::RDHWR_MM, Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__imm_95_0, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_HWRegsAsmReg }, },
7533 { 7743 /* rdhwr */, Mips::RDHWR_MMR6, Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__imm_95_0, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_HWRegsAsmReg }, },
7534 { 7743 /* rdhwr */, Mips::RDHWR64, Convert__GPR64AsmReg1_0__HWRegsAsmReg1_1__imm_95_0, AMFBS_IsGP64bit, { MCK_GPR64AsmReg, MCK_HWRegsAsmReg }, },
7535 { 7743 /* rdhwr */, Mips::RDHWR_MMR6, Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__ConstantUImm3_01_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_HWRegsAsmReg, MCK_ConstantUImm3_0 }, },
7536 { 7743 /* rdhwr */, Mips::RDHWR, Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__ConstantUImm8_01_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_HWRegsAsmReg, MCK_ConstantUImm8_0 }, },
7537 { 7743 /* rdhwr */, Mips::RDHWR_MM, Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__ConstantUImm8_01_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_HWRegsAsmReg, MCK_ConstantUImm8_0 }, },
7538 { 7749 /* rdpgpr */, Mips::RDPGPR_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7539 { 7756 /* recip.d */, Mips::RECIP_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
7540 { 7756 /* recip.d */, Mips::RECIP_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
7541 { 7756 /* recip.d */, Mips::RECIP_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7542 { 7756 /* recip.d */, Mips::RECIP_D64_MM, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7543 { 7764 /* recip.s */, Mips::RECIP_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7544 { 7764 /* recip.s */, Mips::RECIP_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7545 { 7772 /* rem */, Mips::SRemMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7546 { 7772 /* rem */, Mips::SRemIMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
7547 { 7772 /* rem */, Mips::SRemMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7548 { 7772 /* rem */, Mips::SRemIMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
7549 { 7776 /* remu */, Mips::URemMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7550 { 7776 /* remu */, Mips::URemIMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
7551 { 7776 /* remu */, Mips::URemMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7552 { 7776 /* remu */, Mips::URemIMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
7553 { 7781 /* repl.ph */, Mips::REPL_PH_MM, Convert__GPR32AsmReg1_0__ConstantSImm10_01_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ConstantSImm10_0 }, },
7554 { 7781 /* repl.ph */, Mips::REPL_PH, Convert__GPR32AsmReg1_0__ConstantSImm10_01_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_ConstantSImm10_0 }, },
7555 { 7789 /* repl.qb */, Mips::REPL_QB_MM, Convert__GPR32AsmReg1_0__ConstantUImm8_01_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ConstantUImm8_0 }, },
7556 { 7789 /* repl.qb */, Mips::REPL_QB, Convert__GPR32AsmReg1_0__ConstantUImm8_01_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_ConstantUImm8_0 }, },
7557 { 7797 /* replv.ph */, Mips::REPLV_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7558 { 7797 /* replv.ph */, Mips::REPLV_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7559 { 7806 /* replv.qb */, Mips::REPLV_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7560 { 7806 /* replv.qb */, Mips::REPLV_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7561 { 7815 /* rint.d */, Mips::RINT_D, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7562 { 7815 /* rint.d */, Mips::RINT_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7563 { 7822 /* rint.s */, Mips::RINT_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7564 { 7822 /* rint.s */, Mips::RINT_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7565 { 7829 /* rol */, Mips::ROL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_None, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7566 { 7829 /* rol */, Mips::ROLImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm161_1, AMFBS_None, { MCK_GPR32AsmReg, MCK_SImm16 }, },
7567 { 7829 /* rol */, Mips::ROL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7568 { 7829 /* rol */, Mips::ROLImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16 }, },
7569 { 7833 /* ror */, Mips::ROR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_None, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7570 { 7833 /* ror */, Mips::RORImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm161_1, AMFBS_None, { MCK_GPR32AsmReg, MCK_SImm16 }, },
7571 { 7833 /* ror */, Mips::ROR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7572 { 7833 /* ror */, Mips::RORImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16 }, },
7573 { 7837 /* rotr */, Mips::ROTR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7574 { 7837 /* rotr */, Mips::ROTR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7575 { 7837 /* rotr */, Mips::ROTR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7576 { 7837 /* rotr */, Mips::ROTR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7577 { 7837 /* rotr */, Mips::ROTR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7578 { 7842 /* rotrv */, Mips::ROTRV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7579 { 7842 /* rotrv */, Mips::ROTRV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7580 { 7848 /* round.l.d */, Mips::ROUND_L_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips3_32_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7581 { 7848 /* round.l.d */, Mips::ROUND_L_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7582 { 7858 /* round.l.s */, Mips::ROUND_L_S, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, },
7583 { 7858 /* round.l.s */, Mips::ROUND_L_S_MMR6, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, },
7584 { 7868 /* round.w.d */, Mips::ROUND_W_D32, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, },
7585 { 7868 /* round.w.d */, Mips::ROUND_W_MM, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, },
7586 { 7868 /* round.w.d */, Mips::ROUND_W_D64, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg }, },
7587 { 7868 /* round.w.d */, Mips::ROUND_W_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7588 { 7878 /* round.w.s */, Mips::ROUND_W_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_HasMips2_NotR5900_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7589 { 7878 /* round.w.s */, Mips::ROUND_W_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7590 { 7878 /* round.w.s */, Mips::ROUND_W_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7591 { 7888 /* rsqrt.d */, Mips::RSQRT_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
7592 { 7888 /* rsqrt.d */, Mips::RSQRT_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
7593 { 7888 /* rsqrt.d */, Mips::RSQRT_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7594 { 7888 /* rsqrt.d */, Mips::RSQRT_D64_MM, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7595 { 7896 /* rsqrt.s */, Mips::RSQRT_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7596 { 7896 /* rsqrt.s */, Mips::RSQRT_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7597 { 7904 /* s.d */, Mips::SDC1, Convert__AFGR64AsmReg1_0__MemOffsetSimm16_02_1, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_MemOffsetSimm16_0 }, },
7598 { 7904 /* s.d */, Mips::SDC1_M1, Convert__AFGR64AsmReg1_0__MemOffsetSimm16_02_1, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_MemOffsetSimm16_0 }, },
7599 { 7904 /* s.d */, Mips::SDC1_M1, Convert__AFGR64AsmReg1_0__MemOffsetSimm16_02_1, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_MemOffsetSimm16_0 }, },
7600 { 7904 /* s.d */, Mips::SDC164, Convert__FGR64AsmReg1_0__MemOffsetSimm16_02_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_MemOffsetSimm16_0 }, },
7601 { 7908 /* s.s */, Mips::SWC1, Convert__FGR32AsmReg1_0__MemOffsetSimm16_02_1, AMFBS_HasStdEnc_HasMips2_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_MemOffsetSimm16_0 }, },
7602 { 7912 /* saa */, Mips::SaaAddr, Convert__GPR64AsmReg1_0__Mem2_1, AMFBS_HasCnMipsP, { MCK_GPR64AsmReg, MCK_Mem }, },
7603 { 7912 /* saa */, Mips::SAA, Convert__GPR64AsmReg1_0__GPR64AsmReg1_2, AMFBS_HasCnMipsP, { MCK_GPR64AsmReg, MCK__40_, MCK_GPR64AsmReg, MCK__41_ }, },
7604 { 7916 /* saad */, Mips::SaadAddr, Convert__GPR64AsmReg1_0__Mem2_1, AMFBS_HasCnMipsP, { MCK_GPR64AsmReg, MCK_Mem }, },
7605 { 7916 /* saad */, Mips::SAAD, Convert__GPR64AsmReg1_0__GPR64AsmReg1_2, AMFBS_HasCnMipsP, { MCK_GPR64AsmReg, MCK__40_, MCK_GPR64AsmReg, MCK__41_ }, },
7606 { 7921 /* sat_s.b */, Mips::SAT_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, },
7607 { 7929 /* sat_s.d */, Mips::SAT_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, },
7608 { 7937 /* sat_s.h */, Mips::SAT_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, },
7609 { 7945 /* sat_s.w */, Mips::SAT_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
7610 { 7953 /* sat_u.b */, Mips::SAT_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, },
7611 { 7961 /* sat_u.d */, Mips::SAT_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, },
7612 { 7969 /* sat_u.h */, Mips::SAT_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, },
7613 { 7977 /* sat_u.w */, Mips::SAT_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
7614 { 7985 /* sb */, Mips::SB, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
7615 { 7985 /* sb */, Mips::SB_MMR6, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_Mem }, },
7616 { 7985 /* sb */, Mips::SB_MM, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
7617 { 7985 /* sb */, Mips::SbRxRyOffMemX16, Convert__Reg1_0__Reg1_1__SImm161_2, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs, MCK_SImm16 }, },
7618 { 7988 /* sb16 */, Mips::SB16_MM, Convert__GPRMM16AsmRegZero1_0__MicroMipsMem2_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPRMM16AsmRegZero, MCK_MicroMipsMem }, },
7619 { 7988 /* sb16 */, Mips::SB16_MMR6, Convert__GPRMM16AsmRegZero1_0__MicroMipsMem2_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPRMM16AsmRegZero, MCK_MicroMipsMem }, },
7620 { 7993 /* sbe */, Mips::SBE, Convert__GPR32AsmReg1_0__MemOffsetSimm9_02_1, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9_0 }, },
7621 { 7993 /* sbe */, Mips::SBE_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm9_02_1, AMFBS_InMicroMips_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9_0 }, },
7622 { 7997 /* sc */, Mips::SC64_R6, Convert__GPR32AsmReg1_0__Tie0_1_1__MemOffsetSimmPtr2_1, AMFBS_HasStdEnc_IsPTR64bit_HasMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimmPtr }, },
7623 { 7997 /* sc */, Mips::SC_R6, Convert__GPR32AsmReg1_0__Tie0_1_1__MemOffsetSimmPtr2_1, AMFBS_HasStdEnc_IsPTR32bit_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimmPtr }, },
7624 { 7997 /* sc */, Mips::SC_MMR6, Convert__GPR32AsmReg1_0__Tie0_1_1__MemOffsetSimm9_02_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9_0 }, },
7625 { 7997 /* sc */, Mips::SC, Convert__GPR32AsmReg1_0__Tie0_1_1__Mem2_1, AMFBS_HasStdEnc_IsPTR32bit_HasMips2_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
7626 { 7997 /* sc */, Mips::SC64, Convert__GPR32AsmReg1_0__Tie0_1_1__Mem2_1, AMFBS_HasStdEnc_IsPTR64bit_HasMips2_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
7627 { 7997 /* sc */, Mips::SC_MM, Convert__GPR32AsmReg1_0__Tie0_1_1__Mem2_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_Mem }, },
7628 { 8000 /* scd */, Mips::SCD_R6, Convert__GPR64AsmReg1_0__Tie0_1_1__MemOffsetSimmPtr2_1, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR64AsmReg, MCK_MemOffsetSimmPtr }, },
7629 { 8000 /* scd */, Mips::SCD, Convert__GPR64AsmReg1_0__Tie0_1_1__Mem2_1, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900, { MCK_GPR64AsmReg, MCK_Mem }, },
7630 { 8004 /* sce */, Mips::SCE, Convert__GPR32AsmReg1_0__Tie0_1_1__MemOffsetSimm9_02_1, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9_0 }, },
7631 { 8004 /* sce */, Mips::SCE_MM, Convert__GPR32AsmReg1_0__Tie0_1_1__MemOffsetSimm9_02_1, AMFBS_InMicroMips_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9_0 }, },
7632 { 8008 /* sd */, Mips::SDMacro, Convert__GPR32AsmReg1_0__MemOffsetSimm16_02_1, AMFBS_HasStdEnc_NotMips3, { MCK_GPR32AsmReg, MCK_MemOffsetSimm16_0 }, },
7633 { 8008 /* sd */, Mips::SD, Convert__GPR64AsmReg1_0__MemOffsetSimmPtr2_1, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_MemOffsetSimmPtr }, },
7634 { 8011 /* sdbbp */, Mips::SDBBP, Convert__imm_95_0, AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6, { }, },
7635 { 8011 /* sdbbp */, Mips::SDBBP_R6, Convert__imm_95_0, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { }, },
7636 { 8011 /* sdbbp */, Mips::SDBBP_MMR6, Convert__imm_95_0, AMFBS_InMicroMips_HasMips32r6, { }, },
7637 { 8011 /* sdbbp */, Mips::SDBBP_MM, Convert__ConstantUImm10_01_0, AMFBS_InMicroMips, { MCK_ConstantUImm10_0 }, },
7638 { 8011 /* sdbbp */, Mips::SDBBP, Convert__ConstantUImm20_01_0, AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_ConstantUImm20_0 }, },
7639 { 8011 /* sdbbp */, Mips::SDBBP_R6, Convert__ConstantUImm20_01_0, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_ConstantUImm20_0 }, },
7640 { 8011 /* sdbbp */, Mips::SDBBP_MMR6, Convert__ConstantUImm20_01_0, AMFBS_InMicroMips_HasMips32r6, { MCK_ConstantUImm20_0 }, },
7641 { 8017 /* sdbbp16 */, Mips::SDBBP16_MM, Convert__ConstantUImm4_01_0, AMFBS_InMicroMips_NotMips32r6, { MCK_ConstantUImm4_0 }, },
7642 { 8017 /* sdbbp16 */, Mips::SDBBP16_MMR6, Convert__ConstantUImm4_01_0, AMFBS_InMicroMips_HasMips32r6, { MCK_ConstantUImm4_0 }, },
7643 { 8025 /* sdc1 */, Mips::SDC1, Convert__AFGR64AsmReg1_0__MemOffsetSimm16_02_1, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_MemOffsetSimm16_0 }, },
7644 { 8025 /* sdc1 */, Mips::SDC1_MM_D32, Convert__AFGR64AsmReg1_0__MemOffsetSimm16_02_1, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_MemOffsetSimm16_0 }, },
7645 { 8025 /* sdc1 */, Mips::SDC164, Convert__FGR64AsmReg1_0__MemOffsetSimm16_02_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_MemOffsetSimm16_0 }, },
7646 { 8025 /* sdc1 */, Mips::SDC1_D64_MMR6, Convert__FGR64AsmReg1_0__MemOffsetSimm16_02_1, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_MemOffsetSimm16_0 }, },
7647 { 8025 /* sdc1 */, Mips::SDC1_MM_D64, Convert__FGR64AsmReg1_0__MemOffsetSimm16_02_1, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_MemOffsetSimm16_0 }, },
7648 { 8030 /* sdc2 */, Mips::SDC2_R6, Convert__COP2AsmReg1_0__MemOffsetSimm11_02_1, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_COP2AsmReg, MCK_MemOffsetSimm11_0 }, },
7649 { 8030 /* sdc2 */, Mips::SDC2_MMR6, Convert__COP2AsmReg1_0__MemOffsetSimm11_02_1, AMFBS_InMicroMips_HasMips32r6, { MCK_COP2AsmReg, MCK_MemOffsetSimm11_0 }, },
7650 { 8030 /* sdc2 */, Mips::SDC2, Convert__COP2AsmReg1_0__MemOffsetSimm16_02_1, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_COP2AsmReg, MCK_MemOffsetSimm16_0 }, },
7651 { 8035 /* sdc3 */, Mips::SDC3, Convert__COP3AsmReg1_0__Mem2_1, AMFBS_HasStdEnc_HasMips2_NotR5900_NotCnMips_NotInMicroMips, { MCK_COP3AsmReg, MCK_Mem }, },
7652 { 8040 /* sdl */, Mips::SDL, Convert__GPR64AsmReg1_0__Mem2_1, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, { MCK_GPR64AsmReg, MCK_Mem }, },
7653 { 8044 /* sdr */, Mips::SDR, Convert__GPR64AsmReg1_0__Mem2_1, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, { MCK_GPR64AsmReg, MCK_Mem }, },
7654 { 8048 /* sdxc1 */, Mips::SDXC1, Convert__AFGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
7655 { 8048 /* sdxc1 */, Mips::SDXC164, Convert__FGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
7656 { 8054 /* seb */, Mips::SebRx16, Convert__Reg1_0__Tie0_1_1, AMFBS_InMips16Mode, { MCK_CPU16Regs }, },
7657 { 8054 /* seb */, Mips::SEB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips, { MCK_GPR32AsmReg }, },
7658 { 8054 /* seb */, Mips::SEB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0, AMFBS_InMicroMips, { MCK_GPR32AsmReg }, },
7659 { 8054 /* seb */, Mips::SEB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7660 { 8054 /* seb */, Mips::SEB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7661 { 8058 /* seh */, Mips::SehRx16, Convert__Reg1_0__Tie0_1_1, AMFBS_InMips16Mode, { MCK_CPU16Regs }, },
7662 { 8058 /* seh */, Mips::SEH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips, { MCK_GPR32AsmReg }, },
7663 { 8058 /* seh */, Mips::SEH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0, AMFBS_InMicroMips, { MCK_GPR32AsmReg }, },
7664 { 8058 /* seh */, Mips::SEH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7665 { 8058 /* seh */, Mips::SEH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7666 { 8062 /* sel.d */, Mips::SEL_D, Convert__FGR64AsmReg1_0__Tie0_1_1__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7667 { 8062 /* sel.d */, Mips::SEL_D_MMR6, Convert__FGR64AsmReg1_0__Tie0_1_1__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7668 { 8068 /* sel.s */, Mips::SEL_S, Convert__FGR32AsmReg1_0__Tie0_1_1__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7669 { 8068 /* sel.s */, Mips::SEL_S_MMR6, Convert__FGR32AsmReg1_0__Tie0_1_1__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7670 { 8074 /* seleqz */, Mips::SELEQZ, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_IsGP32bit_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7671 { 8074 /* seleqz */, Mips::SELEQZ_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7672 { 8074 /* seleqz */, Mips::SELEQZ64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_IsGP64bit_HasMips32r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
7673 { 8081 /* seleqz.d */, Mips::SELEQZ_D, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7674 { 8081 /* seleqz.d */, Mips::SELEQZ_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7675 { 8090 /* seleqz.s */, Mips::SELEQZ_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7676 { 8090 /* seleqz.s */, Mips::SELEQZ_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7677 { 8099 /* selnez */, Mips::SELNEZ, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_IsGP32bit_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7678 { 8099 /* selnez */, Mips::SELNEZ_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7679 { 8099 /* selnez */, Mips::SELNEZ64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_IsGP64bit_HasMips32r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
7680 { 8106 /* selnez.d */, Mips::SELNEZ_D, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7681 { 8106 /* selnez.d */, Mips::SELNEZ_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7682 { 8115 /* selnez.s */, Mips::SELNEZ_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7683 { 8115 /* selnez.s */, Mips::SELNEZ_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7684 { 8124 /* seq */, Mips::SEQMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_NotCnMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7685 { 8124 /* seq */, Mips::SEQIMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm321_1, AMFBS_NotCnMips, { MCK_GPR32AsmReg, MCK_SImm32 }, },
7686 { 8124 /* seq */, Mips::SEQ, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
7687 { 8124 /* seq */, Mips::SEQMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_NotCnMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7688 { 8124 /* seq */, Mips::SEQIMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_NotCnMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
7689 { 8124 /* seq */, Mips::SEQ, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
7690 { 8128 /* seqi */, Mips::SEQi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantSImm10_01_1, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_ConstantSImm10_0 }, },
7691 { 8128 /* seqi */, Mips::SEQi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantSImm10_01_2, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantSImm10_0 }, },
7692 { 8133 /* sge */, Mips::SGE, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7693 { 8133 /* sge */, Mips::SGEImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm321_1, AMFBS_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm32 }, },
7694 { 8133 /* sge */, Mips::SGEImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, AMFBS_IsGP64bit, { MCK_GPR64AsmReg, MCK_Imm }, },
7695 { 8133 /* sge */, Mips::SGE, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7696 { 8133 /* sge */, Mips::SGEImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm321_2, AMFBS_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32 }, },
7697 { 8133 /* sge */, Mips::SGEImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, AMFBS_IsGP64bit, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, },
7698 { 8137 /* sgeu */, Mips::SGEU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7699 { 8137 /* sgeu */, Mips::SGEUImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm32_Coerced1_1, AMFBS_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_UImm32_Coerced }, },
7700 { 8137 /* sgeu */, Mips::SGEUImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, AMFBS_IsGP64bit, { MCK_GPR64AsmReg, MCK_Imm }, },
7701 { 8137 /* sgeu */, Mips::SGEU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7702 { 8137 /* sgeu */, Mips::SGEUImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm32_Coerced1_2, AMFBS_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm32_Coerced }, },
7703 { 8137 /* sgeu */, Mips::SGEUImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, AMFBS_IsGP64bit, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, },
7704 { 8142 /* sgt */, Mips::SLT, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_0, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7705 { 8142 /* sgt */, Mips::SLT_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_0, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7706 { 8142 /* sgt */, Mips::SGTImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm321_1, AMFBS_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm32 }, },
7707 { 8142 /* sgt */, Mips::SGTImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, AMFBS_IsGP64bit, { MCK_GPR64AsmReg, MCK_Imm }, },
7708 { 8142 /* sgt */, Mips::SLT, Convert__GPR32AsmReg1_0__GPR32AsmReg1_2__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7709 { 8142 /* sgt */, Mips::SLT_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_2__GPR32AsmReg1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7710 { 8142 /* sgt */, Mips::SGTImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm321_2, AMFBS_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32 }, },
7711 { 8142 /* sgt */, Mips::SGTImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, AMFBS_IsGP64bit, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, },
7712 { 8146 /* sgtu */, Mips::SLTu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_0, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7713 { 8146 /* sgtu */, Mips::SLTu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_0, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7714 { 8146 /* sgtu */, Mips::SGTUImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm32_Coerced1_1, AMFBS_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_UImm32_Coerced }, },
7715 { 8146 /* sgtu */, Mips::SGTUImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, AMFBS_IsGP64bit, { MCK_GPR64AsmReg, MCK_Imm }, },
7716 { 8146 /* sgtu */, Mips::SLTu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_2__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7717 { 8146 /* sgtu */, Mips::SLTu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_2__GPR32AsmReg1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7718 { 8146 /* sgtu */, Mips::SGTUImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm32_Coerced1_2, AMFBS_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm32_Coerced }, },
7719 { 8146 /* sgtu */, Mips::SGTUImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, AMFBS_IsGP64bit, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, },
7720 { 8151 /* sh */, Mips::SH, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
7721 { 8151 /* sh */, Mips::SH_MMR6, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_Mem }, },
7722 { 8151 /* sh */, Mips::SH_MM, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
7723 { 8151 /* sh */, Mips::ShRxRyOffMemX16, Convert__Reg1_0__Reg1_1__SImm161_2, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs, MCK_SImm16 }, },
7724 { 8154 /* sh16 */, Mips::SH16_MM, Convert__GPRMM16AsmRegZero1_0__MicroMipsMem2_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPRMM16AsmRegZero, MCK_MicroMipsMem }, },
7725 { 8154 /* sh16 */, Mips::SH16_MMR6, Convert__GPRMM16AsmRegZero1_0__MicroMipsMem2_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPRMM16AsmRegZero, MCK_MicroMipsMem }, },
7726 { 8159 /* she */, Mips::SHE, Convert__GPR32AsmReg1_0__MemOffsetSimm9_02_1, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9_0 }, },
7727 { 8159 /* she */, Mips::SHE_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm9_02_1, AMFBS_InMicroMips_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9_0 }, },
7728 { 8163 /* shf.b */, Mips::SHF_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm8_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm8_0 }, },
7729 { 8169 /* shf.h */, Mips::SHF_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm8_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm8_0 }, },
7730 { 8175 /* shf.w */, Mips::SHF_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm8_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm8_0 }, },
7731 { 8181 /* shilo */, Mips::SHILO_MM, Convert__ACC64DSPAsmReg1_0__ConstantSImm6_01_1__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_ConstantSImm6_0 }, },
7732 { 8181 /* shilo */, Mips::SHILO, Convert__ACC64DSPAsmReg1_0__ConstantSImm6_01_1__Tie0_1_1, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_ConstantSImm6_0 }, },
7733 { 8187 /* shilov */, Mips::SHILOV_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, },
7734 { 8187 /* shilov */, Mips::SHILOV, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__Tie0_1_1, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, },
7735 { 8194 /* shll.ph */, Mips::SHLL_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
7736 { 8194 /* shll.ph */, Mips::SHLL_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
7737 { 8202 /* shll.qb */, Mips::SHLL_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm3_0 }, },
7738 { 8202 /* shll.qb */, Mips::SHLL_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm3_0 }, },
7739 { 8210 /* shll_s.ph */, Mips::SHLL_S_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
7740 { 8210 /* shll_s.ph */, Mips::SHLL_S_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
7741 { 8220 /* shll_s.w */, Mips::SHLL_S_W_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7742 { 8220 /* shll_s.w */, Mips::SHLL_S_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7743 { 8229 /* shllv.ph */, Mips::SHLLV_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7744 { 8229 /* shllv.ph */, Mips::SHLLV_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7745 { 8238 /* shllv.qb */, Mips::SHLLV_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7746 { 8238 /* shllv.qb */, Mips::SHLLV_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7747 { 8247 /* shllv_s.ph */, Mips::SHLLV_S_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7748 { 8247 /* shllv_s.ph */, Mips::SHLLV_S_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7749 { 8258 /* shllv_s.w */, Mips::SHLLV_S_W_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7750 { 8258 /* shllv_s.w */, Mips::SHLLV_S_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7751 { 8268 /* shra.ph */, Mips::SHRA_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
7752 { 8268 /* shra.ph */, Mips::SHRA_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
7753 { 8276 /* shra.qb */, Mips::SHRA_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm3_0 }, },
7754 { 8276 /* shra.qb */, Mips::SHRA_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm3_0 }, },
7755 { 8284 /* shra_r.ph */, Mips::SHRA_R_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
7756 { 8284 /* shra_r.ph */, Mips::SHRA_R_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
7757 { 8294 /* shra_r.qb */, Mips::SHRA_R_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm3_0 }, },
7758 { 8294 /* shra_r.qb */, Mips::SHRA_R_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm3_0 }, },
7759 { 8304 /* shra_r.w */, Mips::SHRA_R_W_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7760 { 8304 /* shra_r.w */, Mips::SHRA_R_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7761 { 8313 /* shrav.ph */, Mips::SHRAV_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7762 { 8313 /* shrav.ph */, Mips::SHRAV_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7763 { 8322 /* shrav.qb */, Mips::SHRAV_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7764 { 8322 /* shrav.qb */, Mips::SHRAV_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7765 { 8331 /* shrav_r.ph */, Mips::SHRAV_R_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7766 { 8331 /* shrav_r.ph */, Mips::SHRAV_R_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7767 { 8342 /* shrav_r.qb */, Mips::SHRAV_R_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7768 { 8342 /* shrav_r.qb */, Mips::SHRAV_R_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7769 { 8353 /* shrav_r.w */, Mips::SHRAV_R_W_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7770 { 8353 /* shrav_r.w */, Mips::SHRAV_R_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7771 { 8363 /* shrl.ph */, Mips::SHRL_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
7772 { 8363 /* shrl.ph */, Mips::SHRL_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
7773 { 8371 /* shrl.qb */, Mips::SHRL_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm3_0 }, },
7774 { 8371 /* shrl.qb */, Mips::SHRL_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm3_0 }, },
7775 { 8379 /* shrlv.ph */, Mips::SHRLV_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7776 { 8379 /* shrlv.ph */, Mips::SHRLV_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7777 { 8388 /* shrlv.qb */, Mips::SHRLV_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7778 { 8388 /* shrlv.qb */, Mips::SHRLV_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7779 { 8397 /* sigrie */, Mips::SIGRIE, Convert__imm_95_0, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { }, },
7780 { 8397 /* sigrie */, Mips::SIGRIE_MMR6, Convert__imm_95_0, AMFBS_InMicroMips_HasMips32r6, { }, },
7781 { 8397 /* sigrie */, Mips::SIGRIE, Convert__UImm161_0, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_UImm16 }, },
7782 { 8397 /* sigrie */, Mips::SIGRIE_MMR6, Convert__UImm161_0, AMFBS_InMicroMips_HasMips32r6, { MCK_UImm16 }, },
7783 { 8404 /* sld.b */, Mips::SLD_B, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__GPR32AsmReg1_3, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_GPR32AsmReg, MCK__93_ }, },
7784 { 8410 /* sld.d */, Mips::SLD_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__GPR32AsmReg1_3, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_GPR32AsmReg, MCK__93_ }, },
7785 { 8416 /* sld.h */, Mips::SLD_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__GPR32AsmReg1_3, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_GPR32AsmReg, MCK__93_ }, },
7786 { 8422 /* sld.w */, Mips::SLD_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__GPR32AsmReg1_3, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_GPR32AsmReg, MCK__93_ }, },
7787 { 8428 /* sldi.b */, Mips::SLDI_B, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm4_01_3, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm4_0, MCK__93_ }, },
7788 { 8435 /* sldi.d */, Mips::SLDI_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm1_01_3, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm1_0, MCK__93_ }, },
7789 { 8442 /* sldi.h */, Mips::SLDI_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm3_01_3, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm3_0, MCK__93_ }, },
7790 { 8449 /* sldi.w */, Mips::SLDI_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm2_01_3, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm2_0, MCK__93_ }, },
7791 { 8456 /* sle */, Mips::SLE, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7792 { 8456 /* sle */, Mips::SLEImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm321_1, AMFBS_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm32 }, },
7793 { 8456 /* sle */, Mips::SLEImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, AMFBS_IsGP64bit, { MCK_GPR64AsmReg, MCK_Imm }, },
7794 { 8456 /* sle */, Mips::SLE, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7795 { 8456 /* sle */, Mips::SLEImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm321_2, AMFBS_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32 }, },
7796 { 8456 /* sle */, Mips::SLEImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, AMFBS_IsGP64bit, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, },
7797 { 8460 /* sleu */, Mips::SLEU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7798 { 8460 /* sleu */, Mips::SLEUImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm32_Coerced1_1, AMFBS_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_UImm32_Coerced }, },
7799 { 8460 /* sleu */, Mips::SLEUImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, AMFBS_IsGP64bit, { MCK_GPR64AsmReg, MCK_Imm }, },
7800 { 8460 /* sleu */, Mips::SLEU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7801 { 8460 /* sleu */, Mips::SLEUImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm32_Coerced1_2, AMFBS_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm32_Coerced }, },
7802 { 8460 /* sleu */, Mips::SLEUImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, AMFBS_IsGP64bit, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, },
7803 { 8465 /* sll */, Mips::SLLV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7804 { 8465 /* sll */, Mips::SLLV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7805 { 8465 /* sll */, Mips::SLL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7806 { 8465 /* sll */, Mips::SLL_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7807 { 8465 /* sll */, Mips::SLL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7808 { 8465 /* sll */, Mips::SLL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7809 { 8465 /* sll */, Mips::SllX16, Convert__Reg1_0__Reg1_1__ConstantUImm5_01_2, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs, MCK_ConstantUImm5_0 }, },
7810 { 8465 /* sll */, Mips::SLLV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7811 { 8465 /* sll */, Mips::SLLV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7812 { 8465 /* sll */, Mips::SLL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7813 { 8465 /* sll */, Mips::SLL_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7814 { 8465 /* sll */, Mips::SLL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7815 { 8469 /* sll.b */, Mips::SLL_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7816 { 8475 /* sll.d */, Mips::SLL_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7817 { 8481 /* sll.h */, Mips::SLL_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7818 { 8487 /* sll.w */, Mips::SLL_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7819 { 8493 /* sll16 */, Mips::SLL16_MM, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Imm1_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_Imm }, },
7820 { 8493 /* sll16 */, Mips::SLL16_MMR6, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Imm1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_Imm }, },
7821 { 8499 /* slli.b */, Mips::SLLI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, },
7822 { 8506 /* slli.d */, Mips::SLLI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, },
7823 { 8513 /* slli.h */, Mips::SLLI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, },
7824 { 8520 /* slli.w */, Mips::SLLI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
7825 { 8527 /* sllv */, Mips::SllvRxRy16, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs }, },
7826 { 8527 /* sllv */, Mips::SLLV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7827 { 8527 /* sllv */, Mips::SLLV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7828 { 8532 /* slt */, Mips::SltRxRy16, Convert__Reg1_0__Reg1_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs }, },
7829 { 8532 /* slt */, Mips::SLTi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
7830 { 8532 /* slt */, Mips::SLTi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
7831 { 8532 /* slt */, Mips::SLTImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, AMFBS_IsGP64bit, { MCK_GPR64AsmReg, MCK_Imm }, },
7832 { 8532 /* slt */, Mips::SLT, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7833 { 8532 /* slt */, Mips::SLT_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7834 { 8532 /* slt */, Mips::SLTi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
7835 { 8532 /* slt */, Mips::SLTi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
7836 { 8532 /* slt */, Mips::SLTImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, AMFBS_IsGP64bit, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, },
7837 { 8536 /* slti */, Mips::SltiRxImmX16, Convert__Reg1_0__SImm161_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_SImm16 }, },
7838 { 8536 /* slti */, Mips::SLTi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16 }, },
7839 { 8536 /* slti */, Mips::SLTi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16 }, },
7840 { 8536 /* slti */, Mips::SltiRxImm16, Convert__Reg1_0__SImm161_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_SImm16, MCK__HASH_, MCK_16, MCK_bit, MCK_inst }, },
7841 { 8541 /* sltiu */, Mips::SltiuRxImmX16, Convert__Reg1_0__SImm161_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_SImm16 }, },
7842 { 8541 /* sltiu */, Mips::SLTiu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16 }, },
7843 { 8541 /* sltiu */, Mips::SLTiu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16 }, },
7844 { 8541 /* sltiu */, Mips::SltiuRxImm16, Convert__Reg1_0__SImm161_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_SImm16, MCK__HASH_, MCK_16, MCK_bit, MCK_inst }, },
7845 { 8547 /* sltu */, Mips::SltuRxRy16, Convert__Reg1_0__Reg1_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs }, },
7846 { 8547 /* sltu */, Mips::SLTiu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
7847 { 8547 /* sltu */, Mips::SLTiu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
7848 { 8547 /* sltu */, Mips::SLTUImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, AMFBS_IsGP64bit, { MCK_GPR64AsmReg, MCK_Imm }, },
7849 { 8547 /* sltu */, Mips::SLTu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7850 { 8547 /* sltu */, Mips::SLTu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7851 { 8547 /* sltu */, Mips::SLTiu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
7852 { 8547 /* sltu */, Mips::SLTiu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
7853 { 8547 /* sltu */, Mips::SLTUImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, AMFBS_IsGP64bit, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, },
7854 { 8552 /* sne */, Mips::SNEMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_NotCnMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7855 { 8552 /* sne */, Mips::SNEIMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm321_1, AMFBS_NotCnMips, { MCK_GPR32AsmReg, MCK_SImm32 }, },
7856 { 8552 /* sne */, Mips::SNE, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
7857 { 8552 /* sne */, Mips::SNEMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_NotCnMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7858 { 8552 /* sne */, Mips::SNEIMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_NotCnMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
7859 { 8552 /* sne */, Mips::SNE, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
7860 { 8556 /* snei */, Mips::SNEi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantSImm10_01_1, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_ConstantSImm10_0 }, },
7861 { 8556 /* snei */, Mips::SNEi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantSImm10_01_2, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantSImm10_0 }, },
7862 { 8561 /* splat.b */, Mips::SPLAT_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__GPR32AsmReg1_3, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_GPR32AsmReg, MCK__93_ }, },
7863 { 8569 /* splat.d */, Mips::SPLAT_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__GPR32AsmReg1_3, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_GPR32AsmReg, MCK__93_ }, },
7864 { 8577 /* splat.h */, Mips::SPLAT_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__GPR32AsmReg1_3, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_GPR32AsmReg, MCK__93_ }, },
7865 { 8585 /* splat.w */, Mips::SPLAT_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__GPR32AsmReg1_3, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_GPR32AsmReg, MCK__93_ }, },
7866 { 8593 /* splati.b */, Mips::SPLATI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_3, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm4_0, MCK__93_ }, },
7867 { 8602 /* splati.d */, Mips::SPLATI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm1_01_3, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm1_0, MCK__93_ }, },
7868 { 8611 /* splati.h */, Mips::SPLATI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_3, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm3_0, MCK__93_ }, },
7869 { 8620 /* splati.w */, Mips::SPLATI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm2_01_3, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm2_0, MCK__93_ }, },
7870 { 8629 /* sqrt.d */, Mips::FSQRT_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
7871 { 8629 /* sqrt.d */, Mips::FSQRT_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
7872 { 8629 /* sqrt.d */, Mips::FSQRT_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7873 { 8629 /* sqrt.d */, Mips::FSQRT_D64_MM, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7874 { 8636 /* sqrt.s */, Mips::FSQRT_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7875 { 8636 /* sqrt.s */, Mips::FSQRT_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7876 { 8643 /* sra */, Mips::SRAV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7877 { 8643 /* sra */, Mips::SRAV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7878 { 8643 /* sra */, Mips::SRA, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7879 { 8643 /* sra */, Mips::SRA_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7880 { 8643 /* sra */, Mips::SRA_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7881 { 8643 /* sra */, Mips::SraX16, Convert__Reg1_0__Reg1_1__ConstantUImm5_01_2, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs, MCK_ConstantUImm5_0 }, },
7882 { 8643 /* sra */, Mips::SRAV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7883 { 8643 /* sra */, Mips::SRAV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7884 { 8643 /* sra */, Mips::SRA, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7885 { 8643 /* sra */, Mips::SRA_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7886 { 8647 /* sra.b */, Mips::SRA_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7887 { 8653 /* sra.d */, Mips::SRA_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7888 { 8659 /* sra.h */, Mips::SRA_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7889 { 8665 /* sra.w */, Mips::SRA_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7890 { 8671 /* srai.b */, Mips::SRAI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, },
7891 { 8678 /* srai.d */, Mips::SRAI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, },
7892 { 8685 /* srai.h */, Mips::SRAI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, },
7893 { 8692 /* srai.w */, Mips::SRAI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
7894 { 8699 /* srar.b */, Mips::SRAR_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7895 { 8706 /* srar.d */, Mips::SRAR_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7896 { 8713 /* srar.h */, Mips::SRAR_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7897 { 8720 /* srar.w */, Mips::SRAR_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7898 { 8727 /* srari.b */, Mips::SRARI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, },
7899 { 8735 /* srari.d */, Mips::SRARI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, },
7900 { 8743 /* srari.h */, Mips::SRARI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, },
7901 { 8751 /* srari.w */, Mips::SRARI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
7902 { 8759 /* srav */, Mips::SravRxRy16, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs }, },
7903 { 8759 /* srav */, Mips::SRAV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7904 { 8759 /* srav */, Mips::SRAV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7905 { 8764 /* srl */, Mips::SRLV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7906 { 8764 /* srl */, Mips::SRLV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7907 { 8764 /* srl */, Mips::SRL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7908 { 8764 /* srl */, Mips::SRL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7909 { 8764 /* srl */, Mips::SRL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7910 { 8764 /* srl */, Mips::SrlX16, Convert__Reg1_0__Reg1_1__ConstantUImm5_01_2, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs, MCK_ConstantUImm5_0 }, },
7911 { 8764 /* srl */, Mips::SRLV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7912 { 8764 /* srl */, Mips::SRLV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7913 { 8764 /* srl */, Mips::SRL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7914 { 8764 /* srl */, Mips::SRL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7915 { 8768 /* srl.b */, Mips::SRL_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7916 { 8774 /* srl.d */, Mips::SRL_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7917 { 8780 /* srl.h */, Mips::SRL_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7918 { 8786 /* srl.w */, Mips::SRL_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7919 { 8792 /* srl16 */, Mips::SRL16_MM, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Imm1_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_Imm }, },
7920 { 8792 /* srl16 */, Mips::SRL16_MMR6, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Imm1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_Imm }, },
7921 { 8798 /* srli.b */, Mips::SRLI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, },
7922 { 8805 /* srli.d */, Mips::SRLI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, },
7923 { 8812 /* srli.h */, Mips::SRLI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, },
7924 { 8819 /* srli.w */, Mips::SRLI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
7925 { 8826 /* srlr.b */, Mips::SRLR_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7926 { 8833 /* srlr.d */, Mips::SRLR_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7927 { 8840 /* srlr.h */, Mips::SRLR_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7928 { 8847 /* srlr.w */, Mips::SRLR_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7929 { 8854 /* srlri.b */, Mips::SRLRI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, },
7930 { 8862 /* srlri.d */, Mips::SRLRI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, },
7931 { 8870 /* srlri.h */, Mips::SRLRI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, },
7932 { 8878 /* srlri.w */, Mips::SRLRI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
7933 { 8886 /* srlv */, Mips::SrlvRxRy16, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs }, },
7934 { 8886 /* srlv */, Mips::SRLV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7935 { 8886 /* srlv */, Mips::SRLV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7936 { 8891 /* ssnop */, Mips::SSNOP, Convert_NoOperands, AMFBS_HasStdEnc_NotInMicroMips, { }, },
7937 { 8891 /* ssnop */, Mips::SSNOP_MMR6, Convert_NoOperands, AMFBS_InMicroMips_HasMips32r6, { }, },
7938 { 8891 /* ssnop */, Mips::SSNOP_MM, Convert_NoOperands, AMFBS_InMicroMips, { }, },
7939 { 8897 /* st.b */, Mips::ST_B, Convert__MSA128AsmReg1_0__MemOffsetSimm10_02_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MemOffsetSimm10_0 }, },
7940 { 8902 /* st.d */, Mips::ST_D, Convert__MSA128AsmReg1_0__MemOffsetSimm10_32_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MemOffsetSimm10_3 }, },
7941 { 8907 /* st.h */, Mips::ST_H, Convert__MSA128AsmReg1_0__MemOffsetSimm10_12_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MemOffsetSimm10_1 }, },
7942 { 8912 /* st.w */, Mips::ST_W, Convert__MSA128AsmReg1_0__MemOffsetSimm10_22_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MemOffsetSimm10_2 }, },
7943 { 8917 /* sub */, Mips::SUB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7944 { 8917 /* sub */, Mips::SUB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7945 { 8917 /* sub */, Mips::SUB_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7946 { 8917 /* sub */, Mips::ADDi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__InvNum1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_InvNum }, },
7947 { 8917 /* sub */, Mips::SUB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7948 { 8917 /* sub */, Mips::SUB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7949 { 8917 /* sub */, Mips::SUB_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7950 { 8917 /* sub */, Mips::ADDi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__InvNum1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_InvNum }, },
7951 { 8921 /* sub.d */, Mips::FSUB_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
7952 { 8921 /* sub.d */, Mips::FSUB_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
7953 { 8921 /* sub.d */, Mips::FSUB_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7954 { 8921 /* sub.d */, Mips::FSUB_D64_MM, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7955 { 8927 /* sub.ps */, Mips::FSUB_PS64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7956 { 8934 /* sub.s */, Mips::FSUB_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7957 { 8934 /* sub.s */, Mips::FSUB_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_2__FGR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7958 { 8934 /* sub.s */, Mips::FSUB_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7959 { 8940 /* subq.ph */, Mips::SUBQ_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7960 { 8940 /* subq.ph */, Mips::SUBQ_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7961 { 8948 /* subq_s.ph */, Mips::SUBQ_S_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7962 { 8948 /* subq_s.ph */, Mips::SUBQ_S_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7963 { 8958 /* subq_s.w */, Mips::SUBQ_S_W_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7964 { 8958 /* subq_s.w */, Mips::SUBQ_S_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7965 { 8967 /* subqh.ph */, Mips::SUBQH_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7966 { 8967 /* subqh.ph */, Mips::SUBQH_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7967 { 8976 /* subqh.w */, Mips::SUBQH_W_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7968 { 8976 /* subqh.w */, Mips::SUBQH_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7969 { 8984 /* subqh_r.ph */, Mips::SUBQH_R_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7970 { 8984 /* subqh_r.ph */, Mips::SUBQH_R_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7971 { 8995 /* subqh_r.w */, Mips::SUBQH_R_W_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7972 { 8995 /* subqh_r.w */, Mips::SUBQH_R_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7973 { 9005 /* subs_s.b */, Mips::SUBS_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7974 { 9014 /* subs_s.d */, Mips::SUBS_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7975 { 9023 /* subs_s.h */, Mips::SUBS_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7976 { 9032 /* subs_s.w */, Mips::SUBS_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7977 { 9041 /* subs_u.b */, Mips::SUBS_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7978 { 9050 /* subs_u.d */, Mips::SUBS_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7979 { 9059 /* subs_u.h */, Mips::SUBS_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7980 { 9068 /* subs_u.w */, Mips::SUBS_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7981 { 9077 /* subsus_u.b */, Mips::SUBSUS_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7982 { 9088 /* subsus_u.d */, Mips::SUBSUS_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7983 { 9099 /* subsus_u.h */, Mips::SUBSUS_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7984 { 9110 /* subsus_u.w */, Mips::SUBSUS_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7985 { 9121 /* subsuu_s.b */, Mips::SUBSUU_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7986 { 9132 /* subsuu_s.d */, Mips::SUBSUU_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7987 { 9143 /* subsuu_s.h */, Mips::SUBSUU_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7988 { 9154 /* subsuu_s.w */, Mips::SUBSUU_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7989 { 9165 /* subu */, Mips::SUBU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7990 { 9165 /* subu */, Mips::SUBu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7991 { 9165 /* subu */, Mips::SUBu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7992 { 9165 /* subu */, Mips::ADDiu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__InvNum1_1, AMFBS_None, { MCK_GPR32AsmReg, MCK_InvNum }, },
7993 { 9165 /* subu */, Mips::SubuRxRyRz16, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs, MCK_CPU16Regs }, },
7994 { 9165 /* subu */, Mips::SUBU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7995 { 9165 /* subu */, Mips::SUBu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7996 { 9165 /* subu */, Mips::SUBu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7997 { 9165 /* subu */, Mips::ADDiu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__InvNum1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_InvNum }, },
7998 { 9170 /* subu.ph */, Mips::SUBU_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7999 { 9170 /* subu.ph */, Mips::SUBU_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
8000 { 9178 /* subu.qb */, Mips::SUBU_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
8001 { 9178 /* subu.qb */, Mips::SUBU_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
8002 { 9186 /* subu16 */, Mips::SUBU16_MM, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__GPRMM16AsmReg1_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, },
8003 { 9186 /* subu16 */, Mips::SUBU16_MMR6, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__GPRMM16AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, },
8004 { 9193 /* subu_s.ph */, Mips::SUBU_S_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
8005 { 9193 /* subu_s.ph */, Mips::SUBU_S_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
8006 { 9203 /* subu_s.qb */, Mips::SUBU_S_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
8007 { 9203 /* subu_s.qb */, Mips::SUBU_S_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
8008 { 9213 /* subuh.qb */, Mips::SUBUH_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
8009 { 9213 /* subuh.qb */, Mips::SUBUH_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
8010 { 9222 /* subuh_r.qb */, Mips::SUBUH_R_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
8011 { 9222 /* subuh_r.qb */, Mips::SUBUH_R_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
8012 { 9233 /* subv.b */, Mips::SUBV_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
8013 { 9240 /* subv.d */, Mips::SUBV_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
8014 { 9247 /* subv.h */, Mips::SUBV_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
8015 { 9254 /* subv.w */, Mips::SUBV_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
8016 { 9261 /* subvi.b */, Mips::SUBVI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
8017 { 9269 /* subvi.d */, Mips::SUBVI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
8018 { 9277 /* subvi.h */, Mips::SUBVI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
8019 { 9285 /* subvi.w */, Mips::SUBVI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
8020 { 9293 /* suxc1 */, Mips::SUXC1, Convert__AFGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
8021 { 9293 /* suxc1 */, Mips::SUXC164, Convert__FGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
8022 { 9293 /* suxc1 */, Mips::SUXC1_MM, Convert__FGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
8023 { 9299 /* sw */, Mips::SWSP_MMR6, Convert__GPR32AsmReg1_0__MicroMipsMemSP2_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_MicroMipsMemSP }, },
8024 { 9299 /* sw */, Mips::SWSP_MM, Convert__GPR32AsmReg1_0__MicroMipsMemSP2_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_MicroMipsMemSP }, },
8025 { 9299 /* sw */, Mips::SW, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
8026 { 9299 /* sw */, Mips::SWDSP, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_NotInMips16Mode_HasDSP, { MCK_GPR32AsmReg, MCK_Mem }, },
8027 { 9299 /* sw */, Mips::SWDSP_MM, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_Mem }, },
8028 { 9299 /* sw */, Mips::SW_MMR6, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_Mem }, },
8029 { 9299 /* sw */, Mips::SW_MM, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
8030 { 9299 /* sw */, Mips::SwRxRyOffMemX16, Convert__Reg1_0__Reg1_1__SImm161_2, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs, MCK_SImm16 }, },
8031 { 9299 /* sw */, Mips::SwRxSpImmX16, Convert__Reg1_0__Reg1_1__SImm161_2, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16RegsPlusSP, MCK_SImm16 }, },
8032 { 9302 /* sw16 */, Mips::SW16_MM, Convert__GPRMM16AsmRegZero1_0__MicroMipsMem2_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPRMM16AsmRegZero, MCK_MicroMipsMem }, },
8033 { 9302 /* sw16 */, Mips::SW16_MMR6, Convert__GPRMM16AsmRegZero1_0__MicroMipsMem2_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPRMM16AsmRegZero, MCK_MicroMipsMem }, },
8034 { 9307 /* swc1 */, Mips::SWC1, Convert__FGR32AsmReg1_0__MemOffsetSimm16_02_1, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_MemOffsetSimm16_0 }, },
8035 { 9307 /* swc1 */, Mips::SWC1_MM, Convert__FGR32AsmReg1_0__MemOffsetSimm16_02_1, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_MemOffsetSimm16_0 }, },
8036 { 9312 /* swc2 */, Mips::SWC2_R6, Convert__COP2AsmReg1_0__MemOffsetSimm11_02_1, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_COP2AsmReg, MCK_MemOffsetSimm11_0 }, },
8037 { 9312 /* swc2 */, Mips::SWC2_MMR6, Convert__COP2AsmReg1_0__MemOffsetSimm11_02_1, AMFBS_InMicroMips_HasMips32r6, { MCK_COP2AsmReg, MCK_MemOffsetSimm11_0 }, },
8038 { 9312 /* swc2 */, Mips::SWC2, Convert__COP2AsmReg1_0__MemOffsetSimm16_02_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_COP2AsmReg, MCK_MemOffsetSimm16_0 }, },
8039 { 9317 /* swc3 */, Mips::SWC3, Convert__COP3AsmReg1_0__Mem2_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_NotCnMips_NotInMicroMips, { MCK_COP3AsmReg, MCK_Mem }, },
8040 { 9322 /* swe */, Mips::SWE, Convert__GPR32AsmReg1_0__MemOffsetSimm9_02_1, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9_0 }, },
8041 { 9322 /* swe */, Mips::SWE_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm9_02_1, AMFBS_InMicroMips_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9_0 }, },
8042 { 9326 /* swl */, Mips::SWL, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
8043 { 9326 /* swl */, Mips::SWL_MM, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_Mem }, },
8044 { 9330 /* swle */, Mips::SWLE, Convert__GPR32AsmReg1_0__MemOffsetSimm9_02_1, AMFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9_0 }, },
8045 { 9330 /* swle */, Mips::SWLE_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm9_02_1, AMFBS_InMicroMips_NotMips32r6_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9_0 }, },
8046 { 9335 /* swm */, Mips::SWM_MM, Convert__RegList1_0__Mem2_1, AMFBS_InMicroMips, { MCK_RegList, MCK_Mem }, },
8047 { 9339 /* swm16 */, Mips::SWM16_MM, Convert__RegList161_0__MemOffsetUimm42_1, AMFBS_InMicroMips_NotMips32r6, { MCK_RegList16, MCK_MemOffsetUimm4 }, },
8048 { 9339 /* swm16 */, Mips::SWM16_MMR6, Convert__RegList161_0__MemOffsetUimm42_1, AMFBS_InMicroMips_HasMips32r6, { MCK_RegList16, MCK_MemOffsetUimm4 }, },
8049 { 9345 /* swm32 */, Mips::SWM32_MM, Convert__RegList1_0__Mem2_1, AMFBS_InMicroMips, { MCK_RegList, MCK_Mem }, },
8050 { 9351 /* swp */, Mips::SWP_MM, ConvertCustom_ConvertXWPOperands, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm12_0 }, },
8051 { 9355 /* swr */, Mips::SWR, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
8052 { 9355 /* swr */, Mips::SWR_MM, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_Mem }, },
8053 { 9359 /* swre */, Mips::SWRE, Convert__GPR32AsmReg1_0__MemOffsetSimm9_02_1, AMFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9_0 }, },
8054 { 9359 /* swre */, Mips::SWRE_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm9_02_1, AMFBS_InMicroMips_NotMips32r6_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9_0 }, },
8055 { 9364 /* swsp */, Mips::SWSP_MM, Convert__GPR32AsmReg1_0__MicroMipsMemSP2_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_MicroMipsMemSP }, },
8056 { 9369 /* swxc1 */, Mips::SWXC1, Convert__FGR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
8057 { 9369 /* swxc1 */, Mips::SWXC1_MM, Convert__FGR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
8058 { 9375 /* sync */, Mips::SYNC, Convert__imm_95_0, AMFBS_HasStdEnc_HasMips2_NotInMicroMips, { }, },
8059 { 9375 /* sync */, Mips::SYNC_MMR6, Convert__imm_95_0, AMFBS_InMicroMips_HasMips32r6, { }, },
8060 { 9375 /* sync */, Mips::SYNC_MM, Convert__imm_95_0, AMFBS_InMicroMips, { }, },
8061 { 9375 /* sync */, Mips::SYNC, Convert__ConstantUImm5_01_0, AMFBS_HasStdEnc_HasMips2_NotInMicroMips, { MCK_ConstantUImm5_0 }, },
8062 { 9375 /* sync */, Mips::SYNC_MMR6, Convert__ConstantUImm5_01_0, AMFBS_InMicroMips_HasMips32r6, { MCK_ConstantUImm5_0 }, },
8063 { 9375 /* sync */, Mips::SYNC_MM, Convert__ConstantUImm5_01_0, AMFBS_InMicroMips, { MCK_ConstantUImm5_0 }, },
8064 { 9380 /* sync_acquire */, Mips::SYNC, Convert__imm_95_17, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips, { }, },
8065 { 9393 /* sync_mb */, Mips::SYNC, Convert__imm_95_16, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips, { }, },
8066 { 9401 /* sync_release */, Mips::SYNC, Convert__imm_95_18, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips, { }, },
8067 { 9414 /* sync_rmb */, Mips::SYNC, Convert__imm_95_19, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips, { }, },
8068 { 9423 /* sync_wmb */, Mips::SYNC, Convert__imm_95_4, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips, { }, },
8069 { 9432 /* synci */, Mips::SYNCI, Convert__MemOffsetSimm16_02_0, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips, { MCK_MemOffsetSimm16_0 }, },
8070 { 9432 /* synci */, Mips::SYNCI_MM, Convert__MemOffsetSimm16_02_0, AMFBS_InMicroMips_NotMips32r6, { MCK_MemOffsetSimm16_0 }, },
8071 { 9432 /* synci */, Mips::SYNCI_MMR6, Convert__MemOffsetSimm16_02_0, AMFBS_InMicroMips_HasMips32r6, { MCK_MemOffsetSimm16_0 }, },
8072 { 9438 /* synciobdma */, Mips::SYNC, Convert__imm_95_2, AMFBS_HasMips64_HasCnMips, { }, },
8073 { 9449 /* syncs */, Mips::SYNC, Convert__imm_95_6, AMFBS_HasMips64_HasCnMips, { }, },
8074 { 9455 /* syncw */, Mips::SYNC, Convert__imm_95_4, AMFBS_HasMips64_HasCnMips, { }, },
8075 { 9461 /* syncws */, Mips::SYNC, Convert__imm_95_5, AMFBS_HasMips64_HasCnMips, { }, },
8076 { 9468 /* syscall */, Mips::SYSCALL, Convert__imm_95_0, AMFBS_HasStdEnc_NotInMicroMips, { }, },
8077 { 9468 /* syscall */, Mips::SYSCALL_MM, Convert__imm_95_0, AMFBS_InMicroMips, { }, },
8078 { 9468 /* syscall */, Mips::SYSCALL_MM, Convert__ConstantUImm10_01_0, AMFBS_InMicroMips, { MCK_ConstantUImm10_0 }, },
8079 { 9468 /* syscall */, Mips::SYSCALL, Convert__ConstantUImm20_01_0, AMFBS_HasStdEnc_NotInMicroMips, { MCK_ConstantUImm20_0 }, },
8080 { 9476 /* teq */, Mips::TEQ, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, AMFBS_HasStdEnc_HasMips2_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
8081 { 9476 /* teq */, Mips::TEQ_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
8082 { 9476 /* teq */, Mips::TEQ_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
8083 { 9476 /* teq */, Mips::TEQ, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm10_01_2, AMFBS_HasStdEnc_HasMips2_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm10_0 }, },
8084 { 9480 /* teqi */, Mips::TEQI, Convert__GPR32AsmReg1_0__SImm161_1, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm16 }, },
8085 { 9480 /* teqi */, Mips::TEQI_MM, Convert__GPR32AsmReg1_0__SImm161_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, },
8086 { 9485 /* tge */, Mips::TGE, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, AMFBS_HasStdEnc_HasMips2_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
8087 { 9485 /* tge */, Mips::TGE_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
8088 { 9485 /* tge */, Mips::TGE_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
8089 { 9485 /* tge */, Mips::TGE, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm10_01_2, AMFBS_HasStdEnc_HasMips2_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm10_0 }, },
8090 { 9489 /* tgei */, Mips::TGEI, Convert__GPR32AsmReg1_0__SImm161_1, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm16 }, },
8091 { 9489 /* tgei */, Mips::TGEI_MM, Convert__GPR32AsmReg1_0__SImm161_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, },
8092 { 9494 /* tgeiu */, Mips::TGEIU, Convert__GPR32AsmReg1_0__SImm161_1, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm16 }, },
8093 { 9494 /* tgeiu */, Mips::TGEIU_MM, Convert__GPR32AsmReg1_0__SImm161_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, },
8094 { 9500 /* tgeu */, Mips::TGEU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, AMFBS_HasStdEnc_HasMips2_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
8095 { 9500 /* tgeu */, Mips::TGEU_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
8096 { 9500 /* tgeu */, Mips::TGEU_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
8097 { 9500 /* tgeu */, Mips::TGEU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm10_01_2, AMFBS_HasStdEnc_HasMips2_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm10_0 }, },
8098 { 9505 /* tlbginv */, Mips::TLBGINV, Convert_NoOperands, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, { }, },
8099 { 9505 /* tlbginv */, Mips::TLBGINV_MM, Convert_NoOperands, AMFBS_InMicroMips_HasMips32r5_HasVirt, { }, },
8100 { 9513 /* tlbginvf */, Mips::TLBGINVF, Convert_NoOperands, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, { }, },
8101 { 9513 /* tlbginvf */, Mips::TLBGINVF_MM, Convert_NoOperands, AMFBS_InMicroMips_HasMips32r5_HasVirt, { }, },
8102 { 9522 /* tlbgp */, Mips::TLBGP, Convert_NoOperands, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, { }, },
8103 { 9522 /* tlbgp */, Mips::TLBGP_MM, Convert_NoOperands, AMFBS_InMicroMips_HasMips32r5_HasVirt, { }, },
8104 { 9528 /* tlbgr */, Mips::TLBGR, Convert_NoOperands, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, { }, },
8105 { 9528 /* tlbgr */, Mips::TLBGR_MM, Convert_NoOperands, AMFBS_InMicroMips_HasMips32r5_HasVirt, { }, },
8106 { 9534 /* tlbgwi */, Mips::TLBGWI, Convert_NoOperands, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, { }, },
8107 { 9534 /* tlbgwi */, Mips::TLBGWI_MM, Convert_NoOperands, AMFBS_InMicroMips_HasMips32r5_HasVirt, { }, },
8108 { 9541 /* tlbgwr */, Mips::TLBGWR, Convert_NoOperands, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, { }, },
8109 { 9541 /* tlbgwr */, Mips::TLBGWR_MM, Convert_NoOperands, AMFBS_InMicroMips_HasMips32r5_HasVirt, { }, },
8110 { 9548 /* tlbinv */, Mips::TLBINV, Convert_NoOperands, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, { }, },
8111 { 9548 /* tlbinv */, Mips::TLBINV_MMR6, Convert_NoOperands, AMFBS_InMicroMips_HasMips32r6, { }, },
8112 { 9555 /* tlbinvf */, Mips::TLBINVF, Convert_NoOperands, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, { }, },
8113 { 9555 /* tlbinvf */, Mips::TLBINVF_MMR6, Convert_NoOperands, AMFBS_InMicroMips_HasMips32r6, { }, },
8114 { 9563 /* tlbp */, Mips::TLBP, Convert_NoOperands, AMFBS_HasStdEnc_NotInMicroMips, { }, },
8115 { 9563 /* tlbp */, Mips::TLBP_MM, Convert_NoOperands, AMFBS_InMicroMips, { }, },
8116 { 9568 /* tlbr */, Mips::TLBR, Convert_NoOperands, AMFBS_HasStdEnc_NotInMicroMips, { }, },
8117 { 9568 /* tlbr */, Mips::TLBR_MM, Convert_NoOperands, AMFBS_InMicroMips, { }, },
8118 { 9573 /* tlbwi */, Mips::TLBWI, Convert_NoOperands, AMFBS_HasStdEnc_NotInMicroMips, { }, },
8119 { 9573 /* tlbwi */, Mips::TLBWI_MM, Convert_NoOperands, AMFBS_InMicroMips, { }, },
8120 { 9579 /* tlbwr */, Mips::TLBWR, Convert_NoOperands, AMFBS_HasStdEnc_NotInMicroMips, { }, },
8121 { 9579 /* tlbwr */, Mips::TLBWR_MM, Convert_NoOperands, AMFBS_InMicroMips, { }, },
8122 { 9585 /* tlt */, Mips::TLT, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, AMFBS_HasStdEnc_HasMips2_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
8123 { 9585 /* tlt */, Mips::TLT_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
8124 { 9585 /* tlt */, Mips::TLT_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
8125 { 9585 /* tlt */, Mips::TLT, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm10_01_2, AMFBS_HasStdEnc_HasMips2_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm10_0 }, },
8126 { 9589 /* tlti */, Mips::TLTI, Convert__GPR32AsmReg1_0__SImm161_1, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm16 }, },
8127 { 9589 /* tlti */, Mips::TLTI_MM, Convert__GPR32AsmReg1_0__SImm161_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, },
8128 { 9594 /* tltiu */, Mips::TTLTIU, Convert__GPR32AsmReg1_0__SImm161_1, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm16 }, },
8129 { 9594 /* tltiu */, Mips::TLTIU_MM, Convert__GPR32AsmReg1_0__SImm161_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, },
8130 { 9600 /* tltu */, Mips::TLTU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, AMFBS_HasStdEnc_HasMips2_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
8131 { 9600 /* tltu */, Mips::TLTU_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
8132 { 9600 /* tltu */, Mips::TLTU_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
8133 { 9600 /* tltu */, Mips::TLTU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm10_01_2, AMFBS_HasStdEnc_HasMips2_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm10_0 }, },
8134 { 9605 /* tne */, Mips::TNE, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, AMFBS_HasStdEnc_HasMips2_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
8135 { 9605 /* tne */, Mips::TNE_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
8136 { 9605 /* tne */, Mips::TNE_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
8137 { 9605 /* tne */, Mips::TNE, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm10_01_2, AMFBS_HasStdEnc_HasMips2_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm10_0 }, },
8138 { 9609 /* tnei */, Mips::TNEI, Convert__GPR32AsmReg1_0__SImm161_1, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm16 }, },
8139 { 9609 /* tnei */, Mips::TNEI_MM, Convert__GPR32AsmReg1_0__SImm161_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, },
8140 { 9614 /* trunc.l.d */, Mips::TRUNC_L_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips3_32_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
8141 { 9614 /* trunc.l.d */, Mips::TRUNC_L_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
8142 { 9624 /* trunc.l.s */, Mips::TRUNC_L_S, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, },
8143 { 9624 /* trunc.l.s */, Mips::TRUNC_L_S_MMR6, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, },
8144 { 9634 /* trunc.w.d */, Mips::TRUNC_W_D32, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, },
8145 { 9634 /* trunc.w.d */, Mips::TRUNC_W_MM, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, },
8146 { 9634 /* trunc.w.d */, Mips::TRUNC_W_D64, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg }, },
8147 { 9634 /* trunc.w.d */, Mips::TRUNC_W_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg }, },
8148 { 9634 /* trunc.w.d */, Mips::PseudoTRUNC_W_D32, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1__GPR32AsmReg1_2, AMFBS_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg, MCK_GPR32AsmReg }, },
8149 { 9634 /* trunc.w.d */, Mips::PseudoTRUNC_W_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__GPR32AsmReg1_2, AMFBS_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_GPR32AsmReg }, },
8150 { 9644 /* trunc.w.s */, Mips::TRUNC_W_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_HasMips2_NotR5900_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
8151 { 9644 /* trunc.w.s */, Mips::TRUNC_W_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
8152 { 9644 /* trunc.w.s */, Mips::TRUNC_W_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
8153 { 9644 /* trunc.w.s */, Mips::PseudoTRUNC_W_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_None, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_GPR32AsmReg }, },
8154 { 9654 /* ulh */, Mips::Ulh, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_None, { MCK_GPR32AsmReg, MCK_Mem }, },
8155 { 9658 /* ulhu */, Mips::Ulhu, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_None, { MCK_GPR32AsmReg, MCK_Mem }, },
8156 { 9663 /* ulw */, Mips::Ulw, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_None, { MCK_GPR32AsmReg, MCK_Mem }, },
8157 { 9667 /* ush */, Mips::Ush, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_None, { MCK_GPR32AsmReg, MCK_Mem }, },
8158 { 9671 /* usw */, Mips::Usw, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_None, { MCK_GPR32AsmReg, MCK_Mem }, },
8159 { 9675 /* v3mulu */, Mips::V3MULU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
8160 { 9675 /* v3mulu */, Mips::V3MULU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
8161 { 9682 /* vmm0 */, Mips::VMM0, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
8162 { 9682 /* vmm0 */, Mips::VMM0, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
8163 { 9687 /* vmulu */, Mips::VMULU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
8164 { 9687 /* vmulu */, Mips::VMULU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
8165 { 9693 /* vshf.b */, Mips::VSHF_B, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
8166 { 9700 /* vshf.d */, Mips::VSHF_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
8167 { 9707 /* vshf.h */, Mips::VSHF_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
8168 { 9714 /* vshf.w */, Mips::VSHF_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
8169 { 9721 /* wait */, Mips::WAIT, Convert_NoOperands, AMFBS_HasStdEnc_HasMips3_32_NotInMicroMips, { }, },
8170 { 9721 /* wait */, Mips::WAIT_MM, Convert__imm_95_0, AMFBS_InMicroMips, { }, },
8171 { 9721 /* wait */, Mips::WAIT_MMR6, Convert__ConstantUImm10_01_0, AMFBS_InMicroMips_HasMips32r6, { MCK_ConstantUImm10_0 }, },
8172 { 9721 /* wait */, Mips::WAIT_MM, Convert__ConstantUImm10_01_0, AMFBS_InMicroMips, { MCK_ConstantUImm10_0 }, },
8173 { 9726 /* wrdsp */, Mips::WRDSP, Convert__GPR32AsmReg1_0__imm_95_31, AMFBS_HasDSP_NotInMicroMips, { MCK_GPR32AsmReg }, },
8174 { 9726 /* wrdsp */, Mips::WRDSP_MM, Convert__GPR32AsmReg1_0__imm_95_31, AMFBS_HasDSP_InMicroMips, { MCK_GPR32AsmReg }, },
8175 { 9726 /* wrdsp */, Mips::WRDSP_MM, Convert__GPR32AsmReg1_0__ConstantUImm7_01_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ConstantUImm7_0 }, },
8176 { 9726 /* wrdsp */, Mips::WRDSP, Convert__GPR32AsmReg1_0__ConstantUImm10_01_1, AMFBS_HasDSP_NotInMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm10_0 }, },
8177 { 9732 /* wrpgpr */, Mips::WRPGPR_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
8178 { 9739 /* wsbh */, Mips::WSBH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
8179 { 9739 /* wsbh */, Mips::WSBH_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
8180 { 9739 /* wsbh */, Mips::WSBH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
8181 { 9744 /* xor */, Mips::XorRxRxRy16, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs }, },
8182 { 9744 /* xor */, Mips::XOR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
8183 { 9744 /* xor */, Mips::XOR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
8184 { 9744 /* xor */, Mips::XOR_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
8185 { 9744 /* xor */, Mips::XORI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_UImm16 }, },
8186 { 9744 /* xor */, Mips::XORi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
8187 { 9744 /* xor */, Mips::XORi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
8188 { 9744 /* xor */, Mips::XORi64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, AMFBS_HasStdEnc_IsGP64bit_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_Imm }, },
8189 { 9744 /* xor */, Mips::XOR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
8190 { 9744 /* xor */, Mips::XOR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
8191 { 9744 /* xor */, Mips::XOR_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
8192 { 9744 /* xor */, Mips::XORI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, },
8193 { 9744 /* xor */, Mips::XORi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
8194 { 9744 /* xor */, Mips::XORi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
8195 { 9744 /* xor */, Mips::XORi64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, AMFBS_HasStdEnc_IsGP64bit_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, },
8196 { 9748 /* xor.v */, Mips::XOR_V, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
8197 { 9754 /* xor16 */, Mips::XOR16_MM, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Tie0_1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, },
8198 { 9754 /* xor16 */, Mips::XOR16_MMR6, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Tie0_1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, },
8199 { 9760 /* xori */, Mips::XORI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_UImm16 }, },
8200 { 9760 /* xori */, Mips::XORi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_UImm16 }, },
8201 { 9760 /* xori */, Mips::XORi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_UImm16 }, },
8202 { 9760 /* xori */, Mips::XORI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, },
8203 { 9760 /* xori */, Mips::XORi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, },
8204 { 9760 /* xori */, Mips::XORi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, },
8205 { 9765 /* xori.b */, Mips::XORI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm8_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm8_0 }, },
8206 { 9772 /* yield */, Mips::YIELD, Convert__regZERO__GPR32AsmReg1_0, AMFBS_HasMT_NotInMicroMips, { MCK_GPR32AsmReg }, },
8207 { 9772 /* yield */, Mips::YIELD, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMT_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
8208};
8209
8210#include "llvm/Support/Debug.h"
8211#include "llvm/Support/Format.h"
8212
8213unsigned MipsAsmParser::
8214MatchInstructionImpl(const OperandVector &Operands,
8215 MCInst &Inst,
8216 uint64_t &ErrorInfo,
8217 FeatureBitset &MissingFeatures,
8218 bool matchingInlineAsm, unsigned VariantID) {
8219 // Eliminate obvious mismatches.
8220 if (Operands.size() > 9) {
8221 ErrorInfo = 9;
8222 return Match_InvalidOperand;
8223 }
8224
8225 // Get the current feature set.
8226 const FeatureBitset &AvailableFeatures = getAvailableFeatures();
8227
8228 // Get the instruction mnemonic, which is the first token.
8229 StringRef Mnemonic = ((MipsOperand &)*Operands[0]).getToken();
8230
8231 // Some state to try to produce better error messages.
8232 bool HadMatchOtherThanFeatures = false;
8233 bool HadMatchOtherThanPredicate = false;
8234 unsigned RetCode = Match_InvalidOperand;
8235 MissingFeatures.set();
8236 // Set ErrorInfo to the operand that mismatches if it is
8237 // wrong for all instances of the instruction.
8238 ErrorInfo = ~0ULL;
8239 // Find the appropriate table for this asm variant.
8240 const MatchEntry *Start, *End;
8241 switch (VariantID) {
8242 default: llvm_unreachable("invalid variant!");
8243 case 0: Start = std::begin(MatchTable0); End = std::end(MatchTable0); break;
8244 }
8245 // Search the table.
8246 auto MnemonicRange = std::equal_range(Start, End, Mnemonic, LessOpcode());
8247
8248 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "AsmMatcher: found " <<
8249 std::distance(MnemonicRange.first, MnemonicRange.second) <<
8250 " encodings with mnemonic '" << Mnemonic << "'\n");
8251
8252 // Return a more specific error code if no mnemonics match.
8253 if (MnemonicRange.first == MnemonicRange.second)
8254 return Match_MnemonicFail;
8255
8256 for (const MatchEntry *it = MnemonicRange.first, *ie = MnemonicRange.second;
8257 it != ie; ++it) {
8258 const FeatureBitset &RequiredFeatures = FeatureBitsets[it->RequiredFeaturesIdx];
8259 bool HasRequiredFeatures =
8260 (AvailableFeatures & RequiredFeatures) == RequiredFeatures;
8261 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Trying to match opcode "
8262 << MII.getName(it->Opcode) << "\n");
8263 // equal_range guarantees that instruction mnemonic matches.
8264 assert(Mnemonic == it->getMnemonic());
8265 bool OperandsValid = true;
8266 unsigned ActualIdx = 1;
8267 for (unsigned FormalIdx = 0; FormalIdx != 8; ++FormalIdx) {
8268 auto Formal = static_cast<MatchClassKind>(it->Classes[FormalIdx]);
8269 DEBUG_WITH_TYPE("asm-matcher",
8270 dbgs() << " Matching formal operand class " << getMatchClassName(Formal)
8271 << " against actual operand at index " << ActualIdx);
8272 if (ActualIdx < Operands.size())
8273 DEBUG_WITH_TYPE("asm-matcher", dbgs() << " (";
8274 Operands[ActualIdx]->print(dbgs(), getContext().getAsmInfo()); dbgs() << "): ");
8275 else
8276 DEBUG_WITH_TYPE("asm-matcher", dbgs() << ": ");
8277 if (ActualIdx >= Operands.size()) {
8278 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "actual operand index out of range\n");
8279 if (Formal == InvalidMatchClass) {
8280 break;
8281 }
8282 if (isSubclass(Formal, OptionalMatchClass)) {
8283 continue;
8284 }
8285 OperandsValid = false;
8286 ErrorInfo = ActualIdx;
8287 break;
8288 }
8289 MCParsedAsmOperand &Actual = *Operands[ActualIdx];
8290 unsigned Diag = validateOperandClass(Actual, Formal, *STI);
8291 if (Diag == Match_Success) {
8292 DEBUG_WITH_TYPE("asm-matcher",
8293 dbgs() << "match success using generic matcher\n");
8294 ++ActualIdx;
8295 continue;
8296 }
8297 // If the generic handler indicates an invalid operand
8298 // failure, check for a special case.
8299 if (Diag != Match_Success) {
8300 unsigned TargetDiag = validateTargetOperandClass(Actual, Formal);
8301 if (TargetDiag == Match_Success) {
8302 DEBUG_WITH_TYPE("asm-matcher",
8303 dbgs() << "match success using target matcher\n");
8304 ++ActualIdx;
8305 continue;
8306 }
8307 // If the target matcher returned a specific error code use
8308 // that, else use the one from the generic matcher.
8309 if (TargetDiag != Match_InvalidOperand && HasRequiredFeatures)
8310 Diag = TargetDiag;
8311 }
8312 // If current formal operand wasn't matched and it is optional
8313 // then try to match next formal operand
8314 if (Diag == Match_InvalidOperand && isSubclass(Formal, OptionalMatchClass)) {
8315 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "ignoring optional operand\n");
8316 continue;
8317 }
8318 // If this operand is broken for all of the instances of this
8319 // mnemonic, keep track of it so we can report loc info.
8320 // If we already had a match that only failed due to a
8321 // target predicate, that diagnostic is preferred.
8322 if (!HadMatchOtherThanPredicate &&
8323 (it == MnemonicRange.first || ErrorInfo <= ActualIdx)) {
8324 if (HasRequiredFeatures && (ErrorInfo != ActualIdx || Diag != Match_InvalidOperand))
8325 RetCode = Diag;
8326 ErrorInfo = ActualIdx;
8327 }
8328 // Otherwise, just reject this instance of the mnemonic.
8329 OperandsValid = false;
8330 break;
8331 }
8332
8333 if (!OperandsValid) {
8334 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Opcode result: multiple "
8335 "operand mismatches, ignoring "
8336 "this opcode\n");
8337 continue;
8338 }
8339 if (!HasRequiredFeatures) {
8340 HadMatchOtherThanFeatures = true;
8341 FeatureBitset NewMissingFeatures = RequiredFeatures & ~AvailableFeatures;
8342 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Missing target features:";
8343 for (unsigned I = 0, E = NewMissingFeatures.size(); I != E; ++I)
8344 if (NewMissingFeatures[I])
8345 dbgs() << ' ' << I;
8346 dbgs() << "\n");
8347 if (NewMissingFeatures.count() <=
8348 MissingFeatures.count())
8349 MissingFeatures = NewMissingFeatures;
8350 continue;
8351 }
8352
8353 Inst.clear();
8354
8355 Inst.setOpcode(it->Opcode);
8356 // We have a potential match but have not rendered the operands.
8357 // Check the target predicate to handle any context sensitive
8358 // constraints.
8359 // For example, Ties that are referenced multiple times must be
8360 // checked here to ensure the input is the same for each match
8361 // constraints. If we leave it any later the ties will have been
8362 // canonicalized
8363 unsigned MatchResult;
8364 if ((MatchResult = checkEarlyTargetMatchPredicate(Inst, Operands)) != Match_Success) {
8365 Inst.clear();
8366 DEBUG_WITH_TYPE(
8367 "asm-matcher",
8368 dbgs() << "Early target match predicate failed with diag code "
8369 << MatchResult << "\n");
8370 RetCode = MatchResult;
8371 HadMatchOtherThanPredicate = true;
8372 continue;
8373 }
8374
8375 if (matchingInlineAsm) {
8376 convertToMapAndConstraints(it->ConvertFn, Operands);
8377 if (!checkAsmTiedOperandConstraints(*this, it->ConvertFn, Operands,
8378 ErrorInfo))
8379 return Match_InvalidTiedOperand;
8380
8381 return Match_Success;
8382 }
8383
8384 // We have selected a definite instruction, convert the parsed
8385 // operands into the appropriate MCInst.
8386 convertToMCInst(it->ConvertFn, Inst, it->Opcode, Operands);
8387
8388 // We have a potential match. Check the target predicate to
8389 // handle any context sensitive constraints.
8390 if ((MatchResult = checkTargetMatchPredicate(Inst)) != Match_Success) {
8391 DEBUG_WITH_TYPE("asm-matcher",
8392 dbgs() << "Target match predicate failed with diag code "
8393 << MatchResult << "\n");
8394 Inst.clear();
8395 RetCode = MatchResult;
8396 HadMatchOtherThanPredicate = true;
8397 continue;
8398 }
8399
8400 if (!checkAsmTiedOperandConstraints(*this, it->ConvertFn, Operands,
8401 ErrorInfo))
8402 return Match_InvalidTiedOperand;
8403
8404 DEBUG_WITH_TYPE(
8405 "asm-matcher",
8406 dbgs() << "Opcode result: complete match, selecting this opcode\n");
8407 return Match_Success;
8408 }
8409
8410 // Okay, we had no match. Try to return a useful error code.
8411 if (HadMatchOtherThanPredicate || !HadMatchOtherThanFeatures)
8412 return RetCode;
8413
8414 ErrorInfo = 0;
8415 return Match_MissingFeature;
8416}
8417
8418namespace {
8419 struct OperandMatchEntry {
8420 uint16_t Mnemonic;
8421 uint8_t OperandMask;
8422 uint8_t Class;
8423 uint8_t RequiredFeaturesIdx;
8424
8425 StringRef getMnemonic() const {
8426 return StringRef(MnemonicTable + Mnemonic + 1,
8427 MnemonicTable[Mnemonic]);
8428 }
8429 };
8430
8431 // Predicate for searching for an opcode.
8432 struct LessOpcodeOperand {
8433 bool operator()(const OperandMatchEntry &LHS, StringRef RHS) {
8434 return LHS.getMnemonic() < RHS;
8435 }
8436 bool operator()(StringRef LHS, const OperandMatchEntry &RHS) {
8437 return LHS < RHS.getMnemonic();
8438 }
8439 bool operator()(const OperandMatchEntry &LHS, const OperandMatchEntry &RHS) {
8440 return LHS.getMnemonic() < RHS.getMnemonic();
8441 }
8442 };
8443} // end anonymous namespace
8444
8445static const OperandMatchEntry OperandMatchTable[3292] = {
8446 /* Operand List Mnemonic, Mask, Operand Class, Features */
8447 { 0 /* abs */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_None },
8448 { 4 /* abs.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips },
8449 { 4 /* abs.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat },
8450 { 4 /* abs.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips },
8451 { 4 /* abs.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat },
8452 { 10 /* abs.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips },
8453 { 10 /* abs.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat },
8454 { 16 /* absq_s.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
8455 { 16 /* absq_s.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
8456 { 26 /* absq_s.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
8457 { 26 /* absq_s.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
8458 { 36 /* absq_s.w */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
8459 { 36 /* absq_s.w */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
8460 { 45 /* add */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
8461 { 45 /* add */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
8462 { 45 /* add */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8463 { 45 /* add */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips },
8464 { 45 /* add */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
8465 { 45 /* add */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
8466 { 45 /* add */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
8467 { 45 /* add */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8468 { 45 /* add */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips },
8469 { 45 /* add */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
8470 { 49 /* add.d */, 7 /* 0, 1, 2 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips },
8471 { 49 /* add.d */, 7 /* 0, 1, 2 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat },
8472 { 49 /* add.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips },
8473 { 49 /* add.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat },
8474 { 55 /* add.ps */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
8475 { 62 /* add.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips },
8476 { 62 /* add.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
8477 { 62 /* add.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat },
8478 { 68 /* add_a.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8479 { 76 /* add_a.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8480 { 84 /* add_a.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8481 { 92 /* add_a.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8482 { 100 /* addi */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
8483 { 100 /* addi */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips },
8484 { 100 /* addi */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
8485 { 100 /* addi */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips },
8486 { 105 /* addiu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8487 { 105 /* addiu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
8488 { 105 /* addiu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
8489 { 105 /* addiu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8490 { 105 /* addiu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
8491 { 105 /* addiu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
8492 { 111 /* addiupc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6 },
8493 { 111 /* addiupc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8494 { 111 /* addiupc */, 1 /* 0 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_NotMips32r6 },
8495 { 119 /* addiur1sp */, 1 /* 0 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips },
8496 { 129 /* addiur2 */, 3 /* 0, 1 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips },
8497 { 137 /* addius5 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
8498 { 153 /* addq.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
8499 { 153 /* addq.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
8500 { 161 /* addq_s.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
8501 { 161 /* addq_s.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
8502 { 171 /* addq_s.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
8503 { 171 /* addq_s.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
8504 { 180 /* addqh.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
8505 { 180 /* addqh.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
8506 { 189 /* addqh.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
8507 { 189 /* addqh.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
8508 { 197 /* addqh_r.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
8509 { 197 /* addqh_r.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
8510 { 208 /* addqh_r.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
8511 { 208 /* addqh_r.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
8512 { 218 /* addr.ps */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMips3D },
8513 { 226 /* adds_a.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8514 { 235 /* adds_a.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8515 { 244 /* adds_a.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8516 { 253 /* adds_a.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8517 { 262 /* adds_s.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8518 { 271 /* adds_s.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8519 { 280 /* adds_s.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8520 { 289 /* adds_s.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8521 { 298 /* adds_u.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8522 { 307 /* adds_u.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8523 { 316 /* adds_u.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8524 { 325 /* adds_u.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8525 { 334 /* addsc */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
8526 { 334 /* addsc */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
8527 { 340 /* addu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8528 { 340 /* addu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
8529 { 340 /* addu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
8530 { 340 /* addu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
8531 { 340 /* addu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
8532 { 340 /* addu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8533 { 340 /* addu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
8534 { 340 /* addu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
8535 { 340 /* addu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
8536 { 340 /* addu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
8537 { 345 /* addu.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
8538 { 345 /* addu.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
8539 { 353 /* addu.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
8540 { 353 /* addu.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
8541 { 361 /* addu16 */, 7 /* 0, 1, 2 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_NotMips32r6 },
8542 { 361 /* addu16 */, 7 /* 0, 1, 2 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8543 { 368 /* addu_s.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
8544 { 368 /* addu_s.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
8545 { 378 /* addu_s.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
8546 { 378 /* addu_s.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
8547 { 388 /* adduh.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
8548 { 388 /* adduh.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
8549 { 397 /* adduh_r.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
8550 { 397 /* adduh_r.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
8551 { 408 /* addv.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8552 { 415 /* addv.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8553 { 422 /* addv.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8554 { 429 /* addv.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8555 { 436 /* addvi.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8556 { 444 /* addvi.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8557 { 452 /* addvi.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8558 { 460 /* addvi.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8559 { 468 /* addwc */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
8560 { 468 /* addwc */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
8561 { 474 /* align */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6 },
8562 { 474 /* align */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8563 { 480 /* aluipc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6 },
8564 { 480 /* aluipc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8565 { 487 /* and */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
8566 { 487 /* and */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
8567 { 487 /* and */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8568 { 487 /* and */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8569 { 487 /* and */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips },
8570 { 487 /* and */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
8571 { 487 /* and */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips3_NotInMicroMips },
8572 { 487 /* and */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
8573 { 487 /* and */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
8574 { 487 /* and */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8575 { 487 /* and */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8576 { 487 /* and */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips },
8577 { 487 /* and */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
8578 { 487 /* and */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips3_NotInMicroMips },
8579 { 491 /* and.v */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8580 { 497 /* and16 */, 3 /* 0, 1 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_NotMips32r6 },
8581 { 497 /* and16 */, 3 /* 0, 1 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8582 { 503 /* andi */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8583 { 503 /* andi */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
8584 { 503 /* andi */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
8585 { 503 /* andi */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8586 { 503 /* andi */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
8587 { 503 /* andi */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
8588 { 508 /* andi.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8589 { 515 /* andi16 */, 3 /* 0, 1 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_NotMips32r6 },
8590 { 515 /* andi16 */, 3 /* 0, 1 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8591 { 522 /* append */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
8592 { 522 /* append */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
8593 { 529 /* asub_s.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8594 { 538 /* asub_s.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8595 { 547 /* asub_s.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8596 { 556 /* asub_s.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8597 { 565 /* asub_u.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8598 { 574 /* asub_u.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8599 { 583 /* asub_u.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8600 { 592 /* asub_u.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8601 { 601 /* aui */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6 },
8602 { 601 /* aui */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8603 { 605 /* auipc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6 },
8604 { 605 /* auipc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8605 { 611 /* ave_s.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8606 { 619 /* ave_s.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8607 { 627 /* ave_s.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8608 { 635 /* ave_s.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8609 { 643 /* ave_u.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8610 { 651 /* ave_u.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8611 { 659 /* ave_u.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8612 { 667 /* ave_u.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8613 { 675 /* aver_s.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8614 { 684 /* aver_s.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8615 { 693 /* aver_s.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8616 { 702 /* aver_s.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8617 { 711 /* aver_u.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8618 { 720 /* aver_u.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8619 { 729 /* aver_u.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8620 { 738 /* aver_u.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8621 { 747 /* b */, 1 /* 0 */, MCK_JumpTarget, AMFBS_HasStdEnc_NotInMicroMips },
8622 { 747 /* b */, 1 /* 0 */, MCK_JumpTarget, AMFBS_InMicroMips },
8623 { 747 /* b */, 1 /* 0 */, MCK_JumpTarget, AMFBS_InMips16Mode },
8624 { 747 /* b */, 1 /* 0 */, MCK_JumpTarget, AMFBS_None },
8625 { 747 /* b */, 1 /* 0 */, MCK_JumpTarget, AMFBS_InMips16Mode },
8626 { 749 /* b16 */, 1 /* 0 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 },
8627 { 749 /* b16 */, 1 /* 0 */, MCK_JumpTarget, AMFBS_InMicroMips },
8628 { 753 /* baddu */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasCnMips },
8629 { 753 /* baddu */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasCnMips },
8630 { 759 /* bal */, 1 /* 0 */, MCK_JumpTarget, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips },
8631 { 759 /* bal */, 1 /* 0 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6 },
8632 { 759 /* bal */, 1 /* 0 */, MCK_JumpTarget, AMFBS_InMicroMips_NotMips32r6 },
8633 { 763 /* balc */, 1 /* 0 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6 },
8634 { 763 /* balc */, 1 /* 0 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 },
8635 { 768 /* balign */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
8636 { 768 /* balign */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
8637 { 775 /* bbit0 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasCnMips },
8638 { 775 /* bbit0 */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasCnMips },
8639 { 775 /* bbit0 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasCnMips },
8640 { 775 /* bbit0 */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasCnMips },
8641 { 781 /* bbit032 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasCnMips },
8642 { 781 /* bbit032 */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasCnMips },
8643 { 789 /* bbit1 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasCnMips },
8644 { 789 /* bbit1 */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasCnMips },
8645 { 789 /* bbit1 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasCnMips },
8646 { 789 /* bbit1 */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasCnMips },
8647 { 795 /* bbit132 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasCnMips },
8648 { 795 /* bbit132 */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasCnMips },
8649 { 803 /* bc */, 1 /* 0 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8650 { 803 /* bc */, 1 /* 0 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 },
8651 { 806 /* bc16 */, 1 /* 0 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 },
8652 { 811 /* bc1eqz */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
8653 { 811 /* bc1eqz */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
8654 { 818 /* bc1eqzc */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
8655 { 818 /* bc1eqzc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
8656 { 826 /* bc1f */, 1 /* 0 */, MCK_JumpTarget, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
8657 { 826 /* bc1f */, 1 /* 0 */, MCK_JumpTarget, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
8658 { 826 /* bc1f */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
8659 { 826 /* bc1f */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
8660 { 826 /* bc1f */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
8661 { 826 /* bc1f */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
8662 { 831 /* bc1fl */, 1 /* 0 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
8663 { 831 /* bc1fl */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
8664 { 831 /* bc1fl */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
8665 { 837 /* bc1nez */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
8666 { 837 /* bc1nez */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
8667 { 844 /* bc1nezc */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
8668 { 844 /* bc1nezc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
8669 { 852 /* bc1t */, 1 /* 0 */, MCK_JumpTarget, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
8670 { 852 /* bc1t */, 1 /* 0 */, MCK_JumpTarget, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
8671 { 852 /* bc1t */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
8672 { 852 /* bc1t */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
8673 { 852 /* bc1t */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
8674 { 852 /* bc1t */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
8675 { 857 /* bc1tl */, 1 /* 0 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
8676 { 857 /* bc1tl */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
8677 { 857 /* bc1tl */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
8678 { 863 /* bc2eqz */, 1 /* 0 */, MCK_COP2AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8679 { 863 /* bc2eqz */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8680 { 870 /* bc2eqzc */, 1 /* 0 */, MCK_COP2AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8681 { 870 /* bc2eqzc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 },
8682 { 878 /* bc2nez */, 1 /* 0 */, MCK_COP2AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8683 { 878 /* bc2nez */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8684 { 885 /* bc2nezc */, 1 /* 0 */, MCK_COP2AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8685 { 885 /* bc2nezc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 },
8686 { 893 /* bclr.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8687 { 900 /* bclr.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8688 { 907 /* bclr.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8689 { 914 /* bclr.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8690 { 921 /* bclri.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8691 { 929 /* bclri.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8692 { 937 /* bclri.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8693 { 945 /* bclri.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8694 { 953 /* beq */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None },
8695 { 953 /* beq */, 4 /* 2 */, MCK_JumpTarget, AMFBS_None },
8696 { 953 /* beq */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
8697 { 953 /* beq */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_NotInMicroMips },
8698 { 953 /* beq */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
8699 { 953 /* beq */, 4 /* 2 */, MCK_JumpTarget, AMFBS_InMicroMips_NotMips32r6 },
8700 { 957 /* beqc */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8701 { 957 /* beqc */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8702 { 957 /* beqc */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8703 { 957 /* beqc */, 4 /* 2 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 },
8704 { 957 /* beqc */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 },
8705 { 957 /* beqc */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 },
8706 { 962 /* beql */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 },
8707 { 962 /* beql */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 },
8708 { 962 /* beql */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips },
8709 { 962 /* beql */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips },
8710 { 967 /* beqz */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMips16Mode },
8711 { 967 /* beqz */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
8712 { 967 /* beqz */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_NotInMicroMips },
8713 { 967 /* beqz */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
8714 { 967 /* beqz */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips },
8715 { 967 /* beqz */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMips16Mode },
8716 { 972 /* beqz16 */, 1 /* 0 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_NotMips32r6 },
8717 { 972 /* beqz16 */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_NotMips32r6 },
8718 { 972 /* beqz16 */, 1 /* 0 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8719 { 972 /* beqz16 */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 },
8720 { 979 /* beqzalc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8721 { 979 /* beqzalc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8722 { 979 /* beqzalc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8723 { 979 /* beqzalc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 },
8724 { 987 /* beqzc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8725 { 987 /* beqzc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8726 { 987 /* beqzc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
8727 { 987 /* beqzc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_NotMips32r6 },
8728 { 987 /* beqzc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8729 { 987 /* beqzc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 },
8730 { 987 /* beqzc */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 },
8731 { 987 /* beqzc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 },
8732 { 993 /* beqzc16 */, 1 /* 0 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8733 { 993 /* beqzc16 */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 },
8734 { 1001 /* beqzl */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotInMicroMips },
8735 { 1001 /* beqzl */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotInMicroMips },
8736 { 1007 /* bge */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None },
8737 { 1007 /* bge */, 4 /* 2 */, MCK_JumpTarget, AMFBS_None },
8738 { 1007 /* bge */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_None },
8739 { 1007 /* bge */, 4 /* 2 */, MCK_JumpTarget, AMFBS_None },
8740 { 1011 /* bgec */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8741 { 1011 /* bgec */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8742 { 1011 /* bgec */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8743 { 1011 /* bgec */, 4 /* 2 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 },
8744 { 1011 /* bgec */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 },
8745 { 1011 /* bgec */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 },
8746 { 1016 /* bgel */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 },
8747 { 1016 /* bgel */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 },
8748 { 1016 /* bgel */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 },
8749 { 1016 /* bgel */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 },
8750 { 1021 /* bgeu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None },
8751 { 1021 /* bgeu */, 4 /* 2 */, MCK_JumpTarget, AMFBS_None },
8752 { 1021 /* bgeu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_None },
8753 { 1021 /* bgeu */, 4 /* 2 */, MCK_JumpTarget, AMFBS_None },
8754 { 1026 /* bgeuc */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8755 { 1026 /* bgeuc */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8756 { 1026 /* bgeuc */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8757 { 1026 /* bgeuc */, 4 /* 2 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 },
8758 { 1026 /* bgeuc */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 },
8759 { 1026 /* bgeuc */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 },
8760 { 1032 /* bgeul */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 },
8761 { 1032 /* bgeul */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 },
8762 { 1032 /* bgeul */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 },
8763 { 1032 /* bgeul */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 },
8764 { 1038 /* bgez */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
8765 { 1038 /* bgez */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_NotInMicroMips },
8766 { 1038 /* bgez */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
8767 { 1038 /* bgez */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_NotMips32r6 },
8768 { 1043 /* bgezal */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips },
8769 { 1043 /* bgezal */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips },
8770 { 1043 /* bgezal */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
8771 { 1043 /* bgezal */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_NotMips32r6 },
8772 { 1050 /* bgezalc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8773 { 1050 /* bgezalc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8774 { 1050 /* bgezalc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8775 { 1050 /* bgezalc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 },
8776 { 1058 /* bgezall */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips },
8777 { 1058 /* bgezall */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips },
8778 { 1066 /* bgezals */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
8779 { 1066 /* bgezals */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_NotMips32r6 },
8780 { 1074 /* bgezc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8781 { 1074 /* bgezc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8782 { 1074 /* bgezc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8783 { 1074 /* bgezc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 },
8784 { 1074 /* bgezc */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 },
8785 { 1074 /* bgezc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 },
8786 { 1080 /* bgezl */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips },
8787 { 1080 /* bgezl */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips },
8788 { 1086 /* bgt */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None },
8789 { 1086 /* bgt */, 4 /* 2 */, MCK_JumpTarget, AMFBS_None },
8790 { 1086 /* bgt */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_None },
8791 { 1086 /* bgt */, 4 /* 2 */, MCK_JumpTarget, AMFBS_None },
8792 { 1090 /* bgtl */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 },
8793 { 1090 /* bgtl */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 },
8794 { 1090 /* bgtl */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 },
8795 { 1090 /* bgtl */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 },
8796 { 1095 /* bgtu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None },
8797 { 1095 /* bgtu */, 4 /* 2 */, MCK_JumpTarget, AMFBS_None },
8798 { 1095 /* bgtu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_None },
8799 { 1095 /* bgtu */, 4 /* 2 */, MCK_JumpTarget, AMFBS_None },
8800 { 1100 /* bgtul */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 },
8801 { 1100 /* bgtul */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 },
8802 { 1100 /* bgtul */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 },
8803 { 1100 /* bgtul */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 },
8804 { 1106 /* bgtz */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
8805 { 1106 /* bgtz */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_NotInMicroMips },
8806 { 1106 /* bgtz */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
8807 { 1106 /* bgtz */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_NotMips32r6 },
8808 { 1111 /* bgtzalc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8809 { 1111 /* bgtzalc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8810 { 1111 /* bgtzalc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8811 { 1111 /* bgtzalc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 },
8812 { 1119 /* bgtzc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8813 { 1119 /* bgtzc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8814 { 1119 /* bgtzc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8815 { 1119 /* bgtzc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 },
8816 { 1119 /* bgtzc */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 },
8817 { 1119 /* bgtzc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 },
8818 { 1125 /* bgtzl */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips },
8819 { 1125 /* bgtzl */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips },
8820 { 1131 /* binsl.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8821 { 1139 /* binsl.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8822 { 1147 /* binsl.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8823 { 1155 /* binsl.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8824 { 1163 /* binsli.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8825 { 1172 /* binsli.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8826 { 1181 /* binsli.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8827 { 1190 /* binsli.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8828 { 1199 /* binsr.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8829 { 1207 /* binsr.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8830 { 1215 /* binsr.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8831 { 1223 /* binsr.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8832 { 1231 /* binsri.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8833 { 1240 /* binsri.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8834 { 1249 /* binsri.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8835 { 1258 /* binsri.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8836 { 1267 /* bitrev */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
8837 { 1267 /* bitrev */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
8838 { 1274 /* bitswap */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6 },
8839 { 1274 /* bitswap */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8840 { 1282 /* ble */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None },
8841 { 1282 /* ble */, 4 /* 2 */, MCK_JumpTarget, AMFBS_None },
8842 { 1282 /* ble */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_None },
8843 { 1282 /* ble */, 4 /* 2 */, MCK_JumpTarget, AMFBS_None },
8844 { 1286 /* blel */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 },
8845 { 1286 /* blel */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 },
8846 { 1286 /* blel */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 },
8847 { 1286 /* blel */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 },
8848 { 1291 /* bleu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None },
8849 { 1291 /* bleu */, 4 /* 2 */, MCK_JumpTarget, AMFBS_None },
8850 { 1291 /* bleu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_None },
8851 { 1291 /* bleu */, 4 /* 2 */, MCK_JumpTarget, AMFBS_None },
8852 { 1296 /* bleul */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 },
8853 { 1296 /* bleul */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 },
8854 { 1296 /* bleul */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 },
8855 { 1296 /* bleul */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 },
8856 { 1302 /* blez */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
8857 { 1302 /* blez */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_NotInMicroMips },
8858 { 1302 /* blez */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
8859 { 1302 /* blez */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_NotMips32r6 },
8860 { 1307 /* blezalc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8861 { 1307 /* blezalc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8862 { 1307 /* blezalc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8863 { 1307 /* blezalc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 },
8864 { 1315 /* blezc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8865 { 1315 /* blezc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8866 { 1315 /* blezc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8867 { 1315 /* blezc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 },
8868 { 1315 /* blezc */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 },
8869 { 1315 /* blezc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 },
8870 { 1321 /* blezl */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips },
8871 { 1321 /* blezl */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips },
8872 { 1327 /* blt */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None },
8873 { 1327 /* blt */, 4 /* 2 */, MCK_JumpTarget, AMFBS_None },
8874 { 1327 /* blt */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_None },
8875 { 1327 /* blt */, 4 /* 2 */, MCK_JumpTarget, AMFBS_None },
8876 { 1331 /* bltc */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8877 { 1331 /* bltc */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8878 { 1331 /* bltc */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8879 { 1331 /* bltc */, 4 /* 2 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 },
8880 { 1331 /* bltc */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 },
8881 { 1331 /* bltc */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 },
8882 { 1336 /* bltl */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 },
8883 { 1336 /* bltl */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 },
8884 { 1336 /* bltl */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 },
8885 { 1336 /* bltl */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 },
8886 { 1341 /* bltu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None },
8887 { 1341 /* bltu */, 4 /* 2 */, MCK_JumpTarget, AMFBS_None },
8888 { 1341 /* bltu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_None },
8889 { 1341 /* bltu */, 4 /* 2 */, MCK_JumpTarget, AMFBS_None },
8890 { 1346 /* bltuc */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8891 { 1346 /* bltuc */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8892 { 1346 /* bltuc */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8893 { 1346 /* bltuc */, 4 /* 2 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 },
8894 { 1346 /* bltuc */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 },
8895 { 1346 /* bltuc */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 },
8896 { 1352 /* bltul */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 },
8897 { 1352 /* bltul */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 },
8898 { 1352 /* bltul */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 },
8899 { 1352 /* bltul */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 },
8900 { 1358 /* bltz */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
8901 { 1358 /* bltz */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_NotInMicroMips },
8902 { 1358 /* bltz */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
8903 { 1358 /* bltz */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_NotMips32r6 },
8904 { 1363 /* bltzal */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips },
8905 { 1363 /* bltzal */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips },
8906 { 1363 /* bltzal */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
8907 { 1363 /* bltzal */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_NotMips32r6 },
8908 { 1370 /* bltzalc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8909 { 1370 /* bltzalc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8910 { 1370 /* bltzalc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8911 { 1370 /* bltzalc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 },
8912 { 1378 /* bltzall */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips },
8913 { 1378 /* bltzall */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips },
8914 { 1386 /* bltzals */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
8915 { 1386 /* bltzals */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_NotMips32r6 },
8916 { 1394 /* bltzc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8917 { 1394 /* bltzc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8918 { 1394 /* bltzc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8919 { 1394 /* bltzc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 },
8920 { 1394 /* bltzc */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 },
8921 { 1394 /* bltzc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 },
8922 { 1400 /* bltzl */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips },
8923 { 1400 /* bltzl */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips },
8924 { 1406 /* bmnz.v */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8925 { 1413 /* bmnzi.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8926 { 1421 /* bmz.v */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8927 { 1427 /* bmzi.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8928 { 1434 /* bne */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None },
8929 { 1434 /* bne */, 4 /* 2 */, MCK_JumpTarget, AMFBS_None },
8930 { 1434 /* bne */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
8931 { 1434 /* bne */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_NotInMicroMips },
8932 { 1434 /* bne */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
8933 { 1434 /* bne */, 4 /* 2 */, MCK_JumpTarget, AMFBS_InMicroMips_NotMips32r6 },
8934 { 1438 /* bnec */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8935 { 1438 /* bnec */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8936 { 1438 /* bnec */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8937 { 1438 /* bnec */, 4 /* 2 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 },
8938 { 1438 /* bnec */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 },
8939 { 1438 /* bnec */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 },
8940 { 1443 /* bneg.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8941 { 1450 /* bneg.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8942 { 1457 /* bneg.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8943 { 1464 /* bneg.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8944 { 1471 /* bnegi.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8945 { 1479 /* bnegi.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8946 { 1487 /* bnegi.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8947 { 1495 /* bnegi.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8948 { 1503 /* bnel */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 },
8949 { 1503 /* bnel */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 },
8950 { 1503 /* bnel */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips },
8951 { 1503 /* bnel */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips },
8952 { 1508 /* bnez */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMips16Mode },
8953 { 1508 /* bnez */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
8954 { 1508 /* bnez */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_NotInMicroMips },
8955 { 1508 /* bnez */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
8956 { 1508 /* bnez */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips },
8957 { 1508 /* bnez */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMips16Mode },
8958 { 1513 /* bnez16 */, 1 /* 0 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_NotMips32r6 },
8959 { 1513 /* bnez16 */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_NotMips32r6 },
8960 { 1513 /* bnez16 */, 1 /* 0 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8961 { 1513 /* bnez16 */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 },
8962 { 1520 /* bnezalc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8963 { 1520 /* bnezalc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8964 { 1520 /* bnezalc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8965 { 1520 /* bnezalc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 },
8966 { 1528 /* bnezc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8967 { 1528 /* bnezc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8968 { 1528 /* bnezc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
8969 { 1528 /* bnezc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_NotMips32r6 },
8970 { 1528 /* bnezc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8971 { 1528 /* bnezc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 },
8972 { 1528 /* bnezc */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 },
8973 { 1528 /* bnezc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 },
8974 { 1534 /* bnezc16 */, 1 /* 0 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8975 { 1534 /* bnezc16 */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 },
8976 { 1542 /* bnezl */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotInMicroMips },
8977 { 1542 /* bnezl */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotInMicroMips },
8978 { 1548 /* bnvc */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8979 { 1548 /* bnvc */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8980 { 1548 /* bnvc */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8981 { 1548 /* bnvc */, 4 /* 2 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 },
8982 { 1553 /* bnz.b */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8983 { 1553 /* bnz.b */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMSA },
8984 { 1559 /* bnz.d */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8985 { 1559 /* bnz.d */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMSA },
8986 { 1565 /* bnz.h */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8987 { 1565 /* bnz.h */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMSA },
8988 { 1571 /* bnz.v */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8989 { 1571 /* bnz.v */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMSA },
8990 { 1577 /* bnz.w */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8991 { 1577 /* bnz.w */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMSA },
8992 { 1583 /* bovc */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8993 { 1583 /* bovc */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8994 { 1583 /* bovc */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8995 { 1583 /* bovc */, 4 /* 2 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 },
8996 { 1588 /* bposge32 */, 1 /* 0 */, MCK_JumpTarget, AMFBS_InMicroMips_NotMips32r6_HasDSP },
8997 { 1588 /* bposge32 */, 1 /* 0 */, MCK_JumpTarget, AMFBS_HasDSP_NotInMicroMips },
8998 { 1597 /* bposge32c */, 1 /* 0 */, MCK_JumpTarget, AMFBS_InMicroMips_HasDSPR3 },
8999 { 1621 /* bsel.v */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9000 { 1628 /* bseli.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9001 { 1636 /* bset.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9002 { 1643 /* bset.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9003 { 1650 /* bset.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9004 { 1657 /* bset.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9005 { 1664 /* bseti.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9006 { 1672 /* bseti.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9007 { 1680 /* bseti.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9008 { 1688 /* bseti.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9009 { 1708 /* bz.b */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9010 { 1708 /* bz.b */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMSA },
9011 { 1713 /* bz.d */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9012 { 1713 /* bz.d */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMSA },
9013 { 1718 /* bz.h */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9014 { 1718 /* bz.h */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMSA },
9015 { 1723 /* bz.v */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9016 { 1723 /* bz.v */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMSA },
9017 { 1728 /* bz.w */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9018 { 1728 /* bz.w */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMSA },
9019 { 1733 /* c.eq.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9020 { 1733 /* c.eq.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9021 { 1733 /* c.eq.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9022 { 1733 /* c.eq.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9023 { 1733 /* c.eq.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9024 { 1733 /* c.eq.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9025 { 1733 /* c.eq.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9026 { 1733 /* c.eq.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9027 { 1733 /* c.eq.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9028 { 1733 /* c.eq.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9029 { 1733 /* c.eq.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9030 { 1733 /* c.eq.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9031 { 1740 /* c.eq.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9032 { 1740 /* c.eq.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9033 { 1740 /* c.eq.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9034 { 1740 /* c.eq.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9035 { 1740 /* c.eq.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9036 { 1740 /* c.eq.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9037 { 1747 /* c.f.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9038 { 1747 /* c.f.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9039 { 1747 /* c.f.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9040 { 1747 /* c.f.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9041 { 1747 /* c.f.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9042 { 1747 /* c.f.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9043 { 1747 /* c.f.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9044 { 1747 /* c.f.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9045 { 1747 /* c.f.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9046 { 1747 /* c.f.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9047 { 1747 /* c.f.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9048 { 1747 /* c.f.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9049 { 1753 /* c.f.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9050 { 1753 /* c.f.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9051 { 1753 /* c.f.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9052 { 1753 /* c.f.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9053 { 1753 /* c.f.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9054 { 1753 /* c.f.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9055 { 1759 /* c.le.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9056 { 1759 /* c.le.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9057 { 1759 /* c.le.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9058 { 1759 /* c.le.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9059 { 1759 /* c.le.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9060 { 1759 /* c.le.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9061 { 1759 /* c.le.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9062 { 1759 /* c.le.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9063 { 1759 /* c.le.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9064 { 1759 /* c.le.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9065 { 1759 /* c.le.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9066 { 1759 /* c.le.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9067 { 1766 /* c.le.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips },
9068 { 1766 /* c.le.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9069 { 1766 /* c.le.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips },
9070 { 1766 /* c.le.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips },
9071 { 1766 /* c.le.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9072 { 1766 /* c.le.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9073 { 1773 /* c.lt.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9074 { 1773 /* c.lt.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9075 { 1773 /* c.lt.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9076 { 1773 /* c.lt.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9077 { 1773 /* c.lt.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9078 { 1773 /* c.lt.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9079 { 1773 /* c.lt.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9080 { 1773 /* c.lt.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9081 { 1773 /* c.lt.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9082 { 1773 /* c.lt.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9083 { 1773 /* c.lt.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9084 { 1773 /* c.lt.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9085 { 1780 /* c.lt.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips },
9086 { 1780 /* c.lt.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9087 { 1780 /* c.lt.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips },
9088 { 1780 /* c.lt.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips },
9089 { 1780 /* c.lt.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9090 { 1780 /* c.lt.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9091 { 1787 /* c.nge.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9092 { 1787 /* c.nge.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9093 { 1787 /* c.nge.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9094 { 1787 /* c.nge.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9095 { 1787 /* c.nge.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9096 { 1787 /* c.nge.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9097 { 1787 /* c.nge.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9098 { 1787 /* c.nge.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9099 { 1787 /* c.nge.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9100 { 1787 /* c.nge.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9101 { 1787 /* c.nge.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9102 { 1787 /* c.nge.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9103 { 1795 /* c.nge.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips },
9104 { 1795 /* c.nge.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9105 { 1795 /* c.nge.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips },
9106 { 1795 /* c.nge.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips },
9107 { 1795 /* c.nge.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9108 { 1795 /* c.nge.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9109 { 1803 /* c.ngl.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9110 { 1803 /* c.ngl.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9111 { 1803 /* c.ngl.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9112 { 1803 /* c.ngl.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9113 { 1803 /* c.ngl.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9114 { 1803 /* c.ngl.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9115 { 1803 /* c.ngl.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9116 { 1803 /* c.ngl.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9117 { 1803 /* c.ngl.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9118 { 1803 /* c.ngl.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9119 { 1803 /* c.ngl.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9120 { 1803 /* c.ngl.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9121 { 1811 /* c.ngl.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips },
9122 { 1811 /* c.ngl.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9123 { 1811 /* c.ngl.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips },
9124 { 1811 /* c.ngl.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips },
9125 { 1811 /* c.ngl.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9126 { 1811 /* c.ngl.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9127 { 1819 /* c.ngle.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9128 { 1819 /* c.ngle.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9129 { 1819 /* c.ngle.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9130 { 1819 /* c.ngle.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9131 { 1819 /* c.ngle.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9132 { 1819 /* c.ngle.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9133 { 1819 /* c.ngle.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9134 { 1819 /* c.ngle.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9135 { 1819 /* c.ngle.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9136 { 1819 /* c.ngle.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9137 { 1819 /* c.ngle.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9138 { 1819 /* c.ngle.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9139 { 1828 /* c.ngle.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips },
9140 { 1828 /* c.ngle.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9141 { 1828 /* c.ngle.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips },
9142 { 1828 /* c.ngle.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips },
9143 { 1828 /* c.ngle.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9144 { 1828 /* c.ngle.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9145 { 1837 /* c.ngt.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9146 { 1837 /* c.ngt.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9147 { 1837 /* c.ngt.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9148 { 1837 /* c.ngt.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9149 { 1837 /* c.ngt.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9150 { 1837 /* c.ngt.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9151 { 1837 /* c.ngt.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9152 { 1837 /* c.ngt.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9153 { 1837 /* c.ngt.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9154 { 1837 /* c.ngt.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9155 { 1837 /* c.ngt.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9156 { 1837 /* c.ngt.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9157 { 1845 /* c.ngt.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips },
9158 { 1845 /* c.ngt.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9159 { 1845 /* c.ngt.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips },
9160 { 1845 /* c.ngt.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips },
9161 { 1845 /* c.ngt.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9162 { 1845 /* c.ngt.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9163 { 1853 /* c.ole.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9164 { 1853 /* c.ole.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9165 { 1853 /* c.ole.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9166 { 1853 /* c.ole.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9167 { 1853 /* c.ole.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9168 { 1853 /* c.ole.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9169 { 1853 /* c.ole.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9170 { 1853 /* c.ole.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9171 { 1853 /* c.ole.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9172 { 1853 /* c.ole.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9173 { 1853 /* c.ole.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9174 { 1853 /* c.ole.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9175 { 1861 /* c.ole.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9176 { 1861 /* c.ole.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9177 { 1861 /* c.ole.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9178 { 1861 /* c.ole.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9179 { 1861 /* c.ole.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9180 { 1861 /* c.ole.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9181 { 1869 /* c.olt.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9182 { 1869 /* c.olt.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9183 { 1869 /* c.olt.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9184 { 1869 /* c.olt.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9185 { 1869 /* c.olt.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9186 { 1869 /* c.olt.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9187 { 1869 /* c.olt.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9188 { 1869 /* c.olt.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9189 { 1869 /* c.olt.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9190 { 1869 /* c.olt.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9191 { 1869 /* c.olt.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9192 { 1869 /* c.olt.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9193 { 1877 /* c.olt.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9194 { 1877 /* c.olt.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9195 { 1877 /* c.olt.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9196 { 1877 /* c.olt.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9197 { 1877 /* c.olt.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9198 { 1877 /* c.olt.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9199 { 1885 /* c.seq.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9200 { 1885 /* c.seq.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9201 { 1885 /* c.seq.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9202 { 1885 /* c.seq.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9203 { 1885 /* c.seq.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9204 { 1885 /* c.seq.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9205 { 1885 /* c.seq.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9206 { 1885 /* c.seq.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9207 { 1885 /* c.seq.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9208 { 1885 /* c.seq.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9209 { 1885 /* c.seq.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9210 { 1885 /* c.seq.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9211 { 1893 /* c.seq.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips },
9212 { 1893 /* c.seq.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9213 { 1893 /* c.seq.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips },
9214 { 1893 /* c.seq.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips },
9215 { 1893 /* c.seq.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9216 { 1893 /* c.seq.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9217 { 1901 /* c.sf.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9218 { 1901 /* c.sf.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9219 { 1901 /* c.sf.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9220 { 1901 /* c.sf.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9221 { 1901 /* c.sf.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9222 { 1901 /* c.sf.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9223 { 1901 /* c.sf.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9224 { 1901 /* c.sf.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9225 { 1901 /* c.sf.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9226 { 1901 /* c.sf.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9227 { 1901 /* c.sf.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9228 { 1901 /* c.sf.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9229 { 1908 /* c.sf.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips },
9230 { 1908 /* c.sf.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9231 { 1908 /* c.sf.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips },
9232 { 1908 /* c.sf.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips },
9233 { 1908 /* c.sf.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9234 { 1908 /* c.sf.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9235 { 1915 /* c.ueq.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9236 { 1915 /* c.ueq.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9237 { 1915 /* c.ueq.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9238 { 1915 /* c.ueq.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9239 { 1915 /* c.ueq.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9240 { 1915 /* c.ueq.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9241 { 1915 /* c.ueq.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9242 { 1915 /* c.ueq.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9243 { 1915 /* c.ueq.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9244 { 1915 /* c.ueq.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9245 { 1915 /* c.ueq.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9246 { 1915 /* c.ueq.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9247 { 1923 /* c.ueq.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips },
9248 { 1923 /* c.ueq.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9249 { 1923 /* c.ueq.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips },
9250 { 1923 /* c.ueq.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips },
9251 { 1923 /* c.ueq.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9252 { 1923 /* c.ueq.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9253 { 1931 /* c.ule.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9254 { 1931 /* c.ule.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9255 { 1931 /* c.ule.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9256 { 1931 /* c.ule.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9257 { 1931 /* c.ule.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9258 { 1931 /* c.ule.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9259 { 1931 /* c.ule.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9260 { 1931 /* c.ule.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9261 { 1931 /* c.ule.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9262 { 1931 /* c.ule.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9263 { 1931 /* c.ule.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9264 { 1931 /* c.ule.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9265 { 1939 /* c.ule.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips },
9266 { 1939 /* c.ule.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9267 { 1939 /* c.ule.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips },
9268 { 1939 /* c.ule.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips },
9269 { 1939 /* c.ule.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9270 { 1939 /* c.ule.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9271 { 1947 /* c.ult.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9272 { 1947 /* c.ult.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9273 { 1947 /* c.ult.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9274 { 1947 /* c.ult.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9275 { 1947 /* c.ult.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9276 { 1947 /* c.ult.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9277 { 1947 /* c.ult.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9278 { 1947 /* c.ult.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9279 { 1947 /* c.ult.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9280 { 1947 /* c.ult.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9281 { 1947 /* c.ult.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9282 { 1947 /* c.ult.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9283 { 1955 /* c.ult.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips },
9284 { 1955 /* c.ult.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9285 { 1955 /* c.ult.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips },
9286 { 1955 /* c.ult.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips },
9287 { 1955 /* c.ult.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9288 { 1955 /* c.ult.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9289 { 1963 /* c.un.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9290 { 1963 /* c.un.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9291 { 1963 /* c.un.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9292 { 1963 /* c.un.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9293 { 1963 /* c.un.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9294 { 1963 /* c.un.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9295 { 1963 /* c.un.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9296 { 1963 /* c.un.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9297 { 1963 /* c.un.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9298 { 1963 /* c.un.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9299 { 1963 /* c.un.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9300 { 1963 /* c.un.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
9301 { 1970 /* c.un.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips },
9302 { 1970 /* c.un.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9303 { 1970 /* c.un.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips },
9304 { 1970 /* c.un.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_IsNotSoftFloat_NotInMicroMips },
9305 { 1970 /* c.un.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9306 { 1970 /* c.un.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9307 { 1977 /* cache */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
9308 { 1977 /* cache */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_HasMips3_32_NotMips32r6_NotMips64r6_NotInMicroMips },
9309 { 1977 /* cache */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips_NotMips32r6 },
9310 { 1977 /* cache */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips_HasMips32r6 },
9311 { 1983 /* cachee */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips },
9312 { 1983 /* cachee */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_InMicroMips_HasEVA },
9313 { 1990 /* ceil.l.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips3_32_IsNotSoftFloat_NotInMicroMips },
9314 { 1990 /* ceil.l.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9315 { 1999 /* ceil.l.s */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips },
9316 { 1999 /* ceil.l.s */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips },
9317 { 1999 /* ceil.l.s */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9318 { 1999 /* ceil.l.s */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9319 { 2008 /* ceil.w.d */, 2 /* 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips },
9320 { 2008 /* ceil.w.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips },
9321 { 2008 /* ceil.w.d */, 2 /* 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat },
9322 { 2008 /* ceil.w.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat },
9323 { 2008 /* ceil.w.d */, 2 /* 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9324 { 2008 /* ceil.w.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9325 { 2008 /* ceil.w.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips },
9326 { 2008 /* ceil.w.d */, 2 /* 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips },
9327 { 2017 /* ceil.w.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotR5900_IsNotSoftFloat_NotInMicroMips },
9328 { 2017 /* ceil.w.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9329 { 2017 /* ceil.w.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat },
9330 { 2026 /* ceq.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9331 { 2032 /* ceq.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9332 { 2038 /* ceq.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9333 { 2044 /* ceq.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9334 { 2050 /* ceqi.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9335 { 2057 /* ceqi.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9336 { 2064 /* ceqi.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9337 { 2071 /* ceqi.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9338 { 2078 /* cfc1 */, 2 /* 1 */, MCK_CCRAsmReg, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips },
9339 { 2078 /* cfc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips },
9340 { 2078 /* cfc1 */, 2 /* 1 */, MCK_CCRAsmReg, AMFBS_InMicroMips_IsNotSoftFloat },
9341 { 2078 /* cfc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat },
9342 { 2083 /* cfc2 */, 2 /* 1 */, MCK_COP2AsmReg, AMFBS_InMicroMips },
9343 { 2083 /* cfc2 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
9344 { 2088 /* cfcmsa */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA },
9345 { 2088 /* cfcmsa */, 2 /* 1 */, MCK_MSACtrlAsmReg, AMFBS_HasStdEnc_HasMSA },
9346 { 2095 /* cftc1 */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_HasMT },
9347 { 2095 /* cftc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT },
9348 { 2101 /* cins */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasMips64_HasCnMips_NotInMicroMips },
9349 { 2101 /* cins */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasMips64_HasCnMips },
9350 { 2101 /* cins */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasMips64_HasCnMips_NotInMicroMips },
9351 { 2101 /* cins */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasMips64_HasCnMips },
9352 { 2106 /* cins32 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasMips64_HasCnMips_NotInMicroMips },
9353 { 2106 /* cins32 */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasMips64_HasCnMips_NotInMicroMips },
9354 { 2113 /* class.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
9355 { 2113 /* class.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6 },
9356 { 2121 /* class.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
9357 { 2121 /* class.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
9358 { 2129 /* cle_s.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9359 { 2137 /* cle_s.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9360 { 2145 /* cle_s.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9361 { 2153 /* cle_s.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9362 { 2161 /* cle_u.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9363 { 2169 /* cle_u.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9364 { 2177 /* cle_u.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9365 { 2185 /* cle_u.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9366 { 2193 /* clei_s.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9367 { 2202 /* clei_s.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9368 { 2211 /* clei_s.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9369 { 2220 /* clei_s.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9370 { 2229 /* clei_u.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9371 { 2238 /* clei_u.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9372 { 2247 /* clei_u.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9373 { 2256 /* clei_u.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9374 { 2265 /* clo */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips },
9375 { 2265 /* clo */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
9376 { 2265 /* clo */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6 },
9377 { 2265 /* clo */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
9378 { 2269 /* clt_s.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9379 { 2277 /* clt_s.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9380 { 2285 /* clt_s.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9381 { 2293 /* clt_s.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9382 { 2301 /* clt_u.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9383 { 2309 /* clt_u.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9384 { 2317 /* clt_u.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9385 { 2325 /* clt_u.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9386 { 2333 /* clti_s.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9387 { 2342 /* clti_s.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9388 { 2351 /* clti_s.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9389 { 2360 /* clti_s.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9390 { 2369 /* clti_u.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9391 { 2378 /* clti_u.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9392 { 2387 /* clti_u.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9393 { 2396 /* clti_u.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9394 { 2405 /* clz */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips },
9395 { 2405 /* clz */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
9396 { 2405 /* clz */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6 },
9397 { 2405 /* clz */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
9398 { 2413 /* cmp.af.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
9399 { 2413 /* cmp.af.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9400 { 2422 /* cmp.af.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
9401 { 2422 /* cmp.af.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9402 { 2431 /* cmp.eq.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
9403 { 2431 /* cmp.eq.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9404 { 2440 /* cmp.eq.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
9405 { 2440 /* cmp.eq.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
9406 { 2450 /* cmp.eq.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
9407 { 2450 /* cmp.eq.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9408 { 2459 /* cmp.le.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
9409 { 2459 /* cmp.le.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9410 { 2468 /* cmp.le.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
9411 { 2468 /* cmp.le.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
9412 { 2478 /* cmp.le.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
9413 { 2478 /* cmp.le.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9414 { 2487 /* cmp.lt.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
9415 { 2487 /* cmp.lt.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9416 { 2496 /* cmp.lt.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
9417 { 2496 /* cmp.lt.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
9418 { 2506 /* cmp.lt.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
9419 { 2506 /* cmp.lt.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9420 { 2515 /* cmp.saf.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
9421 { 2515 /* cmp.saf.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9422 { 2525 /* cmp.saf.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
9423 { 2525 /* cmp.saf.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9424 { 2535 /* cmp.seq.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
9425 { 2535 /* cmp.seq.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9426 { 2545 /* cmp.seq.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
9427 { 2545 /* cmp.seq.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9428 { 2555 /* cmp.sle.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
9429 { 2555 /* cmp.sle.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9430 { 2565 /* cmp.sle.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
9431 { 2565 /* cmp.sle.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9432 { 2575 /* cmp.slt.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
9433 { 2575 /* cmp.slt.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9434 { 2585 /* cmp.slt.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
9435 { 2585 /* cmp.slt.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9436 { 2595 /* cmp.sueq.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
9437 { 2595 /* cmp.sueq.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9438 { 2606 /* cmp.sueq.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
9439 { 2606 /* cmp.sueq.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9440 { 2617 /* cmp.sule.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
9441 { 2617 /* cmp.sule.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9442 { 2628 /* cmp.sule.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
9443 { 2628 /* cmp.sule.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9444 { 2639 /* cmp.sult.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
9445 { 2639 /* cmp.sult.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9446 { 2650 /* cmp.sult.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
9447 { 2650 /* cmp.sult.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9448 { 2661 /* cmp.sun.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
9449 { 2661 /* cmp.sun.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9450 { 2671 /* cmp.sun.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
9451 { 2671 /* cmp.sun.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9452 { 2681 /* cmp.ueq.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
9453 { 2681 /* cmp.ueq.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9454 { 2691 /* cmp.ueq.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
9455 { 2691 /* cmp.ueq.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9456 { 2701 /* cmp.ule.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
9457 { 2701 /* cmp.ule.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9458 { 2711 /* cmp.ule.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
9459 { 2711 /* cmp.ule.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9460 { 2721 /* cmp.ult.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
9461 { 2721 /* cmp.ult.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9462 { 2731 /* cmp.ult.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
9463 { 2731 /* cmp.ult.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9464 { 2741 /* cmp.un.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
9465 { 2741 /* cmp.un.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9466 { 2750 /* cmp.un.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
9467 { 2750 /* cmp.un.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9468 { 2759 /* cmpgdu.eq.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
9469 { 2759 /* cmpgdu.eq.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
9470 { 2772 /* cmpgdu.le.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
9471 { 2772 /* cmpgdu.le.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
9472 { 2785 /* cmpgdu.lt.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
9473 { 2785 /* cmpgdu.lt.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
9474 { 2798 /* cmpgu.eq.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
9475 { 2798 /* cmpgu.eq.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
9476 { 2810 /* cmpgu.le.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
9477 { 2810 /* cmpgu.le.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
9478 { 2822 /* cmpgu.lt.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
9479 { 2822 /* cmpgu.lt.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
9480 { 2839 /* cmpu.eq.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
9481 { 2839 /* cmpu.eq.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
9482 { 2850 /* cmpu.le.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
9483 { 2850 /* cmpu.le.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
9484 { 2861 /* cmpu.lt.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
9485 { 2861 /* cmpu.lt.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
9486 { 2872 /* copy_s.b */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA },
9487 { 2872 /* copy_s.b */, 2 /* 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9488 { 2881 /* copy_s.d */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMSA_HasMips64 },
9489 { 2881 /* copy_s.d */, 2 /* 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA_HasMips64 },
9490 { 2890 /* copy_s.h */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA },
9491 { 2890 /* copy_s.h */, 2 /* 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9492 { 2899 /* copy_s.w */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA },
9493 { 2899 /* copy_s.w */, 2 /* 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9494 { 2908 /* copy_u.b */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA },
9495 { 2908 /* copy_u.b */, 2 /* 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9496 { 2917 /* copy_u.h */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA },
9497 { 2917 /* copy_u.h */, 2 /* 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9498 { 2926 /* copy_u.w */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA_HasMips64 },
9499 { 2926 /* copy_u.w */, 2 /* 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA_HasMips64 },
9500 { 2935 /* crc32b */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips },
9501 { 2942 /* crc32cb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips },
9502 { 2950 /* crc32cd */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips64r6_HasCRC_NotInMicroMips },
9503 { 2958 /* crc32ch */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips },
9504 { 2966 /* crc32cw */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips },
9505 { 2974 /* crc32d */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips64r6_HasCRC_NotInMicroMips },
9506 { 2981 /* crc32h */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips },
9507 { 2988 /* crc32w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips },
9508 { 2995 /* ctc1 */, 2 /* 1 */, MCK_CCRAsmReg, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips },
9509 { 2995 /* ctc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips },
9510 { 2995 /* ctc1 */, 2 /* 1 */, MCK_CCRAsmReg, AMFBS_InMicroMips_IsNotSoftFloat },
9511 { 2995 /* ctc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat },
9512 { 3000 /* ctc2 */, 2 /* 1 */, MCK_COP2AsmReg, AMFBS_InMicroMips },
9513 { 3000 /* ctc2 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
9514 { 3005 /* ctcmsa */, 2 /* 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA },
9515 { 3005 /* ctcmsa */, 1 /* 0 */, MCK_MSACtrlAsmReg, AMFBS_HasStdEnc_HasMSA },
9516 { 3012 /* cttc1 */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_HasMT },
9517 { 3012 /* cttc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT },
9518 { 3018 /* cvt.d.l */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips },
9519 { 3018 /* cvt.d.l */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_HasMips32r6_IsNotSoftFloat },
9520 { 3026 /* cvt.d.s */, 1 /* 0 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips },
9521 { 3026 /* cvt.d.s */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips },
9522 { 3026 /* cvt.d.s */, 1 /* 0 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat },
9523 { 3026 /* cvt.d.s */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat },
9524 { 3026 /* cvt.d.s */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips },
9525 { 3026 /* cvt.d.s */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips },
9526 { 3026 /* cvt.d.s */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat },
9527 { 3026 /* cvt.d.s */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat },
9528 { 3034 /* cvt.d.w */, 1 /* 0 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips },
9529 { 3034 /* cvt.d.w */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips },
9530 { 3034 /* cvt.d.w */, 1 /* 0 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat },
9531 { 3034 /* cvt.d.w */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat },
9532 { 3034 /* cvt.d.w */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips },
9533 { 3034 /* cvt.d.w */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips },
9534 { 3034 /* cvt.d.w */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat },
9535 { 3034 /* cvt.d.w */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat },
9536 { 3042 /* cvt.l.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips },
9537 { 3042 /* cvt.l.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat },
9538 { 3042 /* cvt.l.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9539 { 3050 /* cvt.l.s */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips },
9540 { 3050 /* cvt.l.s */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips },
9541 { 3050 /* cvt.l.s */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat },
9542 { 3050 /* cvt.l.s */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat },
9543 { 3050 /* cvt.l.s */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9544 { 3050 /* cvt.l.s */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9545 { 3058 /* cvt.ps.pw */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMips3D },
9546 { 3068 /* cvt.ps.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9547 { 3068 /* cvt.ps.s */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9548 { 3077 /* cvt.pw.ps */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMips3D },
9549 { 3087 /* cvt.s.d */, 2 /* 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips },
9550 { 3087 /* cvt.s.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips },
9551 { 3087 /* cvt.s.d */, 2 /* 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat },
9552 { 3087 /* cvt.s.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat },
9553 { 3087 /* cvt.s.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips },
9554 { 3087 /* cvt.s.d */, 2 /* 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips },
9555 { 3087 /* cvt.s.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat },
9556 { 3087 /* cvt.s.d */, 2 /* 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat },
9557 { 3095 /* cvt.s.l */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips },
9558 { 3095 /* cvt.s.l */, 2 /* 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips },
9559 { 3095 /* cvt.s.l */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_HasMips32r6_IsNotSoftFloat },
9560 { 3095 /* cvt.s.l */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_HasMips32r6_IsNotSoftFloat },
9561 { 3103 /* cvt.s.pl */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9562 { 3103 /* cvt.s.pl */, 2 /* 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9563 { 3112 /* cvt.s.pu */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9564 { 3112 /* cvt.s.pu */, 2 /* 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9565 { 3121 /* cvt.s.w */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips },
9566 { 3121 /* cvt.s.w */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9567 { 3121 /* cvt.s.w */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat },
9568 { 3129 /* cvt.w.d */, 2 /* 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips },
9569 { 3129 /* cvt.w.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips },
9570 { 3129 /* cvt.w.d */, 2 /* 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat },
9571 { 3129 /* cvt.w.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat },
9572 { 3129 /* cvt.w.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips },
9573 { 3129 /* cvt.w.d */, 2 /* 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips },
9574 { 3129 /* cvt.w.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat },
9575 { 3129 /* cvt.w.d */, 2 /* 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat },
9576 { 3137 /* cvt.w.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips },
9577 { 3137 /* cvt.w.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9578 { 3137 /* cvt.w.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat },
9579 { 3145 /* dadd */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9580 { 3145 /* dadd */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips },
9581 { 3145 /* dadd */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9582 { 3145 /* dadd */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips },
9583 { 3150 /* daddi */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 },
9584 { 3150 /* daddi */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 },
9585 { 3156 /* daddiu */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9586 { 3156 /* daddiu */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9587 { 3163 /* daddu */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9588 { 3163 /* daddu */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9589 { 3163 /* daddu */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9590 { 3163 /* daddu */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9591 { 3169 /* dahi */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips },
9592 { 3174 /* dalign */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips },
9593 { 3181 /* dati */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips },
9594 { 3186 /* daui */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips },
9595 { 3191 /* dbitswap */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips },
9596 { 3200 /* dclo */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips64_NotMips64r6_NotInMicroMips },
9597 { 3200 /* dclo */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips },
9598 { 3205 /* dclz */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips64_NotMips64r6_NotInMicroMips },
9599 { 3205 /* dclz */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips },
9600 { 3210 /* ddiv */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips },
9601 { 3210 /* ddiv */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips },
9602 { 3210 /* ddiv */, 6 /* 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips },
9603 { 3210 /* ddiv */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips },
9604 { 3210 /* ddiv */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips },
9605 { 3210 /* ddiv */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips },
9606 { 3215 /* ddivu */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips },
9607 { 3215 /* ddivu */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips },
9608 { 3215 /* ddivu */, 6 /* 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips },
9609 { 3215 /* ddivu */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips },
9610 { 3215 /* ddivu */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips },
9611 { 3215 /* ddivu */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips },
9612 { 3227 /* dext */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips },
9613 { 3227 /* dext */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips },
9614 { 3227 /* dext */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips },
9615 { 3232 /* dextm */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips },
9616 { 3238 /* dextu */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips },
9617 { 3244 /* di */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips },
9618 { 3244 /* di */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
9619 { 3244 /* di */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
9620 { 3247 /* dins */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips },
9621 { 3247 /* dins */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips },
9622 { 3247 /* dins */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips },
9623 { 3252 /* dinsm */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips },
9624 { 3258 /* dinsu */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips },
9625 { 3264 /* div */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6 },
9626 { 3264 /* div */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 },
9627 { 3264 /* div */, 2 /* 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 },
9628 { 3264 /* div */, 1 /* 0 */, MCK_GPR32NonZeroAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 },
9629 { 3264 /* div */, 2 /* 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 },
9630 { 3264 /* div */, 1 /* 0 */, MCK_GPR32ZeroAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 },
9631 { 3264 /* div */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips },
9632 { 3264 /* div */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
9633 { 3264 /* div */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
9634 { 3264 /* div */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
9635 { 3264 /* div */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 },
9636 { 3264 /* div */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 },
9637 { 3264 /* div */, 1 /* 0 */, MCK_GPR32NonZeroAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 },
9638 { 3268 /* div.d */, 7 /* 0, 1, 2 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips },
9639 { 3268 /* div.d */, 7 /* 0, 1, 2 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat },
9640 { 3268 /* div.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips },
9641 { 3268 /* div.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat },
9642 { 3274 /* div.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips },
9643 { 3274 /* div.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9644 { 3274 /* div.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat },
9645 { 3280 /* div_s.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9646 { 3288 /* div_s.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9647 { 3296 /* div_s.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9648 { 3304 /* div_s.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9649 { 3312 /* div_u.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9650 { 3320 /* div_u.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9651 { 3328 /* div_u.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9652 { 3336 /* div_u.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9653 { 3344 /* divu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6 },
9654 { 3344 /* divu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 },
9655 { 3344 /* divu */, 2 /* 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 },
9656 { 3344 /* divu */, 1 /* 0 */, MCK_GPR32NonZeroAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 },
9657 { 3344 /* divu */, 2 /* 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 },
9658 { 3344 /* divu */, 1 /* 0 */, MCK_GPR32ZeroAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 },
9659 { 3344 /* divu */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips },
9660 { 3344 /* divu */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
9661 { 3344 /* divu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 },
9662 { 3344 /* divu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
9663 { 3344 /* divu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
9664 { 3344 /* divu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 },
9665 { 3349 /* dla */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_None },
9666 { 3349 /* dla */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_None },
9667 { 3349 /* dla */, 2 /* 1 */, MCK_Mem, AMFBS_None },
9668 { 3353 /* dli */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_None },
9669 { 3357 /* dlsa */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMSA_HasMips64 },
9670 { 3357 /* dlsa */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips },
9671 { 3362 /* dmfc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_NotInMicroMips },
9672 { 3362 /* dmfc0 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_NotInMicroMips },
9673 { 3362 /* dmfc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips3 },
9674 { 3362 /* dmfc0 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips3 },
9675 { 3368 /* dmfc1 */, 2 /* 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips3_IsNotSoftFloat_IsNotSingleFloat },
9676 { 3368 /* dmfc1 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_IsNotSoftFloat_IsNotSingleFloat },
9677 { 3374 /* dmfc2 */, 2 /* 1 */, MCK_COP2AsmReg, AMFBS_None },
9678 { 3374 /* dmfc2 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_None },
9679 { 3374 /* dmfc2 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasCnMips },
9680 { 3374 /* dmfc2 */, 2 /* 1 */, MCK_COP2AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips3 },
9681 { 3374 /* dmfc2 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips3 },
9682 { 3380 /* dmfgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasStdEnc_HasMips64r5_HasVirt_NotInMicroMips },
9683 { 3380 /* dmfgc0 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r5_HasVirt_NotInMicroMips },
9684 { 3380 /* dmfgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasStdEnc_HasMips64r5_HasVirt },
9685 { 3380 /* dmfgc0 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r5_HasVirt },
9686 { 3387 /* dmod */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips },
9687 { 3392 /* dmodu */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips },
9688 { 3398 /* dmt */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMT_NotInMicroMips },
9689 { 3402 /* dmtc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_NotInMicroMips },
9690 { 3402 /* dmtc0 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_NotInMicroMips },
9691 { 3402 /* dmtc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips3 },
9692 { 3402 /* dmtc0 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips3 },
9693 { 3408 /* dmtc1 */, 2 /* 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips3_IsNotSoftFloat_IsNotSingleFloat },
9694 { 3408 /* dmtc1 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_IsNotSoftFloat_IsNotSingleFloat },
9695 { 3414 /* dmtc2 */, 2 /* 1 */, MCK_COP2AsmReg, AMFBS_None },
9696 { 3414 /* dmtc2 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_None },
9697 { 3414 /* dmtc2 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasCnMips },
9698 { 3414 /* dmtc2 */, 2 /* 1 */, MCK_COP2AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips3 },
9699 { 3414 /* dmtc2 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips3 },
9700 { 3420 /* dmtgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasStdEnc_HasMips64r5_HasVirt_NotInMicroMips },
9701 { 3420 /* dmtgc0 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r5_HasVirt_NotInMicroMips },
9702 { 3420 /* dmtgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasStdEnc_HasMips64r5_HasVirt },
9703 { 3420 /* dmtgc0 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r5_HasVirt },
9704 { 3427 /* dmuh */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips },
9705 { 3432 /* dmuhu */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips },
9706 { 3438 /* dmul */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasCnMips },
9707 { 3438 /* dmul */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasMips3_NotMips64r6_NotCnMips_NotR5900 },
9708 { 3438 /* dmul */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips },
9709 { 3438 /* dmul */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasCnMips },
9710 { 3438 /* dmul */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900 },
9711 { 3443 /* dmulo */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900 },
9712 { 3449 /* dmulou */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900 },
9713 { 3456 /* dmult */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips },
9714 { 3462 /* dmultu */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips },
9715 { 3469 /* dmulu */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips },
9716 { 3475 /* dneg */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9717 { 3475 /* dneg */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9718 { 3480 /* dnegu */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9719 { 3480 /* dnegu */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9720 { 3486 /* dotp_s.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9721 { 3495 /* dotp_s.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9722 { 3504 /* dotp_s.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9723 { 3513 /* dotp_u.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9724 { 3522 /* dotp_u.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9725 { 3531 /* dotp_u.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9726 { 3540 /* dpa.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSPR2 },
9727 { 3540 /* dpa.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
9728 { 3540 /* dpa.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSPR2 },
9729 { 3540 /* dpa.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
9730 { 3549 /* dpadd_s.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9731 { 3559 /* dpadd_s.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9732 { 3569 /* dpadd_s.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9733 { 3579 /* dpadd_u.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9734 { 3589 /* dpadd_u.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9735 { 3599 /* dpadd_u.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9736 { 3609 /* dpaq_s.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
9737 { 3609 /* dpaq_s.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
9738 { 3609 /* dpaq_s.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
9739 { 3609 /* dpaq_s.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
9740 { 3621 /* dpaq_sa.l.w */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
9741 { 3621 /* dpaq_sa.l.w */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
9742 { 3621 /* dpaq_sa.l.w */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
9743 { 3621 /* dpaq_sa.l.w */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
9744 { 3633 /* dpaqx_s.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSPR2 },
9745 { 3633 /* dpaqx_s.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
9746 { 3633 /* dpaqx_s.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSPR2 },
9747 { 3633 /* dpaqx_s.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
9748 { 3646 /* dpaqx_sa.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSPR2 },
9749 { 3646 /* dpaqx_sa.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
9750 { 3646 /* dpaqx_sa.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSPR2 },
9751 { 3646 /* dpaqx_sa.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
9752 { 3660 /* dpau.h.qbl */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
9753 { 3660 /* dpau.h.qbl */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
9754 { 3660 /* dpau.h.qbl */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
9755 { 3660 /* dpau.h.qbl */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
9756 { 3671 /* dpau.h.qbr */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
9757 { 3671 /* dpau.h.qbr */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
9758 { 3671 /* dpau.h.qbr */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
9759 { 3671 /* dpau.h.qbr */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
9760 { 3682 /* dpax.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSPR2 },
9761 { 3682 /* dpax.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
9762 { 3682 /* dpax.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSPR2 },
9763 { 3682 /* dpax.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
9764 { 3692 /* dpop */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasCnMips },
9765 { 3692 /* dpop */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasCnMips },
9766 { 3697 /* dps.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSPR2 },
9767 { 3697 /* dps.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
9768 { 3697 /* dps.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSPR2 },
9769 { 3697 /* dps.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
9770 { 3706 /* dpsq_s.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
9771 { 3706 /* dpsq_s.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
9772 { 3706 /* dpsq_s.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
9773 { 3706 /* dpsq_s.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
9774 { 3718 /* dpsq_sa.l.w */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
9775 { 3718 /* dpsq_sa.l.w */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
9776 { 3718 /* dpsq_sa.l.w */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
9777 { 3718 /* dpsq_sa.l.w */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
9778 { 3730 /* dpsqx_s.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSPR2 },
9779 { 3730 /* dpsqx_s.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
9780 { 3730 /* dpsqx_s.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSPR2 },
9781 { 3730 /* dpsqx_s.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
9782 { 3743 /* dpsqx_sa.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSPR2 },
9783 { 3743 /* dpsqx_sa.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
9784 { 3743 /* dpsqx_sa.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSPR2 },
9785 { 3743 /* dpsqx_sa.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
9786 { 3757 /* dpsu.h.qbl */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
9787 { 3757 /* dpsu.h.qbl */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
9788 { 3757 /* dpsu.h.qbl */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
9789 { 3757 /* dpsu.h.qbl */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
9790 { 3768 /* dpsu.h.qbr */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
9791 { 3768 /* dpsu.h.qbr */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
9792 { 3768 /* dpsu.h.qbr */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
9793 { 3768 /* dpsu.h.qbr */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
9794 { 3779 /* dpsub_s.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9795 { 3789 /* dpsub_s.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9796 { 3799 /* dpsub_s.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9797 { 3809 /* dpsub_u.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9798 { 3819 /* dpsub_u.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9799 { 3829 /* dpsub_u.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9800 { 3839 /* dpsx.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSPR2 },
9801 { 3839 /* dpsx.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
9802 { 3839 /* dpsx.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSPR2 },
9803 { 3839 /* dpsx.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
9804 { 3849 /* drem */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips },
9805 { 3849 /* drem */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips },
9806 { 3849 /* drem */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips },
9807 { 3849 /* drem */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips },
9808 { 3854 /* dremu */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips },
9809 { 3854 /* dremu */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips },
9810 { 3854 /* dremu */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips },
9811 { 3854 /* dremu */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips },
9812 { 3860 /* drol */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips64 },
9813 { 3860 /* drol */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips64 },
9814 { 3860 /* drol */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips64 },
9815 { 3860 /* drol */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips64 },
9816 { 3865 /* dror */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips64 },
9817 { 3865 /* dror */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips64 },
9818 { 3865 /* dror */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips64 },
9819 { 3865 /* dror */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips64 },
9820 { 3870 /* drotr */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips },
9821 { 3870 /* drotr */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips },
9822 { 3876 /* drotr32 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips },
9823 { 3876 /* drotr32 */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips },
9824 { 3884 /* drotrv */, 4 /* 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips },
9825 { 3884 /* drotrv */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips },
9826 { 3891 /* dsbh */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips },
9827 { 3896 /* dshd */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips },
9828 { 3901 /* dsll */, 2 /* 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9829 { 3901 /* dsll */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9830 { 3901 /* dsll */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9831 { 3901 /* dsll */, 4 /* 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9832 { 3901 /* dsll */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9833 { 3901 /* dsll */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9834 { 3906 /* dsll32 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9835 { 3906 /* dsll32 */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9836 { 3913 /* dsllv */, 4 /* 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9837 { 3913 /* dsllv */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9838 { 3919 /* dsra */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9839 { 3919 /* dsra */, 4 /* 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips3 },
9840 { 3919 /* dsra */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3 },
9841 { 3919 /* dsra */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9842 { 3924 /* dsra32 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9843 { 3924 /* dsra32 */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9844 { 3931 /* dsrav */, 4 /* 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9845 { 3931 /* dsrav */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9846 { 3937 /* dsrl */, 2 /* 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9847 { 3937 /* dsrl */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9848 { 3937 /* dsrl */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9849 { 3937 /* dsrl */, 4 /* 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9850 { 3937 /* dsrl */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9851 { 3937 /* dsrl */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9852 { 3942 /* dsrl32 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9853 { 3942 /* dsrl32 */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9854 { 3949 /* dsrlv */, 4 /* 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9855 { 3949 /* dsrlv */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9856 { 3955 /* dsub */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9857 { 3955 /* dsub */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 },
9858 { 3955 /* dsub */, 2 /* 1 */, MCK_InvNum, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 },
9859 { 3955 /* dsub */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9860 { 3955 /* dsub */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 },
9861 { 3955 /* dsub */, 4 /* 2 */, MCK_InvNum, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 },
9862 { 3960 /* dsubi */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 },
9863 { 3960 /* dsubi */, 2 /* 1 */, MCK_InvNum, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 },
9864 { 3960 /* dsubi */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 },
9865 { 3960 /* dsubi */, 4 /* 2 */, MCK_InvNum, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 },
9866 { 3966 /* dsubu */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9867 { 3966 /* dsubu */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9868 { 3966 /* dsubu */, 2 /* 1 */, MCK_InvNum, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9869 { 3966 /* dsubu */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9870 { 3966 /* dsubu */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9871 { 3966 /* dsubu */, 4 /* 2 */, MCK_InvNum, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9872 { 3972 /* dvp */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6 },
9873 { 3972 /* dvp */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
9874 { 3976 /* dvpe */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMT_NotInMicroMips },
9875 { 3985 /* ei */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips },
9876 { 3985 /* ei */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
9877 { 3985 /* ei */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
9878 { 3988 /* emt */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMT_NotInMicroMips },
9879 { 4004 /* evp */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6 },
9880 { 4004 /* evp */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
9881 { 4008 /* evpe */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMT_NotInMicroMips },
9882 { 4013 /* ext */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips },
9883 { 4013 /* ext */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
9884 { 4013 /* ext */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
9885 { 4017 /* extp */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
9886 { 4017 /* extp */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
9887 { 4017 /* extp */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
9888 { 4017 /* extp */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
9889 { 4022 /* extpdp */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
9890 { 4022 /* extpdp */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
9891 { 4022 /* extpdp */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
9892 { 4022 /* extpdp */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
9893 { 4029 /* extpdpv */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
9894 { 4029 /* extpdpv */, 5 /* 0, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
9895 { 4029 /* extpdpv */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
9896 { 4029 /* extpdpv */, 5 /* 0, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
9897 { 4037 /* extpv */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
9898 { 4037 /* extpv */, 5 /* 0, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
9899 { 4037 /* extpv */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
9900 { 4037 /* extpv */, 5 /* 0, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
9901 { 4043 /* extr.w */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
9902 { 4043 /* extr.w */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
9903 { 4043 /* extr.w */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
9904 { 4043 /* extr.w */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
9905 { 4050 /* extr_r.w */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
9906 { 4050 /* extr_r.w */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
9907 { 4050 /* extr_r.w */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
9908 { 4050 /* extr_r.w */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
9909 { 4059 /* extr_rs.w */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
9910 { 4059 /* extr_rs.w */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
9911 { 4059 /* extr_rs.w */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
9912 { 4059 /* extr_rs.w */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
9913 { 4069 /* extr_s.h */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
9914 { 4069 /* extr_s.h */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
9915 { 4069 /* extr_s.h */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
9916 { 4069 /* extr_s.h */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
9917 { 4078 /* extrv.w */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
9918 { 4078 /* extrv.w */, 5 /* 0, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
9919 { 4078 /* extrv.w */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
9920 { 4078 /* extrv.w */, 5 /* 0, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
9921 { 4086 /* extrv_r.w */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
9922 { 4086 /* extrv_r.w */, 5 /* 0, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
9923 { 4086 /* extrv_r.w */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
9924 { 4086 /* extrv_r.w */, 5 /* 0, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
9925 { 4096 /* extrv_rs.w */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
9926 { 4096 /* extrv_rs.w */, 5 /* 0, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
9927 { 4096 /* extrv_rs.w */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
9928 { 4096 /* extrv_rs.w */, 5 /* 0, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
9929 { 4107 /* extrv_s.h */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
9930 { 4107 /* extrv_s.h */, 5 /* 0, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
9931 { 4107 /* extrv_s.h */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
9932 { 4107 /* extrv_s.h */, 5 /* 0, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
9933 { 4117 /* exts */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasMips64_HasCnMips_NotInMicroMips },
9934 { 4117 /* exts */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasMips64_HasCnMips },
9935 { 4117 /* exts */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasMips64_HasCnMips_NotInMicroMips },
9936 { 4117 /* exts */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasMips64_HasCnMips },
9937 { 4122 /* exts32 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasMips64_HasCnMips_NotInMicroMips },
9938 { 4122 /* exts32 */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasMips64_HasCnMips_NotInMicroMips },
9939 { 4129 /* fadd.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9940 { 4136 /* fadd.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9941 { 4143 /* fcaf.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9942 { 4150 /* fcaf.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9943 { 4157 /* fceq.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9944 { 4164 /* fceq.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9945 { 4171 /* fclass.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9946 { 4180 /* fclass.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9947 { 4189 /* fcle.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9948 { 4196 /* fcle.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9949 { 4203 /* fclt.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9950 { 4210 /* fclt.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9951 { 4217 /* fcne.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9952 { 4224 /* fcne.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9953 { 4231 /* fcor.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9954 { 4238 /* fcor.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9955 { 4245 /* fcueq.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9956 { 4253 /* fcueq.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9957 { 4261 /* fcule.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9958 { 4269 /* fcule.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9959 { 4277 /* fcult.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9960 { 4285 /* fcult.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9961 { 4293 /* fcun.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9962 { 4300 /* fcun.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9963 { 4307 /* fcune.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9964 { 4315 /* fcune.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9965 { 4323 /* fdiv.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9966 { 4330 /* fdiv.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9967 { 4337 /* fexdo.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9968 { 4345 /* fexdo.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9969 { 4353 /* fexp2.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9970 { 4361 /* fexp2.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9971 { 4369 /* fexupl.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9972 { 4378 /* fexupl.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9973 { 4387 /* fexupr.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9974 { 4396 /* fexupr.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9975 { 4405 /* ffint_s.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9976 { 4415 /* ffint_s.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9977 { 4425 /* ffint_u.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9978 { 4435 /* ffint_u.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9979 { 4445 /* ffql.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9980 { 4452 /* ffql.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9981 { 4459 /* ffqr.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9982 { 4466 /* ffqr.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9983 { 4473 /* fill.b */, 2 /* 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA },
9984 { 4473 /* fill.b */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9985 { 4480 /* fill.d */, 2 /* 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMSA_HasMips64 },
9986 { 4480 /* fill.d */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA_HasMips64 },
9987 { 4487 /* fill.h */, 2 /* 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA },
9988 { 4487 /* fill.h */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9989 { 4494 /* fill.w */, 2 /* 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA },
9990 { 4494 /* fill.w */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9991 { 4501 /* flog2.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9992 { 4509 /* flog2.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9993 { 4517 /* floor.l.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips3_32_IsNotSoftFloat_NotInMicroMips },
9994 { 4517 /* floor.l.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9995 { 4527 /* floor.l.s */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips },
9996 { 4527 /* floor.l.s */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips },
9997 { 4527 /* floor.l.s */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9998 { 4527 /* floor.l.s */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9999 { 4537 /* floor.w.d */, 2 /* 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips },
10000 { 4537 /* floor.w.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips },
10001 { 4537 /* floor.w.d */, 2 /* 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat },
10002 { 4537 /* floor.w.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat },
10003 { 4537 /* floor.w.d */, 2 /* 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
10004 { 4537 /* floor.w.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
10005 { 4537 /* floor.w.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips },
10006 { 4537 /* floor.w.d */, 2 /* 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips },
10007 { 4547 /* floor.w.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotR5900_IsNotSoftFloat_NotInMicroMips },
10008 { 4547 /* floor.w.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
10009 { 4547 /* floor.w.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat },
10010 { 4557 /* fmadd.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10011 { 4565 /* fmadd.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10012 { 4573 /* fmax.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10013 { 4580 /* fmax.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10014 { 4587 /* fmax_a.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10015 { 4596 /* fmax_a.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10016 { 4605 /* fmin.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10017 { 4612 /* fmin.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10018 { 4619 /* fmin_a.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10019 { 4628 /* fmin_a.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10020 { 4637 /* fmsub.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10021 { 4645 /* fmsub.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10022 { 4653 /* fmul.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10023 { 4660 /* fmul.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10024 { 4667 /* fork */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMT_NotInMicroMips },
10025 { 4672 /* frcp.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10026 { 4679 /* frcp.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10027 { 4686 /* frint.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10028 { 4694 /* frint.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10029 { 4702 /* frsqrt.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10030 { 4711 /* frsqrt.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10031 { 4720 /* fsaf.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10032 { 4727 /* fsaf.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10033 { 4734 /* fseq.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10034 { 4741 /* fseq.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10035 { 4748 /* fsle.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10036 { 4755 /* fsle.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10037 { 4762 /* fslt.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10038 { 4769 /* fslt.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10039 { 4776 /* fsne.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10040 { 4783 /* fsne.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10041 { 4790 /* fsor.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10042 { 4797 /* fsor.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10043 { 4804 /* fsqrt.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10044 { 4812 /* fsqrt.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10045 { 4820 /* fsub.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10046 { 4827 /* fsub.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10047 { 4834 /* fsueq.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10048 { 4842 /* fsueq.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10049 { 4850 /* fsule.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10050 { 4858 /* fsule.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10051 { 4866 /* fsult.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10052 { 4874 /* fsult.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10053 { 4882 /* fsun.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10054 { 4889 /* fsun.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10055 { 4896 /* fsune.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10056 { 4904 /* fsune.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10057 { 4912 /* ftint_s.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10058 { 4922 /* ftint_s.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10059 { 4932 /* ftint_u.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10060 { 4942 /* ftint_u.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10061 { 4952 /* ftq.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10062 { 4958 /* ftq.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10063 { 4964 /* ftrunc_s.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10064 { 4975 /* ftrunc_s.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10065 { 4986 /* ftrunc_u.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10066 { 4997 /* ftrunc_u.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10067 { 5008 /* ginvi */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_HasGINV_NotInMicroMips },
10068 { 5008 /* ginvi */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6_HasGINV },
10069 { 5014 /* ginvt */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_HasGINV_NotInMicroMips },
10070 { 5014 /* ginvt */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6_HasGINV },
10071 { 5020 /* hadd_s.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10072 { 5029 /* hadd_s.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10073 { 5038 /* hadd_s.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10074 { 5047 /* hadd_u.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10075 { 5056 /* hadd_u.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10076 { 5065 /* hadd_u.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10077 { 5074 /* hsub_s.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10078 { 5083 /* hsub_s.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10079 { 5092 /* hsub_s.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10080 { 5101 /* hsub_u.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10081 { 5110 /* hsub_u.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10082 { 5119 /* hsub_u.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10083 { 5136 /* ilvev.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10084 { 5144 /* ilvev.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10085 { 5152 /* ilvev.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10086 { 5160 /* ilvev.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10087 { 5168 /* ilvl.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10088 { 5175 /* ilvl.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10089 { 5182 /* ilvl.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10090 { 5189 /* ilvl.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10091 { 5196 /* ilvod.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10092 { 5204 /* ilvod.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10093 { 5212 /* ilvod.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10094 { 5220 /* ilvod.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10095 { 5228 /* ilvr.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10096 { 5235 /* ilvr.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10097 { 5242 /* ilvr.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10098 { 5249 /* ilvr.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10099 { 5256 /* ins */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips },
10100 { 5256 /* ins */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10101 { 5256 /* ins */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10102 { 5260 /* insert.b */, 16 /* 4 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA },
10103 { 5260 /* insert.b */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10104 { 5269 /* insert.d */, 16 /* 4 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMSA_HasMips64 },
10105 { 5269 /* insert.d */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA_HasMips64 },
10106 { 5278 /* insert.h */, 16 /* 4 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA },
10107 { 5278 /* insert.h */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10108 { 5287 /* insert.w */, 16 /* 4 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA },
10109 { 5287 /* insert.w */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10110 { 5296 /* insv */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10111 { 5296 /* insv */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10112 { 5301 /* insve.b */, 17 /* 0, 4 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10113 { 5309 /* insve.d */, 17 /* 0, 4 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10114 { 5317 /* insve.h */, 17 /* 0, 4 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10115 { 5325 /* insve.w */, 17 /* 0, 4 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10116 { 5333 /* j */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips },
10117 { 5333 /* j */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
10118 { 5333 /* j */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10119 { 5333 /* j */, 1 /* 0 */, MCK_JumpTarget, AMFBS_HasStdEnc_NotInMicroMips },
10120 { 5335 /* jal */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None },
10121 { 5335 /* jal */, 1 /* 0 */, MCK_JumpTarget, AMFBS_HasStdEnc_NotInMicroMips },
10122 { 5335 /* jal */, 1 /* 0 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 },
10123 { 5335 /* jal */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_None },
10124 { 5339 /* jalr */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10125 { 5339 /* jalr */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10126 { 5339 /* jalr */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_NotInMicroMips },
10127 { 5339 /* jalr */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips_NoIndirectJumpGuards },
10128 { 5339 /* jalr */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10129 { 5339 /* jalr */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_NotInMips16Mode_IsPTR64bit },
10130 { 5344 /* jalr.hb */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32_NotInMicroMips },
10131 { 5344 /* jalr.hb */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10132 { 5344 /* jalr.hb */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64_NotInMicroMips },
10133 { 5344 /* jalr.hb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32 },
10134 { 5344 /* jalr.hb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10135 { 5344 /* jalr.hb */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips },
10136 { 5352 /* jalrc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsGP32bit_HasMips32r6_NotInMicroMips },
10137 { 5352 /* jalrc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10138 { 5352 /* jalrc */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r6 },
10139 { 5352 /* jalrc */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10140 { 5358 /* jalrc.hb */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10141 { 5358 /* jalrc.hb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10142 { 5367 /* jalrs */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10143 { 5373 /* jalrs16 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10144 { 5386 /* jalx */, 1 /* 0 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips },
10145 { 5386 /* jalx */, 1 /* 0 */, MCK_JumpTarget, AMFBS_InMicroMips_NotMips32r6 },
10146 { 5391 /* jialc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6 },
10147 { 5391 /* jialc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6 },
10148 { 5391 /* jialc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10149 { 5391 /* jialc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 },
10150 { 5391 /* jialc */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 },
10151 { 5391 /* jialc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 },
10152 { 5397 /* jic */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6 },
10153 { 5397 /* jic */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6 },
10154 { 5397 /* jic */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10155 { 5397 /* jic */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 },
10156 { 5397 /* jic */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 },
10157 { 5397 /* jic */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 },
10158 { 5401 /* jr */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips },
10159 { 5401 /* jr */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsGP32bit_HasMips32r6_NotInMicroMips },
10160 { 5401 /* jr */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10161 { 5401 /* jr */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_NotInMips16Mode_IsPTR64bit_NotInMicroMips },
10162 { 5401 /* jr */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r6 },
10163 { 5404 /* jr.hb */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6 },
10164 { 5404 /* jr.hb */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10165 { 5404 /* jr.hb */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6 },
10166 { 5404 /* jr.hb */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64_NotMips64r6_NotInMicroMips },
10167 { 5404 /* jr.hb */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips32r6 },
10168 { 5410 /* jr16 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10169 { 5425 /* jrc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsGP32bit_HasMips32r6 },
10170 { 5425 /* jrc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10171 { 5425 /* jrc */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r6 },
10172 { 5429 /* jrc16 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10173 { 5446 /* l.d */, 1 /* 0 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat },
10174 { 5446 /* l.d */, 2 /* 1 */, MCK_MemOffsetSimm16_0, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat },
10175 { 5446 /* l.d */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat },
10176 { 5446 /* l.d */, 2 /* 1 */, MCK_MemOffsetSimm16_0, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat },
10177 { 5450 /* l.s */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips2_IsNotSoftFloat },
10178 { 5450 /* l.s */, 2 /* 1 */, MCK_MemOffsetSimm16_0, AMFBS_HasStdEnc_HasMips2_IsNotSoftFloat },
10179 { 5454 /* la */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None },
10180 { 5454 /* la */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None },
10181 { 5454 /* la */, 2 /* 1 */, MCK_Mem, AMFBS_None },
10182 { 5457 /* lapc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6 },
10183 { 5457 /* lapc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10184 { 5462 /* lb */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
10185 { 5462 /* lb */, 2 /* 1 */, MCK_MemOffsetSimmPtr, AMFBS_HasStdEnc_NotInMicroMips },
10186 { 5462 /* lb */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10187 { 5462 /* lb */, 2 /* 1 */, MCK_MemOffsetSimm16_0, AMFBS_InMicroMips_HasMips32r6 },
10188 { 5462 /* lb */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
10189 { 5462 /* lb */, 2 /* 1 */, MCK_MemOffsetSimm16_0, AMFBS_InMicroMips },
10190 { 5465 /* lbe */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips },
10191 { 5465 /* lbe */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips },
10192 { 5465 /* lbe */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasEVA },
10193 { 5465 /* lbe */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips_HasEVA },
10194 { 5469 /* lbu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
10195 { 5469 /* lbu */, 2 /* 1 */, MCK_MemOffsetSimmPtr, AMFBS_HasStdEnc_NotInMicroMips },
10196 { 5469 /* lbu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10197 { 5469 /* lbu */, 2 /* 1 */, MCK_MemOffsetSimm16_0, AMFBS_InMicroMips_HasMips32r6 },
10198 { 5469 /* lbu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
10199 { 5469 /* lbu */, 2 /* 1 */, MCK_MemOffsetSimm16_0, AMFBS_InMicroMips },
10200 { 5473 /* lbu16 */, 1 /* 0 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips },
10201 { 5473 /* lbu16 */, 2 /* 1 */, MCK_MicroMipsMem, AMFBS_InMicroMips },
10202 { 5479 /* lbue */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips },
10203 { 5479 /* lbue */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips },
10204 { 5479 /* lbue */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasEVA },
10205 { 5479 /* lbue */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips_HasEVA },
10206 { 5484 /* lbux */, 11 /* 0, 1, 3 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10207 { 5484 /* lbux */, 11 /* 0, 1, 3 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10208 { 5489 /* ld */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips3 },
10209 { 5489 /* ld */, 2 /* 1 */, MCK_MemOffsetSimm16_0, AMFBS_HasStdEnc_NotMips3 },
10210 { 5489 /* ld */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
10211 { 5489 /* ld */, 2 /* 1 */, MCK_MemOffsetSimmPtr, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
10212 { 5492 /* ld.b */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10213 { 5492 /* ld.b */, 2 /* 1 */, MCK_MemOffsetSimm10_0, AMFBS_HasStdEnc_HasMSA },
10214 { 5497 /* ld.d */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10215 { 5497 /* ld.d */, 2 /* 1 */, MCK_MemOffsetSimm10_3, AMFBS_HasStdEnc_HasMSA },
10216 { 5502 /* ld.h */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10217 { 5502 /* ld.h */, 2 /* 1 */, MCK_MemOffsetSimm10_1, AMFBS_HasStdEnc_HasMSA },
10218 { 5507 /* ld.w */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10219 { 5507 /* ld.w */, 2 /* 1 */, MCK_MemOffsetSimm10_2, AMFBS_HasStdEnc_HasMSA },
10220 { 5512 /* ldc1 */, 1 /* 0 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips },
10221 { 5512 /* ldc1 */, 2 /* 1 */, MCK_MemOffsetSimm16_0, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips },
10222 { 5512 /* ldc1 */, 1 /* 0 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat },
10223 { 5512 /* ldc1 */, 2 /* 1 */, MCK_MemOffsetSimm16_0, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat },
10224 { 5512 /* ldc1 */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips },
10225 { 5512 /* ldc1 */, 2 /* 1 */, MCK_MemOffsetSimm16_0, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips },
10226 { 5512 /* ldc1 */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_HasMips32r6_IsNotSoftFloat },
10227 { 5512 /* ldc1 */, 2 /* 1 */, MCK_MemOffsetSimm16_0, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_HasMips32r6_IsNotSoftFloat },
10228 { 5512 /* ldc1 */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat },
10229 { 5512 /* ldc1 */, 2 /* 1 */, MCK_MemOffsetSimm16_0, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat },
10230 { 5517 /* ldc2 */, 1 /* 0 */, MCK_COP2AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
10231 { 5517 /* ldc2 */, 2 /* 1 */, MCK_MemOffsetSimm11_0, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
10232 { 5517 /* ldc2 */, 1 /* 0 */, MCK_COP2AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10233 { 5517 /* ldc2 */, 2 /* 1 */, MCK_MemOffsetSimm11_0, AMFBS_InMicroMips_HasMips32r6 },
10234 { 5517 /* ldc2 */, 1 /* 0 */, MCK_COP2AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips },
10235 { 5517 /* ldc2 */, 2 /* 1 */, MCK_MemOffsetSimm16_0, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips },
10236 { 5522 /* ldc3 */, 1 /* 0 */, MCK_COP3AsmReg, AMFBS_HasStdEnc_HasMips2_NotR5900_NotCnMips_NotInMicroMips },
10237 { 5522 /* ldc3 */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_HasMips2_NotR5900_NotCnMips_NotInMicroMips },
10238 { 5527 /* ldi.b */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10239 { 5533 /* ldi.d */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10240 { 5539 /* ldi.h */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10241 { 5545 /* ldi.w */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10242 { 5551 /* ldl */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 },
10243 { 5551 /* ldl */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 },
10244 { 5555 /* ldpc */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r6 },
10245 { 5560 /* ldr */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 },
10246 { 5560 /* ldr */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 },
10247 { 5564 /* ldxc1 */, 1 /* 0 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
10248 { 5564 /* ldxc1 */, 10 /* 1, 3 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
10249 { 5564 /* ldxc1 */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat },
10250 { 5564 /* ldxc1 */, 10 /* 1, 3 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat },
10251 { 5570 /* lh */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
10252 { 5570 /* lh */, 2 /* 1 */, MCK_MemOffsetSimmPtr, AMFBS_HasStdEnc_NotInMicroMips },
10253 { 5570 /* lh */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
10254 { 5570 /* lh */, 2 /* 1 */, MCK_MemOffsetSimmPtr, AMFBS_InMicroMips },
10255 { 5573 /* lhe */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips },
10256 { 5573 /* lhe */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips },
10257 { 5573 /* lhe */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasEVA },
10258 { 5573 /* lhe */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_InMicroMips_HasEVA },
10259 { 5577 /* lhu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
10260 { 5577 /* lhu */, 2 /* 1 */, MCK_MemOffsetSimmPtr, AMFBS_HasStdEnc_NotInMicroMips },
10261 { 5577 /* lhu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
10262 { 5577 /* lhu */, 2 /* 1 */, MCK_MemOffsetSimmPtr, AMFBS_InMicroMips },
10263 { 5581 /* lhu16 */, 1 /* 0 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips },
10264 { 5581 /* lhu16 */, 2 /* 1 */, MCK_MicroMipsMem, AMFBS_InMicroMips },
10265 { 5587 /* lhue */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips },
10266 { 5587 /* lhue */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips },
10267 { 5587 /* lhue */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasEVA },
10268 { 5587 /* lhue */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_InMicroMips_HasEVA },
10269 { 5592 /* lhx */, 11 /* 0, 1, 3 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10270 { 5592 /* lhx */, 11 /* 0, 1, 3 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10271 { 5596 /* li */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None },
10272 { 5599 /* li.d */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None },
10273 { 5599 /* li.d */, 1 /* 0 */, MCK_StrictlyAFGR64AsmReg, AMFBS_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat },
10274 { 5599 /* li.d */, 1 /* 0 */, MCK_StrictlyFGR64AsmReg, AMFBS_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat },
10275 { 5604 /* li.s */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None },
10276 { 5604 /* li.s */, 1 /* 0 */, MCK_StrictlyFGR32AsmReg, AMFBS_IsNotSoftFloat },
10277 { 5609 /* li16 */, 1 /* 0 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10278 { 5609 /* li16 */, 1 /* 0 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10279 { 5614 /* ll */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsPTR64bit_HasMips64r6_NotInMicroMips },
10280 { 5614 /* ll */, 2 /* 1 */, MCK_MemOffsetSimmPtr, AMFBS_HasStdEnc_IsPTR64bit_HasMips64r6_NotInMicroMips },
10281 { 5614 /* ll */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsPTR32bit_HasMips32r6_NotInMicroMips },
10282 { 5614 /* ll */, 2 /* 1 */, MCK_MemOffsetSimmPtr, AMFBS_HasStdEnc_IsPTR32bit_HasMips32r6_NotInMicroMips },
10283 { 5614 /* ll */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10284 { 5614 /* ll */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_InMicroMips_HasMips32r6 },
10285 { 5614 /* ll */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsPTR32bit_HasMips2_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips },
10286 { 5614 /* ll */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_IsPTR32bit_HasMips2_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips },
10287 { 5614 /* ll */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsPTR64bit_HasMips2_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips },
10288 { 5614 /* ll */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_IsPTR64bit_HasMips2_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips },
10289 { 5614 /* ll */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10290 { 5614 /* ll */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips_NotMips32r6 },
10291 { 5617 /* lld */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips },
10292 { 5617 /* lld */, 2 /* 1 */, MCK_MemOffsetSimmPtr, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips },
10293 { 5617 /* lld */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips },
10294 { 5617 /* lld */, 2 /* 1 */, MCK_MemOffsetSimmPtr, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips },
10295 { 5621 /* lle */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips },
10296 { 5621 /* lle */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips },
10297 { 5621 /* lle */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasEVA },
10298 { 5621 /* lle */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_InMicroMips_HasEVA },
10299 { 5625 /* lsa */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA },
10300 { 5625 /* lsa */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10301 { 5625 /* lsa */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6 },
10302 { 5629 /* lui */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10303 { 5629 /* lui */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
10304 { 5629 /* lui */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10305 { 5633 /* luxc1 */, 1 /* 0 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
10306 { 5633 /* luxc1 */, 10 /* 1, 3 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
10307 { 5633 /* luxc1 */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
10308 { 5633 /* luxc1 */, 10 /* 1, 3 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
10309 { 5633 /* luxc1 */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
10310 { 5633 /* luxc1 */, 10 /* 1, 3 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
10311 { 5639 /* lw */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
10312 { 5639 /* lw */, 2 /* 1 */, MCK_MicroMipsMemSP, AMFBS_InMicroMips },
10313 { 5639 /* lw */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
10314 { 5639 /* lw */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_NotInMicroMips },
10315 { 5639 /* lw */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_NotInMips16Mode_HasDSP },
10316 { 5639 /* lw */, 2 /* 1 */, MCK_Mem, AMFBS_NotInMips16Mode_HasDSP },
10317 { 5639 /* lw */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10318 { 5639 /* lw */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips_HasDSP },
10319 { 5639 /* lw */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10320 { 5639 /* lw */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips_HasMips32r6 },
10321 { 5639 /* lw */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
10322 { 5639 /* lw */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips },
10323 { 5639 /* lw */, 1 /* 0 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips },
10324 { 5639 /* lw */, 2 /* 1 */, MCK_MicroMipsMemGP, AMFBS_InMicroMips },
10325 { 5642 /* lw16 */, 1 /* 0 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips },
10326 { 5642 /* lw16 */, 2 /* 1 */, MCK_MicroMipsMem, AMFBS_InMicroMips },
10327 { 5647 /* lwc1 */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips },
10328 { 5647 /* lwc1 */, 2 /* 1 */, MCK_MemOffsetSimm16_0, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips },
10329 { 5647 /* lwc1 */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat },
10330 { 5647 /* lwc1 */, 2 /* 1 */, MCK_MemOffsetSimm16_0, AMFBS_InMicroMips_IsNotSoftFloat },
10331 { 5652 /* lwc2 */, 1 /* 0 */, MCK_COP2AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
10332 { 5652 /* lwc2 */, 2 /* 1 */, MCK_MemOffsetSimm11_0, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
10333 { 5652 /* lwc2 */, 1 /* 0 */, MCK_COP2AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10334 { 5652 /* lwc2 */, 2 /* 1 */, MCK_MemOffsetSimm11_0, AMFBS_InMicroMips_HasMips32r6 },
10335 { 5652 /* lwc2 */, 1 /* 0 */, MCK_COP2AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips },
10336 { 5652 /* lwc2 */, 2 /* 1 */, MCK_MemOffsetSimm16_0, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips },
10337 { 5657 /* lwc3 */, 1 /* 0 */, MCK_COP3AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_NotCnMips_NotInMicroMips },
10338 { 5657 /* lwc3 */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_NotCnMips_NotInMicroMips },
10339 { 5662 /* lwe */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips },
10340 { 5662 /* lwe */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips },
10341 { 5662 /* lwe */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasEVA },
10342 { 5662 /* lwe */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_InMicroMips_HasEVA },
10343 { 5666 /* lwl */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips },
10344 { 5666 /* lwl */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips },
10345 { 5666 /* lwl */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10346 { 5666 /* lwl */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips_NotMips32r6 },
10347 { 5670 /* lwle */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips },
10348 { 5670 /* lwle */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips },
10349 { 5670 /* lwle */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6_HasEVA },
10350 { 5670 /* lwle */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_InMicroMips_NotMips32r6_HasEVA },
10351 { 5675 /* lwm */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips },
10352 { 5675 /* lwm */, 1 /* 0 */, MCK_RegList, AMFBS_InMicroMips },
10353 { 5679 /* lwm16 */, 2 /* 1 */, MCK_MemOffsetUimm4, AMFBS_InMicroMips_NotMips32r6 },
10354 { 5679 /* lwm16 */, 1 /* 0 */, MCK_RegList16, AMFBS_InMicroMips_NotMips32r6 },
10355 { 5679 /* lwm16 */, 2 /* 1 */, MCK_MemOffsetUimm4, AMFBS_InMicroMips_HasMips32r6 },
10356 { 5679 /* lwm16 */, 1 /* 0 */, MCK_RegList16, AMFBS_InMicroMips_HasMips32r6 },
10357 { 5685 /* lwm32 */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips },
10358 { 5685 /* lwm32 */, 1 /* 0 */, MCK_RegList, AMFBS_InMicroMips },
10359 { 5691 /* lwp */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
10360 { 5691 /* lwp */, 2 /* 1 */, MCK_MemOffsetSimm12_0, AMFBS_InMicroMips },
10361 { 5695 /* lwpc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6 },
10362 { 5695 /* lwpc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10363 { 5700 /* lwr */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips },
10364 { 5700 /* lwr */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips },
10365 { 5700 /* lwr */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10366 { 5700 /* lwr */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips_NotMips32r6 },
10367 { 5704 /* lwre */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips },
10368 { 5704 /* lwre */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips },
10369 { 5704 /* lwre */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6_HasEVA },
10370 { 5704 /* lwre */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_InMicroMips_NotMips32r6_HasEVA },
10371 { 5709 /* lwu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10372 { 5709 /* lwu */, 2 /* 1 */, MCK_MemOffsetSimm12_0, AMFBS_InMicroMips_NotMips32r6 },
10373 { 5709 /* lwu */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
10374 { 5709 /* lwu */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
10375 { 5713 /* lwupc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips64r6 },
10376 { 5719 /* lwx */, 11 /* 0, 1, 3 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10377 { 5719 /* lwx */, 11 /* 0, 1, 3 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10378 { 5723 /* lwxc1 */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat },
10379 { 5723 /* lwxc1 */, 10 /* 1, 3 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat },
10380 { 5723 /* lwxc1 */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
10381 { 5723 /* lwxc1 */, 10 /* 1, 3 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
10382 { 5729 /* lwxs */, 11 /* 0, 1, 3 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
10383 { 5734 /* madd */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips },
10384 { 5734 /* madd */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10385 { 5734 /* madd */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
10386 { 5734 /* madd */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10387 { 5734 /* madd */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
10388 { 5734 /* madd */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10389 { 5739 /* madd.d */, 15 /* 0, 1, 2, 3 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4 },
10390 { 5739 /* madd.d */, 15 /* 0, 1, 2, 3 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat_HasMadd4 },
10391 { 5739 /* madd.d */, 15 /* 0, 1, 2, 3 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4 },
10392 { 5746 /* madd.s */, 15 /* 0, 1, 2, 3 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4 },
10393 { 5746 /* madd.s */, 15 /* 0, 1, 2, 3 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat_HasMadd4 },
10394 { 5753 /* madd_q.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10395 { 5762 /* madd_q.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10396 { 5771 /* maddf.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
10397 { 5771 /* maddf.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
10398 { 5779 /* maddf.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
10399 { 5779 /* maddf.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
10400 { 5787 /* maddr_q.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10401 { 5797 /* maddr_q.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10402 { 5807 /* maddu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips },
10403 { 5807 /* maddu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10404 { 5807 /* maddu */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
10405 { 5807 /* maddu */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10406 { 5807 /* maddu */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
10407 { 5807 /* maddu */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10408 { 5813 /* maddv.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10409 { 5821 /* maddv.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10410 { 5829 /* maddv.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10411 { 5837 /* maddv.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10412 { 5845 /* maq_s.w.phl */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
10413 { 5845 /* maq_s.w.phl */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10414 { 5845 /* maq_s.w.phl */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
10415 { 5845 /* maq_s.w.phl */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10416 { 5857 /* maq_s.w.phr */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
10417 { 5857 /* maq_s.w.phr */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10418 { 5857 /* maq_s.w.phr */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
10419 { 5857 /* maq_s.w.phr */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10420 { 5869 /* maq_sa.w.phl */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
10421 { 5869 /* maq_sa.w.phl */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10422 { 5869 /* maq_sa.w.phl */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
10423 { 5869 /* maq_sa.w.phl */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10424 { 5882 /* maq_sa.w.phr */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
10425 { 5882 /* maq_sa.w.phr */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10426 { 5882 /* maq_sa.w.phr */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
10427 { 5882 /* maq_sa.w.phr */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10428 { 5895 /* max.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
10429 { 5895 /* max.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
10430 { 5901 /* max.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
10431 { 5901 /* max.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
10432 { 5907 /* max_a.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10433 { 5915 /* max_a.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10434 { 5923 /* max_a.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10435 { 5931 /* max_a.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10436 { 5939 /* max_s.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10437 { 5947 /* max_s.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10438 { 5955 /* max_s.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10439 { 5963 /* max_s.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10440 { 5971 /* max_u.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10441 { 5979 /* max_u.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10442 { 5987 /* max_u.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10443 { 5995 /* max_u.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10444 { 6003 /* maxa.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
10445 { 6003 /* maxa.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
10446 { 6010 /* maxa.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
10447 { 6010 /* maxa.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
10448 { 6017 /* maxi_s.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10449 { 6026 /* maxi_s.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10450 { 6035 /* maxi_s.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10451 { 6044 /* maxi_s.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10452 { 6053 /* maxi_u.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10453 { 6062 /* maxi_u.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10454 { 6071 /* maxi_u.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10455 { 6080 /* maxi_u.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10456 { 6089 /* mfc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
10457 { 6089 /* mfc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
10458 { 6089 /* mfc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10459 { 6089 /* mfc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10460 { 6089 /* mfc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10461 { 6089 /* mfc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10462 { 6089 /* mfc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
10463 { 6089 /* mfc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
10464 { 6089 /* mfc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10465 { 6089 /* mfc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10466 { 6089 /* mfc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10467 { 6089 /* mfc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10468 { 6094 /* mfc1 */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips },
10469 { 6094 /* mfc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips },
10470 { 6094 /* mfc1 */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
10471 { 6094 /* mfc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
10472 { 6094 /* mfc1 */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat },
10473 { 6094 /* mfc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat },
10474 { 6094 /* mfc1 */, 2 /* 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips },
10475 { 6094 /* mfc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips },
10476 { 6099 /* mfc2 */, 2 /* 1 */, MCK_COP2AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10477 { 6099 /* mfc2 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10478 { 6099 /* mfc2 */, 2 /* 1 */, MCK_COP2AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
10479 { 6099 /* mfc2 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
10480 { 6099 /* mfc2 */, 2 /* 1 */, MCK_COP2AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
10481 { 6099 /* mfc2 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
10482 { 6104 /* mfgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips },
10483 { 6104 /* mfgc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips },
10484 { 6104 /* mfgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_InMicroMips_HasMips32r5_HasVirt },
10485 { 6104 /* mfgc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r5_HasVirt },
10486 { 6104 /* mfgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips },
10487 { 6104 /* mfgc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips },
10488 { 6104 /* mfgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_InMicroMips_HasMips32r5_HasVirt },
10489 { 6104 /* mfgc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r5_HasVirt },
10490 { 6110 /* mfhc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10491 { 6110 /* mfhc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10492 { 6110 /* mfhc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10493 { 6110 /* mfhc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10494 { 6116 /* mfhc1 */, 2 /* 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips32r2_IsNotSoftFloat_NotInMicroMips },
10495 { 6116 /* mfhc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips32r2_IsNotSoftFloat_NotInMicroMips },
10496 { 6116 /* mfhc1 */, 2 /* 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat },
10497 { 6116 /* mfhc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat },
10498 { 6116 /* mfhc1 */, 2 /* 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips32r2_IsNotSoftFloat_NotInMicroMips },
10499 { 6116 /* mfhc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips32r2_IsNotSoftFloat_NotInMicroMips },
10500 { 6116 /* mfhc1 */, 2 /* 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat },
10501 { 6116 /* mfhc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat },
10502 { 6122 /* mfhc2 */, 2 /* 1 */, MCK_COP2AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10503 { 6122 /* mfhc2 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10504 { 6128 /* mfhgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips },
10505 { 6128 /* mfhgc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips },
10506 { 6128 /* mfhgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_InMicroMips_HasMips32r5_HasVirt },
10507 { 6128 /* mfhgc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r5_HasVirt },
10508 { 6128 /* mfhgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips },
10509 { 6128 /* mfhgc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips },
10510 { 6128 /* mfhgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_InMicroMips_HasMips32r5_HasVirt },
10511 { 6128 /* mfhgc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r5_HasVirt },
10512 { 6135 /* mfhi */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips },
10513 { 6135 /* mfhi */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10514 { 6135 /* mfhi */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
10515 { 6135 /* mfhi */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10516 { 6135 /* mfhi */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
10517 { 6135 /* mfhi */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10518 { 6140 /* mfhi16 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10519 { 6147 /* mflo */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips },
10520 { 6147 /* mflo */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10521 { 6147 /* mflo */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
10522 { 6147 /* mflo */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10523 { 6147 /* mflo */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
10524 { 6147 /* mflo */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10525 { 6152 /* mflo16 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10526 { 6159 /* mftacx */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT_NotInMicroMips },
10527 { 6159 /* mftacx */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasMT },
10528 { 6159 /* mftacx */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT },
10529 { 6166 /* mftc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasMT_NotInMicroMips },
10530 { 6166 /* mftc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT_NotInMicroMips },
10531 { 6166 /* mftc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasMT },
10532 { 6166 /* mftc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT },
10533 { 6172 /* mftc1 */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_HasMT },
10534 { 6172 /* mftc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT },
10535 { 6178 /* mftdsp */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT },
10536 { 6185 /* mftgpr */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasMT },
10537 { 6192 /* mfthc1 */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_HasMT },
10538 { 6192 /* mfthc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT },
10539 { 6199 /* mfthi */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT_NotInMicroMips },
10540 { 6199 /* mfthi */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasMT },
10541 { 6199 /* mfthi */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT },
10542 { 6205 /* mftlo */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT_NotInMicroMips },
10543 { 6205 /* mftlo */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasMT },
10544 { 6205 /* mftlo */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT },
10545 { 6211 /* mftr */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMT_NotInMicroMips },
10546 { 6216 /* min.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
10547 { 6216 /* min.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
10548 { 6222 /* min.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
10549 { 6222 /* min.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
10550 { 6228 /* min_a.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10551 { 6236 /* min_a.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10552 { 6244 /* min_a.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10553 { 6252 /* min_a.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10554 { 6260 /* min_s.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10555 { 6268 /* min_s.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10556 { 6276 /* min_s.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10557 { 6284 /* min_s.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10558 { 6292 /* min_u.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10559 { 6300 /* min_u.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10560 { 6308 /* min_u.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10561 { 6316 /* min_u.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10562 { 6324 /* mina.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
10563 { 6324 /* mina.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
10564 { 6331 /* mina.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
10565 { 6331 /* mina.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
10566 { 6338 /* mini_s.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10567 { 6347 /* mini_s.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10568 { 6356 /* mini_s.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10569 { 6365 /* mini_s.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10570 { 6374 /* mini_u.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10571 { 6383 /* mini_u.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10572 { 6392 /* mini_u.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10573 { 6401 /* mini_u.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10574 { 6410 /* mod */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
10575 { 6410 /* mod */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10576 { 6414 /* mod_s.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10577 { 6422 /* mod_s.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10578 { 6430 /* mod_s.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10579 { 6438 /* mod_s.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10580 { 6446 /* mod_u.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10581 { 6454 /* mod_u.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10582 { 6462 /* mod_u.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10583 { 6470 /* mod_u.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10584 { 6478 /* modsub */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10585 { 6478 /* modsub */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10586 { 6485 /* modu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
10587 { 6485 /* modu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10588 { 6490 /* mov.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips },
10589 { 6490 /* mov.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat },
10590 { 6490 /* mov.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips },
10591 { 6490 /* mov.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat },
10592 { 6490 /* mov.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
10593 { 6496 /* mov.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips },
10594 { 6496 /* mov.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
10595 { 6496 /* mov.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat },
10596 { 6502 /* move */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips },
10597 { 6502 /* move */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips },
10598 { 6502 /* move */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10599 { 6502 /* move */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_IsGP64bit_NotInMicroMips },
10600 { 6502 /* move */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_IsGP64bit_NotInMicroMips },
10601 { 6507 /* move.v */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10602 { 6514 /* move16 */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10603 { 6521 /* movep */, 12 /* 2, 3 */, MCK_GPRMM16AsmRegMoveP, AMFBS_InMicroMips_NotMips32r6 },
10604 { 6521 /* movep */, 1 /* 0 */, MCK_GPRMM16AsmRegMovePPairFirst, AMFBS_InMicroMips_NotMips32r6 },
10605 { 6521 /* movep */, 2 /* 1 */, MCK_GPRMM16AsmRegMovePPairSecond, AMFBS_InMicroMips_NotMips32r6 },
10606 { 6521 /* movep */, 12 /* 2, 3 */, MCK_GPRMM16AsmRegMoveP, AMFBS_InMicroMips_HasMips32r6 },
10607 { 6521 /* movep */, 1 /* 0 */, MCK_GPRMM16AsmRegMovePPairFirst, AMFBS_InMicroMips_HasMips32r6 },
10608 { 6521 /* movep */, 2 /* 1 */, MCK_GPRMM16AsmRegMovePPairSecond, AMFBS_InMicroMips_HasMips32r6 },
10609 { 6527 /* movf */, 4 /* 2 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
10610 { 6527 /* movf */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
10611 { 6527 /* movf */, 4 /* 2 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
10612 { 6527 /* movf */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
10613 { 6532 /* movf.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
10614 { 6532 /* movf.d */, 4 /* 2 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
10615 { 6532 /* movf.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
10616 { 6532 /* movf.d */, 4 /* 2 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
10617 { 6532 /* movf.d */, 4 /* 2 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
10618 { 6532 /* movf.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
10619 { 6539 /* movf.s */, 4 /* 2 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
10620 { 6539 /* movf.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
10621 { 6539 /* movf.s */, 4 /* 2 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
10622 { 6539 /* movf.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
10623 { 6546 /* movn */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips },
10624 { 6546 /* movn */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10625 { 6551 /* movn.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
10626 { 6551 /* movn.d */, 4 /* 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
10627 { 6551 /* movn.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
10628 { 6551 /* movn.d */, 4 /* 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
10629 { 6551 /* movn.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
10630 { 6551 /* movn.d */, 4 /* 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
10631 { 6558 /* movn.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
10632 { 6558 /* movn.s */, 4 /* 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
10633 { 6558 /* movn.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
10634 { 6558 /* movn.s */, 4 /* 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
10635 { 6565 /* movt */, 4 /* 2 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
10636 { 6565 /* movt */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
10637 { 6565 /* movt */, 4 /* 2 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
10638 { 6565 /* movt */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
10639 { 6570 /* movt.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
10640 { 6570 /* movt.d */, 4 /* 2 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
10641 { 6570 /* movt.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
10642 { 6570 /* movt.d */, 4 /* 2 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
10643 { 6570 /* movt.d */, 4 /* 2 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
10644 { 6570 /* movt.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
10645 { 6577 /* movt.s */, 4 /* 2 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
10646 { 6577 /* movt.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
10647 { 6577 /* movt.s */, 4 /* 2 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
10648 { 6577 /* movt.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
10649 { 6584 /* movz */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips },
10650 { 6584 /* movz */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10651 { 6589 /* movz.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
10652 { 6589 /* movz.d */, 4 /* 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
10653 { 6589 /* movz.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
10654 { 6589 /* movz.d */, 4 /* 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
10655 { 6589 /* movz.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
10656 { 6589 /* movz.d */, 4 /* 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
10657 { 6596 /* movz.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
10658 { 6596 /* movz.s */, 4 /* 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
10659 { 6596 /* movz.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
10660 { 6596 /* movz.s */, 4 /* 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
10661 { 6603 /* msub */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips },
10662 { 6603 /* msub */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10663 { 6603 /* msub */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
10664 { 6603 /* msub */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10665 { 6603 /* msub */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
10666 { 6603 /* msub */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10667 { 6608 /* msub.d */, 15 /* 0, 1, 2, 3 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4 },
10668 { 6608 /* msub.d */, 15 /* 0, 1, 2, 3 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat_HasMadd4 },
10669 { 6608 /* msub.d */, 15 /* 0, 1, 2, 3 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4 },
10670 { 6615 /* msub.s */, 15 /* 0, 1, 2, 3 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4 },
10671 { 6615 /* msub.s */, 15 /* 0, 1, 2, 3 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat_HasMadd4 },
10672 { 6622 /* msub_q.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10673 { 6631 /* msub_q.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10674 { 6640 /* msubf.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
10675 { 6640 /* msubf.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
10676 { 6648 /* msubf.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
10677 { 6648 /* msubf.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
10678 { 6656 /* msubr_q.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10679 { 6666 /* msubr_q.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10680 { 6676 /* msubu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips },
10681 { 6676 /* msubu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10682 { 6676 /* msubu */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
10683 { 6676 /* msubu */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10684 { 6676 /* msubu */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
10685 { 6676 /* msubu */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10686 { 6682 /* msubv.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10687 { 6690 /* msubv.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10688 { 6698 /* msubv.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10689 { 6706 /* msubv.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10690 { 6714 /* mtc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
10691 { 6714 /* mtc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
10692 { 6714 /* mtc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10693 { 6714 /* mtc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10694 { 6714 /* mtc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10695 { 6714 /* mtc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10696 { 6714 /* mtc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
10697 { 6714 /* mtc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
10698 { 6714 /* mtc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10699 { 6714 /* mtc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10700 { 6714 /* mtc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10701 { 6714 /* mtc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10702 { 6719 /* mtc1 */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips },
10703 { 6719 /* mtc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips },
10704 { 6719 /* mtc1 */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
10705 { 6719 /* mtc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
10706 { 6719 /* mtc1 */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat },
10707 { 6719 /* mtc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat },
10708 { 6719 /* mtc1 */, 2 /* 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips },
10709 { 6719 /* mtc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips },
10710 { 6719 /* mtc1 */, 2 /* 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat },
10711 { 6719 /* mtc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat },
10712 { 6724 /* mtc2 */, 2 /* 1 */, MCK_COP2AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10713 { 6724 /* mtc2 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10714 { 6724 /* mtc2 */, 2 /* 1 */, MCK_COP2AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
10715 { 6724 /* mtc2 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
10716 { 6724 /* mtc2 */, 2 /* 1 */, MCK_COP2AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
10717 { 6724 /* mtc2 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
10718 { 6729 /* mtgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips },
10719 { 6729 /* mtgc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips },
10720 { 6729 /* mtgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_InMicroMips_HasMips32r5_HasVirt },
10721 { 6729 /* mtgc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r5_HasVirt },
10722 { 6729 /* mtgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips },
10723 { 6729 /* mtgc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips },
10724 { 6729 /* mtgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_InMicroMips_HasMips32r5_HasVirt },
10725 { 6729 /* mtgc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r5_HasVirt },
10726 { 6735 /* mthc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10727 { 6735 /* mthc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10728 { 6735 /* mthc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10729 { 6735 /* mthc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10730 { 6741 /* mthc1 */, 2 /* 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips32r2_IsNotSoftFloat_NotInMicroMips },
10731 { 6741 /* mthc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips32r2_IsNotSoftFloat_NotInMicroMips },
10732 { 6741 /* mthc1 */, 2 /* 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat },
10733 { 6741 /* mthc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat },
10734 { 6741 /* mthc1 */, 2 /* 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips32r2_IsNotSoftFloat_NotInMicroMips },
10735 { 6741 /* mthc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips32r2_IsNotSoftFloat_NotInMicroMips },
10736 { 6741 /* mthc1 */, 2 /* 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat },
10737 { 6741 /* mthc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat },
10738 { 6747 /* mthc2 */, 2 /* 1 */, MCK_COP2AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10739 { 6747 /* mthc2 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10740 { 6753 /* mthgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips },
10741 { 6753 /* mthgc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips },
10742 { 6753 /* mthgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_InMicroMips_HasMips32r5_HasVirt },
10743 { 6753 /* mthgc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r5_HasVirt },
10744 { 6753 /* mthgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips },
10745 { 6753 /* mthgc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips },
10746 { 6753 /* mthgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_InMicroMips_HasMips32r5_HasVirt },
10747 { 6753 /* mthgc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r5_HasVirt },
10748 { 6760 /* mthi */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips },
10749 { 6760 /* mthi */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10750 { 6760 /* mthi */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10751 { 6760 /* mthi */, 2 /* 1 */, MCK_HI32DSPAsmReg, AMFBS_InMicroMips_HasDSP },
10752 { 6760 /* mthi */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10753 { 6760 /* mthi */, 2 /* 1 */, MCK_HI32DSPAsmReg, AMFBS_HasDSP },
10754 { 6765 /* mthlip */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
10755 { 6765 /* mthlip */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10756 { 6765 /* mthlip */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
10757 { 6765 /* mthlip */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10758 { 6772 /* mtlo */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips },
10759 { 6772 /* mtlo */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10760 { 6772 /* mtlo */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10761 { 6772 /* mtlo */, 2 /* 1 */, MCK_LO32DSPAsmReg, AMFBS_InMicroMips_HasDSP },
10762 { 6772 /* mtlo */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10763 { 6772 /* mtlo */, 2 /* 1 */, MCK_LO32DSPAsmReg, AMFBS_HasDSP },
10764 { 6777 /* mtm0 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasCnMips },
10765 { 6782 /* mtm1 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasCnMips },
10766 { 6787 /* mtm2 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasCnMips },
10767 { 6792 /* mtp0 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasCnMips },
10768 { 6797 /* mtp1 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasCnMips },
10769 { 6802 /* mtp2 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasCnMips },
10770 { 6807 /* mttacx */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT_NotInMicroMips },
10771 { 6807 /* mttacx */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasMT },
10772 { 6807 /* mttacx */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT },
10773 { 6814 /* mttc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasMT_NotInMicroMips },
10774 { 6814 /* mttc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT_NotInMicroMips },
10775 { 6814 /* mttc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasMT },
10776 { 6814 /* mttc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT },
10777 { 6820 /* mttc1 */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_HasMT },
10778 { 6820 /* mttc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT },
10779 { 6826 /* mttdsp */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT },
10780 { 6833 /* mttgpr */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasMT },
10781 { 6840 /* mtthc1 */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_HasMT },
10782 { 6840 /* mtthc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT },
10783 { 6847 /* mtthi */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT_NotInMicroMips },
10784 { 6847 /* mtthi */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasMT },
10785 { 6847 /* mtthi */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT },
10786 { 6853 /* mttlo */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT_NotInMicroMips },
10787 { 6853 /* mttlo */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasMT },
10788 { 6853 /* mttlo */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT },
10789 { 6859 /* mttr */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMT_NotInMicroMips },
10790 { 6864 /* muh */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10791 { 6864 /* muh */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
10792 { 6864 /* muh */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10793 { 6868 /* muhu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10794 { 6868 /* muhu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
10795 { 6868 /* muhu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10796 { 6873 /* mul */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips },
10797 { 6873 /* mul */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10798 { 6873 /* mul */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10799 { 6873 /* mul */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips },
10800 { 6873 /* mul */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
10801 { 6873 /* mul */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10802 { 6873 /* mul */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10803 { 6873 /* mul */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 },
10804 { 6877 /* mul.d */, 7 /* 0, 1, 2 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips },
10805 { 6877 /* mul.d */, 7 /* 0, 1, 2 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat },
10806 { 6877 /* mul.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips },
10807 { 6877 /* mul.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat },
10808 { 6883 /* mul.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
10809 { 6883 /* mul.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
10810 { 6890 /* mul.ps */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
10811 { 6897 /* mul.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips },
10812 { 6897 /* mul.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
10813 { 6897 /* mul.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat },
10814 { 6903 /* mul_q.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10815 { 6911 /* mul_q.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10816 { 6919 /* mul_s.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
10817 { 6919 /* mul_s.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
10818 { 6928 /* muleq_s.w.phl */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10819 { 6928 /* muleq_s.w.phl */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10820 { 6942 /* muleq_s.w.phr */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10821 { 6942 /* muleq_s.w.phr */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10822 { 6956 /* muleu_s.ph.qbl */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10823 { 6956 /* muleu_s.ph.qbl */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10824 { 6971 /* muleu_s.ph.qbr */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10825 { 6971 /* muleu_s.ph.qbr */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10826 { 6986 /* mulo */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 },
10827 { 6986 /* mulo */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 },
10828 { 6991 /* mulou */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 },
10829 { 6991 /* mulou */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 },
10830 { 6997 /* mulq_rs.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10831 { 6997 /* mulq_rs.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10832 { 7008 /* mulq_rs.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
10833 { 7008 /* mulq_rs.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
10834 { 7018 /* mulq_s.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
10835 { 7018 /* mulq_s.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
10836 { 7028 /* mulq_s.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
10837 { 7028 /* mulq_s.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
10838 { 7037 /* mulr.ps */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMips3D },
10839 { 7045 /* mulr_q.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10840 { 7054 /* mulr_q.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10841 { 7063 /* mulsa.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSPR2 },
10842 { 7063 /* mulsa.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
10843 { 7063 /* mulsa.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSPR2 },
10844 { 7063 /* mulsa.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
10845 { 7074 /* mulsaq_s.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
10846 { 7074 /* mulsaq_s.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10847 { 7074 /* mulsaq_s.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
10848 { 7074 /* mulsaq_s.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10849 { 7088 /* mult */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips },
10850 { 7088 /* mult */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10851 { 7088 /* mult */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
10852 { 7088 /* mult */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10853 { 7088 /* mult */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
10854 { 7088 /* mult */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10855 { 7093 /* multu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips },
10856 { 7093 /* multu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10857 { 7093 /* multu */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
10858 { 7093 /* multu */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10859 { 7093 /* multu */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
10860 { 7093 /* multu */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10861 { 7099 /* mulu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10862 { 7099 /* mulu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
10863 { 7099 /* mulu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10864 { 7104 /* mulv.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10865 { 7111 /* mulv.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10866 { 7118 /* mulv.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10867 { 7125 /* mulv.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10868 { 7136 /* neg */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
10869 { 7136 /* neg */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10870 { 7136 /* neg */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10871 { 7136 /* neg */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
10872 { 7136 /* neg */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10873 { 7136 /* neg */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10874 { 7140 /* neg.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips },
10875 { 7140 /* neg.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat },
10876 { 7140 /* neg.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips },
10877 { 7140 /* neg.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat },
10878 { 7146 /* neg.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
10879 { 7146 /* neg.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsNotSoftFloat },
10880 { 7146 /* neg.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat },
10881 { 7152 /* negu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
10882 { 7152 /* negu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10883 { 7152 /* negu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10884 { 7152 /* negu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
10885 { 7152 /* negu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10886 { 7152 /* negu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10887 { 7157 /* nloc.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10888 { 7164 /* nloc.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10889 { 7171 /* nloc.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10890 { 7178 /* nloc.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10891 { 7185 /* nlzc.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10892 { 7192 /* nlzc.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10893 { 7199 /* nlzc.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10894 { 7206 /* nlzc.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10895 { 7213 /* nmadd.d */, 15 /* 0, 1, 2, 3 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips },
10896 { 7213 /* nmadd.d */, 15 /* 0, 1, 2, 3 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat_HasMadd4 },
10897 { 7213 /* nmadd.d */, 15 /* 0, 1, 2, 3 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips },
10898 { 7221 /* nmadd.s */, 15 /* 0, 1, 2, 3 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips },
10899 { 7221 /* nmadd.s */, 15 /* 0, 1, 2, 3 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat_HasMadd4 },
10900 { 7229 /* nmsub.d */, 15 /* 0, 1, 2, 3 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips },
10901 { 7229 /* nmsub.d */, 15 /* 0, 1, 2, 3 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat_HasMadd4 },
10902 { 7229 /* nmsub.d */, 15 /* 0, 1, 2, 3 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips },
10903 { 7237 /* nmsub.s */, 15 /* 0, 1, 2, 3 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips },
10904 { 7237 /* nmsub.s */, 15 /* 0, 1, 2, 3 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat_HasMadd4 },
10905 { 7249 /* nor */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_IsGP32bit },
10906 { 7249 /* nor */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_IsGP64bit },
10907 { 7249 /* nor */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
10908 { 7249 /* nor */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10909 { 7249 /* nor */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10910 { 7249 /* nor */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_IsGP32bit },
10911 { 7249 /* nor */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_IsGP64bit },
10912 { 7253 /* nor.v */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10913 { 7259 /* nori.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10914 { 7266 /* not */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
10915 { 7266 /* not */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10916 { 7266 /* not */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10917 { 7266 /* not */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
10918 { 7266 /* not */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10919 { 7266 /* not */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10920 { 7270 /* not16 */, 3 /* 0, 1 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10921 { 7270 /* not16 */, 3 /* 0, 1 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10922 { 7276 /* or */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
10923 { 7276 /* or */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10924 { 7276 /* or */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10925 { 7276 /* or */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10926 { 7276 /* or */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips },
10927 { 7276 /* or */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
10928 { 7276 /* or */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips3_NotInMicroMips },
10929 { 7276 /* or */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
10930 { 7276 /* or */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10931 { 7276 /* or */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10932 { 7276 /* or */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10933 { 7276 /* or */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips },
10934 { 7276 /* or */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
10935 { 7276 /* or */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips3_NotInMicroMips },
10936 { 7279 /* or.v */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10937 { 7284 /* or16 */, 3 /* 0, 1 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10938 { 7284 /* or16 */, 3 /* 0, 1 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10939 { 7289 /* ori */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10940 { 7289 /* ori */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
10941 { 7289 /* ori */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10942 { 7289 /* ori */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10943 { 7289 /* ori */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
10944 { 7289 /* ori */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10945 { 7293 /* ori.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10946 { 7299 /* packrl.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10947 { 7299 /* packrl.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10948 { 7315 /* pckev.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10949 { 7323 /* pckev.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10950 { 7331 /* pckev.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10951 { 7339 /* pckev.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10952 { 7347 /* pckod.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10953 { 7355 /* pckod.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10954 { 7363 /* pckod.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10955 { 7371 /* pckod.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10956 { 7379 /* pcnt.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10957 { 7386 /* pcnt.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10958 { 7393 /* pcnt.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10959 { 7400 /* pcnt.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10960 { 7407 /* pick.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10961 { 7407 /* pick.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10962 { 7415 /* pick.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10963 { 7415 /* pick.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10964 { 7423 /* pll.ps */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
10965 { 7430 /* plu.ps */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
10966 { 7437 /* pop */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasCnMips },
10967 { 7437 /* pop */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasCnMips },
10968 { 7441 /* preceq.w.phl */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10969 { 7441 /* preceq.w.phl */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10970 { 7454 /* preceq.w.phr */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10971 { 7454 /* preceq.w.phr */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10972 { 7467 /* precequ.ph.qbl */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10973 { 7467 /* precequ.ph.qbl */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10974 { 7482 /* precequ.ph.qbla */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10975 { 7482 /* precequ.ph.qbla */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10976 { 7498 /* precequ.ph.qbr */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10977 { 7498 /* precequ.ph.qbr */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10978 { 7513 /* precequ.ph.qbra */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10979 { 7513 /* precequ.ph.qbra */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10980 { 7529 /* preceu.ph.qbl */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10981 { 7529 /* preceu.ph.qbl */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10982 { 7543 /* preceu.ph.qbla */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10983 { 7543 /* preceu.ph.qbla */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10984 { 7558 /* preceu.ph.qbr */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10985 { 7558 /* preceu.ph.qbr */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10986 { 7572 /* preceu.ph.qbra */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10987 { 7572 /* preceu.ph.qbra */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10988 { 7587 /* precr.qb.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
10989 { 7587 /* precr.qb.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
10990 { 7599 /* precr_sra.ph.w */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
10991 { 7599 /* precr_sra.ph.w */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
10992 { 7614 /* precr_sra_r.ph.w */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
10993 { 7614 /* precr_sra_r.ph.w */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
10994 { 7631 /* precrq.ph.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10995 { 7631 /* precrq.ph.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10996 { 7643 /* precrq.qb.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10997 { 7643 /* precrq.qb.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10998 { 7656 /* precrq_rs.ph.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10999 { 7656 /* precrq_rs.ph.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
11000 { 7671 /* precrqu_s.qb.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11001 { 7671 /* precrqu_s.qb.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
11002 { 7687 /* pref */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
11003 { 7687 /* pref */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_HasMips3_32_NotMips32r6_NotMips64r6_NotInMicroMips },
11004 { 7687 /* pref */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips_NotMips32r6 },
11005 { 7687 /* pref */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips_HasMips32r6 },
11006 { 7692 /* prefe */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips },
11007 { 7692 /* prefe */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_InMicroMips_HasEVA },
11008 { 7698 /* prefx */, 10 /* 1, 3 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
11009 { 7704 /* prepend */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
11010 { 7704 /* prepend */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
11011 { 7712 /* pul.ps */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
11012 { 7719 /* puu.ps */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
11013 { 7726 /* raddu.w.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11014 { 7726 /* raddu.w.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
11015 { 7737 /* rddsp */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11016 { 7737 /* rddsp */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
11017 { 7743 /* rdhwr */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
11018 { 7743 /* rdhwr */, 2 /* 1 */, MCK_HWRegsAsmReg, AMFBS_HasStdEnc_NotInMicroMips },
11019 { 7743 /* rdhwr */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
11020 { 7743 /* rdhwr */, 2 /* 1 */, MCK_HWRegsAsmReg, AMFBS_InMicroMips_NotMips32r6 },
11021 { 7743 /* rdhwr */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11022 { 7743 /* rdhwr */, 2 /* 1 */, MCK_HWRegsAsmReg, AMFBS_InMicroMips_HasMips32r6 },
11023 { 7743 /* rdhwr */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_IsGP64bit },
11024 { 7743 /* rdhwr */, 2 /* 1 */, MCK_HWRegsAsmReg, AMFBS_IsGP64bit },
11025 { 7743 /* rdhwr */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11026 { 7743 /* rdhwr */, 2 /* 1 */, MCK_HWRegsAsmReg, AMFBS_InMicroMips_HasMips32r6 },
11027 { 7743 /* rdhwr */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
11028 { 7743 /* rdhwr */, 2 /* 1 */, MCK_HWRegsAsmReg, AMFBS_HasStdEnc_NotInMicroMips },
11029 { 7743 /* rdhwr */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
11030 { 7743 /* rdhwr */, 2 /* 1 */, MCK_HWRegsAsmReg, AMFBS_InMicroMips_NotMips32r6 },
11031 { 7749 /* rdpgpr */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11032 { 7756 /* recip.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips },
11033 { 7756 /* recip.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat },
11034 { 7756 /* recip.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips },
11035 { 7756 /* recip.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat },
11036 { 7764 /* recip.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips },
11037 { 7764 /* recip.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat },
11038 { 7772 /* rem */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 },
11039 { 7772 /* rem */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 },
11040 { 7772 /* rem */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 },
11041 { 7772 /* rem */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 },
11042 { 7776 /* remu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 },
11043 { 7776 /* remu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 },
11044 { 7776 /* remu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 },
11045 { 7776 /* remu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 },
11046 { 7781 /* repl.ph */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11047 { 7781 /* repl.ph */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
11048 { 7789 /* repl.qb */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11049 { 7789 /* repl.qb */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
11050 { 7797 /* replv.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11051 { 7797 /* replv.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
11052 { 7806 /* replv.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11053 { 7806 /* replv.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
11054 { 7815 /* rint.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
11055 { 7815 /* rint.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11056 { 7822 /* rint.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
11057 { 7822 /* rint.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11058 { 7829 /* rol */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_None },
11059 { 7829 /* rol */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None },
11060 { 7829 /* rol */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_None },
11061 { 7829 /* rol */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_None },
11062 { 7833 /* ror */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_None },
11063 { 7833 /* ror */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None },
11064 { 7833 /* ror */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_None },
11065 { 7833 /* ror */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_None },
11066 { 7837 /* rotr */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips },
11067 { 7837 /* rotr */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11068 { 7837 /* rotr */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11069 { 7837 /* rotr */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips },
11070 { 7837 /* rotr */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11071 { 7842 /* rotrv */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips },
11072 { 7842 /* rotrv */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11073 { 7848 /* round.l.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips3_32_IsNotSoftFloat_NotInMicroMips },
11074 { 7848 /* round.l.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
11075 { 7858 /* round.l.s */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips },
11076 { 7858 /* round.l.s */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips },
11077 { 7858 /* round.l.s */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
11078 { 7858 /* round.l.s */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
11079 { 7868 /* round.w.d */, 2 /* 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips },
11080 { 7868 /* round.w.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips },
11081 { 7868 /* round.w.d */, 2 /* 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat },
11082 { 7868 /* round.w.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat },
11083 { 7868 /* round.w.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips },
11084 { 7868 /* round.w.d */, 2 /* 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips },
11085 { 7868 /* round.w.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
11086 { 7878 /* round.w.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotR5900_IsNotSoftFloat_NotInMicroMips },
11087 { 7878 /* round.w.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
11088 { 7878 /* round.w.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat },
11089 { 7888 /* rsqrt.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips },
11090 { 7888 /* rsqrt.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat },
11091 { 7888 /* rsqrt.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips },
11092 { 7888 /* rsqrt.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat },
11093 { 7896 /* rsqrt.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips },
11094 { 7896 /* rsqrt.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat },
11095 { 7904 /* s.d */, 1 /* 0 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat },
11096 { 7904 /* s.d */, 2 /* 1 */, MCK_MemOffsetSimm16_0, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat },
11097 { 7904 /* s.d */, 1 /* 0 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat },
11098 { 7904 /* s.d */, 2 /* 1 */, MCK_MemOffsetSimm16_0, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat },
11099 { 7904 /* s.d */, 1 /* 0 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat },
11100 { 7904 /* s.d */, 2 /* 1 */, MCK_MemOffsetSimm16_0, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat },
11101 { 7904 /* s.d */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat },
11102 { 7904 /* s.d */, 2 /* 1 */, MCK_MemOffsetSimm16_0, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat },
11103 { 7908 /* s.s */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips2_IsNotSoftFloat },
11104 { 7908 /* s.s */, 2 /* 1 */, MCK_MemOffsetSimm16_0, AMFBS_HasStdEnc_HasMips2_IsNotSoftFloat },
11105 { 7912 /* saa */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasCnMipsP },
11106 { 7912 /* saa */, 2 /* 1 */, MCK_Mem, AMFBS_HasCnMipsP },
11107 { 7912 /* saa */, 5 /* 0, 2 */, MCK_GPR64AsmReg, AMFBS_HasCnMipsP },
11108 { 7916 /* saad */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasCnMipsP },
11109 { 7916 /* saad */, 2 /* 1 */, MCK_Mem, AMFBS_HasCnMipsP },
11110 { 7916 /* saad */, 5 /* 0, 2 */, MCK_GPR64AsmReg, AMFBS_HasCnMipsP },
11111 { 7921 /* sat_s.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11112 { 7929 /* sat_s.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11113 { 7937 /* sat_s.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11114 { 7945 /* sat_s.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11115 { 7953 /* sat_u.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11116 { 7961 /* sat_u.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11117 { 7969 /* sat_u.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11118 { 7977 /* sat_u.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11119 { 7985 /* sb */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
11120 { 7985 /* sb */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_NotInMicroMips },
11121 { 7985 /* sb */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11122 { 7985 /* sb */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips_HasMips32r6 },
11123 { 7985 /* sb */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11124 { 7985 /* sb */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips },
11125 { 7988 /* sb16 */, 1 /* 0 */, MCK_GPRMM16AsmRegZero, AMFBS_InMicroMips_NotMips32r6 },
11126 { 7988 /* sb16 */, 2 /* 1 */, MCK_MicroMipsMem, AMFBS_InMicroMips_NotMips32r6 },
11127 { 7988 /* sb16 */, 1 /* 0 */, MCK_GPRMM16AsmRegZero, AMFBS_InMicroMips_HasMips32r6 },
11128 { 7988 /* sb16 */, 2 /* 1 */, MCK_MicroMipsMem, AMFBS_InMicroMips_HasMips32r6 },
11129 { 7993 /* sbe */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips },
11130 { 7993 /* sbe */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips },
11131 { 7993 /* sbe */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasEVA },
11132 { 7993 /* sbe */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_InMicroMips_HasEVA },
11133 { 7997 /* sc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsPTR64bit_HasMips64r6_NotInMicroMips },
11134 { 7997 /* sc */, 2 /* 1 */, MCK_MemOffsetSimmPtr, AMFBS_HasStdEnc_IsPTR64bit_HasMips64r6_NotInMicroMips },
11135 { 7997 /* sc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsPTR32bit_HasMips32r6_NotInMicroMips },
11136 { 7997 /* sc */, 2 /* 1 */, MCK_MemOffsetSimmPtr, AMFBS_HasStdEnc_IsPTR32bit_HasMips32r6_NotInMicroMips },
11137 { 7997 /* sc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11138 { 7997 /* sc */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_InMicroMips_HasMips32r6 },
11139 { 7997 /* sc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsPTR32bit_HasMips2_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips },
11140 { 7997 /* sc */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_IsPTR32bit_HasMips2_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips },
11141 { 7997 /* sc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsPTR64bit_HasMips2_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips },
11142 { 7997 /* sc */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_IsPTR64bit_HasMips2_NotMips32r6_NotMips64r6_NotR5900_NotInMicroMips },
11143 { 7997 /* sc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
11144 { 7997 /* sc */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips_NotMips32r6 },
11145 { 8000 /* scd */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips32r6 },
11146 { 8000 /* scd */, 2 /* 1 */, MCK_MemOffsetSimmPtr, AMFBS_HasStdEnc_HasMips32r6 },
11147 { 8000 /* scd */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900 },
11148 { 8000 /* scd */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotR5900 },
11149 { 8004 /* sce */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips },
11150 { 8004 /* sce */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips },
11151 { 8004 /* sce */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasEVA },
11152 { 8004 /* sce */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_InMicroMips_HasEVA },
11153 { 8008 /* sd */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips3 },
11154 { 8008 /* sd */, 2 /* 1 */, MCK_MemOffsetSimm16_0, AMFBS_HasStdEnc_NotMips3 },
11155 { 8008 /* sd */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
11156 { 8008 /* sd */, 2 /* 1 */, MCK_MemOffsetSimmPtr, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
11157 { 8025 /* sdc1 */, 1 /* 0 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips },
11158 { 8025 /* sdc1 */, 2 /* 1 */, MCK_MemOffsetSimm16_0, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips },
11159 { 8025 /* sdc1 */, 1 /* 0 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat },
11160 { 8025 /* sdc1 */, 2 /* 1 */, MCK_MemOffsetSimm16_0, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat },
11161 { 8025 /* sdc1 */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips },
11162 { 8025 /* sdc1 */, 2 /* 1 */, MCK_MemOffsetSimm16_0, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips },
11163 { 8025 /* sdc1 */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_HasMips32r6_IsNotSoftFloat },
11164 { 8025 /* sdc1 */, 2 /* 1 */, MCK_MemOffsetSimm16_0, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_HasMips32r6_IsNotSoftFloat },
11165 { 8025 /* sdc1 */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat },
11166 { 8025 /* sdc1 */, 2 /* 1 */, MCK_MemOffsetSimm16_0, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat },
11167 { 8030 /* sdc2 */, 1 /* 0 */, MCK_COP2AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
11168 { 8030 /* sdc2 */, 2 /* 1 */, MCK_MemOffsetSimm11_0, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
11169 { 8030 /* sdc2 */, 1 /* 0 */, MCK_COP2AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11170 { 8030 /* sdc2 */, 2 /* 1 */, MCK_MemOffsetSimm11_0, AMFBS_InMicroMips_HasMips32r6 },
11171 { 8030 /* sdc2 */, 1 /* 0 */, MCK_COP2AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips },
11172 { 8030 /* sdc2 */, 2 /* 1 */, MCK_MemOffsetSimm16_0, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips },
11173 { 8035 /* sdc3 */, 1 /* 0 */, MCK_COP3AsmReg, AMFBS_HasStdEnc_HasMips2_NotR5900_NotCnMips_NotInMicroMips },
11174 { 8035 /* sdc3 */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_HasMips2_NotR5900_NotCnMips_NotInMicroMips },
11175 { 8040 /* sdl */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 },
11176 { 8040 /* sdl */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 },
11177 { 8044 /* sdr */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 },
11178 { 8044 /* sdr */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 },
11179 { 8048 /* sdxc1 */, 1 /* 0 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
11180 { 8048 /* sdxc1 */, 10 /* 1, 3 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
11181 { 8048 /* sdxc1 */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat },
11182 { 8048 /* sdxc1 */, 10 /* 1, 3 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat },
11183 { 8054 /* seb */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips },
11184 { 8054 /* seb */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11185 { 8054 /* seb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips },
11186 { 8054 /* seb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11187 { 8058 /* seh */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips },
11188 { 8058 /* seh */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11189 { 8058 /* seh */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips },
11190 { 8058 /* seh */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11191 { 8062 /* sel.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
11192 { 8062 /* sel.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11193 { 8068 /* sel.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
11194 { 8068 /* sel.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11195 { 8074 /* seleqz */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsGP32bit_HasMips32r6_NotInMicroMips },
11196 { 8074 /* seleqz */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11197 { 8074 /* seleqz */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips32r6 },
11198 { 8081 /* seleqz.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
11199 { 8081 /* seleqz.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11200 { 8090 /* seleqz.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
11201 { 8090 /* seleqz.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11202 { 8099 /* selnez */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsGP32bit_HasMips32r6_NotInMicroMips },
11203 { 8099 /* selnez */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11204 { 8099 /* selnez */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips32r6 },
11205 { 8106 /* selnez.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
11206 { 8106 /* selnez.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11207 { 8115 /* selnez.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
11208 { 8115 /* selnez.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11209 { 8124 /* seq */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_NotCnMips },
11210 { 8124 /* seq */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_NotCnMips },
11211 { 8124 /* seq */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasCnMips },
11212 { 8124 /* seq */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_NotCnMips },
11213 { 8124 /* seq */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_NotCnMips },
11214 { 8124 /* seq */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasCnMips },
11215 { 8128 /* seqi */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasCnMips },
11216 { 8128 /* seqi */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasCnMips },
11217 { 8133 /* sge */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
11218 { 8133 /* sge */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_IsGP32bit_NotInMicroMips },
11219 { 8133 /* sge */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_IsGP64bit },
11220 { 8133 /* sge */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
11221 { 8133 /* sge */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_IsGP32bit_NotInMicroMips },
11222 { 8133 /* sge */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_IsGP64bit },
11223 { 8137 /* sgeu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
11224 { 8137 /* sgeu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_IsGP32bit_NotInMicroMips },
11225 { 8137 /* sgeu */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_IsGP64bit },
11226 { 8137 /* sgeu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
11227 { 8137 /* sgeu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_IsGP32bit_NotInMicroMips },
11228 { 8137 /* sgeu */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_IsGP64bit },
11229 { 8142 /* sgt */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
11230 { 8142 /* sgt */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11231 { 8142 /* sgt */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_IsGP32bit_NotInMicroMips },
11232 { 8142 /* sgt */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_IsGP64bit },
11233 { 8142 /* sgt */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
11234 { 8142 /* sgt */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11235 { 8142 /* sgt */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_IsGP32bit_NotInMicroMips },
11236 { 8142 /* sgt */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_IsGP64bit },
11237 { 8146 /* sgtu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
11238 { 8146 /* sgtu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11239 { 8146 /* sgtu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_IsGP32bit_NotInMicroMips },
11240 { 8146 /* sgtu */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_IsGP64bit },
11241 { 8146 /* sgtu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
11242 { 8146 /* sgtu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11243 { 8146 /* sgtu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_IsGP32bit_NotInMicroMips },
11244 { 8146 /* sgtu */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_IsGP64bit },
11245 { 8151 /* sh */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
11246 { 8151 /* sh */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_NotInMicroMips },
11247 { 8151 /* sh */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11248 { 8151 /* sh */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips_HasMips32r6 },
11249 { 8151 /* sh */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11250 { 8151 /* sh */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips },
11251 { 8154 /* sh16 */, 1 /* 0 */, MCK_GPRMM16AsmRegZero, AMFBS_InMicroMips_NotMips32r6 },
11252 { 8154 /* sh16 */, 2 /* 1 */, MCK_MicroMipsMem, AMFBS_InMicroMips_NotMips32r6 },
11253 { 8154 /* sh16 */, 1 /* 0 */, MCK_GPRMM16AsmRegZero, AMFBS_InMicroMips_HasMips32r6 },
11254 { 8154 /* sh16 */, 2 /* 1 */, MCK_MicroMipsMem, AMFBS_InMicroMips_HasMips32r6 },
11255 { 8159 /* she */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips },
11256 { 8159 /* she */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips },
11257 { 8159 /* she */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasEVA },
11258 { 8159 /* she */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_InMicroMips_HasEVA },
11259 { 8163 /* shf.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11260 { 8169 /* shf.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11261 { 8175 /* shf.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11262 { 8181 /* shilo */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
11263 { 8181 /* shilo */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
11264 { 8187 /* shilov */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
11265 { 8187 /* shilov */, 2 /* 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11266 { 8187 /* shilov */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
11267 { 8187 /* shilov */, 2 /* 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
11268 { 8194 /* shll.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11269 { 8194 /* shll.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
11270 { 8202 /* shll.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11271 { 8202 /* shll.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
11272 { 8210 /* shll_s.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11273 { 8210 /* shll_s.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
11274 { 8220 /* shll_s.w */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11275 { 8220 /* shll_s.w */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
11276 { 8229 /* shllv.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11277 { 8229 /* shllv.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
11278 { 8238 /* shllv.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11279 { 8238 /* shllv.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
11280 { 8247 /* shllv_s.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11281 { 8247 /* shllv_s.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
11282 { 8258 /* shllv_s.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11283 { 8258 /* shllv_s.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
11284 { 8268 /* shra.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11285 { 8268 /* shra.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
11286 { 8276 /* shra.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
11287 { 8276 /* shra.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
11288 { 8284 /* shra_r.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11289 { 8284 /* shra_r.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
11290 { 8294 /* shra_r.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
11291 { 8294 /* shra_r.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
11292 { 8304 /* shra_r.w */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11293 { 8304 /* shra_r.w */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
11294 { 8313 /* shrav.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11295 { 8313 /* shrav.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
11296 { 8322 /* shrav.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
11297 { 8322 /* shrav.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
11298 { 8331 /* shrav_r.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11299 { 8331 /* shrav_r.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
11300 { 8342 /* shrav_r.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
11301 { 8342 /* shrav_r.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
11302 { 8353 /* shrav_r.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11303 { 8353 /* shrav_r.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
11304 { 8363 /* shrl.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
11305 { 8363 /* shrl.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
11306 { 8371 /* shrl.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11307 { 8371 /* shrl.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
11308 { 8379 /* shrlv.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
11309 { 8379 /* shrlv.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
11310 { 8388 /* shrlv.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11311 { 8388 /* shrlv.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
11312 { 8404 /* sld.b */, 8 /* 3 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA },
11313 { 8404 /* sld.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11314 { 8410 /* sld.d */, 8 /* 3 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA },
11315 { 8410 /* sld.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11316 { 8416 /* sld.h */, 8 /* 3 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA },
11317 { 8416 /* sld.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11318 { 8422 /* sld.w */, 8 /* 3 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA },
11319 { 8422 /* sld.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11320 { 8428 /* sldi.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11321 { 8435 /* sldi.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11322 { 8442 /* sldi.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11323 { 8449 /* sldi.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11324 { 8456 /* sle */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
11325 { 8456 /* sle */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_IsGP32bit_NotInMicroMips },
11326 { 8456 /* sle */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_IsGP64bit },
11327 { 8456 /* sle */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
11328 { 8456 /* sle */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_IsGP32bit_NotInMicroMips },
11329 { 8456 /* sle */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_IsGP64bit },
11330 { 8460 /* sleu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
11331 { 8460 /* sleu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_IsGP32bit_NotInMicroMips },
11332 { 8460 /* sleu */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_IsGP64bit },
11333 { 8460 /* sleu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
11334 { 8460 /* sleu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_IsGP32bit_NotInMicroMips },
11335 { 8460 /* sleu */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_IsGP64bit },
11336 { 8465 /* sll */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_NotInMicroMips },
11337 { 8465 /* sll */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11338 { 8465 /* sll */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
11339 { 8465 /* sll */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11340 { 8465 /* sll */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11341 { 8465 /* sll */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11342 { 8465 /* sll */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_NotInMicroMips },
11343 { 8465 /* sll */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11344 { 8465 /* sll */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
11345 { 8465 /* sll */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11346 { 8465 /* sll */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11347 { 8469 /* sll.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11348 { 8475 /* sll.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11349 { 8481 /* sll.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11350 { 8487 /* sll.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11351 { 8493 /* sll16 */, 3 /* 0, 1 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_NotMips32r6 },
11352 { 8493 /* sll16 */, 3 /* 0, 1 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11353 { 8499 /* slli.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11354 { 8506 /* slli.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11355 { 8513 /* slli.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11356 { 8520 /* slli.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11357 { 8527 /* sllv */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
11358 { 8527 /* sllv */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11359 { 8532 /* slt */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips },
11360 { 8532 /* slt */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11361 { 8532 /* slt */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_IsGP64bit },
11362 { 8532 /* slt */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
11363 { 8532 /* slt */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11364 { 8532 /* slt */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips },
11365 { 8532 /* slt */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11366 { 8532 /* slt */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_IsGP64bit },
11367 { 8536 /* slti */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
11368 { 8536 /* slti */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11369 { 8541 /* sltiu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
11370 { 8541 /* sltiu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11371 { 8547 /* sltu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips },
11372 { 8547 /* sltu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11373 { 8547 /* sltu */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_IsGP64bit },
11374 { 8547 /* sltu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
11375 { 8547 /* sltu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11376 { 8547 /* sltu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips },
11377 { 8547 /* sltu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11378 { 8547 /* sltu */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_IsGP64bit },
11379 { 8552 /* sne */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_NotCnMips },
11380 { 8552 /* sne */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_NotCnMips },
11381 { 8552 /* sne */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasCnMips },
11382 { 8552 /* sne */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_NotCnMips },
11383 { 8552 /* sne */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_NotCnMips },
11384 { 8552 /* sne */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasCnMips },
11385 { 8556 /* snei */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasCnMips },
11386 { 8556 /* snei */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasCnMips },
11387 { 8561 /* splat.b */, 8 /* 3 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA },
11388 { 8561 /* splat.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11389 { 8569 /* splat.d */, 8 /* 3 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA },
11390 { 8569 /* splat.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11391 { 8577 /* splat.h */, 8 /* 3 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA },
11392 { 8577 /* splat.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11393 { 8585 /* splat.w */, 8 /* 3 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA },
11394 { 8585 /* splat.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11395 { 8593 /* splati.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11396 { 8602 /* splati.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11397 { 8611 /* splati.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11398 { 8620 /* splati.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11399 { 8629 /* sqrt.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips },
11400 { 8629 /* sqrt.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat },
11401 { 8629 /* sqrt.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips },
11402 { 8629 /* sqrt.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat },
11403 { 8636 /* sqrt.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips2_IsNotSoftFloat_NotInMicroMips },
11404 { 8636 /* sqrt.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat },
11405 { 8643 /* sra */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_NotInMicroMips },
11406 { 8643 /* sra */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11407 { 8643 /* sra */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
11408 { 8643 /* sra */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11409 { 8643 /* sra */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11410 { 8643 /* sra */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_NotInMicroMips },
11411 { 8643 /* sra */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11412 { 8643 /* sra */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
11413 { 8643 /* sra */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11414 { 8647 /* sra.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11415 { 8653 /* sra.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11416 { 8659 /* sra.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11417 { 8665 /* sra.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11418 { 8671 /* srai.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11419 { 8678 /* srai.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11420 { 8685 /* srai.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11421 { 8692 /* srai.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11422 { 8699 /* srar.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11423 { 8706 /* srar.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11424 { 8713 /* srar.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11425 { 8720 /* srar.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11426 { 8727 /* srari.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11427 { 8735 /* srari.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11428 { 8743 /* srari.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11429 { 8751 /* srari.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11430 { 8759 /* srav */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
11431 { 8759 /* srav */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11432 { 8764 /* srl */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_NotInMicroMips },
11433 { 8764 /* srl */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11434 { 8764 /* srl */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
11435 { 8764 /* srl */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11436 { 8764 /* srl */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11437 { 8764 /* srl */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_NotInMicroMips },
11438 { 8764 /* srl */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11439 { 8764 /* srl */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
11440 { 8764 /* srl */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11441 { 8768 /* srl.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11442 { 8774 /* srl.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11443 { 8780 /* srl.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11444 { 8786 /* srl.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11445 { 8792 /* srl16 */, 3 /* 0, 1 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_NotMips32r6 },
11446 { 8792 /* srl16 */, 3 /* 0, 1 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11447 { 8798 /* srli.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11448 { 8805 /* srli.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11449 { 8812 /* srli.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11450 { 8819 /* srli.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11451 { 8826 /* srlr.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11452 { 8833 /* srlr.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11453 { 8840 /* srlr.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11454 { 8847 /* srlr.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11455 { 8854 /* srlri.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11456 { 8862 /* srlri.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11457 { 8870 /* srlri.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11458 { 8878 /* srlri.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11459 { 8886 /* srlv */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
11460 { 8886 /* srlv */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11461 { 8897 /* st.b */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11462 { 8897 /* st.b */, 2 /* 1 */, MCK_MemOffsetSimm10_0, AMFBS_HasStdEnc_HasMSA },
11463 { 8902 /* st.d */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11464 { 8902 /* st.d */, 2 /* 1 */, MCK_MemOffsetSimm10_3, AMFBS_HasStdEnc_HasMSA },
11465 { 8907 /* st.h */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11466 { 8907 /* st.h */, 2 /* 1 */, MCK_MemOffsetSimm10_1, AMFBS_HasStdEnc_HasMSA },
11467 { 8912 /* st.w */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11468 { 8912 /* st.w */, 2 /* 1 */, MCK_MemOffsetSimm10_2, AMFBS_HasStdEnc_HasMSA },
11469 { 8917 /* sub */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
11470 { 8917 /* sub */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
11471 { 8917 /* sub */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11472 { 8917 /* sub */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 },
11473 { 8917 /* sub */, 2 /* 1 */, MCK_InvNum, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 },
11474 { 8917 /* sub */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
11475 { 8917 /* sub */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
11476 { 8917 /* sub */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11477 { 8917 /* sub */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 },
11478 { 8917 /* sub */, 4 /* 2 */, MCK_InvNum, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 },
11479 { 8921 /* sub.d */, 7 /* 0, 1, 2 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips },
11480 { 8921 /* sub.d */, 7 /* 0, 1, 2 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat },
11481 { 8921 /* sub.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips },
11482 { 8921 /* sub.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat },
11483 { 8927 /* sub.ps */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
11484 { 8934 /* sub.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips },
11485 { 8934 /* sub.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
11486 { 8934 /* sub.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat },
11487 { 8940 /* subq.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11488 { 8940 /* subq.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
11489 { 8948 /* subq_s.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11490 { 8948 /* subq_s.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
11491 { 8958 /* subq_s.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11492 { 8958 /* subq_s.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
11493 { 8967 /* subqh.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
11494 { 8967 /* subqh.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
11495 { 8976 /* subqh.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
11496 { 8976 /* subqh.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
11497 { 8984 /* subqh_r.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
11498 { 8984 /* subqh_r.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
11499 { 8995 /* subqh_r.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
11500 { 8995 /* subqh_r.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
11501 { 9005 /* subs_s.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11502 { 9014 /* subs_s.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11503 { 9023 /* subs_s.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11504 { 9032 /* subs_s.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11505 { 9041 /* subs_u.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11506 { 9050 /* subs_u.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11507 { 9059 /* subs_u.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11508 { 9068 /* subs_u.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11509 { 9077 /* subsus_u.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11510 { 9088 /* subsus_u.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11511 { 9099 /* subsus_u.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11512 { 9110 /* subsus_u.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11513 { 9121 /* subsuu_s.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11514 { 9132 /* subsuu_s.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11515 { 9143 /* subsuu_s.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11516 { 9154 /* subsuu_s.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11517 { 9165 /* subu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11518 { 9165 /* subu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
11519 { 9165 /* subu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
11520 { 9165 /* subu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None },
11521 { 9165 /* subu */, 2 /* 1 */, MCK_InvNum, AMFBS_None },
11522 { 9165 /* subu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11523 { 9165 /* subu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
11524 { 9165 /* subu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
11525 { 9165 /* subu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_None },
11526 { 9165 /* subu */, 4 /* 2 */, MCK_InvNum, AMFBS_None },
11527 { 9170 /* subu.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
11528 { 9170 /* subu.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
11529 { 9178 /* subu.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11530 { 9178 /* subu.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
11531 { 9186 /* subu16 */, 7 /* 0, 1, 2 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_NotMips32r6 },
11532 { 9186 /* subu16 */, 7 /* 0, 1, 2 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11533 { 9193 /* subu_s.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
11534 { 9193 /* subu_s.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
11535 { 9203 /* subu_s.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11536 { 9203 /* subu_s.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
11537 { 9213 /* subuh.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
11538 { 9213 /* subuh.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
11539 { 9222 /* subuh_r.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
11540 { 9222 /* subuh_r.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
11541 { 9233 /* subv.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11542 { 9240 /* subv.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11543 { 9247 /* subv.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11544 { 9254 /* subv.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11545 { 9261 /* subvi.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11546 { 9269 /* subvi.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11547 { 9277 /* subvi.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11548 { 9285 /* subvi.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11549 { 9293 /* suxc1 */, 1 /* 0 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
11550 { 9293 /* suxc1 */, 10 /* 1, 3 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
11551 { 9293 /* suxc1 */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
11552 { 9293 /* suxc1 */, 10 /* 1, 3 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
11553 { 9293 /* suxc1 */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
11554 { 9293 /* suxc1 */, 10 /* 1, 3 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_NotMips32r6_IsNotSoftFloat },
11555 { 9299 /* sw */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11556 { 9299 /* sw */, 2 /* 1 */, MCK_MicroMipsMemSP, AMFBS_InMicroMips_HasMips32r6 },
11557 { 9299 /* sw */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11558 { 9299 /* sw */, 2 /* 1 */, MCK_MicroMipsMemSP, AMFBS_InMicroMips },
11559 { 9299 /* sw */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
11560 { 9299 /* sw */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_NotInMicroMips },
11561 { 9299 /* sw */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_NotInMips16Mode_HasDSP },
11562 { 9299 /* sw */, 2 /* 1 */, MCK_Mem, AMFBS_NotInMips16Mode_HasDSP },
11563 { 9299 /* sw */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11564 { 9299 /* sw */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips_HasDSP },
11565 { 9299 /* sw */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11566 { 9299 /* sw */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips_HasMips32r6 },
11567 { 9299 /* sw */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11568 { 9299 /* sw */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips },
11569 { 9302 /* sw16 */, 1 /* 0 */, MCK_GPRMM16AsmRegZero, AMFBS_InMicroMips_NotMips32r6 },
11570 { 9302 /* sw16 */, 2 /* 1 */, MCK_MicroMipsMem, AMFBS_InMicroMips_NotMips32r6 },
11571 { 9302 /* sw16 */, 1 /* 0 */, MCK_GPRMM16AsmRegZero, AMFBS_InMicroMips_HasMips32r6 },
11572 { 9302 /* sw16 */, 2 /* 1 */, MCK_MicroMipsMem, AMFBS_InMicroMips_HasMips32r6 },
11573 { 9307 /* swc1 */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips },
11574 { 9307 /* swc1 */, 2 /* 1 */, MCK_MemOffsetSimm16_0, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips },
11575 { 9307 /* swc1 */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat },
11576 { 9307 /* swc1 */, 2 /* 1 */, MCK_MemOffsetSimm16_0, AMFBS_InMicroMips_IsNotSoftFloat },
11577 { 9312 /* swc2 */, 1 /* 0 */, MCK_COP2AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
11578 { 9312 /* swc2 */, 2 /* 1 */, MCK_MemOffsetSimm11_0, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
11579 { 9312 /* swc2 */, 1 /* 0 */, MCK_COP2AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11580 { 9312 /* swc2 */, 2 /* 1 */, MCK_MemOffsetSimm11_0, AMFBS_InMicroMips_HasMips32r6 },
11581 { 9312 /* swc2 */, 1 /* 0 */, MCK_COP2AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips },
11582 { 9312 /* swc2 */, 2 /* 1 */, MCK_MemOffsetSimm16_0, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips },
11583 { 9317 /* swc3 */, 1 /* 0 */, MCK_COP3AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_NotCnMips_NotInMicroMips },
11584 { 9317 /* swc3 */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotR5900_NotCnMips_NotInMicroMips },
11585 { 9322 /* swe */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips },
11586 { 9322 /* swe */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips },
11587 { 9322 /* swe */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasEVA },
11588 { 9322 /* swe */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_InMicroMips_HasEVA },
11589 { 9326 /* swl */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips },
11590 { 9326 /* swl */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips },
11591 { 9326 /* swl */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
11592 { 9326 /* swl */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips_NotMips32r6 },
11593 { 9330 /* swle */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips },
11594 { 9330 /* swle */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips },
11595 { 9330 /* swle */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6_HasEVA },
11596 { 9330 /* swle */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_InMicroMips_NotMips32r6_HasEVA },
11597 { 9335 /* swm */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips },
11598 { 9335 /* swm */, 1 /* 0 */, MCK_RegList, AMFBS_InMicroMips },
11599 { 9339 /* swm16 */, 2 /* 1 */, MCK_MemOffsetUimm4, AMFBS_InMicroMips_NotMips32r6 },
11600 { 9339 /* swm16 */, 1 /* 0 */, MCK_RegList16, AMFBS_InMicroMips_NotMips32r6 },
11601 { 9339 /* swm16 */, 2 /* 1 */, MCK_MemOffsetUimm4, AMFBS_InMicroMips_HasMips32r6 },
11602 { 9339 /* swm16 */, 1 /* 0 */, MCK_RegList16, AMFBS_InMicroMips_HasMips32r6 },
11603 { 9345 /* swm32 */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips },
11604 { 9345 /* swm32 */, 1 /* 0 */, MCK_RegList, AMFBS_InMicroMips },
11605 { 9351 /* swp */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11606 { 9351 /* swp */, 2 /* 1 */, MCK_MemOffsetSimm12_0, AMFBS_InMicroMips },
11607 { 9355 /* swr */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips },
11608 { 9355 /* swr */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips },
11609 { 9355 /* swr */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
11610 { 9355 /* swr */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips_NotMips32r6 },
11611 { 9359 /* swre */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips },
11612 { 9359 /* swre */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips },
11613 { 9359 /* swre */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6_HasEVA },
11614 { 9359 /* swre */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_InMicroMips_NotMips32r6_HasEVA },
11615 { 9364 /* swsp */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
11616 { 9364 /* swsp */, 2 /* 1 */, MCK_MicroMipsMemSP, AMFBS_InMicroMips_NotMips32r6 },
11617 { 9369 /* swxc1 */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat },
11618 { 9369 /* swxc1 */, 10 /* 1, 3 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat },
11619 { 9369 /* swxc1 */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
11620 { 9369 /* swxc1 */, 10 /* 1, 3 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
11621 { 9432 /* synci */, 1 /* 0 */, MCK_MemOffsetSimm16_0, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips },
11622 { 9432 /* synci */, 1 /* 0 */, MCK_MemOffsetSimm16_0, AMFBS_InMicroMips_NotMips32r6 },
11623 { 9432 /* synci */, 1 /* 0 */, MCK_MemOffsetSimm16_0, AMFBS_InMicroMips_HasMips32r6 },
11624 { 9476 /* teq */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotInMicroMips },
11625 { 9476 /* teq */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11626 { 9476 /* teq */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11627 { 9476 /* teq */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotInMicroMips },
11628 { 9480 /* teqi */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips },
11629 { 9480 /* teqi */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
11630 { 9485 /* tge */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotInMicroMips },
11631 { 9485 /* tge */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11632 { 9485 /* tge */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11633 { 9485 /* tge */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotInMicroMips },
11634 { 9489 /* tgei */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips },
11635 { 9489 /* tgei */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
11636 { 9494 /* tgeiu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips },
11637 { 9494 /* tgeiu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
11638 { 9500 /* tgeu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotInMicroMips },
11639 { 9500 /* tgeu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11640 { 9500 /* tgeu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11641 { 9500 /* tgeu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotInMicroMips },
11642 { 9585 /* tlt */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotInMicroMips },
11643 { 9585 /* tlt */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11644 { 9585 /* tlt */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11645 { 9585 /* tlt */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotInMicroMips },
11646 { 9589 /* tlti */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips },
11647 { 9589 /* tlti */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
11648 { 9594 /* tltiu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips },
11649 { 9594 /* tltiu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
11650 { 9600 /* tltu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotInMicroMips },
11651 { 9600 /* tltu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11652 { 9600 /* tltu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11653 { 9600 /* tltu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotInMicroMips },
11654 { 9605 /* tne */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotInMicroMips },
11655 { 9605 /* tne */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11656 { 9605 /* tne */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11657 { 9605 /* tne */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotInMicroMips },
11658 { 9609 /* tnei */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips },
11659 { 9609 /* tnei */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
11660 { 9614 /* trunc.l.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips3_32_IsNotSoftFloat_NotInMicroMips },
11661 { 9614 /* trunc.l.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
11662 { 9624 /* trunc.l.s */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips },
11663 { 9624 /* trunc.l.s */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips },
11664 { 9624 /* trunc.l.s */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
11665 { 9624 /* trunc.l.s */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
11666 { 9634 /* trunc.w.d */, 2 /* 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips },
11667 { 9634 /* trunc.w.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips },
11668 { 9634 /* trunc.w.d */, 2 /* 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat },
11669 { 9634 /* trunc.w.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat },
11670 { 9634 /* trunc.w.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips },
11671 { 9634 /* trunc.w.d */, 2 /* 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_HasMips2_IsNotSoftFloat_NotInMicroMips },
11672 { 9634 /* trunc.w.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
11673 { 9634 /* trunc.w.d */, 2 /* 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
11674 { 9634 /* trunc.w.d */, 2 /* 1 */, MCK_AFGR64AsmReg, AMFBS_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat },
11675 { 9634 /* trunc.w.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat },
11676 { 9634 /* trunc.w.d */, 4 /* 2 */, MCK_GPR32AsmReg, AMFBS_NotFP64bit_IsNotSingleFloat_IsNotSoftFloat },
11677 { 9634 /* trunc.w.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat },
11678 { 9634 /* trunc.w.d */, 2 /* 1 */, MCK_FGR64AsmReg, AMFBS_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat },
11679 { 9634 /* trunc.w.d */, 4 /* 2 */, MCK_GPR32AsmReg, AMFBS_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat },
11680 { 9644 /* trunc.w.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotR5900_IsNotSoftFloat_NotInMicroMips },
11681 { 9644 /* trunc.w.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
11682 { 9644 /* trunc.w.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat },
11683 { 9644 /* trunc.w.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_None },
11684 { 9644 /* trunc.w.s */, 4 /* 2 */, MCK_GPR32AsmReg, AMFBS_None },
11685 { 9654 /* ulh */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None },
11686 { 9654 /* ulh */, 2 /* 1 */, MCK_Mem, AMFBS_None },
11687 { 9658 /* ulhu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None },
11688 { 9658 /* ulhu */, 2 /* 1 */, MCK_Mem, AMFBS_None },
11689 { 9663 /* ulw */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None },
11690 { 9663 /* ulw */, 2 /* 1 */, MCK_Mem, AMFBS_None },
11691 { 9667 /* ush */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None },
11692 { 9667 /* ush */, 2 /* 1 */, MCK_Mem, AMFBS_None },
11693 { 9671 /* usw */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None },
11694 { 9671 /* usw */, 2 /* 1 */, MCK_Mem, AMFBS_None },
11695 { 9675 /* v3mulu */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasCnMips },
11696 { 9675 /* v3mulu */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasCnMips },
11697 { 9682 /* vmm0 */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasCnMips },
11698 { 9682 /* vmm0 */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasCnMips },
11699 { 9687 /* vmulu */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasCnMips },
11700 { 9687 /* vmulu */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasCnMips },
11701 { 9693 /* vshf.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11702 { 9700 /* vshf.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11703 { 9707 /* vshf.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11704 { 9714 /* vshf.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11705 { 9726 /* wrdsp */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasDSP_NotInMicroMips },
11706 { 9726 /* wrdsp */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasDSP_InMicroMips },
11707 { 9726 /* wrdsp */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11708 { 9726 /* wrdsp */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasDSP_NotInMicroMips },
11709 { 9732 /* wrpgpr */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11710 { 9739 /* wsbh */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips },
11711 { 9739 /* wsbh */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11712 { 9739 /* wsbh */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11713 { 9744 /* xor */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
11714 { 9744 /* xor */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
11715 { 9744 /* xor */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11716 { 9744 /* xor */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11717 { 9744 /* xor */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips },
11718 { 9744 /* xor */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11719 { 9744 /* xor */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips3_NotInMicroMips },
11720 { 9744 /* xor */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
11721 { 9744 /* xor */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
11722 { 9744 /* xor */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11723 { 9744 /* xor */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11724 { 9744 /* xor */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips },
11725 { 9744 /* xor */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11726 { 9744 /* xor */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips3_NotInMicroMips },
11727 { 9748 /* xor.v */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11728 { 9754 /* xor16 */, 3 /* 0, 1 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_NotMips32r6 },
11729 { 9754 /* xor16 */, 3 /* 0, 1 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11730 { 9760 /* xori */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11731 { 9760 /* xori */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
11732 { 9760 /* xori */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
11733 { 9760 /* xori */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11734 { 9760 /* xori */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
11735 { 9760 /* xori */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
11736 { 9765 /* xori.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11737 { 9772 /* yield */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT_NotInMicroMips },
11738 { 9772 /* yield */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMT_NotInMicroMips },
11739};
11740
11741ParseStatus MipsAsmParser::
11742tryCustomParseOperand(OperandVector &Operands,
11743 unsigned MCK) {
11744
11745 switch(MCK) {
11746 case MCK_ACC64DSPAsmReg:
11747 return parseAnyRegister(Operands);
11748 case MCK_AFGR64AsmReg:
11749 return parseAnyRegister(Operands);
11750 case MCK_CCRAsmReg:
11751 return parseAnyRegister(Operands);
11752 case MCK_COP0AsmReg:
11753 return parseAnyRegister(Operands);
11754 case MCK_COP2AsmReg:
11755 return parseAnyRegister(Operands);
11756 case MCK_COP3AsmReg:
11757 return parseAnyRegister(Operands);
11758 case MCK_FCCAsmReg:
11759 return parseAnyRegister(Operands);
11760 case MCK_FGR32AsmReg:
11761 return parseAnyRegister(Operands);
11762 case MCK_FGR64AsmReg:
11763 return parseAnyRegister(Operands);
11764 case MCK_GPR32AsmReg:
11765 return parseAnyRegister(Operands);
11766 case MCK_GPR32NonZeroAsmReg:
11767 return parseAnyRegister(Operands);
11768 case MCK_GPR32ZeroAsmReg:
11769 return parseAnyRegister(Operands);
11770 case MCK_GPR64AsmReg:
11771 return parseAnyRegister(Operands);
11772 case MCK_GPRMM16AsmReg:
11773 return parseAnyRegister(Operands);
11774 case MCK_GPRMM16AsmRegMoveP:
11775 return parseAnyRegister(Operands);
11776 case MCK_GPRMM16AsmRegMovePPairFirst:
11777 return parseAnyRegister(Operands);
11778 case MCK_GPRMM16AsmRegMovePPairSecond:
11779 return parseAnyRegister(Operands);
11780 case MCK_GPRMM16AsmRegZero:
11781 return parseAnyRegister(Operands);
11782 case MCK_HI32DSPAsmReg:
11783 return parseAnyRegister(Operands);
11784 case MCK_HWRegsAsmReg:
11785 return parseAnyRegister(Operands);
11786 case MCK_LO32DSPAsmReg:
11787 return parseAnyRegister(Operands);
11788 case MCK_MSA128AsmReg:
11789 return parseAnyRegister(Operands);
11790 case MCK_MSACtrlAsmReg:
11791 return parseAnyRegister(Operands);
11792 case MCK_MicroMipsMemGP:
11793 return parseMemOperand(Operands);
11794 case MCK_MicroMipsMem:
11795 return parseMemOperand(Operands);
11796 case MCK_MicroMipsMemSP:
11797 return parseMemOperand(Operands);
11798 case MCK_InvNum:
11799 return parseInvNum(Operands);
11800 case MCK_JumpTarget:
11801 return parseJumpTarget(Operands);
11802 case MCK_MemOffsetSimmPtr:
11803 return parseMemOperand(Operands);
11804 case MCK_MemOffsetUimm4:
11805 return parseMemOperand(Operands);
11806 case MCK_MemOffsetSimm9_0:
11807 return parseMemOperand(Operands);
11808 case MCK_MemOffsetSimm10_0:
11809 return parseMemOperand(Operands);
11810 case MCK_MemOffsetSimm11_0:
11811 return parseMemOperand(Operands);
11812 case MCK_MemOffsetSimm12_0:
11813 return parseMemOperand(Operands);
11814 case MCK_MemOffsetSimm16_0:
11815 return parseMemOperand(Operands);
11816 case MCK_MemOffsetSimm10_1:
11817 return parseMemOperand(Operands);
11818 case MCK_MemOffsetSimm10_2:
11819 return parseMemOperand(Operands);
11820 case MCK_MemOffsetSimm10_3:
11821 return parseMemOperand(Operands);
11822 case MCK_Mem:
11823 return parseMemOperand(Operands);
11824 case MCK_RegList16:
11825 return parseRegisterList(Operands);
11826 case MCK_RegList:
11827 return parseRegisterList(Operands);
11828 case MCK_StrictlyAFGR64AsmReg:
11829 return parseAnyRegister(Operands);
11830 case MCK_StrictlyFGR32AsmReg:
11831 return parseAnyRegister(Operands);
11832 case MCK_StrictlyFGR64AsmReg:
11833 return parseAnyRegister(Operands);
11834 default:
11835 return ParseStatus::NoMatch;
11836 }
11837 return ParseStatus::NoMatch;
11838}
11839
11840ParseStatus MipsAsmParser::
11841MatchOperandParserImpl(OperandVector &Operands,
11842 StringRef Mnemonic,
11843 bool ParseForAllFeatures) {
11844 // Get the current feature set.
11845 const FeatureBitset &AvailableFeatures = getAvailableFeatures();
11846
11847 // Get the next operand index.
11848 unsigned NextOpNum = Operands.size() - 1;
11849 // Search the table.
11850 auto MnemonicRange =
11851 std::equal_range(std::begin(OperandMatchTable), std::end(OperandMatchTable),
11852 Mnemonic, LessOpcodeOperand());
11853
11854 if (MnemonicRange.first == MnemonicRange.second)
11855 return ParseStatus::NoMatch;
11856
11857 for (const OperandMatchEntry *it = MnemonicRange.first,
11858 *ie = MnemonicRange.second; it != ie; ++it) {
11859 // equal_range guarantees that instruction mnemonic matches.
11860 assert(Mnemonic == it->getMnemonic());
11861
11862 // check if the available features match
11863 const FeatureBitset &RequiredFeatures = FeatureBitsets[it->RequiredFeaturesIdx];
11864 if (!ParseForAllFeatures && (AvailableFeatures & RequiredFeatures) != RequiredFeatures)
11865 continue;
11866
11867 // check if the operand in question has a custom parser.
11868 if (!(it->OperandMask & (1 << NextOpNum)))
11869 continue;
11870
11871 // call custom parse method to handle the operand
11872 ParseStatus Result = tryCustomParseOperand(Operands, it->Class);
11873 if (!Result.isNoMatch())
11874 return Result;
11875 }
11876
11877 // Okay, we had no match.
11878 return ParseStatus::NoMatch;
11879}
11880
11881#endif // GET_MATCHER_IMPLEMENTATION
11882
11883
11884#ifdef GET_MNEMONIC_SPELL_CHECKER
11885#undef GET_MNEMONIC_SPELL_CHECKER
11886
11887static std::string MipsMnemonicSpellCheck(StringRef S, const FeatureBitset &FBS, unsigned VariantID) {
11888 const unsigned MaxEditDist = 2;
11889 std::vector<StringRef> Candidates;
11890 StringRef Prev = "";
11891
11892 // Find the appropriate table for this asm variant.
11893 const MatchEntry *Start, *End;
11894 switch (VariantID) {
11895 default: llvm_unreachable("invalid variant!");
11896 case 0: Start = std::begin(MatchTable0); End = std::end(MatchTable0); break;
11897 }
11898
11899 for (auto I = Start; I < End; I++) {
11900 // Ignore unsupported instructions.
11901 const FeatureBitset &RequiredFeatures = FeatureBitsets[I->RequiredFeaturesIdx];
11902 if ((FBS & RequiredFeatures) != RequiredFeatures)
11903 continue;
11904
11905 StringRef T = I->getMnemonic();
11906 // Avoid recomputing the edit distance for the same string.
11907 if (T == Prev)
11908 continue;
11909
11910 Prev = T;
11911 unsigned Dist = S.edit_distance(T, false, MaxEditDist);
11912 if (Dist <= MaxEditDist)
11913 Candidates.push_back(T);
11914 }
11915
11916 if (Candidates.empty())
11917 return "";
11918
11919 std::string Res = ", did you mean: ";
11920 unsigned i = 0;
11921 for (; i < Candidates.size() - 1; i++)
11922 Res += Candidates[i].str() + ", ";
11923 return Res + Candidates[i].str() + "?";
11924}
11925
11926#endif // GET_MNEMONIC_SPELL_CHECKER
11927
11928
11929#ifdef GET_MNEMONIC_CHECKER
11930#undef GET_MNEMONIC_CHECKER
11931
11932static bool MipsCheckMnemonic(StringRef Mnemonic,
11933 const FeatureBitset &AvailableFeatures,
11934 unsigned VariantID) {
11935 // Find the appropriate table for this asm variant.
11936 const MatchEntry *Start, *End;
11937 switch (VariantID) {
11938 default: llvm_unreachable("invalid variant!");
11939 case 0: Start = std::begin(MatchTable0); End = std::end(MatchTable0); break;
11940 }
11941
11942 // Search the table.
11943 auto MnemonicRange = std::equal_range(Start, End, Mnemonic, LessOpcode());
11944
11945 if (MnemonicRange.first == MnemonicRange.second)
11946 return false;
11947
11948 for (const MatchEntry *it = MnemonicRange.first, *ie = MnemonicRange.second;
11949 it != ie; ++it) {
11950 const FeatureBitset &RequiredFeatures =
11951 FeatureBitsets[it->RequiredFeaturesIdx];
11952 if ((AvailableFeatures & RequiredFeatures) == RequiredFeatures)
11953 return true;
11954 }
11955 return false;
11956}
11957
11958#endif // GET_MNEMONIC_CHECKER
11959
11960