1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Register Bank Source Fragments *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_REGBANK_DECLARATIONS
10#undef GET_REGBANK_DECLARATIONS
11
12namespace llvm::Mips {
13
14enum : unsigned {
15 InvalidRegBankID = ~0u,
16 FPRBRegBankID = 0,
17 GPRBRegBankID = 1,
18 NumRegisterBanks,
19};
20
21} // namespace llvm::Mips
22
23#endif // GET_REGBANK_DECLARATIONS
24
25#ifdef GET_TARGET_REGBANK_CLASS
26#undef GET_TARGET_REGBANK_CLASS
27
28private:
29 static const RegisterBank *RegBanks[];
30 static const unsigned Sizes[];
31
32public:
33 const RegisterBank &getRegBankFromRegClass(const TargetRegisterClass &RC, LLT Ty) const override;
34protected:
35 MipsGenRegisterBankInfo(unsigned HwMode = 0);
36
37
38#endif // GET_TARGET_REGBANK_CLASS
39
40#ifdef GET_TARGET_REGBANK_IMPL
41#undef GET_TARGET_REGBANK_IMPL
42
43namespace llvm {
44
45namespace Mips {
46
47const uint32_t FPRBRegBankCoverageData[] = {
48 // 0-31
49 (1u << (Mips::FGR32RegClassID - 0)) |
50 (1u << (Mips::FGR32CCRegClassID - 0)) |
51 0,
52 // 32-63
53 (1u << (Mips::FGR64RegClassID - 32)) |
54 (1u << (Mips::AFGR64RegClassID - 32)) |
55 (1u << (Mips::FGR64CCRegClassID - 32)) |
56 0,
57 // 64-95
58 (1u << (Mips::MSA128DRegClassID - 64)) |
59 (1u << (Mips::MSA128BRegClassID - 64)) |
60 (1u << (Mips::MSA128HRegClassID - 64)) |
61 (1u << (Mips::MSA128WRegClassID - 64)) |
62 (1u << (Mips::MSA128WEvensRegClassID - 64)) |
63 0,
64};
65const uint32_t GPRBRegBankCoverageData[] = {
66 // 0-31
67 (1u << (Mips::GPR32RegClassID - 0)) |
68 (1u << (Mips::GPR32NONZERORegClassID - 0)) |
69 (1u << (Mips::CPU16RegsPlusSPRegClassID - 0)) |
70 (1u << (Mips::CPU16RegsRegClassID - 0)) |
71 (1u << (Mips::GPRMM16RegClassID - 0)) |
72 (1u << (Mips::CPU16Regs_and_GPRMM16ZeroRegClassID - 0)) |
73 (1u << (Mips::CPU16Regs_and_GPRMM16MovePPairSecondRegClassID - 0)) |
74 (1u << (Mips::GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClassID - 0)) |
75 (1u << (Mips::GPRMM16MovePPairFirstRegClassID - 0)) |
76 (1u << (Mips::GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID - 0)) |
77 (1u << (Mips::CPU16Regs_and_GPRMM16MovePRegClassID - 0)) |
78 (1u << (Mips::CPUSPRegRegClassID - 0)) |
79 (1u << (Mips::GPR32NONZERO_and_GPRMM16MovePRegClassID - 0)) |
80 (1u << (Mips::GPRMM16MovePPairSecondRegClassID - 0)) |
81 (1u << (Mips::CPURARegRegClassID - 0)) |
82 (1u << (Mips::GPRMM16MovePRegClassID - 0)) |
83 (1u << (Mips::GPRMM16MoveP_and_GPRMM16ZeroRegClassID - 0)) |
84 (1u << (Mips::GPRMM16ZeroRegClassID - 0)) |
85 (1u << (Mips::DSPRRegClassID - 0)) |
86 0,
87 // 32-63
88 (1u << (Mips::SP32RegClassID - 32)) |
89 (1u << (Mips::GP32RegClassID - 32)) |
90 (1u << (Mips::GPR32ZERORegClassID - 32)) |
91 (1u << (Mips::GPR64RegClassID - 32)) |
92 (1u << (Mips::GPR64_with_sub_32_in_GPR32NONZERORegClassID - 32)) |
93 (1u << (Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClassID - 32)) |
94 (1u << (Mips::GPR64_with_sub_32_in_CPU16RegsRegClassID - 32)) |
95 (1u << (Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClassID - 32)) |
96 (1u << (Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondRegClassID - 32)) |
97 (1u << (Mips::GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClassID - 32)) |
98 (1u << (Mips::GPR64_with_sub_32_in_GPRMM16MovePPairFirstRegClassID - 32)) |
99 (1u << (Mips::GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID - 32)) |
100 (1u << (Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClassID - 32)) |
101 (1u << (Mips::GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClassID - 32)) |
102 (1u << (Mips::GPR64_with_sub_32_in_GPRMM16MovePPairSecondRegClassID - 32)) |
103 (1u << (Mips::GP64RegClassID - 32)) |
104 (1u << (Mips::GPR64_with_sub_32_in_CPURARegRegClassID - 32)) |
105 (1u << (Mips::GPR64_with_sub_32_in_GPRMM16MovePRegClassID - 32)) |
106 (1u << (Mips::GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClassID - 32)) |
107 (1u << (Mips::GPR64_with_sub_32_in_GPR32ZERORegClassID - 32)) |
108 (1u << (Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClassID - 32)) |
109 0,
110 // 64-95
111 (1u << (Mips::SP64RegClassID - 64)) |
112 0,
113};
114
115constexpr RegisterBank FPRBRegBank(/* ID */ Mips::FPRBRegBankID, /* Name */ "FPRB", /* CoveredRegClasses */ FPRBRegBankCoverageData, /* NumRegClasses */ 71);
116constexpr RegisterBank GPRBRegBank(/* ID */ Mips::GPRBRegBankID, /* Name */ "GPRB", /* CoveredRegClasses */ GPRBRegBankCoverageData, /* NumRegClasses */ 71);
117
118} // namespace Mips
119
120const RegisterBank *MipsGenRegisterBankInfo::RegBanks[] = {
121 &Mips::FPRBRegBank,
122 &Mips::GPRBRegBank,
123};
124
125const unsigned MipsGenRegisterBankInfo::Sizes[] = {
126 // Mode = 0 (Default)
127 128,
128 64,
129 // Mode = 1 (MIPS64)
130 128,
131 64,
132};
133
134MipsGenRegisterBankInfo::MipsGenRegisterBankInfo(unsigned HwMode)
135 : RegisterBankInfo(RegBanks, Mips::NumRegisterBanks, Sizes, HwMode) {
136 // Assert that RegBank indices match their ID's
137#ifndef NDEBUG
138 for (auto RB : enumerate(RegBanks))
139 assert(RB.index() == RB.value()->getID() && "Index != ID");
140#endif // NDEBUG
141}
142
143const RegisterBank &
144MipsGenRegisterBankInfo::getRegBankFromRegClass(const TargetRegisterClass &RC, LLT) const {
145 constexpr uint32_t InvalidRegBankID = uint32_t(Mips::InvalidRegBankID) & 3;
146 static const uint32_t RegClass2RegBank[5] = {
147 (uint32_t(InvalidRegBankID) << 0) |
148 (uint32_t(InvalidRegBankID) << 2) |
149 (uint32_t(InvalidRegBankID) << 4) |
150 (uint32_t(InvalidRegBankID) << 6) |
151 (uint32_t(InvalidRegBankID) << 8) |
152 (uint32_t(Mips::GPRBRegBankID) << 10) | // DSPRRegClassID
153 (uint32_t(Mips::FPRBRegBankID) << 12) | // FGR32RegClassID
154 (uint32_t(Mips::FPRBRegBankID) << 14) | // FGR32CCRegClassID
155 (uint32_t(Mips::GPRBRegBankID) << 16) | // GPR32RegClassID
156 (uint32_t(InvalidRegBankID) << 18) |
157 (uint32_t(InvalidRegBankID) << 20) |
158 (uint32_t(Mips::GPRBRegBankID) << 22) | // GPR32NONZERORegClassID
159 (uint32_t(Mips::GPRBRegBankID) << 24) | // CPU16RegsPlusSPRegClassID
160 (uint32_t(Mips::GPRBRegBankID) << 26) | // CPU16RegsRegClassID
161 (uint32_t(InvalidRegBankID) << 28) |
162 (uint32_t(Mips::GPRBRegBankID) << 30), // GPRMM16RegClassID
163 (uint32_t(Mips::GPRBRegBankID) << 0) | // GPRMM16MovePRegClassID
164 (uint32_t(Mips::GPRBRegBankID) << 2) | // GPRMM16ZeroRegClassID
165 (uint32_t(Mips::GPRBRegBankID) << 4) | // CPU16Regs_and_GPRMM16ZeroRegClassID
166 (uint32_t(Mips::GPRBRegBankID) << 6) | // GPR32NONZERO_and_GPRMM16MovePRegClassID
167 (uint32_t(Mips::GPRBRegBankID) << 8) | // GPRMM16MovePPairSecondRegClassID
168 (uint32_t(Mips::GPRBRegBankID) << 10) | // CPU16Regs_and_GPRMM16MovePRegClassID
169 (uint32_t(Mips::GPRBRegBankID) << 12) | // GPRMM16MoveP_and_GPRMM16ZeroRegClassID
170 (uint32_t(InvalidRegBankID) << 14) |
171 (uint32_t(InvalidRegBankID) << 16) |
172 (uint32_t(Mips::GPRBRegBankID) << 18) | // CPU16Regs_and_GPRMM16MovePPairSecondRegClassID
173 (uint32_t(Mips::GPRBRegBankID) << 20) | // GPRMM16MovePPairFirstRegClassID
174 (uint32_t(Mips::GPRBRegBankID) << 22) | // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID
175 (uint32_t(Mips::GPRBRegBankID) << 24) | // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClassID
176 (uint32_t(Mips::GPRBRegBankID) << 26) | // CPURARegRegClassID
177 (uint32_t(Mips::GPRBRegBankID) << 28) | // CPUSPRegRegClassID
178 (uint32_t(InvalidRegBankID) << 30),
179 (uint32_t(Mips::GPRBRegBankID) << 0) | // GP32RegClassID
180 (uint32_t(Mips::GPRBRegBankID) << 2) | // GPR32ZERORegClassID
181 (uint32_t(InvalidRegBankID) << 4) |
182 (uint32_t(InvalidRegBankID) << 6) |
183 (uint32_t(Mips::GPRBRegBankID) << 8) | // SP32RegClassID
184 (uint32_t(Mips::FPRBRegBankID) << 10) | // FGR64CCRegClassID
185 (uint32_t(Mips::FPRBRegBankID) << 12) | // FGR64RegClassID
186 (uint32_t(Mips::GPRBRegBankID) << 14) | // GPR64RegClassID
187 (uint32_t(Mips::GPRBRegBankID) << 16) | // GPR64_with_sub_32_in_GPR32NONZERORegClassID
188 (uint32_t(Mips::FPRBRegBankID) << 18) | // AFGR64RegClassID
189 (uint32_t(Mips::GPRBRegBankID) << 20) | // GPR64_with_sub_32_in_CPU16RegsPlusSPRegClassID
190 (uint32_t(Mips::GPRBRegBankID) << 22) | // GPR64_with_sub_32_in_CPU16RegsRegClassID
191 (uint32_t(Mips::GPRBRegBankID) << 24) | // GPR64_with_sub_32_in_GPRMM16MovePRegClassID
192 (uint32_t(Mips::GPRBRegBankID) << 26) | // GPR64_with_sub_32_in_GPRMM16ZeroRegClassID
193 (uint32_t(Mips::GPRBRegBankID) << 28) | // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClassID
194 (uint32_t(Mips::GPRBRegBankID) << 30), // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClassID
195 (uint32_t(Mips::GPRBRegBankID) << 0) | // GPR64_with_sub_32_in_GPRMM16MovePPairSecondRegClassID
196 (uint32_t(InvalidRegBankID) << 2) |
197 (uint32_t(Mips::GPRBRegBankID) << 4) | // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClassID
198 (uint32_t(Mips::GPRBRegBankID) << 6) | // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClassID
199 (uint32_t(Mips::GPRBRegBankID) << 8) | // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondRegClassID
200 (uint32_t(Mips::GPRBRegBankID) << 10) | // GPR64_with_sub_32_in_GPRMM16MovePPairFirstRegClassID
201 (uint32_t(Mips::GPRBRegBankID) << 12) | // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID
202 (uint32_t(InvalidRegBankID) << 14) |
203 (uint32_t(InvalidRegBankID) << 16) |
204 (uint32_t(Mips::GPRBRegBankID) << 18) | // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClassID
205 (uint32_t(InvalidRegBankID) << 20) |
206 (uint32_t(Mips::GPRBRegBankID) << 22) | // GP64RegClassID
207 (uint32_t(Mips::GPRBRegBankID) << 24) | // GPR64_with_sub_32_in_CPURARegRegClassID
208 (uint32_t(Mips::GPRBRegBankID) << 26) | // GPR64_with_sub_32_in_GPR32ZERORegClassID
209 (uint32_t(InvalidRegBankID) << 28) |
210 (uint32_t(InvalidRegBankID) << 30),
211 (uint32_t(Mips::GPRBRegBankID) << 0) | // SP64RegClassID
212 (uint32_t(Mips::FPRBRegBankID) << 2) | // MSA128BRegClassID
213 (uint32_t(Mips::FPRBRegBankID) << 4) | // MSA128DRegClassID
214 (uint32_t(Mips::FPRBRegBankID) << 6) | // MSA128HRegClassID
215 (uint32_t(Mips::FPRBRegBankID) << 8) | // MSA128WRegClassID
216 (uint32_t(Mips::FPRBRegBankID) << 10) // MSA128WEvensRegClassID
217 };
218 const unsigned RegClassID = RC.getID();
219 if (LLVM_LIKELY(RegClassID < 70)) {
220 unsigned RegBankID = (RegClass2RegBank[RegClassID / 16] >> ((RegClassID % 16) * 2)) & 3;
221 if (RegBankID != InvalidRegBankID)
222 return getRegBank(RegBankID);
223 }
224 llvm_unreachable(llvm::Twine("Target needs to handle register class ID 0x").concat(llvm::Twine::utohexstr(RegClassID)).str().c_str());
225}
226
227} // namespace llvm
228
229#endif // GET_TARGET_REGBANK_IMPL
230
231