1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target SDNode descriptions *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* From: Mips.td *|
7|* *|
8\*===----------------------------------------------------------------------===*/
9
10#ifdef GET_SDNODE_ENUM
11#undef GET_SDNODE_ENUM
12
13namespace llvm::MipsISD {
14
15enum GenNodeType : unsigned {
16 BuildPairF64 = ISD::BUILTIN_OP_END,
17 BuildPairF64_FPR,
18 CIns,
19 CMovFP_F,
20 CMovFP_T,
21 DPAQX_SA_W_PH,
22 DPAQX_S_W_PH,
23 DPAQ_SA_L_W,
24 DPAQ_S_W_PH,
25 DPAU_H_QBL,
26 DPAU_H_QBR,
27 DPAX_W_PH,
28 DPA_W_PH,
29 DPSQX_SA_W_PH,
30 DPSQX_S_W_PH,
31 DPSQ_SA_L_W,
32 DPSQ_S_W_PH,
33 DPSU_H_QBL,
34 DPSU_H_QBR,
35 DPSX_W_PH,
36 DPS_W_PH,
37 DivRem,
38 DivRem16,
39 DivRemU,
40 DivRemU16,
41 EH_RETURN,
42 ERet,
43 EXTP,
44 EXTPDP,
45 EXTR_RS_W,
46 EXTR_R_W,
47 EXTR_S_H,
48 EXTR_W,
49 Ext,
50 ExtractElementF64,
51 ExtractElementF64_FPR,
52 FMS,
53 FPBrcond,
54 FPCmp,
55 GPRel,
56 GotHi,
57 Hi,
58 Higher,
59 Highest,
60 ILVEV,
61 ILVL,
62 ILVOD,
63 ILVR,
64 INSVE,
65 Ins,
66 JmpLink,
67 LDL,
68 LDR,
69 LWL,
70 LWR,
71 Lo,
72 MADDU_DSP,
73 MADD_DSP,
74 MAQ_SA_W_PHL,
75 MAQ_SA_W_PHR,
76 MAQ_S_W_PHL,
77 MAQ_S_W_PHR,
78 MAdd,
79 MAddu,
80 MFHI,
81 MFLO,
82 MSUBU_DSP,
83 MSUB_DSP,
84 MSub,
85 MSubu,
86 MTC1_D64,
87 MTHLIP,
88 MTLOHI,
89 MULSAQ_S_W_PH,
90 MULSA_W_PH,
91 MULT,
92 MULTU,
93 Mult,
94 Multu,
95 PCKEV,
96 PCKOD,
97 Ret,
98 SDL,
99 SDR,
100 SELECT_CC_DSP,
101 SETCC_DSP,
102 SHF,
103 SHILO,
104 SHLL_DSP,
105 SHRA_DSP,
106 SHRL_DSP,
107 SWL,
108 SWR,
109 Sync,
110 TailCall,
111 ThreadPointer,
112 TlsHi,
113 TruncIntFP,
114 VALL_NONZERO,
115 VALL_ZERO,
116 VANY_NONZERO,
117 VANY_ZERO,
118 VEXTRACT_SEXT_ELT,
119 VEXTRACT_ZEXT_ELT,
120 VNOR,
121 VSHF,
122 Wrapper,
123};
124
125static constexpr unsigned GENERATED_OPCODE_END = Wrapper + 1;
126
127} // namespace llvm::MipsISD
128
129#endif // GET_SDNODE_ENUM
130
131#ifdef GET_SDNODE_DESC
132#undef GET_SDNODE_DESC
133
134namespace llvm {
135
136
137#ifdef __GNUC__
138#pragma GCC diagnostic push
139#pragma GCC diagnostic ignored "-Woverlength-strings"
140#endif
141static constexpr char MipsSDNodeNamesStorage[] =
142 "\0"
143 "MipsISD::BuildPairF64\0"
144 "MipsISD::BuildPairF64_FPR\0"
145 "MipsISD::CIns\0"
146 "MipsISD::CMovFP_F\0"
147 "MipsISD::CMovFP_T\0"
148 "MipsISD::DPAQX_SA_W_PH\0"
149 "MipsISD::DPAQX_S_W_PH\0"
150 "MipsISD::DPAQ_SA_L_W\0"
151 "MipsISD::DPAQ_S_W_PH\0"
152 "MipsISD::DPAU_H_QBL\0"
153 "MipsISD::DPAU_H_QBR\0"
154 "MipsISD::DPAX_W_PH\0"
155 "MipsISD::DPA_W_PH\0"
156 "MipsISD::DPSQX_SA_W_PH\0"
157 "MipsISD::DPSQX_S_W_PH\0"
158 "MipsISD::DPSQ_SA_L_W\0"
159 "MipsISD::DPSQ_S_W_PH\0"
160 "MipsISD::DPSU_H_QBL\0"
161 "MipsISD::DPSU_H_QBR\0"
162 "MipsISD::DPSX_W_PH\0"
163 "MipsISD::DPS_W_PH\0"
164 "MipsISD::DivRem\0"
165 "MipsISD::DivRem16\0"
166 "MipsISD::DivRemU\0"
167 "MipsISD::DivRemU16\0"
168 "MipsISD::EH_RETURN\0"
169 "MipsISD::ERet\0"
170 "MipsISD::EXTP\0"
171 "MipsISD::EXTPDP\0"
172 "MipsISD::EXTR_RS_W\0"
173 "MipsISD::EXTR_R_W\0"
174 "MipsISD::EXTR_S_H\0"
175 "MipsISD::EXTR_W\0"
176 "MipsISD::Ext\0"
177 "MipsISD::ExtractElementF64\0"
178 "MipsISD::ExtractElementF64_FPR\0"
179 "MipsISD::FMS\0"
180 "MipsISD::FPBrcond\0"
181 "MipsISD::FPCmp\0"
182 "MipsISD::GPRel\0"
183 "MipsISD::GotHi\0"
184 "MipsISD::Hi\0"
185 "MipsISD::Higher\0"
186 "MipsISD::Highest\0"
187 "MipsISD::ILVEV\0"
188 "MipsISD::ILVL\0"
189 "MipsISD::ILVOD\0"
190 "MipsISD::ILVR\0"
191 "MipsISD::INSVE\0"
192 "MipsISD::Ins\0"
193 "MipsISD::JmpLink\0"
194 "MipsISD::LDL\0"
195 "MipsISD::LDR\0"
196 "MipsISD::LWL\0"
197 "MipsISD::LWR\0"
198 "MipsISD::Lo\0"
199 "MipsISD::MADDU_DSP\0"
200 "MipsISD::MADD_DSP\0"
201 "MipsISD::MAQ_SA_W_PHL\0"
202 "MipsISD::MAQ_SA_W_PHR\0"
203 "MipsISD::MAQ_S_W_PHL\0"
204 "MipsISD::MAQ_S_W_PHR\0"
205 "MipsISD::MAdd\0"
206 "MipsISD::MAddu\0"
207 "MipsISD::MFHI\0"
208 "MipsISD::MFLO\0"
209 "MipsISD::MSUBU_DSP\0"
210 "MipsISD::MSUB_DSP\0"
211 "MipsISD::MSub\0"
212 "MipsISD::MSubu\0"
213 "MipsISD::MTC1_D64\0"
214 "MipsISD::MTHLIP\0"
215 "MipsISD::MTLOHI\0"
216 "MipsISD::MULSAQ_S_W_PH\0"
217 "MipsISD::MULSA_W_PH\0"
218 "MipsISD::MULT\0"
219 "MipsISD::MULTU\0"
220 "MipsISD::Mult\0"
221 "MipsISD::Multu\0"
222 "MipsISD::PCKEV\0"
223 "MipsISD::PCKOD\0"
224 "MipsISD::Ret\0"
225 "MipsISD::SDL\0"
226 "MipsISD::SDR\0"
227 "MipsISD::SELECT_CC_DSP\0"
228 "MipsISD::SETCC_DSP\0"
229 "MipsISD::SHF\0"
230 "MipsISD::SHILO\0"
231 "MipsISD::SHLL_DSP\0"
232 "MipsISD::SHRA_DSP\0"
233 "MipsISD::SHRL_DSP\0"
234 "MipsISD::SWL\0"
235 "MipsISD::SWR\0"
236 "MipsISD::Sync\0"
237 "MipsISD::TailCall\0"
238 "MipsISD::ThreadPointer\0"
239 "MipsISD::TlsHi\0"
240 "MipsISD::TruncIntFP\0"
241 "MipsISD::VALL_NONZERO\0"
242 "MipsISD::VALL_ZERO\0"
243 "MipsISD::VANY_NONZERO\0"
244 "MipsISD::VANY_ZERO\0"
245 "MipsISD::VEXTRACT_SEXT_ELT\0"
246 "MipsISD::VEXTRACT_ZEXT_ELT\0"
247 "MipsISD::VNOR\0"
248 "MipsISD::VSHF\0"
249 "MipsISD::Wrapper\0"
250 ;
251#ifdef __GNUC__
252#pragma GCC diagnostic pop
253#endif
254
255static constexpr llvm::StringTable
256MipsSDNodeNames = MipsSDNodeNamesStorage;
257
258static const VTByHwModePair MipsVTByHwModeTable[] = {
259 /* dummy */ {0, MVT::INVALID_SIMPLE_VALUE_TYPE}
260};
261
262static const SDTypeConstraint MipsSDTypeConstraints[] = {
263 /* 0 */ {SDTCisVT, 2, 0, 0, MVT::Untyped}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVT, 0, 0, 0, MVT::i32},
264 /* 3 */ {SDTCisVT, 2, 0, 0, MVT::i32}, {SDTCisVT, 1, 0, 0, MVT::f64}, {SDTCisVT, 0, 0, 0, MVT::i32},
265 /* 6 */ {SDTCisVT, 2, 0, 0, MVT::i32}, {SDTCisVT, 1, 0, 0, MVT::f64}, {SDTCisVT, 0, 0, 0, MVT::f32},
266 /* 9 */ {SDTCisSameAs, 1, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVT, 1, 0, 0, MVT::i32}, {SDTCisVT, 0, 0, 0, MVT::f64},
267 /* 12 */ {SDTCisSameAs, 1, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVT, 1, 0, 0, MVT::f32}, {SDTCisVT, 0, 0, 0, MVT::f64},
268 /* 15 */ {SDTCisVT, 1, 0, 0, MVT::i32}, {SDTCisSameAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVT, 0, 0, 0, MVT::Untyped},
269 /* 18 */ {SDTCisSameAs, 1, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVT, 1, 0, 0, MVT::i32}, {SDTCisSameAs, 0, 3, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVT, 0, 0, 0, MVT::Untyped},
270 /* 22 */ {SDTCisSameAs, 1, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVT, 1, 0, 0, MVT::v4i8}, {SDTCisSameAs, 0, 3, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVT, 0, 0, 0, MVT::Untyped},
271 /* 26 */ {SDTCisSameAs, 1, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVT, 1, 0, 0, MVT::v2i16}, {SDTCisSameAs, 0, 3, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVT, 0, 0, 0, MVT::Untyped},
272 /* 30 */ {SDTCisSameAs, 1, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVT, 0, 0, 0, MVT::Untyped},
273 /* 33 */ {SDTCisVT, 0, 0, 0, MVT::iPTR},
274 /* 34 */ {SDTCisPtrTy, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
275 /* 35 */ {SDTCisSameAs, 1, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
276 /* 39 */ {SDTCisSameAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVT, 1, 0, 0, MVT::i32}, {SDTCisVec, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
277 /* 43 */ {SDTCisSameAs, 2, 3, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
278 /* 49 */ {SDTCisSameAs, 0, 4, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 2, 3, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVT, 2, 0, 0, MVT::i32}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
279 /* 54 */ {SDTCisVT, 2, 0, 0, MVT::Other}, {SDTCisVT, 1, 0, 0, MVT::i32}, {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
280 /* 57 */ {SDTCisVT, 1, 0, 0, MVT::Untyped}, {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
281 /* 59 */ {SDTCisSameAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisPtrTy, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
282 /* 62 */ {SDTCisVec, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
283 /* 64 */ {SDTCisVT, 3, 0, 0, MVT::Other}, {SDTCisSameAs, 1, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
284 /* 67 */ {SDTCisFP, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisFP, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
285 /* 69 */ {SDTCisVT, 4, 0, 0, MVT::i32}, {SDTCisSameAs, 0, 3, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVT, 2, 0, 0, MVT::i32}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
286 /* 74 */ {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
287 /* 76 */ {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
288 /* 79 */ {SDTCisFP, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 3, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
289 /* 83 */ {SDTCisVT, 2, 0, 0, MVT::i32}, {SDTCisFP, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
290 /* 86 */ {SDTCisSameAs, 1, 3, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVT, 2, 0, 0, MVT::i32}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
291 /* 89 */ {SDTCisPtrTy, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
292 /* 90 */ {SDTCisVT, 5, 0, 0, MVT::Other}, {SDTCisSameAs, 0, 3, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 3, 4, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 1, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
293 /* 94 */ {SDTCisPtrTy, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
294};
295
296static const SDNodeDesc MipsSDNodeDescs[] = {
297 {1, 2, 0, 0, 0, 1, 9, 3}, // BuildPairF64
298 {1, 2, 0, 0, 0, 23, 12, 3}, // BuildPairF64_FPR
299 {1, 3, 0, 0, 0, 49, 50, 4}, // CIns
300 {1, 3, 0|1<<SDNPInGlue, 0, 0, 63, 86, 3}, // CMovFP_F
301 {1, 3, 0|1<<SDNPInGlue, 0, 0, 81, 86, 3}, // CMovFP_T
302 {1, 3, 0|1<<SDNPHasChain, 0, 0, 99, 26, 4}, // DPAQX_SA_W_PH
303 {1, 3, 0|1<<SDNPHasChain, 0, 0, 122, 26, 4}, // DPAQX_S_W_PH
304 {1, 3, 0|1<<SDNPHasChain, 0, 0, 144, 18, 4}, // DPAQ_SA_L_W
305 {1, 3, 0|1<<SDNPHasChain, 0, 0, 165, 26, 4}, // DPAQ_S_W_PH
306 {1, 3, 0, 0, 0, 186, 22, 4}, // DPAU_H_QBL
307 {1, 3, 0, 0, 0, 206, 22, 4}, // DPAU_H_QBR
308 {1, 3, 0, 0, 0, 226, 26, 4}, // DPAX_W_PH
309 {1, 3, 0, 0, 0, 245, 26, 4}, // DPA_W_PH
310 {1, 3, 0|1<<SDNPHasChain, 0, 0, 263, 26, 4}, // DPSQX_SA_W_PH
311 {1, 3, 0|1<<SDNPHasChain, 0, 0, 286, 26, 4}, // DPSQX_S_W_PH
312 {1, 3, 0|1<<SDNPHasChain, 0, 0, 308, 18, 4}, // DPSQ_SA_L_W
313 {1, 3, 0|1<<SDNPHasChain, 0, 0, 329, 26, 4}, // DPSQ_S_W_PH
314 {1, 3, 0, 0, 0, 350, 22, 4}, // DPSU_H_QBL
315 {1, 3, 0, 0, 0, 370, 22, 4}, // DPSU_H_QBR
316 {1, 3, 0, 0, 0, 390, 26, 4}, // DPSX_W_PH
317 {1, 3, 0, 0, 0, 409, 26, 4}, // DPS_W_PH
318 {1, 2, 0, 0, 0, 427, 30, 3}, // DivRem
319 {0, 2, 0|1<<SDNPOutGlue, 0, 0, 443, 52, 2}, // DivRem16
320 {1, 2, 0, 0, 0, 461, 30, 3}, // DivRemU
321 {0, 2, 0|1<<SDNPOutGlue, 0, 0, 478, 52, 2}, // DivRemU16
322 {0, 2, 0|1<<SDNPHasChain|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 497, 60, 2}, // EH_RETURN
323 {0, 0, 0|1<<SDNPHasChain|1<<SDNPOptInGlue, 0, 0, 516, 0, 0}, // ERet
324 {1, 2, 0|1<<SDNPHasChain, 0, 0, 530, 0, 3}, // EXTP
325 {1, 2, 0|1<<SDNPHasChain, 0, 0, 544, 0, 3}, // EXTPDP
326 {1, 2, 0|1<<SDNPHasChain, 0, 0, 560, 0, 3}, // EXTR_RS_W
327 {1, 2, 0|1<<SDNPHasChain, 0, 0, 579, 0, 3}, // EXTR_R_W
328 {1, 2, 0|1<<SDNPHasChain, 0, 0, 597, 0, 3}, // EXTR_S_H
329 {1, 2, 0|1<<SDNPHasChain, 0, 0, 615, 0, 3}, // EXTR_W
330 {1, 3, 0, 0, 0, 631, 50, 4}, // Ext
331 {1, 2, 0, 0, 0, 644, 3, 3}, // ExtractElementF64
332 {1, 2, 0, 0, 0, 671, 6, 3}, // ExtractElementF64_FPR
333 {1, 3, 0, 0, 0, 702, 79, 4}, // FMS
334 {0, 3, 0|1<<SDNPHasChain|1<<SDNPOptInGlue, 0, 0, 715, 54, 3}, // FPBrcond
335 {0, 3, 0|1<<SDNPOutGlue, 0, 0, 733, 83, 3}, // FPCmp
336 {1, 1, 0, 0, 0, 748, 74, 2}, // GPRel
337 {1, 1, 0, 0, 0, 763, 74, 2}, // GotHi
338 {1, 1, 0, 0, 0, 778, 74, 2}, // Hi
339 {1, 1, 0, 0, 0, 790, 74, 2}, // Higher
340 {1, 1, 0, 0, 0, 806, 74, 2}, // Highest
341 {1, 2, 0, 0, 0, 823, 35, 4}, // ILVEV
342 {1, 2, 0, 0, 0, 838, 35, 4}, // ILVL
343 {1, 2, 0, 0, 0, 852, 35, 4}, // ILVOD
344 {1, 2, 0, 0, 0, 867, 35, 4}, // ILVR
345 {1, 4, 0, 0, 0, 881, 69, 5}, // INSVE
346 {1, 4, 0, 0, 0, 896, 49, 5}, // Ins
347 {0, 1, 0|1<<SDNPHasChain|1<<SDNPOutGlue|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 909, 33, 1}, // JmpLink
348 {1, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 926, 59, 3}, // LDL
349 {1, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 939, 59, 3}, // LDR
350 {1, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 952, 59, 3}, // LWL
351 {1, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 965, 59, 3}, // LWR
352 {1, 1, 0, 0, 0, 978, 74, 2}, // Lo
353 {1, 3, 0, 0, 0, 990, 18, 4}, // MADDU_DSP
354 {1, 3, 0, 0, 0, 1009, 18, 4}, // MADD_DSP
355 {1, 3, 0|1<<SDNPHasChain, 0, 0, 1027, 26, 4}, // MAQ_SA_W_PHL
356 {1, 3, 0|1<<SDNPHasChain, 0, 0, 1049, 26, 4}, // MAQ_SA_W_PHR
357 {1, 3, 0|1<<SDNPHasChain, 0, 0, 1071, 26, 4}, // MAQ_S_W_PHL
358 {1, 3, 0|1<<SDNPHasChain, 0, 0, 1092, 26, 4}, // MAQ_S_W_PHR
359 {1, 3, 0, 0, 0, 1113, 18, 4}, // MAdd
360 {1, 3, 0, 0, 0, 1127, 18, 4}, // MAddu
361 {1, 1, 0, 0, 0, 1142, 57, 2}, // MFHI
362 {1, 1, 0, 0, 0, 1156, 57, 2}, // MFLO
363 {1, 3, 0, 0, 0, 1170, 18, 4}, // MSUBU_DSP
364 {1, 3, 0, 0, 0, 1189, 18, 4}, // MSUB_DSP
365 {1, 3, 0, 0, 0, 1207, 18, 4}, // MSub
366 {1, 3, 0, 0, 0, 1221, 18, 4}, // MSubu
367 {1, 1, 0, 0, 0, 1236, 10, 2}, // MTC1_D64
368 {1, 2, 0|1<<SDNPHasChain, 0, 0, 1254, 15, 3}, // MTHLIP
369 {1, 2, 0, 0, 0, 1270, 30, 3}, // MTLOHI
370 {1, 3, 0|1<<SDNPHasChain, 0, 0, 1286, 26, 4}, // MULSAQ_S_W_PH
371 {1, 3, 0, 0, 0, 1309, 26, 4}, // MULSA_W_PH
372 {1, 3, 0, 0, 0, 1329, 18, 4}, // MULT
373 {1, 3, 0, 0, 0, 1343, 18, 4}, // MULTU
374 {1, 2, 0, 0, 0, 1358, 30, 3}, // Mult
375 {1, 2, 0, 0, 0, 1372, 30, 3}, // Multu
376 {1, 2, 0, 0, 0, 1387, 35, 4}, // PCKEV
377 {1, 2, 0, 0, 0, 1402, 35, 4}, // PCKOD
378 {0, 0, 0|1<<SDNPHasChain|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 1417, 0, 0}, // Ret
379 {0, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 1430, 89, 1}, // SDL
380 {0, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 1443, 89, 1}, // SDR
381 {1, 5, 0, 0, 0, 1456, 90, 4}, // SELECT_CC_DSP
382 {1, 3, 0, 0, 0, 1479, 64, 3}, // SETCC_DSP
383 {1, 2, 0, 0, 0, 1498, 39, 4}, // SHF
384 {1, 2, 0, 0, 0, 1511, 15, 3}, // SHILO
385 {1, 2, 0, 0, 0, 1526, 71, 3}, // SHLL_DSP
386 {1, 2, 0, 0, 0, 1544, 71, 3}, // SHRA_DSP
387 {1, 2, 0, 0, 0, 1562, 71, 3}, // SHRL_DSP
388 {0, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 1580, 89, 1}, // SWL
389 {0, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 1593, 89, 1}, // SWR
390 {0, 1, 0|1<<SDNPHasChain, 0, 0, 1606, 2, 1}, // Sync
391 {0, 1, 0|1<<SDNPHasChain|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 1620, 33, 1}, // TailCall
392 {1, 0, 0, 0, 0, 1638, 34, 1}, // ThreadPointer
393 {1, 1, 0, 0, 0, 1661, 74, 2}, // TlsHi
394 {1, 1, 0, 0, 0, 1676, 67, 2}, // TruncIntFP
395 {1, 1, 0, 0, 0, 1696, 62, 2}, // VALL_NONZERO
396 {1, 1, 0, 0, 0, 1718, 62, 2}, // VALL_ZERO
397 {1, 1, 0, 0, 0, 1737, 62, 2}, // VANY_NONZERO
398 {1, 1, 0, 0, 0, 1759, 62, 2}, // VANY_ZERO
399 {1, 3, 0, 0, 0, 1778, 94, 1}, // VEXTRACT_SEXT_ELT
400 {1, 3, 0, 0, 0, 1805, 94, 1}, // VEXTRACT_ZEXT_ELT
401 {1, 2, 0, 0, 0, 1832, 76, 3}, // VNOR
402 {1, 3, 0, 0, 0, 1846, 43, 6}, // VSHF
403 {1, 2, 0, 0, 0, 1860, 76, 3}, // Wrapper
404};
405
406static const SDNodeInfo MipsGenSDNodeInfo(
407 /*NumOpcodes=*/107, MipsSDNodeDescs, MipsSDNodeNames,
408 MipsVTByHwModeTable, MipsSDTypeConstraints);
409
410} // namespace llvm
411
412#endif // GET_SDNODE_DESC
413
414