1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target SDNode descriptions *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* From: Mips.td *|
7|* *|
8\*===----------------------------------------------------------------------===*/
9
10#ifdef GET_SDNODE_ENUM
11#undef GET_SDNODE_ENUM
12
13namespace llvm::MipsISD {
14
15enum GenNodeType : unsigned {
16 BuildPairF64 = ISD::BUILTIN_OP_END,
17 BuildPairF64_FPR,
18 CIns,
19 CMovFP_F,
20 CMovFP_T,
21 DPAQX_SA_W_PH,
22 DPAQX_S_W_PH,
23 DPAQ_SA_L_W,
24 DPAQ_S_W_PH,
25 DPAU_H_QBL,
26 DPAU_H_QBR,
27 DPAX_W_PH,
28 DPA_W_PH,
29 DPSQX_SA_W_PH,
30 DPSQX_S_W_PH,
31 DPSQ_SA_L_W,
32 DPSQ_S_W_PH,
33 DPSU_H_QBL,
34 DPSU_H_QBR,
35 DPSX_W_PH,
36 DPS_W_PH,
37 DivRem,
38 DivRem16,
39 DivRemU,
40 DivRemU16,
41 EH_RETURN,
42 ERet,
43 EXTP,
44 EXTPDP,
45 EXTR_RS_W,
46 EXTR_R_W,
47 EXTR_S_H,
48 EXTR_W,
49 Ext,
50 ExtractElementF64,
51 ExtractElementF64_FPR,
52 FMS,
53 FPBrcond,
54 FPCmp,
55 FSELECT,
56 GPRel,
57 GotHi,
58 Hi,
59 Higher,
60 Highest,
61 ILVEV,
62 ILVL,
63 ILVOD,
64 ILVR,
65 INSVE,
66 Ins,
67 JmpLink,
68 LDL,
69 LDR,
70 LWL,
71 LWR,
72 Lo,
73 MADDU_DSP,
74 MADD_DSP,
75 MAQ_SA_W_PHL,
76 MAQ_SA_W_PHR,
77 MAQ_S_W_PHL,
78 MAQ_S_W_PHR,
79 MAdd,
80 MAddu,
81 MFHI,
82 MFLO,
83 MSUBU_DSP,
84 MSUB_DSP,
85 MSub,
86 MSubu,
87 MTC1_D64,
88 MTHLIP,
89 MTLOHI,
90 MULSAQ_S_W_PH,
91 MULSA_W_PH,
92 MULT,
93 MULTU,
94 Mult,
95 Multu,
96 PCKEV,
97 PCKOD,
98 Ret,
99 SDL,
100 SDR,
101 SELECT_CC_DSP,
102 SETCC_DSP,
103 SHF,
104 SHILO,
105 SHLL_DSP,
106 SHRA_DSP,
107 SHRL_DSP,
108 SWL,
109 SWR,
110 Sync,
111 TailCall,
112 ThreadPointer,
113 TlsHi,
114 TruncIntFP,
115 VALL_NONZERO,
116 VALL_ZERO,
117 VANY_NONZERO,
118 VANY_ZERO,
119 VEXTRACT_SEXT_ELT,
120 VEXTRACT_ZEXT_ELT,
121 VNOR,
122 VSHF,
123 Wrapper,
124};
125
126static constexpr unsigned GENERATED_OPCODE_END = Wrapper + 1;
127
128} // namespace llvm::MipsISD
129
130#endif // GET_SDNODE_ENUM
131
132#ifdef GET_SDNODE_DESC
133#undef GET_SDNODE_DESC
134
135namespace llvm {
136
137
138#ifdef __GNUC__
139#pragma GCC diagnostic push
140#pragma GCC diagnostic ignored "-Woverlength-strings"
141#endif
142static constexpr char MipsSDNodeNamesStorage[] =
143 "\0"
144 "MipsISD::BuildPairF64\0"
145 "MipsISD::BuildPairF64_FPR\0"
146 "MipsISD::CIns\0"
147 "MipsISD::CMovFP_F\0"
148 "MipsISD::CMovFP_T\0"
149 "MipsISD::DPAQX_SA_W_PH\0"
150 "MipsISD::DPAQX_S_W_PH\0"
151 "MipsISD::DPAQ_SA_L_W\0"
152 "MipsISD::DPAQ_S_W_PH\0"
153 "MipsISD::DPAU_H_QBL\0"
154 "MipsISD::DPAU_H_QBR\0"
155 "MipsISD::DPAX_W_PH\0"
156 "MipsISD::DPA_W_PH\0"
157 "MipsISD::DPSQX_SA_W_PH\0"
158 "MipsISD::DPSQX_S_W_PH\0"
159 "MipsISD::DPSQ_SA_L_W\0"
160 "MipsISD::DPSQ_S_W_PH\0"
161 "MipsISD::DPSU_H_QBL\0"
162 "MipsISD::DPSU_H_QBR\0"
163 "MipsISD::DPSX_W_PH\0"
164 "MipsISD::DPS_W_PH\0"
165 "MipsISD::DivRem\0"
166 "MipsISD::DivRem16\0"
167 "MipsISD::DivRemU\0"
168 "MipsISD::DivRemU16\0"
169 "MipsISD::EH_RETURN\0"
170 "MipsISD::ERet\0"
171 "MipsISD::EXTP\0"
172 "MipsISD::EXTPDP\0"
173 "MipsISD::EXTR_RS_W\0"
174 "MipsISD::EXTR_R_W\0"
175 "MipsISD::EXTR_S_H\0"
176 "MipsISD::EXTR_W\0"
177 "MipsISD::Ext\0"
178 "MipsISD::ExtractElementF64\0"
179 "MipsISD::ExtractElementF64_FPR\0"
180 "MipsISD::FMS\0"
181 "MipsISD::FPBrcond\0"
182 "MipsISD::FPCmp\0"
183 "MipsISD::FSELECT\0"
184 "MipsISD::GPRel\0"
185 "MipsISD::GotHi\0"
186 "MipsISD::Hi\0"
187 "MipsISD::Higher\0"
188 "MipsISD::Highest\0"
189 "MipsISD::ILVEV\0"
190 "MipsISD::ILVL\0"
191 "MipsISD::ILVOD\0"
192 "MipsISD::ILVR\0"
193 "MipsISD::INSVE\0"
194 "MipsISD::Ins\0"
195 "MipsISD::JmpLink\0"
196 "MipsISD::LDL\0"
197 "MipsISD::LDR\0"
198 "MipsISD::LWL\0"
199 "MipsISD::LWR\0"
200 "MipsISD::Lo\0"
201 "MipsISD::MADDU_DSP\0"
202 "MipsISD::MADD_DSP\0"
203 "MipsISD::MAQ_SA_W_PHL\0"
204 "MipsISD::MAQ_SA_W_PHR\0"
205 "MipsISD::MAQ_S_W_PHL\0"
206 "MipsISD::MAQ_S_W_PHR\0"
207 "MipsISD::MAdd\0"
208 "MipsISD::MAddu\0"
209 "MipsISD::MFHI\0"
210 "MipsISD::MFLO\0"
211 "MipsISD::MSUBU_DSP\0"
212 "MipsISD::MSUB_DSP\0"
213 "MipsISD::MSub\0"
214 "MipsISD::MSubu\0"
215 "MipsISD::MTC1_D64\0"
216 "MipsISD::MTHLIP\0"
217 "MipsISD::MTLOHI\0"
218 "MipsISD::MULSAQ_S_W_PH\0"
219 "MipsISD::MULSA_W_PH\0"
220 "MipsISD::MULT\0"
221 "MipsISD::MULTU\0"
222 "MipsISD::Mult\0"
223 "MipsISD::Multu\0"
224 "MipsISD::PCKEV\0"
225 "MipsISD::PCKOD\0"
226 "MipsISD::Ret\0"
227 "MipsISD::SDL\0"
228 "MipsISD::SDR\0"
229 "MipsISD::SELECT_CC_DSP\0"
230 "MipsISD::SETCC_DSP\0"
231 "MipsISD::SHF\0"
232 "MipsISD::SHILO\0"
233 "MipsISD::SHLL_DSP\0"
234 "MipsISD::SHRA_DSP\0"
235 "MipsISD::SHRL_DSP\0"
236 "MipsISD::SWL\0"
237 "MipsISD::SWR\0"
238 "MipsISD::Sync\0"
239 "MipsISD::TailCall\0"
240 "MipsISD::ThreadPointer\0"
241 "MipsISD::TlsHi\0"
242 "MipsISD::TruncIntFP\0"
243 "MipsISD::VALL_NONZERO\0"
244 "MipsISD::VALL_ZERO\0"
245 "MipsISD::VANY_NONZERO\0"
246 "MipsISD::VANY_ZERO\0"
247 "MipsISD::VEXTRACT_SEXT_ELT\0"
248 "MipsISD::VEXTRACT_ZEXT_ELT\0"
249 "MipsISD::VNOR\0"
250 "MipsISD::VSHF\0"
251 "MipsISD::Wrapper\0"
252 ;
253#ifdef __GNUC__
254#pragma GCC diagnostic pop
255#endif
256
257static constexpr llvm::StringTable
258MipsSDNodeNames = MipsSDNodeNamesStorage;
259
260static const VTByHwModePair MipsVTByHwModeTable[] = {
261 /* dummy */ {0, MVT::INVALID_SIMPLE_VALUE_TYPE}
262};
263
264static const SDTypeConstraint MipsSDTypeConstraints[] = {
265 /* 0 */ {SDTCisVT, 2, 0, 0, MVT::Untyped}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVT, 0, 0, 0, MVT::i32},
266 /* 3 */ {SDTCisVT, 2, 0, 0, MVT::i32}, {SDTCisVT, 1, 0, 0, MVT::f64}, {SDTCisVT, 0, 0, 0, MVT::i32},
267 /* 6 */ {SDTCisVT, 2, 0, 0, MVT::i32}, {SDTCisVT, 1, 0, 0, MVT::f64}, {SDTCisVT, 0, 0, 0, MVT::f32},
268 /* 9 */ {SDTCisSameAs, 1, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVT, 1, 0, 0, MVT::i32}, {SDTCisVT, 0, 0, 0, MVT::f64},
269 /* 12 */ {SDTCisSameAs, 1, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVT, 1, 0, 0, MVT::f32}, {SDTCisVT, 0, 0, 0, MVT::f64},
270 /* 15 */ {SDTCisVT, 1, 0, 0, MVT::i32}, {SDTCisSameAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVT, 0, 0, 0, MVT::Untyped},
271 /* 18 */ {SDTCisSameAs, 1, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVT, 1, 0, 0, MVT::i32}, {SDTCisSameAs, 0, 3, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVT, 0, 0, 0, MVT::Untyped},
272 /* 22 */ {SDTCisSameAs, 1, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVT, 1, 0, 0, MVT::v4i8}, {SDTCisSameAs, 0, 3, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVT, 0, 0, 0, MVT::Untyped},
273 /* 26 */ {SDTCisSameAs, 1, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVT, 1, 0, 0, MVT::v2i16}, {SDTCisSameAs, 0, 3, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVT, 0, 0, 0, MVT::Untyped},
274 /* 30 */ {SDTCisSameAs, 1, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVT, 0, 0, 0, MVT::Untyped},
275 /* 33 */ {SDTCisVT, 0, 0, 0, MVT::iPTR},
276 /* 34 */ {SDTCisPtrTy, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
277 /* 35 */ {SDTCisSameAs, 1, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
278 /* 39 */ {SDTCisSameAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVT, 1, 0, 0, MVT::i32}, {SDTCisVec, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
279 /* 43 */ {SDTCisSameAs, 2, 3, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
280 /* 49 */ {SDTCisSameAs, 0, 4, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 2, 3, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVT, 2, 0, 0, MVT::i32}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
281 /* 54 */ {SDTCisVT, 2, 0, 0, MVT::Other}, {SDTCisVT, 1, 0, 0, MVT::i32}, {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
282 /* 57 */ {SDTCisVT, 1, 0, 0, MVT::Untyped}, {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
283 /* 59 */ {SDTCisSameAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisPtrTy, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
284 /* 62 */ {SDTCisVec, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
285 /* 64 */ {SDTCisVT, 3, 0, 0, MVT::Other}, {SDTCisSameAs, 1, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
286 /* 67 */ {SDTCisFP, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisFP, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
287 /* 69 */ {SDTCisVT, 4, 0, 0, MVT::i32}, {SDTCisSameAs, 0, 3, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVT, 2, 0, 0, MVT::i32}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
288 /* 74 */ {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
289 /* 76 */ {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
290 /* 79 */ {SDTCisFP, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 3, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
291 /* 83 */ {SDTCisVT, 2, 0, 0, MVT::i32}, {SDTCisFP, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
292 /* 86 */ {SDTCisSameAs, 1, 3, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVT, 2, 0, 0, MVT::i32}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
293 /* 89 */ {SDTCisPtrTy, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
294 /* 90 */ {SDTCisSameAs, 2, 3, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisFP, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
295 /* 93 */ {SDTCisVT, 5, 0, 0, MVT::Other}, {SDTCisSameAs, 0, 3, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 3, 4, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 1, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
296 /* 97 */ {SDTCisPtrTy, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
297};
298
299static const SDNodeDesc MipsSDNodeDescs[] = {
300 {1, 2, 0, 0, 0, 1, 9, 3}, // BuildPairF64
301 {1, 2, 0, 0, 0, 23, 12, 3}, // BuildPairF64_FPR
302 {1, 3, 0, 0, 0, 49, 50, 4}, // CIns
303 {1, 3, 0|1<<SDNPInGlue, 0, 0, 63, 86, 3}, // CMovFP_F
304 {1, 3, 0|1<<SDNPInGlue, 0, 0, 81, 86, 3}, // CMovFP_T
305 {1, 3, 0|1<<SDNPHasChain, 0, 0, 99, 26, 4}, // DPAQX_SA_W_PH
306 {1, 3, 0|1<<SDNPHasChain, 0, 0, 122, 26, 4}, // DPAQX_S_W_PH
307 {1, 3, 0|1<<SDNPHasChain, 0, 0, 144, 18, 4}, // DPAQ_SA_L_W
308 {1, 3, 0|1<<SDNPHasChain, 0, 0, 165, 26, 4}, // DPAQ_S_W_PH
309 {1, 3, 0, 0, 0, 186, 22, 4}, // DPAU_H_QBL
310 {1, 3, 0, 0, 0, 206, 22, 4}, // DPAU_H_QBR
311 {1, 3, 0, 0, 0, 226, 26, 4}, // DPAX_W_PH
312 {1, 3, 0, 0, 0, 245, 26, 4}, // DPA_W_PH
313 {1, 3, 0|1<<SDNPHasChain, 0, 0, 263, 26, 4}, // DPSQX_SA_W_PH
314 {1, 3, 0|1<<SDNPHasChain, 0, 0, 286, 26, 4}, // DPSQX_S_W_PH
315 {1, 3, 0|1<<SDNPHasChain, 0, 0, 308, 18, 4}, // DPSQ_SA_L_W
316 {1, 3, 0|1<<SDNPHasChain, 0, 0, 329, 26, 4}, // DPSQ_S_W_PH
317 {1, 3, 0, 0, 0, 350, 22, 4}, // DPSU_H_QBL
318 {1, 3, 0, 0, 0, 370, 22, 4}, // DPSU_H_QBR
319 {1, 3, 0, 0, 0, 390, 26, 4}, // DPSX_W_PH
320 {1, 3, 0, 0, 0, 409, 26, 4}, // DPS_W_PH
321 {1, 2, 0, 0, 0, 427, 30, 3}, // DivRem
322 {0, 2, 0|1<<SDNPOutGlue, 0, 0, 443, 52, 2}, // DivRem16
323 {1, 2, 0, 0, 0, 461, 30, 3}, // DivRemU
324 {0, 2, 0|1<<SDNPOutGlue, 0, 0, 478, 52, 2}, // DivRemU16
325 {0, 2, 0|1<<SDNPHasChain|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 497, 60, 2}, // EH_RETURN
326 {0, 0, 0|1<<SDNPHasChain|1<<SDNPOptInGlue, 0, 0, 516, 0, 0}, // ERet
327 {1, 2, 0|1<<SDNPHasChain, 0, 0, 530, 0, 3}, // EXTP
328 {1, 2, 0|1<<SDNPHasChain, 0, 0, 544, 0, 3}, // EXTPDP
329 {1, 2, 0|1<<SDNPHasChain, 0, 0, 560, 0, 3}, // EXTR_RS_W
330 {1, 2, 0|1<<SDNPHasChain, 0, 0, 579, 0, 3}, // EXTR_R_W
331 {1, 2, 0|1<<SDNPHasChain, 0, 0, 597, 0, 3}, // EXTR_S_H
332 {1, 2, 0|1<<SDNPHasChain, 0, 0, 615, 0, 3}, // EXTR_W
333 {1, 3, 0, 0, 0, 631, 50, 4}, // Ext
334 {1, 2, 0, 0, 0, 644, 3, 3}, // ExtractElementF64
335 {1, 2, 0, 0, 0, 671, 6, 3}, // ExtractElementF64_FPR
336 {1, 3, 0, 0, 0, 702, 79, 4}, // FMS
337 {0, 3, 0|1<<SDNPHasChain|1<<SDNPOptInGlue, 0, 0, 715, 54, 3}, // FPBrcond
338 {0, 3, 0|1<<SDNPOutGlue, 0, 0, 733, 83, 3}, // FPCmp
339 {1, 3, 0, 0, 0, 748, 90, 3}, // FSELECT
340 {1, 1, 0, 0, 0, 765, 74, 2}, // GPRel
341 {1, 1, 0, 0, 0, 780, 74, 2}, // GotHi
342 {1, 1, 0, 0, 0, 795, 74, 2}, // Hi
343 {1, 1, 0, 0, 0, 807, 74, 2}, // Higher
344 {1, 1, 0, 0, 0, 823, 74, 2}, // Highest
345 {1, 2, 0, 0, 0, 840, 35, 4}, // ILVEV
346 {1, 2, 0, 0, 0, 855, 35, 4}, // ILVL
347 {1, 2, 0, 0, 0, 869, 35, 4}, // ILVOD
348 {1, 2, 0, 0, 0, 884, 35, 4}, // ILVR
349 {1, 4, 0, 0, 0, 898, 69, 5}, // INSVE
350 {1, 4, 0, 0, 0, 913, 49, 5}, // Ins
351 {0, 1, 0|1<<SDNPHasChain|1<<SDNPOutGlue|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 926, 33, 1}, // JmpLink
352 {1, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 943, 59, 3}, // LDL
353 {1, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 956, 59, 3}, // LDR
354 {1, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 969, 59, 3}, // LWL
355 {1, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 982, 59, 3}, // LWR
356 {1, 1, 0, 0, 0, 995, 74, 2}, // Lo
357 {1, 3, 0, 0, 0, 1007, 18, 4}, // MADDU_DSP
358 {1, 3, 0, 0, 0, 1026, 18, 4}, // MADD_DSP
359 {1, 3, 0|1<<SDNPHasChain, 0, 0, 1044, 26, 4}, // MAQ_SA_W_PHL
360 {1, 3, 0|1<<SDNPHasChain, 0, 0, 1066, 26, 4}, // MAQ_SA_W_PHR
361 {1, 3, 0|1<<SDNPHasChain, 0, 0, 1088, 26, 4}, // MAQ_S_W_PHL
362 {1, 3, 0|1<<SDNPHasChain, 0, 0, 1109, 26, 4}, // MAQ_S_W_PHR
363 {1, 3, 0, 0, 0, 1130, 18, 4}, // MAdd
364 {1, 3, 0, 0, 0, 1144, 18, 4}, // MAddu
365 {1, 1, 0, 0, 0, 1159, 57, 2}, // MFHI
366 {1, 1, 0, 0, 0, 1173, 57, 2}, // MFLO
367 {1, 3, 0, 0, 0, 1187, 18, 4}, // MSUBU_DSP
368 {1, 3, 0, 0, 0, 1206, 18, 4}, // MSUB_DSP
369 {1, 3, 0, 0, 0, 1224, 18, 4}, // MSub
370 {1, 3, 0, 0, 0, 1238, 18, 4}, // MSubu
371 {1, 1, 0, 0, 0, 1253, 10, 2}, // MTC1_D64
372 {1, 2, 0|1<<SDNPHasChain, 0, 0, 1271, 15, 3}, // MTHLIP
373 {1, 2, 0, 0, 0, 1287, 30, 3}, // MTLOHI
374 {1, 3, 0|1<<SDNPHasChain, 0, 0, 1303, 26, 4}, // MULSAQ_S_W_PH
375 {1, 3, 0, 0, 0, 1326, 26, 4}, // MULSA_W_PH
376 {1, 3, 0, 0, 0, 1346, 18, 4}, // MULT
377 {1, 3, 0, 0, 0, 1360, 18, 4}, // MULTU
378 {1, 2, 0, 0, 0, 1375, 30, 3}, // Mult
379 {1, 2, 0, 0, 0, 1389, 30, 3}, // Multu
380 {1, 2, 0, 0, 0, 1404, 35, 4}, // PCKEV
381 {1, 2, 0, 0, 0, 1419, 35, 4}, // PCKOD
382 {0, 0, 0|1<<SDNPHasChain|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 1434, 0, 0}, // Ret
383 {0, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 1447, 89, 1}, // SDL
384 {0, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 1460, 89, 1}, // SDR
385 {1, 5, 0, 0, 0, 1473, 93, 4}, // SELECT_CC_DSP
386 {1, 3, 0, 0, 0, 1496, 64, 3}, // SETCC_DSP
387 {1, 2, 0, 0, 0, 1515, 39, 4}, // SHF
388 {1, 2, 0, 0, 0, 1528, 15, 3}, // SHILO
389 {1, 2, 0, 0, 0, 1543, 71, 3}, // SHLL_DSP
390 {1, 2, 0, 0, 0, 1561, 71, 3}, // SHRA_DSP
391 {1, 2, 0, 0, 0, 1579, 71, 3}, // SHRL_DSP
392 {0, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 1597, 89, 1}, // SWL
393 {0, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 1610, 89, 1}, // SWR
394 {0, 1, 0|1<<SDNPHasChain, 0, 0, 1623, 2, 1}, // Sync
395 {0, 1, 0|1<<SDNPHasChain|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 1637, 33, 1}, // TailCall
396 {1, 0, 0, 0, 0, 1655, 34, 1}, // ThreadPointer
397 {1, 1, 0, 0, 0, 1678, 74, 2}, // TlsHi
398 {1, 1, 0, 0, 0, 1693, 67, 2}, // TruncIntFP
399 {1, 1, 0, 0, 0, 1713, 62, 2}, // VALL_NONZERO
400 {1, 1, 0, 0, 0, 1735, 62, 2}, // VALL_ZERO
401 {1, 1, 0, 0, 0, 1754, 62, 2}, // VANY_NONZERO
402 {1, 1, 0, 0, 0, 1776, 62, 2}, // VANY_ZERO
403 {1, 3, 0, 0, 0, 1795, 97, 1}, // VEXTRACT_SEXT_ELT
404 {1, 3, 0, 0, 0, 1822, 97, 1}, // VEXTRACT_ZEXT_ELT
405 {1, 2, 0, 0, 0, 1849, 76, 3}, // VNOR
406 {1, 3, 0, 0, 0, 1863, 43, 6}, // VSHF
407 {1, 2, 0, 0, 0, 1877, 76, 3}, // Wrapper
408};
409
410static const SDNodeInfo MipsGenSDNodeInfo(
411 /*NumOpcodes=*/108, MipsSDNodeDescs, MipsSDNodeNames,
412 MipsVTByHwModeTable, MipsSDTypeConstraints);
413
414} // namespace llvm
415
416#endif // GET_SDNODE_DESC
417
418