1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Subtarget Enumeration Source Fragment *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_SUBTARGETINFO_ENUM
10#undef GET_SUBTARGETINFO_ENUM
11
12namespace llvm {
13
14namespace NVPTX {
15
16enum {
17 PTX32 = 0,
18 PTX40 = 1,
19 PTX41 = 2,
20 PTX42 = 3,
21 PTX43 = 4,
22 PTX50 = 5,
23 PTX60 = 6,
24 PTX61 = 7,
25 PTX62 = 8,
26 PTX63 = 9,
27 PTX64 = 10,
28 PTX65 = 11,
29 PTX70 = 12,
30 PTX71 = 13,
31 PTX72 = 14,
32 PTX73 = 15,
33 PTX74 = 16,
34 PTX75 = 17,
35 PTX76 = 18,
36 PTX77 = 19,
37 PTX78 = 20,
38 PTX80 = 21,
39 PTX81 = 22,
40 PTX82 = 23,
41 PTX83 = 24,
42 PTX84 = 25,
43 PTX85 = 26,
44 PTX86 = 27,
45 PTX87 = 28,
46 PTX88 = 29,
47 PTX90 = 30,
48 PTX91 = 31,
49 PTX92 = 32,
50 PTX93 = 33,
51 PTX94 = 34,
52 SM20 = 35,
53 SM21 = 36,
54 SM30 = 37,
55 SM32 = 38,
56 SM35 = 39,
57 SM37 = 40,
58 SM50 = 41,
59 SM52 = 42,
60 SM53 = 43,
61 SM60 = 44,
62 SM61 = 45,
63 SM62 = 46,
64 SM70 = 47,
65 SM72 = 48,
66 SM75 = 49,
67 SM80 = 50,
68 SM86 = 51,
69 SM87 = 52,
70 SM88 = 53,
71 SM89 = 54,
72 SM90 = 55,
73 SM90a = 56,
74 SM100 = 57,
75 SM100a = 58,
76 SM100f = 59,
77 SM103 = 60,
78 SM103a = 61,
79 SM103f = 62,
80 SM107 = 63,
81 SM107a = 64,
82 SM107f = 65,
83 SM110 = 66,
84 SM110a = 67,
85 SM110f = 68,
86 SM120 = 69,
87 SM120a = 70,
88 SM120f = 71,
89 SM121 = 72,
90 SM121a = 73,
91 SM121f = 74,
92 NumSubtargetFeatures = 75
93};
94
95} // namespace NVPTX
96
97} // namespace llvm
98
99#endif // GET_SUBTARGETINFO_ENUM
100
101#ifdef GET_SUBTARGETINFO_MACRO
102
103GET_SUBTARGETINFO_MACRO(HasArchitecture, false, hasArchitecture)
104GET_SUBTARGETINFO_MACRO(HasArchitecture, false, hasArchitecture)
105GET_SUBTARGETINFO_MACRO(HasArchitecture, false, hasArchitecture)
106GET_SUBTARGETINFO_MACRO(HasArchitecture, false, hasArchitecture)
107GET_SUBTARGETINFO_MACRO(HasArchitecture, false, hasArchitecture)
108GET_SUBTARGETINFO_MACRO(HasArchitecture, false, hasArchitecture)
109GET_SUBTARGETINFO_MACRO(HasArchitecture, false, hasArchitecture)
110GET_SUBTARGETINFO_MACRO(HasArchitecture, false, hasArchitecture)
111GET_SUBTARGETINFO_MACRO(HasArchitecture, false, hasArchitecture)
112GET_SUBTARGETINFO_MACRO(HasArchitecture, false, hasArchitecture)
113GET_SUBTARGETINFO_MACRO(HasArchitecture, false, hasArchitecture)
114GET_SUBTARGETINFO_MACRO(HasArchitecture, false, hasArchitecture)
115GET_SUBTARGETINFO_MACRO(HasArchitecture, false, hasArchitecture)
116GET_SUBTARGETINFO_MACRO(HasArchitecture, false, hasArchitecture)
117GET_SUBTARGETINFO_MACRO(HasArchitecture, false, hasArchitecture)
118GET_SUBTARGETINFO_MACRO(HasArchitecture, false, hasArchitecture)
119GET_SUBTARGETINFO_MACRO(HasArchitecture, false, hasArchitecture)
120GET_SUBTARGETINFO_MACRO(HasArchitecture, false, hasArchitecture)
121GET_SUBTARGETINFO_MACRO(HasArchitecture, false, hasArchitecture)
122GET_SUBTARGETINFO_MACRO(HasArchitecture, false, hasArchitecture)
123GET_SUBTARGETINFO_MACRO(HasArchitecture, false, hasArchitecture)
124GET_SUBTARGETINFO_MACRO(HasArchitecture, false, hasArchitecture)
125GET_SUBTARGETINFO_MACRO(HasArchitecture, false, hasArchitecture)
126GET_SUBTARGETINFO_MACRO(HasArchitecture, false, hasArchitecture)
127GET_SUBTARGETINFO_MACRO(HasArchitecture, false, hasArchitecture)
128GET_SUBTARGETINFO_MACRO(HasArchitecture, false, hasArchitecture)
129GET_SUBTARGETINFO_MACRO(HasArchitecture, false, hasArchitecture)
130GET_SUBTARGETINFO_MACRO(HasArchitecture, false, hasArchitecture)
131GET_SUBTARGETINFO_MACRO(HasArchitecture, false, hasArchitecture)
132GET_SUBTARGETINFO_MACRO(HasArchitecture, false, hasArchitecture)
133GET_SUBTARGETINFO_MACRO(HasArchitecture, false, hasArchitecture)
134GET_SUBTARGETINFO_MACRO(HasArchitecture, false, hasArchitecture)
135GET_SUBTARGETINFO_MACRO(HasArchitecture, false, hasArchitecture)
136GET_SUBTARGETINFO_MACRO(HasArchitecture, false, hasArchitecture)
137GET_SUBTARGETINFO_MACRO(HasArchitecture, false, hasArchitecture)
138GET_SUBTARGETINFO_MACRO(HasArchitecture, false, hasArchitecture)
139GET_SUBTARGETINFO_MACRO(HasArchitecture, false, hasArchitecture)
140GET_SUBTARGETINFO_MACRO(HasArchitecture, false, hasArchitecture)
141GET_SUBTARGETINFO_MACRO(HasArchitecture, false, hasArchitecture)
142GET_SUBTARGETINFO_MACRO(HasArchitecture, false, hasArchitecture)
143
144#undef GET_SUBTARGETINFO_MACRO
145#endif // GET_SUBTARGETINFO_MACRO
146
147#ifdef GET_SUBTARGETINFO_MC_DESC
148#undef GET_SUBTARGETINFO_MC_DESC
149
150namespace llvm {
151
152// Sorted (by key) array of values for CPU features.
153extern const llvm::SubtargetFeatureKVStorage< 75, 1699> NVPTXFeatureKVStorage = {
154 {
155 { sizeof(SubtargetFeatureKV) * 75 + 1, sizeof(SubtargetFeatureKV) * 75 + 7, NVPTX::PTX32, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
156 { sizeof(SubtargetFeatureKV) * 74 + 26, sizeof(SubtargetFeatureKV) * 74 + 32, NVPTX::PTX40, { { { 0x1ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
157 { sizeof(SubtargetFeatureKV) * 73 + 51, sizeof(SubtargetFeatureKV) * 73 + 57, NVPTX::PTX41, { { { 0x3ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
158 { sizeof(SubtargetFeatureKV) * 72 + 76, sizeof(SubtargetFeatureKV) * 72 + 82, NVPTX::PTX42, { { { 0x7ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
159 { sizeof(SubtargetFeatureKV) * 71 + 101, sizeof(SubtargetFeatureKV) * 71 + 107, NVPTX::PTX43, { { { 0xfULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
160 { sizeof(SubtargetFeatureKV) * 70 + 126, sizeof(SubtargetFeatureKV) * 70 + 132, NVPTX::PTX50, { { { 0x1fULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
161 { sizeof(SubtargetFeatureKV) * 69 + 151, sizeof(SubtargetFeatureKV) * 69 + 157, NVPTX::PTX60, { { { 0x3fULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
162 { sizeof(SubtargetFeatureKV) * 68 + 176, sizeof(SubtargetFeatureKV) * 68 + 182, NVPTX::PTX61, { { { 0x7fULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
163 { sizeof(SubtargetFeatureKV) * 67 + 201, sizeof(SubtargetFeatureKV) * 67 + 207, NVPTX::PTX62, { { { 0xffULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
164 { sizeof(SubtargetFeatureKV) * 66 + 226, sizeof(SubtargetFeatureKV) * 66 + 232, NVPTX::PTX63, { { { 0x1ffULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
165 { sizeof(SubtargetFeatureKV) * 65 + 251, sizeof(SubtargetFeatureKV) * 65 + 257, NVPTX::PTX64, { { { 0x3ffULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
166 { sizeof(SubtargetFeatureKV) * 64 + 276, sizeof(SubtargetFeatureKV) * 64 + 282, NVPTX::PTX65, { { { 0x7ffULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
167 { sizeof(SubtargetFeatureKV) * 63 + 301, sizeof(SubtargetFeatureKV) * 63 + 307, NVPTX::PTX70, { { { 0xfffULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
168 { sizeof(SubtargetFeatureKV) * 62 + 326, sizeof(SubtargetFeatureKV) * 62 + 332, NVPTX::PTX71, { { { 0x1fffULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
169 { sizeof(SubtargetFeatureKV) * 61 + 351, sizeof(SubtargetFeatureKV) * 61 + 357, NVPTX::PTX72, { { { 0x3fffULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
170 { sizeof(SubtargetFeatureKV) * 60 + 376, sizeof(SubtargetFeatureKV) * 60 + 382, NVPTX::PTX73, { { { 0x7fffULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
171 { sizeof(SubtargetFeatureKV) * 59 + 401, sizeof(SubtargetFeatureKV) * 59 + 407, NVPTX::PTX74, { { { 0xffffULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
172 { sizeof(SubtargetFeatureKV) * 58 + 426, sizeof(SubtargetFeatureKV) * 58 + 432, NVPTX::PTX75, { { { 0x1ffffULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
173 { sizeof(SubtargetFeatureKV) * 57 + 451, sizeof(SubtargetFeatureKV) * 57 + 457, NVPTX::PTX76, { { { 0x3ffffULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
174 { sizeof(SubtargetFeatureKV) * 56 + 476, sizeof(SubtargetFeatureKV) * 56 + 482, NVPTX::PTX77, { { { 0x7ffffULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
175 { sizeof(SubtargetFeatureKV) * 55 + 501, sizeof(SubtargetFeatureKV) * 55 + 507, NVPTX::PTX78, { { { 0xfffffULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
176 { sizeof(SubtargetFeatureKV) * 54 + 526, sizeof(SubtargetFeatureKV) * 54 + 532, NVPTX::PTX80, { { { 0x1fffffULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
177 { sizeof(SubtargetFeatureKV) * 53 + 551, sizeof(SubtargetFeatureKV) * 53 + 557, NVPTX::PTX81, { { { 0x3fffffULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
178 { sizeof(SubtargetFeatureKV) * 52 + 576, sizeof(SubtargetFeatureKV) * 52 + 582, NVPTX::PTX82, { { { 0x7fffffULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
179 { sizeof(SubtargetFeatureKV) * 51 + 601, sizeof(SubtargetFeatureKV) * 51 + 607, NVPTX::PTX83, { { { 0xffffffULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
180 { sizeof(SubtargetFeatureKV) * 50 + 626, sizeof(SubtargetFeatureKV) * 50 + 632, NVPTX::PTX84, { { { 0x1ffffffULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
181 { sizeof(SubtargetFeatureKV) * 49 + 651, sizeof(SubtargetFeatureKV) * 49 + 657, NVPTX::PTX85, { { { 0x3ffffffULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
182 { sizeof(SubtargetFeatureKV) * 48 + 676, sizeof(SubtargetFeatureKV) * 48 + 682, NVPTX::PTX86, { { { 0x7ffffffULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
183 { sizeof(SubtargetFeatureKV) * 47 + 701, sizeof(SubtargetFeatureKV) * 47 + 707, NVPTX::PTX87, { { { 0xfffffffULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
184 { sizeof(SubtargetFeatureKV) * 46 + 726, sizeof(SubtargetFeatureKV) * 46 + 732, NVPTX::PTX88, { { { 0x1fffffffULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
185 { sizeof(SubtargetFeatureKV) * 45 + 751, sizeof(SubtargetFeatureKV) * 45 + 757, NVPTX::PTX90, { { { 0x3fffffffULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
186 { sizeof(SubtargetFeatureKV) * 44 + 776, sizeof(SubtargetFeatureKV) * 44 + 782, NVPTX::PTX91, { { { 0x7fffffffULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
187 { sizeof(SubtargetFeatureKV) * 43 + 801, sizeof(SubtargetFeatureKV) * 43 + 807, NVPTX::PTX92, { { { 0xffffffffULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
188 { sizeof(SubtargetFeatureKV) * 42 + 826, sizeof(SubtargetFeatureKV) * 42 + 832, NVPTX::PTX93, { { { 0x1ffffffffULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
189 { sizeof(SubtargetFeatureKV) * 41 + 851, sizeof(SubtargetFeatureKV) * 41 + 857, NVPTX::PTX94, { { { 0x3ffffffffULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
190 { sizeof(SubtargetFeatureKV) * 40 + 876, sizeof(SubtargetFeatureKV) * 40 + 883, NVPTX::SM100, { { { 0xfffff800000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
191 { sizeof(SubtargetFeatureKV) * 39 + 897, sizeof(SubtargetFeatureKV) * 39 + 905, NVPTX::SM100a, { { { 0x800000000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
192 { sizeof(SubtargetFeatureKV) * 38 + 920, sizeof(SubtargetFeatureKV) * 38 + 928, NVPTX::SM100f, { { { 0x200000000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
193 { sizeof(SubtargetFeatureKV) * 37 + 943, sizeof(SubtargetFeatureKV) * 37 + 950, NVPTX::SM103, { { { 0x2fffff800000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
194 { sizeof(SubtargetFeatureKV) * 36 + 964, sizeof(SubtargetFeatureKV) * 36 + 972, NVPTX::SM103a, { { { 0x4000000000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
195 { sizeof(SubtargetFeatureKV) * 35 + 987, sizeof(SubtargetFeatureKV) * 35 + 995, NVPTX::SM103f, { { { 0x1800000000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
196 { sizeof(SubtargetFeatureKV) * 34 + 1010, sizeof(SubtargetFeatureKV) * 34 + 1017, NVPTX::SM107, { { { 0x12fffff800000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
197 { sizeof(SubtargetFeatureKV) * 33 + 1031, sizeof(SubtargetFeatureKV) * 33 + 1039, NVPTX::SM107a, { { { 0x0ULL, 0x2ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
198 { sizeof(SubtargetFeatureKV) * 32 + 1054, sizeof(SubtargetFeatureKV) * 32 + 1062, NVPTX::SM107f, { { { 0xc800000000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
199 { sizeof(SubtargetFeatureKV) * 31 + 1077, sizeof(SubtargetFeatureKV) * 31 + 1084, NVPTX::SM110, { { { 0x92fffff800000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
200 { sizeof(SubtargetFeatureKV) * 30 + 1098, sizeof(SubtargetFeatureKV) * 30 + 1106, NVPTX::SM110a, { { { 0x0ULL, 0x10ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
201 { sizeof(SubtargetFeatureKV) * 29 + 1121, sizeof(SubtargetFeatureKV) * 29 + 1129, NVPTX::SM110f, { { { 0x0ULL, 0x4ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
202 { sizeof(SubtargetFeatureKV) * 28 + 1144, sizeof(SubtargetFeatureKV) * 28 + 1151, NVPTX::SM120, { { { 0x92fffff800000000ULL, 0x4ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
203 { sizeof(SubtargetFeatureKV) * 27 + 1165, sizeof(SubtargetFeatureKV) * 27 + 1173, NVPTX::SM120a, { { { 0x0ULL, 0x80ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
204 { sizeof(SubtargetFeatureKV) * 26 + 1188, sizeof(SubtargetFeatureKV) * 26 + 1196, NVPTX::SM120f, { { { 0x0ULL, 0x20ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
205 { sizeof(SubtargetFeatureKV) * 25 + 1211, sizeof(SubtargetFeatureKV) * 25 + 1218, NVPTX::SM121, { { { 0x92fffff800000000ULL, 0x24ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
206 { sizeof(SubtargetFeatureKV) * 24 + 1232, sizeof(SubtargetFeatureKV) * 24 + 1240, NVPTX::SM121a, { { { 0x0ULL, 0x400ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
207 { sizeof(SubtargetFeatureKV) * 23 + 1255, sizeof(SubtargetFeatureKV) * 23 + 1263, NVPTX::SM121f, { { { 0x0ULL, 0x180ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
208 { sizeof(SubtargetFeatureKV) * 22 + 1278, sizeof(SubtargetFeatureKV) * 22 + 1284, NVPTX::SM20, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
209 { sizeof(SubtargetFeatureKV) * 21 + 1297, sizeof(SubtargetFeatureKV) * 21 + 1303, NVPTX::SM21, { { { 0x800000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
210 { sizeof(SubtargetFeatureKV) * 20 + 1316, sizeof(SubtargetFeatureKV) * 20 + 1322, NVPTX::SM30, { { { 0x1800000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
211 { sizeof(SubtargetFeatureKV) * 19 + 1335, sizeof(SubtargetFeatureKV) * 19 + 1341, NVPTX::SM32, { { { 0x3800000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
212 { sizeof(SubtargetFeatureKV) * 18 + 1354, sizeof(SubtargetFeatureKV) * 18 + 1360, NVPTX::SM35, { { { 0x7800000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
213 { sizeof(SubtargetFeatureKV) * 17 + 1373, sizeof(SubtargetFeatureKV) * 17 + 1379, NVPTX::SM37, { { { 0xf800000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
214 { sizeof(SubtargetFeatureKV) * 16 + 1392, sizeof(SubtargetFeatureKV) * 16 + 1398, NVPTX::SM50, { { { 0x1f800000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
215 { sizeof(SubtargetFeatureKV) * 15 + 1411, sizeof(SubtargetFeatureKV) * 15 + 1417, NVPTX::SM52, { { { 0x3f800000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
216 { sizeof(SubtargetFeatureKV) * 14 + 1430, sizeof(SubtargetFeatureKV) * 14 + 1436, NVPTX::SM53, { { { 0x7f800000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
217 { sizeof(SubtargetFeatureKV) * 13 + 1449, sizeof(SubtargetFeatureKV) * 13 + 1455, NVPTX::SM60, { { { 0xff800000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
218 { sizeof(SubtargetFeatureKV) * 12 + 1468, sizeof(SubtargetFeatureKV) * 12 + 1474, NVPTX::SM61, { { { 0x1ff800000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
219 { sizeof(SubtargetFeatureKV) * 11 + 1487, sizeof(SubtargetFeatureKV) * 11 + 1493, NVPTX::SM62, { { { 0x3ff800000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
220 { sizeof(SubtargetFeatureKV) * 10 + 1506, sizeof(SubtargetFeatureKV) * 10 + 1512, NVPTX::SM70, { { { 0x7ff800000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
221 { sizeof(SubtargetFeatureKV) * 9 + 1525, sizeof(SubtargetFeatureKV) * 9 + 1531, NVPTX::SM72, { { { 0xfff800000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
222 { sizeof(SubtargetFeatureKV) * 8 + 1544, sizeof(SubtargetFeatureKV) * 8 + 1550, NVPTX::SM75, { { { 0x1fff800000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
223 { sizeof(SubtargetFeatureKV) * 7 + 1563, sizeof(SubtargetFeatureKV) * 7 + 1569, NVPTX::SM80, { { { 0x3fff800000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
224 { sizeof(SubtargetFeatureKV) * 6 + 1582, sizeof(SubtargetFeatureKV) * 6 + 1588, NVPTX::SM86, { { { 0x7fff800000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
225 { sizeof(SubtargetFeatureKV) * 5 + 1601, sizeof(SubtargetFeatureKV) * 5 + 1607, NVPTX::SM87, { { { 0xffff800000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
226 { sizeof(SubtargetFeatureKV) * 4 + 1620, sizeof(SubtargetFeatureKV) * 4 + 1626, NVPTX::SM88, { { { 0x1ffff800000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
227 { sizeof(SubtargetFeatureKV) * 3 + 1639, sizeof(SubtargetFeatureKV) * 3 + 1645, NVPTX::SM89, { { { 0x3ffff800000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
228 { sizeof(SubtargetFeatureKV) * 2 + 1658, sizeof(SubtargetFeatureKV) * 2 + 1664, NVPTX::SM90, { { { 0x7ffff800000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
229 { sizeof(SubtargetFeatureKV) * 1 + 1677, sizeof(SubtargetFeatureKV) * 1 + 1684, NVPTX::SM90a, { { { 0x80000000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
230 },
231 "\000ptx32\000Use PTX version 32\000ptx40\000Use PTX version 40\000ptx41"
232 "\000Use PTX version 41\000ptx42\000Use PTX version 42\000ptx43\000Use P"
233 "TX version 43\000ptx50\000Use PTX version 50\000ptx60\000Use PTX versio"
234 "n 60\000ptx61\000Use PTX version 61\000ptx62\000Use PTX version 62\000p"
235 "tx63\000Use PTX version 63\000ptx64\000Use PTX version 64\000ptx65\000U"
236 "se PTX version 65\000ptx70\000Use PTX version 70\000ptx71\000Use PTX ve"
237 "rsion 71\000ptx72\000Use PTX version 72\000ptx73\000Use PTX version 73\000"
238 "ptx74\000Use PTX version 74\000ptx75\000Use PTX version 75\000ptx76\000"
239 "Use PTX version 76\000ptx77\000Use PTX version 77\000ptx78\000Use PTX v"
240 "ersion 78\000ptx80\000Use PTX version 80\000ptx81\000Use PTX version 81"
241 "\000ptx82\000Use PTX version 82\000ptx83\000Use PTX version 83\000ptx84"
242 "\000Use PTX version 84\000ptx85\000Use PTX version 85\000ptx86\000Use P"
243 "TX version 86\000ptx87\000Use PTX version 87\000ptx88\000Use PTX versio"
244 "n 88\000ptx90\000Use PTX version 90\000ptx91\000Use PTX version 91\000p"
245 "tx92\000Use PTX version 92\000ptx93\000Use PTX version 93\000ptx94\000U"
246 "se PTX version 94\000sm_100\000Target SM 100\000sm_100a\000Target SM 10"
247 "0a\000sm_100f\000Target SM 100f\000sm_103\000Target SM 103\000sm_103a\000"
248 "Target SM 103a\000sm_103f\000Target SM 103f\000sm_107\000Target SM 107\000"
249 "sm_107a\000Target SM 107a\000sm_107f\000Target SM 107f\000sm_110\000Tar"
250 "get SM 110\000sm_110a\000Target SM 110a\000sm_110f\000Target SM 110f\000"
251 "sm_120\000Target SM 120\000sm_120a\000Target SM 120a\000sm_120f\000Targ"
252 "et SM 120f\000sm_121\000Target SM 121\000sm_121a\000Target SM 121a\000s"
253 "m_121f\000Target SM 121f\000sm_20\000Target SM 20\000sm_21\000Target SM"
254 " 21\000sm_30\000Target SM 30\000sm_32\000Target SM 32\000sm_35\000Targe"
255 "t SM 35\000sm_37\000Target SM 37\000sm_50\000Target SM 50\000sm_52\000T"
256 "arget SM 52\000sm_53\000Target SM 53\000sm_60\000Target SM 60\000sm_61\000"
257 "Target SM 61\000sm_62\000Target SM 62\000sm_70\000Target SM 70\000sm_72"
258 "\000Target SM 72\000sm_75\000Target SM 75\000sm_80\000Target SM 80\000s"
259 "m_86\000Target SM 86\000sm_87\000Target SM 87\000sm_88\000Target SM 88\000"
260 "sm_89\000Target SM 89\000sm_90\000Target SM 90\000sm_90a\000Target SM 9"
261 "0a\000"};
262
263#ifdef DBGFIELD
264#error "<target>GenSubtargetInfo.inc requires a DBGFIELD macro"
265#endif
266#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
267#define DBGFIELD(x) x,
268#define DBGVAL_OR_NULLPTR(x) x
269#else
270#define DBGFIELD(x)
271#define DBGVAL_OR_NULLPTR(x) nullptr
272#endif
273
274// ===============================================================
275// Data tables for the new per-operand machine model.
276
277static_assert(0 <= UINT8_MAX, "NumWriteProcResEntries does not fit in uint8_t");
278static_assert(0 <= UINT8_MAX, "NumWriteLatencyEntries does not fit in uint8_t");
279
280// {ProcResourceIdx, ReleaseAtCycle, AcquireAtCycle}
281extern const llvm::MCWriteProcResEntry NVPTXWriteProcResTable[] = {
282 { 0, 0, 0 }, // Invalid
283}; // NVPTXWriteProcResTable
284
285// {Cycles, WriteResourceID}
286extern const llvm::MCWriteLatencyEntry NVPTXWriteLatencyTable[] = {
287 { 0, 0}, // Invalid
288}; // NVPTXWriteLatencyTable
289
290// {UseIdx, WriteResourceID, Cycles}
291extern const llvm::MCReadAdvanceEntry NVPTXReadAdvanceTable[] = {
292 {0, 0, 0}, // Invalid
293}; // NVPTXReadAdvanceTable
294
295#ifdef __GNUC__
296#pragma GCC diagnostic push
297#pragma GCC diagnostic ignored "-Woverlength-strings"
298#endif
299static constexpr char NVPTXSchedClassNamesStorage[] =
300 "\0"
301 "InvalidSchedClass\0"
302 ;
303#ifdef __GNUC__
304#pragma GCC diagnostic pop
305#endif
306
307static constexpr llvm::StringTable
308NVPTXSchedClassNames = NVPTXSchedClassNamesStorage;
309
310extern const llvm::MCSchedModel NVPTXSchedModels[] = {
311{ // NoSchedModel
312 MCSchedModel::DefaultIssueWidth,
313 MCSchedModel::DefaultMicroOpBufferSize,
314 MCSchedModel::DefaultLoopMicroOpBufferSize,
315 MCSchedModel::DefaultLoadLatency,
316 MCSchedModel::DefaultHighLatency,
317 MCSchedModel::DefaultMispredictPenalty,
318 false, // PostRAScheduler
319 false, // CompleteModel
320 false, // EnableIntervals
321 0, // Processor ID
322 nullptr, nullptr, 0, 0, // No instruction-level machine model.
323 DBGVAL_OR_NULLPTR(&NVPTXSchedClassNames), // SchedClassNames
324 nullptr, // No Itinerary
325 nullptr // No extra processor descriptor
326 },
327};
328
329#undef DBGFIELD
330
331#undef DBGVAL_OR_NULLPTR
332
333static constexpr size_t NVPTXCPUAliasArraySize = sizeof(std::array<SubtargetSubTypeAliasKV, 3>);
334// Sorted (by key) array of values for CPU subtype.
335extern const llvm::SubtargetSubTypeKVStorage< 40, 3, 296> NVPTXSubTypeKVStorage = {
336 {
337 { sizeof(SubtargetSubTypeKV) * 40 + NVPTXCPUAliasArraySize + 1, { { { 0x200000000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
338 { sizeof(SubtargetSubTypeKV) * 39 + NVPTXCPUAliasArraySize + 8, { { { 0x400000000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
339 { sizeof(SubtargetSubTypeKV) * 38 + NVPTXCPUAliasArraySize + 16, { { { 0x800000000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
340 { sizeof(SubtargetSubTypeKV) * 37 + NVPTXCPUAliasArraySize + 47, { { { 0x1000000000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
341 { sizeof(SubtargetSubTypeKV) * 36 + NVPTXCPUAliasArraySize + 54, { { { 0x2000000000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
342 { sizeof(SubtargetSubTypeKV) * 35 + NVPTXCPUAliasArraySize + 62, { { { 0x4000000000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
343 { sizeof(SubtargetSubTypeKV) * 34 + NVPTXCPUAliasArraySize + 70, { { { 0x8000000000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
344 { sizeof(SubtargetSubTypeKV) * 33 + NVPTXCPUAliasArraySize + 77, { { { 0x0ULL, 0x1ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
345 { sizeof(SubtargetSubTypeKV) * 32 + NVPTXCPUAliasArraySize + 85, { { { 0x0ULL, 0x2ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
346 { sizeof(SubtargetSubTypeKV) * 31 + NVPTXCPUAliasArraySize + 93, { { { 0x0ULL, 0x4ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
347 { sizeof(SubtargetSubTypeKV) * 30 + NVPTXCPUAliasArraySize + 100, { { { 0x0ULL, 0x8ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
348 { sizeof(SubtargetSubTypeKV) * 29 + NVPTXCPUAliasArraySize + 108, { { { 0x0ULL, 0x10ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
349 { sizeof(SubtargetSubTypeKV) * 28 + NVPTXCPUAliasArraySize + 116, { { { 0x0ULL, 0x20ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
350 { sizeof(SubtargetSubTypeKV) * 27 + NVPTXCPUAliasArraySize + 123, { { { 0x0ULL, 0x40ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
351 { sizeof(SubtargetSubTypeKV) * 26 + NVPTXCPUAliasArraySize + 131, { { { 0x0ULL, 0x80ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
352 { sizeof(SubtargetSubTypeKV) * 25 + NVPTXCPUAliasArraySize + 139, { { { 0x0ULL, 0x100ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
353 { sizeof(SubtargetSubTypeKV) * 24 + NVPTXCPUAliasArraySize + 146, { { { 0x0ULL, 0x200ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
354 { sizeof(SubtargetSubTypeKV) * 23 + NVPTXCPUAliasArraySize + 154, { { { 0x0ULL, 0x400ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
355 { sizeof(SubtargetSubTypeKV) * 22 + NVPTXCPUAliasArraySize + 162, { { { 0x800000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
356 { sizeof(SubtargetSubTypeKV) * 21 + NVPTXCPUAliasArraySize + 168, { { { 0x1000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
357 { sizeof(SubtargetSubTypeKV) * 20 + NVPTXCPUAliasArraySize + 174, { { { 0x2000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
358 { sizeof(SubtargetSubTypeKV) * 19 + NVPTXCPUAliasArraySize + 180, { { { 0x4000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
359 { sizeof(SubtargetSubTypeKV) * 18 + NVPTXCPUAliasArraySize + 186, { { { 0x8000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
360 { sizeof(SubtargetSubTypeKV) * 17 + NVPTXCPUAliasArraySize + 192, { { { 0x10000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
361 { sizeof(SubtargetSubTypeKV) * 16 + NVPTXCPUAliasArraySize + 198, { { { 0x20000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
362 { sizeof(SubtargetSubTypeKV) * 15 + NVPTXCPUAliasArraySize + 204, { { { 0x40000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
363 { sizeof(SubtargetSubTypeKV) * 14 + NVPTXCPUAliasArraySize + 210, { { { 0x80000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
364 { sizeof(SubtargetSubTypeKV) * 13 + NVPTXCPUAliasArraySize + 216, { { { 0x100000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
365 { sizeof(SubtargetSubTypeKV) * 12 + NVPTXCPUAliasArraySize + 222, { { { 0x200000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
366 { sizeof(SubtargetSubTypeKV) * 11 + NVPTXCPUAliasArraySize + 228, { { { 0x400000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
367 { sizeof(SubtargetSubTypeKV) * 10 + NVPTXCPUAliasArraySize + 234, { { { 0x800000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
368 { sizeof(SubtargetSubTypeKV) * 9 + NVPTXCPUAliasArraySize + 240, { { { 0x1000000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
369 { sizeof(SubtargetSubTypeKV) * 8 + NVPTXCPUAliasArraySize + 246, { { { 0x2000000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
370 { sizeof(SubtargetSubTypeKV) * 7 + NVPTXCPUAliasArraySize + 252, { { { 0x4000000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
371 { sizeof(SubtargetSubTypeKV) * 6 + NVPTXCPUAliasArraySize + 258, { { { 0x8000000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
372 { sizeof(SubtargetSubTypeKV) * 5 + NVPTXCPUAliasArraySize + 264, { { { 0x10000000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
373 { sizeof(SubtargetSubTypeKV) * 4 + NVPTXCPUAliasArraySize + 270, { { { 0x20000000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
374 { sizeof(SubtargetSubTypeKV) * 3 + NVPTXCPUAliasArraySize + 276, { { { 0x40000000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
375 { sizeof(SubtargetSubTypeKV) * 2 + NVPTXCPUAliasArraySize + 282, { { { 0x80000000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
376 { sizeof(SubtargetSubTypeKV) * 1 + NVPTXCPUAliasArraySize + 288, { { { 0x100000000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
377 },
378 { {
379 { sizeof(SubtargetSubTypeAliasKV) * 3 + 24, 9 },
380 { sizeof(SubtargetSubTypeAliasKV) * 2 + 31, 10 },
381 { sizeof(SubtargetSubTypeAliasKV) * 1 + 39, 11 },
382 } },
383 "\000sm_100\000sm_100a\000sm_100f\000sm_101\000sm_101a\000sm_101f\000sm_"
384 "103\000sm_103a\000sm_103f\000sm_107\000sm_107a\000sm_107f\000sm_110\000"
385 "sm_110a\000sm_110f\000sm_120\000sm_120a\000sm_120f\000sm_121\000sm_121a"
386 "\000sm_121f\000sm_20\000sm_21\000sm_30\000sm_32\000sm_35\000sm_37\000sm"
387 "_50\000sm_52\000sm_53\000sm_60\000sm_61\000sm_62\000sm_70\000sm_72\000s"
388 "m_75\000sm_80\000sm_86\000sm_87\000sm_88\000sm_89\000sm_90\000sm_90a\000"};
389
390namespace NVPTX_MC {
391
392unsigned resolveVariantSchedClassImpl(unsigned SchedClass,
393 const MCInst *MI, const MCInstrInfo *MCII, const MCSubtargetInfo &STI, unsigned CPUID) {
394 // Don't know how to resolve this scheduling class.
395 return 0;
396}
397
398} // namespace NVPTX_MC
399struct NVPTXGenMCSubtargetInfo : public MCSubtargetInfo {
400 NVPTXGenMCSubtargetInfo(const Triple &TT,
401 StringRef CPU, StringRef TuneCPU, StringRef FS,
402 StringTable PN,
403 ArrayRef<SubtargetFeatureKV> PF,
404 ArrayRef<SubtargetSubTypeKV> PD,
405 ArrayRef<SubtargetSubTypeAliasKV> PA,
406 const MCSchedModel *PSM,
407 const MCWriteProcResEntry *WPR,
408 const MCWriteLatencyEntry *WL,
409 const MCReadAdvanceEntry *RA, const InstrStage *IS,
410 const unsigned *OC, const unsigned *FP) :
411 MCSubtargetInfo(TT, CPU, TuneCPU, FS, PN, PF, PD, PA, PSM,
412 WPR, WL, RA, IS, OC, FP) { }
413
414 unsigned resolveVariantSchedClass(unsigned SchedClass,
415 const MCInst *MI, const MCInstrInfo *MCII,
416 unsigned CPUID) const final {
417 return NVPTX_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, *this, CPUID);
418 }
419 unsigned getHwModeSet() const final;
420 unsigned getHwMode(enum HwModeType type = HwMode_Default) const final;
421};
422unsigned NVPTXGenMCSubtargetInfo::getHwModeSet() const {
423 [[maybe_unused]] const FeatureBitset &FB = getFeatureBits();
424 // Collect HwModes and store them as a bit set.
425 unsigned Modes = 0;
426 if (false) Modes |= (1 << 0);
427 return Modes;
428}
429unsigned NVPTXGenMCSubtargetInfo::getHwMode(enum HwModeType type) const {
430 unsigned Modes = getHwModeSet();
431
432 if (!Modes)
433 return Modes;
434
435 switch (type) {
436 case HwMode_Default:
437 return llvm::countr_zero(Modes) + 1;
438 case HwMode_ValueType:
439 // No HwMode for ValueType.
440 return 0;
441 case HwMode_RegInfo:
442 Modes &= 1;
443 if (!Modes)
444 return Modes;
445 if (!llvm::has_single_bit<unsigned>(Modes))
446 llvm_unreachable("Two or more HwModes for RegInfo were found!");
447 return llvm::countr_zero(Modes) + 1;
448 case HwMode_EncodingInfo:
449 // No HwMode for EncodingInfo.
450 return 0;
451 }
452 llvm_unreachable("unexpected HwModeType");
453 return 0; // should not get here
454}
455
456static inline MCSubtargetInfo *createNVPTXMCSubtargetInfoImpl(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS) {
457 return new NVPTXGenMCSubtargetInfo(TT, CPU, TuneCPU, FS, StringTable(NVPTXSubTypeKVStorage.Strings), NVPTXFeatureKVStorage.Features, NVPTXSubTypeKVStorage.SubTypes, ArrayRef(NVPTXSubTypeKVStorage.Aliases).take_front(3), NVPTXSchedModels,
458 NVPTXWriteProcResTable, NVPTXWriteLatencyTable, NVPTXReadAdvanceTable,
459 nullptr, nullptr, nullptr);
460}
461
462
463} // namespace llvm
464
465#endif // GET_SUBTARGETINFO_MC_DESC
466
467#ifdef GET_SUBTARGETINFO_TARGET_DESC
468#undef GET_SUBTARGETINFO_TARGET_DESC
469
470#include "llvm/ADT/BitmaskEnum.h"
471#include "llvm/Support/Debug.h"
472#include "llvm/Support/raw_ostream.h"
473
474// ParseSubtargetFeatures - Parses features string setting specified
475// subtarget options.
476void llvm::NVPTXSubtarget::ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS) {
477 LLVM_DEBUG(dbgs() << "\nFeatures:" << FS);
478 LLVM_DEBUG(dbgs() << "\nCPU:" << CPU);
479 LLVM_DEBUG(dbgs() << "\nTuneCPU:" << TuneCPU << "\n\n");
480 InitMCProcessorInfo(CPU, TuneCPU, FS);
481 const FeatureBitset &Bits = getFeatureBits();
482 if (Bits[NVPTX::PTX32] && PTXVersion < 32) PTXVersion = 32;
483 if (Bits[NVPTX::PTX40] && PTXVersion < 40) PTXVersion = 40;
484 if (Bits[NVPTX::PTX41] && PTXVersion < 41) PTXVersion = 41;
485 if (Bits[NVPTX::PTX42] && PTXVersion < 42) PTXVersion = 42;
486 if (Bits[NVPTX::PTX43] && PTXVersion < 43) PTXVersion = 43;
487 if (Bits[NVPTX::PTX50] && PTXVersion < 50) PTXVersion = 50;
488 if (Bits[NVPTX::PTX60] && PTXVersion < 60) PTXVersion = 60;
489 if (Bits[NVPTX::PTX61] && PTXVersion < 61) PTXVersion = 61;
490 if (Bits[NVPTX::PTX62] && PTXVersion < 62) PTXVersion = 62;
491 if (Bits[NVPTX::PTX63] && PTXVersion < 63) PTXVersion = 63;
492 if (Bits[NVPTX::PTX64] && PTXVersion < 64) PTXVersion = 64;
493 if (Bits[NVPTX::PTX65] && PTXVersion < 65) PTXVersion = 65;
494 if (Bits[NVPTX::PTX70] && PTXVersion < 70) PTXVersion = 70;
495 if (Bits[NVPTX::PTX71] && PTXVersion < 71) PTXVersion = 71;
496 if (Bits[NVPTX::PTX72] && PTXVersion < 72) PTXVersion = 72;
497 if (Bits[NVPTX::PTX73] && PTXVersion < 73) PTXVersion = 73;
498 if (Bits[NVPTX::PTX74] && PTXVersion < 74) PTXVersion = 74;
499 if (Bits[NVPTX::PTX75] && PTXVersion < 75) PTXVersion = 75;
500 if (Bits[NVPTX::PTX76] && PTXVersion < 76) PTXVersion = 76;
501 if (Bits[NVPTX::PTX77] && PTXVersion < 77) PTXVersion = 77;
502 if (Bits[NVPTX::PTX78] && PTXVersion < 78) PTXVersion = 78;
503 if (Bits[NVPTX::PTX80] && PTXVersion < 80) PTXVersion = 80;
504 if (Bits[NVPTX::PTX81] && PTXVersion < 81) PTXVersion = 81;
505 if (Bits[NVPTX::PTX82] && PTXVersion < 82) PTXVersion = 82;
506 if (Bits[NVPTX::PTX83] && PTXVersion < 83) PTXVersion = 83;
507 if (Bits[NVPTX::PTX84] && PTXVersion < 84) PTXVersion = 84;
508 if (Bits[NVPTX::PTX85] && PTXVersion < 85) PTXVersion = 85;
509 if (Bits[NVPTX::PTX86] && PTXVersion < 86) PTXVersion = 86;
510 if (Bits[NVPTX::PTX87] && PTXVersion < 87) PTXVersion = 87;
511 if (Bits[NVPTX::PTX88] && PTXVersion < 88) PTXVersion = 88;
512 if (Bits[NVPTX::PTX90] && PTXVersion < 90) PTXVersion = 90;
513 if (Bits[NVPTX::PTX91] && PTXVersion < 91) PTXVersion = 91;
514 if (Bits[NVPTX::PTX92] && PTXVersion < 92) PTXVersion = 92;
515 if (Bits[NVPTX::PTX93] && PTXVersion < 93) PTXVersion = 93;
516 if (Bits[NVPTX::PTX94] && PTXVersion < 94) PTXVersion = 94;
517 if (Bits[NVPTX::SM20]) HasArchitecture = true;
518 if (Bits[NVPTX::SM21]) HasArchitecture = true;
519 if (Bits[NVPTX::SM30]) HasArchitecture = true;
520 if (Bits[NVPTX::SM32]) HasArchitecture = true;
521 if (Bits[NVPTX::SM35]) HasArchitecture = true;
522 if (Bits[NVPTX::SM37]) HasArchitecture = true;
523 if (Bits[NVPTX::SM50]) HasArchitecture = true;
524 if (Bits[NVPTX::SM52]) HasArchitecture = true;
525 if (Bits[NVPTX::SM53]) HasArchitecture = true;
526 if (Bits[NVPTX::SM60]) HasArchitecture = true;
527 if (Bits[NVPTX::SM61]) HasArchitecture = true;
528 if (Bits[NVPTX::SM62]) HasArchitecture = true;
529 if (Bits[NVPTX::SM70]) HasArchitecture = true;
530 if (Bits[NVPTX::SM72]) HasArchitecture = true;
531 if (Bits[NVPTX::SM75]) HasArchitecture = true;
532 if (Bits[NVPTX::SM80]) HasArchitecture = true;
533 if (Bits[NVPTX::SM86]) HasArchitecture = true;
534 if (Bits[NVPTX::SM87]) HasArchitecture = true;
535 if (Bits[NVPTX::SM88]) HasArchitecture = true;
536 if (Bits[NVPTX::SM89]) HasArchitecture = true;
537 if (Bits[NVPTX::SM90]) HasArchitecture = true;
538 if (Bits[NVPTX::SM90a]) HasArchitecture = true;
539 if (Bits[NVPTX::SM100]) HasArchitecture = true;
540 if (Bits[NVPTX::SM100a]) HasArchitecture = true;
541 if (Bits[NVPTX::SM100f]) HasArchitecture = true;
542 if (Bits[NVPTX::SM103]) HasArchitecture = true;
543 if (Bits[NVPTX::SM103a]) HasArchitecture = true;
544 if (Bits[NVPTX::SM103f]) HasArchitecture = true;
545 if (Bits[NVPTX::SM107]) HasArchitecture = true;
546 if (Bits[NVPTX::SM107a]) HasArchitecture = true;
547 if (Bits[NVPTX::SM107f]) HasArchitecture = true;
548 if (Bits[NVPTX::SM110]) HasArchitecture = true;
549 if (Bits[NVPTX::SM110a]) HasArchitecture = true;
550 if (Bits[NVPTX::SM110f]) HasArchitecture = true;
551 if (Bits[NVPTX::SM120]) HasArchitecture = true;
552 if (Bits[NVPTX::SM120a]) HasArchitecture = true;
553 if (Bits[NVPTX::SM120f]) HasArchitecture = true;
554 if (Bits[NVPTX::SM121]) HasArchitecture = true;
555 if (Bits[NVPTX::SM121a]) HasArchitecture = true;
556 if (Bits[NVPTX::SM121f]) HasArchitecture = true;
557}
558
559#endif // GET_SUBTARGETINFO_TARGET_DESC
560
561#ifdef GET_SUBTARGETINFO_HEADER
562#undef GET_SUBTARGETINFO_HEADER
563
564namespace llvm {
565
566class DFAPacketizer;
567namespace NVPTX_MC {
568
569unsigned resolveVariantSchedClassImpl(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, const MCSubtargetInfo &STI, unsigned CPUID);
570
571} // namespace NVPTX_MC
572struct NVPTXGenSubtargetInfo : public TargetSubtargetInfo {
573 explicit NVPTXGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS);
574public:
575 unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const final;
576 unsigned resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const final;
577 DFAPacketizer *createDFAPacketizer(const InstrItineraryData *IID) const;
578 enum class NVPTXHwModeBits : unsigned {
579 DefaultMode = 0,
580 NVPTX64 = (1 << 0),
581
582 LLVM_MARK_AS_BITMASK_ENUM(/*LargestValue=*/NVPTX64),
583 };
584 unsigned getHwModeSet() const final;
585 unsigned getHwMode(enum HwModeType type = HwMode_Default) const final;
586 const FeatureBitset &getInlineIgnoreFeatures() const override;
587 const FeatureBitset &getInlineInverseFeatures() const override;
588 const FeatureBitset &getInlineMustMatchFeatures() const override;
589};
590
591} // namespace llvm
592
593#endif // GET_SUBTARGETINFO_HEADER
594
595#ifdef GET_SUBTARGETINFO_CTOR
596#undef GET_SUBTARGETINFO_CTOR
597
598#include "llvm/CodeGen/TargetSchedule.h"
599
600namespace llvm {
601
602extern const llvm::StringRef NVPTXNames[];
603extern const llvm::SubtargetFeatureKVStorage<75, 1699> NVPTXFeatureKVStorage;
604extern const llvm::SubtargetSubTypeKVStorage<40, 3, 296> NVPTXSubTypeKVStorage;
605extern const llvm::MCSchedModel NVPTXSchedModels[];
606extern const llvm::MCWriteProcResEntry NVPTXWriteProcResTable[];
607extern const llvm::MCWriteLatencyEntry NVPTXWriteLatencyTable[];
608extern const llvm::MCReadAdvanceEntry NVPTXReadAdvanceTable[];
609NVPTXGenSubtargetInfo::NVPTXGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS)
610 : TargetSubtargetInfo(TT, CPU, TuneCPU, FS, StringTable(NVPTXSubTypeKVStorage.Strings), ArrayRef(NVPTXFeatureKVStorage.Features), ArrayRef(NVPTXSubTypeKVStorage.SubTypes), ArrayRef(NVPTXSubTypeKVStorage.Aliases).take_front(3), NVPTXSchedModels,
611 NVPTXWriteProcResTable, NVPTXWriteLatencyTable, NVPTXReadAdvanceTable,
612 nullptr, nullptr, nullptr) {}
613
614unsigned NVPTXGenSubtargetInfo
615::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const {
616 report_fatal_error("Expected a variant SchedClass");
617} // NVPTXGenSubtargetInfo::resolveSchedClass
618
619unsigned NVPTXGenSubtargetInfo
620::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const {
621 return NVPTX_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, *this, CPUID);
622} // NVPTXGenSubtargetInfo::resolveVariantSchedClass
623
624unsigned NVPTXGenSubtargetInfo::getHwModeSet() const {
625 [[maybe_unused]] const auto *Subtarget =
626 static_cast<const NVPTXSubtarget *>(this);
627 // Collect HwModes and store them as a bit set.
628 unsigned Modes = 0;
629 if ((Subtarget->getTargetTriple().getArch() == Triple::nvptx64)) Modes |= (1 << 0);
630 return Modes;
631}
632unsigned NVPTXGenSubtargetInfo::getHwMode(enum HwModeType type) const {
633 unsigned Modes = getHwModeSet();
634
635 if (!Modes)
636 return Modes;
637
638 switch (type) {
639 case HwMode_Default:
640 return llvm::countr_zero(Modes) + 1;
641 case HwMode_ValueType:
642 // No HwMode for ValueType.
643 return 0;
644 case HwMode_RegInfo:
645 Modes &= 1;
646 if (!Modes)
647 return Modes;
648 if (!llvm::has_single_bit<unsigned>(Modes))
649 llvm_unreachable("Two or more HwModes for RegInfo were found!");
650 return llvm::countr_zero(Modes) + 1;
651 case HwMode_EncodingInfo:
652 // No HwMode for EncodingInfo.
653 return 0;
654 }
655 llvm_unreachable("unexpected HwModeType");
656 return 0; // should not get here
657}
658const FeatureBitset &NVPTXGenSubtargetInfo::getInlineIgnoreFeatures() const {
659 static constexpr FeatureBitset Features = {
660 };
661 return Features;
662}
663
664const FeatureBitset &NVPTXGenSubtargetInfo::getInlineInverseFeatures() const {
665 static constexpr FeatureBitset Features = {
666 };
667 return Features;
668}
669
670const FeatureBitset &NVPTXGenSubtargetInfo::getInlineMustMatchFeatures() const {
671 static constexpr FeatureBitset Features = {
672 };
673 return Features;
674}
675
676
677} // namespace llvm
678
679#endif // GET_SUBTARGETINFO_CTOR
680
681#ifdef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
682#undef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
683
684
685#endif // GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
686
687#ifdef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
688#undef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
689
690
691#endif // GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
692
693