1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Subtarget Enumeration Source Fragment *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_SUBTARGETINFO_ENUM
10#undef GET_SUBTARGETINFO_ENUM
11
12namespace llvm {
13
14namespace NVPTX {
15
16enum {
17 PTX32 = 0,
18 PTX40 = 1,
19 PTX41 = 2,
20 PTX42 = 3,
21 PTX43 = 4,
22 PTX50 = 5,
23 PTX60 = 6,
24 PTX61 = 7,
25 PTX62 = 8,
26 PTX63 = 9,
27 PTX64 = 10,
28 PTX65 = 11,
29 PTX70 = 12,
30 PTX71 = 13,
31 PTX72 = 14,
32 PTX73 = 15,
33 PTX74 = 16,
34 PTX75 = 17,
35 PTX76 = 18,
36 PTX77 = 19,
37 PTX78 = 20,
38 PTX80 = 21,
39 PTX81 = 22,
40 PTX82 = 23,
41 PTX83 = 24,
42 PTX84 = 25,
43 PTX85 = 26,
44 PTX86 = 27,
45 PTX87 = 28,
46 PTX88 = 29,
47 PTX90 = 30,
48 PTX91 = 31,
49 SM20 = 32,
50 SM21 = 33,
51 SM30 = 34,
52 SM32 = 35,
53 SM35 = 36,
54 SM37 = 37,
55 SM50 = 38,
56 SM52 = 39,
57 SM53 = 40,
58 SM60 = 41,
59 SM61 = 42,
60 SM62 = 43,
61 SM70 = 44,
62 SM72 = 45,
63 SM75 = 46,
64 SM80 = 47,
65 SM86 = 48,
66 SM87 = 49,
67 SM88 = 50,
68 SM89 = 51,
69 SM90 = 52,
70 SM90a = 53,
71 SM100 = 54,
72 SM100a = 55,
73 SM100f = 56,
74 SM101 = 57,
75 SM101a = 58,
76 SM101f = 59,
77 SM103 = 60,
78 SM103a = 61,
79 SM103f = 62,
80 SM110 = 63,
81 SM110a = 64,
82 SM110f = 65,
83 SM120 = 66,
84 SM120a = 67,
85 SM120f = 68,
86 SM121 = 69,
87 SM121a = 70,
88 SM121f = 71,
89 NumSubtargetFeatures = 72
90};
91
92} // namespace NVPTX
93
94} // namespace llvm
95
96#endif // GET_SUBTARGETINFO_ENUM
97
98#ifdef GET_SUBTARGETINFO_MACRO
99
100
101#undef GET_SUBTARGETINFO_MACRO
102#endif // GET_SUBTARGETINFO_MACRO
103
104#ifdef GET_SUBTARGETINFO_MC_DESC
105#undef GET_SUBTARGETINFO_MC_DESC
106
107namespace llvm {
108
109// Sorted (by key) array of values for CPU features.
110extern const llvm::SubtargetFeatureKV NVPTXFeatureKV[] = {
111 { "ptx32", "Use PTX version 32", NVPTX::PTX32, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
112 { "ptx40", "Use PTX version 40", NVPTX::PTX40, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
113 { "ptx41", "Use PTX version 41", NVPTX::PTX41, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
114 { "ptx42", "Use PTX version 42", NVPTX::PTX42, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
115 { "ptx43", "Use PTX version 43", NVPTX::PTX43, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
116 { "ptx50", "Use PTX version 50", NVPTX::PTX50, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
117 { "ptx60", "Use PTX version 60", NVPTX::PTX60, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
118 { "ptx61", "Use PTX version 61", NVPTX::PTX61, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
119 { "ptx62", "Use PTX version 62", NVPTX::PTX62, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
120 { "ptx63", "Use PTX version 63", NVPTX::PTX63, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
121 { "ptx64", "Use PTX version 64", NVPTX::PTX64, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
122 { "ptx65", "Use PTX version 65", NVPTX::PTX65, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
123 { "ptx70", "Use PTX version 70", NVPTX::PTX70, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
124 { "ptx71", "Use PTX version 71", NVPTX::PTX71, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
125 { "ptx72", "Use PTX version 72", NVPTX::PTX72, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
126 { "ptx73", "Use PTX version 73", NVPTX::PTX73, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
127 { "ptx74", "Use PTX version 74", NVPTX::PTX74, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
128 { "ptx75", "Use PTX version 75", NVPTX::PTX75, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
129 { "ptx76", "Use PTX version 76", NVPTX::PTX76, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
130 { "ptx77", "Use PTX version 77", NVPTX::PTX77, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
131 { "ptx78", "Use PTX version 78", NVPTX::PTX78, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
132 { "ptx80", "Use PTX version 80", NVPTX::PTX80, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
133 { "ptx81", "Use PTX version 81", NVPTX::PTX81, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
134 { "ptx82", "Use PTX version 82", NVPTX::PTX82, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
135 { "ptx83", "Use PTX version 83", NVPTX::PTX83, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
136 { "ptx84", "Use PTX version 84", NVPTX::PTX84, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
137 { "ptx85", "Use PTX version 85", NVPTX::PTX85, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
138 { "ptx86", "Use PTX version 86", NVPTX::PTX86, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
139 { "ptx87", "Use PTX version 87", NVPTX::PTX87, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
140 { "ptx88", "Use PTX version 88", NVPTX::PTX88, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
141 { "ptx90", "Use PTX version 90", NVPTX::PTX90, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
142 { "ptx91", "Use PTX version 91", NVPTX::PTX91, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
143 { "sm_100", "Target SM 100", NVPTX::SM100, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
144 { "sm_100a", "Target SM 100a", NVPTX::SM100a, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
145 { "sm_100f", "Target SM 100f", NVPTX::SM100f, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
146 { "sm_101", "Target SM 101", NVPTX::SM101, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
147 { "sm_101a", "Target SM 101a", NVPTX::SM101a, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
148 { "sm_101f", "Target SM 101f", NVPTX::SM101f, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
149 { "sm_103", "Target SM 103", NVPTX::SM103, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
150 { "sm_103a", "Target SM 103a", NVPTX::SM103a, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
151 { "sm_103f", "Target SM 103f", NVPTX::SM103f, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
152 { "sm_110", "Target SM 110", NVPTX::SM110, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
153 { "sm_110a", "Target SM 110a", NVPTX::SM110a, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
154 { "sm_110f", "Target SM 110f", NVPTX::SM110f, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
155 { "sm_120", "Target SM 120", NVPTX::SM120, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
156 { "sm_120a", "Target SM 120a", NVPTX::SM120a, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
157 { "sm_120f", "Target SM 120f", NVPTX::SM120f, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
158 { "sm_121", "Target SM 121", NVPTX::SM121, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
159 { "sm_121a", "Target SM 121a", NVPTX::SM121a, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
160 { "sm_121f", "Target SM 121f", NVPTX::SM121f, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
161 { "sm_20", "Target SM 20", NVPTX::SM20, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
162 { "sm_21", "Target SM 21", NVPTX::SM21, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
163 { "sm_30", "Target SM 30", NVPTX::SM30, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
164 { "sm_32", "Target SM 32", NVPTX::SM32, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
165 { "sm_35", "Target SM 35", NVPTX::SM35, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
166 { "sm_37", "Target SM 37", NVPTX::SM37, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
167 { "sm_50", "Target SM 50", NVPTX::SM50, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
168 { "sm_52", "Target SM 52", NVPTX::SM52, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
169 { "sm_53", "Target SM 53", NVPTX::SM53, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
170 { "sm_60", "Target SM 60", NVPTX::SM60, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
171 { "sm_61", "Target SM 61", NVPTX::SM61, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
172 { "sm_62", "Target SM 62", NVPTX::SM62, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
173 { "sm_70", "Target SM 70", NVPTX::SM70, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
174 { "sm_72", "Target SM 72", NVPTX::SM72, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
175 { "sm_75", "Target SM 75", NVPTX::SM75, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
176 { "sm_80", "Target SM 80", NVPTX::SM80, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
177 { "sm_86", "Target SM 86", NVPTX::SM86, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
178 { "sm_87", "Target SM 87", NVPTX::SM87, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
179 { "sm_88", "Target SM 88", NVPTX::SM88, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
180 { "sm_89", "Target SM 89", NVPTX::SM89, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
181 { "sm_90", "Target SM 90", NVPTX::SM90, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
182 { "sm_90a", "Target SM 90a", NVPTX::SM90a, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
183};
184
185#ifdef DBGFIELD
186#error "<target>GenSubtargetInfo.inc requires a DBGFIELD macro"
187#endif
188#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
189#define DBGFIELD(x) x,
190#define DBGVAL_OR_NULLPTR(x) x
191#else
192#define DBGFIELD(x)
193#define DBGVAL_OR_NULLPTR(x) nullptr
194#endif
195
196// ===============================================================
197// Data tables for the new per-operand machine model.
198
199// {ProcResourceIdx, ReleaseAtCycle, AcquireAtCycle}
200extern const llvm::MCWriteProcResEntry NVPTXWriteProcResTable[] = {
201 { 0, 0, 0 }, // Invalid
202}; // NVPTXWriteProcResTable
203
204// {Cycles, WriteResourceID}
205extern const llvm::MCWriteLatencyEntry NVPTXWriteLatencyTable[] = {
206 { 0, 0}, // Invalid
207}; // NVPTXWriteLatencyTable
208
209// {UseIdx, WriteResourceID, Cycles}
210extern const llvm::MCReadAdvanceEntry NVPTXReadAdvanceTable[] = {
211 {0, 0, 0}, // Invalid
212}; // NVPTXReadAdvanceTable
213
214#ifdef __GNUC__
215#pragma GCC diagnostic push
216#pragma GCC diagnostic ignored "-Woverlength-strings"
217#endif
218static constexpr char NVPTXSchedClassNamesStorage[] =
219 "\0"
220 "InvalidSchedClass\0"
221 ;
222#ifdef __GNUC__
223#pragma GCC diagnostic pop
224#endif
225
226static constexpr llvm::StringTable
227NVPTXSchedClassNames = NVPTXSchedClassNamesStorage;
228
229static const llvm::MCSchedModel NoSchedModel = {
230 MCSchedModel::DefaultIssueWidth,
231 MCSchedModel::DefaultMicroOpBufferSize,
232 MCSchedModel::DefaultLoopMicroOpBufferSize,
233 MCSchedModel::DefaultLoadLatency,
234 MCSchedModel::DefaultHighLatency,
235 MCSchedModel::DefaultMispredictPenalty,
236 false, // PostRAScheduler
237 false, // CompleteModel
238 false, // EnableIntervals
239 0, // Processor ID
240 nullptr, nullptr, 0, 0, // No instruction-level machine model.
241 DBGVAL_OR_NULLPTR(&NVPTXSchedClassNames), // SchedClassNames
242 nullptr, // No Itinerary
243 nullptr // No extra processor descriptor
244};
245
246#undef DBGFIELD
247
248#undef DBGVAL_OR_NULLPTR
249
250// Sorted (by key) array of values for CPU subtype.
251extern const llvm::SubtargetSubTypeKV NVPTXSubTypeKV[] = {
252 { "sm_100", { { { 0x40000000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
253 { "sm_100a", { { { 0x80000000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
254 { "sm_100f", { { { 0x100000000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
255 { "sm_101", { { { 0x200000000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
256 { "sm_101a", { { { 0x400000000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
257 { "sm_101f", { { { 0x800000000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
258 { "sm_103", { { { 0x1000000000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
259 { "sm_103a", { { { 0x2000000000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
260 { "sm_103f", { { { 0x4000000000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
261 { "sm_110", { { { 0x8000000000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
262 { "sm_110a", { { { 0x0ULL, 0x1ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
263 { "sm_110f", { { { 0x0ULL, 0x2ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
264 { "sm_120", { { { 0x0ULL, 0x4ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
265 { "sm_120a", { { { 0x0ULL, 0x8ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
266 { "sm_120f", { { { 0x0ULL, 0x10ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
267 { "sm_121", { { { 0x0ULL, 0x20ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
268 { "sm_121a", { { { 0x0ULL, 0x40ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
269 { "sm_121f", { { { 0x0ULL, 0x80ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
270 { "sm_20", { { { 0x100000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
271 { "sm_21", { { { 0x200000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
272 { "sm_30", { { { 0x400000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
273 { "sm_32", { { { 0x800000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
274 { "sm_35", { { { 0x1000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
275 { "sm_37", { { { 0x2000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
276 { "sm_50", { { { 0x4000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
277 { "sm_52", { { { 0x8000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
278 { "sm_53", { { { 0x10000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
279 { "sm_60", { { { 0x20000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
280 { "sm_61", { { { 0x40000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
281 { "sm_62", { { { 0x80000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
282 { "sm_70", { { { 0x100000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
283 { "sm_72", { { { 0x200000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
284 { "sm_75", { { { 0x400000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
285 { "sm_80", { { { 0x800000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
286 { "sm_86", { { { 0x1000000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
287 { "sm_87", { { { 0x2000000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
288 { "sm_88", { { { 0x4000000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
289 { "sm_89", { { { 0x8000000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
290 { "sm_90", { { { 0x10000000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
291 { "sm_90a", { { { 0x20000000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
292};
293
294// Sorted array of names of CPU subtypes, including aliases.
295extern const llvm::StringRef NVPTXNames[] = {
296"sm_100",
297"sm_100a",
298"sm_100f",
299"sm_101",
300"sm_101a",
301"sm_101f",
302"sm_103",
303"sm_103a",
304"sm_103f",
305"sm_110",
306"sm_110a",
307"sm_110f",
308"sm_120",
309"sm_120a",
310"sm_120f",
311"sm_121",
312"sm_121a",
313"sm_121f",
314"sm_20",
315"sm_21",
316"sm_30",
317"sm_32",
318"sm_35",
319"sm_37",
320"sm_50",
321"sm_52",
322"sm_53",
323"sm_60",
324"sm_61",
325"sm_62",
326"sm_70",
327"sm_72",
328"sm_75",
329"sm_80",
330"sm_86",
331"sm_87",
332"sm_88",
333"sm_89",
334"sm_90",
335"sm_90a"};
336
337namespace NVPTX_MC {
338
339unsigned resolveVariantSchedClassImpl(unsigned SchedClass,
340 const MCInst *MI, const MCInstrInfo *MCII, const MCSubtargetInfo &STI, unsigned CPUID) {
341 // Don't know how to resolve this scheduling class.
342 return 0;
343}
344
345} // namespace NVPTX_MC
346struct NVPTXGenMCSubtargetInfo : public MCSubtargetInfo {
347 NVPTXGenMCSubtargetInfo(const Triple &TT,
348 StringRef CPU, StringRef TuneCPU, StringRef FS,
349 ArrayRef<StringRef> PN,
350 ArrayRef<SubtargetFeatureKV> PF,
351 ArrayRef<SubtargetSubTypeKV> PD,
352 const MCWriteProcResEntry *WPR,
353 const MCWriteLatencyEntry *WL,
354 const MCReadAdvanceEntry *RA, const InstrStage *IS,
355 const unsigned *OC, const unsigned *FP) :
356 MCSubtargetInfo(TT, CPU, TuneCPU, FS, PN, PF, PD,
357 WPR, WL, RA, IS, OC, FP) { }
358
359 unsigned resolveVariantSchedClass(unsigned SchedClass,
360 const MCInst *MI, const MCInstrInfo *MCII,
361 unsigned CPUID) const final {
362 return NVPTX_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, *this, CPUID);
363 }
364 unsigned getHwModeSet() const final;
365 unsigned getHwMode(enum HwModeType type = HwMode_Default) const final;
366};
367unsigned NVPTXGenMCSubtargetInfo::getHwModeSet() const {
368 [[maybe_unused]] const FeatureBitset &FB = getFeatureBits();
369 // Collect HwModes and store them as a bit set.
370 unsigned Modes = 0;
371 if (false) Modes |= (1 << 0);
372 return Modes;
373}
374unsigned NVPTXGenMCSubtargetInfo::getHwMode(enum HwModeType type) const {
375 unsigned Modes = getHwModeSet();
376
377 if (!Modes)
378 return Modes;
379
380 switch (type) {
381 case HwMode_Default:
382 return llvm::countr_zero(Modes) + 1;
383 case HwMode_ValueType:
384 Modes &= 0;
385 if (!Modes)
386 return Modes;
387 if (!llvm::has_single_bit<unsigned>(Modes))
388 llvm_unreachable("Two or more HwModes for ValueType were found!");
389 return llvm::countr_zero(Modes) + 1;
390 case HwMode_RegInfo:
391 Modes &= 1;
392 if (!Modes)
393 return Modes;
394 if (!llvm::has_single_bit<unsigned>(Modes))
395 llvm_unreachable("Two or more HwModes for RegInfo were found!");
396 return llvm::countr_zero(Modes) + 1;
397 case HwMode_EncodingInfo:
398 Modes &= 0;
399 if (!Modes)
400 return Modes;
401 if (!llvm::has_single_bit<unsigned>(Modes))
402 llvm_unreachable("Two or more HwModes for EncodingInfo were found!");
403 return llvm::countr_zero(Modes) + 1;
404 }
405 llvm_unreachable("unexpected HwModeType");
406 return 0; // should not get here
407}
408
409static inline MCSubtargetInfo *createNVPTXMCSubtargetInfoImpl(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS) {
410 return new NVPTXGenMCSubtargetInfo(TT, CPU, TuneCPU, FS, NVPTXNames, NVPTXFeatureKV, NVPTXSubTypeKV,
411 NVPTXWriteProcResTable, NVPTXWriteLatencyTable, NVPTXReadAdvanceTable,
412 nullptr, nullptr, nullptr);
413}
414
415
416} // namespace llvm
417
418#endif // GET_SUBTARGETINFO_MC_DESC
419
420#ifdef GET_SUBTARGETINFO_TARGET_DESC
421#undef GET_SUBTARGETINFO_TARGET_DESC
422
423#include "llvm/ADT/BitmaskEnum.h"
424#include "llvm/Support/Debug.h"
425#include "llvm/Support/raw_ostream.h"
426
427// ParseSubtargetFeatures - Parses features string setting specified
428// subtarget options.
429void llvm::NVPTXSubtarget::ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS) {
430 LLVM_DEBUG(dbgs() << "\nFeatures:" << FS);
431 LLVM_DEBUG(dbgs() << "\nCPU:" << CPU);
432 LLVM_DEBUG(dbgs() << "\nTuneCPU:" << TuneCPU << "\n\n");
433 InitMCProcessorInfo(CPU, TuneCPU, FS);
434 const FeatureBitset &Bits = getFeatureBits();
435 if (Bits[NVPTX::PTX32] && PTXVersion < 32) PTXVersion = 32;
436 if (Bits[NVPTX::PTX40] && PTXVersion < 40) PTXVersion = 40;
437 if (Bits[NVPTX::PTX41] && PTXVersion < 41) PTXVersion = 41;
438 if (Bits[NVPTX::PTX42] && PTXVersion < 42) PTXVersion = 42;
439 if (Bits[NVPTX::PTX43] && PTXVersion < 43) PTXVersion = 43;
440 if (Bits[NVPTX::PTX50] && PTXVersion < 50) PTXVersion = 50;
441 if (Bits[NVPTX::PTX60] && PTXVersion < 60) PTXVersion = 60;
442 if (Bits[NVPTX::PTX61] && PTXVersion < 61) PTXVersion = 61;
443 if (Bits[NVPTX::PTX62] && PTXVersion < 62) PTXVersion = 62;
444 if (Bits[NVPTX::PTX63] && PTXVersion < 63) PTXVersion = 63;
445 if (Bits[NVPTX::PTX64] && PTXVersion < 64) PTXVersion = 64;
446 if (Bits[NVPTX::PTX65] && PTXVersion < 65) PTXVersion = 65;
447 if (Bits[NVPTX::PTX70] && PTXVersion < 70) PTXVersion = 70;
448 if (Bits[NVPTX::PTX71] && PTXVersion < 71) PTXVersion = 71;
449 if (Bits[NVPTX::PTX72] && PTXVersion < 72) PTXVersion = 72;
450 if (Bits[NVPTX::PTX73] && PTXVersion < 73) PTXVersion = 73;
451 if (Bits[NVPTX::PTX74] && PTXVersion < 74) PTXVersion = 74;
452 if (Bits[NVPTX::PTX75] && PTXVersion < 75) PTXVersion = 75;
453 if (Bits[NVPTX::PTX76] && PTXVersion < 76) PTXVersion = 76;
454 if (Bits[NVPTX::PTX77] && PTXVersion < 77) PTXVersion = 77;
455 if (Bits[NVPTX::PTX78] && PTXVersion < 78) PTXVersion = 78;
456 if (Bits[NVPTX::PTX80] && PTXVersion < 80) PTXVersion = 80;
457 if (Bits[NVPTX::PTX81] && PTXVersion < 81) PTXVersion = 81;
458 if (Bits[NVPTX::PTX82] && PTXVersion < 82) PTXVersion = 82;
459 if (Bits[NVPTX::PTX83] && PTXVersion < 83) PTXVersion = 83;
460 if (Bits[NVPTX::PTX84] && PTXVersion < 84) PTXVersion = 84;
461 if (Bits[NVPTX::PTX85] && PTXVersion < 85) PTXVersion = 85;
462 if (Bits[NVPTX::PTX86] && PTXVersion < 86) PTXVersion = 86;
463 if (Bits[NVPTX::PTX87] && PTXVersion < 87) PTXVersion = 87;
464 if (Bits[NVPTX::PTX88] && PTXVersion < 88) PTXVersion = 88;
465 if (Bits[NVPTX::PTX90] && PTXVersion < 90) PTXVersion = 90;
466 if (Bits[NVPTX::PTX91] && PTXVersion < 91) PTXVersion = 91;
467 if (Bits[NVPTX::SM20] && FullSmVersion < 200) FullSmVersion = 200;
468 if (Bits[NVPTX::SM21] && FullSmVersion < 210) FullSmVersion = 210;
469 if (Bits[NVPTX::SM30] && FullSmVersion < 300) FullSmVersion = 300;
470 if (Bits[NVPTX::SM32] && FullSmVersion < 320) FullSmVersion = 320;
471 if (Bits[NVPTX::SM35] && FullSmVersion < 350) FullSmVersion = 350;
472 if (Bits[NVPTX::SM37] && FullSmVersion < 370) FullSmVersion = 370;
473 if (Bits[NVPTX::SM50] && FullSmVersion < 500) FullSmVersion = 500;
474 if (Bits[NVPTX::SM52] && FullSmVersion < 520) FullSmVersion = 520;
475 if (Bits[NVPTX::SM53] && FullSmVersion < 530) FullSmVersion = 530;
476 if (Bits[NVPTX::SM60] && FullSmVersion < 600) FullSmVersion = 600;
477 if (Bits[NVPTX::SM61] && FullSmVersion < 610) FullSmVersion = 610;
478 if (Bits[NVPTX::SM62] && FullSmVersion < 620) FullSmVersion = 620;
479 if (Bits[NVPTX::SM70] && FullSmVersion < 700) FullSmVersion = 700;
480 if (Bits[NVPTX::SM72] && FullSmVersion < 720) FullSmVersion = 720;
481 if (Bits[NVPTX::SM75] && FullSmVersion < 750) FullSmVersion = 750;
482 if (Bits[NVPTX::SM80] && FullSmVersion < 800) FullSmVersion = 800;
483 if (Bits[NVPTX::SM86] && FullSmVersion < 860) FullSmVersion = 860;
484 if (Bits[NVPTX::SM87] && FullSmVersion < 870) FullSmVersion = 870;
485 if (Bits[NVPTX::SM88] && FullSmVersion < 880) FullSmVersion = 880;
486 if (Bits[NVPTX::SM89] && FullSmVersion < 890) FullSmVersion = 890;
487 if (Bits[NVPTX::SM90] && FullSmVersion < 900) FullSmVersion = 900;
488 if (Bits[NVPTX::SM90a] && FullSmVersion < 903) FullSmVersion = 903;
489 if (Bits[NVPTX::SM100] && FullSmVersion < 1000) FullSmVersion = 1000;
490 if (Bits[NVPTX::SM100a] && FullSmVersion < 1003) FullSmVersion = 1003;
491 if (Bits[NVPTX::SM100f] && FullSmVersion < 1002) FullSmVersion = 1002;
492 if (Bits[NVPTX::SM101] && FullSmVersion < 1010) FullSmVersion = 1010;
493 if (Bits[NVPTX::SM101a] && FullSmVersion < 1013) FullSmVersion = 1013;
494 if (Bits[NVPTX::SM101f] && FullSmVersion < 1012) FullSmVersion = 1012;
495 if (Bits[NVPTX::SM103] && FullSmVersion < 1030) FullSmVersion = 1030;
496 if (Bits[NVPTX::SM103a] && FullSmVersion < 1033) FullSmVersion = 1033;
497 if (Bits[NVPTX::SM103f] && FullSmVersion < 1032) FullSmVersion = 1032;
498 if (Bits[NVPTX::SM110] && FullSmVersion < 1100) FullSmVersion = 1100;
499 if (Bits[NVPTX::SM110a] && FullSmVersion < 1103) FullSmVersion = 1103;
500 if (Bits[NVPTX::SM110f] && FullSmVersion < 1102) FullSmVersion = 1102;
501 if (Bits[NVPTX::SM120] && FullSmVersion < 1200) FullSmVersion = 1200;
502 if (Bits[NVPTX::SM120a] && FullSmVersion < 1203) FullSmVersion = 1203;
503 if (Bits[NVPTX::SM120f] && FullSmVersion < 1202) FullSmVersion = 1202;
504 if (Bits[NVPTX::SM121] && FullSmVersion < 1210) FullSmVersion = 1210;
505 if (Bits[NVPTX::SM121a] && FullSmVersion < 1213) FullSmVersion = 1213;
506 if (Bits[NVPTX::SM121f] && FullSmVersion < 1212) FullSmVersion = 1212;
507}
508
509#endif // GET_SUBTARGETINFO_TARGET_DESC
510
511#ifdef GET_SUBTARGETINFO_HEADER
512#undef GET_SUBTARGETINFO_HEADER
513
514namespace llvm {
515
516class DFAPacketizer;
517namespace NVPTX_MC {
518
519unsigned resolveVariantSchedClassImpl(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, const MCSubtargetInfo &STI, unsigned CPUID);
520
521} // namespace NVPTX_MC
522struct NVPTXGenSubtargetInfo : public TargetSubtargetInfo {
523 explicit NVPTXGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS);
524public:
525 unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const final;
526 unsigned resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const final;
527 DFAPacketizer *createDFAPacketizer(const InstrItineraryData *IID) const;
528 enum class NVPTXHwModeBits : unsigned {
529 DefaultMode = 0,
530 NVPTX64 = (1 << 0),
531
532 LLVM_MARK_AS_BITMASK_ENUM(/*LargestValue=*/NVPTX64),
533 };
534 unsigned getHwModeSet() const final;
535 unsigned getHwMode(enum HwModeType type = HwMode_Default) const final;
536};
537
538} // namespace llvm
539
540#endif // GET_SUBTARGETINFO_HEADER
541
542#ifdef GET_SUBTARGETINFO_CTOR
543#undef GET_SUBTARGETINFO_CTOR
544
545#include "llvm/CodeGen/TargetSchedule.h"
546
547namespace llvm {
548
549extern const llvm::StringRef NVPTXNames[];
550extern const llvm::SubtargetFeatureKV NVPTXFeatureKV[];
551extern const llvm::SubtargetSubTypeKV NVPTXSubTypeKV[];
552extern const llvm::MCWriteProcResEntry NVPTXWriteProcResTable[];
553extern const llvm::MCWriteLatencyEntry NVPTXWriteLatencyTable[];
554extern const llvm::MCReadAdvanceEntry NVPTXReadAdvanceTable[];
555NVPTXGenSubtargetInfo::NVPTXGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS)
556 : TargetSubtargetInfo(TT, CPU, TuneCPU, FS, ArrayRef(NVPTXNames, 40), ArrayRef(NVPTXFeatureKV, 72), ArrayRef(NVPTXSubTypeKV, 40),
557 NVPTXWriteProcResTable, NVPTXWriteLatencyTable, NVPTXReadAdvanceTable,
558 nullptr, nullptr, nullptr) {}
559
560unsigned NVPTXGenSubtargetInfo
561::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const {
562 report_fatal_error("Expected a variant SchedClass");
563} // NVPTXGenSubtargetInfo::resolveSchedClass
564
565unsigned NVPTXGenSubtargetInfo
566::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const {
567 return NVPTX_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, *this, CPUID);
568} // NVPTXGenSubtargetInfo::resolveVariantSchedClass
569
570unsigned NVPTXGenSubtargetInfo::getHwModeSet() const {
571 [[maybe_unused]] const auto *Subtarget =
572 static_cast<const NVPTXSubtarget *>(this);
573 // Collect HwModes and store them as a bit set.
574 unsigned Modes = 0;
575 if ((Subtarget->getTargetTriple().getArch() == Triple::nvptx64)) Modes |= (1 << 0);
576 return Modes;
577}
578unsigned NVPTXGenSubtargetInfo::getHwMode(enum HwModeType type) const {
579 unsigned Modes = getHwModeSet();
580
581 if (!Modes)
582 return Modes;
583
584 switch (type) {
585 case HwMode_Default:
586 return llvm::countr_zero(Modes) + 1;
587 case HwMode_ValueType:
588 Modes &= 0;
589 if (!Modes)
590 return Modes;
591 if (!llvm::has_single_bit<unsigned>(Modes))
592 llvm_unreachable("Two or more HwModes for ValueType were found!");
593 return llvm::countr_zero(Modes) + 1;
594 case HwMode_RegInfo:
595 Modes &= 1;
596 if (!Modes)
597 return Modes;
598 if (!llvm::has_single_bit<unsigned>(Modes))
599 llvm_unreachable("Two or more HwModes for RegInfo were found!");
600 return llvm::countr_zero(Modes) + 1;
601 case HwMode_EncodingInfo:
602 Modes &= 0;
603 if (!Modes)
604 return Modes;
605 if (!llvm::has_single_bit<unsigned>(Modes))
606 llvm_unreachable("Two or more HwModes for EncodingInfo were found!");
607 return llvm::countr_zero(Modes) + 1;
608 }
609 llvm_unreachable("unexpected HwModeType");
610 return 0; // should not get here
611}
612
613} // namespace llvm
614
615#endif // GET_SUBTARGETINFO_CTOR
616
617#ifdef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
618#undef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
619
620
621#endif // GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
622
623#ifdef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
624#undef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
625
626
627#endif // GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
628
629