1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Subtarget Enumeration Source Fragment *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_SUBTARGETINFO_ENUM
10#undef GET_SUBTARGETINFO_ENUM
11
12namespace llvm {
13
14namespace NVPTX {
15
16enum {
17 PTX32 = 0,
18 PTX40 = 1,
19 PTX41 = 2,
20 PTX42 = 3,
21 PTX43 = 4,
22 PTX50 = 5,
23 PTX60 = 6,
24 PTX61 = 7,
25 PTX62 = 8,
26 PTX63 = 9,
27 PTX64 = 10,
28 PTX65 = 11,
29 PTX70 = 12,
30 PTX71 = 13,
31 PTX72 = 14,
32 PTX73 = 15,
33 PTX74 = 16,
34 PTX75 = 17,
35 PTX76 = 18,
36 PTX77 = 19,
37 PTX78 = 20,
38 PTX80 = 21,
39 PTX81 = 22,
40 PTX82 = 23,
41 PTX83 = 24,
42 PTX84 = 25,
43 PTX85 = 26,
44 PTX86 = 27,
45 PTX87 = 28,
46 PTX88 = 29,
47 PTX90 = 30,
48 PTX91 = 31,
49 PTX92 = 32,
50 PTX93 = 33,
51 SM20 = 34,
52 SM21 = 35,
53 SM30 = 36,
54 SM32 = 37,
55 SM35 = 38,
56 SM37 = 39,
57 SM50 = 40,
58 SM52 = 41,
59 SM53 = 42,
60 SM60 = 43,
61 SM61 = 44,
62 SM62 = 45,
63 SM70 = 46,
64 SM72 = 47,
65 SM75 = 48,
66 SM80 = 49,
67 SM86 = 50,
68 SM87 = 51,
69 SM88 = 52,
70 SM89 = 53,
71 SM90 = 54,
72 SM90a = 55,
73 SM100 = 56,
74 SM100a = 57,
75 SM100f = 58,
76 SM101 = 59,
77 SM101a = 60,
78 SM101f = 61,
79 SM103 = 62,
80 SM103a = 63,
81 SM103f = 64,
82 SM110 = 65,
83 SM110a = 66,
84 SM110f = 67,
85 SM120 = 68,
86 SM120a = 69,
87 SM120f = 70,
88 SM121 = 71,
89 SM121a = 72,
90 SM121f = 73,
91 NumSubtargetFeatures = 74
92};
93
94} // namespace NVPTX
95
96} // namespace llvm
97
98#endif // GET_SUBTARGETINFO_ENUM
99
100#ifdef GET_SUBTARGETINFO_MACRO
101
102
103#undef GET_SUBTARGETINFO_MACRO
104#endif // GET_SUBTARGETINFO_MACRO
105
106#ifdef GET_SUBTARGETINFO_MC_DESC
107#undef GET_SUBTARGETINFO_MC_DESC
108
109namespace llvm {
110
111// Sorted (by key) array of values for CPU features.
112extern const llvm::SubtargetFeatureKVStorage< 74, 1674> NVPTXFeatureKVStorage = {
113 {
114 { sizeof(SubtargetFeatureKV) * 74 + 1, sizeof(SubtargetFeatureKV) * 74 + 7, NVPTX::PTX32, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
115 { sizeof(SubtargetFeatureKV) * 73 + 26, sizeof(SubtargetFeatureKV) * 73 + 32, NVPTX::PTX40, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
116 { sizeof(SubtargetFeatureKV) * 72 + 51, sizeof(SubtargetFeatureKV) * 72 + 57, NVPTX::PTX41, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
117 { sizeof(SubtargetFeatureKV) * 71 + 76, sizeof(SubtargetFeatureKV) * 71 + 82, NVPTX::PTX42, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
118 { sizeof(SubtargetFeatureKV) * 70 + 101, sizeof(SubtargetFeatureKV) * 70 + 107, NVPTX::PTX43, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
119 { sizeof(SubtargetFeatureKV) * 69 + 126, sizeof(SubtargetFeatureKV) * 69 + 132, NVPTX::PTX50, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
120 { sizeof(SubtargetFeatureKV) * 68 + 151, sizeof(SubtargetFeatureKV) * 68 + 157, NVPTX::PTX60, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
121 { sizeof(SubtargetFeatureKV) * 67 + 176, sizeof(SubtargetFeatureKV) * 67 + 182, NVPTX::PTX61, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
122 { sizeof(SubtargetFeatureKV) * 66 + 201, sizeof(SubtargetFeatureKV) * 66 + 207, NVPTX::PTX62, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
123 { sizeof(SubtargetFeatureKV) * 65 + 226, sizeof(SubtargetFeatureKV) * 65 + 232, NVPTX::PTX63, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
124 { sizeof(SubtargetFeatureKV) * 64 + 251, sizeof(SubtargetFeatureKV) * 64 + 257, NVPTX::PTX64, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
125 { sizeof(SubtargetFeatureKV) * 63 + 276, sizeof(SubtargetFeatureKV) * 63 + 282, NVPTX::PTX65, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
126 { sizeof(SubtargetFeatureKV) * 62 + 301, sizeof(SubtargetFeatureKV) * 62 + 307, NVPTX::PTX70, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
127 { sizeof(SubtargetFeatureKV) * 61 + 326, sizeof(SubtargetFeatureKV) * 61 + 332, NVPTX::PTX71, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
128 { sizeof(SubtargetFeatureKV) * 60 + 351, sizeof(SubtargetFeatureKV) * 60 + 357, NVPTX::PTX72, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
129 { sizeof(SubtargetFeatureKV) * 59 + 376, sizeof(SubtargetFeatureKV) * 59 + 382, NVPTX::PTX73, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
130 { sizeof(SubtargetFeatureKV) * 58 + 401, sizeof(SubtargetFeatureKV) * 58 + 407, NVPTX::PTX74, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
131 { sizeof(SubtargetFeatureKV) * 57 + 426, sizeof(SubtargetFeatureKV) * 57 + 432, NVPTX::PTX75, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
132 { sizeof(SubtargetFeatureKV) * 56 + 451, sizeof(SubtargetFeatureKV) * 56 + 457, NVPTX::PTX76, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
133 { sizeof(SubtargetFeatureKV) * 55 + 476, sizeof(SubtargetFeatureKV) * 55 + 482, NVPTX::PTX77, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
134 { sizeof(SubtargetFeatureKV) * 54 + 501, sizeof(SubtargetFeatureKV) * 54 + 507, NVPTX::PTX78, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
135 { sizeof(SubtargetFeatureKV) * 53 + 526, sizeof(SubtargetFeatureKV) * 53 + 532, NVPTX::PTX80, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
136 { sizeof(SubtargetFeatureKV) * 52 + 551, sizeof(SubtargetFeatureKV) * 52 + 557, NVPTX::PTX81, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
137 { sizeof(SubtargetFeatureKV) * 51 + 576, sizeof(SubtargetFeatureKV) * 51 + 582, NVPTX::PTX82, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
138 { sizeof(SubtargetFeatureKV) * 50 + 601, sizeof(SubtargetFeatureKV) * 50 + 607, NVPTX::PTX83, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
139 { sizeof(SubtargetFeatureKV) * 49 + 626, sizeof(SubtargetFeatureKV) * 49 + 632, NVPTX::PTX84, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
140 { sizeof(SubtargetFeatureKV) * 48 + 651, sizeof(SubtargetFeatureKV) * 48 + 657, NVPTX::PTX85, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
141 { sizeof(SubtargetFeatureKV) * 47 + 676, sizeof(SubtargetFeatureKV) * 47 + 682, NVPTX::PTX86, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
142 { sizeof(SubtargetFeatureKV) * 46 + 701, sizeof(SubtargetFeatureKV) * 46 + 707, NVPTX::PTX87, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
143 { sizeof(SubtargetFeatureKV) * 45 + 726, sizeof(SubtargetFeatureKV) * 45 + 732, NVPTX::PTX88, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
144 { sizeof(SubtargetFeatureKV) * 44 + 751, sizeof(SubtargetFeatureKV) * 44 + 757, NVPTX::PTX90, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
145 { sizeof(SubtargetFeatureKV) * 43 + 776, sizeof(SubtargetFeatureKV) * 43 + 782, NVPTX::PTX91, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
146 { sizeof(SubtargetFeatureKV) * 42 + 801, sizeof(SubtargetFeatureKV) * 42 + 807, NVPTX::PTX92, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
147 { sizeof(SubtargetFeatureKV) * 41 + 826, sizeof(SubtargetFeatureKV) * 41 + 832, NVPTX::PTX93, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
148 { sizeof(SubtargetFeatureKV) * 40 + 851, sizeof(SubtargetFeatureKV) * 40 + 858, NVPTX::SM100, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
149 { sizeof(SubtargetFeatureKV) * 39 + 872, sizeof(SubtargetFeatureKV) * 39 + 880, NVPTX::SM100a, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
150 { sizeof(SubtargetFeatureKV) * 38 + 895, sizeof(SubtargetFeatureKV) * 38 + 903, NVPTX::SM100f, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
151 { sizeof(SubtargetFeatureKV) * 37 + 918, sizeof(SubtargetFeatureKV) * 37 + 925, NVPTX::SM101, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
152 { sizeof(SubtargetFeatureKV) * 36 + 939, sizeof(SubtargetFeatureKV) * 36 + 947, NVPTX::SM101a, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
153 { sizeof(SubtargetFeatureKV) * 35 + 962, sizeof(SubtargetFeatureKV) * 35 + 970, NVPTX::SM101f, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
154 { sizeof(SubtargetFeatureKV) * 34 + 985, sizeof(SubtargetFeatureKV) * 34 + 992, NVPTX::SM103, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
155 { sizeof(SubtargetFeatureKV) * 33 + 1006, sizeof(SubtargetFeatureKV) * 33 + 1014, NVPTX::SM103a, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
156 { sizeof(SubtargetFeatureKV) * 32 + 1029, sizeof(SubtargetFeatureKV) * 32 + 1037, NVPTX::SM103f, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
157 { sizeof(SubtargetFeatureKV) * 31 + 1052, sizeof(SubtargetFeatureKV) * 31 + 1059, NVPTX::SM110, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
158 { sizeof(SubtargetFeatureKV) * 30 + 1073, sizeof(SubtargetFeatureKV) * 30 + 1081, NVPTX::SM110a, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
159 { sizeof(SubtargetFeatureKV) * 29 + 1096, sizeof(SubtargetFeatureKV) * 29 + 1104, NVPTX::SM110f, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
160 { sizeof(SubtargetFeatureKV) * 28 + 1119, sizeof(SubtargetFeatureKV) * 28 + 1126, NVPTX::SM120, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
161 { sizeof(SubtargetFeatureKV) * 27 + 1140, sizeof(SubtargetFeatureKV) * 27 + 1148, NVPTX::SM120a, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
162 { sizeof(SubtargetFeatureKV) * 26 + 1163, sizeof(SubtargetFeatureKV) * 26 + 1171, NVPTX::SM120f, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
163 { sizeof(SubtargetFeatureKV) * 25 + 1186, sizeof(SubtargetFeatureKV) * 25 + 1193, NVPTX::SM121, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
164 { sizeof(SubtargetFeatureKV) * 24 + 1207, sizeof(SubtargetFeatureKV) * 24 + 1215, NVPTX::SM121a, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
165 { sizeof(SubtargetFeatureKV) * 23 + 1230, sizeof(SubtargetFeatureKV) * 23 + 1238, NVPTX::SM121f, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
166 { sizeof(SubtargetFeatureKV) * 22 + 1253, sizeof(SubtargetFeatureKV) * 22 + 1259, NVPTX::SM20, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
167 { sizeof(SubtargetFeatureKV) * 21 + 1272, sizeof(SubtargetFeatureKV) * 21 + 1278, NVPTX::SM21, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
168 { sizeof(SubtargetFeatureKV) * 20 + 1291, sizeof(SubtargetFeatureKV) * 20 + 1297, NVPTX::SM30, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
169 { sizeof(SubtargetFeatureKV) * 19 + 1310, sizeof(SubtargetFeatureKV) * 19 + 1316, NVPTX::SM32, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
170 { sizeof(SubtargetFeatureKV) * 18 + 1329, sizeof(SubtargetFeatureKV) * 18 + 1335, NVPTX::SM35, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
171 { sizeof(SubtargetFeatureKV) * 17 + 1348, sizeof(SubtargetFeatureKV) * 17 + 1354, NVPTX::SM37, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
172 { sizeof(SubtargetFeatureKV) * 16 + 1367, sizeof(SubtargetFeatureKV) * 16 + 1373, NVPTX::SM50, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
173 { sizeof(SubtargetFeatureKV) * 15 + 1386, sizeof(SubtargetFeatureKV) * 15 + 1392, NVPTX::SM52, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
174 { sizeof(SubtargetFeatureKV) * 14 + 1405, sizeof(SubtargetFeatureKV) * 14 + 1411, NVPTX::SM53, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
175 { sizeof(SubtargetFeatureKV) * 13 + 1424, sizeof(SubtargetFeatureKV) * 13 + 1430, NVPTX::SM60, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
176 { sizeof(SubtargetFeatureKV) * 12 + 1443, sizeof(SubtargetFeatureKV) * 12 + 1449, NVPTX::SM61, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
177 { sizeof(SubtargetFeatureKV) * 11 + 1462, sizeof(SubtargetFeatureKV) * 11 + 1468, NVPTX::SM62, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
178 { sizeof(SubtargetFeatureKV) * 10 + 1481, sizeof(SubtargetFeatureKV) * 10 + 1487, NVPTX::SM70, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
179 { sizeof(SubtargetFeatureKV) * 9 + 1500, sizeof(SubtargetFeatureKV) * 9 + 1506, NVPTX::SM72, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
180 { sizeof(SubtargetFeatureKV) * 8 + 1519, sizeof(SubtargetFeatureKV) * 8 + 1525, NVPTX::SM75, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
181 { sizeof(SubtargetFeatureKV) * 7 + 1538, sizeof(SubtargetFeatureKV) * 7 + 1544, NVPTX::SM80, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
182 { sizeof(SubtargetFeatureKV) * 6 + 1557, sizeof(SubtargetFeatureKV) * 6 + 1563, NVPTX::SM86, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
183 { sizeof(SubtargetFeatureKV) * 5 + 1576, sizeof(SubtargetFeatureKV) * 5 + 1582, NVPTX::SM87, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
184 { sizeof(SubtargetFeatureKV) * 4 + 1595, sizeof(SubtargetFeatureKV) * 4 + 1601, NVPTX::SM88, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
185 { sizeof(SubtargetFeatureKV) * 3 + 1614, sizeof(SubtargetFeatureKV) * 3 + 1620, NVPTX::SM89, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
186 { sizeof(SubtargetFeatureKV) * 2 + 1633, sizeof(SubtargetFeatureKV) * 2 + 1639, NVPTX::SM90, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
187 { sizeof(SubtargetFeatureKV) * 1 + 1652, sizeof(SubtargetFeatureKV) * 1 + 1659, NVPTX::SM90a, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
188 },
189 "\000ptx32\000Use PTX version 32\000ptx40\000Use PTX version 40\000ptx41"
190 "\000Use PTX version 41\000ptx42\000Use PTX version 42\000ptx43\000Use P"
191 "TX version 43\000ptx50\000Use PTX version 50\000ptx60\000Use PTX versio"
192 "n 60\000ptx61\000Use PTX version 61\000ptx62\000Use PTX version 62\000p"
193 "tx63\000Use PTX version 63\000ptx64\000Use PTX version 64\000ptx65\000U"
194 "se PTX version 65\000ptx70\000Use PTX version 70\000ptx71\000Use PTX ve"
195 "rsion 71\000ptx72\000Use PTX version 72\000ptx73\000Use PTX version 73\000"
196 "ptx74\000Use PTX version 74\000ptx75\000Use PTX version 75\000ptx76\000"
197 "Use PTX version 76\000ptx77\000Use PTX version 77\000ptx78\000Use PTX v"
198 "ersion 78\000ptx80\000Use PTX version 80\000ptx81\000Use PTX version 81"
199 "\000ptx82\000Use PTX version 82\000ptx83\000Use PTX version 83\000ptx84"
200 "\000Use PTX version 84\000ptx85\000Use PTX version 85\000ptx86\000Use P"
201 "TX version 86\000ptx87\000Use PTX version 87\000ptx88\000Use PTX versio"
202 "n 88\000ptx90\000Use PTX version 90\000ptx91\000Use PTX version 91\000p"
203 "tx92\000Use PTX version 92\000ptx93\000Use PTX version 93\000sm_100\000"
204 "Target SM 100\000sm_100a\000Target SM 100a\000sm_100f\000Target SM 100f"
205 "\000sm_101\000Target SM 101\000sm_101a\000Target SM 101a\000sm_101f\000"
206 "Target SM 101f\000sm_103\000Target SM 103\000sm_103a\000Target SM 103a\000"
207 "sm_103f\000Target SM 103f\000sm_110\000Target SM 110\000sm_110a\000Targ"
208 "et SM 110a\000sm_110f\000Target SM 110f\000sm_120\000Target SM 120\000s"
209 "m_120a\000Target SM 120a\000sm_120f\000Target SM 120f\000sm_121\000Targ"
210 "et SM 121\000sm_121a\000Target SM 121a\000sm_121f\000Target SM 121f\000"
211 "sm_20\000Target SM 20\000sm_21\000Target SM 21\000sm_30\000Target SM 30"
212 "\000sm_32\000Target SM 32\000sm_35\000Target SM 35\000sm_37\000Target S"
213 "M 37\000sm_50\000Target SM 50\000sm_52\000Target SM 52\000sm_53\000Targ"
214 "et SM 53\000sm_60\000Target SM 60\000sm_61\000Target SM 61\000sm_62\000"
215 "Target SM 62\000sm_70\000Target SM 70\000sm_72\000Target SM 72\000sm_75"
216 "\000Target SM 75\000sm_80\000Target SM 80\000sm_86\000Target SM 86\000s"
217 "m_87\000Target SM 87\000sm_88\000Target SM 88\000sm_89\000Target SM 89\000"
218 "sm_90\000Target SM 90\000sm_90a\000Target SM 90a\000"};
219
220#ifdef DBGFIELD
221#error "<target>GenSubtargetInfo.inc requires a DBGFIELD macro"
222#endif
223#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
224#define DBGFIELD(x) x,
225#define DBGVAL_OR_NULLPTR(x) x
226#else
227#define DBGFIELD(x)
228#define DBGVAL_OR_NULLPTR(x) nullptr
229#endif
230
231// ===============================================================
232// Data tables for the new per-operand machine model.
233
234static_assert(0 <= UINT8_MAX, "NumWriteProcResEntries does not fit in uint8_t");
235static_assert(0 <= UINT8_MAX, "NumWriteLatencyEntries does not fit in uint8_t");
236
237// {ProcResourceIdx, ReleaseAtCycle, AcquireAtCycle}
238extern const llvm::MCWriteProcResEntry NVPTXWriteProcResTable[] = {
239 { 0, 0, 0 }, // Invalid
240}; // NVPTXWriteProcResTable
241
242// {Cycles, WriteResourceID}
243extern const llvm::MCWriteLatencyEntry NVPTXWriteLatencyTable[] = {
244 { 0, 0}, // Invalid
245}; // NVPTXWriteLatencyTable
246
247// {UseIdx, WriteResourceID, Cycles}
248extern const llvm::MCReadAdvanceEntry NVPTXReadAdvanceTable[] = {
249 {0, 0, 0}, // Invalid
250}; // NVPTXReadAdvanceTable
251
252#ifdef __GNUC__
253#pragma GCC diagnostic push
254#pragma GCC diagnostic ignored "-Woverlength-strings"
255#endif
256static constexpr char NVPTXSchedClassNamesStorage[] =
257 "\0"
258 "InvalidSchedClass\0"
259 ;
260#ifdef __GNUC__
261#pragma GCC diagnostic pop
262#endif
263
264static constexpr llvm::StringTable
265NVPTXSchedClassNames = NVPTXSchedClassNamesStorage;
266
267extern const llvm::MCSchedModel NVPTXSchedModels[] = {
268{ // NoSchedModel
269 MCSchedModel::DefaultIssueWidth,
270 MCSchedModel::DefaultMicroOpBufferSize,
271 MCSchedModel::DefaultLoopMicroOpBufferSize,
272 MCSchedModel::DefaultLoadLatency,
273 MCSchedModel::DefaultHighLatency,
274 MCSchedModel::DefaultMispredictPenalty,
275 false, // PostRAScheduler
276 false, // CompleteModel
277 false, // EnableIntervals
278 0, // Processor ID
279 nullptr, nullptr, 0, 0, // No instruction-level machine model.
280 DBGVAL_OR_NULLPTR(&NVPTXSchedClassNames), // SchedClassNames
281 nullptr, // No Itinerary
282 nullptr // No extra processor descriptor
283 },
284};
285
286#undef DBGFIELD
287
288#undef DBGVAL_OR_NULLPTR
289
290// Sorted (by key) array of values for CPU subtype.
291extern const llvm::SubtargetSubTypeKVStorage< 40, 273> NVPTXSubTypeKVStorage = {
292 {
293 { sizeof(SubtargetSubTypeKV) * 40 + 1, { { { 0x100000000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
294 { sizeof(SubtargetSubTypeKV) * 39 + 8, { { { 0x200000000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
295 { sizeof(SubtargetSubTypeKV) * 38 + 16, { { { 0x400000000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
296 { sizeof(SubtargetSubTypeKV) * 37 + 24, { { { 0x800000000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
297 { sizeof(SubtargetSubTypeKV) * 36 + 31, { { { 0x1000000000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
298 { sizeof(SubtargetSubTypeKV) * 35 + 39, { { { 0x2000000000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
299 { sizeof(SubtargetSubTypeKV) * 34 + 47, { { { 0x4000000000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
300 { sizeof(SubtargetSubTypeKV) * 33 + 54, { { { 0x8000000000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
301 { sizeof(SubtargetSubTypeKV) * 32 + 62, { { { 0x0ULL, 0x1ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
302 { sizeof(SubtargetSubTypeKV) * 31 + 70, { { { 0x0ULL, 0x2ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
303 { sizeof(SubtargetSubTypeKV) * 30 + 77, { { { 0x0ULL, 0x4ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
304 { sizeof(SubtargetSubTypeKV) * 29 + 85, { { { 0x0ULL, 0x8ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
305 { sizeof(SubtargetSubTypeKV) * 28 + 93, { { { 0x0ULL, 0x10ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
306 { sizeof(SubtargetSubTypeKV) * 27 + 100, { { { 0x0ULL, 0x20ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
307 { sizeof(SubtargetSubTypeKV) * 26 + 108, { { { 0x0ULL, 0x40ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
308 { sizeof(SubtargetSubTypeKV) * 25 + 116, { { { 0x0ULL, 0x80ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
309 { sizeof(SubtargetSubTypeKV) * 24 + 123, { { { 0x0ULL, 0x100ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
310 { sizeof(SubtargetSubTypeKV) * 23 + 131, { { { 0x0ULL, 0x200ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
311 { sizeof(SubtargetSubTypeKV) * 22 + 139, { { { 0x400000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
312 { sizeof(SubtargetSubTypeKV) * 21 + 145, { { { 0x800000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
313 { sizeof(SubtargetSubTypeKV) * 20 + 151, { { { 0x1000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
314 { sizeof(SubtargetSubTypeKV) * 19 + 157, { { { 0x2000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
315 { sizeof(SubtargetSubTypeKV) * 18 + 163, { { { 0x4000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
316 { sizeof(SubtargetSubTypeKV) * 17 + 169, { { { 0x8000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
317 { sizeof(SubtargetSubTypeKV) * 16 + 175, { { { 0x10000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
318 { sizeof(SubtargetSubTypeKV) * 15 + 181, { { { 0x20000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
319 { sizeof(SubtargetSubTypeKV) * 14 + 187, { { { 0x40000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
320 { sizeof(SubtargetSubTypeKV) * 13 + 193, { { { 0x80000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
321 { sizeof(SubtargetSubTypeKV) * 12 + 199, { { { 0x100000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
322 { sizeof(SubtargetSubTypeKV) * 11 + 205, { { { 0x200000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
323 { sizeof(SubtargetSubTypeKV) * 10 + 211, { { { 0x400000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
324 { sizeof(SubtargetSubTypeKV) * 9 + 217, { { { 0x800000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
325 { sizeof(SubtargetSubTypeKV) * 8 + 223, { { { 0x1000000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
326 { sizeof(SubtargetSubTypeKV) * 7 + 229, { { { 0x2000000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
327 { sizeof(SubtargetSubTypeKV) * 6 + 235, { { { 0x4000000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
328 { sizeof(SubtargetSubTypeKV) * 5 + 241, { { { 0x8000000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
329 { sizeof(SubtargetSubTypeKV) * 4 + 247, { { { 0x10000000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
330 { sizeof(SubtargetSubTypeKV) * 3 + 253, { { { 0x20000000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
331 { sizeof(SubtargetSubTypeKV) * 2 + 259, { { { 0x40000000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
332 { sizeof(SubtargetSubTypeKV) * 1 + 265, { { { 0x80000000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
333 },
334 "\000sm_100\000sm_100a\000sm_100f\000sm_101\000sm_101a\000sm_101f\000sm_"
335 "103\000sm_103a\000sm_103f\000sm_110\000sm_110a\000sm_110f\000sm_120\000"
336 "sm_120a\000sm_120f\000sm_121\000sm_121a\000sm_121f\000sm_20\000sm_21\000"
337 "sm_30\000sm_32\000sm_35\000sm_37\000sm_50\000sm_52\000sm_53\000sm_60\000"
338 "sm_61\000sm_62\000sm_70\000sm_72\000sm_75\000sm_80\000sm_86\000sm_87\000"
339 "sm_88\000sm_89\000sm_90\000sm_90a\000"};
340
341namespace NVPTX_MC {
342
343unsigned resolveVariantSchedClassImpl(unsigned SchedClass,
344 const MCInst *MI, const MCInstrInfo *MCII, const MCSubtargetInfo &STI, unsigned CPUID) {
345 // Don't know how to resolve this scheduling class.
346 return 0;
347}
348
349} // namespace NVPTX_MC
350struct NVPTXGenMCSubtargetInfo : public MCSubtargetInfo {
351 NVPTXGenMCSubtargetInfo(const Triple &TT,
352 StringRef CPU, StringRef TuneCPU, StringRef FS,
353 StringTable PN,
354 ArrayRef<SubtargetFeatureKV> PF,
355 ArrayRef<SubtargetSubTypeKV> PD,
356 const MCSchedModel *PSM,
357 const MCWriteProcResEntry *WPR,
358 const MCWriteLatencyEntry *WL,
359 const MCReadAdvanceEntry *RA, const InstrStage *IS,
360 const unsigned *OC, const unsigned *FP) :
361 MCSubtargetInfo(TT, CPU, TuneCPU, FS, PN, PF, PD, PSM,
362 WPR, WL, RA, IS, OC, FP) { }
363
364 unsigned resolveVariantSchedClass(unsigned SchedClass,
365 const MCInst *MI, const MCInstrInfo *MCII,
366 unsigned CPUID) const final {
367 return NVPTX_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, *this, CPUID);
368 }
369 unsigned getHwModeSet() const final;
370 unsigned getHwMode(enum HwModeType type = HwMode_Default) const final;
371};
372unsigned NVPTXGenMCSubtargetInfo::getHwModeSet() const {
373 [[maybe_unused]] const FeatureBitset &FB = getFeatureBits();
374 // Collect HwModes and store them as a bit set.
375 unsigned Modes = 0;
376 if (false) Modes |= (1 << 0);
377 return Modes;
378}
379unsigned NVPTXGenMCSubtargetInfo::getHwMode(enum HwModeType type) const {
380 unsigned Modes = getHwModeSet();
381
382 if (!Modes)
383 return Modes;
384
385 switch (type) {
386 case HwMode_Default:
387 return llvm::countr_zero(Modes) + 1;
388 case HwMode_ValueType:
389 // No HwMode for ValueType.
390 return 0;
391 case HwMode_RegInfo:
392 Modes &= 1;
393 if (!Modes)
394 return Modes;
395 if (!llvm::has_single_bit<unsigned>(Modes))
396 llvm_unreachable("Two or more HwModes for RegInfo were found!");
397 return llvm::countr_zero(Modes) + 1;
398 case HwMode_EncodingInfo:
399 // No HwMode for EncodingInfo.
400 return 0;
401 }
402 llvm_unreachable("unexpected HwModeType");
403 return 0; // should not get here
404}
405
406static inline MCSubtargetInfo *createNVPTXMCSubtargetInfoImpl(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS) {
407 return new NVPTXGenMCSubtargetInfo(TT, CPU, TuneCPU, FS, StringTable(NVPTXSubTypeKVStorage.Strings), NVPTXFeatureKVStorage.Features, NVPTXSubTypeKVStorage.SubTypes, NVPTXSchedModels,
408 NVPTXWriteProcResTable, NVPTXWriteLatencyTable, NVPTXReadAdvanceTable,
409 nullptr, nullptr, nullptr);
410}
411
412
413} // namespace llvm
414
415#endif // GET_SUBTARGETINFO_MC_DESC
416
417#ifdef GET_SUBTARGETINFO_TARGET_DESC
418#undef GET_SUBTARGETINFO_TARGET_DESC
419
420#include "llvm/ADT/BitmaskEnum.h"
421#include "llvm/Support/Debug.h"
422#include "llvm/Support/raw_ostream.h"
423
424// ParseSubtargetFeatures - Parses features string setting specified
425// subtarget options.
426void llvm::NVPTXSubtarget::ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS) {
427 LLVM_DEBUG(dbgs() << "\nFeatures:" << FS);
428 LLVM_DEBUG(dbgs() << "\nCPU:" << CPU);
429 LLVM_DEBUG(dbgs() << "\nTuneCPU:" << TuneCPU << "\n\n");
430 InitMCProcessorInfo(CPU, TuneCPU, FS);
431 const FeatureBitset &Bits = getFeatureBits();
432 if (Bits[NVPTX::PTX32] && PTXVersion < 32) PTXVersion = 32;
433 if (Bits[NVPTX::PTX40] && PTXVersion < 40) PTXVersion = 40;
434 if (Bits[NVPTX::PTX41] && PTXVersion < 41) PTXVersion = 41;
435 if (Bits[NVPTX::PTX42] && PTXVersion < 42) PTXVersion = 42;
436 if (Bits[NVPTX::PTX43] && PTXVersion < 43) PTXVersion = 43;
437 if (Bits[NVPTX::PTX50] && PTXVersion < 50) PTXVersion = 50;
438 if (Bits[NVPTX::PTX60] && PTXVersion < 60) PTXVersion = 60;
439 if (Bits[NVPTX::PTX61] && PTXVersion < 61) PTXVersion = 61;
440 if (Bits[NVPTX::PTX62] && PTXVersion < 62) PTXVersion = 62;
441 if (Bits[NVPTX::PTX63] && PTXVersion < 63) PTXVersion = 63;
442 if (Bits[NVPTX::PTX64] && PTXVersion < 64) PTXVersion = 64;
443 if (Bits[NVPTX::PTX65] && PTXVersion < 65) PTXVersion = 65;
444 if (Bits[NVPTX::PTX70] && PTXVersion < 70) PTXVersion = 70;
445 if (Bits[NVPTX::PTX71] && PTXVersion < 71) PTXVersion = 71;
446 if (Bits[NVPTX::PTX72] && PTXVersion < 72) PTXVersion = 72;
447 if (Bits[NVPTX::PTX73] && PTXVersion < 73) PTXVersion = 73;
448 if (Bits[NVPTX::PTX74] && PTXVersion < 74) PTXVersion = 74;
449 if (Bits[NVPTX::PTX75] && PTXVersion < 75) PTXVersion = 75;
450 if (Bits[NVPTX::PTX76] && PTXVersion < 76) PTXVersion = 76;
451 if (Bits[NVPTX::PTX77] && PTXVersion < 77) PTXVersion = 77;
452 if (Bits[NVPTX::PTX78] && PTXVersion < 78) PTXVersion = 78;
453 if (Bits[NVPTX::PTX80] && PTXVersion < 80) PTXVersion = 80;
454 if (Bits[NVPTX::PTX81] && PTXVersion < 81) PTXVersion = 81;
455 if (Bits[NVPTX::PTX82] && PTXVersion < 82) PTXVersion = 82;
456 if (Bits[NVPTX::PTX83] && PTXVersion < 83) PTXVersion = 83;
457 if (Bits[NVPTX::PTX84] && PTXVersion < 84) PTXVersion = 84;
458 if (Bits[NVPTX::PTX85] && PTXVersion < 85) PTXVersion = 85;
459 if (Bits[NVPTX::PTX86] && PTXVersion < 86) PTXVersion = 86;
460 if (Bits[NVPTX::PTX87] && PTXVersion < 87) PTXVersion = 87;
461 if (Bits[NVPTX::PTX88] && PTXVersion < 88) PTXVersion = 88;
462 if (Bits[NVPTX::PTX90] && PTXVersion < 90) PTXVersion = 90;
463 if (Bits[NVPTX::PTX91] && PTXVersion < 91) PTXVersion = 91;
464 if (Bits[NVPTX::PTX92] && PTXVersion < 92) PTXVersion = 92;
465 if (Bits[NVPTX::PTX93] && PTXVersion < 93) PTXVersion = 93;
466 if (Bits[NVPTX::SM20] && FullSmVersion < 200) FullSmVersion = 200;
467 if (Bits[NVPTX::SM21] && FullSmVersion < 210) FullSmVersion = 210;
468 if (Bits[NVPTX::SM30] && FullSmVersion < 300) FullSmVersion = 300;
469 if (Bits[NVPTX::SM32] && FullSmVersion < 320) FullSmVersion = 320;
470 if (Bits[NVPTX::SM35] && FullSmVersion < 350) FullSmVersion = 350;
471 if (Bits[NVPTX::SM37] && FullSmVersion < 370) FullSmVersion = 370;
472 if (Bits[NVPTX::SM50] && FullSmVersion < 500) FullSmVersion = 500;
473 if (Bits[NVPTX::SM52] && FullSmVersion < 520) FullSmVersion = 520;
474 if (Bits[NVPTX::SM53] && FullSmVersion < 530) FullSmVersion = 530;
475 if (Bits[NVPTX::SM60] && FullSmVersion < 600) FullSmVersion = 600;
476 if (Bits[NVPTX::SM61] && FullSmVersion < 610) FullSmVersion = 610;
477 if (Bits[NVPTX::SM62] && FullSmVersion < 620) FullSmVersion = 620;
478 if (Bits[NVPTX::SM70] && FullSmVersion < 700) FullSmVersion = 700;
479 if (Bits[NVPTX::SM72] && FullSmVersion < 720) FullSmVersion = 720;
480 if (Bits[NVPTX::SM75] && FullSmVersion < 750) FullSmVersion = 750;
481 if (Bits[NVPTX::SM80] && FullSmVersion < 800) FullSmVersion = 800;
482 if (Bits[NVPTX::SM86] && FullSmVersion < 860) FullSmVersion = 860;
483 if (Bits[NVPTX::SM87] && FullSmVersion < 870) FullSmVersion = 870;
484 if (Bits[NVPTX::SM88] && FullSmVersion < 880) FullSmVersion = 880;
485 if (Bits[NVPTX::SM89] && FullSmVersion < 890) FullSmVersion = 890;
486 if (Bits[NVPTX::SM90] && FullSmVersion < 900) FullSmVersion = 900;
487 if (Bits[NVPTX::SM90a] && FullSmVersion < 903) FullSmVersion = 903;
488 if (Bits[NVPTX::SM100] && FullSmVersion < 1000) FullSmVersion = 1000;
489 if (Bits[NVPTX::SM100a] && FullSmVersion < 1003) FullSmVersion = 1003;
490 if (Bits[NVPTX::SM100f] && FullSmVersion < 1002) FullSmVersion = 1002;
491 if (Bits[NVPTX::SM101] && FullSmVersion < 1010) FullSmVersion = 1010;
492 if (Bits[NVPTX::SM101a] && FullSmVersion < 1013) FullSmVersion = 1013;
493 if (Bits[NVPTX::SM101f] && FullSmVersion < 1012) FullSmVersion = 1012;
494 if (Bits[NVPTX::SM103] && FullSmVersion < 1030) FullSmVersion = 1030;
495 if (Bits[NVPTX::SM103a] && FullSmVersion < 1033) FullSmVersion = 1033;
496 if (Bits[NVPTX::SM103f] && FullSmVersion < 1032) FullSmVersion = 1032;
497 if (Bits[NVPTX::SM110] && FullSmVersion < 1100) FullSmVersion = 1100;
498 if (Bits[NVPTX::SM110a] && FullSmVersion < 1103) FullSmVersion = 1103;
499 if (Bits[NVPTX::SM110f] && FullSmVersion < 1102) FullSmVersion = 1102;
500 if (Bits[NVPTX::SM120] && FullSmVersion < 1200) FullSmVersion = 1200;
501 if (Bits[NVPTX::SM120a] && FullSmVersion < 1203) FullSmVersion = 1203;
502 if (Bits[NVPTX::SM120f] && FullSmVersion < 1202) FullSmVersion = 1202;
503 if (Bits[NVPTX::SM121] && FullSmVersion < 1210) FullSmVersion = 1210;
504 if (Bits[NVPTX::SM121a] && FullSmVersion < 1213) FullSmVersion = 1213;
505 if (Bits[NVPTX::SM121f] && FullSmVersion < 1212) FullSmVersion = 1212;
506}
507
508#endif // GET_SUBTARGETINFO_TARGET_DESC
509
510#ifdef GET_SUBTARGETINFO_HEADER
511#undef GET_SUBTARGETINFO_HEADER
512
513namespace llvm {
514
515class DFAPacketizer;
516namespace NVPTX_MC {
517
518unsigned resolveVariantSchedClassImpl(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, const MCSubtargetInfo &STI, unsigned CPUID);
519
520} // namespace NVPTX_MC
521struct NVPTXGenSubtargetInfo : public TargetSubtargetInfo {
522 explicit NVPTXGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS);
523public:
524 unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const final;
525 unsigned resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const final;
526 DFAPacketizer *createDFAPacketizer(const InstrItineraryData *IID) const;
527 enum class NVPTXHwModeBits : unsigned {
528 DefaultMode = 0,
529 NVPTX64 = (1 << 0),
530
531 LLVM_MARK_AS_BITMASK_ENUM(/*LargestValue=*/NVPTX64),
532 };
533 unsigned getHwModeSet() const final;
534 unsigned getHwMode(enum HwModeType type = HwMode_Default) const final;
535 const FeatureBitset &getInlineIgnoreFeatures() const override;
536 const FeatureBitset &getInlineInverseFeatures() const override;
537 const FeatureBitset &getInlineMustMatchFeatures() const override;
538};
539
540} // namespace llvm
541
542#endif // GET_SUBTARGETINFO_HEADER
543
544#ifdef GET_SUBTARGETINFO_CTOR
545#undef GET_SUBTARGETINFO_CTOR
546
547#include "llvm/CodeGen/TargetSchedule.h"
548
549namespace llvm {
550
551extern const llvm::StringRef NVPTXNames[];
552extern const llvm::SubtargetFeatureKVStorage<74, 1674> NVPTXFeatureKVStorage;
553extern const llvm::SubtargetSubTypeKVStorage<40, 273> NVPTXSubTypeKVStorage;
554extern const llvm::MCSchedModel NVPTXSchedModels[];
555extern const llvm::MCWriteProcResEntry NVPTXWriteProcResTable[];
556extern const llvm::MCWriteLatencyEntry NVPTXWriteLatencyTable[];
557extern const llvm::MCReadAdvanceEntry NVPTXReadAdvanceTable[];
558NVPTXGenSubtargetInfo::NVPTXGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS)
559 : TargetSubtargetInfo(TT, CPU, TuneCPU, FS, StringTable(NVPTXSubTypeKVStorage.Strings), ArrayRef(NVPTXFeatureKVStorage.Features), ArrayRef(NVPTXSubTypeKVStorage.SubTypes), NVPTXSchedModels,
560 NVPTXWriteProcResTable, NVPTXWriteLatencyTable, NVPTXReadAdvanceTable,
561 nullptr, nullptr, nullptr) {}
562
563unsigned NVPTXGenSubtargetInfo
564::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const {
565 report_fatal_error("Expected a variant SchedClass");
566} // NVPTXGenSubtargetInfo::resolveSchedClass
567
568unsigned NVPTXGenSubtargetInfo
569::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const {
570 return NVPTX_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, *this, CPUID);
571} // NVPTXGenSubtargetInfo::resolveVariantSchedClass
572
573unsigned NVPTXGenSubtargetInfo::getHwModeSet() const {
574 [[maybe_unused]] const auto *Subtarget =
575 static_cast<const NVPTXSubtarget *>(this);
576 // Collect HwModes and store them as a bit set.
577 unsigned Modes = 0;
578 if ((Subtarget->getTargetTriple().getArch() == Triple::nvptx64)) Modes |= (1 << 0);
579 return Modes;
580}
581unsigned NVPTXGenSubtargetInfo::getHwMode(enum HwModeType type) const {
582 unsigned Modes = getHwModeSet();
583
584 if (!Modes)
585 return Modes;
586
587 switch (type) {
588 case HwMode_Default:
589 return llvm::countr_zero(Modes) + 1;
590 case HwMode_ValueType:
591 // No HwMode for ValueType.
592 return 0;
593 case HwMode_RegInfo:
594 Modes &= 1;
595 if (!Modes)
596 return Modes;
597 if (!llvm::has_single_bit<unsigned>(Modes))
598 llvm_unreachable("Two or more HwModes for RegInfo were found!");
599 return llvm::countr_zero(Modes) + 1;
600 case HwMode_EncodingInfo:
601 // No HwMode for EncodingInfo.
602 return 0;
603 }
604 llvm_unreachable("unexpected HwModeType");
605 return 0; // should not get here
606}
607const FeatureBitset &NVPTXGenSubtargetInfo::getInlineIgnoreFeatures() const {
608 static constexpr FeatureBitset Features = {
609 };
610 return Features;
611}
612
613const FeatureBitset &NVPTXGenSubtargetInfo::getInlineInverseFeatures() const {
614 static constexpr FeatureBitset Features = {
615 };
616 return Features;
617}
618
619const FeatureBitset &NVPTXGenSubtargetInfo::getInlineMustMatchFeatures() const {
620 static constexpr FeatureBitset Features = {
621 };
622 return Features;
623}
624
625
626} // namespace llvm
627
628#endif // GET_SUBTARGETINFO_CTOR
629
630#ifdef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
631#undef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
632
633
634#endif // GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
635
636#ifdef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
637#undef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
638
639
640#endif // GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
641
642