1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Subtarget Enumeration Source Fragment *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_SUBTARGETINFO_ENUM
10#undef GET_SUBTARGETINFO_ENUM
11
12namespace llvm {
13
14namespace NVPTX {
15
16enum {
17 PTX32 = 0,
18 PTX40 = 1,
19 PTX41 = 2,
20 PTX42 = 3,
21 PTX43 = 4,
22 PTX50 = 5,
23 PTX60 = 6,
24 PTX61 = 7,
25 PTX62 = 8,
26 PTX63 = 9,
27 PTX64 = 10,
28 PTX65 = 11,
29 PTX70 = 12,
30 PTX71 = 13,
31 PTX72 = 14,
32 PTX73 = 15,
33 PTX74 = 16,
34 PTX75 = 17,
35 PTX76 = 18,
36 PTX77 = 19,
37 PTX78 = 20,
38 PTX80 = 21,
39 PTX81 = 22,
40 PTX82 = 23,
41 PTX83 = 24,
42 PTX84 = 25,
43 PTX85 = 26,
44 PTX86 = 27,
45 PTX87 = 28,
46 PTX88 = 29,
47 PTX90 = 30,
48 SM20 = 31,
49 SM21 = 32,
50 SM30 = 33,
51 SM32 = 34,
52 SM35 = 35,
53 SM37 = 36,
54 SM50 = 37,
55 SM52 = 38,
56 SM53 = 39,
57 SM60 = 40,
58 SM61 = 41,
59 SM62 = 42,
60 SM70 = 43,
61 SM72 = 44,
62 SM75 = 45,
63 SM80 = 46,
64 SM86 = 47,
65 SM87 = 48,
66 SM88 = 49,
67 SM89 = 50,
68 SM90 = 51,
69 SM90a = 52,
70 SM100 = 53,
71 SM100a = 54,
72 SM100f = 55,
73 SM101 = 56,
74 SM101a = 57,
75 SM101f = 58,
76 SM103 = 59,
77 SM103a = 60,
78 SM103f = 61,
79 SM110 = 62,
80 SM110a = 63,
81 SM110f = 64,
82 SM120 = 65,
83 SM120a = 66,
84 SM120f = 67,
85 SM121 = 68,
86 SM121a = 69,
87 SM121f = 70,
88 NumSubtargetFeatures = 71
89};
90
91} // namespace NVPTX
92
93} // namespace llvm
94
95#endif // GET_SUBTARGETINFO_ENUM
96
97#ifdef GET_SUBTARGETINFO_MACRO
98
99
100#undef GET_SUBTARGETINFO_MACRO
101#endif // GET_SUBTARGETINFO_MACRO
102
103#ifdef GET_SUBTARGETINFO_MC_DESC
104#undef GET_SUBTARGETINFO_MC_DESC
105
106namespace llvm {
107
108// Sorted (by key) array of values for CPU features.
109extern const llvm::SubtargetFeatureKV NVPTXFeatureKV[] = {
110 { "ptx32", "Use PTX version 32", NVPTX::PTX32, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
111 { "ptx40", "Use PTX version 40", NVPTX::PTX40, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
112 { "ptx41", "Use PTX version 41", NVPTX::PTX41, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
113 { "ptx42", "Use PTX version 42", NVPTX::PTX42, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
114 { "ptx43", "Use PTX version 43", NVPTX::PTX43, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
115 { "ptx50", "Use PTX version 50", NVPTX::PTX50, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
116 { "ptx60", "Use PTX version 60", NVPTX::PTX60, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
117 { "ptx61", "Use PTX version 61", NVPTX::PTX61, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
118 { "ptx62", "Use PTX version 62", NVPTX::PTX62, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
119 { "ptx63", "Use PTX version 63", NVPTX::PTX63, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
120 { "ptx64", "Use PTX version 64", NVPTX::PTX64, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
121 { "ptx65", "Use PTX version 65", NVPTX::PTX65, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
122 { "ptx70", "Use PTX version 70", NVPTX::PTX70, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
123 { "ptx71", "Use PTX version 71", NVPTX::PTX71, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
124 { "ptx72", "Use PTX version 72", NVPTX::PTX72, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
125 { "ptx73", "Use PTX version 73", NVPTX::PTX73, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
126 { "ptx74", "Use PTX version 74", NVPTX::PTX74, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
127 { "ptx75", "Use PTX version 75", NVPTX::PTX75, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
128 { "ptx76", "Use PTX version 76", NVPTX::PTX76, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
129 { "ptx77", "Use PTX version 77", NVPTX::PTX77, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
130 { "ptx78", "Use PTX version 78", NVPTX::PTX78, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
131 { "ptx80", "Use PTX version 80", NVPTX::PTX80, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
132 { "ptx81", "Use PTX version 81", NVPTX::PTX81, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
133 { "ptx82", "Use PTX version 82", NVPTX::PTX82, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
134 { "ptx83", "Use PTX version 83", NVPTX::PTX83, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
135 { "ptx84", "Use PTX version 84", NVPTX::PTX84, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
136 { "ptx85", "Use PTX version 85", NVPTX::PTX85, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
137 { "ptx86", "Use PTX version 86", NVPTX::PTX86, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
138 { "ptx87", "Use PTX version 87", NVPTX::PTX87, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
139 { "ptx88", "Use PTX version 88", NVPTX::PTX88, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
140 { "ptx90", "Use PTX version 90", NVPTX::PTX90, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
141 { "sm_100", "Target SM 100", NVPTX::SM100, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
142 { "sm_100a", "Target SM 100a", NVPTX::SM100a, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
143 { "sm_100f", "Target SM 100f", NVPTX::SM100f, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
144 { "sm_101", "Target SM 101", NVPTX::SM101, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
145 { "sm_101a", "Target SM 101a", NVPTX::SM101a, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
146 { "sm_101f", "Target SM 101f", NVPTX::SM101f, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
147 { "sm_103", "Target SM 103", NVPTX::SM103, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
148 { "sm_103a", "Target SM 103a", NVPTX::SM103a, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
149 { "sm_103f", "Target SM 103f", NVPTX::SM103f, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
150 { "sm_110", "Target SM 110", NVPTX::SM110, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
151 { "sm_110a", "Target SM 110a", NVPTX::SM110a, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
152 { "sm_110f", "Target SM 110f", NVPTX::SM110f, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
153 { "sm_120", "Target SM 120", NVPTX::SM120, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
154 { "sm_120a", "Target SM 120a", NVPTX::SM120a, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
155 { "sm_120f", "Target SM 120f", NVPTX::SM120f, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
156 { "sm_121", "Target SM 121", NVPTX::SM121, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
157 { "sm_121a", "Target SM 121a", NVPTX::SM121a, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
158 { "sm_121f", "Target SM 121f", NVPTX::SM121f, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
159 { "sm_20", "Target SM 20", NVPTX::SM20, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
160 { "sm_21", "Target SM 21", NVPTX::SM21, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
161 { "sm_30", "Target SM 30", NVPTX::SM30, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
162 { "sm_32", "Target SM 32", NVPTX::SM32, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
163 { "sm_35", "Target SM 35", NVPTX::SM35, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
164 { "sm_37", "Target SM 37", NVPTX::SM37, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
165 { "sm_50", "Target SM 50", NVPTX::SM50, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
166 { "sm_52", "Target SM 52", NVPTX::SM52, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
167 { "sm_53", "Target SM 53", NVPTX::SM53, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
168 { "sm_60", "Target SM 60", NVPTX::SM60, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
169 { "sm_61", "Target SM 61", NVPTX::SM61, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
170 { "sm_62", "Target SM 62", NVPTX::SM62, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
171 { "sm_70", "Target SM 70", NVPTX::SM70, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
172 { "sm_72", "Target SM 72", NVPTX::SM72, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
173 { "sm_75", "Target SM 75", NVPTX::SM75, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
174 { "sm_80", "Target SM 80", NVPTX::SM80, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
175 { "sm_86", "Target SM 86", NVPTX::SM86, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
176 { "sm_87", "Target SM 87", NVPTX::SM87, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
177 { "sm_88", "Target SM 88", NVPTX::SM88, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
178 { "sm_89", "Target SM 89", NVPTX::SM89, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
179 { "sm_90", "Target SM 90", NVPTX::SM90, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
180 { "sm_90a", "Target SM 90a", NVPTX::SM90a, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
181};
182
183#ifdef DBGFIELD
184#error "<target>GenSubtargetInfo.inc requires a DBGFIELD macro"
185#endif
186#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
187#define DBGFIELD(x) x,
188#define DBGVAL_OR_NULLPTR(x) x
189#else
190#define DBGFIELD(x)
191#define DBGVAL_OR_NULLPTR(x) nullptr
192#endif
193
194// ===============================================================
195// Data tables for the new per-operand machine model.
196
197// {ProcResourceIdx, ReleaseAtCycle, AcquireAtCycle}
198extern const llvm::MCWriteProcResEntry NVPTXWriteProcResTable[] = {
199 { 0, 0, 0 }, // Invalid
200}; // NVPTXWriteProcResTable
201
202// {Cycles, WriteResourceID}
203extern const llvm::MCWriteLatencyEntry NVPTXWriteLatencyTable[] = {
204 { 0, 0}, // Invalid
205}; // NVPTXWriteLatencyTable
206
207// {UseIdx, WriteResourceID, Cycles}
208extern const llvm::MCReadAdvanceEntry NVPTXReadAdvanceTable[] = {
209 {0, 0, 0}, // Invalid
210}; // NVPTXReadAdvanceTable
211
212#ifdef __GNUC__
213#pragma GCC diagnostic push
214#pragma GCC diagnostic ignored "-Woverlength-strings"
215#endif
216static constexpr char NVPTXSchedClassNamesStorage[] =
217 "\0"
218 "InvalidSchedClass\0"
219 ;
220#ifdef __GNUC__
221#pragma GCC diagnostic pop
222#endif
223
224static constexpr llvm::StringTable
225NVPTXSchedClassNames = NVPTXSchedClassNamesStorage;
226
227static const llvm::MCSchedModel NoSchedModel = {
228 MCSchedModel::DefaultIssueWidth,
229 MCSchedModel::DefaultMicroOpBufferSize,
230 MCSchedModel::DefaultLoopMicroOpBufferSize,
231 MCSchedModel::DefaultLoadLatency,
232 MCSchedModel::DefaultHighLatency,
233 MCSchedModel::DefaultMispredictPenalty,
234 false, // PostRAScheduler
235 false, // CompleteModel
236 false, // EnableIntervals
237 0, // Processor ID
238 nullptr, nullptr, 0, 0, // No instruction-level machine model.
239 DBGVAL_OR_NULLPTR(&NVPTXSchedClassNames), // SchedClassNames
240 nullptr, // No Itinerary
241 nullptr // No extra processor descriptor
242};
243
244#undef DBGFIELD
245
246#undef DBGVAL_OR_NULLPTR
247
248// Sorted (by key) array of values for CPU subtype.
249extern const llvm::SubtargetSubTypeKV NVPTXSubTypeKV[] = {
250 { "sm_100", { { { 0x20000008000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
251 { "sm_100a", { { { 0x40000008000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
252 { "sm_100f", { { { 0x80000020000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
253 { "sm_101", { { { 0x100000008000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
254 { "sm_101a", { { { 0x200000008000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
255 { "sm_101f", { { { 0x400000020000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
256 { "sm_103", { { { 0x800000020000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
257 { "sm_103a", { { { 0x1000000020000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
258 { "sm_103f", { { { 0x2000000020000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
259 { "sm_110", { { { 0x4000000040000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
260 { "sm_110a", { { { 0x8000000040000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
261 { "sm_110f", { { { 0x40000000ULL, 0x1ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
262 { "sm_120", { { { 0x10000000ULL, 0x2ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
263 { "sm_120a", { { { 0x10000000ULL, 0x4ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
264 { "sm_120f", { { { 0x20000000ULL, 0x8ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
265 { "sm_121", { { { 0x20000000ULL, 0x10ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
266 { "sm_121a", { { { 0x20000000ULL, 0x20ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
267 { "sm_121f", { { { 0x20000000ULL, 0x40ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
268 { "sm_20", { { { 0x80000001ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
269 { "sm_21", { { { 0x100000001ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
270 { "sm_30", { { { 0x200000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
271 { "sm_32", { { { 0x400000002ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
272 { "sm_35", { { { 0x800000001ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
273 { "sm_37", { { { 0x1000000004ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
274 { "sm_50", { { { 0x2000000002ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
275 { "sm_52", { { { 0x4000000004ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
276 { "sm_53", { { { 0x8000000008ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
277 { "sm_60", { { { 0x10000000020ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
278 { "sm_61", { { { 0x20000000020ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
279 { "sm_62", { { { 0x40000000020ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
280 { "sm_70", { { { 0x80000000040ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
281 { "sm_72", { { { 0x100000000080ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
282 { "sm_75", { { { 0x200000000200ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
283 { "sm_80", { { { 0x400000001000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
284 { "sm_86", { { { 0x800000002000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
285 { "sm_87", { { { 0x1000000010000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
286 { "sm_88", { { { 0x2000040000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
287 { "sm_89", { { { 0x4000000100000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
288 { "sm_90", { { { 0x8000000100000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
289 { "sm_90a", { { { 0x10000000200000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
290};
291
292// Sorted array of names of CPU subtypes, including aliases.
293extern const llvm::StringRef NVPTXNames[] = {
294"sm_100",
295"sm_100a",
296"sm_100f",
297"sm_101",
298"sm_101a",
299"sm_101f",
300"sm_103",
301"sm_103a",
302"sm_103f",
303"sm_110",
304"sm_110a",
305"sm_110f",
306"sm_120",
307"sm_120a",
308"sm_120f",
309"sm_121",
310"sm_121a",
311"sm_121f",
312"sm_20",
313"sm_21",
314"sm_30",
315"sm_32",
316"sm_35",
317"sm_37",
318"sm_50",
319"sm_52",
320"sm_53",
321"sm_60",
322"sm_61",
323"sm_62",
324"sm_70",
325"sm_72",
326"sm_75",
327"sm_80",
328"sm_86",
329"sm_87",
330"sm_88",
331"sm_89",
332"sm_90",
333"sm_90a"};
334
335namespace NVPTX_MC {
336
337unsigned resolveVariantSchedClassImpl(unsigned SchedClass,
338 const MCInst *MI, const MCInstrInfo *MCII, const MCSubtargetInfo &STI, unsigned CPUID) {
339 // Don't know how to resolve this scheduling class.
340 return 0;
341}
342
343} // namespace NVPTX_MC
344struct NVPTXGenMCSubtargetInfo : public MCSubtargetInfo {
345 NVPTXGenMCSubtargetInfo(const Triple &TT,
346 StringRef CPU, StringRef TuneCPU, StringRef FS,
347 ArrayRef<StringRef> PN,
348 ArrayRef<SubtargetFeatureKV> PF,
349 ArrayRef<SubtargetSubTypeKV> PD,
350 const MCWriteProcResEntry *WPR,
351 const MCWriteLatencyEntry *WL,
352 const MCReadAdvanceEntry *RA, const InstrStage *IS,
353 const unsigned *OC, const unsigned *FP) :
354 MCSubtargetInfo(TT, CPU, TuneCPU, FS, PN, PF, PD,
355 WPR, WL, RA, IS, OC, FP) { }
356
357 unsigned resolveVariantSchedClass(unsigned SchedClass,
358 const MCInst *MI, const MCInstrInfo *MCII,
359 unsigned CPUID) const final {
360 return NVPTX_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, *this, CPUID);
361 }
362 unsigned getHwModeSet() const final;
363 unsigned getHwMode(enum HwModeType type = HwMode_Default) const final;
364};
365unsigned NVPTXGenMCSubtargetInfo::getHwModeSet() const {
366 [[maybe_unused]] const FeatureBitset &FB = getFeatureBits();
367 // Collect HwModes and store them as a bit set.
368 unsigned Modes = 0;
369 if (false) Modes |= (1 << 0);
370 return Modes;
371}
372unsigned NVPTXGenMCSubtargetInfo::getHwMode(enum HwModeType type) const {
373 unsigned Modes = getHwModeSet();
374
375 if (!Modes)
376 return Modes;
377
378 switch (type) {
379 case HwMode_Default:
380 return llvm::countr_zero(Modes) + 1;
381 case HwMode_ValueType:
382 Modes &= 0;
383 if (!Modes)
384 return Modes;
385 if (!llvm::has_single_bit<unsigned>(Modes))
386 llvm_unreachable("Two or more HwModes for ValueType were found!");
387 return llvm::countr_zero(Modes) + 1;
388 case HwMode_RegInfo:
389 Modes &= 1;
390 if (!Modes)
391 return Modes;
392 if (!llvm::has_single_bit<unsigned>(Modes))
393 llvm_unreachable("Two or more HwModes for RegInfo were found!");
394 return llvm::countr_zero(Modes) + 1;
395 case HwMode_EncodingInfo:
396 Modes &= 0;
397 if (!Modes)
398 return Modes;
399 if (!llvm::has_single_bit<unsigned>(Modes))
400 llvm_unreachable("Two or more HwModes for EncodingInfo were found!");
401 return llvm::countr_zero(Modes) + 1;
402 }
403 llvm_unreachable("unexpected HwModeType");
404 return 0; // should not get here
405}
406
407static inline MCSubtargetInfo *createNVPTXMCSubtargetInfoImpl(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS) {
408 return new NVPTXGenMCSubtargetInfo(TT, CPU, TuneCPU, FS, NVPTXNames, NVPTXFeatureKV, NVPTXSubTypeKV,
409 NVPTXWriteProcResTable, NVPTXWriteLatencyTable, NVPTXReadAdvanceTable,
410 nullptr, nullptr, nullptr);
411}
412
413
414} // namespace llvm
415
416#endif // GET_SUBTARGETINFO_MC_DESC
417
418#ifdef GET_SUBTARGETINFO_TARGET_DESC
419#undef GET_SUBTARGETINFO_TARGET_DESC
420
421#include "llvm/ADT/BitmaskEnum.h"
422#include "llvm/Support/Debug.h"
423#include "llvm/Support/raw_ostream.h"
424
425// ParseSubtargetFeatures - Parses features string setting specified
426// subtarget options.
427void llvm::NVPTXSubtarget::ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS) {
428 LLVM_DEBUG(dbgs() << "\nFeatures:" << FS);
429 LLVM_DEBUG(dbgs() << "\nCPU:" << CPU);
430 LLVM_DEBUG(dbgs() << "\nTuneCPU:" << TuneCPU << "\n\n");
431 InitMCProcessorInfo(CPU, TuneCPU, FS);
432 const FeatureBitset &Bits = getFeatureBits();
433 if (Bits[NVPTX::PTX32] && PTXVersion < 32) PTXVersion = 32;
434 if (Bits[NVPTX::PTX40] && PTXVersion < 40) PTXVersion = 40;
435 if (Bits[NVPTX::PTX41] && PTXVersion < 41) PTXVersion = 41;
436 if (Bits[NVPTX::PTX42] && PTXVersion < 42) PTXVersion = 42;
437 if (Bits[NVPTX::PTX43] && PTXVersion < 43) PTXVersion = 43;
438 if (Bits[NVPTX::PTX50] && PTXVersion < 50) PTXVersion = 50;
439 if (Bits[NVPTX::PTX60] && PTXVersion < 60) PTXVersion = 60;
440 if (Bits[NVPTX::PTX61] && PTXVersion < 61) PTXVersion = 61;
441 if (Bits[NVPTX::PTX62] && PTXVersion < 62) PTXVersion = 62;
442 if (Bits[NVPTX::PTX63] && PTXVersion < 63) PTXVersion = 63;
443 if (Bits[NVPTX::PTX64] && PTXVersion < 64) PTXVersion = 64;
444 if (Bits[NVPTX::PTX65] && PTXVersion < 65) PTXVersion = 65;
445 if (Bits[NVPTX::PTX70] && PTXVersion < 70) PTXVersion = 70;
446 if (Bits[NVPTX::PTX71] && PTXVersion < 71) PTXVersion = 71;
447 if (Bits[NVPTX::PTX72] && PTXVersion < 72) PTXVersion = 72;
448 if (Bits[NVPTX::PTX73] && PTXVersion < 73) PTXVersion = 73;
449 if (Bits[NVPTX::PTX74] && PTXVersion < 74) PTXVersion = 74;
450 if (Bits[NVPTX::PTX75] && PTXVersion < 75) PTXVersion = 75;
451 if (Bits[NVPTX::PTX76] && PTXVersion < 76) PTXVersion = 76;
452 if (Bits[NVPTX::PTX77] && PTXVersion < 77) PTXVersion = 77;
453 if (Bits[NVPTX::PTX78] && PTXVersion < 78) PTXVersion = 78;
454 if (Bits[NVPTX::PTX80] && PTXVersion < 80) PTXVersion = 80;
455 if (Bits[NVPTX::PTX81] && PTXVersion < 81) PTXVersion = 81;
456 if (Bits[NVPTX::PTX82] && PTXVersion < 82) PTXVersion = 82;
457 if (Bits[NVPTX::PTX83] && PTXVersion < 83) PTXVersion = 83;
458 if (Bits[NVPTX::PTX84] && PTXVersion < 84) PTXVersion = 84;
459 if (Bits[NVPTX::PTX85] && PTXVersion < 85) PTXVersion = 85;
460 if (Bits[NVPTX::PTX86] && PTXVersion < 86) PTXVersion = 86;
461 if (Bits[NVPTX::PTX87] && PTXVersion < 87) PTXVersion = 87;
462 if (Bits[NVPTX::PTX88] && PTXVersion < 88) PTXVersion = 88;
463 if (Bits[NVPTX::PTX90] && PTXVersion < 90) PTXVersion = 90;
464 if (Bits[NVPTX::SM20] && FullSmVersion < 200) FullSmVersion = 200;
465 if (Bits[NVPTX::SM21] && FullSmVersion < 210) FullSmVersion = 210;
466 if (Bits[NVPTX::SM30] && FullSmVersion < 300) FullSmVersion = 300;
467 if (Bits[NVPTX::SM32] && FullSmVersion < 320) FullSmVersion = 320;
468 if (Bits[NVPTX::SM35] && FullSmVersion < 350) FullSmVersion = 350;
469 if (Bits[NVPTX::SM37] && FullSmVersion < 370) FullSmVersion = 370;
470 if (Bits[NVPTX::SM50] && FullSmVersion < 500) FullSmVersion = 500;
471 if (Bits[NVPTX::SM52] && FullSmVersion < 520) FullSmVersion = 520;
472 if (Bits[NVPTX::SM53] && FullSmVersion < 530) FullSmVersion = 530;
473 if (Bits[NVPTX::SM60] && FullSmVersion < 600) FullSmVersion = 600;
474 if (Bits[NVPTX::SM61] && FullSmVersion < 610) FullSmVersion = 610;
475 if (Bits[NVPTX::SM62] && FullSmVersion < 620) FullSmVersion = 620;
476 if (Bits[NVPTX::SM70] && FullSmVersion < 700) FullSmVersion = 700;
477 if (Bits[NVPTX::SM72] && FullSmVersion < 720) FullSmVersion = 720;
478 if (Bits[NVPTX::SM75] && FullSmVersion < 750) FullSmVersion = 750;
479 if (Bits[NVPTX::SM80] && FullSmVersion < 800) FullSmVersion = 800;
480 if (Bits[NVPTX::SM86] && FullSmVersion < 860) FullSmVersion = 860;
481 if (Bits[NVPTX::SM87] && FullSmVersion < 870) FullSmVersion = 870;
482 if (Bits[NVPTX::SM88] && FullSmVersion < 880) FullSmVersion = 880;
483 if (Bits[NVPTX::SM89] && FullSmVersion < 890) FullSmVersion = 890;
484 if (Bits[NVPTX::SM90] && FullSmVersion < 900) FullSmVersion = 900;
485 if (Bits[NVPTX::SM90a] && FullSmVersion < 903) FullSmVersion = 903;
486 if (Bits[NVPTX::SM100] && FullSmVersion < 1000) FullSmVersion = 1000;
487 if (Bits[NVPTX::SM100a] && FullSmVersion < 1003) FullSmVersion = 1003;
488 if (Bits[NVPTX::SM100f] && FullSmVersion < 1002) FullSmVersion = 1002;
489 if (Bits[NVPTX::SM101] && FullSmVersion < 1010) FullSmVersion = 1010;
490 if (Bits[NVPTX::SM101a] && FullSmVersion < 1013) FullSmVersion = 1013;
491 if (Bits[NVPTX::SM101f] && FullSmVersion < 1012) FullSmVersion = 1012;
492 if (Bits[NVPTX::SM103] && FullSmVersion < 1030) FullSmVersion = 1030;
493 if (Bits[NVPTX::SM103a] && FullSmVersion < 1033) FullSmVersion = 1033;
494 if (Bits[NVPTX::SM103f] && FullSmVersion < 1032) FullSmVersion = 1032;
495 if (Bits[NVPTX::SM110] && FullSmVersion < 1100) FullSmVersion = 1100;
496 if (Bits[NVPTX::SM110a] && FullSmVersion < 1103) FullSmVersion = 1103;
497 if (Bits[NVPTX::SM110f] && FullSmVersion < 1102) FullSmVersion = 1102;
498 if (Bits[NVPTX::SM120] && FullSmVersion < 1200) FullSmVersion = 1200;
499 if (Bits[NVPTX::SM120a] && FullSmVersion < 1203) FullSmVersion = 1203;
500 if (Bits[NVPTX::SM120f] && FullSmVersion < 1202) FullSmVersion = 1202;
501 if (Bits[NVPTX::SM121] && FullSmVersion < 1210) FullSmVersion = 1210;
502 if (Bits[NVPTX::SM121a] && FullSmVersion < 1213) FullSmVersion = 1213;
503 if (Bits[NVPTX::SM121f] && FullSmVersion < 1212) FullSmVersion = 1212;
504}
505
506#endif // GET_SUBTARGETINFO_TARGET_DESC
507
508#ifdef GET_SUBTARGETINFO_HEADER
509#undef GET_SUBTARGETINFO_HEADER
510
511namespace llvm {
512
513class DFAPacketizer;
514namespace NVPTX_MC {
515
516unsigned resolveVariantSchedClassImpl(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, const MCSubtargetInfo &STI, unsigned CPUID);
517
518} // namespace NVPTX_MC
519struct NVPTXGenSubtargetInfo : public TargetSubtargetInfo {
520 explicit NVPTXGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS);
521public:
522 unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const final;
523 unsigned resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const final;
524 DFAPacketizer *createDFAPacketizer(const InstrItineraryData *IID) const;
525 enum class NVPTXHwModeBits : unsigned {
526 DefaultMode = 0,
527 NVPTX64 = (1 << 0),
528
529 LLVM_MARK_AS_BITMASK_ENUM(/*LargestValue=*/NVPTX64),
530 };
531 unsigned getHwModeSet() const final;
532 unsigned getHwMode(enum HwModeType type = HwMode_Default) const final;
533};
534
535} // namespace llvm
536
537#endif // GET_SUBTARGETINFO_HEADER
538
539#ifdef GET_SUBTARGETINFO_CTOR
540#undef GET_SUBTARGETINFO_CTOR
541
542#include "llvm/CodeGen/TargetSchedule.h"
543
544namespace llvm {
545
546extern const llvm::StringRef NVPTXNames[];
547extern const llvm::SubtargetFeatureKV NVPTXFeatureKV[];
548extern const llvm::SubtargetSubTypeKV NVPTXSubTypeKV[];
549extern const llvm::MCWriteProcResEntry NVPTXWriteProcResTable[];
550extern const llvm::MCWriteLatencyEntry NVPTXWriteLatencyTable[];
551extern const llvm::MCReadAdvanceEntry NVPTXReadAdvanceTable[];
552NVPTXGenSubtargetInfo::NVPTXGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS)
553 : TargetSubtargetInfo(TT, CPU, TuneCPU, FS, ArrayRef(NVPTXNames, 40), ArrayRef(NVPTXFeatureKV, 71), ArrayRef(NVPTXSubTypeKV, 40),
554 NVPTXWriteProcResTable, NVPTXWriteLatencyTable, NVPTXReadAdvanceTable,
555 nullptr, nullptr, nullptr) {}
556
557unsigned NVPTXGenSubtargetInfo
558::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const {
559 report_fatal_error("Expected a variant SchedClass");
560} // NVPTXGenSubtargetInfo::resolveSchedClass
561
562unsigned NVPTXGenSubtargetInfo
563::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const {
564 return NVPTX_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, *this, CPUID);
565} // NVPTXGenSubtargetInfo::resolveVariantSchedClass
566
567unsigned NVPTXGenSubtargetInfo::getHwModeSet() const {
568 [[maybe_unused]] const auto *Subtarget =
569 static_cast<const NVPTXSubtarget *>(this);
570 // Collect HwModes and store them as a bit set.
571 unsigned Modes = 0;
572 if ((Subtarget->getTargetTriple().getArch() == Triple::nvptx64)) Modes |= (1 << 0);
573 return Modes;
574}
575unsigned NVPTXGenSubtargetInfo::getHwMode(enum HwModeType type) const {
576 unsigned Modes = getHwModeSet();
577
578 if (!Modes)
579 return Modes;
580
581 switch (type) {
582 case HwMode_Default:
583 return llvm::countr_zero(Modes) + 1;
584 case HwMode_ValueType:
585 Modes &= 0;
586 if (!Modes)
587 return Modes;
588 if (!llvm::has_single_bit<unsigned>(Modes))
589 llvm_unreachable("Two or more HwModes for ValueType were found!");
590 return llvm::countr_zero(Modes) + 1;
591 case HwMode_RegInfo:
592 Modes &= 1;
593 if (!Modes)
594 return Modes;
595 if (!llvm::has_single_bit<unsigned>(Modes))
596 llvm_unreachable("Two or more HwModes for RegInfo were found!");
597 return llvm::countr_zero(Modes) + 1;
598 case HwMode_EncodingInfo:
599 Modes &= 0;
600 if (!Modes)
601 return Modes;
602 if (!llvm::has_single_bit<unsigned>(Modes))
603 llvm_unreachable("Two or more HwModes for EncodingInfo were found!");
604 return llvm::countr_zero(Modes) + 1;
605 }
606 llvm_unreachable("unexpected HwModeType");
607 return 0; // should not get here
608}
609
610} // namespace llvm
611
612#endif // GET_SUBTARGETINFO_CTOR
613
614#ifdef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
615#undef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
616
617
618#endif // GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
619
620#ifdef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
621#undef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
622
623
624#endif // GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
625
626