1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* * PPC Disassembler *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9
10#include "llvm/MC/MCInst.h"
11#include "llvm/MC/MCSubtargetInfo.h"
12#include "llvm/Support/DataTypes.h"
13#include "llvm/Support/Debug.h"
14#include "llvm/Support/LEB128.h"
15#include "llvm/Support/raw_ostream.h"
16#include "llvm/TargetParser/SubtargetFeature.h"
17#include <assert.h>
18
19namespace {
20
21// InsnBitWidth is essentially a type trait used by the decoder emitter to query
22// the supported bitwidth for a given type. But default, the value is 0, making
23// it an invalid type for use as `InsnType` when instantiating the decoder.
24// Individual targets are expected to provide specializations for these based
25// on their usage.
26template <typename T> constexpr uint32_t InsnBitWidth = 0;
27
28[[maybe_unused]]
29static DecodeStatus Decodeppc_ptr_rcRegClassByHwMode(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder) {
30 switch (Decoder->getSubtargetInfo().getHwMode(type: MCSubtargetInfo::HwMode_RegInfo)) {
31 case 0: // DefaultMode
32 return DecodeGPRCRegisterClass(Inst, RegNo: Imm, Address: Addr, Decoder);
33 case 1: // PPC64
34 return DecodeG8RCRegisterClass(Inst, RegNo: Imm, Address: Addr, Decoder);
35 default:
36 llvm_unreachable("no decoder for hwmode");
37 }
38}
39
40[[maybe_unused]]
41static DecodeStatus Decodeptr_rc_idx_by_hwmodeRegClassByHwMode(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder) {
42 switch (Decoder->getSubtargetInfo().getHwMode(type: MCSubtargetInfo::HwMode_RegInfo)) {
43 case 0: // DefaultMode
44 return DecodeGPRCRegisterClass(Inst, RegNo: Imm, Address: Addr, Decoder);
45 case 1: // PPC64
46 return DecodeG8RCRegisterClass(Inst, RegNo: Imm, Address: Addr, Decoder);
47 default:
48 llvm_unreachable("no decoder for hwmode");
49 }
50}
51
52[[maybe_unused]]
53static DecodeStatus Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder) {
54 switch (Decoder->getSubtargetInfo().getHwMode(type: MCSubtargetInfo::HwMode_RegInfo)) {
55 case 0: // DefaultMode
56 return DecodeGPRC_NOR0RegisterClass(Inst, RegNo: Imm, Address: Addr, Decoder);
57 case 1: // PPC64
58 return DecodeG8RC_NOX0RegisterClass(Inst, RegNo: Imm, Address: Addr, Decoder);
59 default:
60 llvm_unreachable("no decoder for hwmode");
61 }
62}
63
64
65static const uint8_t DecoderTable32[16439] = {
66 OPC_SwitchField, 26, 6, // 0: switch Inst[31:26] {
67 0, 9, // 3: case 0x0: {
68 OPC_CheckField, 1, 10, 128, 2, // 5: check Inst[10:1] == 0x100
69 OPC_Decode, 170, 4, 0, // 10: decode to ATTN using decoder 0
70 // 10: }
71 2, 4, // 14: case 0x2: {
72 OPC_Decode, 249, 16, 1, // 16: decode to TDI using decoder 1
73 // 16: }
74 3, 4, // 20: case 0x3: {
75 OPC_Decode, 153, 17, 2, // 22: decode to TWI using decoder 2
76 // 22: }
77 4, 186, 31, // 26: case 0x4: {
78 OPC_SwitchField, 1, 5, // 29: switch Inst[5:1] {
79 0, 215, 3, // 32: case 0x0: {
80 OPC_SwitchField, 6, 3, // 35: switch Inst[8:6] {
81 0, 68, // 38: case 0x0: {
82 OPC_SwitchField, 0, 1, // 40: switch Inst[0] {
83 0, 27, // 43: case 0x0: {
84 OPC_SwitchField, 9, 2, // 45: switch Inst[10:9] {
85 0, 4, // 48: case 0x0: {
86 OPC_Decode, 167, 17, 3, // 50: decode to VADDUBM using decoder 3
87 // 50: }
88 1, 4, // 54: case 0x1: {
89 OPC_Decode, 168, 17, 3, // 56: decode to VADDUBS using decoder 3
90 // 56: }
91 2, 4, // 60: case 0x2: {
92 OPC_Decode, 135, 20, 3, // 62: decode to VSUBUBM using decoder 3
93 // 62: }
94 3, 0, // 66: case 0x3: {
95 OPC_Decode, 136, 20, 3, // 68: decode to VSUBUBS using decoder 3
96 // 68: }
97 // 68: } // switch Inst[10:9]
98 // 68: }
99 1, 0, // 72: case 0x1: {
100 OPC_SwitchField, 10, 1, // 74: switch Inst[10] {
101 0, 23, // 77: case 0x0: {
102 OPC_SwitchField, 9, 1, // 79: switch Inst[9] {
103 0, 8, // 82: case 0x0: {
104 OPC_CheckField, 11, 5, 0, // 84: check Inst[15:11] == 0x0
105 OPC_Decode, 130, 19, 4, // 88: decode to VMUL10CUQ using decoder 4
106 // 88: }
107 1, 0, // 92: case 0x1: {
108 OPC_CheckField, 11, 5, 0, // 94: check Inst[15:11] == 0x0
109 OPC_Decode, 133, 19, 4, // 98: decode to VMUL10UQ using decoder 4
110 // 98: }
111 // 98: } // switch Inst[9]
112 // 98: }
113 1, 0, // 102: case 0x1: {
114 OPC_Decode, 192, 4, 5, // 104: decode to BCDADD_rec using decoder 5
115 // 104: }
116 // 104: } // switch Inst[10]
117 // 104: }
118 // 104: } // switch Inst[0]
119 // 104: }
120 1, 60, // 108: case 0x1: {
121 OPC_SwitchField, 0, 1, // 110: switch Inst[0] {
122 0, 27, // 113: case 0x0: {
123 OPC_SwitchField, 9, 2, // 115: switch Inst[10:9] {
124 0, 4, // 118: case 0x0: {
125 OPC_Decode, 170, 17, 3, // 120: decode to VADDUHM using decoder 3
126 // 120: }
127 1, 4, // 124: case 0x1: {
128 OPC_Decode, 171, 17, 3, // 126: decode to VADDUHS using decoder 3
129 // 126: }
130 2, 4, // 130: case 0x2: {
131 OPC_Decode, 138, 20, 3, // 132: decode to VSUBUHM using decoder 3
132 // 132: }
133 3, 0, // 136: case 0x3: {
134 OPC_Decode, 139, 20, 3, // 138: decode to VSUBUHS using decoder 3
135 // 138: }
136 // 138: } // switch Inst[10:9]
137 // 138: }
138 1, 0, // 142: case 0x1: {
139 OPC_SwitchField, 10, 1, // 144: switch Inst[10] {
140 0, 15, // 147: case 0x0: {
141 OPC_SwitchField, 9, 1, // 149: switch Inst[9] {
142 0, 4, // 152: case 0x0: {
143 OPC_Decode, 131, 19, 3, // 154: decode to VMUL10ECUQ using decoder 3
144 // 154: }
145 1, 0, // 158: case 0x1: {
146 OPC_Decode, 132, 19, 3, // 160: decode to VMUL10EUQ using decoder 3
147 // 160: }
148 // 160: } // switch Inst[9]
149 // 160: }
150 1, 0, // 164: case 0x1: {
151 OPC_Decode, 202, 4, 5, // 166: decode to BCDSUB_rec using decoder 5
152 // 166: }
153 // 166: } // switch Inst[10]
154 // 166: }
155 // 166: } // switch Inst[0]
156 // 166: }
157 2, 50, // 170: case 0x2: {
158 OPC_SwitchField, 9, 2, // 172: switch Inst[10:9] {
159 0, 8, // 175: case 0x0: {
160 OPC_CheckField, 0, 1, 0, // 177: check Inst[0] == 0x0
161 OPC_Decode, 173, 17, 3, // 181: decode to VADDUWM using decoder 3
162 // 181: }
163 1, 8, // 185: case 0x1: {
164 OPC_CheckField, 0, 1, 0, // 187: check Inst[0] == 0x0
165 OPC_Decode, 174, 17, 3, // 191: decode to VADDUWS using decoder 3
166 // 191: }
167 2, 15, // 195: case 0x2: {
168 OPC_SwitchField, 0, 1, // 197: switch Inst[0] {
169 0, 4, // 200: case 0x0: {
170 OPC_Decode, 141, 20, 3, // 202: decode to VSUBUWM using decoder 3
171 // 202: }
172 1, 0, // 206: case 0x1: {
173 OPC_Decode, 205, 4, 3, // 208: decode to BCDUS_rec using decoder 3
174 // 208: }
175 // 208: } // switch Inst[0]
176 // 208: }
177 3, 0, // 212: case 0x3: {
178 OPC_CheckField, 0, 1, 0, // 214: check Inst[0] == 0x0
179 OPC_Decode, 142, 20, 3, // 218: decode to VSUBUWS using decoder 3
180 // 218: }
181 // 218: } // switch Inst[10:9]
182 // 218: }
183 3, 30, // 222: case 0x3: {
184 OPC_SwitchField, 0, 1, // 224: switch Inst[0] {
185 0, 15, // 227: case 0x0: {
186 OPC_SwitchField, 9, 2, // 229: switch Inst[10:9] {
187 0, 4, // 232: case 0x0: {
188 OPC_Decode, 169, 17, 3, // 234: decode to VADDUDM using decoder 3
189 // 234: }
190 2, 0, // 238: case 0x2: {
191 OPC_Decode, 137, 20, 3, // 240: decode to VSUBUDM using decoder 3
192 // 240: }
193 // 240: } // switch Inst[10:9]
194 // 240: }
195 1, 0, // 244: case 0x1: {
196 OPC_CheckField, 10, 1, 1, // 246: check Inst[10] == 0x1
197 OPC_Decode, 203, 4, 5, // 250: decode to BCDS_rec using decoder 5
198 // 250: }
199 // 250: } // switch Inst[0]
200 // 250: }
201 4, 57, // 254: case 0x4: {
202 OPC_SwitchField, 0, 1, // 256: switch Inst[0] {
203 0, 27, // 259: case 0x0: {
204 OPC_SwitchField, 9, 2, // 261: switch Inst[10:9] {
205 0, 4, // 264: case 0x0: {
206 OPC_Decode, 172, 17, 3, // 266: decode to VADDUQM using decoder 3
207 // 266: }
208 1, 4, // 270: case 0x1: {
209 OPC_Decode, 164, 17, 3, // 272: decode to VADDSBS using decoder 3
210 // 272: }
211 2, 4, // 276: case 0x2: {
212 OPC_Decode, 140, 20, 3, // 278: decode to VSUBUQM using decoder 3
213 // 278: }
214 3, 0, // 282: case 0x3: {
215 OPC_Decode, 132, 20, 3, // 284: decode to VSUBSBS using decoder 3
216 // 284: }
217 // 284: } // switch Inst[10:9]
218 // 284: }
219 1, 0, // 288: case 0x1: {
220 OPC_SwitchField, 10, 1, // 290: switch Inst[10] {
221 0, 12, // 293: case 0x0: {
222 OPC_CheckField, 21, 2, 0, // 295: check Inst[22:21] == 0x0
223 OPC_CheckField, 9, 1, 0, // 299: check Inst[9] == 0x0
224 OPC_Decode, 251, 17, 6, // 303: decode to VCMPUQ using decoder 6
225 // 303: }
226 1, 0, // 307: case 0x1: {
227 OPC_Decode, 204, 4, 5, // 309: decode to BCDTRUNC_rec using decoder 5
228 // 309: }
229 // 309: } // switch Inst[10]
230 // 309: }
231 // 309: } // switch Inst[0]
232 // 309: }
233 5, 68, // 313: case 0x5: {
234 OPC_SwitchField, 9, 2, // 315: switch Inst[10:9] {
235 0, 19, // 318: case 0x0: {
236 OPC_SwitchField, 0, 1, // 320: switch Inst[0] {
237 0, 4, // 323: case 0x0: {
238 OPC_Decode, 159, 17, 3, // 325: decode to VADDCUQ using decoder 3
239 // 325: }
240 1, 0, // 329: case 0x1: {
241 OPC_CheckField, 21, 2, 0, // 331: check Inst[22:21] == 0x0
242 OPC_Decode, 250, 17, 6, // 335: decode to VCMPSQ using decoder 6
243 // 335: }
244 // 335: } // switch Inst[0]
245 // 335: }
246 1, 15, // 339: case 0x1: {
247 OPC_SwitchField, 0, 1, // 341: switch Inst[0] {
248 0, 4, // 344: case 0x0: {
249 OPC_Decode, 165, 17, 3, // 346: decode to VADDSHS using decoder 3
250 // 346: }
251 1, 0, // 350: case 0x1: {
252 OPC_Decode, 196, 4, 3, // 352: decode to BCDCPSGN_rec using decoder 3
253 // 352: }
254 // 352: } // switch Inst[0]
255 // 352: }
256 2, 15, // 356: case 0x2: {
257 OPC_SwitchField, 0, 1, // 358: switch Inst[0] {
258 0, 4, // 361: case 0x0: {
259 OPC_Decode, 255, 19, 3, // 363: decode to VSUBCUQ using decoder 3
260 // 363: }
261 1, 0, // 367: case 0x1: {
262 OPC_Decode, 206, 4, 3, // 369: decode to BCDUTRUNC_rec using decoder 3
263 // 369: }
264 // 369: } // switch Inst[0]
265 // 369: }
266 3, 0, // 373: case 0x3: {
267 OPC_CheckField, 0, 1, 0, // 375: check Inst[0] == 0x0
268 OPC_Decode, 133, 20, 3, // 379: decode to VSUBSHS using decoder 3
269 // 379: }
270 // 379: } // switch Inst[10:9]
271 // 379: }
272 6, 107, // 383: case 0x6: {
273 OPC_SwitchField, 0, 1, // 385: switch Inst[0] {
274 0, 27, // 388: case 0x0: {
275 OPC_SwitchField, 9, 2, // 390: switch Inst[10:9] {
276 0, 4, // 393: case 0x0: {
277 OPC_Decode, 160, 17, 3, // 395: decode to VADDCUW using decoder 3
278 // 395: }
279 1, 4, // 399: case 0x1: {
280 OPC_Decode, 166, 17, 3, // 401: decode to VADDSWS using decoder 3
281 // 401: }
282 2, 4, // 405: case 0x2: {
283 OPC_Decode, 128, 20, 3, // 407: decode to VSUBCUW using decoder 3
284 // 407: }
285 3, 0, // 411: case 0x3: {
286 OPC_Decode, 134, 20, 3, // 413: decode to VSUBSWS using decoder 3
287 // 413: }
288 // 413: } // switch Inst[10:9]
289 // 413: }
290 1, 0, // 417: case 0x1: {
291 OPC_SwitchField, 16, 5, // 419: switch Inst[20:16] {
292 0, 8, // 422: case 0x0: {
293 OPC_CheckField, 9, 2, 2, // 424: check Inst[10:9] == 0x2
294 OPC_Decode, 198, 4, 7, // 428: decode to BCDCTSQ_rec using decoder 7
295 // 428: }
296 2, 8, // 432: case 0x2: {
297 OPC_CheckField, 10, 1, 1, // 434: check Inst[10] == 0x1
298 OPC_Decode, 194, 4, 8, // 438: decode to BCDCFSQ_rec using decoder 8
299 // 438: }
300 4, 8, // 442: case 0x4: {
301 OPC_CheckField, 10, 1, 1, // 444: check Inst[10] == 0x1
302 OPC_Decode, 199, 4, 8, // 448: decode to BCDCTZ_rec using decoder 8
303 // 448: }
304 5, 8, // 452: case 0x5: {
305 OPC_CheckField, 9, 2, 2, // 454: check Inst[10:9] == 0x2
306 OPC_Decode, 197, 4, 7, // 458: decode to BCDCTN_rec using decoder 7
307 // 458: }
308 6, 8, // 462: case 0x6: {
309 OPC_CheckField, 10, 1, 1, // 464: check Inst[10] == 0x1
310 OPC_Decode, 195, 4, 8, // 468: decode to BCDCFZ_rec using decoder 8
311 // 468: }
312 7, 8, // 472: case 0x7: {
313 OPC_CheckField, 10, 1, 1, // 474: check Inst[10] == 0x1
314 OPC_Decode, 193, 4, 8, // 478: decode to BCDCFN_rec using decoder 8
315 // 478: }
316 31, 0, // 482: case 0x1f: {
317 OPC_CheckField, 10, 1, 1, // 484: check Inst[10] == 0x1
318 OPC_Decode, 200, 4, 8, // 488: decode to BCDSETSGN_rec using decoder 8
319 // 488: }
320 // 488: } // switch Inst[20:16]
321 // 488: }
322 // 488: } // switch Inst[0]
323 // 488: }
324 7, 0, // 492: case 0x7: {
325 OPC_CheckField, 10, 1, 1, // 494: check Inst[10] == 0x1
326 OPC_CheckField, 0, 1, 1, // 498: check Inst[0] == 0x1
327 OPC_Decode, 201, 4, 5, // 502: decode to BCDSR_rec using decoder 5
328 // 502: }
329 // 502: } // switch Inst[8:6]
330 // 502: }
331 1, 237, 6, // 506: case 0x1: {
332 OPC_SwitchField, 6, 5, // 509: switch Inst[10:6] {
333 0, 15, // 512: case 0x0: {
334 OPC_SwitchField, 0, 1, // 514: switch Inst[0] {
335 0, 4, // 517: case 0x0: {
336 OPC_Decode, 220, 18, 3, // 519: decode to VMAXUB using decoder 3
337 // 519: }
338 1, 0, // 523: case 0x1: {
339 OPC_Decode, 150, 20, 3, // 525: decode to VUCMPRHN using decoder 3
340 // 525: }
341 // 525: } // switch Inst[0]
342 // 525: }
343 1, 15, // 529: case 0x1: {
344 OPC_SwitchField, 0, 1, // 531: switch Inst[0] {
345 0, 4, // 534: case 0x0: {
346 OPC_Decode, 222, 18, 3, // 536: decode to VMAXUH using decoder 3
347 // 536: }
348 1, 0, // 540: case 0x1: {
349 OPC_Decode, 153, 20, 3, // 542: decode to VUCMPRLN using decoder 3
350 // 542: }
351 // 542: } // switch Inst[0]
352 // 542: }
353 2, 15, // 546: case 0x2: {
354 OPC_SwitchField, 0, 1, // 548: switch Inst[0] {
355 0, 4, // 551: case 0x0: {
356 OPC_Decode, 223, 18, 3, // 553: decode to VMAXUW using decoder 3
357 // 553: }
358 1, 0, // 557: case 0x1: {
359 OPC_Decode, 148, 20, 3, // 559: decode to VUCMPRHB using decoder 3
360 // 559: }
361 // 559: } // switch Inst[0]
362 // 559: }
363 3, 15, // 563: case 0x3: {
364 OPC_SwitchField, 0, 1, // 565: switch Inst[0] {
365 0, 4, // 568: case 0x0: {
366 OPC_Decode, 221, 18, 3, // 570: decode to VMAXUD using decoder 3
367 // 570: }
368 1, 0, // 574: case 0x1: {
369 OPC_Decode, 151, 20, 3, // 576: decode to VUCMPRLB using decoder 3
370 // 576: }
371 // 576: } // switch Inst[0]
372 // 576: }
373 4, 15, // 580: case 0x4: {
374 OPC_SwitchField, 0, 1, // 582: switch Inst[0] {
375 0, 4, // 585: case 0x0: {
376 OPC_Decode, 216, 18, 3, // 587: decode to VMAXSB using decoder 3
377 // 587: }
378 1, 0, // 591: case 0x1: {
379 OPC_Decode, 149, 20, 3, // 593: decode to VUCMPRHH using decoder 3
380 // 593: }
381 // 593: } // switch Inst[0]
382 // 593: }
383 5, 15, // 597: case 0x5: {
384 OPC_SwitchField, 0, 1, // 599: switch Inst[0] {
385 0, 4, // 602: case 0x0: {
386 OPC_Decode, 218, 18, 3, // 604: decode to VMAXSH using decoder 3
387 // 604: }
388 1, 0, // 608: case 0x1: {
389 OPC_Decode, 152, 20, 3, // 610: decode to VUCMPRLH using decoder 3
390 // 610: }
391 // 610: } // switch Inst[0]
392 // 610: }
393 6, 65, // 614: case 0x6: {
394 OPC_SwitchField, 0, 1, // 616: switch Inst[0] {
395 0, 4, // 619: case 0x0: {
396 OPC_Decode, 219, 18, 3, // 621: decode to VMAXSW using decoder 3
397 // 621: }
398 1, 0, // 625: case 0x1: {
399 OPC_SwitchField, 19, 2, // 627: switch Inst[20:19] {
400 0, 26, // 630: case 0x0: {
401 OPC_SwitchField, 17, 2, // 632: switch Inst[18:17] {
402 0, 15, // 635: case 0x0: {
403 OPC_SwitchField, 16, 1, // 637: switch Inst[16] {
404 0, 4, // 640: case 0x0: {
405 OPC_Decode, 157, 20, 7, // 642: decode to VUPKHSNTOB using decoder 7
406 // 642: }
407 1, 0, // 646: case 0x1: {
408 OPC_Decode, 166, 20, 7, // 648: decode to VUPKLSNTOB using decoder 7
409 // 648: }
410 // 648: } // switch Inst[16]
411 // 648: }
412 1, 0, // 652: case 0x1: {
413 OPC_Decode, 161, 20, 9, // 654: decode to VUPKINT8TOBF16 using decoder 9
414 // 654: }
415 // 654: } // switch Inst[18:17]
416 // 654: }
417 1, 15, // 658: case 0x1: {
418 OPC_SwitchField, 18, 1, // 660: switch Inst[18] {
419 0, 4, // 663: case 0x0: {
420 OPC_Decode, 159, 20, 10, // 665: decode to VUPKINT4TOBF16 using decoder 10
421 // 665: }
422 1, 0, // 669: case 0x1: {
423 OPC_Decode, 162, 20, 10, // 671: decode to VUPKINT8TOFP32 using decoder 10
424 // 671: }
425 // 671: } // switch Inst[18]
426 // 671: }
427 2, 0, // 675: case 0x2: {
428 OPC_Decode, 160, 20, 11, // 677: decode to VUPKINT4TOFP32 using decoder 11
429 // 677: }
430 // 677: } // switch Inst[20:19]
431 // 677: }
432 // 677: } // switch Inst[0]
433 // 677: }
434 7, 8, // 681: case 0x7: {
435 OPC_CheckField, 0, 1, 0, // 683: check Inst[0] == 0x0
436 OPC_Decode, 217, 18, 3, // 687: decode to VMAXSD using decoder 3
437 // 687: }
438 8, 8, // 691: case 0x8: {
439 OPC_CheckField, 0, 1, 0, // 693: check Inst[0] == 0x0
440 OPC_Decode, 231, 18, 3, // 697: decode to VMINUB using decoder 3
441 // 697: }
442 9, 8, // 701: case 0x9: {
443 OPC_CheckField, 0, 1, 0, // 703: check Inst[0] == 0x0
444 OPC_Decode, 233, 18, 3, // 707: decode to VMINUH using decoder 3
445 // 707: }
446 10, 8, // 711: case 0xa: {
447 OPC_CheckField, 0, 1, 0, // 713: check Inst[0] == 0x0
448 OPC_Decode, 234, 18, 3, // 717: decode to VMINUW using decoder 3
449 // 717: }
450 11, 8, // 721: case 0xb: {
451 OPC_CheckField, 0, 1, 0, // 723: check Inst[0] == 0x0
452 OPC_Decode, 232, 18, 3, // 727: decode to VMINUD using decoder 3
453 // 727: }
454 12, 8, // 731: case 0xc: {
455 OPC_CheckField, 0, 1, 0, // 733: check Inst[0] == 0x0
456 OPC_Decode, 227, 18, 3, // 737: decode to VMINSB using decoder 3
457 // 737: }
458 13, 8, // 741: case 0xd: {
459 OPC_CheckField, 0, 1, 0, // 743: check Inst[0] == 0x0
460 OPC_Decode, 229, 18, 3, // 747: decode to VMINSH using decoder 3
461 // 747: }
462 14, 8, // 751: case 0xe: {
463 OPC_CheckField, 0, 1, 0, // 753: check Inst[0] == 0x0
464 OPC_Decode, 230, 18, 3, // 757: decode to VMINSW using decoder 3
465 // 757: }
466 15, 8, // 761: case 0xf: {
467 OPC_CheckField, 0, 1, 0, // 763: check Inst[0] == 0x0
468 OPC_Decode, 228, 18, 3, // 767: decode to VMINSD using decoder 3
469 // 767: }
470 16, 15, // 771: case 0x10: {
471 OPC_SwitchField, 0, 1, // 773: switch Inst[0] {
472 0, 4, // 776: case 0x0: {
473 OPC_Decode, 180, 17, 3, // 778: decode to VAVGUB using decoder 3
474 // 778: }
475 1, 0, // 782: case 0x1: {
476 OPC_Decode, 156, 17, 3, // 784: decode to VABSDUB using decoder 3
477 // 784: }
478 // 784: } // switch Inst[0]
479 // 784: }
480 17, 15, // 788: case 0x11: {
481 OPC_SwitchField, 0, 1, // 790: switch Inst[0] {
482 0, 4, // 793: case 0x0: {
483 OPC_Decode, 181, 17, 3, // 795: decode to VAVGUH using decoder 3
484 // 795: }
485 1, 0, // 799: case 0x1: {
486 OPC_Decode, 157, 17, 3, // 801: decode to VABSDUH using decoder 3
487 // 801: }
488 // 801: } // switch Inst[0]
489 // 801: }
490 18, 15, // 805: case 0x12: {
491 OPC_SwitchField, 0, 1, // 807: switch Inst[0] {
492 0, 4, // 810: case 0x0: {
493 OPC_Decode, 182, 17, 3, // 812: decode to VAVGUW using decoder 3
494 // 812: }
495 1, 0, // 816: case 0x1: {
496 OPC_Decode, 158, 17, 3, // 818: decode to VABSDUW using decoder 3
497 // 818: }
498 // 818: } // switch Inst[0]
499 // 818: }
500 20, 8, // 822: case 0x14: {
501 OPC_CheckField, 0, 1, 0, // 824: check Inst[0] == 0x0
502 OPC_Decode, 177, 17, 3, // 828: decode to VAVGSB using decoder 3
503 // 828: }
504 21, 8, // 832: case 0x15: {
505 OPC_CheckField, 0, 1, 0, // 834: check Inst[0] == 0x0
506 OPC_Decode, 178, 17, 3, // 838: decode to VAVGSH using decoder 3
507 // 838: }
508 22, 8, // 842: case 0x16: {
509 OPC_CheckField, 0, 1, 0, // 844: check Inst[0] == 0x0
510 OPC_Decode, 179, 17, 3, // 848: decode to VAVGSW using decoder 3
511 // 848: }
512 24, 173, 1, // 852: case 0x18: {
513 OPC_SwitchField, 16, 5, // 855: switch Inst[20:16] {
514 0, 8, // 858: case 0x0: {
515 OPC_CheckField, 0, 1, 0, // 860: check Inst[0] == 0x0
516 OPC_Decode, 198, 17, 12, // 864: decode to VCLZLSBB using decoder 12
517 // 864: }
518 1, 8, // 868: case 0x1: {
519 OPC_CheckField, 0, 1, 0, // 870: check Inst[0] == 0x0
520 OPC_Decode, 136, 18, 12, // 874: decode to VCTZLSBB using decoder 12
521 // 874: }
522 6, 8, // 878: case 0x6: {
523 OPC_CheckField, 0, 1, 0, // 880: check Inst[0] == 0x0
524 OPC_Decode, 160, 19, 7, // 884: decode to VNEGW using decoder 7
525 // 884: }
526 7, 8, // 888: case 0x7: {
527 OPC_CheckField, 0, 1, 0, // 890: check Inst[0] == 0x0
528 OPC_Decode, 159, 19, 7, // 894: decode to VNEGD using decoder 7
529 // 894: }
530 8, 8, // 898: case 0x8: {
531 OPC_CheckField, 0, 1, 0, // 900: check Inst[0] == 0x0
532 OPC_Decode, 193, 19, 7, // 904: decode to VPRTYBW using decoder 7
533 // 904: }
534 9, 8, // 908: case 0x9: {
535 OPC_CheckField, 0, 1, 0, // 910: check Inst[0] == 0x0
536 OPC_Decode, 191, 19, 7, // 914: decode to VPRTYBD using decoder 7
537 // 914: }
538 10, 8, // 918: case 0xa: {
539 OPC_CheckField, 0, 1, 0, // 920: check Inst[0] == 0x0
540 OPC_Decode, 192, 19, 7, // 924: decode to VPRTYBQ using decoder 7
541 // 924: }
542 16, 8, // 928: case 0x10: {
543 OPC_CheckField, 0, 1, 0, // 930: check Inst[0] == 0x0
544 OPC_Decode, 176, 18, 7, // 934: decode to VEXTSB2W using decoder 7
545 // 934: }
546 17, 8, // 938: case 0x11: {
547 OPC_CheckField, 0, 1, 0, // 940: check Inst[0] == 0x0
548 OPC_Decode, 181, 18, 7, // 944: decode to VEXTSH2W using decoder 7
549 // 944: }
550 24, 8, // 948: case 0x18: {
551 OPC_CheckField, 0, 1, 0, // 950: check Inst[0] == 0x0
552 OPC_Decode, 174, 18, 7, // 954: decode to VEXTSB2D using decoder 7
553 // 954: }
554 25, 8, // 958: case 0x19: {
555 OPC_CheckField, 0, 1, 0, // 960: check Inst[0] == 0x0
556 OPC_Decode, 179, 18, 7, // 964: decode to VEXTSH2D using decoder 7
557 // 964: }
558 26, 8, // 968: case 0x1a: {
559 OPC_CheckField, 0, 1, 0, // 970: check Inst[0] == 0x0
560 OPC_Decode, 183, 18, 7, // 974: decode to VEXTSW2D using decoder 7
561 // 974: }
562 27, 8, // 978: case 0x1b: {
563 OPC_CheckField, 0, 1, 0, // 980: check Inst[0] == 0x0
564 OPC_Decode, 178, 18, 7, // 984: decode to VEXTSD2Q using decoder 7
565 // 984: }
566 28, 8, // 988: case 0x1c: {
567 OPC_CheckField, 0, 1, 0, // 990: check Inst[0] == 0x0
568 OPC_Decode, 132, 18, 7, // 994: decode to VCTZB using decoder 7
569 // 994: }
570 29, 8, // 998: case 0x1d: {
571 OPC_CheckField, 0, 1, 0, // 1000: check Inst[0] == 0x0
572 OPC_Decode, 135, 18, 7, // 1004: decode to VCTZH using decoder 7
573 // 1004: }
574 30, 8, // 1008: case 0x1e: {
575 OPC_CheckField, 0, 1, 0, // 1010: check Inst[0] == 0x0
576 OPC_Decode, 137, 18, 7, // 1014: decode to VCTZW using decoder 7
577 // 1014: }
578 31, 0, // 1018: case 0x1f: {
579 OPC_CheckField, 0, 1, 0, // 1020: check Inst[0] == 0x0
580 OPC_Decode, 133, 18, 7, // 1024: decode to VCTZD using decoder 7
581 // 1024: }
582 // 1024: } // switch Inst[20:16]
583 // 1024: }
584 25, 235, 1, // 1028: case 0x19: {
585 OPC_SwitchField, 17, 4, // 1031: switch Inst[20:17] {
586 0, 23, // 1034: case 0x0: {
587 OPC_SwitchField, 16, 1, // 1036: switch Inst[16] {
588 0, 8, // 1039: case 0x0: {
589 OPC_CheckField, 0, 1, 0, // 1041: check Inst[0] == 0x0
590 OPC_Decode, 151, 18, 7, // 1045: decode to VEXPANDBM using decoder 7
591 // 1045: }
592 1, 0, // 1049: case 0x1: {
593 OPC_CheckField, 0, 1, 0, // 1051: check Inst[0] == 0x0
594 OPC_Decode, 153, 18, 7, // 1055: decode to VEXPANDHM using decoder 7
595 // 1055: }
596 // 1055: } // switch Inst[16]
597 // 1055: }
598 1, 23, // 1059: case 0x1: {
599 OPC_SwitchField, 16, 1, // 1061: switch Inst[16] {
600 0, 8, // 1064: case 0x0: {
601 OPC_CheckField, 0, 1, 0, // 1066: check Inst[0] == 0x0
602 OPC_Decode, 155, 18, 7, // 1070: decode to VEXPANDWM using decoder 7
603 // 1070: }
604 1, 0, // 1074: case 0x1: {
605 OPC_CheckField, 0, 1, 0, // 1076: check Inst[0] == 0x0
606 OPC_Decode, 152, 18, 7, // 1080: decode to VEXPANDDM using decoder 7
607 // 1080: }
608 // 1080: } // switch Inst[16]
609 // 1080: }
610 2, 12, // 1084: case 0x2: {
611 OPC_CheckField, 16, 1, 0, // 1086: check Inst[16] == 0x0
612 OPC_CheckField, 0, 1, 0, // 1090: check Inst[0] == 0x0
613 OPC_Decode, 154, 18, 7, // 1094: decode to VEXPANDQM using decoder 7
614 // 1094: }
615 4, 23, // 1098: case 0x4: {
616 OPC_SwitchField, 16, 1, // 1100: switch Inst[16] {
617 0, 8, // 1103: case 0x0: {
618 OPC_CheckField, 0, 1, 0, // 1105: check Inst[0] == 0x0
619 OPC_Decode, 165, 18, 12, // 1109: decode to VEXTRACTBM using decoder 12
620 // 1109: }
621 1, 0, // 1113: case 0x1: {
622 OPC_CheckField, 0, 1, 0, // 1115: check Inst[0] == 0x0
623 OPC_Decode, 168, 18, 12, // 1119: decode to VEXTRACTHM using decoder 12
624 // 1119: }
625 // 1119: } // switch Inst[16]
626 // 1119: }
627 5, 23, // 1123: case 0x5: {
628 OPC_SwitchField, 16, 1, // 1125: switch Inst[16] {
629 0, 8, // 1128: case 0x0: {
630 OPC_CheckField, 0, 1, 0, // 1130: check Inst[0] == 0x0
631 OPC_Decode, 173, 18, 12, // 1134: decode to VEXTRACTWM using decoder 12
632 // 1134: }
633 1, 0, // 1138: case 0x1: {
634 OPC_CheckField, 0, 1, 0, // 1140: check Inst[0] == 0x0
635 OPC_Decode, 167, 18, 12, // 1144: decode to VEXTRACTDM using decoder 12
636 // 1144: }
637 // 1144: } // switch Inst[16]
638 // 1144: }
639 6, 12, // 1148: case 0x6: {
640 OPC_CheckField, 16, 1, 0, // 1150: check Inst[16] == 0x0
641 OPC_CheckField, 0, 1, 0, // 1154: check Inst[0] == 0x0
642 OPC_Decode, 169, 18, 12, // 1158: decode to VEXTRACTQM using decoder 12
643 // 1158: }
644 8, 23, // 1162: case 0x8: {
645 OPC_SwitchField, 16, 1, // 1164: switch Inst[16] {
646 0, 8, // 1167: case 0x0: {
647 OPC_CheckField, 0, 1, 0, // 1169: check Inst[0] == 0x0
648 OPC_Decode, 171, 12, 13, // 1173: decode to MTVSRBM using decoder 13
649 // 1173: }
650 1, 0, // 1177: case 0x1: {
651 OPC_CheckField, 0, 1, 0, // 1179: check Inst[0] == 0x0
652 OPC_Decode, 176, 12, 13, // 1183: decode to MTVSRHM using decoder 13
653 // 1183: }
654 // 1183: } // switch Inst[16]
655 // 1183: }
656 9, 23, // 1187: case 0x9: {
657 OPC_SwitchField, 16, 1, // 1189: switch Inst[16] {
658 0, 8, // 1192: case 0x0: {
659 OPC_CheckField, 0, 1, 0, // 1194: check Inst[0] == 0x0
660 OPC_Decode, 179, 12, 13, // 1198: decode to MTVSRWM using decoder 13
661 // 1198: }
662 1, 0, // 1202: case 0x1: {
663 OPC_CheckField, 0, 1, 0, // 1204: check Inst[0] == 0x0
664 OPC_Decode, 175, 12, 13, // 1208: decode to MTVSRDM using decoder 13
665 // 1208: }
666 // 1208: } // switch Inst[16]
667 // 1208: }
668 10, 12, // 1212: case 0xa: {
669 OPC_CheckField, 16, 1, 0, // 1214: check Inst[16] == 0x0
670 OPC_CheckField, 0, 1, 0, // 1218: check Inst[0] == 0x0
671 OPC_Decode, 177, 12, 13, // 1222: decode to MTVSRQM using decoder 13
672 // 1222: }
673 12, 8, // 1226: case 0xc: {
674 OPC_CheckField, 0, 1, 0, // 1228: check Inst[0] == 0x0
675 OPC_Decode, 252, 17, 14, // 1232: decode to VCNTMBB using decoder 14
676 // 1232: }
677 13, 8, // 1236: case 0xd: {
678 OPC_CheckField, 0, 1, 0, // 1238: check Inst[0] == 0x0
679 OPC_Decode, 254, 17, 14, // 1242: decode to VCNTMBH using decoder 14
680 // 1242: }
681 14, 8, // 1246: case 0xe: {
682 OPC_CheckField, 0, 1, 0, // 1248: check Inst[0] == 0x0
683 OPC_Decode, 255, 17, 14, // 1252: decode to VCNTMBW using decoder 14
684 // 1252: }
685 15, 0, // 1256: case 0xf: {
686 OPC_CheckField, 0, 1, 0, // 1258: check Inst[0] == 0x0
687 OPC_Decode, 253, 17, 14, // 1262: decode to VCNTMBD using decoder 14
688 // 1262: }
689 // 1262: } // switch Inst[20:17]
690 // 1262: }
691 26, 8, // 1266: case 0x1a: {
692 OPC_CheckField, 0, 1, 0, // 1268: check Inst[0] == 0x0
693 OPC_Decode, 214, 19, 15, // 1272: decode to VSHASIGMAW using decoder 15
694 // 1272: }
695 27, 8, // 1276: case 0x1b: {
696 OPC_CheckField, 0, 1, 0, // 1278: check Inst[0] == 0x0
697 OPC_Decode, 213, 19, 15, // 1282: decode to VSHASIGMAD using decoder 15
698 // 1282: }
699 28, 23, // 1286: case 0x1c: {
700 OPC_SwitchField, 0, 1, // 1288: switch Inst[0] {
701 0, 8, // 1291: case 0x0: {
702 OPC_CheckField, 16, 5, 0, // 1293: check Inst[20:16] == 0x0
703 OPC_Decode, 194, 17, 7, // 1297: decode to VCLZB using decoder 7
704 // 1297: }
705 1, 0, // 1301: case 0x1: {
706 OPC_CheckField, 16, 5, 0, // 1303: check Inst[20:16] == 0x0
707 OPC_Decode, 187, 19, 7, // 1307: decode to VPOPCNTB using decoder 7
708 // 1307: }
709 // 1307: } // switch Inst[0]
710 // 1307: }
711 29, 23, // 1311: case 0x1d: {
712 OPC_SwitchField, 0, 1, // 1313: switch Inst[0] {
713 0, 8, // 1316: case 0x0: {
714 OPC_CheckField, 16, 5, 0, // 1318: check Inst[20:16] == 0x0
715 OPC_Decode, 197, 17, 7, // 1322: decode to VCLZH using decoder 7
716 // 1322: }
717 1, 0, // 1326: case 0x1: {
718 OPC_CheckField, 16, 5, 0, // 1328: check Inst[20:16] == 0x0
719 OPC_Decode, 189, 19, 7, // 1332: decode to VPOPCNTH using decoder 7
720 // 1332: }
721 // 1332: } // switch Inst[0]
722 // 1332: }
723 30, 23, // 1336: case 0x1e: {
724 OPC_SwitchField, 0, 1, // 1338: switch Inst[0] {
725 0, 8, // 1341: case 0x0: {
726 OPC_CheckField, 16, 5, 0, // 1343: check Inst[20:16] == 0x0
727 OPC_Decode, 199, 17, 7, // 1347: decode to VCLZW using decoder 7
728 // 1347: }
729 1, 0, // 1351: case 0x1: {
730 OPC_CheckField, 16, 5, 0, // 1353: check Inst[20:16] == 0x0
731 OPC_Decode, 190, 19, 7, // 1357: decode to VPOPCNTW using decoder 7
732 // 1357: }
733 // 1357: } // switch Inst[0]
734 // 1357: }
735 31, 0, // 1361: case 0x1f: {
736 OPC_SwitchField, 0, 1, // 1363: switch Inst[0] {
737 0, 8, // 1366: case 0x0: {
738 OPC_CheckField, 16, 5, 0, // 1368: check Inst[20:16] == 0x0
739 OPC_Decode, 195, 17, 7, // 1372: decode to VCLZD using decoder 7
740 // 1372: }
741 1, 0, // 1376: case 0x1: {
742 OPC_CheckField, 16, 5, 0, // 1378: check Inst[20:16] == 0x0
743 OPC_Decode, 188, 19, 7, // 1382: decode to VPOPCNTD using decoder 7
744 // 1382: }
745 // 1382: } // switch Inst[0]
746 // 1382: }
747 // 1382: } // switch Inst[10:6]
748 // 1382: }
749 2, 145, 3, // 1386: case 0x2: {
750 OPC_SwitchField, 6, 5, // 1389: switch Inst[10:6] {
751 0, 15, // 1392: case 0x0: {
752 OPC_SwitchField, 0, 1, // 1394: switch Inst[0] {
753 0, 4, // 1397: case 0x0: {
754 OPC_Decode, 199, 19, 3, // 1399: decode to VRLB using decoder 3
755 // 1399: }
756 1, 0, // 1403: case 0x1: {
757 OPC_Decode, 204, 19, 3, // 1405: decode to VRLQ using decoder 3
758 // 1405: }
759 // 1405: } // switch Inst[0]
760 // 1405: }
761 1, 15, // 1409: case 0x1: {
762 OPC_SwitchField, 0, 1, // 1411: switch Inst[0] {
763 0, 4, // 1414: case 0x0: {
764 OPC_Decode, 203, 19, 3, // 1416: decode to VRLH using decoder 3
765 // 1416: }
766 1, 0, // 1420: case 0x1: {
767 OPC_Decode, 205, 19, 16, // 1422: decode to VRLQMI using decoder 16
768 // 1422: }
769 // 1422: } // switch Inst[0]
770 // 1422: }
771 2, 15, // 1426: case 0x2: {
772 OPC_SwitchField, 0, 1, // 1428: switch Inst[0] {
773 0, 4, // 1431: case 0x0: {
774 OPC_Decode, 207, 19, 3, // 1433: decode to VRLW using decoder 3
775 // 1433: }
776 1, 0, // 1437: case 0x1: {
777 OPC_Decode, 208, 19, 16, // 1439: decode to VRLWMI using decoder 16
778 // 1439: }
779 // 1439: } // switch Inst[0]
780 // 1439: }
781 3, 15, // 1443: case 0x3: {
782 OPC_SwitchField, 0, 1, // 1445: switch Inst[0] {
783 0, 4, // 1448: case 0x0: {
784 OPC_Decode, 200, 19, 3, // 1450: decode to VRLD using decoder 3
785 // 1450: }
786 1, 0, // 1454: case 0x1: {
787 OPC_Decode, 201, 19, 16, // 1456: decode to VRLDMI using decoder 16
788 // 1456: }
789 // 1456: } // switch Inst[0]
790 // 1456: }
791 4, 15, // 1460: case 0x4: {
792 OPC_SwitchField, 0, 1, // 1462: switch Inst[0] {
793 0, 4, // 1465: case 0x0: {
794 OPC_Decode, 216, 19, 3, // 1467: decode to VSLB using decoder 3
795 // 1467: }
796 1, 0, // 1471: case 0x1: {
797 OPC_Decode, 222, 19, 3, // 1473: decode to VSLQ using decoder 3
798 // 1473: }
799 // 1473: } // switch Inst[0]
800 // 1473: }
801 5, 15, // 1477: case 0x5: {
802 OPC_SwitchField, 0, 1, // 1479: switch Inst[0] {
803 0, 4, // 1482: case 0x0: {
804 OPC_Decode, 220, 19, 3, // 1484: decode to VSLH using decoder 3
805 // 1484: }
806 1, 0, // 1488: case 0x1: {
807 OPC_Decode, 206, 19, 3, // 1490: decode to VRLQNM using decoder 3
808 // 1490: }
809 // 1490: } // switch Inst[0]
810 // 1490: }
811 6, 15, // 1494: case 0x6: {
812 OPC_SwitchField, 0, 1, // 1496: switch Inst[0] {
813 0, 4, // 1499: case 0x0: {
814 OPC_Decode, 224, 19, 3, // 1501: decode to VSLW using decoder 3
815 // 1501: }
816 1, 0, // 1505: case 0x1: {
817 OPC_Decode, 209, 19, 3, // 1507: decode to VRLWNM using decoder 3
818 // 1507: }
819 // 1507: } // switch Inst[0]
820 // 1507: }
821 7, 15, // 1511: case 0x7: {
822 OPC_SwitchField, 0, 1, // 1513: switch Inst[0] {
823 0, 4, // 1516: case 0x0: {
824 OPC_Decode, 215, 19, 3, // 1518: decode to VSL using decoder 3
825 // 1518: }
826 1, 0, // 1522: case 0x1: {
827 OPC_Decode, 202, 19, 3, // 1524: decode to VRLDNM using decoder 3
828 // 1524: }
829 // 1524: } // switch Inst[0]
830 // 1524: }
831 8, 15, // 1528: case 0x8: {
832 OPC_SwitchField, 0, 1, // 1530: switch Inst[0] {
833 0, 4, // 1533: case 0x0: {
834 OPC_Decode, 239, 19, 3, // 1535: decode to VSRB using decoder 3
835 // 1535: }
836 1, 0, // 1539: case 0x1: {
837 OPC_Decode, 244, 19, 3, // 1541: decode to VSRQ using decoder 3
838 // 1541: }
839 // 1541: } // switch Inst[0]
840 // 1541: }
841 9, 8, // 1545: case 0x9: {
842 OPC_CheckField, 0, 1, 0, // 1547: check Inst[0] == 0x0
843 OPC_Decode, 242, 19, 3, // 1551: decode to VSRH using decoder 3
844 // 1551: }
845 10, 8, // 1555: case 0xa: {
846 OPC_CheckField, 0, 1, 0, // 1557: check Inst[0] == 0x0
847 OPC_Decode, 246, 19, 3, // 1561: decode to VSRW using decoder 3
848 // 1561: }
849 11, 8, // 1565: case 0xb: {
850 OPC_CheckField, 0, 1, 0, // 1567: check Inst[0] == 0x0
851 OPC_Decode, 233, 19, 3, // 1571: decode to VSR using decoder 3
852 // 1571: }
853 12, 15, // 1575: case 0xc: {
854 OPC_SwitchField, 0, 1, // 1577: switch Inst[0] {
855 0, 4, // 1580: case 0x0: {
856 OPC_Decode, 234, 19, 3, // 1582: decode to VSRAB using decoder 3
857 // 1582: }
858 1, 0, // 1586: case 0x1: {
859 OPC_Decode, 237, 19, 3, // 1588: decode to VSRAQ using decoder 3
860 // 1588: }
861 // 1588: } // switch Inst[0]
862 // 1588: }
863 13, 8, // 1592: case 0xd: {
864 OPC_CheckField, 0, 1, 0, // 1594: check Inst[0] == 0x0
865 OPC_Decode, 236, 19, 3, // 1598: decode to VSRAH using decoder 3
866 // 1598: }
867 14, 8, // 1602: case 0xe: {
868 OPC_CheckField, 0, 1, 0, // 1604: check Inst[0] == 0x0
869 OPC_Decode, 238, 19, 3, // 1608: decode to VSRAW using decoder 3
870 // 1608: }
871 15, 8, // 1612: case 0xf: {
872 OPC_CheckField, 0, 1, 0, // 1614: check Inst[0] == 0x0
873 OPC_Decode, 235, 19, 3, // 1618: decode to VSRAD using decoder 3
874 // 1618: }
875 16, 8, // 1622: case 0x10: {
876 OPC_CheckField, 0, 1, 0, // 1624: check Inst[0] == 0x0
877 OPC_Decode, 175, 17, 3, // 1628: decode to VAND using decoder 3
878 // 1628: }
879 17, 8, // 1632: case 0x11: {
880 OPC_CheckField, 0, 1, 0, // 1634: check Inst[0] == 0x0
881 OPC_Decode, 176, 17, 3, // 1638: decode to VANDC using decoder 3
882 // 1638: }
883 18, 8, // 1642: case 0x12: {
884 OPC_CheckField, 0, 1, 0, // 1644: check Inst[0] == 0x0
885 OPC_Decode, 163, 19, 3, // 1648: decode to VOR using decoder 3
886 // 1648: }
887 19, 8, // 1652: case 0x13: {
888 OPC_CheckField, 0, 1, 0, // 1654: check Inst[0] == 0x0
889 OPC_Decode, 168, 20, 3, // 1658: decode to VXOR using decoder 3
890 // 1658: }
891 20, 8, // 1662: case 0x14: {
892 OPC_CheckField, 0, 1, 0, // 1664: check Inst[0] == 0x0
893 OPC_Decode, 162, 19, 3, // 1668: decode to VNOR using decoder 3
894 // 1668: }
895 21, 8, // 1672: case 0x15: {
896 OPC_CheckField, 0, 1, 0, // 1674: check Inst[0] == 0x0
897 OPC_Decode, 164, 19, 3, // 1678: decode to VORC using decoder 3
898 // 1678: }
899 22, 8, // 1682: case 0x16: {
900 OPC_CheckField, 0, 1, 0, // 1684: check Inst[0] == 0x0
901 OPC_Decode, 156, 19, 3, // 1688: decode to VNAND using decoder 3
902 // 1688: }
903 23, 8, // 1692: case 0x17: {
904 OPC_CheckField, 0, 1, 0, // 1694: check Inst[0] == 0x0
905 OPC_Decode, 217, 19, 3, // 1698: decode to VSLD using decoder 3
906 // 1698: }
907 24, 12, // 1702: case 0x18: {
908 OPC_CheckField, 11, 10, 0, // 1704: check Inst[20:11] == 0x0
909 OPC_CheckField, 0, 1, 0, // 1708: check Inst[0] == 0x0
910 OPC_Decode, 252, 11, 17, // 1712: decode to MFVSCR using decoder 17
911 // 1712: }
912 25, 12, // 1716: case 0x19: {
913 OPC_CheckField, 16, 10, 0, // 1718: check Inst[25:16] == 0x0
914 OPC_CheckField, 0, 1, 0, // 1722: check Inst[0] == 0x0
915 OPC_Decode, 170, 12, 18, // 1726: decode to MTVSCR using decoder 18
916 // 1726: }
917 26, 8, // 1730: case 0x1a: {
918 OPC_CheckField, 0, 1, 0, // 1732: check Inst[0] == 0x0
919 OPC_Decode, 150, 18, 3, // 1736: decode to VEQV using decoder 3
920 // 1736: }
921 27, 8, // 1740: case 0x1b: {
922 OPC_CheckField, 0, 1, 0, // 1742: check Inst[0] == 0x0
923 OPC_Decode, 240, 19, 3, // 1746: decode to VSRD using decoder 3
924 // 1746: }
925 28, 8, // 1750: case 0x1c: {
926 OPC_CheckField, 0, 1, 0, // 1752: check Inst[0] == 0x0
927 OPC_Decode, 245, 19, 3, // 1756: decode to VSRV using decoder 3
928 // 1756: }
929 29, 8, // 1760: case 0x1d: {
930 OPC_CheckField, 0, 1, 0, // 1762: check Inst[0] == 0x0
931 OPC_Decode, 223, 19, 3, // 1766: decode to VSLV using decoder 3
932 // 1766: }
933 30, 8, // 1770: case 0x1e: {
934 OPC_CheckField, 0, 1, 0, // 1772: check Inst[0] == 0x0
935 OPC_Decode, 196, 17, 3, // 1776: decode to VCLZDM using decoder 3
936 // 1776: }
937 31, 0, // 1780: case 0x1f: {
938 OPC_CheckField, 0, 1, 0, // 1782: check Inst[0] == 0x0
939 OPC_Decode, 134, 18, 3, // 1786: decode to VCTZDM using decoder 3
940 // 1786: }
941 // 1786: } // switch Inst[10:6]
942 // 1786: }
943 3, 193, 3, // 1790: case 0x3: {
944 OPC_SwitchField, 6, 5, // 1793: switch Inst[10:6] {
945 0, 15, // 1796: case 0x0: {
946 OPC_SwitchField, 0, 1, // 1798: switch Inst[0] {
947 0, 4, // 1801: case 0x0: {
948 OPC_Decode, 204, 17, 3, // 1803: decode to VCMPEQUB using decoder 3
949 // 1803: }
950 1, 0, // 1807: case 0x1: {
951 OPC_Decode, 238, 17, 3, // 1809: decode to VCMPNEB using decoder 3
952 // 1809: }
953 // 1809: } // switch Inst[0]
954 // 1809: }
955 1, 15, // 1813: case 0x1: {
956 OPC_SwitchField, 0, 1, // 1815: switch Inst[0] {
957 0, 4, // 1818: case 0x0: {
958 OPC_Decode, 208, 17, 3, // 1820: decode to VCMPEQUH using decoder 3
959 // 1820: }
960 1, 0, // 1824: case 0x1: {
961 OPC_Decode, 240, 17, 3, // 1826: decode to VCMPNEH using decoder 3
962 // 1826: }
963 // 1826: } // switch Inst[0]
964 // 1826: }
965 2, 15, // 1830: case 0x2: {
966 OPC_SwitchField, 0, 1, // 1832: switch Inst[0] {
967 0, 4, // 1835: case 0x0: {
968 OPC_Decode, 212, 17, 3, // 1837: decode to VCMPEQUW using decoder 3
969 // 1837: }
970 1, 0, // 1841: case 0x1: {
971 OPC_Decode, 242, 17, 3, // 1843: decode to VCMPNEW using decoder 3
972 // 1843: }
973 // 1843: } // switch Inst[0]
974 // 1843: }
975 3, 15, // 1847: case 0x3: {
976 OPC_SwitchField, 0, 1, // 1849: switch Inst[0] {
977 0, 4, // 1852: case 0x0: {
978 OPC_Decode, 202, 17, 3, // 1854: decode to VCMPEQFP using decoder 3
979 // 1854: }
980 1, 0, // 1858: case 0x1: {
981 OPC_Decode, 206, 17, 3, // 1860: decode to VCMPEQUD using decoder 3
982 // 1860: }
983 // 1860: } // switch Inst[0]
984 // 1860: }
985 4, 8, // 1864: case 0x4: {
986 OPC_CheckField, 0, 1, 1, // 1866: check Inst[0] == 0x1
987 OPC_Decode, 244, 17, 3, // 1870: decode to VCMPNEZB using decoder 3
988 // 1870: }
989 5, 8, // 1874: case 0x5: {
990 OPC_CheckField, 0, 1, 1, // 1876: check Inst[0] == 0x1
991 OPC_Decode, 246, 17, 3, // 1880: decode to VCMPNEZH using decoder 3
992 // 1880: }
993 6, 8, // 1884: case 0x6: {
994 OPC_CheckField, 0, 1, 1, // 1886: check Inst[0] == 0x1
995 OPC_Decode, 248, 17, 3, // 1890: decode to VCMPNEZW using decoder 3
996 // 1890: }
997 7, 15, // 1894: case 0x7: {
998 OPC_SwitchField, 0, 1, // 1896: switch Inst[0] {
999 0, 4, // 1899: case 0x0: {
1000 OPC_Decode, 214, 17, 3, // 1901: decode to VCMPGEFP using decoder 3
1001 // 1901: }
1002 1, 0, // 1905: case 0x1: {
1003 OPC_Decode, 210, 17, 3, // 1907: decode to VCMPEQUQ using decoder 3
1004 // 1907: }
1005 // 1907: } // switch Inst[0]
1006 // 1907: }
1007 8, 8, // 1911: case 0x8: {
1008 OPC_CheckField, 0, 1, 0, // 1913: check Inst[0] == 0x0
1009 OPC_Decode, 228, 17, 3, // 1917: decode to VCMPGTUB using decoder 3
1010 // 1917: }
1011 9, 8, // 1921: case 0x9: {
1012 OPC_CheckField, 0, 1, 0, // 1923: check Inst[0] == 0x0
1013 OPC_Decode, 232, 17, 3, // 1927: decode to VCMPGTUH using decoder 3
1014 // 1927: }
1015 10, 15, // 1931: case 0xa: {
1016 OPC_SwitchField, 0, 1, // 1933: switch Inst[0] {
1017 0, 4, // 1936: case 0x0: {
1018 OPC_Decode, 236, 17, 3, // 1938: decode to VCMPGTUW using decoder 3
1019 // 1938: }
1020 1, 0, // 1942: case 0x1: {
1021 OPC_Decode, 234, 17, 3, // 1944: decode to VCMPGTUQ using decoder 3
1022 // 1944: }
1023 // 1944: } // switch Inst[0]
1024 // 1944: }
1025 11, 15, // 1948: case 0xb: {
1026 OPC_SwitchField, 0, 1, // 1950: switch Inst[0] {
1027 0, 4, // 1953: case 0x0: {
1028 OPC_Decode, 216, 17, 3, // 1955: decode to VCMPGTFP using decoder 3
1029 // 1955: }
1030 1, 0, // 1959: case 0x1: {
1031 OPC_Decode, 230, 17, 3, // 1961: decode to VCMPGTUD using decoder 3
1032 // 1961: }
1033 // 1961: } // switch Inst[0]
1034 // 1961: }
1035 12, 8, // 1965: case 0xc: {
1036 OPC_CheckField, 0, 1, 0, // 1967: check Inst[0] == 0x0
1037 OPC_Decode, 218, 17, 3, // 1971: decode to VCMPGTSB using decoder 3
1038 // 1971: }
1039 13, 8, // 1975: case 0xd: {
1040 OPC_CheckField, 0, 1, 0, // 1977: check Inst[0] == 0x0
1041 OPC_Decode, 222, 17, 3, // 1981: decode to VCMPGTSH using decoder 3
1042 // 1981: }
1043 14, 15, // 1985: case 0xe: {
1044 OPC_SwitchField, 0, 1, // 1987: switch Inst[0] {
1045 0, 4, // 1990: case 0x0: {
1046 OPC_Decode, 226, 17, 3, // 1992: decode to VCMPGTSW using decoder 3
1047 // 1992: }
1048 1, 0, // 1996: case 0x1: {
1049 OPC_Decode, 224, 17, 3, // 1998: decode to VCMPGTSQ using decoder 3
1050 // 1998: }
1051 // 1998: } // switch Inst[0]
1052 // 1998: }
1053 15, 15, // 2002: case 0xf: {
1054 OPC_SwitchField, 0, 1, // 2004: switch Inst[0] {
1055 0, 4, // 2007: case 0x0: {
1056 OPC_Decode, 200, 17, 3, // 2009: decode to VCMPBFP using decoder 3
1057 // 2009: }
1058 1, 0, // 2013: case 0x1: {
1059 OPC_Decode, 220, 17, 3, // 2015: decode to VCMPGTSD using decoder 3
1060 // 2015: }
1061 // 2015: } // switch Inst[0]
1062 // 2015: }
1063 16, 15, // 2019: case 0x10: {
1064 OPC_SwitchField, 0, 1, // 2021: switch Inst[0] {
1065 0, 4, // 2024: case 0x0: {
1066 OPC_Decode, 205, 17, 3, // 2026: decode to VCMPEQUB_rec using decoder 3
1067 // 2026: }
1068 1, 0, // 2030: case 0x1: {
1069 OPC_Decode, 239, 17, 3, // 2032: decode to VCMPNEB_rec using decoder 3
1070 // 2032: }
1071 // 2032: } // switch Inst[0]
1072 // 2032: }
1073 17, 15, // 2036: case 0x11: {
1074 OPC_SwitchField, 0, 1, // 2038: switch Inst[0] {
1075 0, 4, // 2041: case 0x0: {
1076 OPC_Decode, 209, 17, 3, // 2043: decode to VCMPEQUH_rec using decoder 3
1077 // 2043: }
1078 1, 0, // 2047: case 0x1: {
1079 OPC_Decode, 241, 17, 3, // 2049: decode to VCMPNEH_rec using decoder 3
1080 // 2049: }
1081 // 2049: } // switch Inst[0]
1082 // 2049: }
1083 18, 15, // 2053: case 0x12: {
1084 OPC_SwitchField, 0, 1, // 2055: switch Inst[0] {
1085 0, 4, // 2058: case 0x0: {
1086 OPC_Decode, 213, 17, 3, // 2060: decode to VCMPEQUW_rec using decoder 3
1087 // 2060: }
1088 1, 0, // 2064: case 0x1: {
1089 OPC_Decode, 243, 17, 3, // 2066: decode to VCMPNEW_rec using decoder 3
1090 // 2066: }
1091 // 2066: } // switch Inst[0]
1092 // 2066: }
1093 19, 15, // 2070: case 0x13: {
1094 OPC_SwitchField, 0, 1, // 2072: switch Inst[0] {
1095 0, 4, // 2075: case 0x0: {
1096 OPC_Decode, 203, 17, 3, // 2077: decode to VCMPEQFP_rec using decoder 3
1097 // 2077: }
1098 1, 0, // 2081: case 0x1: {
1099 OPC_Decode, 207, 17, 3, // 2083: decode to VCMPEQUD_rec using decoder 3
1100 // 2083: }
1101 // 2083: } // switch Inst[0]
1102 // 2083: }
1103 20, 8, // 2087: case 0x14: {
1104 OPC_CheckField, 0, 1, 1, // 2089: check Inst[0] == 0x1
1105 OPC_Decode, 245, 17, 3, // 2093: decode to VCMPNEZB_rec using decoder 3
1106 // 2093: }
1107 21, 8, // 2097: case 0x15: {
1108 OPC_CheckField, 0, 1, 1, // 2099: check Inst[0] == 0x1
1109 OPC_Decode, 247, 17, 3, // 2103: decode to VCMPNEZH_rec using decoder 3
1110 // 2103: }
1111 22, 8, // 2107: case 0x16: {
1112 OPC_CheckField, 0, 1, 1, // 2109: check Inst[0] == 0x1
1113 OPC_Decode, 249, 17, 3, // 2113: decode to VCMPNEZW_rec using decoder 3
1114 // 2113: }
1115 23, 15, // 2117: case 0x17: {
1116 OPC_SwitchField, 0, 1, // 2119: switch Inst[0] {
1117 0, 4, // 2122: case 0x0: {
1118 OPC_Decode, 215, 17, 3, // 2124: decode to VCMPGEFP_rec using decoder 3
1119 // 2124: }
1120 1, 0, // 2128: case 0x1: {
1121 OPC_Decode, 211, 17, 3, // 2130: decode to VCMPEQUQ_rec using decoder 3
1122 // 2130: }
1123 // 2130: } // switch Inst[0]
1124 // 2130: }
1125 24, 8, // 2134: case 0x18: {
1126 OPC_CheckField, 0, 1, 0, // 2136: check Inst[0] == 0x0
1127 OPC_Decode, 229, 17, 3, // 2140: decode to VCMPGTUB_rec using decoder 3
1128 // 2140: }
1129 25, 8, // 2144: case 0x19: {
1130 OPC_CheckField, 0, 1, 0, // 2146: check Inst[0] == 0x0
1131 OPC_Decode, 233, 17, 3, // 2150: decode to VCMPGTUH_rec using decoder 3
1132 // 2150: }
1133 26, 15, // 2154: case 0x1a: {
1134 OPC_SwitchField, 0, 1, // 2156: switch Inst[0] {
1135 0, 4, // 2159: case 0x0: {
1136 OPC_Decode, 237, 17, 3, // 2161: decode to VCMPGTUW_rec using decoder 3
1137 // 2161: }
1138 1, 0, // 2165: case 0x1: {
1139 OPC_Decode, 235, 17, 3, // 2167: decode to VCMPGTUQ_rec using decoder 3
1140 // 2167: }
1141 // 2167: } // switch Inst[0]
1142 // 2167: }
1143 27, 15, // 2171: case 0x1b: {
1144 OPC_SwitchField, 0, 1, // 2173: switch Inst[0] {
1145 0, 4, // 2176: case 0x0: {
1146 OPC_Decode, 217, 17, 3, // 2178: decode to VCMPGTFP_rec using decoder 3
1147 // 2178: }
1148 1, 0, // 2182: case 0x1: {
1149 OPC_Decode, 231, 17, 3, // 2184: decode to VCMPGTUD_rec using decoder 3
1150 // 2184: }
1151 // 2184: } // switch Inst[0]
1152 // 2184: }
1153 28, 8, // 2188: case 0x1c: {
1154 OPC_CheckField, 0, 1, 0, // 2190: check Inst[0] == 0x0
1155 OPC_Decode, 219, 17, 3, // 2194: decode to VCMPGTSB_rec using decoder 3
1156 // 2194: }
1157 29, 8, // 2198: case 0x1d: {
1158 OPC_CheckField, 0, 1, 0, // 2200: check Inst[0] == 0x0
1159 OPC_Decode, 223, 17, 3, // 2204: decode to VCMPGTSH_rec using decoder 3
1160 // 2204: }
1161 30, 15, // 2208: case 0x1e: {
1162 OPC_SwitchField, 0, 1, // 2210: switch Inst[0] {
1163 0, 4, // 2213: case 0x0: {
1164 OPC_Decode, 227, 17, 3, // 2215: decode to VCMPGTSW_rec using decoder 3
1165 // 2215: }
1166 1, 0, // 2219: case 0x1: {
1167 OPC_Decode, 225, 17, 3, // 2221: decode to VCMPGTSQ_rec using decoder 3
1168 // 2221: }
1169 // 2221: } // switch Inst[0]
1170 // 2221: }
1171 31, 0, // 2225: case 0x1f: {
1172 OPC_SwitchField, 0, 1, // 2227: switch Inst[0] {
1173 0, 4, // 2230: case 0x0: {
1174 OPC_Decode, 201, 17, 3, // 2232: decode to VCMPBFP_rec using decoder 3
1175 // 2232: }
1176 1, 0, // 2236: case 0x1: {
1177 OPC_Decode, 221, 17, 3, // 2238: decode to VCMPGTSD_rec using decoder 3
1178 // 2238: }
1179 // 2238: } // switch Inst[0]
1180 // 2238: }
1181 // 2238: } // switch Inst[10:6]
1182 // 2238: }
1183 4, 215, 2, // 2242: case 0x4: {
1184 OPC_SwitchField, 6, 5, // 2245: switch Inst[10:6] {
1185 0, 8, // 2248: case 0x0: {
1186 OPC_CheckField, 0, 1, 0, // 2250: check Inst[0] == 0x0
1187 OPC_Decode, 151, 19, 3, // 2254: decode to VMULOUB using decoder 3
1188 // 2254: }
1189 1, 8, // 2258: case 0x1: {
1190 OPC_CheckField, 0, 1, 0, // 2260: check Inst[0] == 0x0
1191 OPC_Decode, 153, 19, 3, // 2264: decode to VMULOUH using decoder 3
1192 // 2264: }
1193 2, 15, // 2268: case 0x2: {
1194 OPC_SwitchField, 0, 1, // 2270: switch Inst[0] {
1195 0, 4, // 2273: case 0x0: {
1196 OPC_Decode, 154, 19, 3, // 2275: decode to VMULOUW using decoder 3
1197 // 2275: }
1198 1, 0, // 2279: case 0x1: {
1199 OPC_Decode, 155, 19, 3, // 2281: decode to VMULUWM using decoder 3
1200 // 2281: }
1201 // 2281: } // switch Inst[0]
1202 // 2281: }
1203 3, 8, // 2285: case 0x3: {
1204 OPC_CheckField, 0, 1, 0, // 2287: check Inst[0] == 0x0
1205 OPC_Decode, 152, 19, 3, // 2291: decode to VMULOUD using decoder 3
1206 // 2291: }
1207 4, 8, // 2295: case 0x4: {
1208 OPC_CheckField, 0, 1, 0, // 2297: check Inst[0] == 0x0
1209 OPC_Decode, 147, 19, 3, // 2301: decode to VMULOSB using decoder 3
1210 // 2301: }
1211 5, 8, // 2305: case 0x5: {
1212 OPC_CheckField, 0, 1, 0, // 2307: check Inst[0] == 0x0
1213 OPC_Decode, 149, 19, 3, // 2311: decode to VMULOSH using decoder 3
1214 // 2311: }
1215 6, 8, // 2315: case 0x6: {
1216 OPC_CheckField, 0, 1, 0, // 2317: check Inst[0] == 0x0
1217 OPC_Decode, 150, 19, 3, // 2321: decode to VMULOSW using decoder 3
1218 // 2321: }
1219 7, 15, // 2325: case 0x7: {
1220 OPC_SwitchField, 0, 1, // 2327: switch Inst[0] {
1221 0, 4, // 2330: case 0x0: {
1222 OPC_Decode, 148, 19, 3, // 2332: decode to VMULOSD using decoder 3
1223 // 2332: }
1224 1, 0, // 2336: case 0x1: {
1225 OPC_Decode, 146, 19, 3, // 2338: decode to VMULLD using decoder 3
1226 // 2338: }
1227 // 2338: } // switch Inst[0]
1228 // 2338: }
1229 8, 8, // 2342: case 0x8: {
1230 OPC_CheckField, 0, 1, 0, // 2344: check Inst[0] == 0x0
1231 OPC_Decode, 138, 19, 3, // 2348: decode to VMULEUB using decoder 3
1232 // 2348: }
1233 9, 8, // 2352: case 0x9: {
1234 OPC_CheckField, 0, 1, 0, // 2354: check Inst[0] == 0x0
1235 OPC_Decode, 140, 19, 3, // 2358: decode to VMULEUH using decoder 3
1236 // 2358: }
1237 10, 15, // 2362: case 0xa: {
1238 OPC_SwitchField, 0, 1, // 2364: switch Inst[0] {
1239 0, 4, // 2367: case 0x0: {
1240 OPC_Decode, 141, 19, 3, // 2369: decode to VMULEUW using decoder 3
1241 // 2369: }
1242 1, 0, // 2373: case 0x1: {
1243 OPC_Decode, 145, 19, 3, // 2375: decode to VMULHUW using decoder 3
1244 // 2375: }
1245 // 2375: } // switch Inst[0]
1246 // 2375: }
1247 11, 15, // 2379: case 0xb: {
1248 OPC_SwitchField, 0, 1, // 2381: switch Inst[0] {
1249 0, 4, // 2384: case 0x0: {
1250 OPC_Decode, 139, 19, 3, // 2386: decode to VMULEUD using decoder 3
1251 // 2386: }
1252 1, 0, // 2390: case 0x1: {
1253 OPC_Decode, 144, 19, 3, // 2392: decode to VMULHUD using decoder 3
1254 // 2392: }
1255 // 2392: } // switch Inst[0]
1256 // 2392: }
1257 12, 8, // 2396: case 0xc: {
1258 OPC_CheckField, 0, 1, 0, // 2398: check Inst[0] == 0x0
1259 OPC_Decode, 134, 19, 3, // 2402: decode to VMULESB using decoder 3
1260 // 2402: }
1261 13, 8, // 2406: case 0xd: {
1262 OPC_CheckField, 0, 1, 0, // 2408: check Inst[0] == 0x0
1263 OPC_Decode, 136, 19, 3, // 2412: decode to VMULESH using decoder 3
1264 // 2412: }
1265 14, 15, // 2416: case 0xe: {
1266 OPC_SwitchField, 0, 1, // 2418: switch Inst[0] {
1267 0, 4, // 2421: case 0x0: {
1268 OPC_Decode, 137, 19, 3, // 2423: decode to VMULESW using decoder 3
1269 // 2423: }
1270 1, 0, // 2427: case 0x1: {
1271 OPC_Decode, 143, 19, 3, // 2429: decode to VMULHSW using decoder 3
1272 // 2429: }
1273 // 2429: } // switch Inst[0]
1274 // 2429: }
1275 15, 15, // 2433: case 0xf: {
1276 OPC_SwitchField, 0, 1, // 2435: switch Inst[0] {
1277 0, 4, // 2438: case 0x0: {
1278 OPC_Decode, 135, 19, 3, // 2440: decode to VMULESD using decoder 3
1279 // 2440: }
1280 1, 0, // 2444: case 0x1: {
1281 OPC_Decode, 142, 19, 3, // 2446: decode to VMULHSD using decoder 3
1282 // 2446: }
1283 // 2446: } // switch Inst[0]
1284 // 2446: }
1285 16, 8, // 2450: case 0x10: {
1286 OPC_CheckField, 0, 1, 0, // 2452: check Inst[0] == 0x0
1287 OPC_Decode, 183, 19, 3, // 2456: decode to VPMSUMB using decoder 3
1288 // 2456: }
1289 17, 8, // 2460: case 0x11: {
1290 OPC_CheckField, 0, 1, 0, // 2462: check Inst[0] == 0x0
1291 OPC_Decode, 185, 19, 3, // 2466: decode to VPMSUMH using decoder 3
1292 // 2466: }
1293 18, 8, // 2470: case 0x12: {
1294 OPC_CheckField, 0, 1, 0, // 2472: check Inst[0] == 0x0
1295 OPC_Decode, 186, 19, 3, // 2476: decode to VPMSUMW using decoder 3
1296 // 2476: }
1297 19, 8, // 2480: case 0x13: {
1298 OPC_CheckField, 0, 1, 0, // 2482: check Inst[0] == 0x0
1299 OPC_Decode, 184, 19, 3, // 2486: decode to VPMSUMD using decoder 3
1300 // 2486: }
1301 20, 15, // 2490: case 0x14: {
1302 OPC_SwitchField, 0, 1, // 2492: switch Inst[0] {
1303 0, 4, // 2495: case 0x0: {
1304 OPC_Decode, 190, 17, 3, // 2497: decode to VCIPHER using decoder 3
1305 // 2497: }
1306 1, 0, // 2501: case 0x1: {
1307 OPC_Decode, 191, 17, 3, // 2503: decode to VCIPHERLAST using decoder 3
1308 // 2503: }
1309 // 2503: } // switch Inst[0]
1310 // 2503: }
1311 21, 15, // 2507: case 0x15: {
1312 OPC_SwitchField, 0, 1, // 2509: switch Inst[0] {
1313 0, 4, // 2512: case 0x0: {
1314 OPC_Decode, 157, 19, 3, // 2514: decode to VNCIPHER using decoder 3
1315 // 2514: }
1316 1, 0, // 2518: case 0x1: {
1317 OPC_Decode, 158, 19, 3, // 2520: decode to VNCIPHERLAST using decoder 3
1318 // 2520: }
1319 // 2520: } // switch Inst[0]
1320 // 2520: }
1321 23, 12, // 2524: case 0x17: {
1322 OPC_CheckField, 11, 5, 0, // 2526: check Inst[15:11] == 0x0
1323 OPC_CheckField, 0, 1, 0, // 2530: check Inst[0] == 0x0
1324 OPC_Decode, 211, 19, 4, // 2534: decode to VSBOX using decoder 4
1325 // 2534: }
1326 24, 8, // 2538: case 0x18: {
1327 OPC_CheckField, 0, 1, 0, // 2540: check Inst[0] == 0x0
1328 OPC_Decode, 146, 20, 3, // 2544: decode to VSUM4UBS using decoder 3
1329 // 2544: }
1330 25, 8, // 2548: case 0x19: {
1331 OPC_CheckField, 0, 1, 0, // 2550: check Inst[0] == 0x0
1332 OPC_Decode, 145, 20, 3, // 2554: decode to VSUM4SHS using decoder 3
1333 // 2554: }
1334 26, 8, // 2558: case 0x1a: {
1335 OPC_CheckField, 0, 1, 0, // 2560: check Inst[0] == 0x0
1336 OPC_Decode, 143, 20, 3, // 2564: decode to VSUM2SWS using decoder 3
1337 // 2564: }
1338 28, 8, // 2568: case 0x1c: {
1339 OPC_CheckField, 0, 1, 0, // 2570: check Inst[0] == 0x0
1340 OPC_Decode, 144, 20, 3, // 2574: decode to VSUM4SBS using decoder 3
1341 // 2574: }
1342 30, 0, // 2578: case 0x1e: {
1343 OPC_CheckField, 0, 1, 0, // 2580: check Inst[0] == 0x0
1344 OPC_Decode, 147, 20, 3, // 2584: decode to VSUMSWS using decoder 3
1345 // 2584: }
1346 // 2584: } // switch Inst[10:6]
1347 // 2584: }
1348 5, 217, 2, // 2588: case 0x5: {
1349 OPC_SwitchField, 6, 5, // 2591: switch Inst[10:6] {
1350 0, 15, // 2594: case 0x0: {
1351 OPC_SwitchField, 0, 1, // 2596: switch Inst[0] {
1352 0, 4, // 2599: case 0x0: {
1353 OPC_Decode, 163, 17, 3, // 2601: decode to VADDFP using decoder 3
1354 // 2601: }
1355 1, 0, // 2605: case 0x1: {
1356 OPC_Decode, 148, 18, 3, // 2607: decode to VDIVUQ using decoder 3
1357 // 2607: }
1358 // 2607: } // switch Inst[0]
1359 // 2607: }
1360 1, 8, // 2611: case 0x1: {
1361 OPC_CheckField, 0, 1, 0, // 2613: check Inst[0] == 0x0
1362 OPC_Decode, 131, 20, 3, // 2617: decode to VSUBFP using decoder 3
1363 // 2617: }
1364 2, 8, // 2621: case 0x2: {
1365 OPC_CheckField, 0, 1, 1, // 2623: check Inst[0] == 0x1
1366 OPC_Decode, 149, 18, 3, // 2627: decode to VDIVUW using decoder 3
1367 // 2627: }
1368 3, 8, // 2631: case 0x3: {
1369 OPC_CheckField, 0, 1, 1, // 2633: check Inst[0] == 0x1
1370 OPC_Decode, 147, 18, 3, // 2637: decode to VDIVUD using decoder 3
1371 // 2637: }
1372 4, 19, // 2641: case 0x4: {
1373 OPC_SwitchField, 0, 1, // 2643: switch Inst[0] {
1374 0, 8, // 2646: case 0x0: {
1375 OPC_CheckField, 16, 5, 0, // 2648: check Inst[20:16] == 0x0
1376 OPC_Decode, 194, 19, 7, // 2652: decode to VREFP using decoder 7
1377 // 2652: }
1378 1, 0, // 2656: case 0x1: {
1379 OPC_Decode, 145, 18, 3, // 2658: decode to VDIVSQ using decoder 3
1380 // 2658: }
1381 // 2658: } // switch Inst[0]
1382 // 2658: }
1383 5, 12, // 2662: case 0x5: {
1384 OPC_CheckField, 16, 5, 0, // 2664: check Inst[20:16] == 0x0
1385 OPC_CheckField, 0, 1, 0, // 2668: check Inst[0] == 0x0
1386 OPC_Decode, 210, 19, 7, // 2672: decode to VRSQRTEFP using decoder 7
1387 // 2672: }
1388 6, 19, // 2676: case 0x6: {
1389 OPC_SwitchField, 0, 1, // 2678: switch Inst[0] {
1390 0, 8, // 2681: case 0x0: {
1391 OPC_CheckField, 16, 5, 0, // 2683: check Inst[20:16] == 0x0
1392 OPC_Decode, 156, 18, 7, // 2687: decode to VEXPTEFP using decoder 7
1393 // 2687: }
1394 1, 0, // 2691: case 0x1: {
1395 OPC_Decode, 146, 18, 3, // 2693: decode to VDIVSW using decoder 3
1396 // 2693: }
1397 // 2693: } // switch Inst[0]
1398 // 2693: }
1399 7, 19, // 2697: case 0x7: {
1400 OPC_SwitchField, 0, 1, // 2699: switch Inst[0] {
1401 0, 8, // 2702: case 0x0: {
1402 OPC_CheckField, 16, 5, 0, // 2704: check Inst[20:16] == 0x0
1403 OPC_Decode, 213, 18, 7, // 2708: decode to VLOGEFP using decoder 7
1404 // 2708: }
1405 1, 0, // 2712: case 0x1: {
1406 OPC_Decode, 144, 18, 3, // 2714: decode to VDIVSD using decoder 3
1407 // 2714: }
1408 // 2714: } // switch Inst[0]
1409 // 2714: }
1410 8, 19, // 2718: case 0x8: {
1411 OPC_SwitchField, 0, 1, // 2720: switch Inst[0] {
1412 0, 8, // 2723: case 0x0: {
1413 OPC_CheckField, 16, 5, 0, // 2725: check Inst[20:16] == 0x0
1414 OPC_Decode, 196, 19, 7, // 2729: decode to VRFIN using decoder 7
1415 // 2729: }
1416 1, 0, // 2733: case 0x1: {
1417 OPC_Decode, 142, 18, 3, // 2735: decode to VDIVEUQ using decoder 3
1418 // 2735: }
1419 // 2735: } // switch Inst[0]
1420 // 2735: }
1421 9, 12, // 2739: case 0x9: {
1422 OPC_CheckField, 16, 5, 0, // 2741: check Inst[20:16] == 0x0
1423 OPC_CheckField, 0, 1, 0, // 2745: check Inst[0] == 0x0
1424 OPC_Decode, 198, 19, 7, // 2749: decode to VRFIZ using decoder 7
1425 // 2749: }
1426 10, 19, // 2753: case 0xa: {
1427 OPC_SwitchField, 0, 1, // 2755: switch Inst[0] {
1428 0, 8, // 2758: case 0x0: {
1429 OPC_CheckField, 16, 5, 0, // 2760: check Inst[20:16] == 0x0
1430 OPC_Decode, 197, 19, 7, // 2764: decode to VRFIP using decoder 7
1431 // 2764: }
1432 1, 0, // 2768: case 0x1: {
1433 OPC_Decode, 143, 18, 3, // 2770: decode to VDIVEUW using decoder 3
1434 // 2770: }
1435 // 2770: } // switch Inst[0]
1436 // 2770: }
1437 11, 19, // 2774: case 0xb: {
1438 OPC_SwitchField, 0, 1, // 2776: switch Inst[0] {
1439 0, 8, // 2779: case 0x0: {
1440 OPC_CheckField, 16, 5, 0, // 2781: check Inst[20:16] == 0x0
1441 OPC_Decode, 195, 19, 7, // 2785: decode to VRFIM using decoder 7
1442 // 2785: }
1443 1, 0, // 2789: case 0x1: {
1444 OPC_Decode, 141, 18, 3, // 2791: decode to VDIVEUD using decoder 3
1445 // 2791: }
1446 // 2791: } // switch Inst[0]
1447 // 2791: }
1448 12, 15, // 2795: case 0xc: {
1449 OPC_SwitchField, 0, 1, // 2797: switch Inst[0] {
1450 0, 4, // 2800: case 0x0: {
1451 OPC_Decode, 188, 17, 19, // 2802: decode to VCFUX using decoder 19
1452 // 2802: }
1453 1, 0, // 2806: case 0x1: {
1454 OPC_Decode, 139, 18, 3, // 2808: decode to VDIVESQ using decoder 3
1455 // 2808: }
1456 // 2808: } // switch Inst[0]
1457 // 2808: }
1458 13, 8, // 2812: case 0xd: {
1459 OPC_CheckField, 0, 1, 0, // 2814: check Inst[0] == 0x0
1460 OPC_Decode, 185, 17, 19, // 2818: decode to VCFSX using decoder 19
1461 // 2818: }
1462 14, 15, // 2822: case 0xe: {
1463 OPC_SwitchField, 0, 1, // 2824: switch Inst[0] {
1464 0, 4, // 2827: case 0x0: {
1465 OPC_Decode, 130, 18, 19, // 2829: decode to VCTUXS using decoder 19
1466 // 2829: }
1467 1, 0, // 2833: case 0x1: {
1468 OPC_Decode, 140, 18, 3, // 2835: decode to VDIVESW using decoder 3
1469 // 2835: }
1470 // 2835: } // switch Inst[0]
1471 // 2835: }
1472 15, 15, // 2839: case 0xf: {
1473 OPC_SwitchField, 0, 1, // 2841: switch Inst[0] {
1474 0, 4, // 2844: case 0x0: {
1475 OPC_Decode, 128, 18, 19, // 2846: decode to VCTSXS using decoder 19
1476 // 2846: }
1477 1, 0, // 2850: case 0x1: {
1478 OPC_Decode, 138, 18, 3, // 2852: decode to VDIVESD using decoder 3
1479 // 2852: }
1480 // 2852: } // switch Inst[0]
1481 // 2852: }
1482 16, 8, // 2856: case 0x10: {
1483 OPC_CheckField, 0, 1, 0, // 2858: check Inst[0] == 0x0
1484 OPC_Decode, 215, 18, 3, // 2862: decode to VMAXFP using decoder 3
1485 // 2862: }
1486 17, 8, // 2866: case 0x11: {
1487 OPC_CheckField, 0, 1, 0, // 2868: check Inst[0] == 0x0
1488 OPC_Decode, 226, 18, 3, // 2872: decode to VMINFP using decoder 3
1489 // 2872: }
1490 24, 8, // 2876: case 0x18: {
1491 OPC_CheckField, 0, 1, 1, // 2878: check Inst[0] == 0x1
1492 OPC_Decode, 240, 18, 3, // 2882: decode to VMODUQ using decoder 3
1493 // 2882: }
1494 26, 8, // 2886: case 0x1a: {
1495 OPC_CheckField, 0, 1, 1, // 2888: check Inst[0] == 0x1
1496 OPC_Decode, 241, 18, 3, // 2892: decode to VMODUW using decoder 3
1497 // 2892: }
1498 27, 8, // 2896: case 0x1b: {
1499 OPC_CheckField, 0, 1, 1, // 2898: check Inst[0] == 0x1
1500 OPC_Decode, 239, 18, 3, // 2902: decode to VMODUD using decoder 3
1501 // 2902: }
1502 28, 8, // 2906: case 0x1c: {
1503 OPC_CheckField, 0, 1, 1, // 2908: check Inst[0] == 0x1
1504 OPC_Decode, 237, 18, 3, // 2912: decode to VMODSQ using decoder 3
1505 // 2912: }
1506 30, 8, // 2916: case 0x1e: {
1507 OPC_CheckField, 0, 1, 1, // 2918: check Inst[0] == 0x1
1508 OPC_Decode, 238, 18, 3, // 2922: decode to VMODSW using decoder 3
1509 // 2922: }
1510 31, 0, // 2926: case 0x1f: {
1511 OPC_CheckField, 0, 1, 1, // 2928: check Inst[0] == 0x1
1512 OPC_Decode, 236, 18, 3, // 2932: decode to VMODSD using decoder 3
1513 // 2932: }
1514 // 2932: } // switch Inst[10:6]
1515 // 2932: }
1516 6, 184, 3, // 2936: case 0x6: {
1517 OPC_SwitchField, 6, 5, // 2939: switch Inst[10:6] {
1518 0, 38, // 2942: case 0x0: {
1519 OPC_SwitchField, 0, 1, // 2944: switch Inst[0] {
1520 0, 4, // 2947: case 0x0: {
1521 OPC_Decode, 243, 18, 3, // 2949: decode to VMRGHB using decoder 3
1522 // 2949: }
1523 1, 0, // 2953: case 0x1: {
1524 OPC_SwitchField, 16, 5, // 2955: switch Inst[20:16] {
1525 0, 4, // 2958: case 0x0: {
1526 OPC_Decode, 247, 19, 7, // 2960: decode to VSTRIBL using decoder 7
1527 // 2960: }
1528 1, 4, // 2964: case 0x1: {
1529 OPC_Decode, 249, 19, 7, // 2966: decode to VSTRIBR using decoder 7
1530 // 2966: }
1531 2, 4, // 2970: case 0x2: {
1532 OPC_Decode, 251, 19, 7, // 2972: decode to VSTRIHL using decoder 7
1533 // 2972: }
1534 3, 0, // 2976: case 0x3: {
1535 OPC_Decode, 253, 19, 7, // 2978: decode to VSTRIHR using decoder 7
1536 // 2978: }
1537 // 2978: } // switch Inst[20:16]
1538 // 2978: }
1539 // 2978: } // switch Inst[0]
1540 // 2978: }
1541 1, 8, // 2982: case 0x1: {
1542 OPC_CheckField, 0, 1, 0, // 2984: check Inst[0] == 0x0
1543 OPC_Decode, 244, 18, 3, // 2988: decode to VMRGHH using decoder 3
1544 // 2988: }
1545 2, 8, // 2992: case 0x2: {
1546 OPC_CheckField, 0, 1, 0, // 2994: check Inst[0] == 0x0
1547 OPC_Decode, 245, 18, 3, // 2998: decode to VMRGHW using decoder 3
1548 // 2998: }
1549 4, 8, // 3002: case 0x4: {
1550 OPC_CheckField, 0, 1, 0, // 3004: check Inst[0] == 0x0
1551 OPC_Decode, 246, 18, 3, // 3008: decode to VMRGLB using decoder 3
1552 // 3008: }
1553 5, 8, // 3012: case 0x5: {
1554 OPC_CheckField, 0, 1, 0, // 3014: check Inst[0] == 0x0
1555 OPC_Decode, 247, 18, 3, // 3018: decode to VMRGLH using decoder 3
1556 // 3018: }
1557 6, 15, // 3022: case 0x6: {
1558 OPC_SwitchField, 0, 1, // 3024: switch Inst[0] {
1559 0, 4, // 3027: case 0x0: {
1560 OPC_Decode, 248, 18, 3, // 3029: decode to VMRGLW using decoder 3
1561 // 3029: }
1562 1, 0, // 3033: case 0x1: {
1563 OPC_Decode, 192, 17, 20, // 3035: decode to VCLRLB using decoder 20
1564 // 3035: }
1565 // 3035: } // switch Inst[0]
1566 // 3035: }
1567 7, 8, // 3039: case 0x7: {
1568 OPC_CheckField, 0, 1, 1, // 3041: check Inst[0] == 0x1
1569 OPC_Decode, 193, 17, 20, // 3045: decode to VCLRRB using decoder 20
1570 // 3045: }
1571 8, 15, // 3049: case 0x8: {
1572 OPC_SwitchField, 0, 1, // 3051: switch Inst[0] {
1573 0, 4, // 3054: case 0x0: {
1574 OPC_Decode, 225, 19, 19, // 3056: decode to VSPLTB using decoder 19
1575 // 3056: }
1576 1, 0, // 3060: case 0x1: {
1577 OPC_Decode, 170, 18, 21, // 3062: decode to VEXTRACTUB using decoder 21
1578 // 3062: }
1579 // 3062: } // switch Inst[0]
1580 // 3062: }
1581 9, 15, // 3066: case 0x9: {
1582 OPC_SwitchField, 0, 1, // 3068: switch Inst[0] {
1583 0, 4, // 3071: case 0x0: {
1584 OPC_Decode, 227, 19, 19, // 3073: decode to VSPLTH using decoder 19
1585 // 3073: }
1586 1, 0, // 3077: case 0x1: {
1587 OPC_Decode, 171, 18, 21, // 3079: decode to VEXTRACTUH using decoder 21
1588 // 3079: }
1589 // 3079: } // switch Inst[0]
1590 // 3079: }
1591 10, 15, // 3083: case 0xa: {
1592 OPC_SwitchField, 0, 1, // 3085: switch Inst[0] {
1593 0, 4, // 3088: case 0x0: {
1594 OPC_Decode, 232, 19, 19, // 3090: decode to VSPLTW using decoder 19
1595 // 3090: }
1596 1, 0, // 3094: case 0x1: {
1597 OPC_Decode, 172, 18, 21, // 3096: decode to VEXTRACTUW using decoder 21
1598 // 3096: }
1599 // 3096: } // switch Inst[0]
1600 // 3096: }
1601 11, 8, // 3100: case 0xb: {
1602 OPC_CheckField, 0, 1, 1, // 3102: check Inst[0] == 0x1
1603 OPC_Decode, 166, 18, 21, // 3106: decode to VEXTRACTD using decoder 21
1604 // 3106: }
1605 12, 19, // 3110: case 0xc: {
1606 OPC_SwitchField, 0, 1, // 3112: switch Inst[0] {
1607 0, 8, // 3115: case 0x0: {
1608 OPC_CheckField, 11, 5, 0, // 3117: check Inst[15:11] == 0x0
1609 OPC_Decode, 229, 19, 22, // 3121: decode to VSPLTISB using decoder 22
1610 // 3121: }
1611 1, 0, // 3125: case 0x1: {
1612 OPC_Decode, 200, 18, 23, // 3127: decode to VINSERTB using decoder 23
1613 // 3127: }
1614 // 3127: } // switch Inst[0]
1615 // 3127: }
1616 13, 19, // 3131: case 0xd: {
1617 OPC_SwitchField, 0, 1, // 3133: switch Inst[0] {
1618 0, 8, // 3136: case 0x0: {
1619 OPC_CheckField, 11, 5, 0, // 3138: check Inst[15:11] == 0x0
1620 OPC_Decode, 230, 19, 22, // 3142: decode to VSPLTISH using decoder 22
1621 // 3142: }
1622 1, 0, // 3146: case 0x1: {
1623 OPC_Decode, 202, 18, 23, // 3148: decode to VINSERTH using decoder 23
1624 // 3148: }
1625 // 3148: } // switch Inst[0]
1626 // 3148: }
1627 14, 19, // 3152: case 0xe: {
1628 OPC_SwitchField, 0, 1, // 3154: switch Inst[0] {
1629 0, 8, // 3157: case 0x0: {
1630 OPC_CheckField, 11, 5, 0, // 3159: check Inst[15:11] == 0x0
1631 OPC_Decode, 231, 19, 22, // 3163: decode to VSPLTISW using decoder 22
1632 // 3163: }
1633 1, 0, // 3167: case 0x1: {
1634 OPC_Decode, 203, 18, 21, // 3169: decode to VINSERTW using decoder 21
1635 // 3169: }
1636 // 3169: } // switch Inst[0]
1637 // 3169: }
1638 15, 8, // 3173: case 0xf: {
1639 OPC_CheckField, 0, 1, 1, // 3175: check Inst[0] == 0x1
1640 OPC_Decode, 201, 18, 21, // 3179: decode to VINSERTD using decoder 21
1641 // 3179: }
1642 16, 38, // 3183: case 0x10: {
1643 OPC_SwitchField, 0, 1, // 3185: switch Inst[0] {
1644 0, 4, // 3188: case 0x0: {
1645 OPC_Decode, 221, 19, 3, // 3190: decode to VSLO using decoder 3
1646 // 3190: }
1647 1, 0, // 3194: case 0x1: {
1648 OPC_SwitchField, 16, 5, // 3196: switch Inst[20:16] {
1649 0, 4, // 3199: case 0x0: {
1650 OPC_Decode, 248, 19, 7, // 3201: decode to VSTRIBL_rec using decoder 7
1651 // 3201: }
1652 1, 4, // 3205: case 0x1: {
1653 OPC_Decode, 250, 19, 7, // 3207: decode to VSTRIBR_rec using decoder 7
1654 // 3207: }
1655 2, 4, // 3211: case 0x2: {
1656 OPC_Decode, 252, 19, 7, // 3213: decode to VSTRIHL_rec using decoder 7
1657 // 3213: }
1658 3, 0, // 3217: case 0x3: {
1659 OPC_Decode, 254, 19, 7, // 3219: decode to VSTRIHR_rec using decoder 7
1660 // 3219: }
1661 // 3219: } // switch Inst[20:16]
1662 // 3219: }
1663 // 3219: } // switch Inst[0]
1664 // 3219: }
1665 17, 8, // 3223: case 0x11: {
1666 OPC_CheckField, 0, 1, 0, // 3225: check Inst[0] == 0x0
1667 OPC_Decode, 243, 19, 3, // 3229: decode to VSRO using decoder 3
1668 // 3229: }
1669 19, 12, // 3233: case 0x13: {
1670 OPC_CheckField, 19, 2, 0, // 3235: check Inst[20:19] == 0x0
1671 OPC_CheckField, 0, 1, 0, // 3239: check Inst[0] == 0x0
1672 OPC_Decode, 192, 18, 24, // 3243: decode to VGNB using decoder 24
1673 // 3243: }
1674 20, 12, // 3247: case 0x14: {
1675 OPC_CheckField, 16, 5, 0, // 3249: check Inst[20:16] == 0x0
1676 OPC_CheckField, 0, 1, 0, // 3253: check Inst[0] == 0x0
1677 OPC_Decode, 191, 18, 7, // 3257: decode to VGBBD using decoder 7
1678 // 3257: }
1679 21, 15, // 3261: case 0x15: {
1680 OPC_SwitchField, 0, 1, // 3263: switch Inst[0] {
1681 0, 4, // 3266: case 0x0: {
1682 OPC_Decode, 184, 17, 3, // 3268: decode to VBPERMQ using decoder 3
1683 // 3268: }
1684 1, 0, // 3272: case 0x1: {
1685 OPC_Decode, 187, 17, 3, // 3274: decode to VCFUGED using decoder 3
1686 // 3274: }
1687 // 3274: } // switch Inst[0]
1688 // 3274: }
1689 22, 8, // 3278: case 0x16: {
1690 OPC_CheckField, 0, 1, 1, // 3280: check Inst[0] == 0x1
1691 OPC_Decode, 169, 19, 3, // 3284: decode to VPEXTD using decoder 3
1692 // 3284: }
1693 23, 15, // 3288: case 0x17: {
1694 OPC_SwitchField, 0, 1, // 3290: switch Inst[0] {
1695 0, 4, // 3293: case 0x0: {
1696 OPC_Decode, 183, 17, 3, // 3295: decode to VBPERMD using decoder 3
1697 // 3295: }
1698 1, 0, // 3299: case 0x1: {
1699 OPC_Decode, 165, 19, 3, // 3301: decode to VPDEPD using decoder 3
1700 // 3301: }
1701 // 3301: } // switch Inst[0]
1702 // 3301: }
1703 24, 8, // 3305: case 0x18: {
1704 OPC_CheckField, 0, 1, 1, // 3307: check Inst[0] == 0x1
1705 OPC_Decode, 185, 18, 25, // 3311: decode to VEXTUBLX using decoder 25
1706 // 3311: }
1707 25, 8, // 3315: case 0x19: {
1708 OPC_CheckField, 0, 1, 1, // 3317: check Inst[0] == 0x1
1709 OPC_Decode, 187, 18, 25, // 3321: decode to VEXTUHLX using decoder 25
1710 // 3321: }
1711 26, 15, // 3325: case 0x1a: {
1712 OPC_SwitchField, 0, 1, // 3327: switch Inst[0] {
1713 0, 4, // 3330: case 0x0: {
1714 OPC_Decode, 249, 18, 3, // 3332: decode to VMRGOW using decoder 3
1715 // 3332: }
1716 1, 0, // 3336: case 0x1: {
1717 OPC_Decode, 189, 18, 25, // 3338: decode to VEXTUWLX using decoder 25
1718 // 3338: }
1719 // 3338: } // switch Inst[0]
1720 // 3338: }
1721 28, 8, // 3342: case 0x1c: {
1722 OPC_CheckField, 0, 1, 1, // 3344: check Inst[0] == 0x1
1723 OPC_Decode, 186, 18, 25, // 3348: decode to VEXTUBRX using decoder 25
1724 // 3348: }
1725 29, 8, // 3352: case 0x1d: {
1726 OPC_CheckField, 0, 1, 1, // 3354: check Inst[0] == 0x1
1727 OPC_Decode, 188, 18, 25, // 3358: decode to VEXTUHRX using decoder 25
1728 // 3358: }
1729 30, 0, // 3362: case 0x1e: {
1730 OPC_SwitchField, 0, 1, // 3364: switch Inst[0] {
1731 0, 4, // 3367: case 0x0: {
1732 OPC_Decode, 242, 18, 3, // 3369: decode to VMRGEW using decoder 3
1733 // 3369: }
1734 1, 0, // 3373: case 0x1: {
1735 OPC_Decode, 190, 18, 25, // 3375: decode to VEXTUWRX using decoder 25
1736 // 3375: }
1737 // 3375: } // switch Inst[0]
1738 // 3375: }
1739 // 3375: } // switch Inst[10:6]
1740 // 3375: }
1741 7, 232, 2, // 3379: case 0x7: {
1742 OPC_SwitchField, 6, 5, // 3382: switch Inst[10:6] {
1743 0, 15, // 3385: case 0x0: {
1744 OPC_SwitchField, 0, 1, // 3387: switch Inst[0] {
1745 0, 4, // 3390: case 0x0: {
1746 OPC_Decode, 179, 19, 3, // 3392: decode to VPKUHUM using decoder 3
1747 // 3392: }
1748 1, 0, // 3396: case 0x1: {
1749 OPC_Decode, 195, 18, 26, // 3398: decode to VINSBVLX using decoder 26
1750 // 3398: }
1751 // 3398: } // switch Inst[0]
1752 // 3398: }
1753 1, 15, // 3402: case 0x1: {
1754 OPC_SwitchField, 0, 1, // 3404: switch Inst[0] {
1755 0, 4, // 3407: case 0x0: {
1756 OPC_Decode, 181, 19, 3, // 3409: decode to VPKUWUM using decoder 3
1757 // 3409: }
1758 1, 0, // 3413: case 0x1: {
1759 OPC_Decode, 206, 18, 26, // 3415: decode to VINSHVLX using decoder 26
1760 // 3415: }
1761 // 3415: } // switch Inst[0]
1762 // 3415: }
1763 2, 15, // 3419: case 0x2: {
1764 OPC_SwitchField, 0, 1, // 3421: switch Inst[0] {
1765 0, 4, // 3424: case 0x0: {
1766 OPC_Decode, 180, 19, 3, // 3426: decode to VPKUHUS using decoder 3
1767 // 3426: }
1768 1, 0, // 3430: case 0x1: {
1769 OPC_Decode, 211, 18, 26, // 3432: decode to VINSWVLX using decoder 26
1770 // 3432: }
1771 // 3432: } // switch Inst[0]
1772 // 3432: }
1773 3, 15, // 3436: case 0x3: {
1774 OPC_SwitchField, 0, 1, // 3438: switch Inst[0] {
1775 0, 4, // 3441: case 0x0: {
1776 OPC_Decode, 182, 19, 3, // 3443: decode to VPKUWUS using decoder 3
1777 // 3443: }
1778 1, 0, // 3447: case 0x1: {
1779 OPC_Decode, 208, 18, 27, // 3449: decode to VINSW using decoder 27
1780 // 3449: }
1781 // 3449: } // switch Inst[0]
1782 // 3449: }
1783 4, 15, // 3453: case 0x4: {
1784 OPC_SwitchField, 0, 1, // 3455: switch Inst[0] {
1785 0, 4, // 3458: case 0x0: {
1786 OPC_Decode, 174, 19, 3, // 3460: decode to VPKSHUS using decoder 3
1787 // 3460: }
1788 1, 0, // 3464: case 0x1: {
1789 OPC_Decode, 196, 18, 26, // 3466: decode to VINSBVRX using decoder 26
1790 // 3466: }
1791 // 3466: } // switch Inst[0]
1792 // 3466: }
1793 5, 15, // 3470: case 0x5: {
1794 OPC_SwitchField, 0, 1, // 3472: switch Inst[0] {
1795 0, 4, // 3475: case 0x0: {
1796 OPC_Decode, 176, 19, 3, // 3477: decode to VPKSWUS using decoder 3
1797 // 3477: }
1798 1, 0, // 3481: case 0x1: {
1799 OPC_Decode, 207, 18, 26, // 3483: decode to VINSHVRX using decoder 26
1800 // 3483: }
1801 // 3483: } // switch Inst[0]
1802 // 3483: }
1803 6, 15, // 3487: case 0x6: {
1804 OPC_SwitchField, 0, 1, // 3489: switch Inst[0] {
1805 0, 4, // 3492: case 0x0: {
1806 OPC_Decode, 173, 19, 3, // 3494: decode to VPKSHSS using decoder 3
1807 // 3494: }
1808 1, 0, // 3498: case 0x1: {
1809 OPC_Decode, 212, 18, 26, // 3500: decode to VINSWVRX using decoder 26
1810 // 3500: }
1811 // 3500: } // switch Inst[0]
1812 // 3500: }
1813 7, 15, // 3504: case 0x7: {
1814 OPC_SwitchField, 0, 1, // 3506: switch Inst[0] {
1815 0, 4, // 3509: case 0x0: {
1816 OPC_Decode, 175, 19, 3, // 3511: decode to VPKSWSS using decoder 3
1817 // 3511: }
1818 1, 0, // 3515: case 0x1: {
1819 OPC_Decode, 197, 18, 28, // 3517: decode to VINSD using decoder 28
1820 // 3517: }
1821 // 3517: } // switch Inst[0]
1822 // 3517: }
1823 8, 19, // 3521: case 0x8: {
1824 OPC_SwitchField, 0, 1, // 3523: switch Inst[0] {
1825 0, 8, // 3526: case 0x0: {
1826 OPC_CheckField, 16, 5, 0, // 3528: check Inst[20:16] == 0x0
1827 OPC_Decode, 155, 20, 7, // 3532: decode to VUPKHSB using decoder 7
1828 // 3532: }
1829 1, 0, // 3536: case 0x1: {
1830 OPC_Decode, 193, 18, 29, // 3538: decode to VINSBLX using decoder 29
1831 // 3538: }
1832 // 3538: } // switch Inst[0]
1833 // 3538: }
1834 9, 19, // 3542: case 0x9: {
1835 OPC_SwitchField, 0, 1, // 3544: switch Inst[0] {
1836 0, 8, // 3547: case 0x0: {
1837 OPC_CheckField, 16, 5, 0, // 3549: check Inst[20:16] == 0x0
1838 OPC_Decode, 156, 20, 7, // 3553: decode to VUPKHSH using decoder 7
1839 // 3553: }
1840 1, 0, // 3557: case 0x1: {
1841 OPC_Decode, 204, 18, 29, // 3559: decode to VINSHLX using decoder 29
1842 // 3559: }
1843 // 3559: } // switch Inst[0]
1844 // 3559: }
1845 10, 19, // 3563: case 0xa: {
1846 OPC_SwitchField, 0, 1, // 3565: switch Inst[0] {
1847 0, 8, // 3568: case 0x0: {
1848 OPC_CheckField, 16, 5, 0, // 3570: check Inst[20:16] == 0x0
1849 OPC_Decode, 164, 20, 7, // 3574: decode to VUPKLSB using decoder 7
1850 // 3574: }
1851 1, 0, // 3578: case 0x1: {
1852 OPC_Decode, 209, 18, 29, // 3580: decode to VINSWLX using decoder 29
1853 // 3580: }
1854 // 3580: } // switch Inst[0]
1855 // 3580: }
1856 11, 19, // 3584: case 0xb: {
1857 OPC_SwitchField, 0, 1, // 3586: switch Inst[0] {
1858 0, 8, // 3589: case 0x0: {
1859 OPC_CheckField, 16, 5, 0, // 3591: check Inst[20:16] == 0x0
1860 OPC_Decode, 165, 20, 7, // 3595: decode to VUPKLSH using decoder 7
1861 // 3595: }
1862 1, 0, // 3599: case 0x1: {
1863 OPC_Decode, 198, 18, 30, // 3601: decode to VINSDLX using decoder 30
1864 // 3601: }
1865 // 3601: } // switch Inst[0]
1866 // 3601: }
1867 12, 15, // 3605: case 0xc: {
1868 OPC_SwitchField, 0, 1, // 3607: switch Inst[0] {
1869 0, 4, // 3610: case 0x0: {
1870 OPC_Decode, 170, 19, 3, // 3612: decode to VPKPX using decoder 3
1871 // 3612: }
1872 1, 0, // 3616: case 0x1: {
1873 OPC_Decode, 194, 18, 29, // 3618: decode to VINSBRX using decoder 29
1874 // 3618: }
1875 // 3618: } // switch Inst[0]
1876 // 3618: }
1877 13, 19, // 3622: case 0xd: {
1878 OPC_SwitchField, 0, 1, // 3624: switch Inst[0] {
1879 0, 8, // 3627: case 0x0: {
1880 OPC_CheckField, 16, 5, 0, // 3629: check Inst[20:16] == 0x0
1881 OPC_Decode, 154, 20, 7, // 3633: decode to VUPKHPX using decoder 7
1882 // 3633: }
1883 1, 0, // 3637: case 0x1: {
1884 OPC_Decode, 205, 18, 29, // 3639: decode to VINSHRX using decoder 29
1885 // 3639: }
1886 // 3639: } // switch Inst[0]
1887 // 3639: }
1888 14, 8, // 3643: case 0xe: {
1889 OPC_CheckField, 0, 1, 1, // 3645: check Inst[0] == 0x1
1890 OPC_Decode, 210, 18, 29, // 3649: decode to VINSWRX using decoder 29
1891 // 3649: }
1892 15, 19, // 3653: case 0xf: {
1893 OPC_SwitchField, 0, 1, // 3655: switch Inst[0] {
1894 0, 8, // 3658: case 0x0: {
1895 OPC_CheckField, 16, 5, 0, // 3660: check Inst[20:16] == 0x0
1896 OPC_Decode, 163, 20, 7, // 3664: decode to VUPKLPX using decoder 7
1897 // 3664: }
1898 1, 0, // 3668: case 0x1: {
1899 OPC_Decode, 199, 18, 30, // 3670: decode to VINSDRX using decoder 30
1900 // 3670: }
1901 // 3670: } // switch Inst[0]
1902 // 3670: }
1903 17, 8, // 3674: case 0x11: {
1904 OPC_CheckField, 0, 1, 0, // 3676: check Inst[0] == 0x0
1905 OPC_Decode, 177, 19, 3, // 3680: decode to VPKUDUM using decoder 3
1906 // 3680: }
1907 19, 8, // 3684: case 0x13: {
1908 OPC_CheckField, 0, 1, 0, // 3686: check Inst[0] == 0x0
1909 OPC_Decode, 178, 19, 3, // 3690: decode to VPKUDUS using decoder 3
1910 // 3690: }
1911 21, 8, // 3694: case 0x15: {
1912 OPC_CheckField, 0, 1, 0, // 3696: check Inst[0] == 0x0
1913 OPC_Decode, 172, 19, 3, // 3700: decode to VPKSDUS using decoder 3
1914 // 3700: }
1915 23, 8, // 3704: case 0x17: {
1916 OPC_CheckField, 0, 1, 0, // 3706: check Inst[0] == 0x0
1917 OPC_Decode, 171, 19, 3, // 3710: decode to VPKSDSS using decoder 3
1918 // 3710: }
1919 25, 12, // 3714: case 0x19: {
1920 OPC_CheckField, 16, 5, 0, // 3716: check Inst[20:16] == 0x0
1921 OPC_CheckField, 0, 1, 0, // 3720: check Inst[0] == 0x0
1922 OPC_Decode, 158, 20, 7, // 3724: decode to VUPKHSW using decoder 7
1923 // 3724: }
1924 27, 0, // 3728: case 0x1b: {
1925 OPC_CheckField, 16, 5, 0, // 3730: check Inst[20:16] == 0x0
1926 OPC_CheckField, 0, 1, 0, // 3734: check Inst[0] == 0x0
1927 OPC_Decode, 167, 20, 7, // 3738: decode to VUPKLSW using decoder 7
1928 // 3738: }
1929 // 3738: } // switch Inst[10:6]
1930 // 3738: }
1931 10, 4, // 3742: case 0xa: {
1932 OPC_Decode, 172, 12, 31, // 3744: decode to MTVSRBMI using decoder 31
1933 // 3744: }
1934 11, 26, // 3748: case 0xb: {
1935 OPC_SwitchField, 0, 1, // 3750: switch Inst[0] {
1936 0, 15, // 3753: case 0x0: {
1937 OPC_SwitchField, 9, 2, // 3755: switch Inst[10:9] {
1938 0, 4, // 3758: case 0x0: {
1939 OPC_Decode, 218, 19, 32, // 3760: decode to VSLDBI using decoder 32
1940 // 3760: }
1941 1, 0, // 3764: case 0x1: {
1942 OPC_Decode, 241, 19, 32, // 3766: decode to VSRDBI using decoder 32
1943 // 3766: }
1944 // 3766: } // switch Inst[10:9]
1945 // 3766: }
1946 1, 0, // 3770: case 0x1: {
1947 OPC_Decode, 250, 18, 33, // 3772: decode to VMSUMCUD using decoder 33
1948 // 3772: }
1949 // 3772: } // switch Inst[0]
1950 // 3772: }
1951 12, 15, // 3776: case 0xc: {
1952 OPC_SwitchField, 0, 1, // 3778: switch Inst[0] {
1953 0, 4, // 3781: case 0x0: {
1954 OPC_Decode, 159, 18, 34, // 3783: decode to VEXTDUBVLX using decoder 34
1955 // 3783: }
1956 1, 0, // 3787: case 0x1: {
1957 OPC_Decode, 160, 18, 34, // 3789: decode to VEXTDUBVRX using decoder 34
1958 // 3789: }
1959 // 3789: } // switch Inst[0]
1960 // 3789: }
1961 13, 15, // 3793: case 0xd: {
1962 OPC_SwitchField, 0, 1, // 3795: switch Inst[0] {
1963 0, 4, // 3798: case 0x0: {
1964 OPC_Decode, 161, 18, 34, // 3800: decode to VEXTDUHVLX using decoder 34
1965 // 3800: }
1966 1, 0, // 3804: case 0x1: {
1967 OPC_Decode, 162, 18, 34, // 3806: decode to VEXTDUHVRX using decoder 34
1968 // 3806: }
1969 // 3806: } // switch Inst[0]
1970 // 3806: }
1971 14, 15, // 3810: case 0xe: {
1972 OPC_SwitchField, 0, 1, // 3812: switch Inst[0] {
1973 0, 4, // 3815: case 0x0: {
1974 OPC_Decode, 163, 18, 34, // 3817: decode to VEXTDUWVLX using decoder 34
1975 // 3817: }
1976 1, 0, // 3821: case 0x1: {
1977 OPC_Decode, 164, 18, 34, // 3823: decode to VEXTDUWVRX using decoder 34
1978 // 3823: }
1979 // 3823: } // switch Inst[0]
1980 // 3823: }
1981 15, 15, // 3827: case 0xf: {
1982 OPC_SwitchField, 0, 1, // 3829: switch Inst[0] {
1983 0, 4, // 3832: case 0x0: {
1984 OPC_Decode, 157, 18, 34, // 3834: decode to VEXTDDVLX using decoder 34
1985 // 3834: }
1986 1, 0, // 3838: case 0x1: {
1987 OPC_Decode, 158, 18, 34, // 3840: decode to VEXTDDVRX using decoder 34
1988 // 3840: }
1989 // 3840: } // switch Inst[0]
1990 // 3840: }
1991 16, 15, // 3844: case 0x10: {
1992 OPC_SwitchField, 0, 1, // 3846: switch Inst[0] {
1993 0, 4, // 3849: case 0x0: {
1994 OPC_Decode, 224, 18, 33, // 3851: decode to VMHADDSHS using decoder 33
1995 // 3851: }
1996 1, 0, // 3855: case 0x1: {
1997 OPC_Decode, 225, 18, 33, // 3857: decode to VMHRADDSHS using decoder 33
1998 // 3857: }
1999 // 3857: } // switch Inst[0]
2000 // 3857: }
2001 17, 15, // 3861: case 0x11: {
2002 OPC_SwitchField, 0, 1, // 3863: switch Inst[0] {
2003 0, 4, // 3866: case 0x0: {
2004 OPC_Decode, 235, 18, 33, // 3868: decode to VMLADDUHM using decoder 33
2005 // 3868: }
2006 1, 0, // 3872: case 0x1: {
2007 OPC_Decode, 255, 18, 33, // 3874: decode to VMSUMUDM using decoder 33
2008 // 3874: }
2009 // 3874: } // switch Inst[0]
2010 // 3874: }
2011 18, 15, // 3878: case 0x12: {
2012 OPC_SwitchField, 0, 1, // 3880: switch Inst[0] {
2013 0, 4, // 3883: case 0x0: {
2014 OPC_Decode, 254, 18, 33, // 3885: decode to VMSUMUBM using decoder 33
2015 // 3885: }
2016 1, 0, // 3889: case 0x1: {
2017 OPC_Decode, 251, 18, 33, // 3891: decode to VMSUMMBM using decoder 33
2018 // 3891: }
2019 // 3891: } // switch Inst[0]
2020 // 3891: }
2021 19, 15, // 3895: case 0x13: {
2022 OPC_SwitchField, 0, 1, // 3897: switch Inst[0] {
2023 0, 4, // 3900: case 0x0: {
2024 OPC_Decode, 128, 19, 33, // 3902: decode to VMSUMUHM using decoder 33
2025 // 3902: }
2026 1, 0, // 3906: case 0x1: {
2027 OPC_Decode, 129, 19, 33, // 3908: decode to VMSUMUHS using decoder 33
2028 // 3908: }
2029 // 3908: } // switch Inst[0]
2030 // 3908: }
2031 20, 15, // 3912: case 0x14: {
2032 OPC_SwitchField, 0, 1, // 3914: switch Inst[0] {
2033 0, 4, // 3917: case 0x0: {
2034 OPC_Decode, 252, 18, 33, // 3919: decode to VMSUMSHM using decoder 33
2035 // 3919: }
2036 1, 0, // 3923: case 0x1: {
2037 OPC_Decode, 253, 18, 33, // 3925: decode to VMSUMSHS using decoder 33
2038 // 3925: }
2039 // 3925: } // switch Inst[0]
2040 // 3925: }
2041 21, 15, // 3929: case 0x15: {
2042 OPC_SwitchField, 0, 1, // 3931: switch Inst[0] {
2043 0, 4, // 3934: case 0x0: {
2044 OPC_Decode, 212, 19, 33, // 3936: decode to VSEL using decoder 33
2045 // 3936: }
2046 1, 0, // 3940: case 0x1: {
2047 OPC_Decode, 166, 19, 33, // 3942: decode to VPERM using decoder 33
2048 // 3942: }
2049 // 3942: } // switch Inst[0]
2050 // 3942: }
2051 22, 19, // 3946: case 0x16: {
2052 OPC_SwitchField, 0, 1, // 3948: switch Inst[0] {
2053 0, 8, // 3951: case 0x0: {
2054 OPC_CheckField, 10, 1, 0, // 3953: check Inst[10] == 0x0
2055 OPC_Decode, 219, 19, 35, // 3957: decode to VSLDOI using decoder 35
2056 // 3957: }
2057 1, 0, // 3961: case 0x1: {
2058 OPC_Decode, 168, 19, 33, // 3963: decode to VPERMXOR using decoder 33
2059 // 3963: }
2060 // 3963: } // switch Inst[0]
2061 // 3963: }
2062 23, 15, // 3967: case 0x17: {
2063 OPC_SwitchField, 0, 1, // 3969: switch Inst[0] {
2064 0, 4, // 3972: case 0x0: {
2065 OPC_Decode, 214, 18, 36, // 3974: decode to VMADDFP using decoder 36
2066 // 3974: }
2067 1, 0, // 3978: case 0x1: {
2068 OPC_Decode, 161, 19, 36, // 3980: decode to VNMSUBFP using decoder 36
2069 // 3980: }
2070 // 3980: } // switch Inst[0]
2071 // 3980: }
2072 24, 15, // 3984: case 0x18: {
2073 OPC_SwitchField, 0, 1, // 3986: switch Inst[0] {
2074 0, 4, // 3989: case 0x0: {
2075 OPC_Decode, 213, 11, 37, // 3991: decode to MADDHD using decoder 37
2076 // 3991: }
2077 1, 0, // 3995: case 0x1: {
2078 OPC_Decode, 214, 11, 37, // 3997: decode to MADDHDU using decoder 37
2079 // 3997: }
2080 // 3997: } // switch Inst[0]
2081 // 3997: }
2082 25, 8, // 4001: case 0x19: {
2083 OPC_CheckField, 0, 1, 1, // 4003: check Inst[0] == 0x1
2084 OPC_Decode, 215, 11, 38, // 4007: decode to MADDLD using decoder 38
2085 // 4007: }
2086 29, 8, // 4011: case 0x1d: {
2087 OPC_CheckField, 0, 1, 1, // 4013: check Inst[0] == 0x1
2088 OPC_Decode, 167, 19, 33, // 4017: decode to VPERMR using decoder 33
2089 // 4017: }
2090 30, 15, // 4021: case 0x1e: {
2091 OPC_SwitchField, 0, 1, // 4023: switch Inst[0] {
2092 0, 4, // 4026: case 0x0: {
2093 OPC_Decode, 162, 17, 33, // 4028: decode to VADDEUQM using decoder 33
2094 // 4028: }
2095 1, 0, // 4032: case 0x1: {
2096 OPC_Decode, 161, 17, 33, // 4034: decode to VADDECUQ using decoder 33
2097 // 4034: }
2098 // 4034: } // switch Inst[0]
2099 // 4034: }
2100 31, 0, // 4038: case 0x1f: {
2101 OPC_SwitchField, 0, 1, // 4040: switch Inst[0] {
2102 0, 4, // 4043: case 0x0: {
2103 OPC_Decode, 130, 20, 33, // 4045: decode to VSUBEUQM using decoder 33
2104 // 4045: }
2105 1, 0, // 4049: case 0x1: {
2106 OPC_Decode, 129, 20, 33, // 4051: decode to VSUBECUQ using decoder 33
2107 // 4051: }
2108 // 4051: } // switch Inst[0]
2109 // 4051: }
2110 // 4051: } // switch Inst[5:1]
2111 // 4051: }
2112 6, 15, // 4055: case 0x6: {
2113 OPC_SwitchField, 0, 4, // 4057: switch Inst[3:0] {
2114 0, 4, // 4060: case 0x0: {
2115 OPC_Decode, 199, 11, 39, // 4062: decode to LXVP using decoder 39
2116 // 4062: }
2117 1, 0, // 4066: case 0x1: {
2118 OPC_Decode, 168, 16, 39, // 4068: decode to STXVP using decoder 39
2119 // 4068: }
2120 // 4068: } // switch Inst[3:0]
2121 // 4068: }
2122 7, 4, // 4072: case 0x7: {
2123 OPC_Decode, 194, 12, 40, // 4074: decode to MULLI using decoder 40
2124 // 4074: }
2125 8, 4, // 4078: case 0x8: {
2126 OPC_Decode, 202, 16, 40, // 4080: decode to SUBFIC using decoder 40
2127 // 4080: }
2128 10, 15, // 4084: case 0xa: {
2129 OPC_SwitchField, 21, 2, // 4086: switch Inst[22:21] {
2130 0, 4, // 4089: case 0x0: {
2131 OPC_Decode, 182, 5, 41, // 4091: decode to CMPLWI using decoder 41
2132 // 4091: }
2133 1, 0, // 4095: case 0x1: {
2134 OPC_Decode, 180, 5, 42, // 4097: decode to CMPLDI using decoder 42
2135 // 4097: }
2136 // 4097: } // switch Inst[22:21]
2137 // 4097: }
2138 11, 15, // 4101: case 0xb: {
2139 OPC_SwitchField, 21, 2, // 4103: switch Inst[22:21] {
2140 0, 4, // 4106: case 0x0: {
2141 OPC_Decode, 186, 5, 43, // 4108: decode to CMPWI using decoder 43
2142 // 4108: }
2143 1, 0, // 4112: case 0x1: {
2144 OPC_Decode, 177, 5, 44, // 4114: decode to CMPDI using decoder 44
2145 // 4114: }
2146 // 4114: } // switch Inst[22:21]
2147 // 4114: }
2148 12, 4, // 4118: case 0xc: {
2149 OPC_Decode, 189, 3, 40, // 4120: decode to ADDIC using decoder 40
2150 // 4120: }
2151 13, 4, // 4124: case 0xd: {
2152 OPC_Decode, 191, 3, 40, // 4126: decode to ADDIC_rec using decoder 40
2153 // 4126: }
2154 14, 14, // 4130: case 0xe: {
2155 OPC_Scope, 8, // 4132: try {
2156 OPC_CheckField, 16, 5, 0, // 4134: check Inst[20:16] == 0x0
2157 OPC_Decode, 136, 11, 45, // 4138: decode to LI using decoder 45
2158 // 4138: } else try {
2159 OPC_Decode, 187, 3, 46, // 4142: decode to ADDI using decoder 46
2160 // 4142: }
2161 // 4142: }
2162 15, 14, // 4146: case 0xf: {
2163 OPC_Scope, 8, // 4148: try {
2164 OPC_CheckField, 16, 5, 0, // 4150: check Inst[20:16] == 0x0
2165 OPC_Decode, 138, 11, 45, // 4154: decode to LIS using decoder 45
2166 // 4154: } else try {
2167 OPC_Decode, 192, 3, 46, // 4158: decode to ADDIS using decoder 46
2168 // 4158: }
2169 // 4158: }
2170 16, 215, 1, // 4162: case 0x10: {
2171 OPC_SwitchField, 0, 2, // 4165: switch Inst[1:0] {
2172 0, 51, // 4168: case 0x0: {
2173 OPC_Scope, 45, // 4170: try {
2174 OPC_SwitchField, 16, 10, // 4172: switch Inst[25:16] {
2175 128, 4, 4, // 4175: case 0x200: {
2176 OPC_Decode, 225, 4, 47, // 4178: decode to BDNZ using decoder 47
2177 // 4178: }
2178 192, 4, 4, // 4182: case 0x240: {
2179 OPC_Decode, 245, 4, 47, // 4185: decode to BDZ using decoder 47
2180 // 4185: }
2181 128, 6, 4, // 4189: case 0x300: {
2182 OPC_Decode, 243, 4, 47, // 4192: decode to BDNZm using decoder 47
2183 // 4192: }
2184 160, 6, 4, // 4196: case 0x320: {
2185 OPC_Decode, 244, 4, 47, // 4199: decode to BDNZp using decoder 47
2186 // 4199: }
2187 192, 6, 4, // 4203: case 0x340: {
2188 OPC_Decode, 135, 5, 47, // 4206: decode to BDZm using decoder 47
2189 // 4206: }
2190 224, 6, 0, // 4210: case 0x360: {
2191 OPC_Decode, 136, 5, 47, // 4213: decode to BDZp using decoder 47
2192 // 4213: }
2193 // 4213: } // switch Inst[25:16]
2194 // 4213: } else try {
2195 OPC_Decode, 173, 23, 48, // 4217: decode to gBC using decoder 48
2196 // 4217: }
2197 // 4217: }
2198 1, 51, // 4221: case 0x1: {
2199 OPC_Scope, 45, // 4223: try {
2200 OPC_SwitchField, 16, 10, // 4225: switch Inst[25:16] {
2201 128, 4, 4, // 4228: case 0x200: {
2202 OPC_Decode, 230, 4, 47, // 4231: decode to BDNZL using decoder 47
2203 // 4231: }
2204 192, 4, 4, // 4235: case 0x240: {
2205 OPC_Decode, 250, 4, 47, // 4238: decode to BDZL using decoder 47
2206 // 4238: }
2207 128, 6, 4, // 4242: case 0x300: {
2208 OPC_Decode, 241, 4, 47, // 4245: decode to BDNZLm using decoder 47
2209 // 4245: }
2210 160, 6, 4, // 4249: case 0x320: {
2211 OPC_Decode, 242, 4, 47, // 4252: decode to BDNZLp using decoder 47
2212 // 4252: }
2213 192, 6, 4, // 4256: case 0x340: {
2214 OPC_Decode, 133, 5, 47, // 4259: decode to BDZLm using decoder 47
2215 // 4259: }
2216 224, 6, 0, // 4263: case 0x360: {
2217 OPC_Decode, 134, 5, 47, // 4266: decode to BDZLp using decoder 47
2218 // 4266: }
2219 // 4266: } // switch Inst[25:16]
2220 // 4266: } else try {
2221 OPC_Decode, 178, 23, 48, // 4270: decode to gBCL using decoder 48
2222 // 4270: }
2223 // 4270: }
2224 2, 51, // 4274: case 0x2: {
2225 OPC_Scope, 45, // 4276: try {
2226 OPC_SwitchField, 16, 10, // 4278: switch Inst[25:16] {
2227 128, 4, 4, // 4281: case 0x200: {
2228 OPC_Decode, 227, 4, 47, // 4284: decode to BDNZA using decoder 47
2229 // 4284: }
2230 192, 4, 4, // 4288: case 0x240: {
2231 OPC_Decode, 247, 4, 47, // 4291: decode to BDZA using decoder 47
2232 // 4291: }
2233 128, 6, 4, // 4295: case 0x300: {
2234 OPC_Decode, 228, 4, 47, // 4298: decode to BDNZAm using decoder 47
2235 // 4298: }
2236 160, 6, 4, // 4302: case 0x320: {
2237 OPC_Decode, 229, 4, 47, // 4305: decode to BDNZAp using decoder 47
2238 // 4305: }
2239 192, 6, 4, // 4309: case 0x340: {
2240 OPC_Decode, 248, 4, 47, // 4312: decode to BDZAm using decoder 47
2241 // 4312: }
2242 224, 6, 0, // 4316: case 0x360: {
2243 OPC_Decode, 249, 4, 47, // 4319: decode to BDZAp using decoder 47
2244 // 4319: }
2245 // 4319: } // switch Inst[25:16]
2246 // 4319: } else try {
2247 OPC_Decode, 174, 23, 48, // 4323: decode to gBCA using decoder 48
2248 // 4323: }
2249 // 4323: }
2250 3, 0, // 4327: case 0x3: {
2251 OPC_Scope, 45, // 4329: try {
2252 OPC_SwitchField, 16, 10, // 4331: switch Inst[25:16] {
2253 128, 4, 4, // 4334: case 0x200: {
2254 OPC_Decode, 231, 4, 47, // 4337: decode to BDNZLA using decoder 47
2255 // 4337: }
2256 192, 4, 4, // 4341: case 0x240: {
2257 OPC_Decode, 251, 4, 47, // 4344: decode to BDZLA using decoder 47
2258 // 4344: }
2259 128, 6, 4, // 4348: case 0x300: {
2260 OPC_Decode, 232, 4, 47, // 4351: decode to BDNZLAm using decoder 47
2261 // 4351: }
2262 160, 6, 4, // 4355: case 0x320: {
2263 OPC_Decode, 233, 4, 47, // 4358: decode to BDNZLAp using decoder 47
2264 // 4358: }
2265 192, 6, 4, // 4362: case 0x340: {
2266 OPC_Decode, 252, 4, 47, // 4365: decode to BDZLAm using decoder 47
2267 // 4365: }
2268 224, 6, 0, // 4369: case 0x360: {
2269 OPC_Decode, 253, 4, 47, // 4372: decode to BDZLAp using decoder 47
2270 // 4372: }
2271 // 4372: } // switch Inst[25:16]
2272 // 4372: } else try {
2273 OPC_Decode, 179, 23, 48, // 4376: decode to gBCLA using decoder 48
2274 // 4376: }
2275 // 4376: }
2276 // 4376: } // switch Inst[1:0]
2277 // 4376: }
2278 17, 15, // 4380: case 0x11: {
2279 OPC_SwitchField, 0, 2, // 4382: switch Inst[1:0] {
2280 1, 4, // 4385: case 0x1: {
2281 OPC_Decode, 247, 14, 49, // 4387: decode to SCV using decoder 49
2282 // 4387: }
2283 2, 0, // 4391: case 0x2: {
2284 OPC_Decode, 246, 14, 49, // 4393: decode to SC using decoder 49
2285 // 4393: }
2286 // 4393: } // switch Inst[1:0]
2287 // 4393: }
2288 18, 27, // 4397: case 0x12: {
2289 OPC_SwitchField, 0, 2, // 4399: switch Inst[1:0] {
2290 0, 4, // 4402: case 0x0: {
2291 OPC_Decode, 171, 4, 50, // 4404: decode to B using decoder 50
2292 // 4404: }
2293 1, 4, // 4408: case 0x1: {
2294 OPC_Decode, 137, 5, 50, // 4410: decode to BL using decoder 50
2295 // 4410: }
2296 2, 4, // 4414: case 0x2: {
2297 OPC_Decode, 172, 4, 50, // 4416: decode to BA using decoder 50
2298 // 4416: }
2299 3, 0, // 4420: case 0x3: {
2300 OPC_Decode, 148, 5, 50, // 4422: decode to BLA using decoder 50
2301 // 4422: }
2302 // 4422: } // switch Inst[1:0]
2303 // 4422: }
2304 19, 251, 3, // 4426: case 0x13: {
2305 OPC_SwitchField, 1, 5, // 4429: switch Inst[5:1] {
2306 0, 16, // 4432: case 0x0: {
2307 OPC_CheckField, 21, 2, 0, // 4434: check Inst[22:21] == 0x0
2308 OPC_CheckField, 6, 12, 0, // 4438: check Inst[17:6] == 0x0
2309 OPC_CheckField, 0, 1, 0, // 4442: check Inst[0] == 0x0
2310 OPC_Decode, 218, 11, 51, // 4446: decode to MCRF using decoder 51
2311 // 4446: }
2312 1, 83, // 4450: case 0x1: {
2313 OPC_SwitchField, 6, 5, // 4452: switch Inst[10:6] {
2314 1, 8, // 4455: case 0x1: {
2315 OPC_CheckField, 0, 1, 0, // 4457: check Inst[0] == 0x0
2316 OPC_Decode, 212, 5, 52, // 4461: decode to CRNOR using decoder 52
2317 // 4461: }
2318 4, 8, // 4465: case 0x4: {
2319 OPC_CheckField, 0, 1, 0, // 4467: check Inst[0] == 0x0
2320 OPC_Decode, 209, 5, 52, // 4471: decode to CRANDC using decoder 52
2321 // 4471: }
2322 6, 8, // 4475: case 0x6: {
2323 OPC_CheckField, 0, 1, 0, // 4477: check Inst[0] == 0x0
2324 OPC_Decode, 218, 5, 52, // 4481: decode to CRXOR using decoder 52
2325 // 4481: }
2326 7, 8, // 4485: case 0x7: {
2327 OPC_CheckField, 0, 1, 0, // 4487: check Inst[0] == 0x0
2328 OPC_Decode, 211, 5, 52, // 4491: decode to CRNAND using decoder 52
2329 // 4491: }
2330 8, 8, // 4495: case 0x8: {
2331 OPC_CheckField, 0, 1, 0, // 4497: check Inst[0] == 0x0
2332 OPC_Decode, 208, 5, 52, // 4501: decode to CRAND using decoder 52
2333 // 4501: }
2334 9, 8, // 4505: case 0x9: {
2335 OPC_CheckField, 0, 1, 0, // 4507: check Inst[0] == 0x0
2336 OPC_Decode, 210, 5, 52, // 4511: decode to CREQV using decoder 52
2337 // 4511: }
2338 13, 8, // 4515: case 0xd: {
2339 OPC_CheckField, 0, 1, 0, // 4517: check Inst[0] == 0x0
2340 OPC_Decode, 215, 5, 52, // 4521: decode to CRORC using decoder 52
2341 // 4521: }
2342 14, 0, // 4525: case 0xe: {
2343 OPC_CheckField, 0, 1, 0, // 4527: check Inst[0] == 0x0
2344 OPC_Decode, 214, 5, 52, // 4531: decode to CROR using decoder 52
2345 // 4531: }
2346 // 4531: } // switch Inst[10:6]
2347 // 4531: }
2348 2, 4, // 4535: case 0x2: {
2349 OPC_Decode, 223, 3, 53, // 4537: decode to ADDPCIS using decoder 53
2350 // 4537: }
2351 6, 12, // 4541: case 0x6: {
2352 OPC_CheckField, 6, 20, 1, // 4543: check Inst[25:6] == 0x1
2353 OPC_CheckField, 0, 1, 0, // 4547: check Inst[0] == 0x0
2354 OPC_Decode, 216, 14, 0, // 4551: decode to RFMCI using decoder 0
2355 // 4551: }
2356 7, 12, // 4555: case 0x7: {
2357 OPC_CheckField, 6, 20, 1, // 4557: check Inst[25:6] == 0x1
2358 OPC_CheckField, 0, 1, 0, // 4561: check Inst[0] == 0x0
2359 OPC_Decode, 212, 14, 0, // 4565: decode to RFDI using decoder 0
2360 // 4565: }
2361 16, 247, 1, // 4569: case 0x10: {
2362 OPC_SwitchField, 0, 1, // 4572: switch Inst[0] {
2363 0, 120, // 4575: case 0x0: {
2364 OPC_SwitchField, 6, 5, // 4577: switch Inst[10:6] {
2365 0, 90, // 4580: case 0x0: {
2366 OPC_CheckField, 13, 3, 0, // 4582: check Inst[15:13] == 0x0
2367 OPC_Scope, 80, // 4586: try {
2368 OPC_SwitchField, 16, 10, // 4588: switch Inst[25:16] {
2369 128, 4, 8, // 4591: case 0x200: {
2370 OPC_CheckField, 11, 2, 0, // 4594: check Inst[12:11] == 0x0
2371 OPC_Decode, 234, 4, 0, // 4598: decode to BDNZLR using decoder 0
2372 // 4598: }
2373 192, 4, 8, // 4602: case 0x240: {
2374 OPC_CheckField, 11, 2, 0, // 4605: check Inst[12:11] == 0x0
2375 OPC_Decode, 254, 4, 0, // 4609: decode to BDZLR using decoder 0
2376 // 4609: }
2377 128, 5, 8, // 4613: case 0x280: {
2378 OPC_CheckField, 11, 2, 0, // 4616: check Inst[12:11] == 0x0
2379 OPC_Decode, 154, 5, 0, // 4620: decode to BLR using decoder 0
2380 // 4620: }
2381 128, 6, 8, // 4624: case 0x300: {
2382 OPC_CheckField, 11, 2, 0, // 4627: check Inst[12:11] == 0x0
2383 OPC_Decode, 239, 4, 0, // 4631: decode to BDNZLRm using decoder 0
2384 // 4631: }
2385 160, 6, 8, // 4635: case 0x320: {
2386 OPC_CheckField, 11, 2, 0, // 4638: check Inst[12:11] == 0x0
2387 OPC_Decode, 240, 4, 0, // 4642: decode to BDNZLRp using decoder 0
2388 // 4642: }
2389 192, 6, 8, // 4646: case 0x340: {
2390 OPC_CheckField, 11, 2, 0, // 4649: check Inst[12:11] == 0x0
2391 OPC_Decode, 131, 5, 0, // 4653: decode to BDZLRm using decoder 0
2392 // 4653: }
2393 224, 6, 0, // 4657: case 0x360: {
2394 OPC_CheckField, 11, 2, 0, // 4660: check Inst[12:11] == 0x0
2395 OPC_Decode, 132, 5, 0, // 4664: decode to BDZLRp using decoder 0
2396 // 4664: }
2397 // 4664: } // switch Inst[25:16]
2398 // 4664: } else try {
2399 OPC_Decode, 181, 23, 54, // 4668: decode to gBCLR using decoder 54
2400 // 4668: }
2401 // 4668: }
2402 16, 0, // 4672: case 0x10: {
2403 OPC_CheckField, 13, 3, 0, // 4674: check Inst[15:13] == 0x0
2404 OPC_Scope, 13, // 4678: try {
2405 OPC_CheckField, 11, 2, 0, // 4680: check Inst[12:11] == 0x0
2406 OPC_CheckField, 16, 10, 128, 5, // 4684: check Inst[25:16] == 0x280
2407 OPC_Decode, 214, 4, 0, // 4689: decode to BCTR using decoder 0
2408 // 4689: } else try {
2409 OPC_Decode, 176, 23, 54, // 4693: decode to gBCCTR using decoder 54
2410 // 4693: }
2411 // 4693: }
2412 // 4693: } // switch Inst[10:6]
2413 // 4693: }
2414 1, 0, // 4697: case 0x1: {
2415 OPC_SwitchField, 6, 5, // 4699: switch Inst[10:6] {
2416 0, 90, // 4702: case 0x0: {
2417 OPC_CheckField, 13, 3, 0, // 4704: check Inst[15:13] == 0x0
2418 OPC_Scope, 80, // 4708: try {
2419 OPC_SwitchField, 16, 10, // 4710: switch Inst[25:16] {
2420 128, 4, 8, // 4713: case 0x200: {
2421 OPC_CheckField, 11, 2, 0, // 4716: check Inst[12:11] == 0x0
2422 OPC_Decode, 236, 4, 0, // 4720: decode to BDNZLRL using decoder 0
2423 // 4720: }
2424 192, 4, 8, // 4724: case 0x240: {
2425 OPC_CheckField, 11, 2, 0, // 4727: check Inst[12:11] == 0x0
2426 OPC_Decode, 128, 5, 0, // 4731: decode to BDZLRL using decoder 0
2427 // 4731: }
2428 128, 5, 8, // 4735: case 0x280: {
2429 OPC_CheckField, 11, 2, 0, // 4738: check Inst[12:11] == 0x0
2430 OPC_Decode, 156, 5, 0, // 4742: decode to BLRL using decoder 0
2431 // 4742: }
2432 128, 6, 8, // 4746: case 0x300: {
2433 OPC_CheckField, 11, 2, 0, // 4749: check Inst[12:11] == 0x0
2434 OPC_Decode, 237, 4, 0, // 4753: decode to BDNZLRLm using decoder 0
2435 // 4753: }
2436 160, 6, 8, // 4757: case 0x320: {
2437 OPC_CheckField, 11, 2, 0, // 4760: check Inst[12:11] == 0x0
2438 OPC_Decode, 238, 4, 0, // 4764: decode to BDNZLRLp using decoder 0
2439 // 4764: }
2440 192, 6, 8, // 4768: case 0x340: {
2441 OPC_CheckField, 11, 2, 0, // 4771: check Inst[12:11] == 0x0
2442 OPC_Decode, 129, 5, 0, // 4775: decode to BDZLRLm using decoder 0
2443 // 4775: }
2444 224, 6, 0, // 4779: case 0x360: {
2445 OPC_CheckField, 11, 2, 0, // 4782: check Inst[12:11] == 0x0
2446 OPC_Decode, 130, 5, 0, // 4786: decode to BDZLRLp using decoder 0
2447 // 4786: }
2448 // 4786: } // switch Inst[25:16]
2449 // 4786: } else try {
2450 OPC_Decode, 182, 23, 54, // 4790: decode to gBCLRL using decoder 54
2451 // 4790: }
2452 // 4790: }
2453 16, 0, // 4794: case 0x10: {
2454 OPC_CheckField, 13, 3, 0, // 4796: check Inst[15:13] == 0x0
2455 OPC_Scope, 13, // 4800: try {
2456 OPC_CheckField, 11, 2, 0, // 4802: check Inst[12:11] == 0x0
2457 OPC_CheckField, 16, 10, 128, 5, // 4806: check Inst[25:16] == 0x280
2458 OPC_Decode, 216, 4, 0, // 4811: decode to BCTRL using decoder 0
2459 // 4811: } else try {
2460 OPC_Decode, 177, 23, 54, // 4815: decode to gBCCTRL using decoder 54
2461 // 4815: }
2462 // 4815: }
2463 // 4815: } // switch Inst[10:6]
2464 // 4815: }
2465 // 4815: } // switch Inst[0]
2466 // 4815: }
2467 18, 87, // 4819: case 0x12: {
2468 OPC_SwitchField, 6, 5, // 4821: switch Inst[10:6] {
2469 0, 12, // 4824: case 0x0: {
2470 OPC_CheckField, 11, 15, 0, // 4826: check Inst[25:11] == 0x0
2471 OPC_CheckField, 0, 1, 0, // 4830: check Inst[0] == 0x0
2472 OPC_Decode, 215, 14, 0, // 4834: decode to RFID using decoder 0
2473 // 4834: }
2474 1, 12, // 4838: case 0x1: {
2475 OPC_CheckField, 11, 15, 0, // 4840: check Inst[25:11] == 0x0
2476 OPC_CheckField, 0, 1, 0, // 4844: check Inst[0] == 0x0
2477 OPC_Decode, 214, 14, 0, // 4848: decode to RFI using decoder 0
2478 // 4848: }
2479 4, 12, // 4852: case 0x4: {
2480 OPC_CheckField, 12, 14, 0, // 4854: check Inst[25:12] == 0x0
2481 OPC_CheckField, 0, 1, 0, // 4858: check Inst[0] == 0x0
2482 OPC_Decode, 213, 14, 55, // 4862: decode to RFEBB using decoder 55
2483 // 4862: }
2484 8, 12, // 4866: case 0x8: {
2485 OPC_CheckField, 11, 15, 0, // 4868: check Inst[25:11] == 0x0
2486 OPC_CheckField, 0, 1, 0, // 4872: check Inst[0] == 0x0
2487 OPC_Decode, 173, 10, 0, // 4876: decode to HRFID using decoder 0
2488 // 4876: }
2489 11, 12, // 4880: case 0xb: {
2490 OPC_CheckField, 11, 15, 0, // 4882: check Inst[25:11] == 0x0
2491 OPC_CheckField, 0, 1, 0, // 4886: check Inst[0] == 0x0
2492 OPC_Decode, 255, 15, 0, // 4890: decode to STOP using decoder 0
2493 // 4890: }
2494 13, 0, // 4894: case 0xd: {
2495 OPC_CheckField, 11, 15, 0, // 4896: check Inst[25:11] == 0x0
2496 OPC_CheckField, 0, 1, 0, // 4900: check Inst[0] == 0x0
2497 OPC_Decode, 207, 12, 0, // 4904: decode to NAP using decoder 0
2498 // 4904: }
2499 // 4904: } // switch Inst[10:6]
2500 // 4904: }
2501 19, 12, // 4908: case 0x13: {
2502 OPC_CheckField, 6, 20, 1, // 4910: check Inst[25:6] == 0x1
2503 OPC_CheckField, 0, 1, 0, // 4914: check Inst[0] == 0x0
2504 OPC_Decode, 211, 14, 0, // 4918: decode to RFCI using decoder 0
2505 // 4918: }
2506 22, 0, // 4922: case 0x16: {
2507 OPC_CheckField, 6, 20, 4, // 4924: check Inst[25:6] == 0x4
2508 OPC_CheckField, 0, 1, 0, // 4928: check Inst[0] == 0x0
2509 OPC_Decode, 183, 10, 0, // 4932: decode to ISYNC using decoder 0
2510 // 4932: }
2511 // 4932: } // switch Inst[5:1]
2512 // 4932: }
2513 20, 15, // 4936: case 0x14: {
2514 OPC_SwitchField, 0, 1, // 4938: switch Inst[0] {
2515 0, 4, // 4941: case 0x0: {
2516 OPC_Decode, 233, 14, 56, // 4943: decode to RLWIMI using decoder 56
2517 // 4943: }
2518 1, 0, // 4947: case 0x1: {
2519 OPC_Decode, 236, 14, 56, // 4949: decode to RLWIMI_rec using decoder 56
2520 // 4949: }
2521 // 4949: } // switch Inst[0]
2522 // 4949: }
2523 21, 15, // 4953: case 0x15: {
2524 OPC_SwitchField, 0, 1, // 4955: switch Inst[0] {
2525 0, 4, // 4958: case 0x0: {
2526 OPC_Decode, 237, 14, 57, // 4960: decode to RLWINM using decoder 57
2527 // 4960: }
2528 1, 0, // 4964: case 0x1: {
2529 OPC_Decode, 240, 14, 57, // 4966: decode to RLWINM_rec using decoder 57
2530 // 4966: }
2531 // 4966: } // switch Inst[0]
2532 // 4966: }
2533 23, 15, // 4970: case 0x17: {
2534 OPC_SwitchField, 0, 1, // 4972: switch Inst[0] {
2535 0, 4, // 4975: case 0x0: {
2536 OPC_Decode, 241, 14, 58, // 4977: decode to RLWNM using decoder 58
2537 // 4977: }
2538 1, 0, // 4981: case 0x1: {
2539 OPC_Decode, 244, 14, 58, // 4983: decode to RLWNM_rec using decoder 58
2540 // 4983: }
2541 // 4983: } // switch Inst[0]
2542 // 4983: }
2543 24, 14, // 4987: case 0x18: {
2544 OPC_Scope, 8, // 4989: try {
2545 OPC_CheckField, 0, 26, 0, // 4991: check Inst[25:0] == 0x0
2546 OPC_Decode, 216, 12, 0, // 4995: decode to NOP using decoder 0
2547 // 4995: } else try {
2548 OPC_Decode, 230, 12, 59, // 4999: decode to ORI using decoder 59
2549 // 4999: }
2550 // 4999: }
2551 25, 4, // 5003: case 0x19: {
2552 OPC_Decode, 232, 12, 59, // 5005: decode to ORIS using decoder 59
2553 // 5005: }
2554 26, 4, // 5009: case 0x1a: {
2555 OPC_Decode, 182, 20, 59, // 5011: decode to XORI using decoder 59
2556 // 5011: }
2557 27, 4, // 5015: case 0x1b: {
2558 OPC_Decode, 184, 20, 59, // 5017: decode to XORIS using decoder 59
2559 // 5017: }
2560 28, 4, // 5021: case 0x1c: {
2561 OPC_Decode, 244, 3, 59, // 5023: decode to ANDI_rec using decoder 59
2562 // 5023: }
2563 29, 4, // 5027: case 0x1d: {
2564 OPC_Decode, 243, 3, 59, // 5029: decode to ANDIS_rec using decoder 59
2565 // 5029: }
2566 30, 100, // 5033: case 0x1e: {
2567 OPC_SwitchField, 2, 3, // 5035: switch Inst[4:2] {
2568 0, 15, // 5038: case 0x0: {
2569 OPC_SwitchField, 0, 1, // 5040: switch Inst[0] {
2570 0, 4, // 5043: case 0x0: {
2571 OPC_Decode, 222, 14, 60, // 5045: decode to RLDICL using decoder 60
2572 // 5045: }
2573 1, 0, // 5049: case 0x1: {
2574 OPC_Decode, 226, 14, 60, // 5051: decode to RLDICL_rec using decoder 60
2575 // 5051: }
2576 // 5051: } // switch Inst[0]
2577 // 5051: }
2578 1, 15, // 5055: case 0x1: {
2579 OPC_SwitchField, 0, 1, // 5057: switch Inst[0] {
2580 0, 4, // 5060: case 0x0: {
2581 OPC_Decode, 227, 14, 60, // 5062: decode to RLDICR using decoder 60
2582 // 5062: }
2583 1, 0, // 5066: case 0x1: {
2584 OPC_Decode, 229, 14, 60, // 5068: decode to RLDICR_rec using decoder 60
2585 // 5068: }
2586 // 5068: } // switch Inst[0]
2587 // 5068: }
2588 2, 15, // 5072: case 0x2: {
2589 OPC_SwitchField, 0, 1, // 5074: switch Inst[0] {
2590 0, 4, // 5077: case 0x0: {
2591 OPC_Decode, 221, 14, 60, // 5079: decode to RLDIC using decoder 60
2592 // 5079: }
2593 1, 0, // 5083: case 0x1: {
2594 OPC_Decode, 230, 14, 60, // 5085: decode to RLDIC_rec using decoder 60
2595 // 5085: }
2596 // 5085: } // switch Inst[0]
2597 // 5085: }
2598 3, 15, // 5089: case 0x3: {
2599 OPC_SwitchField, 0, 1, // 5091: switch Inst[0] {
2600 0, 4, // 5094: case 0x0: {
2601 OPC_Decode, 231, 14, 61, // 5096: decode to RLDIMI using decoder 61
2602 // 5096: }
2603 1, 0, // 5100: case 0x1: {
2604 OPC_Decode, 232, 14, 61, // 5102: decode to RLDIMI_rec using decoder 61
2605 // 5102: }
2606 // 5102: } // switch Inst[0]
2607 // 5102: }
2608 4, 0, // 5106: case 0x4: {
2609 OPC_SwitchField, 0, 2, // 5108: switch Inst[1:0] {
2610 0, 4, // 5111: case 0x0: {
2611 OPC_Decode, 217, 14, 62, // 5113: decode to RLDCL using decoder 62
2612 // 5113: }
2613 1, 4, // 5117: case 0x1: {
2614 OPC_Decode, 218, 14, 62, // 5119: decode to RLDCL_rec using decoder 62
2615 // 5119: }
2616 2, 4, // 5123: case 0x2: {
2617 OPC_Decode, 219, 14, 62, // 5125: decode to RLDCR using decoder 62
2618 // 5125: }
2619 3, 0, // 5129: case 0x3: {
2620 OPC_Decode, 220, 14, 62, // 5131: decode to RLDCR_rec using decoder 62
2621 // 5131: }
2622 // 5131: } // switch Inst[1:0]
2623 // 5131: }
2624 // 5131: } // switch Inst[4:2]
2625 // 5131: }
2626 31, 229, 36, // 5135: case 0x1f: {
2627 OPC_SwitchField, 2, 4, // 5138: switch Inst[5:2] {
2628 0, 165, 1, // 5141: case 0x0: {
2629 OPC_SwitchField, 6, 5, // 5144: switch Inst[10:6] {
2630 0, 23, // 5147: case 0x0: {
2631 OPC_SwitchField, 21, 2, // 5149: switch Inst[22:21] {
2632 0, 8, // 5152: case 0x0: {
2633 OPC_CheckField, 0, 2, 0, // 5154: check Inst[1:0] == 0x0
2634 OPC_Decode, 185, 5, 63, // 5158: decode to CMPW using decoder 63
2635 // 5158: }
2636 1, 0, // 5162: case 0x1: {
2637 OPC_CheckField, 0, 2, 0, // 5164: check Inst[1:0] == 0x0
2638 OPC_Decode, 176, 5, 64, // 5168: decode to CMPD using decoder 64
2639 // 5168: }
2640 // 5168: } // switch Inst[22:21]
2641 // 5168: }
2642 1, 23, // 5172: case 0x1: {
2643 OPC_SwitchField, 21, 2, // 5174: switch Inst[22:21] {
2644 0, 8, // 5177: case 0x0: {
2645 OPC_CheckField, 0, 2, 0, // 5179: check Inst[1:0] == 0x0
2646 OPC_Decode, 181, 5, 63, // 5183: decode to CMPLW using decoder 63
2647 // 5183: }
2648 1, 0, // 5187: case 0x1: {
2649 OPC_CheckField, 0, 2, 0, // 5189: check Inst[1:0] == 0x0
2650 OPC_Decode, 179, 5, 64, // 5193: decode to CMPLD using decoder 64
2651 // 5193: }
2652 // 5193: } // switch Inst[22:21]
2653 // 5193: }
2654 4, 12, // 5197: case 0x4: {
2655 OPC_CheckField, 11, 7, 0, // 5199: check Inst[17:11] == 0x0
2656 OPC_CheckField, 0, 2, 0, // 5203: check Inst[1:0] == 0x0
2657 OPC_Decode, 142, 15, 65, // 5207: decode to SETB using decoder 65
2658 // 5207: }
2659 6, 12, // 5211: case 0x6: {
2660 OPC_CheckField, 22, 1, 0, // 5213: check Inst[22] == 0x0
2661 OPC_CheckField, 0, 2, 0, // 5217: check Inst[1:0] == 0x0
2662 OPC_Decode, 183, 5, 66, // 5221: decode to CMPRB using decoder 66
2663 // 5221: }
2664 7, 12, // 5225: case 0x7: {
2665 OPC_CheckField, 21, 2, 0, // 5227: check Inst[22:21] == 0x0
2666 OPC_CheckField, 0, 2, 0, // 5231: check Inst[1:0] == 0x0
2667 OPC_Decode, 178, 5, 64, // 5235: decode to CMPEQB using decoder 64
2668 // 5235: }
2669 12, 12, // 5239: case 0xc: {
2670 OPC_CheckField, 11, 5, 0, // 5241: check Inst[15:11] == 0x0
2671 OPC_CheckField, 0, 2, 0, // 5245: check Inst[1:0] == 0x0
2672 OPC_Decode, 144, 15, 67, // 5249: decode to SETBC using decoder 67
2673 // 5249: }
2674 13, 12, // 5253: case 0xd: {
2675 OPC_CheckField, 11, 5, 0, // 5255: check Inst[15:11] == 0x0
2676 OPC_CheckField, 0, 2, 0, // 5259: check Inst[1:0] == 0x0
2677 OPC_Decode, 146, 15, 67, // 5263: decode to SETBCR using decoder 67
2678 // 5263: }
2679 14, 12, // 5267: case 0xe: {
2680 OPC_CheckField, 11, 5, 0, // 5269: check Inst[15:11] == 0x0
2681 OPC_CheckField, 0, 2, 0, // 5273: check Inst[1:0] == 0x0
2682 OPC_Decode, 149, 15, 67, // 5277: decode to SETNBC using decoder 67
2683 // 5277: }
2684 15, 12, // 5281: case 0xf: {
2685 OPC_CheckField, 11, 5, 0, // 5283: check Inst[15:11] == 0x0
2686 OPC_CheckField, 0, 2, 0, // 5287: check Inst[1:0] == 0x0
2687 OPC_Decode, 151, 15, 67, // 5291: decode to SETNBCR using decoder 67
2688 // 5291: }
2689 18, 0, // 5295: case 0x12: {
2690 OPC_CheckField, 11, 12, 0, // 5297: check Inst[22:11] == 0x0
2691 OPC_CheckField, 0, 2, 0, // 5301: check Inst[1:0] == 0x0
2692 OPC_Decode, 220, 11, 68, // 5305: decode to MCRXRX using decoder 68
2693 // 5305: }
2694 // 5305: } // switch Inst[10:6]
2695 // 5305: }
2696 1, 47, // 5309: case 0x1: {
2697 OPC_SwitchField, 6, 5, // 5311: switch Inst[10:6] {
2698 4, 12, // 5314: case 0x4: {
2699 OPC_CheckField, 16, 1, 0, // 5316: check Inst[16] == 0x0
2700 OPC_CheckField, 1, 1, 1, // 5320: check Inst[1] == 0x1
2701 OPC_Decode, 177, 20, 69, // 5324: decode to WRTEE using decoder 69
2702 // 5324: }
2703 5, 8, // 5328: case 0x5: {
2704 OPC_CheckField, 1, 1, 1, // 5330: check Inst[1] == 0x1
2705 OPC_Decode, 178, 20, 70, // 5334: decode to WRTEEI using decoder 70
2706 // 5334: }
2707 10, 8, // 5338: case 0xa: {
2708 OPC_CheckField, 0, 2, 2, // 5340: check Inst[1:0] == 0x2
2709 OPC_Decode, 226, 11, 71, // 5344: decode to MFDCR using decoder 71
2710 // 5344: }
2711 14, 0, // 5348: case 0xe: {
2712 OPC_CheckField, 0, 2, 2, // 5350: check Inst[1:0] == 0x2
2713 OPC_Decode, 142, 12, 71, // 5354: decode to MTDCR using decoder 71
2714 // 5354: }
2715 // 5354: } // switch Inst[10:6]
2716 // 5354: }
2717 2, 35, // 5358: case 0x2: {
2718 OPC_SwitchField, 6, 5, // 5360: switch Inst[10:6] {
2719 0, 20, // 5363: case 0x0: {
2720 OPC_CheckField, 0, 2, 0, // 5365: check Inst[1:0] == 0x0
2721 OPC_Scope, 10, // 5369: try {
2722 OPC_CheckField, 11, 15, 128, 248, 1, // 5371: check Inst[25:11] == 0x7c00
2723 OPC_Decode, 148, 17, 0, // 5377: decode to TRAP using decoder 0
2724 // 5377: } else try {
2725 OPC_Decode, 152, 17, 72, // 5381: decode to TW using decoder 72
2726 // 5381: }
2727 // 5381: }
2728 2, 0, // 5385: case 0x2: {
2729 OPC_CheckField, 0, 2, 0, // 5387: check Inst[1:0] == 0x0
2730 OPC_Decode, 248, 16, 73, // 5391: decode to TD using decoder 73
2731 // 5391: }
2732 // 5391: } // switch Inst[10:6]
2733 // 5391: }
2734 3, 132, 2, // 5395: case 0x3: {
2735 OPC_SwitchField, 6, 5, // 5398: switch Inst[10:6] {
2736 0, 15, // 5401: case 0x0: {
2737 OPC_SwitchField, 0, 2, // 5403: switch Inst[1:0] {
2738 0, 4, // 5406: case 0x0: {
2739 OPC_Decode, 149, 11, 74, // 5408: decode to LVSL using decoder 74
2740 // 5408: }
2741 2, 0, // 5412: case 0x2: {
2742 OPC_Decode, 146, 11, 74, // 5414: decode to LVEBX using decoder 74
2743 // 5414: }
2744 // 5414: } // switch Inst[1:0]
2745 // 5414: }
2746 1, 15, // 5418: case 0x1: {
2747 OPC_SwitchField, 0, 2, // 5420: switch Inst[1:0] {
2748 0, 4, // 5423: case 0x0: {
2749 OPC_Decode, 150, 11, 74, // 5425: decode to LVSR using decoder 74
2750 // 5425: }
2751 2, 0, // 5429: case 0x2: {
2752 OPC_Decode, 147, 11, 74, // 5431: decode to LVEHX using decoder 74
2753 // 5431: }
2754 // 5431: } // switch Inst[1:0]
2755 // 5431: }
2756 2, 8, // 5435: case 0x2: {
2757 OPC_CheckField, 0, 2, 2, // 5437: check Inst[1:0] == 0x2
2758 OPC_Decode, 148, 11, 74, // 5441: decode to LVEWX using decoder 74
2759 // 5441: }
2760 3, 8, // 5445: case 0x3: {
2761 OPC_CheckField, 0, 2, 2, // 5447: check Inst[1:0] == 0x2
2762 OPC_Decode, 151, 11, 74, // 5451: decode to LVX using decoder 74
2763 // 5451: }
2764 4, 8, // 5455: case 0x4: {
2765 OPC_CheckField, 0, 2, 2, // 5457: check Inst[1:0] == 0x2
2766 OPC_Decode, 132, 16, 74, // 5461: decode to STVEBX using decoder 74
2767 // 5461: }
2768 5, 8, // 5465: case 0x5: {
2769 OPC_CheckField, 0, 2, 2, // 5467: check Inst[1:0] == 0x2
2770 OPC_Decode, 133, 16, 74, // 5471: decode to STVEHX using decoder 74
2771 // 5471: }
2772 6, 19, // 5475: case 0x6: {
2773 OPC_SwitchField, 0, 2, // 5477: switch Inst[1:0] {
2774 0, 8, // 5480: case 0x0: {
2775 OPC_CheckField, 25, 1, 0, // 5482: check Inst[25] == 0x0
2776 OPC_Decode, 177, 10, 75, // 5486: decode to ICBLQ using decoder 75
2777 // 5486: }
2778 2, 0, // 5490: case 0x2: {
2779 OPC_Decode, 134, 16, 74, // 5492: decode to STVEWX using decoder 74
2780 // 5492: }
2781 // 5492: } // switch Inst[1:0]
2782 // 5492: }
2783 7, 19, // 5496: case 0x7: {
2784 OPC_SwitchField, 0, 2, // 5498: switch Inst[1:0] {
2785 0, 8, // 5501: case 0x0: {
2786 OPC_CheckField, 25, 1, 0, // 5503: check Inst[25] == 0x0
2787 OPC_Decode, 176, 10, 75, // 5507: decode to ICBLC using decoder 75
2788 // 5507: }
2789 2, 0, // 5511: case 0x2: {
2790 OPC_Decode, 135, 16, 74, // 5513: decode to STVX using decoder 74
2791 // 5513: }
2792 // 5513: } // switch Inst[1:0]
2793 // 5513: }
2794 11, 8, // 5517: case 0xb: {
2795 OPC_CheckField, 0, 2, 2, // 5519: check Inst[1:0] == 0x2
2796 OPC_Decode, 152, 11, 74, // 5523: decode to LVXL using decoder 74
2797 // 5523: }
2798 14, 12, // 5527: case 0xe: {
2799 OPC_CheckField, 21, 5, 0, // 5529: check Inst[25:21] == 0x0
2800 OPC_CheckField, 0, 2, 0, // 5533: check Inst[1:0] == 0x0
2801 OPC_Decode, 239, 5, 76, // 5537: decode to DCCCI using decoder 76
2802 // 5537: }
2803 15, 19, // 5541: case 0xf: {
2804 OPC_SwitchField, 0, 2, // 5543: switch Inst[1:0] {
2805 0, 8, // 5546: case 0x0: {
2806 OPC_CheckField, 25, 1, 0, // 5548: check Inst[25] == 0x0
2807 OPC_Decode, 179, 10, 75, // 5552: decode to ICBTLS using decoder 75
2808 // 5552: }
2809 2, 0, // 5556: case 0x2: {
2810 OPC_Decode, 136, 16, 74, // 5558: decode to STVXL using decoder 74
2811 // 5558: }
2812 // 5558: } // switch Inst[1:0]
2813 // 5558: }
2814 18, 8, // 5562: case 0x12: {
2815 OPC_CheckField, 0, 2, 0, // 5564: check Inst[1:0] == 0x0
2816 OPC_Decode, 156, 11, 77, // 5568: decode to LWAT using decoder 77
2817 // 5568: }
2818 19, 8, // 5572: case 0x13: {
2819 OPC_CheckField, 0, 2, 0, // 5574: check Inst[1:0] == 0x0
2820 OPC_Decode, 204, 10, 77, // 5578: decode to LDAT using decoder 77
2821 // 5578: }
2822 22, 8, // 5582: case 0x16: {
2823 OPC_CheckField, 0, 2, 0, // 5584: check Inst[1:0] == 0x0
2824 OPC_Decode, 139, 16, 78, // 5588: decode to STWAT using decoder 78
2825 // 5588: }
2826 23, 8, // 5592: case 0x17: {
2827 OPC_CheckField, 0, 2, 0, // 5594: check Inst[1:0] == 0x0
2828 OPC_Decode, 216, 15, 79, // 5598: decode to STDAT using decoder 79
2829 // 5598: }
2830 24, 12, // 5602: case 0x18: {
2831 OPC_CheckField, 21, 5, 1, // 5604: check Inst[25:21] == 0x1
2832 OPC_CheckField, 0, 2, 0, // 5608: check Inst[1:0] == 0x0
2833 OPC_Decode, 202, 5, 76, // 5612: decode to CP_COPY using decoder 76
2834 // 5612: }
2835 26, 12, // 5616: case 0x1a: {
2836 OPC_CheckField, 11, 15, 0, // 5618: check Inst[25:11] == 0x0
2837 OPC_CheckField, 0, 2, 0, // 5622: check Inst[1:0] == 0x0
2838 OPC_Decode, 201, 5, 0, // 5626: decode to CP_ABORT using decoder 0
2839 // 5626: }
2840 28, 12, // 5630: case 0x1c: {
2841 OPC_CheckField, 22, 4, 0, // 5632: check Inst[25:22] == 0x0
2842 OPC_CheckField, 0, 2, 1, // 5636: check Inst[1:0] == 0x1
2843 OPC_Decode, 205, 5, 80, // 5640: decode to CP_PASTE_rec using decoder 80
2844 // 5640: }
2845 30, 0, // 5644: case 0x1e: {
2846 OPC_CheckField, 21, 5, 0, // 5646: check Inst[25:21] == 0x0
2847 OPC_CheckField, 0, 2, 0, // 5650: check Inst[1:0] == 0x0
2848 OPC_Decode, 180, 10, 76, // 5654: decode to ICCCI using decoder 76
2849 // 5654: }
2850 // 5654: } // switch Inst[10:6]
2851 // 5654: }
2852 4, 253, 3, // 5658: case 0x4: {
2853 OPC_SwitchField, 6, 4, // 5661: switch Inst[9:6] {
2854 0, 57, // 5664: case 0x0: {
2855 OPC_SwitchField, 0, 2, // 5666: switch Inst[1:0] {
2856 0, 15, // 5669: case 0x0: {
2857 OPC_SwitchField, 10, 1, // 5671: switch Inst[10] {
2858 0, 4, // 5674: case 0x0: {
2859 OPC_Decode, 186, 16, 81, // 5676: decode to SUBFC using decoder 81
2860 // 5676: }
2861 1, 0, // 5680: case 0x1: {
2862 OPC_Decode, 191, 16, 81, // 5682: decode to SUBFCO using decoder 81
2863 // 5682: }
2864 // 5682: } // switch Inst[10]
2865 // 5682: }
2866 1, 15, // 5686: case 0x1: {
2867 OPC_SwitchField, 10, 1, // 5688: switch Inst[10] {
2868 0, 4, // 5691: case 0x0: {
2869 OPC_Decode, 193, 16, 81, // 5693: decode to SUBFC_rec using decoder 81
2870 // 5693: }
2871 1, 0, // 5697: case 0x1: {
2872 OPC_Decode, 192, 16, 81, // 5699: decode to SUBFCO_rec using decoder 81
2873 // 5699: }
2874 // 5699: } // switch Inst[10]
2875 // 5699: }
2876 2, 8, // 5703: case 0x2: {
2877 OPC_CheckField, 10, 1, 0, // 5705: check Inst[10] == 0x0
2878 OPC_Decode, 183, 12, 82, // 5709: decode to MULHDU using decoder 82
2879 // 5709: }
2880 3, 0, // 5713: case 0x3: {
2881 OPC_CheckField, 10, 1, 0, // 5715: check Inst[10] == 0x0
2882 OPC_Decode, 184, 12, 82, // 5719: decode to MULHDU_rec using decoder 82
2883 // 5719: }
2884 // 5719: } // switch Inst[1:0]
2885 // 5719: }
2886 1, 37, // 5723: case 0x1: {
2887 OPC_SwitchField, 0, 2, // 5725: switch Inst[1:0] {
2888 0, 15, // 5728: case 0x0: {
2889 OPC_SwitchField, 10, 1, // 5730: switch Inst[10] {
2890 0, 4, // 5733: case 0x0: {
2891 OPC_Decode, 181, 16, 81, // 5735: decode to SUBF using decoder 81
2892 // 5735: }
2893 1, 0, // 5739: case 0x1: {
2894 OPC_Decode, 212, 16, 81, // 5741: decode to SUBFO using decoder 81
2895 // 5741: }
2896 // 5741: } // switch Inst[10]
2897 // 5741: }
2898 1, 0, // 5745: case 0x1: {
2899 OPC_SwitchField, 10, 1, // 5747: switch Inst[10] {
2900 0, 4, // 5750: case 0x0: {
2901 OPC_Decode, 224, 16, 81, // 5752: decode to SUBF_rec using decoder 81
2902 // 5752: }
2903 1, 0, // 5756: case 0x1: {
2904 OPC_Decode, 213, 16, 81, // 5758: decode to SUBFO_rec using decoder 81
2905 // 5758: }
2906 // 5758: } // switch Inst[10]
2907 // 5758: }
2908 // 5758: } // switch Inst[1:0]
2909 // 5758: }
2910 2, 35, // 5762: case 0x2: {
2911 OPC_SwitchField, 0, 2, // 5764: switch Inst[1:0] {
2912 0, 4, // 5767: case 0x0: {
2913 OPC_Decode, 214, 16, 83, // 5769: decode to SUBFUS using decoder 83
2914 // 5769: }
2915 1, 4, // 5773: case 0x1: {
2916 OPC_Decode, 215, 16, 83, // 5775: decode to SUBFUS_rec using decoder 83
2917 // 5775: }
2918 2, 8, // 5779: case 0x2: {
2919 OPC_CheckField, 10, 1, 0, // 5781: check Inst[10] == 0x0
2920 OPC_Decode, 182, 12, 82, // 5785: decode to MULHD using decoder 82
2921 // 5785: }
2922 3, 0, // 5789: case 0x3: {
2923 OPC_CheckField, 10, 1, 0, // 5791: check Inst[10] == 0x0
2924 OPC_Decode, 185, 12, 82, // 5795: decode to MULHD_rec using decoder 82
2925 // 5795: }
2926 // 5795: } // switch Inst[1:0]
2927 // 5795: }
2928 3, 37, // 5799: case 0x3: {
2929 OPC_SwitchField, 0, 2, // 5801: switch Inst[1:0] {
2930 0, 15, // 5804: case 0x0: {
2931 OPC_SwitchField, 10, 6, // 5806: switch Inst[15:10] {
2932 0, 4, // 5809: case 0x0: {
2933 OPC_Decode, 208, 12, 84, // 5811: decode to NEG using decoder 84
2934 // 5811: }
2935 1, 0, // 5815: case 0x1: {
2936 OPC_Decode, 213, 12, 84, // 5817: decode to NEGO using decoder 84
2937 // 5817: }
2938 // 5817: } // switch Inst[15:10]
2939 // 5817: }
2940 1, 0, // 5821: case 0x1: {
2941 OPC_SwitchField, 10, 6, // 5823: switch Inst[15:10] {
2942 0, 4, // 5826: case 0x0: {
2943 OPC_Decode, 215, 12, 84, // 5828: decode to NEG_rec using decoder 84
2944 // 5828: }
2945 1, 0, // 5832: case 0x1: {
2946 OPC_Decode, 214, 12, 84, // 5834: decode to NEGO_rec using decoder 84
2947 // 5834: }
2948 // 5834: } // switch Inst[15:10]
2949 // 5834: }
2950 // 5834: } // switch Inst[1:0]
2951 // 5834: }
2952 4, 37, // 5838: case 0x4: {
2953 OPC_SwitchField, 0, 2, // 5840: switch Inst[1:0] {
2954 0, 15, // 5843: case 0x0: {
2955 OPC_SwitchField, 10, 1, // 5845: switch Inst[10] {
2956 0, 4, // 5848: case 0x0: {
2957 OPC_Decode, 194, 16, 81, // 5850: decode to SUBFE using decoder 81
2958 // 5850: }
2959 1, 0, // 5854: case 0x1: {
2960 OPC_Decode, 199, 16, 81, // 5856: decode to SUBFEO using decoder 81
2961 // 5856: }
2962 // 5856: } // switch Inst[10]
2963 // 5856: }
2964 1, 0, // 5860: case 0x1: {
2965 OPC_SwitchField, 10, 1, // 5862: switch Inst[10] {
2966 0, 4, // 5865: case 0x0: {
2967 OPC_Decode, 201, 16, 81, // 5867: decode to SUBFE_rec using decoder 81
2968 // 5867: }
2969 1, 0, // 5871: case 0x1: {
2970 OPC_Decode, 200, 16, 81, // 5873: decode to SUBFEO_rec using decoder 81
2971 // 5873: }
2972 // 5873: } // switch Inst[10]
2973 // 5873: }
2974 // 5873: } // switch Inst[1:0]
2975 // 5873: }
2976 6, 37, // 5877: case 0x6: {
2977 OPC_SwitchField, 0, 2, // 5879: switch Inst[1:0] {
2978 0, 15, // 5882: case 0x0: {
2979 OPC_SwitchField, 10, 6, // 5884: switch Inst[15:10] {
2980 0, 4, // 5887: case 0x0: {
2981 OPC_Decode, 216, 16, 84, // 5889: decode to SUBFZE using decoder 84
2982 // 5889: }
2983 1, 0, // 5893: case 0x1: {
2984 OPC_Decode, 221, 16, 84, // 5895: decode to SUBFZEO using decoder 84
2985 // 5895: }
2986 // 5895: } // switch Inst[15:10]
2987 // 5895: }
2988 1, 0, // 5899: case 0x1: {
2989 OPC_SwitchField, 10, 6, // 5901: switch Inst[15:10] {
2990 0, 4, // 5904: case 0x0: {
2991 OPC_Decode, 223, 16, 84, // 5906: decode to SUBFZE_rec using decoder 84
2992 // 5906: }
2993 1, 0, // 5910: case 0x1: {
2994 OPC_Decode, 222, 16, 84, // 5912: decode to SUBFZEO_rec using decoder 84
2995 // 5912: }
2996 // 5912: } // switch Inst[15:10]
2997 // 5912: }
2998 // 5912: } // switch Inst[1:0]
2999 // 5912: }
3000 7, 71, // 5916: case 0x7: {
3001 OPC_SwitchField, 0, 2, // 5918: switch Inst[1:0] {
3002 0, 15, // 5921: case 0x0: {
3003 OPC_SwitchField, 10, 6, // 5923: switch Inst[15:10] {
3004 0, 4, // 5926: case 0x0: {
3005 OPC_Decode, 204, 16, 84, // 5928: decode to SUBFME using decoder 84
3006 // 5928: }
3007 1, 0, // 5932: case 0x1: {
3008 OPC_Decode, 209, 16, 84, // 5934: decode to SUBFMEO using decoder 84
3009 // 5934: }
3010 // 5934: } // switch Inst[15:10]
3011 // 5934: }
3012 1, 15, // 5938: case 0x1: {
3013 OPC_SwitchField, 10, 6, // 5940: switch Inst[15:10] {
3014 0, 4, // 5943: case 0x0: {
3015 OPC_Decode, 211, 16, 84, // 5945: decode to SUBFME_rec using decoder 84
3016 // 5945: }
3017 1, 0, // 5949: case 0x1: {
3018 OPC_Decode, 210, 16, 84, // 5951: decode to SUBFMEO_rec using decoder 84
3019 // 5951: }
3020 // 5951: } // switch Inst[15:10]
3021 // 5951: }
3022 2, 15, // 5955: case 0x2: {
3023 OPC_SwitchField, 10, 1, // 5957: switch Inst[10] {
3024 0, 4, // 5960: case 0x0: {
3025 OPC_Decode, 190, 12, 82, // 5962: decode to MULLD using decoder 82
3026 // 5962: }
3027 1, 0, // 5966: case 0x1: {
3028 OPC_Decode, 191, 12, 82, // 5968: decode to MULLDO using decoder 82
3029 // 5968: }
3030 // 5968: } // switch Inst[10]
3031 // 5968: }
3032 3, 0, // 5972: case 0x3: {
3033 OPC_SwitchField, 10, 1, // 5974: switch Inst[10] {
3034 0, 4, // 5977: case 0x0: {
3035 OPC_Decode, 193, 12, 82, // 5979: decode to MULLD_rec using decoder 82
3036 // 5979: }
3037 1, 0, // 5983: case 0x1: {
3038 OPC_Decode, 192, 12, 82, // 5985: decode to MULLDO_rec using decoder 82
3039 // 5985: }
3040 // 5985: } // switch Inst[10]
3041 // 5985: }
3042 // 5985: } // switch Inst[1:0]
3043 // 5985: }
3044 8, 23, // 5989: case 0x8: {
3045 OPC_SwitchField, 10, 1, // 5991: switch Inst[10] {
3046 0, 8, // 5994: case 0x0: {
3047 OPC_CheckField, 0, 2, 2, // 5996: check Inst[1:0] == 0x2
3048 OPC_Decode, 130, 12, 82, // 6000: decode to MODUD using decoder 82
3049 // 6000: }
3050 1, 0, // 6004: case 0x1: {
3051 OPC_CheckField, 0, 2, 2, // 6006: check Inst[1:0] == 0x2
3052 OPC_Decode, 128, 12, 82, // 6010: decode to MODSD using decoder 82
3053 // 6010: }
3054 // 6010: } // switch Inst[10]
3055 // 6010: }
3056 12, 37, // 6014: case 0xc: {
3057 OPC_SwitchField, 0, 2, // 6016: switch Inst[1:0] {
3058 2, 15, // 6019: case 0x2: {
3059 OPC_SwitchField, 10, 1, // 6021: switch Inst[10] {
3060 0, 4, // 6024: case 0x0: {
3061 OPC_Decode, 150, 6, 82, // 6026: decode to DIVDEU using decoder 82
3062 // 6026: }
3063 1, 0, // 6030: case 0x1: {
3064 OPC_Decode, 151, 6, 82, // 6032: decode to DIVDEUO using decoder 82
3065 // 6032: }
3066 // 6032: } // switch Inst[10]
3067 // 6032: }
3068 3, 0, // 6036: case 0x3: {
3069 OPC_SwitchField, 10, 1, // 6038: switch Inst[10] {
3070 0, 4, // 6041: case 0x0: {
3071 OPC_Decode, 153, 6, 82, // 6043: decode to DIVDEU_rec using decoder 82
3072 // 6043: }
3073 1, 0, // 6047: case 0x1: {
3074 OPC_Decode, 152, 6, 82, // 6049: decode to DIVDEUO_rec using decoder 82
3075 // 6049: }
3076 // 6049: } // switch Inst[10]
3077 // 6049: }
3078 // 6049: } // switch Inst[1:0]
3079 // 6049: }
3080 13, 37, // 6053: case 0xd: {
3081 OPC_SwitchField, 0, 2, // 6055: switch Inst[1:0] {
3082 2, 15, // 6058: case 0x2: {
3083 OPC_SwitchField, 10, 1, // 6060: switch Inst[10] {
3084 0, 4, // 6063: case 0x0: {
3085 OPC_Decode, 147, 6, 82, // 6065: decode to DIVDE using decoder 82
3086 // 6065: }
3087 1, 0, // 6069: case 0x1: {
3088 OPC_Decode, 148, 6, 82, // 6071: decode to DIVDEO using decoder 82
3089 // 6071: }
3090 // 6071: } // switch Inst[10]
3091 // 6071: }
3092 3, 0, // 6075: case 0x3: {
3093 OPC_SwitchField, 10, 1, // 6077: switch Inst[10] {
3094 0, 4, // 6080: case 0x0: {
3095 OPC_Decode, 154, 6, 82, // 6082: decode to DIVDE_rec using decoder 82
3096 // 6082: }
3097 1, 0, // 6086: case 0x1: {
3098 OPC_Decode, 149, 6, 82, // 6088: decode to DIVDEO_rec using decoder 82
3099 // 6088: }
3100 // 6088: } // switch Inst[10]
3101 // 6088: }
3102 // 6088: } // switch Inst[1:0]
3103 // 6088: }
3104 14, 37, // 6092: case 0xe: {
3105 OPC_SwitchField, 0, 2, // 6094: switch Inst[1:0] {
3106 2, 15, // 6097: case 0x2: {
3107 OPC_SwitchField, 10, 1, // 6099: switch Inst[10] {
3108 0, 4, // 6102: case 0x0: {
3109 OPC_Decode, 157, 6, 82, // 6104: decode to DIVDU using decoder 82
3110 // 6104: }
3111 1, 0, // 6108: case 0x1: {
3112 OPC_Decode, 158, 6, 82, // 6110: decode to DIVDUO using decoder 82
3113 // 6110: }
3114 // 6110: } // switch Inst[10]
3115 // 6110: }
3116 3, 0, // 6114: case 0x3: {
3117 OPC_SwitchField, 10, 1, // 6116: switch Inst[10] {
3118 0, 4, // 6119: case 0x0: {
3119 OPC_Decode, 160, 6, 82, // 6121: decode to DIVDU_rec using decoder 82
3120 // 6121: }
3121 1, 0, // 6125: case 0x1: {
3122 OPC_Decode, 159, 6, 82, // 6127: decode to DIVDUO_rec using decoder 82
3123 // 6127: }
3124 // 6127: } // switch Inst[10]
3125 // 6127: }
3126 // 6127: } // switch Inst[1:0]
3127 // 6127: }
3128 15, 0, // 6131: case 0xf: {
3129 OPC_SwitchField, 0, 2, // 6133: switch Inst[1:0] {
3130 2, 15, // 6136: case 0x2: {
3131 OPC_SwitchField, 10, 1, // 6138: switch Inst[10] {
3132 0, 4, // 6141: case 0x0: {
3133 OPC_Decode, 146, 6, 82, // 6143: decode to DIVD using decoder 82
3134 // 6143: }
3135 1, 0, // 6147: case 0x1: {
3136 OPC_Decode, 155, 6, 82, // 6149: decode to DIVDO using decoder 82
3137 // 6149: }
3138 // 6149: } // switch Inst[10]
3139 // 6149: }
3140 3, 0, // 6153: case 0x3: {
3141 OPC_SwitchField, 10, 1, // 6155: switch Inst[10] {
3142 0, 4, // 6158: case 0x0: {
3143 OPC_Decode, 161, 6, 82, // 6160: decode to DIVD_rec using decoder 82
3144 // 6160: }
3145 1, 0, // 6164: case 0x1: {
3146 OPC_Decode, 156, 6, 82, // 6166: decode to DIVDO_rec using decoder 82
3147 // 6166: }
3148 // 6166: } // switch Inst[10]
3149 // 6166: }
3150 // 6166: } // switch Inst[1:0]
3151 // 6166: }
3152 // 6166: } // switch Inst[9:6]
3153 // 6166: }
3154 5, 166, 3, // 6170: case 0x5: {
3155 OPC_SwitchField, 6, 3, // 6173: switch Inst[8:6] {
3156 0, 94, // 6176: case 0x0: {
3157 OPC_SwitchField, 0, 2, // 6178: switch Inst[1:0] {
3158 0, 27, // 6181: case 0x0: {
3159 OPC_SwitchField, 9, 2, // 6183: switch Inst[10:9] {
3160 0, 4, // 6186: case 0x0: {
3161 OPC_Decode, 167, 3, 81, // 6188: decode to ADDC using decoder 81
3162 // 6188: }
3163 1, 4, // 6192: case 0x1: {
3164 OPC_Decode, 156, 3, 81, // 6194: decode to ADD4 using decoder 81
3165 // 6194: }
3166 2, 4, // 6198: case 0x2: {
3167 OPC_Decode, 172, 3, 81, // 6200: decode to ADDCO using decoder 81
3168 // 6200: }
3169 3, 0, // 6204: case 0x3: {
3170 OPC_Decode, 157, 3, 81, // 6206: decode to ADD4O using decoder 81
3171 // 6206: }
3172 // 6206: } // switch Inst[10:9]
3173 // 6206: }
3174 1, 27, // 6210: case 0x1: {
3175 OPC_SwitchField, 9, 2, // 6212: switch Inst[10:9] {
3176 0, 4, // 6215: case 0x0: {
3177 OPC_Decode, 174, 3, 81, // 6217: decode to ADDC_rec using decoder 81
3178 // 6217: }
3179 1, 4, // 6221: case 0x1: {
3180 OPC_Decode, 160, 3, 81, // 6223: decode to ADD4_rec using decoder 81
3181 // 6223: }
3182 2, 4, // 6227: case 0x2: {
3183 OPC_Decode, 173, 3, 81, // 6229: decode to ADDCO_rec using decoder 81
3184 // 6229: }
3185 3, 0, // 6233: case 0x3: {
3186 OPC_Decode, 158, 3, 81, // 6235: decode to ADD4O_rec using decoder 81
3187 // 6235: }
3188 // 6235: } // switch Inst[10:9]
3189 // 6235: }
3190 2, 21, // 6239: case 0x2: {
3191 OPC_SwitchField, 9, 2, // 6241: switch Inst[10:9] {
3192 0, 4, // 6244: case 0x0: {
3193 OPC_Decode, 187, 12, 81, // 6246: decode to MULHWU using decoder 81
3194 // 6246: }
3195 1, 4, // 6250: case 0x1: {
3196 OPC_Decode, 131, 12, 81, // 6252: decode to MODUW using decoder 81
3197 // 6252: }
3198 3, 0, // 6256: case 0x3: {
3199 OPC_Decode, 129, 12, 81, // 6258: decode to MODSW using decoder 81
3200 // 6258: }
3201 // 6258: } // switch Inst[10:9]
3202 // 6258: }
3203 3, 0, // 6262: case 0x3: {
3204 OPC_CheckField, 9, 2, 0, // 6264: check Inst[10:9] == 0x0
3205 OPC_Decode, 188, 12, 81, // 6268: decode to MULHWU_rec using decoder 81
3206 // 6268: }
3207 // 6268: } // switch Inst[1:0]
3208 // 6268: }
3209 2, 33, // 6272: case 0x2: {
3210 OPC_SwitchField, 0, 2, // 6274: switch Inst[1:0] {
3211 0, 8, // 6277: case 0x0: {
3212 OPC_CheckField, 9, 2, 0, // 6279: check Inst[10:9] == 0x0
3213 OPC_Decode, 185, 3, 81, // 6283: decode to ADDG6S using decoder 81
3214 // 6283: }
3215 2, 8, // 6287: case 0x2: {
3216 OPC_CheckField, 9, 2, 0, // 6289: check Inst[10:9] == 0x0
3217 OPC_Decode, 186, 12, 81, // 6293: decode to MULHW using decoder 81
3218 // 6293: }
3219 3, 0, // 6297: case 0x3: {
3220 OPC_CheckField, 9, 2, 0, // 6299: check Inst[10:9] == 0x0
3221 OPC_Decode, 189, 12, 81, // 6303: decode to MULHW_rec using decoder 81
3222 // 6303: }
3223 // 6303: } // switch Inst[1:0]
3224 // 6303: }
3225 4, 71, // 6307: case 0x4: {
3226 OPC_SwitchField, 0, 2, // 6309: switch Inst[1:0] {
3227 0, 15, // 6312: case 0x0: {
3228 OPC_SwitchField, 9, 2, // 6314: switch Inst[10:9] {
3229 0, 4, // 6317: case 0x0: {
3230 OPC_Decode, 175, 3, 81, // 6319: decode to ADDE using decoder 81
3231 // 6319: }
3232 2, 0, // 6323: case 0x2: {
3233 OPC_Decode, 180, 3, 81, // 6325: decode to ADDEO using decoder 81
3234 // 6325: }
3235 // 6325: } // switch Inst[10:9]
3236 // 6325: }
3237 1, 15, // 6329: case 0x1: {
3238 OPC_SwitchField, 9, 2, // 6331: switch Inst[10:9] {
3239 0, 4, // 6334: case 0x0: {
3240 OPC_Decode, 184, 3, 81, // 6336: decode to ADDE_rec using decoder 81
3241 // 6336: }
3242 2, 0, // 6340: case 0x2: {
3243 OPC_Decode, 181, 3, 81, // 6342: decode to ADDEO_rec using decoder 81
3244 // 6342: }
3245 // 6342: } // switch Inst[10:9]
3246 // 6342: }
3247 2, 15, // 6346: case 0x2: {
3248 OPC_SwitchField, 9, 2, // 6348: switch Inst[10:9] {
3249 1, 4, // 6351: case 0x1: {
3250 OPC_Decode, 166, 6, 81, // 6353: decode to DIVWEU using decoder 81
3251 // 6353: }
3252 3, 0, // 6357: case 0x3: {
3253 OPC_Decode, 167, 6, 81, // 6359: decode to DIVWEUO using decoder 81
3254 // 6359: }
3255 // 6359: } // switch Inst[10:9]
3256 // 6359: }
3257 3, 0, // 6363: case 0x3: {
3258 OPC_SwitchField, 9, 2, // 6365: switch Inst[10:9] {
3259 1, 4, // 6368: case 0x1: {
3260 OPC_Decode, 169, 6, 81, // 6370: decode to DIVWEU_rec using decoder 81
3261 // 6370: }
3262 3, 0, // 6374: case 0x3: {
3263 OPC_Decode, 168, 6, 81, // 6376: decode to DIVWEUO_rec using decoder 81
3264 // 6376: }
3265 // 6376: } // switch Inst[10:9]
3266 // 6376: }
3267 // 6376: } // switch Inst[1:0]
3268 // 6376: }
3269 5, 43, // 6380: case 0x5: {
3270 OPC_SwitchField, 0, 2, // 6382: switch Inst[1:0] {
3271 0, 4, // 6385: case 0x0: {
3272 OPC_Decode, 182, 3, 85, // 6387: decode to ADDEX using decoder 85
3273 // 6387: }
3274 2, 15, // 6391: case 0x2: {
3275 OPC_SwitchField, 9, 2, // 6393: switch Inst[10:9] {
3276 1, 4, // 6396: case 0x1: {
3277 OPC_Decode, 163, 6, 81, // 6398: decode to DIVWE using decoder 81
3278 // 6398: }
3279 3, 0, // 6402: case 0x3: {
3280 OPC_Decode, 164, 6, 81, // 6404: decode to DIVWEO using decoder 81
3281 // 6404: }
3282 // 6404: } // switch Inst[10:9]
3283 // 6404: }
3284 3, 0, // 6408: case 0x3: {
3285 OPC_SwitchField, 9, 2, // 6410: switch Inst[10:9] {
3286 1, 4, // 6413: case 0x1: {
3287 OPC_Decode, 170, 6, 81, // 6415: decode to DIVWE_rec using decoder 81
3288 // 6415: }
3289 3, 0, // 6419: case 0x3: {
3290 OPC_Decode, 165, 6, 81, // 6421: decode to DIVWEO_rec using decoder 81
3291 // 6421: }
3292 // 6421: } // switch Inst[10:9]
3293 // 6421: }
3294 // 6421: } // switch Inst[1:0]
3295 // 6421: }
3296 6, 71, // 6425: case 0x6: {
3297 OPC_SwitchField, 0, 2, // 6427: switch Inst[1:0] {
3298 0, 15, // 6430: case 0x0: {
3299 OPC_SwitchField, 9, 7, // 6432: switch Inst[15:9] {
3300 0, 4, // 6435: case 0x0: {
3301 OPC_Decode, 224, 3, 84, // 6437: decode to ADDZE using decoder 84
3302 // 6437: }
3303 2, 0, // 6441: case 0x2: {
3304 OPC_Decode, 229, 3, 84, // 6443: decode to ADDZEO using decoder 84
3305 // 6443: }
3306 // 6443: } // switch Inst[15:9]
3307 // 6443: }
3308 1, 15, // 6447: case 0x1: {
3309 OPC_SwitchField, 9, 7, // 6449: switch Inst[15:9] {
3310 0, 4, // 6452: case 0x0: {
3311 OPC_Decode, 231, 3, 84, // 6454: decode to ADDZE_rec using decoder 84
3312 // 6454: }
3313 2, 0, // 6458: case 0x2: {
3314 OPC_Decode, 230, 3, 84, // 6460: decode to ADDZEO_rec using decoder 84
3315 // 6460: }
3316 // 6460: } // switch Inst[15:9]
3317 // 6460: }
3318 2, 15, // 6464: case 0x2: {
3319 OPC_SwitchField, 9, 2, // 6466: switch Inst[10:9] {
3320 1, 4, // 6469: case 0x1: {
3321 OPC_Decode, 173, 6, 81, // 6471: decode to DIVWU using decoder 81
3322 // 6471: }
3323 3, 0, // 6475: case 0x3: {
3324 OPC_Decode, 174, 6, 81, // 6477: decode to DIVWUO using decoder 81
3325 // 6477: }
3326 // 6477: } // switch Inst[10:9]
3327 // 6477: }
3328 3, 0, // 6481: case 0x3: {
3329 OPC_SwitchField, 9, 2, // 6483: switch Inst[10:9] {
3330 1, 4, // 6486: case 0x1: {
3331 OPC_Decode, 176, 6, 81, // 6488: decode to DIVWU_rec using decoder 81
3332 // 6488: }
3333 3, 0, // 6492: case 0x3: {
3334 OPC_Decode, 175, 6, 81, // 6494: decode to DIVWUO_rec using decoder 81
3335 // 6494: }
3336 // 6494: } // switch Inst[10:9]
3337 // 6494: }
3338 // 6494: } // switch Inst[1:0]
3339 // 6494: }
3340 7, 0, // 6498: case 0x7: {
3341 OPC_SwitchField, 0, 2, // 6500: switch Inst[1:0] {
3342 0, 15, // 6503: case 0x0: {
3343 OPC_SwitchField, 9, 7, // 6505: switch Inst[15:9] {
3344 0, 4, // 6508: case 0x0: {
3345 OPC_Decode, 215, 3, 84, // 6510: decode to ADDME using decoder 84
3346 // 6510: }
3347 2, 0, // 6514: case 0x2: {
3348 OPC_Decode, 220, 3, 84, // 6516: decode to ADDMEO using decoder 84
3349 // 6516: }
3350 // 6516: } // switch Inst[15:9]
3351 // 6516: }
3352 1, 15, // 6520: case 0x1: {
3353 OPC_SwitchField, 9, 7, // 6522: switch Inst[15:9] {
3354 0, 4, // 6525: case 0x0: {
3355 OPC_Decode, 222, 3, 84, // 6527: decode to ADDME_rec using decoder 84
3356 // 6527: }
3357 2, 0, // 6531: case 0x2: {
3358 OPC_Decode, 221, 3, 84, // 6533: decode to ADDMEO_rec using decoder 84
3359 // 6533: }
3360 // 6533: } // switch Inst[15:9]
3361 // 6533: }
3362 2, 27, // 6537: case 0x2: {
3363 OPC_SwitchField, 9, 2, // 6539: switch Inst[10:9] {
3364 0, 4, // 6542: case 0x0: {
3365 OPC_Decode, 196, 12, 81, // 6544: decode to MULLW using decoder 81
3366 // 6544: }
3367 1, 4, // 6548: case 0x1: {
3368 OPC_Decode, 162, 6, 81, // 6550: decode to DIVW using decoder 81
3369 // 6550: }
3370 2, 4, // 6554: case 0x2: {
3371 OPC_Decode, 197, 12, 81, // 6556: decode to MULLWO using decoder 81
3372 // 6556: }
3373 3, 0, // 6560: case 0x3: {
3374 OPC_Decode, 171, 6, 81, // 6562: decode to DIVWO using decoder 81
3375 // 6562: }
3376 // 6562: } // switch Inst[10:9]
3377 // 6562: }
3378 3, 0, // 6566: case 0x3: {
3379 OPC_SwitchField, 9, 2, // 6568: switch Inst[10:9] {
3380 0, 4, // 6571: case 0x0: {
3381 OPC_Decode, 199, 12, 81, // 6573: decode to MULLW_rec using decoder 81
3382 // 6573: }
3383 1, 4, // 6577: case 0x1: {
3384 OPC_Decode, 177, 6, 81, // 6579: decode to DIVW_rec using decoder 81
3385 // 6579: }
3386 2, 4, // 6583: case 0x2: {
3387 OPC_Decode, 198, 12, 81, // 6585: decode to MULLWO_rec using decoder 81
3388 // 6585: }
3389 3, 0, // 6589: case 0x3: {
3390 OPC_Decode, 172, 6, 81, // 6591: decode to DIVWO_rec using decoder 81
3391 // 6591: }
3392 // 6591: } // switch Inst[10:9]
3393 // 6591: }
3394 // 6591: } // switch Inst[1:0]
3395 // 6591: }
3396 // 6591: } // switch Inst[8:6]
3397 // 6591: }
3398 6, 189, 3, // 6595: case 0x6: {
3399 OPC_SwitchField, 6, 5, // 6598: switch Inst[10:6] {
3400 0, 15, // 6601: case 0x0: {
3401 OPC_SwitchField, 1, 1, // 6603: switch Inst[1] {
3402 0, 4, // 6606: case 0x0: {
3403 OPC_Decode, 188, 11, 86, // 6608: decode to LXSIWZX using decoder 86
3404 // 6608: }
3405 1, 0, // 6612: case 0x1: {
3406 OPC_Decode, 204, 11, 87, // 6614: decode to LXVRBX using decoder 87
3407 // 6614: }
3408 // 6614: } // switch Inst[1]
3409 // 6614: }
3410 1, 8, // 6618: case 0x1: {
3411 OPC_CheckField, 1, 1, 1, // 6620: check Inst[1] == 0x1
3412 OPC_Decode, 206, 11, 87, // 6624: decode to LXVRHX using decoder 87
3413 // 6624: }
3414 2, 15, // 6628: case 0x2: {
3415 OPC_SwitchField, 1, 1, // 6630: switch Inst[1] {
3416 0, 4, // 6633: case 0x0: {
3417 OPC_Decode, 187, 11, 86, // 6635: decode to LXSIWAX using decoder 86
3418 // 6635: }
3419 1, 0, // 6639: case 0x1: {
3420 OPC_Decode, 209, 11, 87, // 6641: decode to LXVRWX using decoder 87
3421 // 6641: }
3422 // 6641: } // switch Inst[1]
3423 // 6641: }
3424 3, 8, // 6645: case 0x3: {
3425 OPC_CheckField, 1, 1, 1, // 6647: check Inst[1] == 0x1
3426 OPC_Decode, 205, 11, 87, // 6651: decode to LXVRDX using decoder 87
3427 // 6651: }
3428 4, 15, // 6655: case 0x4: {
3429 OPC_SwitchField, 1, 1, // 6657: switch Inst[1] {
3430 0, 4, // 6660: case 0x0: {
3431 OPC_Decode, 159, 16, 86, // 6662: decode to STXSIWX using decoder 86
3432 // 6662: }
3433 1, 0, // 6666: case 0x1: {
3434 OPC_Decode, 173, 16, 87, // 6668: decode to STXVRBX using decoder 87
3435 // 6668: }
3436 // 6668: } // switch Inst[1]
3437 // 6668: }
3438 5, 8, // 6672: case 0x5: {
3439 OPC_CheckField, 1, 1, 1, // 6674: check Inst[1] == 0x1
3440 OPC_Decode, 175, 16, 87, // 6678: decode to STXVRHX using decoder 87
3441 // 6678: }
3442 6, 8, // 6682: case 0x6: {
3443 OPC_CheckField, 1, 1, 1, // 6684: check Inst[1] == 0x1
3444 OPC_Decode, 178, 16, 87, // 6688: decode to STXVRWX using decoder 87
3445 // 6688: }
3446 7, 8, // 6692: case 0x7: {
3447 OPC_CheckField, 1, 1, 1, // 6694: check Inst[1] == 0x1
3448 OPC_Decode, 174, 16, 87, // 6698: decode to STXVRDX using decoder 87
3449 // 6698: }
3450 8, 15, // 6702: case 0x8: {
3451 OPC_SwitchField, 1, 1, // 6704: switch Inst[1] {
3452 0, 4, // 6707: case 0x0: {
3453 OPC_Decode, 212, 11, 87, // 6709: decode to LXVX using decoder 87
3454 // 6709: }
3455 1, 0, // 6713: case 0x1: {
3456 OPC_Decode, 197, 11, 88, // 6715: decode to LXVL using decoder 88
3457 // 6715: }
3458 // 6715: } // switch Inst[1]
3459 // 6715: }
3460 9, 8, // 6719: case 0x9: {
3461 OPC_CheckField, 1, 1, 1, // 6721: check Inst[1] == 0x1
3462 OPC_Decode, 198, 11, 88, // 6725: decode to LXVLL using decoder 88
3463 // 6725: }
3464 10, 19, // 6729: case 0xa: {
3465 OPC_SwitchField, 1, 1, // 6731: switch Inst[1] {
3466 0, 4, // 6734: case 0x0: {
3467 OPC_Decode, 194, 11, 87, // 6736: decode to LXVDSX using decoder 87
3468 // 6736: }
3469 1, 0, // 6740: case 0x1: {
3470 OPC_CheckField, 0, 1, 0, // 6742: check Inst[0] == 0x0
3471 OPC_Decode, 203, 11, 89, // 6746: decode to LXVPX using decoder 89
3472 // 6746: }
3473 // 6746: } // switch Inst[1]
3474 // 6746: }
3475 11, 8, // 6750: case 0xb: {
3476 OPC_CheckField, 1, 1, 0, // 6752: check Inst[1] == 0x0
3477 OPC_Decode, 211, 11, 87, // 6756: decode to LXVWSX using decoder 87
3478 // 6756: }
3479 12, 15, // 6760: case 0xc: {
3480 OPC_SwitchField, 1, 1, // 6762: switch Inst[1] {
3481 0, 4, // 6765: case 0x0: {
3482 OPC_Decode, 180, 16, 87, // 6767: decode to STXVX using decoder 87
3483 // 6767: }
3484 1, 0, // 6771: case 0x1: {
3485 OPC_Decode, 166, 16, 88, // 6773: decode to STXVL using decoder 88
3486 // 6773: }
3487 // 6773: } // switch Inst[1]
3488 // 6773: }
3489 13, 8, // 6777: case 0xd: {
3490 OPC_CheckField, 1, 1, 1, // 6779: check Inst[1] == 0x1
3491 OPC_Decode, 167, 16, 88, // 6783: decode to STXVLL using decoder 88
3492 // 6783: }
3493 14, 8, // 6787: case 0xe: {
3494 OPC_CheckField, 0, 2, 2, // 6789: check Inst[1:0] == 0x2
3495 OPC_Decode, 172, 16, 89, // 6793: decode to STXVPX using decoder 89
3496 // 6793: }
3497 16, 15, // 6797: case 0x10: {
3498 OPC_SwitchField, 1, 1, // 6799: switch Inst[1] {
3499 0, 4, // 6802: case 0x0: {
3500 OPC_Decode, 190, 11, 90, // 6804: decode to LXSSPX using decoder 90
3501 // 6804: }
3502 1, 0, // 6808: case 0x1: {
3503 OPC_Decode, 207, 11, 88, // 6810: decode to LXVRL using decoder 88
3504 // 6810: }
3505 // 6810: } // switch Inst[1]
3506 // 6810: }
3507 17, 8, // 6814: case 0x11: {
3508 OPC_CheckField, 1, 1, 1, // 6816: check Inst[1] == 0x1
3509 OPC_Decode, 208, 11, 88, // 6820: decode to LXVRLL using decoder 88
3510 // 6820: }
3511 18, 19, // 6824: case 0x12: {
3512 OPC_SwitchField, 1, 1, // 6826: switch Inst[1] {
3513 0, 4, // 6829: case 0x0: {
3514 OPC_Decode, 184, 11, 86, // 6831: decode to LXSDX using decoder 86
3515 // 6831: }
3516 1, 0, // 6835: case 0x1: {
3517 OPC_CheckField, 0, 1, 0, // 6837: check Inst[0] == 0x0
3518 OPC_Decode, 201, 11, 91, // 6841: decode to LXVPRL using decoder 91
3519 // 6841: }
3520 // 6841: } // switch Inst[1]
3521 // 6841: }
3522 19, 8, // 6845: case 0x13: {
3523 OPC_CheckField, 0, 2, 2, // 6847: check Inst[1:0] == 0x2
3524 OPC_Decode, 202, 11, 91, // 6851: decode to LXVPRLL using decoder 91
3525 // 6851: }
3526 20, 15, // 6855: case 0x14: {
3527 OPC_SwitchField, 1, 1, // 6857: switch Inst[1] {
3528 0, 4, // 6860: case 0x0: {
3529 OPC_Decode, 161, 16, 90, // 6862: decode to STXSSPX using decoder 90
3530 // 6862: }
3531 1, 0, // 6866: case 0x1: {
3532 OPC_Decode, 176, 16, 88, // 6868: decode to STXVRL using decoder 88
3533 // 6868: }
3534 // 6868: } // switch Inst[1]
3535 // 6868: }
3536 21, 8, // 6872: case 0x15: {
3537 OPC_CheckField, 1, 1, 1, // 6874: check Inst[1] == 0x1
3538 OPC_Decode, 177, 16, 88, // 6878: decode to STXVRLL using decoder 88
3539 // 6878: }
3540 22, 19, // 6882: case 0x16: {
3541 OPC_SwitchField, 1, 1, // 6884: switch Inst[1] {
3542 0, 4, // 6887: case 0x0: {
3543 OPC_Decode, 154, 16, 86, // 6889: decode to STXSDX using decoder 86
3544 // 6889: }
3545 1, 0, // 6893: case 0x1: {
3546 OPC_CheckField, 0, 1, 0, // 6895: check Inst[0] == 0x0
3547 OPC_Decode, 170, 16, 91, // 6899: decode to STXVPRL using decoder 91
3548 // 6899: }
3549 // 6899: } // switch Inst[1]
3550 // 6899: }
3551 23, 8, // 6903: case 0x17: {
3552 OPC_CheckField, 0, 2, 2, // 6905: check Inst[1:0] == 0x2
3553 OPC_Decode, 171, 16, 91, // 6909: decode to STXVPRLL using decoder 91
3554 // 6909: }
3555 24, 15, // 6913: case 0x18: {
3556 OPC_SwitchField, 1, 1, // 6915: switch Inst[1] {
3557 0, 4, // 6918: case 0x0: {
3558 OPC_Decode, 210, 11, 87, // 6920: decode to LXVW4X using decoder 87
3559 // 6920: }
3560 1, 0, // 6924: case 0x1: {
3561 OPC_Decode, 185, 11, 86, // 6926: decode to LXSIBZX using decoder 86
3562 // 6926: }
3563 // 6926: } // switch Inst[1]
3564 // 6926: }
3565 25, 15, // 6930: case 0x19: {
3566 OPC_SwitchField, 1, 1, // 6932: switch Inst[1] {
3567 0, 4, // 6935: case 0x0: {
3568 OPC_Decode, 195, 11, 87, // 6937: decode to LXVH8X using decoder 87
3569 // 6937: }
3570 1, 0, // 6941: case 0x1: {
3571 OPC_Decode, 186, 11, 86, // 6943: decode to LXSIHZX using decoder 86
3572 // 6943: }
3573 // 6943: } // switch Inst[1]
3574 // 6943: }
3575 26, 8, // 6947: case 0x1a: {
3576 OPC_CheckField, 1, 1, 0, // 6949: check Inst[1] == 0x0
3577 OPC_Decode, 193, 11, 87, // 6953: decode to LXVD2X using decoder 87
3578 // 6953: }
3579 27, 19, // 6957: case 0x1b: {
3580 OPC_SwitchField, 1, 1, // 6959: switch Inst[1] {
3581 0, 4, // 6962: case 0x0: {
3582 OPC_Decode, 192, 11, 87, // 6964: decode to LXVB16X using decoder 87
3583 // 6964: }
3584 1, 0, // 6968: case 0x1: {
3585 OPC_CheckField, 0, 1, 0, // 6970: check Inst[0] == 0x0
3586 OPC_Decode, 200, 11, 91, // 6974: decode to LXVPB32X using decoder 91
3587 // 6974: }
3588 // 6974: } // switch Inst[1]
3589 // 6974: }
3590 28, 15, // 6978: case 0x1c: {
3591 OPC_SwitchField, 1, 1, // 6980: switch Inst[1] {
3592 0, 4, // 6983: case 0x0: {
3593 OPC_Decode, 179, 16, 87, // 6985: decode to STXVW4X using decoder 87
3594 // 6985: }
3595 1, 0, // 6989: case 0x1: {
3596 OPC_Decode, 155, 16, 86, // 6991: decode to STXSIBX using decoder 86
3597 // 6991: }
3598 // 6991: } // switch Inst[1]
3599 // 6991: }
3600 29, 15, // 6995: case 0x1d: {
3601 OPC_SwitchField, 1, 1, // 6997: switch Inst[1] {
3602 0, 4, // 7000: case 0x0: {
3603 OPC_Decode, 165, 16, 87, // 7002: decode to STXVH8X using decoder 87
3604 // 7002: }
3605 1, 0, // 7006: case 0x1: {
3606 OPC_Decode, 157, 16, 86, // 7008: decode to STXSIHX using decoder 86
3607 // 7008: }
3608 // 7008: } // switch Inst[1]
3609 // 7008: }
3610 30, 8, // 7012: case 0x1e: {
3611 OPC_CheckField, 1, 1, 0, // 7014: check Inst[1] == 0x0
3612 OPC_Decode, 164, 16, 87, // 7018: decode to STXVD2X using decoder 87
3613 // 7018: }
3614 31, 0, // 7022: case 0x1f: {
3615 OPC_SwitchField, 1, 1, // 7024: switch Inst[1] {
3616 0, 4, // 7027: case 0x0: {
3617 OPC_Decode, 163, 16, 87, // 7029: decode to STXVB16X using decoder 87
3618 // 7029: }
3619 1, 0, // 7033: case 0x1: {
3620 OPC_CheckField, 0, 1, 0, // 7035: check Inst[0] == 0x0
3621 OPC_Decode, 169, 16, 91, // 7039: decode to STXVPB32X using decoder 91
3622 // 7039: }
3623 // 7039: } // switch Inst[1]
3624 // 7039: }
3625 // 7039: } // switch Inst[10:6]
3626 // 7039: }
3627 7, 167, 1, // 7043: case 0x7: {
3628 OPC_SwitchField, 0, 2, // 7046: switch Inst[1:0] {
3629 0, 51, // 7049: case 0x0: {
3630 OPC_SwitchField, 6, 5, // 7051: switch Inst[10:6] {
3631 4, 8, // 7054: case 0x4: {
3632 OPC_CheckField, 16, 10, 0, // 7056: check Inst[25:16] == 0x0
3633 OPC_Decode, 132, 12, 92, // 7060: decode to MSGSNDP using decoder 92
3634 // 7060: }
3635 9, 4, // 7064: case 0x9: {
3636 OPC_Decode, 221, 11, 93, // 7066: decode to MFBHRBE using decoder 93
3637 // 7066: }
3638 10, 4, // 7070: case 0xa: {
3639 OPC_Decode, 240, 11, 71, // 7072: decode to MFPMR using decoder 71
3640 // 7072: }
3641 13, 8, // 7076: case 0xd: {
3642 OPC_CheckField, 11, 15, 0, // 7078: check Inst[25:11] == 0x0
3643 OPC_Decode, 173, 5, 0, // 7082: decode to CLRBHRB using decoder 0
3644 // 7082: }
3645 14, 4, // 7086: case 0xe: {
3646 OPC_Decode, 159, 12, 94, // 7088: decode to MTPMR using decoder 94
3647 // 7088: }
3648 22, 0, // 7092: case 0x16: {
3649 OPC_CheckField, 11, 12, 0, // 7094: check Inst[22:11] == 0x0
3650 OPC_Decode, 240, 16, 68, // 7098: decode to TCHECK using decoder 68
3651 // 7098: }
3652 // 7098: } // switch Inst[10:6]
3653 // 7098: }
3654 1, 103, // 7102: case 0x1: {
3655 OPC_SwitchField, 6, 5, // 7104: switch Inst[10:6] {
3656 20, 12, // 7107: case 0x14: {
3657 OPC_CheckField, 22, 4, 0, // 7109: check Inst[25:22] == 0x0
3658 OPC_CheckField, 11, 10, 0, // 7113: check Inst[20:11] == 0x0
3659 OPC_Decode, 238, 16, 95, // 7117: decode to TBEGIN using decoder 95
3660 // 7117: }
3661 21, 8, // 7121: case 0x15: {
3662 OPC_CheckField, 11, 14, 0, // 7123: check Inst[24:11] == 0x0
3663 OPC_Decode, 250, 16, 96, // 7127: decode to TEND using decoder 96
3664 // 7127: }
3665 23, 12, // 7131: case 0x17: {
3666 OPC_CheckField, 22, 3, 0, // 7133: check Inst[24:22] == 0x0
3667 OPC_CheckField, 11, 10, 0, // 7137: check Inst[20:11] == 0x0
3668 OPC_Decode, 151, 17, 95, // 7141: decode to TSR using decoder 95
3669 // 7141: }
3670 24, 4, // 7145: case 0x18: {
3671 OPC_Decode, 230, 16, 72, // 7147: decode to TABORTWC using decoder 72
3672 // 7147: }
3673 25, 4, // 7151: case 0x19: {
3674 OPC_Decode, 228, 16, 72, // 7153: decode to TABORTDC using decoder 72
3675 // 7153: }
3676 26, 4, // 7157: case 0x1a: {
3677 OPC_Decode, 231, 16, 97, // 7159: decode to TABORTWCI using decoder 97
3678 // 7159: }
3679 27, 4, // 7163: case 0x1b: {
3680 OPC_Decode, 229, 16, 97, // 7165: decode to TABORTDCI using decoder 97
3681 // 7165: }
3682 28, 12, // 7169: case 0x1c: {
3683 OPC_CheckField, 21, 5, 0, // 7171: check Inst[25:21] == 0x0
3684 OPC_CheckField, 11, 5, 0, // 7175: check Inst[15:11] == 0x0
3685 OPC_Decode, 227, 16, 98, // 7179: decode to TABORT using decoder 98
3686 // 7179: }
3687 29, 12, // 7183: case 0x1d: {
3688 OPC_CheckField, 21, 5, 0, // 7185: check Inst[25:21] == 0x0
3689 OPC_CheckField, 11, 5, 0, // 7189: check Inst[15:11] == 0x0
3690 OPC_Decode, 150, 17, 98, // 7193: decode to TRECLAIM using decoder 98
3691 // 7193: }
3692 31, 0, // 7197: case 0x1f: {
3693 OPC_CheckField, 11, 15, 0, // 7199: check Inst[25:11] == 0x0
3694 OPC_Decode, 149, 17, 0, // 7203: decode to TRECHKPT using decoder 0
3695 // 7203: }
3696 // 7203: } // switch Inst[10:6]
3697 // 7203: }
3698 2, 0, // 7207: case 0x2: {
3699 OPC_Decode, 181, 10, 99, // 7209: decode to ISEL using decoder 99
3700 // 7209: }
3701 // 7209: } // switch Inst[1:0]
3702 // 7209: }
3703 8, 145, 1, // 7213: case 0x8: {
3704 OPC_SwitchField, 0, 2, // 7216: switch Inst[1:0] {
3705 0, 23, // 7219: case 0x0: {
3706 OPC_SwitchField, 20, 1, // 7221: switch Inst[20] {
3707 0, 8, // 7224: case 0x0: {
3708 OPC_CheckField, 6, 6, 4, // 7226: check Inst[11:6] == 0x4
3709 OPC_Decode, 136, 12, 100, // 7230: decode to MTCRF using decoder 100
3710 // 7230: }
3711 1, 0, // 7234: case 0x1: {
3712 OPC_CheckField, 6, 6, 4, // 7236: check Inst[11:6] == 0x4
3713 OPC_Decode, 157, 12, 101, // 7240: decode to MTOCRF using decoder 101
3714 // 7240: }
3715 // 7240: } // switch Inst[20]
3716 // 7240: }
3717 2, 0, // 7244: case 0x2: {
3718 OPC_SwitchField, 16, 5, // 7246: switch Inst[20:16] {
3719 0, 12, // 7249: case 0x0: {
3720 OPC_CheckField, 21, 2, 0, // 7251: check Inst[22:21] == 0x0
3721 OPC_CheckField, 6, 10, 5, // 7255: check Inst[15:6] == 0x5
3722 OPC_Decode, 146, 23, 102, // 7259: decode to XXMFACC using decoder 102
3723 // 7259: }
3724 1, 12, // 7263: case 0x1: {
3725 OPC_CheckField, 21, 2, 0, // 7265: check Inst[22:21] == 0x0
3726 OPC_CheckField, 6, 10, 5, // 7269: check Inst[15:6] == 0x5
3727 OPC_Decode, 150, 23, 102, // 7273: decode to XXMTACC using decoder 102
3728 // 7273: }
3729 2, 12, // 7277: case 0x2: {
3730 OPC_CheckField, 21, 2, 0, // 7279: check Inst[22:21] == 0x0
3731 OPC_CheckField, 6, 10, 5, // 7283: check Inst[15:6] == 0x5
3732 OPC_Decode, 179, 6, 103, // 7287: decode to DMSETDMRZ using decoder 103
3733 // 7287: }
3734 3, 12, // 7291: case 0x3: {
3735 OPC_CheckField, 21, 2, 0, // 7293: check Inst[22:21] == 0x0
3736 OPC_CheckField, 6, 10, 5, // 7297: check Inst[15:6] == 0x5
3737 OPC_Decode, 161, 23, 104, // 7301: decode to XXSETACCZ using decoder 104
3738 // 7301: }
3739 6, 12, // 7305: case 0x6: {
3740 OPC_CheckField, 21, 2, 0, // 7307: check Inst[22:21] == 0x0
3741 OPC_CheckField, 6, 7, 5, // 7311: check Inst[12:6] == 0x5
3742 OPC_Decode, 178, 6, 105, // 7315: decode to DMMR using decoder 105
3743 // 7315: }
3744 7, 12, // 7319: case 0x7: {
3745 OPC_CheckField, 21, 2, 0, // 7321: check Inst[22:21] == 0x0
3746 OPC_CheckField, 6, 7, 5, // 7325: check Inst[12:6] == 0x5
3747 OPC_Decode, 186, 6, 106, // 7329: decode to DMXOR using decoder 106
3748 // 7329: }
3749 14, 12, // 7333: case 0xe: {
3750 OPC_CheckField, 22, 1, 0, // 7335: check Inst[22] == 0x0
3751 OPC_CheckField, 6, 7, 5, // 7339: check Inst[12:6] == 0x5
3752 OPC_Decode, 180, 6, 107, // 7343: decode to DMSHA2HASH using decoder 107
3753 // 7343: }
3754 15, 0, // 7347: case 0xf: {
3755 OPC_CheckField, 21, 3, 0, // 7349: check Inst[23:21] == 0x0
3756 OPC_CheckField, 6, 5, 5, // 7353: check Inst[10:6] == 0x5
3757 OPC_Decode, 181, 6, 108, // 7357: decode to DMSHA3HASH using decoder 108
3758 // 7357: }
3759 // 7357: } // switch Inst[20:16]
3760 // 7357: }
3761 // 7357: } // switch Inst[1:0]
3762 // 7357: }
3763 9, 132, 5, // 7361: case 0x9: {
3764 OPC_SwitchField, 6, 5, // 7364: switch Inst[10:6] {
3765 0, 48, // 7367: case 0x0: {
3766 OPC_SwitchField, 0, 2, // 7369: switch Inst[1:0] {
3767 0, 18, // 7372: case 0x0: {
3768 OPC_Scope, 12, // 7374: try {
3769 OPC_CheckField, 16, 2, 0, // 7376: check Inst[17:16] == 0x0
3770 OPC_CheckField, 20, 1, 0, // 7380: check Inst[20] == 0x0
3771 OPC_Decode, 254, 16, 109, // 7384: decode to TLBIEIO using decoder 109
3772 // 7384: } else try {
3773 OPC_Decode, 131, 17, 110, // 7388: decode to TLBILX using decoder 110
3774 // 7388: }
3775 // 7388: }
3776 2, 0, // 7392: case 0x2: {
3777 OPC_SwitchField, 20, 1, // 7394: switch Inst[20] {
3778 0, 8, // 7397: case 0x0: {
3779 OPC_CheckField, 11, 9, 0, // 7399: check Inst[19:11] == 0x0
3780 OPC_Decode, 222, 11, 69, // 7403: decode to MFCR using decoder 69
3781 // 7403: }
3782 1, 0, // 7407: case 0x1: {
3783 OPC_CheckField, 11, 1, 0, // 7409: check Inst[11] == 0x0
3784 OPC_Decode, 238, 11, 111, // 7413: decode to MFOCRF using decoder 111
3785 // 7413: }
3786 // 7413: } // switch Inst[20]
3787 // 7413: }
3788 // 7413: } // switch Inst[1:0]
3789 // 7413: }
3790 1, 27, // 7417: case 0x1: {
3791 OPC_SwitchField, 1, 1, // 7419: switch Inst[1] {
3792 0, 12, // 7422: case 0x0: {
3793 OPC_CheckField, 20, 1, 0, // 7424: check Inst[20] == 0x0
3794 OPC_CheckField, 0, 1, 0, // 7428: check Inst[0] == 0x0
3795 OPC_Decode, 128, 17, 112, // 7432: decode to TLBIEP using decoder 112
3796 // 7432: }
3797 1, 0, // 7436: case 0x1: {
3798 OPC_CheckField, 11, 5, 0, // 7438: check Inst[15:11] == 0x0
3799 OPC_Decode, 253, 11, 113, // 7442: decode to MFVSRD using decoder 113
3800 // 7442: }
3801 // 7442: } // switch Inst[1]
3802 // 7442: }
3803 2, 12, // 7446: case 0x2: {
3804 OPC_CheckField, 11, 10, 0, // 7448: check Inst[20:11] == 0x0
3805 OPC_CheckField, 0, 2, 2, // 7452: check Inst[1:0] == 0x2
3806 OPC_Decode, 237, 11, 69, // 7456: decode to MFMSR using decoder 69
3807 // 7456: }
3808 3, 12, // 7460: case 0x3: {
3809 OPC_CheckField, 11, 5, 0, // 7462: check Inst[15:11] == 0x0
3810 OPC_CheckField, 1, 1, 1, // 7466: check Inst[1] == 0x1
3811 OPC_Decode, 255, 11, 114, // 7470: decode to MFVSRWZ using decoder 114
3812 // 7470: }
3813 4, 8, // 7474: case 0x4: {
3814 OPC_CheckField, 1, 1, 0, // 7476: check Inst[1] == 0x0
3815 OPC_Decode, 155, 12, 115, // 7480: decode to MTMSR using decoder 115
3816 // 7480: }
3817 5, 19, // 7484: case 0x5: {
3818 OPC_SwitchField, 1, 1, // 7486: switch Inst[1] {
3819 0, 4, // 7489: case 0x0: {
3820 OPC_Decode, 156, 12, 115, // 7491: decode to MTMSRD using decoder 115
3821 // 7491: }
3822 1, 0, // 7495: case 0x1: {
3823 OPC_CheckField, 11, 5, 0, // 7497: check Inst[15:11] == 0x0
3824 OPC_Decode, 173, 12, 116, // 7501: decode to MTVSRD using decoder 116
3825 // 7501: }
3826 // 7501: } // switch Inst[1]
3827 // 7501: }
3828 6, 19, // 7505: case 0x6: {
3829 OPC_SwitchField, 1, 1, // 7507: switch Inst[1] {
3830 0, 4, // 7510: case 0x0: {
3831 OPC_Decode, 162, 12, 117, // 7512: decode to MTSR using decoder 117
3832 // 7512: }
3833 1, 0, // 7516: case 0x1: {
3834 OPC_CheckField, 11, 5, 0, // 7518: check Inst[15:11] == 0x0
3835 OPC_Decode, 178, 12, 118, // 7522: decode to MTVSRWA using decoder 118
3836 // 7522: }
3837 // 7522: } // switch Inst[1]
3838 // 7522: }
3839 7, 19, // 7526: case 0x7: {
3840 OPC_SwitchField, 1, 1, // 7528: switch Inst[1] {
3841 0, 4, // 7531: case 0x0: {
3842 OPC_Decode, 163, 12, 119, // 7533: decode to MTSRIN using decoder 119
3843 // 7533: }
3844 1, 0, // 7537: case 0x1: {
3845 OPC_CheckField, 11, 5, 0, // 7539: check Inst[15:11] == 0x0
3846 OPC_Decode, 181, 12, 118, // 7543: decode to MTVSRWZ using decoder 118
3847 // 7543: }
3848 // 7543: } // switch Inst[1]
3849 // 7543: }
3850 8, 23, // 7547: case 0x8: {
3851 OPC_SwitchField, 0, 2, // 7549: switch Inst[1:0] {
3852 0, 8, // 7552: case 0x0: {
3853 OPC_CheckField, 16, 10, 0, // 7554: check Inst[25:16] == 0x0
3854 OPC_Decode, 255, 16, 92, // 7558: decode to TLBIEL using decoder 92
3855 // 7558: }
3856 2, 0, // 7562: case 0x2: {
3857 OPC_CheckField, 16, 5, 0, // 7564: check Inst[20:16] == 0x0
3858 OPC_Decode, 151, 12, 120, // 7568: decode to MTLPL using decoder 120
3859 // 7568: }
3860 // 7568: } // switch Inst[1:0]
3861 // 7568: }
3862 9, 37, // 7572: case 0x9: {
3863 OPC_SwitchField, 1, 1, // 7574: switch Inst[1] {
3864 0, 22, // 7577: case 0x0: {
3865 OPC_CheckField, 0, 1, 0, // 7579: check Inst[0] == 0x0
3866 OPC_CheckField, 20, 1, 0, // 7583: check Inst[20] == 0x0
3867 OPC_Scope, 8, // 7587: try {
3868 OPC_CheckField, 16, 4, 0, // 7589: check Inst[19:16] == 0x0
3869 OPC_Decode, 252, 16, 119, // 7593: decode to TLBIE using decoder 119
3870 // 7593: } else try {
3871 OPC_Decode, 130, 17, 112, // 7597: decode to TLBIEP9 using decoder 112
3872 // 7597: }
3873 // 7597: }
3874 1, 0, // 7601: case 0x1: {
3875 OPC_CheckField, 11, 5, 0, // 7603: check Inst[15:11] == 0x0
3876 OPC_Decode, 254, 11, 121, // 7607: decode to MFVSRLD using decoder 121
3877 // 7607: }
3878 // 7607: } // switch Inst[1]
3879 // 7607: }
3880 10, 44, // 7611: case 0xa: {
3881 OPC_SwitchField, 0, 2, // 7613: switch Inst[1:0] {
3882 0, 8, // 7616: case 0x0: {
3883 OPC_CheckField, 11, 15, 0, // 7618: check Inst[25:11] == 0x0
3884 OPC_Decode, 162, 15, 0, // 7622: decode to SLBSYNC using decoder 0
3885 // 7622: }
3886 2, 0, // 7626: case 0x2: {
3887 OPC_Scope, 23, // 7628: try {
3888 OPC_SwitchField, 11, 10, // 7630: switch Inst[20:11] {
3889 96, 4, // 7633: case 0x60: {
3890 OPC_Decode, 247, 11, 69, // 7635: decode to MFUDSCR using decoder 69
3891 // 7635: }
3892 128, 2, 4, // 7639: case 0x100: {
3893 OPC_Decode, 235, 11, 69, // 7642: decode to MFLR using decoder 69
3894 // 7642: }
3895 160, 2, 0, // 7646: case 0x120: {
3896 OPC_Decode, 224, 11, 69, // 7649: decode to MFCTR using decoder 69
3897 // 7649: }
3898 // 7649: } // switch Inst[20:11]
3899 // 7649: } else try {
3900 OPC_Decode, 241, 11, 71, // 7653: decode to MFSPR using decoder 71
3901 // 7653: }
3902 // 7653: }
3903 // 7653: } // switch Inst[1:0]
3904 // 7653: }
3905 11, 19, // 7657: case 0xb: {
3906 OPC_SwitchField, 0, 2, // 7659: switch Inst[1:0] {
3907 0, 8, // 7662: case 0x0: {
3908 OPC_CheckField, 11, 15, 0, // 7664: check Inst[25:11] == 0x0
3909 OPC_Decode, 251, 16, 0, // 7668: decode to TLBIA using decoder 0
3910 // 7668: }
3911 2, 0, // 7672: case 0x2: {
3912 OPC_Decode, 245, 11, 71, // 7674: decode to MFTB using decoder 71
3913 // 7674: }
3914 // 7674: } // switch Inst[1:0]
3915 // 7674: }
3916 12, 27, // 7678: case 0xc: {
3917 OPC_SwitchField, 1, 1, // 7680: switch Inst[1] {
3918 0, 12, // 7683: case 0x0: {
3919 OPC_CheckField, 16, 5, 0, // 7685: check Inst[20:16] == 0x0
3920 OPC_CheckField, 0, 1, 0, // 7689: check Inst[0] == 0x0
3921 OPC_Decode, 161, 15, 119, // 7693: decode to SLBMTE using decoder 119
3922 // 7693: }
3923 1, 0, // 7697: case 0x1: {
3924 OPC_CheckField, 11, 5, 0, // 7699: check Inst[15:11] == 0x0
3925 OPC_Decode, 180, 12, 122, // 7703: decode to MTVSRWS using decoder 122
3926 // 7703: }
3927 // 7703: } // switch Inst[1]
3928 // 7703: }
3929 13, 23, // 7707: case 0xd: {
3930 OPC_SwitchField, 1, 1, // 7709: switch Inst[1] {
3931 0, 12, // 7712: case 0x0: {
3932 OPC_CheckField, 16, 10, 0, // 7714: check Inst[25:16] == 0x0
3933 OPC_CheckField, 0, 1, 0, // 7718: check Inst[0] == 0x0
3934 OPC_Decode, 157, 15, 92, // 7722: decode to SLBIE using decoder 92
3935 // 7722: }
3936 1, 0, // 7726: case 0x1: {
3937 OPC_Decode, 174, 12, 123, // 7728: decode to MTVSRDD using decoder 123
3938 // 7728: }
3939 // 7728: } // switch Inst[1]
3940 // 7728: }
3941 14, 44, // 7732: case 0xe: {
3942 OPC_SwitchField, 0, 2, // 7734: switch Inst[1:0] {
3943 0, 8, // 7737: case 0x0: {
3944 OPC_CheckField, 16, 5, 0, // 7739: check Inst[20:16] == 0x0
3945 OPC_Decode, 158, 15, 119, // 7743: decode to SLBIEG using decoder 119
3946 // 7743: }
3947 2, 0, // 7747: case 0x2: {
3948 OPC_Scope, 23, // 7749: try {
3949 OPC_SwitchField, 11, 10, // 7751: switch Inst[20:11] {
3950 96, 4, // 7754: case 0x60: {
3951 OPC_Decode, 164, 12, 69, // 7756: decode to MTUDSCR using decoder 69
3952 // 7756: }
3953 128, 2, 4, // 7760: case 0x100: {
3954 OPC_Decode, 153, 12, 69, // 7763: decode to MTLR using decoder 69
3955 // 7763: }
3956 160, 2, 0, // 7767: case 0x120: {
3957 OPC_Decode, 138, 12, 69, // 7770: decode to MTCTR using decoder 69
3958 // 7770: }
3959 // 7770: } // switch Inst[20:11]
3960 // 7770: } else try {
3961 OPC_Decode, 160, 12, 94, // 7774: decode to MTSPR using decoder 94
3962 // 7774: }
3963 // 7774: }
3964 // 7774: } // switch Inst[1:0]
3965 // 7774: }
3966 15, 12, // 7778: case 0xf: {
3967 OPC_CheckField, 11, 15, 0, // 7780: check Inst[25:11] == 0x0
3968 OPC_CheckField, 0, 2, 0, // 7784: check Inst[1:0] == 0x0
3969 OPC_Decode, 156, 15, 0, // 7788: decode to SLBIA using decoder 0
3970 // 7788: }
3971 18, 8, // 7792: case 0x12: {
3972 OPC_CheckField, 1, 1, 1, // 7794: check Inst[1] == 0x1
3973 OPC_Decode, 243, 11, 117, // 7798: decode to MFSR using decoder 117
3974 // 7798: }
3975 20, 15, // 7802: case 0x14: {
3976 OPC_SwitchField, 1, 1, // 7804: switch Inst[1] {
3977 0, 4, // 7807: case 0x0: {
3978 OPC_Decode, 171, 10, 124, // 7809: decode to HASHSTP using decoder 124
3979 // 7809: }
3980 1, 0, // 7813: case 0x1: {
3981 OPC_Decode, 244, 11, 119, // 7815: decode to MFSRIN using decoder 119
3982 // 7815: }
3983 // 7815: } // switch Inst[1]
3984 // 7815: }
3985 21, 8, // 7819: case 0x15: {
3986 OPC_CheckField, 1, 1, 0, // 7821: check Inst[1] == 0x0
3987 OPC_Decode, 167, 10, 124, // 7825: decode to HASHCHKP using decoder 124
3988 // 7825: }
3989 22, 8, // 7829: case 0x16: {
3990 OPC_CheckField, 1, 1, 0, // 7831: check Inst[1] == 0x0
3991 OPC_Decode, 169, 10, 124, // 7835: decode to HASHST using decoder 124
3992 // 7835: }
3993 23, 27, // 7839: case 0x17: {
3994 OPC_SwitchField, 1, 1, // 7841: switch Inst[1] {
3995 0, 4, // 7844: case 0x0: {
3996 OPC_Decode, 165, 10, 124, // 7846: decode to HASHCHK using decoder 124
3997 // 7846: }
3998 1, 0, // 7850: case 0x1: {
3999 OPC_CheckField, 18, 3, 0, // 7852: check Inst[20:18] == 0x0
4000 OPC_CheckField, 11, 5, 0, // 7856: check Inst[15:11] == 0x0
4001 OPC_CheckField, 0, 1, 0, // 7860: check Inst[0] == 0x0
4002 OPC_Decode, 224, 5, 125, // 7864: decode to DARN using decoder 125
4003 // 7864: }
4004 // 7864: } // switch Inst[1]
4005 // 7864: }
4006 24, 12, // 7868: case 0x18: {
4007 OPC_CheckField, 21, 5, 0, // 7870: check Inst[25:21] == 0x0
4008 OPC_CheckField, 0, 2, 0, // 7874: check Inst[1:0] == 0x0
4009 OPC_Decode, 132, 17, 76, // 7878: decode to TLBIVAX using decoder 76
4010 // 7878: }
4011 26, 12, // 7882: case 0x1a: {
4012 OPC_CheckField, 16, 5, 0, // 7884: check Inst[20:16] == 0x0
4013 OPC_CheckField, 0, 2, 2, // 7888: check Inst[1:0] == 0x2
4014 OPC_Decode, 160, 15, 119, // 7892: decode to SLBMFEV using decoder 119
4015 // 7892: }
4016 28, 35, // 7896: case 0x1c: {
4017 OPC_SwitchField, 0, 2, // 7898: switch Inst[1:0] {
4018 0, 14, // 7901: case 0x0: {
4019 OPC_Scope, 8, // 7903: try {
4020 OPC_CheckField, 21, 5, 0, // 7905: check Inst[25:21] == 0x0
4021 OPC_Decode, 137, 17, 76, // 7909: decode to TLBSX using decoder 76
4022 // 7909: } else try {
4023 OPC_Decode, 138, 17, 81, // 7913: decode to TLBSX2 using decoder 81
4024 // 7913: }
4025 // 7913: }
4026 1, 4, // 7917: case 0x1: {
4027 OPC_Decode, 139, 17, 81, // 7919: decode to TLBSX2D using decoder 81
4028 // 7919: }
4029 2, 0, // 7923: case 0x2: {
4030 OPC_CheckField, 16, 5, 0, // 7925: check Inst[20:16] == 0x0
4031 OPC_Decode, 159, 15, 119, // 7929: decode to SLBMFEE using decoder 119
4032 // 7929: }
4033 // 7929: } // switch Inst[1:0]
4034 // 7929: }
4035 29, 18, // 7933: case 0x1d: {
4036 OPC_CheckField, 0, 2, 0, // 7935: check Inst[1:0] == 0x0
4037 OPC_Scope, 8, // 7939: try {
4038 OPC_CheckField, 11, 15, 0, // 7941: check Inst[25:11] == 0x0
4039 OPC_Decode, 135, 17, 0, // 7945: decode to TLBRE using decoder 0
4040 // 7945: } else try {
4041 OPC_Decode, 136, 17, 126, // 7949: decode to TLBRE2 using decoder 126
4042 // 7949: }
4043 // 7949: }
4044 30, 39, // 7953: case 0x1e: {
4045 OPC_SwitchField, 0, 2, // 7955: switch Inst[1:0] {
4046 0, 24, // 7958: case 0x0: {
4047 OPC_Scope, 8, // 7960: try {
4048 OPC_CheckField, 11, 15, 0, // 7962: check Inst[25:11] == 0x0
4049 OPC_Decode, 142, 17, 0, // 7966: decode to TLBWE using decoder 0
4050 OPC_Scope, 8, // 7970: } else try {
4051 OPC_CheckField, 16, 10, 0, // 7972: check Inst[25:16] == 0x0
4052 OPC_Decode, 133, 17, 92, // 7976: decode to TLBLD using decoder 92
4053 // 7976: } else try {
4054 OPC_Decode, 143, 17, 126, // 7980: decode to TLBWE2 using decoder 126
4055 // 7980: }
4056 // 7980: }
4057 3, 0, // 7984: case 0x3: {
4058 OPC_CheckField, 16, 5, 0, // 7986: check Inst[20:16] == 0x0
4059 OPC_Decode, 155, 15, 119, // 7990: decode to SLBFEE_rec using decoder 119
4060 // 7990: }
4061 // 7990: } // switch Inst[1:0]
4062 // 7990: }
4063 31, 0, // 7994: case 0x1f: {
4064 OPC_CheckField, 16, 10, 0, // 7996: check Inst[25:16] == 0x0
4065 OPC_CheckField, 0, 2, 0, // 8000: check Inst[1:0] == 0x0
4066 OPC_Decode, 134, 17, 92, // 8004: decode to TLBLI using decoder 92
4067 // 8004: }
4068 // 8004: } // switch Inst[10:6]
4069 // 8004: }
4070 10, 173, 2, // 8008: case 0xa: {
4071 OPC_SwitchField, 6, 5, // 8011: switch Inst[10:6] {
4072 0, 22, // 8014: case 0x0: {
4073 OPC_SwitchField, 0, 2, // 8016: switch Inst[1:0] {
4074 0, 4, // 8019: case 0x0: {
4075 OPC_Decode, 154, 11, 127, // 8021: decode to LWARX using decoder 127
4076 // 8021: }
4077 1, 4, // 8025: case 0x1: {
4078 OPC_Decode, 155, 11, 127, // 8027: decode to LWARXL using decoder 127
4079 // 8027: }
4080 2, 0, // 8031: case 0x2: {
4081 OPC_Decode, 211, 10, 128, 1, // 8033: decode to LDX using decoder 128
4082 // 8033: }
4083 // 8033: } // switch Inst[1:0]
4084 // 8033: }
4085 1, 22, // 8038: case 0x1: {
4086 OPC_SwitchField, 0, 2, // 8040: switch Inst[1:0] {
4087 0, 4, // 8043: case 0x0: {
4088 OPC_Decode, 186, 10, 127, // 8045: decode to LBARX using decoder 127
4089 // 8045: }
4090 1, 4, // 8049: case 0x1: {
4091 OPC_Decode, 187, 10, 127, // 8051: decode to LBARXL using decoder 127
4092 // 8051: }
4093 2, 0, // 8055: case 0x2: {
4094 OPC_Decode, 210, 10, 129, 1, // 8057: decode to LDUX using decoder 129
4095 // 8057: }
4096 // 8057: } // switch Inst[1:0]
4097 // 8057: }
4098 2, 17, // 8062: case 0x2: {
4099 OPC_SwitchField, 0, 2, // 8064: switch Inst[1:0] {
4100 0, 5, // 8067: case 0x0: {
4101 OPC_Decode, 202, 10, 128, 1, // 8069: decode to LDARX using decoder 128
4102 // 8069: }
4103 1, 0, // 8074: case 0x1: {
4104 OPC_Decode, 203, 10, 128, 1, // 8076: decode to LDARXL using decoder 128
4105 // 8076: }
4106 // 8076: } // switch Inst[1:0]
4107 // 8076: }
4108 3, 15, // 8081: case 0x3: {
4109 OPC_SwitchField, 0, 2, // 8083: switch Inst[1:0] {
4110 0, 4, // 8086: case 0x0: {
4111 OPC_Decode, 238, 10, 127, // 8088: decode to LHARX using decoder 127
4112 // 8088: }
4113 1, 0, // 8092: case 0x1: {
4114 OPC_Decode, 239, 10, 127, // 8094: decode to LHARXL using decoder 127
4115 // 8094: }
4116 // 8094: } // switch Inst[1:0]
4117 // 8094: }
4118 4, 9, // 8098: case 0x4: {
4119 OPC_CheckField, 0, 2, 2, // 8100: check Inst[1:0] == 0x2
4120 OPC_Decode, 222, 15, 128, 1, // 8104: decode to STDX using decoder 128
4121 // 8104: }
4122 5, 9, // 8109: case 0x5: {
4123 OPC_CheckField, 0, 2, 2, // 8111: check Inst[1:0] == 0x2
4124 OPC_Decode, 221, 15, 130, 1, // 8115: decode to STDUX using decoder 130
4125 // 8115: }
4126 8, 17, // 8120: case 0x8: {
4127 OPC_SwitchField, 0, 2, // 8122: switch Inst[1:0] {
4128 0, 5, // 8125: case 0x0: {
4129 OPC_Decode, 142, 11, 131, 1, // 8127: decode to LQARX using decoder 131
4130 // 8127: }
4131 1, 0, // 8132: case 0x1: {
4132 OPC_Decode, 143, 11, 131, 1, // 8134: decode to LQARXL using decoder 131
4133 // 8134: }
4134 // 8134: } // switch Inst[1:0]
4135 // 8134: }
4136 10, 9, // 8139: case 0xa: {
4137 OPC_CheckField, 0, 2, 2, // 8141: check Inst[1:0] == 0x2
4138 OPC_Decode, 160, 11, 128, 1, // 8145: decode to LWAX using decoder 128
4139 // 8145: }
4140 11, 9, // 8150: case 0xb: {
4141 OPC_CheckField, 0, 2, 2, // 8152: check Inst[1:0] == 0x2
4142 OPC_Decode, 159, 11, 129, 1, // 8156: decode to LWAUX using decoder 129
4143 // 8156: }
4144 16, 9, // 8161: case 0x10: {
4145 OPC_CheckField, 0, 2, 0, // 8163: check Inst[1:0] == 0x0
4146 OPC_Decode, 207, 10, 128, 1, // 8167: decode to LDBRX using decoder 128
4147 // 8167: }
4148 17, 13, // 8172: case 0x11: {
4149 OPC_CheckField, 11, 10, 0, // 8174: check Inst[20:11] == 0x0
4150 OPC_CheckField, 0, 2, 0, // 8178: check Inst[1:0] == 0x0
4151 OPC_Decode, 141, 17, 132, 1, // 8182: decode to TLBSYNCIO using decoder 132
4152 // 8182: }
4153 18, 21, // 8187: case 0x12: {
4154 OPC_SwitchField, 0, 2, // 8189: switch Inst[1:0] {
4155 0, 9, // 8192: case 0x0: {
4156 OPC_CheckField, 11, 10, 0, // 8194: check Inst[20:11] == 0x0
4157 OPC_Decode, 201, 14, 132, 1, // 8198: decode to PTESYNCIO using decoder 132
4158 // 8198: }
4159 2, 0, // 8203: case 0x2: {
4160 OPC_Decode, 145, 11, 133, 1, // 8205: decode to LSWI using decoder 133
4161 // 8205: }
4162 // 8205: } // switch Inst[1:0]
4163 // 8205: }
4164 20, 9, // 8210: case 0x14: {
4165 OPC_CheckField, 0, 2, 0, // 8212: check Inst[1:0] == 0x0
4166 OPC_Decode, 217, 15, 128, 1, // 8216: decode to STDBRX using decoder 128
4167 // 8216: }
4168 22, 9, // 8221: case 0x16: {
4169 OPC_CheckField, 0, 2, 2, // 8223: check Inst[1:0] == 0x2
4170 OPC_Decode, 131, 16, 133, 1, // 8227: decode to STSWI using decoder 133
4171 // 8227: }
4172 24, 8, // 8232: case 0x18: {
4173 OPC_CheckField, 0, 2, 2, // 8234: check Inst[1:0] == 0x2
4174 OPC_Decode, 171, 11, 81, // 8238: decode to LWZCIX using decoder 81
4175 // 8238: }
4176 25, 8, // 8242: case 0x19: {
4177 OPC_CheckField, 0, 2, 2, // 8244: check Inst[1:0] == 0x2
4178 OPC_Decode, 254, 10, 81, // 8248: decode to LHZCIX using decoder 81
4179 // 8248: }
4180 26, 8, // 8252: case 0x1a: {
4181 OPC_CheckField, 0, 2, 2, // 8254: check Inst[1:0] == 0x2
4182 OPC_Decode, 191, 10, 81, // 8258: decode to LBZCIX using decoder 81
4183 // 8258: }
4184 27, 8, // 8262: case 0x1b: {
4185 OPC_CheckField, 0, 2, 2, // 8264: check Inst[1:0] == 0x2
4186 OPC_Decode, 208, 10, 81, // 8268: decode to LDCIX using decoder 81
4187 // 8268: }
4188 28, 8, // 8272: case 0x1c: {
4189 OPC_CheckField, 0, 2, 2, // 8274: check Inst[1:0] == 0x2
4190 OPC_Decode, 141, 16, 81, // 8278: decode to STWCIX using decoder 81
4191 // 8278: }
4192 29, 8, // 8282: case 0x1d: {
4193 OPC_CheckField, 0, 2, 2, // 8284: check Inst[1:0] == 0x2
4194 OPC_Decode, 242, 15, 81, // 8288: decode to STHCIX using decoder 81
4195 // 8288: }
4196 30, 8, // 8292: case 0x1e: {
4197 OPC_CheckField, 0, 2, 2, // 8294: check Inst[1:0] == 0x2
4198 OPC_Decode, 203, 15, 81, // 8298: decode to STBCIX using decoder 81
4199 // 8298: }
4200 31, 0, // 8302: case 0x1f: {
4201 OPC_CheckField, 0, 2, 2, // 8304: check Inst[1:0] == 0x2
4202 OPC_Decode, 218, 15, 81, // 8308: decode to STDCIX using decoder 81
4203 // 8308: }
4204 // 8308: } // switch Inst[10:6]
4205 // 8308: }
4206 11, 228, 4, // 8312: case 0xb: {
4207 OPC_SwitchField, 6, 5, // 8315: switch Inst[10:6] {
4208 0, 19, // 8318: case 0x0: {
4209 OPC_SwitchField, 0, 2, // 8320: switch Inst[1:0] {
4210 0, 8, // 8323: case 0x0: {
4211 OPC_CheckField, 25, 1, 0, // 8325: check Inst[25] == 0x0
4212 OPC_Decode, 178, 10, 75, // 8329: decode to ICBT using decoder 75
4213 // 8329: }
4214 2, 0, // 8333: case 0x2: {
4215 OPC_Decode, 176, 11, 127, // 8335: decode to LWZX using decoder 127
4216 // 8335: }
4217 // 8335: } // switch Inst[1:0]
4218 // 8335: }
4219 1, 21, // 8339: case 0x1: {
4220 OPC_SwitchField, 0, 2, // 8341: switch Inst[1:0] {
4221 0, 9, // 8344: case 0x0: {
4222 OPC_CheckField, 21, 5, 0, // 8346: check Inst[25:21] == 0x0
4223 OPC_Decode, 229, 5, 134, 1, // 8350: decode to DCBST using decoder 134
4224 // 8350: }
4225 2, 0, // 8355: case 0x2: {
4226 OPC_Decode, 174, 11, 135, 1, // 8357: decode to LWZUX using decoder 135
4227 // 8357: }
4228 // 8357: } // switch Inst[1:0]
4229 // 8357: }
4230 2, 16, // 8362: case 0x2: {
4231 OPC_SwitchField, 0, 2, // 8364: switch Inst[1:0] {
4232 0, 5, // 8367: case 0x0: {
4233 OPC_Decode, 226, 5, 136, 1, // 8369: decode to DCBF using decoder 136
4234 // 8369: }
4235 2, 0, // 8374: case 0x2: {
4236 OPC_Decode, 196, 10, 127, // 8376: decode to LBZX using decoder 127
4237 // 8376: }
4238 // 8376: } // switch Inst[1:0]
4239 // 8376: }
4240 3, 9, // 8380: case 0x3: {
4241 OPC_CheckField, 0, 2, 2, // 8382: check Inst[1:0] == 0x2
4242 OPC_Decode, 194, 10, 135, 1, // 8386: decode to LBZUX using decoder 135
4243 // 8386: }
4244 4, 15, // 8391: case 0x4: {
4245 OPC_SwitchField, 0, 2, // 8393: switch Inst[1:0] {
4246 1, 4, // 8396: case 0x1: {
4247 OPC_Decode, 142, 16, 127, // 8398: decode to STWCX using decoder 127
4248 // 8398: }
4249 2, 0, // 8402: case 0x2: {
4250 OPC_Decode, 148, 16, 127, // 8404: decode to STWX using decoder 127
4251 // 8404: }
4252 // 8404: } // switch Inst[1:0]
4253 // 8404: }
4254 5, 17, // 8408: case 0x5: {
4255 OPC_SwitchField, 0, 2, // 8410: switch Inst[1:0] {
4256 1, 5, // 8413: case 0x1: {
4257 OPC_Decode, 129, 16, 131, 1, // 8415: decode to STQCX using decoder 131
4258 // 8415: }
4259 2, 0, // 8420: case 0x2: {
4260 OPC_Decode, 146, 16, 137, 1, // 8422: decode to STWUX using decoder 137
4261 // 8422: }
4262 // 8422: } // switch Inst[1:0]
4263 // 8422: }
4264 6, 16, // 8427: case 0x6: {
4265 OPC_SwitchField, 0, 2, // 8429: switch Inst[1:0] {
4266 1, 5, // 8432: case 0x1: {
4267 OPC_Decode, 219, 15, 128, 1, // 8434: decode to STDCX using decoder 128
4268 // 8434: }
4269 2, 0, // 8439: case 0x2: {
4270 OPC_Decode, 210, 15, 127, // 8441: decode to STBX using decoder 127
4271 // 8441: }
4272 // 8441: } // switch Inst[1:0]
4273 // 8441: }
4274 7, 17, // 8445: case 0x7: {
4275 OPC_SwitchField, 0, 2, // 8447: switch Inst[1:0] {
4276 0, 5, // 8450: case 0x0: {
4277 OPC_Decode, 233, 5, 138, 1, // 8452: decode to DCBTST using decoder 138
4278 // 8452: }
4279 2, 0, // 8457: case 0x2: {
4280 OPC_Decode, 208, 15, 137, 1, // 8459: decode to STBUX using decoder 137
4281 // 8459: }
4282 // 8459: } // switch Inst[1:0]
4283 // 8459: }
4284 8, 16, // 8464: case 0x8: {
4285 OPC_SwitchField, 0, 2, // 8466: switch Inst[1:0] {
4286 0, 5, // 8469: case 0x0: {
4287 OPC_Decode, 231, 5, 138, 1, // 8471: decode to DCBT using decoder 138
4288 // 8471: }
4289 2, 0, // 8476: case 0x2: {
4290 OPC_Decode, 131, 11, 127, // 8478: decode to LHZX using decoder 127
4291 // 8478: }
4292 // 8478: } // switch Inst[1:0]
4293 // 8478: }
4294 9, 9, // 8482: case 0x9: {
4295 OPC_CheckField, 0, 2, 2, // 8484: check Inst[1:0] == 0x2
4296 OPC_Decode, 129, 11, 135, 1, // 8488: decode to LHZUX using decoder 135
4297 // 8488: }
4298 10, 28, // 8493: case 0xa: {
4299 OPC_SwitchField, 0, 2, // 8495: switch Inst[1:0] {
4300 0, 17, // 8498: case 0x0: {
4301 OPC_SwitchField, 23, 3, // 8500: switch Inst[25:23] {
4302 0, 5, // 8503: case 0x0: {
4303 OPC_Decode, 242, 6, 139, 1, // 8505: decode to DST using decoder 139
4304 // 8505: }
4305 4, 0, // 8510: case 0x4: {
4306 OPC_Decode, 248, 6, 139, 1, // 8512: decode to DSTT using decoder 139
4307 // 8512: }
4308 // 8512: } // switch Inst[25:23]
4309 // 8512: }
4310 2, 0, // 8517: case 0x2: {
4311 OPC_Decode, 244, 10, 127, // 8519: decode to LHAX using decoder 127
4312 // 8519: }
4313 // 8519: } // switch Inst[1:0]
4314 // 8519: }
4315 11, 29, // 8523: case 0xb: {
4316 OPC_SwitchField, 0, 2, // 8525: switch Inst[1:0] {
4317 0, 17, // 8528: case 0x0: {
4318 OPC_SwitchField, 23, 3, // 8530: switch Inst[25:23] {
4319 0, 5, // 8533: case 0x0: {
4320 OPC_Decode, 244, 6, 139, 1, // 8535: decode to DSTST using decoder 139
4321 // 8535: }
4322 4, 0, // 8540: case 0x4: {
4323 OPC_Decode, 246, 6, 139, 1, // 8542: decode to DSTSTT using decoder 139
4324 // 8542: }
4325 // 8542: } // switch Inst[25:23]
4326 // 8542: }
4327 2, 0, // 8547: case 0x2: {
4328 OPC_Decode, 242, 10, 135, 1, // 8549: decode to LHAUX using decoder 135
4329 // 8549: }
4330 // 8549: } // switch Inst[1:0]
4331 // 8549: }
4332 12, 8, // 8554: case 0xc: {
4333 OPC_CheckField, 0, 2, 2, // 8556: check Inst[1:0] == 0x2
4334 OPC_Decode, 249, 15, 127, // 8560: decode to STHX using decoder 127
4335 // 8560: }
4336 13, 9, // 8564: case 0xd: {
4337 OPC_CheckField, 0, 2, 2, // 8566: check Inst[1:0] == 0x2
4338 OPC_Decode, 247, 15, 137, 1, // 8570: decode to STHUX using decoder 137
4339 // 8570: }
4340 14, 13, // 8575: case 0xe: {
4341 OPC_CheckField, 21, 5, 0, // 8577: check Inst[25:21] == 0x0
4342 OPC_CheckField, 0, 2, 0, // 8581: check Inst[1:0] == 0x0
4343 OPC_Decode, 228, 5, 134, 1, // 8585: decode to DCBI using decoder 134
4344 // 8585: }
4345 16, 16, // 8590: case 0x10: {
4346 OPC_SwitchField, 0, 2, // 8592: switch Inst[1:0] {
4347 0, 4, // 8595: case 0x0: {
4348 OPC_Decode, 166, 11, 127, // 8597: decode to LWBRX using decoder 127
4349 // 8597: }
4350 2, 0, // 8601: case 0x2: {
4351 OPC_Decode, 233, 10, 140, 1, // 8603: decode to LFSX using decoder 140
4352 // 8603: }
4353 // 8603: } // switch Inst[1:0]
4354 // 8603: }
4355 17, 20, // 8608: case 0x11: {
4356 OPC_SwitchField, 0, 2, // 8610: switch Inst[1:0] {
4357 0, 8, // 8613: case 0x0: {
4358 OPC_CheckField, 11, 15, 0, // 8615: check Inst[25:11] == 0x0
4359 OPC_Decode, 140, 17, 0, // 8619: decode to TLBSYNC using decoder 0
4360 // 8619: }
4361 2, 0, // 8623: case 0x2: {
4362 OPC_Decode, 232, 10, 141, 1, // 8625: decode to LFSUX using decoder 141
4363 // 8625: }
4364 // 8625: } // switch Inst[1:0]
4365 // 8625: }
4366 18, 44, // 8630: case 0x12: {
4367 OPC_SwitchField, 0, 2, // 8632: switch Inst[1:0] {
4368 0, 32, // 8635: case 0x0: {
4369 OPC_CheckField, 11, 5, 0, // 8637: check Inst[15:11] == 0x0
4370 OPC_CheckField, 18, 3, 0, // 8641: check Inst[20:18] == 0x0
4371 OPC_CheckField, 24, 2, 0, // 8645: check Inst[25:24] == 0x0
4372 OPC_Scope, 13, // 8649: try {
4373 OPC_CheckField, 16, 2, 0, // 8651: check Inst[17:16] == 0x0
4374 OPC_CheckField, 23, 1, 0, // 8655: check Inst[23] == 0x0
4375 OPC_Decode, 225, 16, 142, 1, // 8659: decode to SYNC using decoder 142
4376 // 8659: } else try {
4377 OPC_Decode, 226, 16, 143, 1, // 8664: decode to SYNCP10 using decoder 143
4378 // 8664: }
4379 // 8664: }
4380 2, 0, // 8669: case 0x2: {
4381 OPC_Decode, 225, 10, 144, 1, // 8671: decode to LFDX using decoder 144
4382 // 8671: }
4383 // 8671: } // switch Inst[1:0]
4384 // 8671: }
4385 19, 9, // 8676: case 0x13: {
4386 OPC_CheckField, 0, 2, 2, // 8678: check Inst[1:0] == 0x2
4387 OPC_Decode, 224, 10, 145, 1, // 8682: decode to LFDUX using decoder 145
4388 // 8682: }
4389 20, 16, // 8687: case 0x14: {
4390 OPC_SwitchField, 0, 2, // 8689: switch Inst[1:0] {
4391 0, 4, // 8692: case 0x0: {
4392 OPC_Decode, 140, 16, 127, // 8694: decode to STWBRX using decoder 127
4393 // 8694: }
4394 2, 0, // 8698: case 0x2: {
4395 OPC_Decode, 236, 15, 140, 1, // 8700: decode to STFSX using decoder 140
4396 // 8700: }
4397 // 8700: } // switch Inst[1:0]
4398 // 8700: }
4399 21, 16, // 8705: case 0x15: {
4400 OPC_SwitchField, 0, 2, // 8707: switch Inst[1:0] {
4401 1, 4, // 8710: case 0x1: {
4402 OPC_Decode, 204, 15, 127, // 8712: decode to STBCX using decoder 127
4403 // 8712: }
4404 2, 0, // 8716: case 0x2: {
4405 OPC_Decode, 235, 15, 146, 1, // 8718: decode to STFSUX using decoder 146
4406 // 8718: }
4407 // 8718: } // switch Inst[1:0]
4408 // 8718: }
4409 22, 16, // 8723: case 0x16: {
4410 OPC_SwitchField, 0, 2, // 8725: switch Inst[1:0] {
4411 1, 4, // 8728: case 0x1: {
4412 OPC_Decode, 243, 15, 127, // 8730: decode to STHCX using decoder 127
4413 // 8730: }
4414 2, 0, // 8734: case 0x2: {
4415 OPC_Decode, 229, 15, 144, 1, // 8736: decode to STFDX using decoder 144
4416 // 8736: }
4417 // 8736: } // switch Inst[1:0]
4418 // 8736: }
4419 23, 21, // 8741: case 0x17: {
4420 OPC_SwitchField, 0, 2, // 8743: switch Inst[1:0] {
4421 0, 9, // 8746: case 0x0: {
4422 OPC_CheckField, 21, 5, 0, // 8748: check Inst[25:21] == 0x0
4423 OPC_Decode, 225, 5, 134, 1, // 8752: decode to DCBA using decoder 134
4424 // 8752: }
4425 2, 0, // 8757: case 0x2: {
4426 OPC_Decode, 228, 15, 147, 1, // 8759: decode to STFDUX using decoder 147
4427 // 8759: }
4428 // 8759: } // switch Inst[1:0]
4429 // 8759: }
4430 24, 8, // 8764: case 0x18: {
4431 OPC_CheckField, 0, 2, 0, // 8766: check Inst[1:0] == 0x0
4432 OPC_Decode, 249, 10, 127, // 8770: decode to LHBRX using decoder 127
4433 // 8770: }
4434 25, 32, // 8774: case 0x19: {
4435 OPC_SwitchField, 23, 3, // 8776: switch Inst[25:23] {
4436 0, 13, // 8779: case 0x0: {
4437 OPC_CheckField, 11, 10, 0, // 8781: check Inst[20:11] == 0x0
4438 OPC_CheckField, 0, 2, 0, // 8785: check Inst[1:0] == 0x0
4439 OPC_Decode, 240, 6, 148, 1, // 8789: decode to DSS using decoder 148
4440 // 8789: }
4441 4, 0, // 8794: case 0x4: {
4442 OPC_CheckField, 11, 12, 0, // 8796: check Inst[22:11] == 0x0
4443 OPC_CheckField, 0, 2, 0, // 8800: check Inst[1:0] == 0x0
4444 OPC_Decode, 241, 6, 0, // 8804: decode to DSSALL using decoder 0
4445 // 8804: }
4446 // 8804: } // switch Inst[25:23]
4447 // 8804: }
4448 26, 35, // 8808: case 0x1a: {
4449 OPC_SwitchField, 1, 1, // 8810: switch Inst[1] {
4450 0, 19, // 8813: case 0x0: {
4451 OPC_Scope, 12, // 8815: try {
4452 OPC_CheckField, 0, 1, 0, // 8817: check Inst[0] == 0x0
4453 OPC_CheckField, 11, 15, 0, // 8821: check Inst[25:11] == 0x0
4454 OPC_Decode, 165, 9, 0, // 8825: decode to EnforceIEIO using decoder 0
4455 // 8825: } else try {
4456 OPC_Decode, 217, 11, 149, 1, // 8829: decode to MBAR using decoder 149
4457 // 8829: }
4458 // 8829: }
4459 1, 0, // 8834: case 0x1: {
4460 OPC_CheckField, 0, 1, 0, // 8836: check Inst[0] == 0x0
4461 OPC_Decode, 228, 10, 144, 1, // 8840: decode to LFIWAX using decoder 144
4462 // 8840: }
4463 // 8840: } // switch Inst[1]
4464 // 8840: }
4465 27, 20, // 8845: case 0x1b: {
4466 OPC_SwitchField, 0, 2, // 8847: switch Inst[1:0] {
4467 0, 8, // 8850: case 0x0: {
4468 OPC_CheckField, 11, 15, 0, // 8852: check Inst[25:11] == 0x0
4469 OPC_Decode, 134, 12, 0, // 8856: decode to MSGSYNC using decoder 0
4470 // 8856: }
4471 2, 0, // 8860: case 0x2: {
4472 OPC_Decode, 229, 10, 144, 1, // 8862: decode to LFIWZX using decoder 144
4473 // 8862: }
4474 // 8862: } // switch Inst[1:0]
4475 // 8862: }
4476 28, 8, // 8867: case 0x1c: {
4477 OPC_CheckField, 0, 2, 0, // 8869: check Inst[1:0] == 0x0
4478 OPC_Decode, 241, 15, 127, // 8873: decode to STHBRX using decoder 127
4479 // 8873: }
4480 30, 21, // 8877: case 0x1e: {
4481 OPC_SwitchField, 0, 2, // 8879: switch Inst[1:0] {
4482 0, 9, // 8882: case 0x0: {
4483 OPC_CheckField, 21, 5, 0, // 8884: check Inst[25:21] == 0x0
4484 OPC_Decode, 174, 10, 134, 1, // 8888: decode to ICBI using decoder 134
4485 // 8888: }
4486 2, 0, // 8893: case 0x2: {
4487 OPC_Decode, 232, 15, 144, 1, // 8895: decode to STFIWX using decoder 144
4488 // 8895: }
4489 // 8895: } // switch Inst[1:0]
4490 // 8895: }
4491 31, 0, // 8900: case 0x1f: {
4492 OPC_SwitchField, 21, 5, // 8902: switch Inst[25:21] {
4493 0, 9, // 8905: case 0x0: {
4494 OPC_CheckField, 0, 2, 0, // 8907: check Inst[1:0] == 0x0
4495 OPC_Decode, 235, 5, 134, 1, // 8911: decode to DCBZ using decoder 134
4496 // 8911: }
4497 1, 0, // 8916: case 0x1: {
4498 OPC_CheckField, 0, 2, 0, // 8918: check Inst[1:0] == 0x0
4499 OPC_Decode, 237, 5, 134, 1, // 8922: decode to DCBZL using decoder 134
4500 // 8922: }
4501 // 8922: } // switch Inst[25:21]
4502 // 8922: }
4503 // 8922: } // switch Inst[10:6]
4504 // 8922: }
4505 12, 79, // 8927: case 0xc: {
4506 OPC_SwitchField, 6, 5, // 8929: switch Inst[10:6] {
4507 0, 17, // 8932: case 0x0: {
4508 OPC_SwitchField, 0, 2, // 8934: switch Inst[1:0] {
4509 0, 5, // 8937: case 0x0: {
4510 OPC_Decode, 165, 15, 150, 1, // 8939: decode to SLW using decoder 150
4511 // 8939: }
4512 1, 0, // 8944: case 0x1: {
4513 OPC_Decode, 168, 15, 150, 1, // 8946: decode to SLW_rec using decoder 150
4514 // 8946: }
4515 // 8946: } // switch Inst[1:0]
4516 // 8946: }
4517 16, 17, // 8951: case 0x10: {
4518 OPC_SwitchField, 0, 2, // 8953: switch Inst[1:0] {
4519 0, 5, // 8956: case 0x0: {
4520 OPC_Decode, 197, 15, 150, 1, // 8958: decode to SRW using decoder 150
4521 // 8958: }
4522 1, 0, // 8963: case 0x1: {
4523 OPC_Decode, 200, 15, 150, 1, // 8965: decode to SRW_rec using decoder 150
4524 // 8965: }
4525 // 8965: } // switch Inst[1:0]
4526 // 8965: }
4527 24, 17, // 8970: case 0x18: {
4528 OPC_SwitchField, 0, 2, // 8972: switch Inst[1:0] {
4529 0, 5, // 8975: case 0x0: {
4530 OPC_Decode, 187, 15, 150, 1, // 8977: decode to SRAW using decoder 150
4531 // 8977: }
4532 1, 0, // 8982: case 0x1: {
4533 OPC_Decode, 194, 15, 150, 1, // 8984: decode to SRAW_rec using decoder 150
4534 // 8984: }
4535 // 8984: } // switch Inst[1:0]
4536 // 8984: }
4537 25, 0, // 8989: case 0x19: {
4538 OPC_SwitchField, 0, 2, // 8991: switch Inst[1:0] {
4539 0, 5, // 8994: case 0x0: {
4540 OPC_Decode, 190, 15, 151, 1, // 8996: decode to SRAWI using decoder 151
4541 // 8996: }
4542 1, 0, // 9001: case 0x1: {
4543 OPC_Decode, 193, 15, 151, 1, // 9003: decode to SRAWI_rec using decoder 151
4544 // 9003: }
4545 // 9003: } // switch Inst[1:0]
4546 // 9003: }
4547 // 9003: } // switch Inst[10:6]
4548 // 9003: }
4549 13, 155, 3, // 9008: case 0xd: {
4550 OPC_SwitchField, 6, 5, // 9011: switch Inst[10:6] {
4551 0, 39, // 9014: case 0x0: {
4552 OPC_SwitchField, 0, 2, // 9016: switch Inst[1:0] {
4553 0, 9, // 9019: case 0x0: {
4554 OPC_CheckField, 11, 5, 0, // 9021: check Inst[15:11] == 0x0
4555 OPC_Decode, 190, 5, 152, 1, // 9025: decode to CNTLZW using decoder 152
4556 // 9025: }
4557 1, 9, // 9030: case 0x1: {
4558 OPC_CheckField, 11, 5, 0, // 9032: check Inst[15:11] == 0x0
4559 OPC_Decode, 193, 5, 152, 1, // 9036: decode to CNTLZW_rec using decoder 152
4560 // 9036: }
4561 2, 5, // 9041: case 0x2: {
4562 OPC_Decode, 163, 15, 153, 1, // 9043: decode to SLD using decoder 153
4563 // 9043: }
4564 3, 0, // 9048: case 0x3: {
4565 OPC_Decode, 164, 15, 153, 1, // 9050: decode to SLD_rec using decoder 153
4566 // 9050: }
4567 // 9050: } // switch Inst[1:0]
4568 // 9050: }
4569 1, 32, // 9055: case 0x1: {
4570 OPC_SwitchField, 0, 2, // 9057: switch Inst[1:0] {
4571 0, 9, // 9060: case 0x0: {
4572 OPC_CheckField, 11, 5, 0, // 9062: check Inst[15:11] == 0x0
4573 OPC_Decode, 187, 5, 154, 1, // 9066: decode to CNTLZD using decoder 154
4574 // 9066: }
4575 1, 9, // 9071: case 0x1: {
4576 OPC_CheckField, 11, 5, 0, // 9073: check Inst[15:11] == 0x0
4577 OPC_Decode, 189, 5, 154, 1, // 9077: decode to CNTLZD_rec using decoder 154
4578 // 9077: }
4579 2, 0, // 9082: case 0x2: {
4580 OPC_Decode, 188, 5, 155, 1, // 9084: decode to CNTLZDM using decoder 155
4581 // 9084: }
4582 // 9084: } // switch Inst[1:0]
4583 // 9084: }
4584 3, 13, // 9089: case 0x3: {
4585 OPC_CheckField, 11, 5, 0, // 9091: check Inst[15:11] == 0x0
4586 OPC_CheckField, 0, 2, 0, // 9095: check Inst[1:0] == 0x0
4587 OPC_Decode, 135, 14, 152, 1, // 9099: decode to POPCNTB using decoder 152
4588 // 9099: }
4589 4, 13, // 9104: case 0x4: {
4590 OPC_CheckField, 11, 5, 0, // 9106: check Inst[15:11] == 0x0
4591 OPC_CheckField, 0, 2, 2, // 9110: check Inst[1:0] == 0x2
4592 OPC_Decode, 166, 5, 152, 1, // 9114: decode to BRW using decoder 152
4593 // 9114: }
4594 5, 13, // 9119: case 0x5: {
4595 OPC_CheckField, 11, 5, 0, // 9121: check Inst[15:11] == 0x0
4596 OPC_CheckField, 0, 2, 2, // 9125: check Inst[1:0] == 0x2
4597 OPC_Decode, 162, 5, 154, 1, // 9129: decode to BRD using decoder 154
4598 // 9129: }
4599 6, 13, // 9134: case 0x6: {
4600 OPC_CheckField, 11, 5, 0, // 9136: check Inst[15:11] == 0x0
4601 OPC_CheckField, 0, 2, 2, // 9140: check Inst[1:0] == 0x2
4602 OPC_Decode, 163, 5, 152, 1, // 9144: decode to BRH using decoder 152
4603 // 9144: }
4604 8, 13, // 9149: case 0x8: {
4605 OPC_CheckField, 11, 5, 0, // 9151: check Inst[15:11] == 0x0
4606 OPC_CheckField, 0, 2, 0, // 9155: check Inst[1:0] == 0x0
4607 OPC_Decode, 170, 5, 152, 1, // 9159: decode to CDTBCD using decoder 152
4608 // 9159: }
4609 9, 13, // 9164: case 0x9: {
4610 OPC_CheckField, 11, 5, 0, // 9166: check Inst[15:11] == 0x0
4611 OPC_CheckField, 0, 2, 0, // 9170: check Inst[1:0] == 0x0
4612 OPC_Decode, 168, 5, 152, 1, // 9174: decode to CBCDTD using decoder 152
4613 // 9174: }
4614 11, 13, // 9179: case 0xb: {
4615 OPC_CheckField, 11, 5, 0, // 9181: check Inst[15:11] == 0x0
4616 OPC_CheckField, 0, 2, 0, // 9185: check Inst[1:0] == 0x0
4617 OPC_Decode, 138, 14, 152, 1, // 9189: decode to POPCNTW using decoder 152
4618 // 9189: }
4619 15, 13, // 9194: case 0xf: {
4620 OPC_CheckField, 11, 5, 0, // 9196: check Inst[15:11] == 0x0
4621 OPC_CheckField, 0, 2, 0, // 9200: check Inst[1:0] == 0x0
4622 OPC_Decode, 137, 14, 154, 1, // 9204: decode to POPCNTD using decoder 154
4623 // 9204: }
4624 16, 39, // 9209: case 0x10: {
4625 OPC_SwitchField, 0, 2, // 9211: switch Inst[1:0] {
4626 0, 9, // 9214: case 0x0: {
4627 OPC_CheckField, 11, 5, 0, // 9216: check Inst[15:11] == 0x0
4628 OPC_Decode, 197, 5, 152, 1, // 9220: decode to CNTTZW using decoder 152
4629 // 9220: }
4630 1, 9, // 9225: case 0x1: {
4631 OPC_CheckField, 11, 5, 0, // 9227: check Inst[15:11] == 0x0
4632 OPC_Decode, 200, 5, 152, 1, // 9231: decode to CNTTZW_rec using decoder 152
4633 // 9231: }
4634 2, 5, // 9236: case 0x2: {
4635 OPC_Decode, 195, 15, 153, 1, // 9238: decode to SRD using decoder 153
4636 // 9238: }
4637 3, 0, // 9243: case 0x3: {
4638 OPC_Decode, 196, 15, 153, 1, // 9245: decode to SRD_rec using decoder 153
4639 // 9245: }
4640 // 9245: } // switch Inst[1:0]
4641 // 9245: }
4642 17, 32, // 9250: case 0x11: {
4643 OPC_SwitchField, 0, 2, // 9252: switch Inst[1:0] {
4644 0, 9, // 9255: case 0x0: {
4645 OPC_CheckField, 11, 5, 0, // 9257: check Inst[15:11] == 0x0
4646 OPC_Decode, 194, 5, 154, 1, // 9261: decode to CNTTZD using decoder 154
4647 // 9261: }
4648 1, 9, // 9266: case 0x1: {
4649 OPC_CheckField, 11, 5, 0, // 9268: check Inst[15:11] == 0x0
4650 OPC_Decode, 196, 5, 154, 1, // 9272: decode to CNTTZD_rec using decoder 154
4651 // 9272: }
4652 2, 0, // 9277: case 0x2: {
4653 OPC_Decode, 195, 5, 155, 1, // 9279: decode to CNTTZDM using decoder 155
4654 // 9279: }
4655 // 9279: } // switch Inst[1:0]
4656 // 9279: }
4657 24, 17, // 9284: case 0x18: {
4658 OPC_SwitchField, 0, 2, // 9286: switch Inst[1:0] {
4659 0, 5, // 9289: case 0x0: {
4660 OPC_Decode, 182, 15, 153, 1, // 9291: decode to SRAD using decoder 153
4661 // 9291: }
4662 1, 0, // 9296: case 0x1: {
4663 OPC_Decode, 186, 15, 153, 1, // 9298: decode to SRAD_rec using decoder 153
4664 // 9298: }
4665 // 9298: } // switch Inst[1:0]
4666 // 9298: }
4667 25, 17, // 9303: case 0x19: {
4668 OPC_SwitchField, 0, 1, // 9305: switch Inst[0] {
4669 0, 5, // 9308: case 0x0: {
4670 OPC_Decode, 183, 15, 156, 1, // 9310: decode to SRADI using decoder 156
4671 // 9310: }
4672 1, 0, // 9315: case 0x1: {
4673 OPC_Decode, 185, 15, 156, 1, // 9317: decode to SRADI_rec using decoder 156
4674 // 9317: }
4675 // 9317: } // switch Inst[0]
4676 // 9317: }
4677 27, 17, // 9322: case 0x1b: {
4678 OPC_SwitchField, 0, 1, // 9324: switch Inst[0] {
4679 0, 5, // 9327: case 0x0: {
4680 OPC_Decode, 157, 9, 156, 1, // 9329: decode to EXTSWSLI using decoder 156
4681 // 9329: }
4682 1, 0, // 9334: case 0x1: {
4683 OPC_Decode, 160, 9, 156, 1, // 9336: decode to EXTSWSLI_rec using decoder 156
4684 // 9336: }
4685 // 9336: } // switch Inst[0]
4686 // 9336: }
4687 28, 25, // 9341: case 0x1c: {
4688 OPC_SwitchField, 0, 2, // 9343: switch Inst[1:0] {
4689 0, 9, // 9346: case 0x0: {
4690 OPC_CheckField, 11, 5, 0, // 9348: check Inst[15:11] == 0x0
4691 OPC_Decode, 151, 9, 152, 1, // 9352: decode to EXTSH using decoder 152
4692 // 9352: }
4693 1, 0, // 9357: case 0x1: {
4694 OPC_CheckField, 11, 5, 0, // 9359: check Inst[15:11] == 0x0
4695 OPC_Decode, 155, 9, 152, 1, // 9363: decode to EXTSH_rec using decoder 152
4696 // 9363: }
4697 // 9363: } // switch Inst[1:0]
4698 // 9363: }
4699 29, 25, // 9368: case 0x1d: {
4700 OPC_SwitchField, 0, 2, // 9370: switch Inst[1:0] {
4701 0, 9, // 9373: case 0x0: {
4702 OPC_CheckField, 11, 5, 0, // 9375: check Inst[15:11] == 0x0
4703 OPC_Decode, 146, 9, 152, 1, // 9379: decode to EXTSB using decoder 152
4704 // 9379: }
4705 1, 0, // 9384: case 0x1: {
4706 OPC_CheckField, 11, 5, 0, // 9386: check Inst[15:11] == 0x0
4707 OPC_Decode, 150, 9, 152, 1, // 9390: decode to EXTSB_rec using decoder 152
4708 // 9390: }
4709 // 9390: } // switch Inst[1:0]
4710 // 9390: }
4711 30, 0, // 9395: case 0x1e: {
4712 OPC_SwitchField, 0, 2, // 9397: switch Inst[1:0] {
4713 0, 9, // 9400: case 0x0: {
4714 OPC_CheckField, 11, 5, 0, // 9402: check Inst[15:11] == 0x0
4715 OPC_Decode, 156, 9, 154, 1, // 9406: decode to EXTSW using decoder 154
4716 // 9406: }
4717 1, 0, // 9411: case 0x1: {
4718 OPC_CheckField, 11, 5, 0, // 9413: check Inst[15:11] == 0x0
4719 OPC_Decode, 164, 9, 154, 1, // 9417: decode to EXTSW_rec using decoder 154
4720 // 9417: }
4721 // 9417: } // switch Inst[1:0]
4722 // 9417: }
4723 // 9417: } // switch Inst[10:6]
4724 // 9417: }
4725 14, 210, 1, // 9422: case 0xe: {
4726 OPC_SwitchField, 6, 5, // 9425: switch Inst[10:6] {
4727 0, 17, // 9428: case 0x0: {
4728 OPC_SwitchField, 0, 2, // 9430: switch Inst[1:0] {
4729 0, 5, // 9433: case 0x0: {
4730 OPC_Decode, 234, 3, 150, 1, // 9435: decode to AND using decoder 150
4731 // 9435: }
4732 1, 0, // 9440: case 0x1: {
4733 OPC_Decode, 249, 3, 150, 1, // 9442: decode to AND_rec using decoder 150
4734 // 9442: }
4735 // 9442: } // switch Inst[1:0]
4736 // 9442: }
4737 1, 17, // 9447: case 0x1: {
4738 OPC_SwitchField, 0, 2, // 9449: switch Inst[1:0] {
4739 0, 5, // 9452: case 0x0: {
4740 OPC_Decode, 237, 3, 150, 1, // 9454: decode to ANDC using decoder 150
4741 // 9454: }
4742 1, 0, // 9459: case 0x1: {
4743 OPC_Decode, 240, 3, 150, 1, // 9461: decode to ANDC_rec using decoder 150
4744 // 9461: }
4745 // 9461: } // switch Inst[1:0]
4746 // 9461: }
4747 3, 17, // 9466: case 0x3: {
4748 OPC_SwitchField, 0, 2, // 9468: switch Inst[1:0] {
4749 0, 5, // 9471: case 0x0: {
4750 OPC_Decode, 219, 12, 150, 1, // 9473: decode to NOR using decoder 150
4751 // 9473: }
4752 1, 0, // 9478: case 0x1: {
4753 OPC_Decode, 222, 12, 150, 1, // 9480: decode to NOR_rec using decoder 150
4754 // 9480: }
4755 // 9480: } // switch Inst[1:0]
4756 // 9480: }
4757 4, 9, // 9485: case 0x4: {
4758 OPC_CheckField, 0, 2, 0, // 9487: check Inst[1:0] == 0x0
4759 OPC_Decode, 244, 12, 155, 1, // 9491: decode to PDEPD using decoder 155
4760 // 9491: }
4761 5, 9, // 9496: case 0x5: {
4762 OPC_CheckField, 0, 2, 0, // 9498: check Inst[1:0] == 0x0
4763 OPC_Decode, 245, 12, 155, 1, // 9502: decode to PEXTD using decoder 155
4764 // 9502: }
4765 6, 9, // 9507: case 0x6: {
4766 OPC_CheckField, 0, 2, 0, // 9509: check Inst[1:0] == 0x0
4767 OPC_Decode, 172, 5, 155, 1, // 9513: decode to CFUGED using decoder 155
4768 // 9513: }
4769 7, 9, // 9518: case 0x7: {
4770 OPC_CheckField, 0, 2, 0, // 9520: check Inst[1:0] == 0x0
4771 OPC_Decode, 161, 5, 155, 1, // 9524: decode to BPERMD using decoder 155
4772 // 9524: }
4773 8, 17, // 9529: case 0x8: {
4774 OPC_SwitchField, 0, 2, // 9531: switch Inst[1:0] {
4775 0, 5, // 9534: case 0x0: {
4776 OPC_Decode, 203, 7, 150, 1, // 9536: decode to EQV using decoder 150
4777 // 9536: }
4778 1, 0, // 9541: case 0x1: {
4779 OPC_Decode, 206, 7, 150, 1, // 9543: decode to EQV_rec using decoder 150
4780 // 9543: }
4781 // 9543: } // switch Inst[1:0]
4782 // 9543: }
4783 9, 17, // 9548: case 0x9: {
4784 OPC_SwitchField, 0, 2, // 9550: switch Inst[1:0] {
4785 0, 5, // 9553: case 0x0: {
4786 OPC_Decode, 179, 20, 150, 1, // 9555: decode to XOR using decoder 150
4787 // 9555: }
4788 1, 0, // 9560: case 0x1: {
4789 OPC_Decode, 186, 20, 150, 1, // 9562: decode to XOR_rec using decoder 150
4790 // 9562: }
4791 // 9562: } // switch Inst[1:0]
4792 // 9562: }
4793 12, 17, // 9567: case 0xc: {
4794 OPC_SwitchField, 0, 2, // 9569: switch Inst[1:0] {
4795 0, 5, // 9572: case 0x0: {
4796 OPC_Decode, 226, 12, 150, 1, // 9574: decode to ORC using decoder 150
4797 // 9574: }
4798 1, 0, // 9579: case 0x1: {
4799 OPC_Decode, 229, 12, 150, 1, // 9581: decode to ORC_rec using decoder 150
4800 // 9581: }
4801 // 9581: } // switch Inst[1:0]
4802 // 9581: }
4803 13, 17, // 9586: case 0xd: {
4804 OPC_SwitchField, 0, 2, // 9588: switch Inst[1:0] {
4805 0, 5, // 9591: case 0x0: {
4806 OPC_Decode, 223, 12, 150, 1, // 9593: decode to OR using decoder 150
4807 // 9593: }
4808 1, 0, // 9598: case 0x1: {
4809 OPC_Decode, 234, 12, 150, 1, // 9600: decode to OR_rec using decoder 150
4810 // 9600: }
4811 // 9600: } // switch Inst[1:0]
4812 // 9600: }
4813 14, 17, // 9605: case 0xe: {
4814 OPC_SwitchField, 0, 2, // 9607: switch Inst[1:0] {
4815 0, 5, // 9610: case 0x0: {
4816 OPC_Decode, 203, 12, 150, 1, // 9612: decode to NAND using decoder 150
4817 // 9612: }
4818 1, 0, // 9617: case 0x1: {
4819 OPC_Decode, 206, 12, 150, 1, // 9619: decode to NAND_rec using decoder 150
4820 // 9619: }
4821 // 9619: } // switch Inst[1:0]
4822 // 9619: }
4823 15, 0, // 9624: case 0xf: {
4824 OPC_CheckField, 0, 2, 0, // 9626: check Inst[1:0] == 0x0
4825 OPC_Decode, 174, 5, 150, 1, // 9630: decode to CMPB using decoder 150
4826 // 9630: }
4827 // 9630: } // switch Inst[10:6]
4828 // 9630: }
4829 15, 0, // 9635: case 0xf: {
4830 OPC_SwitchField, 6, 5, // 9637: switch Inst[10:6] {
4831 0, 39, // 9640: case 0x0: {
4832 OPC_SwitchField, 0, 2, // 9642: switch Inst[1:0] {
4833 0, 28, // 9645: case 0x0: {
4834 OPC_CheckField, 11, 5, 0, // 9647: check Inst[15:11] == 0x0
4835 OPC_CheckField, 18, 3, 0, // 9651: check Inst[20:18] == 0x0
4836 OPC_CheckField, 23, 3, 0, // 9655: check Inst[25:23] == 0x0
4837 OPC_Scope, 9, // 9659: try {
4838 OPC_CheckField, 16, 2, 0, // 9661: check Inst[17:16] == 0x0
4839 OPC_Decode, 175, 20, 142, 1, // 9665: decode to WAIT using decoder 142
4840 // 9665: } else try {
4841 OPC_Decode, 176, 20, 157, 1, // 9670: decode to WAITP10 using decoder 157
4842 // 9670: }
4843 // 9670: }
4844 2, 0, // 9675: case 0x2: {
4845 OPC_Decode, 168, 11, 127, // 9677: decode to LWEPX using decoder 127
4846 // 9677: }
4847 // 9677: } // switch Inst[1:0]
4848 // 9677: }
4849 1, 13, // 9681: case 0x1: {
4850 OPC_CheckField, 21, 5, 0, // 9683: check Inst[25:21] == 0x0
4851 OPC_CheckField, 0, 2, 2, // 9687: check Inst[1:0] == 0x2
4852 OPC_Decode, 230, 5, 134, 1, // 9691: decode to DCBSTEP using decoder 134
4853 // 9691: }
4854 2, 8, // 9696: case 0x2: {
4855 OPC_CheckField, 0, 2, 2, // 9698: check Inst[1:0] == 0x2
4856 OPC_Decode, 188, 10, 127, // 9702: decode to LBEPX using decoder 127
4857 // 9702: }
4858 3, 13, // 9706: case 0x3: {
4859 OPC_CheckField, 21, 5, 0, // 9708: check Inst[25:21] == 0x0
4860 OPC_CheckField, 0, 2, 2, // 9712: check Inst[1:0] == 0x2
4861 OPC_Decode, 227, 5, 134, 1, // 9716: decode to DCBFEP using decoder 134
4862 // 9716: }
4863 4, 8, // 9721: case 0x4: {
4864 OPC_CheckField, 0, 2, 2, // 9723: check Inst[1:0] == 0x2
4865 OPC_Decode, 143, 16, 127, // 9727: decode to STWEPX using decoder 127
4866 // 9727: }
4867 6, 8, // 9731: case 0x6: {
4868 OPC_CheckField, 0, 2, 2, // 9733: check Inst[1:0] == 0x2
4869 OPC_Decode, 205, 15, 127, // 9737: decode to STBEPX using decoder 127
4870 // 9737: }
4871 7, 9, // 9741: case 0x7: {
4872 OPC_CheckField, 0, 2, 2, // 9743: check Inst[1:0] == 0x2
4873 OPC_Decode, 234, 5, 158, 1, // 9747: decode to DCBTSTEP using decoder 158
4874 // 9747: }
4875 8, 8, // 9752: case 0x8: {
4876 OPC_CheckField, 0, 2, 2, // 9754: check Inst[1:0] == 0x2
4877 OPC_Decode, 251, 10, 127, // 9758: decode to LHEPX using decoder 127
4878 // 9758: }
4879 9, 9, // 9762: case 0x9: {
4880 OPC_CheckField, 0, 2, 2, // 9764: check Inst[1:0] == 0x2
4881 OPC_Decode, 232, 5, 158, 1, // 9768: decode to DCBTEP using decoder 158
4882 // 9768: }
4883 12, 8, // 9773: case 0xc: {
4884 OPC_CheckField, 0, 2, 2, // 9775: check Inst[1:0] == 0x2
4885 OPC_Decode, 244, 15, 127, // 9779: decode to STHEPX using decoder 127
4886 // 9779: }
4887 18, 9, // 9783: case 0x12: {
4888 OPC_CheckField, 0, 2, 2, // 9785: check Inst[1:0] == 0x2
4889 OPC_Decode, 222, 10, 144, 1, // 9789: decode to LFDEPX using decoder 144
4890 // 9789: }
4891 22, 9, // 9794: case 0x16: {
4892 OPC_CheckField, 0, 2, 2, // 9796: check Inst[1:0] == 0x2
4893 OPC_Decode, 226, 15, 144, 1, // 9800: decode to STFDEPX using decoder 144
4894 // 9800: }
4895 30, 13, // 9805: case 0x1e: {
4896 OPC_CheckField, 21, 5, 0, // 9807: check Inst[25:21] == 0x0
4897 OPC_CheckField, 0, 2, 2, // 9811: check Inst[1:0] == 0x2
4898 OPC_Decode, 175, 10, 134, 1, // 9815: decode to ICBIEP using decoder 134
4899 // 9815: }
4900 31, 0, // 9820: case 0x1f: {
4901 OPC_SwitchField, 21, 5, // 9822: switch Inst[25:21] {
4902 0, 9, // 9825: case 0x0: {
4903 OPC_CheckField, 0, 2, 2, // 9827: check Inst[1:0] == 0x2
4904 OPC_Decode, 236, 5, 134, 1, // 9831: decode to DCBZEP using decoder 134
4905 // 9831: }
4906 1, 0, // 9836: case 0x1: {
4907 OPC_CheckField, 0, 2, 2, // 9838: check Inst[1:0] == 0x2
4908 OPC_Decode, 238, 5, 134, 1, // 9842: decode to DCBZLEP using decoder 134
4909 // 9842: }
4910 // 9842: } // switch Inst[25:21]
4911 // 9842: }
4912 // 9842: } // switch Inst[10:6]
4913 // 9842: }
4914 // 9842: } // switch Inst[5:2]
4915 // 9842: }
4916 32, 5, // 9847: case 0x20: {
4917 OPC_Decode, 169, 11, 159, 1, // 9849: decode to LWZ using decoder 159
4918 // 9849: }
4919 33, 5, // 9854: case 0x21: {
4920 OPC_Decode, 172, 11, 160, 1, // 9856: decode to LWZU using decoder 160
4921 // 9856: }
4922 34, 5, // 9861: case 0x22: {
4923 OPC_Decode, 189, 10, 159, 1, // 9863: decode to LBZ using decoder 159
4924 // 9863: }
4925 35, 5, // 9868: case 0x23: {
4926 OPC_Decode, 192, 10, 160, 1, // 9870: decode to LBZU using decoder 160
4927 // 9870: }
4928 36, 5, // 9875: case 0x24: {
4929 OPC_Decode, 137, 16, 159, 1, // 9877: decode to STW using decoder 159
4930 // 9877: }
4931 37, 5, // 9882: case 0x25: {
4932 OPC_Decode, 144, 16, 161, 1, // 9884: decode to STWU using decoder 161
4933 // 9884: }
4934 38, 5, // 9889: case 0x26: {
4935 OPC_Decode, 201, 15, 159, 1, // 9891: decode to STB using decoder 159
4936 // 9891: }
4937 39, 5, // 9896: case 0x27: {
4938 OPC_Decode, 206, 15, 161, 1, // 9898: decode to STBU using decoder 161
4939 // 9898: }
4940 40, 5, // 9903: case 0x28: {
4941 OPC_Decode, 252, 10, 159, 1, // 9905: decode to LHZ using decoder 159
4942 // 9905: }
4943 41, 5, // 9910: case 0x29: {
4944 OPC_Decode, 255, 10, 160, 1, // 9912: decode to LHZU using decoder 160
4945 // 9912: }
4946 42, 5, // 9917: case 0x2a: {
4947 OPC_Decode, 236, 10, 159, 1, // 9919: decode to LHA using decoder 159
4948 // 9919: }
4949 43, 5, // 9924: case 0x2b: {
4950 OPC_Decode, 240, 10, 160, 1, // 9926: decode to LHAU using decoder 160
4951 // 9926: }
4952 44, 5, // 9931: case 0x2c: {
4953 OPC_Decode, 239, 15, 159, 1, // 9933: decode to STH using decoder 159
4954 // 9933: }
4955 45, 5, // 9938: case 0x2d: {
4956 OPC_Decode, 245, 15, 161, 1, // 9940: decode to STHU using decoder 161
4957 // 9940: }
4958 46, 5, // 9945: case 0x2e: {
4959 OPC_Decode, 140, 11, 159, 1, // 9947: decode to LMW using decoder 159
4960 // 9947: }
4961 47, 5, // 9952: case 0x2f: {
4962 OPC_Decode, 254, 15, 159, 1, // 9954: decode to STMW using decoder 159
4963 // 9954: }
4964 48, 5, // 9959: case 0x30: {
4965 OPC_Decode, 230, 10, 162, 1, // 9961: decode to LFS using decoder 162
4966 // 9961: }
4967 49, 5, // 9966: case 0x31: {
4968 OPC_Decode, 231, 10, 163, 1, // 9968: decode to LFSU using decoder 163
4969 // 9968: }
4970 50, 5, // 9973: case 0x32: {
4971 OPC_Decode, 221, 10, 164, 1, // 9975: decode to LFD using decoder 164
4972 // 9975: }
4973 51, 5, // 9980: case 0x33: {
4974 OPC_Decode, 223, 10, 165, 1, // 9982: decode to LFDU using decoder 165
4975 // 9982: }
4976 52, 5, // 9987: case 0x34: {
4977 OPC_Decode, 233, 15, 162, 1, // 9989: decode to STFS using decoder 162
4978 // 9989: }
4979 53, 5, // 9994: case 0x35: {
4980 OPC_Decode, 234, 15, 166, 1, // 9996: decode to STFSU using decoder 166
4981 // 9996: }
4982 54, 5, // 10001: case 0x36: {
4983 OPC_Decode, 225, 15, 164, 1, // 10003: decode to STFD using decoder 164
4984 // 10003: }
4985 55, 5, // 10008: case 0x37: {
4986 OPC_Decode, 227, 15, 167, 1, // 10010: decode to STFDU using decoder 167
4987 // 10010: }
4988 56, 9, // 10015: case 0x38: {
4989 OPC_CheckField, 0, 4, 0, // 10017: check Inst[3:0] == 0x0
4990 OPC_Decode, 141, 11, 168, 1, // 10021: decode to LQ using decoder 168
4991 // 10021: }
4992 57, 17, // 10026: case 0x39: {
4993 OPC_SwitchField, 0, 2, // 10028: switch Inst[1:0] {
4994 2, 5, // 10031: case 0x2: {
4995 OPC_Decode, 183, 11, 169, 1, // 10033: decode to LXSD using decoder 169
4996 // 10033: }
4997 3, 0, // 10038: case 0x3: {
4998 OPC_Decode, 189, 11, 169, 1, // 10040: decode to LXSSP using decoder 169
4999 // 10040: }
5000 // 10040: } // switch Inst[1:0]
5001 // 10040: }
5002 58, 24, // 10045: case 0x3a: {
5003 OPC_SwitchField, 0, 2, // 10047: switch Inst[1:0] {
5004 0, 5, // 10050: case 0x0: {
5005 OPC_Decode, 201, 10, 170, 1, // 10052: decode to LD using decoder 170
5006 // 10052: }
5007 1, 5, // 10057: case 0x1: {
5008 OPC_Decode, 209, 10, 171, 1, // 10059: decode to LDU using decoder 171
5009 // 10059: }
5010 2, 0, // 10064: case 0x2: {
5011 OPC_Decode, 153, 11, 170, 1, // 10066: decode to LWA using decoder 170
5012 // 10066: }
5013 // 10066: } // switch Inst[1:0]
5014 // 10066: }
5015 59, 190, 13, // 10071: case 0x3b: {
5016 OPC_SwitchField, 3, 3, // 10074: switch Inst[5:3] {
5017 0, 206, 4, // 10077: case 0x0: {
5018 OPC_SwitchField, 6, 3, // 10080: switch Inst[8:6] {
5019 0, 99, // 10083: case 0x0: {
5020 OPC_SwitchField, 0, 3, // 10085: switch Inst[2:0] {
5021 4, 39, // 10088: case 0x4: {
5022 OPC_SwitchField, 9, 2, // 10090: switch Inst[10:9] {
5023 0, 5, // 10093: case 0x0: {
5024 OPC_Decode, 220, 5, 172, 1, // 10095: decode to DADD using decoder 172
5025 // 10095: }
5026 1, 9, // 10100: case 0x1: {
5027 OPC_CheckField, 16, 5, 0, // 10102: check Inst[20:16] == 0x0
5028 OPC_Decode, 249, 5, 173, 1, // 10106: decode to DCTDP using decoder 173
5029 // 10106: }
5030 2, 5, // 10111: case 0x2: {
5031 OPC_Decode, 250, 6, 172, 1, // 10113: decode to DSUB using decoder 172
5032 // 10113: }
5033 3, 0, // 10118: case 0x3: {
5034 OPC_CheckField, 16, 5, 0, // 10120: check Inst[20:16] == 0x0
5035 OPC_Decode, 230, 6, 173, 1, // 10124: decode to DRSP using decoder 173
5036 // 10124: }
5037 // 10124: } // switch Inst[10:9]
5038 // 10124: }
5039 5, 39, // 10129: case 0x5: {
5040 OPC_SwitchField, 9, 2, // 10131: switch Inst[10:9] {
5041 0, 5, // 10134: case 0x0: {
5042 OPC_Decode, 223, 5, 172, 1, // 10136: decode to DADD_rec using decoder 172
5043 // 10136: }
5044 1, 9, // 10141: case 0x1: {
5045 OPC_CheckField, 16, 5, 0, // 10143: check Inst[20:16] == 0x0
5046 OPC_Decode, 250, 5, 173, 1, // 10147: decode to DCTDP_rec using decoder 173
5047 // 10147: }
5048 2, 5, // 10152: case 0x2: {
5049 OPC_Decode, 253, 6, 172, 1, // 10154: decode to DSUB_rec using decoder 172
5050 // 10154: }
5051 3, 0, // 10159: case 0x3: {
5052 OPC_CheckField, 16, 5, 0, // 10161: check Inst[20:16] == 0x0
5053 OPC_Decode, 231, 6, 173, 1, // 10165: decode to DRSP_rec using decoder 173
5054 // 10165: }
5055 // 10165: } // switch Inst[10:9]
5056 // 10165: }
5057 6, 5, // 10170: case 0x6: {
5058 OPC_Decode, 208, 6, 174, 1, // 10172: decode to DQUA using decoder 174
5059 // 10172: }
5060 7, 0, // 10177: case 0x7: {
5061 OPC_Decode, 215, 6, 174, 1, // 10179: decode to DQUA_rec using decoder 174
5062 // 10179: }
5063 // 10179: } // switch Inst[2:0]
5064 // 10179: }
5065 1, 99, // 10184: case 0x1: {
5066 OPC_SwitchField, 0, 3, // 10186: switch Inst[2:0] {
5067 4, 39, // 10189: case 0x4: {
5068 OPC_SwitchField, 9, 2, // 10191: switch Inst[10:9] {
5069 0, 5, // 10194: case 0x0: {
5070 OPC_Decode, 182, 6, 172, 1, // 10196: decode to DMUL using decoder 172
5071 // 10196: }
5072 1, 9, // 10201: case 0x1: {
5073 OPC_CheckField, 16, 5, 0, // 10203: check Inst[20:16] == 0x0
5074 OPC_Decode, 251, 5, 173, 1, // 10207: decode to DCTFIX using decoder 173
5075 // 10207: }
5076 2, 5, // 10212: case 0x2: {
5077 OPC_Decode, 134, 6, 172, 1, // 10214: decode to DDIV using decoder 172
5078 // 10214: }
5079 3, 0, // 10219: case 0x3: {
5080 OPC_CheckField, 16, 5, 0, // 10221: check Inst[20:16] == 0x0
5081 OPC_Decode, 240, 5, 173, 1, // 10225: decode to DCFFIX using decoder 173
5082 // 10225: }
5083 // 10225: } // switch Inst[10:9]
5084 // 10225: }
5085 5, 39, // 10230: case 0x5: {
5086 OPC_SwitchField, 9, 2, // 10232: switch Inst[10:9] {
5087 0, 5, // 10235: case 0x0: {
5088 OPC_Decode, 185, 6, 172, 1, // 10237: decode to DMUL_rec using decoder 172
5089 // 10237: }
5090 1, 9, // 10242: case 0x1: {
5091 OPC_CheckField, 16, 5, 0, // 10244: check Inst[20:16] == 0x0
5092 OPC_Decode, 255, 5, 173, 1, // 10248: decode to DCTFIX_rec using decoder 173
5093 // 10248: }
5094 2, 5, // 10253: case 0x2: {
5095 OPC_Decode, 137, 6, 172, 1, // 10255: decode to DDIV_rec using decoder 172
5096 // 10255: }
5097 3, 0, // 10260: case 0x3: {
5098 OPC_CheckField, 16, 5, 0, // 10262: check Inst[20:16] == 0x0
5099 OPC_Decode, 244, 5, 173, 1, // 10266: decode to DCFFIX_rec using decoder 173
5100 // 10266: }
5101 // 10266: } // switch Inst[10:9]
5102 // 10266: }
5103 6, 5, // 10271: case 0x6: {
5104 OPC_Decode, 226, 6, 174, 1, // 10273: decode to DRRND using decoder 174
5105 // 10273: }
5106 7, 0, // 10278: case 0x7: {
5107 OPC_Decode, 229, 6, 174, 1, // 10280: decode to DRRND_rec using decoder 174
5108 // 10280: }
5109 // 10280: } // switch Inst[2:0]
5110 // 10280: }
5111 2, 95, // 10285: case 0x2: {
5112 OPC_SwitchField, 0, 3, // 10287: switch Inst[2:0] {
5113 4, 37, // 10290: case 0x4: {
5114 OPC_SwitchField, 9, 1, // 10292: switch Inst[9] {
5115 0, 5, // 10295: case 0x0: {
5116 OPC_Decode, 232, 6, 175, 1, // 10297: decode to DSCLI using decoder 175
5117 // 10297: }
5118 1, 0, // 10302: case 0x1: {
5119 OPC_SwitchField, 10, 1, // 10304: switch Inst[10] {
5120 0, 9, // 10307: case 0x0: {
5121 OPC_CheckField, 16, 3, 0, // 10309: check Inst[18:16] == 0x0
5122 OPC_Decode, 130, 6, 176, 1, // 10313: decode to DDEDPD using decoder 176
5123 // 10313: }
5124 1, 0, // 10318: case 0x1: {
5125 OPC_CheckField, 16, 4, 0, // 10320: check Inst[19:16] == 0x0
5126 OPC_Decode, 138, 6, 177, 1, // 10324: decode to DENBCD using decoder 177
5127 // 10324: }
5128 // 10324: } // switch Inst[10]
5129 // 10324: }
5130 // 10324: } // switch Inst[9]
5131 // 10324: }
5132 5, 37, // 10329: case 0x5: {
5133 OPC_SwitchField, 9, 1, // 10331: switch Inst[9] {
5134 0, 5, // 10334: case 0x0: {
5135 OPC_Decode, 235, 6, 175, 1, // 10336: decode to DSCLI_rec using decoder 175
5136 // 10336: }
5137 1, 0, // 10341: case 0x1: {
5138 OPC_SwitchField, 10, 1, // 10343: switch Inst[10] {
5139 0, 9, // 10346: case 0x0: {
5140 OPC_CheckField, 16, 3, 0, // 10348: check Inst[18:16] == 0x0
5141 OPC_Decode, 133, 6, 176, 1, // 10352: decode to DDEDPD_rec using decoder 176
5142 // 10352: }
5143 1, 0, // 10357: case 0x1: {
5144 OPC_CheckField, 16, 4, 0, // 10359: check Inst[19:16] == 0x0
5145 OPC_Decode, 141, 6, 177, 1, // 10363: decode to DENBCD_rec using decoder 177
5146 // 10363: }
5147 // 10363: } // switch Inst[10]
5148 // 10363: }
5149 // 10363: } // switch Inst[9]
5150 // 10363: }
5151 6, 5, // 10368: case 0x6: {
5152 OPC_Decode, 209, 6, 178, 1, // 10370: decode to DQUAI using decoder 178
5153 // 10370: }
5154 7, 0, // 10375: case 0x7: {
5155 OPC_Decode, 212, 6, 178, 1, // 10377: decode to DQUAI_rec using decoder 178
5156 // 10377: }
5157 // 10377: } // switch Inst[2:0]
5158 // 10377: }
5159 3, 95, // 10382: case 0x3: {
5160 OPC_SwitchField, 0, 3, // 10384: switch Inst[2:0] {
5161 4, 33, // 10387: case 0x4: {
5162 OPC_SwitchField, 9, 1, // 10389: switch Inst[9] {
5163 0, 5, // 10392: case 0x0: {
5164 OPC_Decode, 236, 6, 175, 1, // 10394: decode to DSCRI using decoder 175
5165 // 10394: }
5166 1, 0, // 10399: case 0x1: {
5167 OPC_SwitchField, 10, 1, // 10401: switch Inst[10] {
5168 0, 9, // 10404: case 0x0: {
5169 OPC_CheckField, 16, 5, 0, // 10406: check Inst[20:16] == 0x0
5170 OPC_Decode, 136, 7, 173, 1, // 10410: decode to DXEX using decoder 173
5171 // 10410: }
5172 1, 0, // 10415: case 0x1: {
5173 OPC_Decode, 142, 6, 172, 1, // 10417: decode to DIEX using decoder 172
5174 // 10417: }
5175 // 10417: } // switch Inst[10]
5176 // 10417: }
5177 // 10417: } // switch Inst[9]
5178 // 10417: }
5179 5, 33, // 10422: case 0x5: {
5180 OPC_SwitchField, 9, 1, // 10424: switch Inst[9] {
5181 0, 5, // 10427: case 0x0: {
5182 OPC_Decode, 239, 6, 175, 1, // 10429: decode to DSCRI_rec using decoder 175
5183 // 10429: }
5184 1, 0, // 10434: case 0x1: {
5185 OPC_SwitchField, 10, 1, // 10436: switch Inst[10] {
5186 0, 9, // 10439: case 0x0: {
5187 OPC_CheckField, 16, 5, 0, // 10441: check Inst[20:16] == 0x0
5188 OPC_Decode, 139, 7, 173, 1, // 10445: decode to DXEX_rec using decoder 173
5189 // 10445: }
5190 1, 0, // 10450: case 0x1: {
5191 OPC_Decode, 145, 6, 172, 1, // 10452: decode to DIEX_rec using decoder 172
5192 // 10452: }
5193 // 10452: } // switch Inst[10]
5194 // 10452: }
5195 // 10452: } // switch Inst[9]
5196 // 10452: }
5197 6, 9, // 10457: case 0x6: {
5198 OPC_CheckField, 17, 4, 0, // 10459: check Inst[20:17] == 0x0
5199 OPC_Decode, 222, 6, 179, 1, // 10463: decode to DRINTX using decoder 179
5200 // 10463: }
5201 7, 0, // 10468: case 0x7: {
5202 OPC_CheckField, 17, 4, 0, // 10470: check Inst[20:17] == 0x0
5203 OPC_Decode, 225, 6, 179, 1, // 10474: decode to DRINTX_rec using decoder 179
5204 // 10474: }
5205 // 10474: } // switch Inst[2:0]
5206 // 10474: }
5207 4, 47, // 10479: case 0x4: {
5208 OPC_SwitchField, 9, 2, // 10481: switch Inst[10:9] {
5209 0, 13, // 10484: case 0x0: {
5210 OPC_CheckField, 21, 2, 0, // 10486: check Inst[22:21] == 0x0
5211 OPC_CheckField, 0, 3, 4, // 10490: check Inst[2:0] == 0x4
5212 OPC_Decode, 245, 5, 180, 1, // 10494: decode to DCMPO using decoder 180
5213 // 10494: }
5214 1, 5, // 10499: case 0x1: {
5215 OPC_Decode, 190, 20, 181, 1, // 10501: decode to XSADDADDUQM using decoder 181
5216 // 10501: }
5217 2, 13, // 10506: case 0x2: {
5218 OPC_CheckField, 21, 2, 0, // 10508: check Inst[22:21] == 0x0
5219 OPC_CheckField, 0, 3, 4, // 10512: check Inst[2:0] == 0x4
5220 OPC_Decode, 247, 5, 180, 1, // 10516: decode to DCMPU using decoder 180
5221 // 10516: }
5222 3, 0, // 10521: case 0x3: {
5223 OPC_Decode, 195, 20, 181, 1, // 10523: decode to XSADDSUBSUQM using decoder 181
5224 // 10523: }
5225 // 10523: } // switch Inst[10:9]
5226 // 10523: }
5227 5, 59, // 10528: case 0x5: {
5228 OPC_SwitchField, 9, 2, // 10530: switch Inst[10:9] {
5229 0, 13, // 10533: case 0x0: {
5230 OPC_CheckField, 21, 2, 0, // 10535: check Inst[22:21] == 0x0
5231 OPC_CheckField, 0, 3, 4, // 10539: check Inst[2:0] == 0x4
5232 OPC_Decode, 130, 7, 180, 1, // 10543: decode to DTSTEX using decoder 180
5233 // 10543: }
5234 1, 5, // 10548: case 0x1: {
5235 OPC_Decode, 189, 20, 181, 1, // 10550: decode to XSADDADDSUQM using decoder 181
5236 // 10550: }
5237 2, 25, // 10555: case 0x2: {
5238 OPC_SwitchField, 0, 3, // 10557: switch Inst[2:0] {
5239 4, 9, // 10560: case 0x4: {
5240 OPC_CheckField, 21, 2, 0, // 10562: check Inst[22:21] == 0x0
5241 OPC_Decode, 132, 7, 180, 1, // 10566: decode to DTSTSF using decoder 180
5242 // 10566: }
5243 6, 0, // 10571: case 0x6: {
5244 OPC_CheckField, 22, 1, 0, // 10573: check Inst[22] == 0x0
5245 OPC_Decode, 133, 7, 182, 1, // 10577: decode to DTSTSFI using decoder 182
5246 // 10577: }
5247 // 10577: } // switch Inst[2:0]
5248 // 10577: }
5249 3, 0, // 10582: case 0x3: {
5250 OPC_Decode, 130, 21, 181, 1, // 10584: decode to XSMERGE2T1UQM using decoder 181
5251 // 10584: }
5252 // 10584: } // switch Inst[10:9]
5253 // 10584: }
5254 6, 37, // 10589: case 0x6: {
5255 OPC_SwitchField, 9, 1, // 10591: switch Inst[9] {
5256 0, 13, // 10594: case 0x0: {
5257 OPC_CheckField, 21, 2, 0, // 10596: check Inst[22:21] == 0x0
5258 OPC_CheckField, 0, 3, 4, // 10600: check Inst[2:0] == 0x4
5259 OPC_Decode, 254, 6, 183, 1, // 10604: decode to DTSTDC using decoder 183
5260 // 10604: }
5261 1, 0, // 10609: case 0x1: {
5262 OPC_SwitchField, 10, 1, // 10611: switch Inst[10] {
5263 0, 5, // 10614: case 0x0: {
5264 OPC_Decode, 196, 20, 181, 1, // 10616: decode to XSADDSUBUQM using decoder 181
5265 // 10616: }
5266 1, 0, // 10621: case 0x1: {
5267 OPC_Decode, 131, 21, 181, 1, // 10623: decode to XSMERGE2T2UQM using decoder 181
5268 // 10623: }
5269 // 10623: } // switch Inst[10]
5270 // 10623: }
5271 // 10623: } // switch Inst[9]
5272 // 10623: }
5273 7, 0, // 10628: case 0x7: {
5274 OPC_SwitchField, 0, 3, // 10630: switch Inst[2:0] {
5275 4, 13, // 10633: case 0x4: {
5276 OPC_CheckField, 21, 2, 0, // 10635: check Inst[22:21] == 0x0
5277 OPC_CheckField, 9, 1, 0, // 10639: check Inst[9] == 0x0
5278 OPC_Decode, 128, 7, 183, 1, // 10643: decode to DTSTDG using decoder 183
5279 // 10643: }
5280 6, 9, // 10648: case 0x6: {
5281 OPC_CheckField, 17, 4, 0, // 10650: check Inst[20:17] == 0x0
5282 OPC_Decode, 218, 6, 179, 1, // 10654: decode to DRINTN using decoder 179
5283 // 10654: }
5284 7, 0, // 10659: case 0x7: {
5285 OPC_CheckField, 17, 4, 0, // 10661: check Inst[20:17] == 0x0
5286 OPC_Decode, 221, 6, 179, 1, // 10665: decode to DRINTN_rec using decoder 179
5287 // 10665: }
5288 // 10665: } // switch Inst[2:0]
5289 // 10665: }
5290 // 10665: } // switch Inst[8:6]
5291 // 10665: }
5292 1, 119, // 10670: case 0x1: {
5293 OPC_SwitchField, 6, 2, // 10672: switch Inst[7:6] {
5294 0, 5, // 10675: case 0x0: {
5295 OPC_Decode, 152, 23, 184, 1, // 10677: decode to XXMULMUL using decoder 184
5296 // 10677: }
5297 1, 5, // 10682: case 0x1: {
5298 OPC_Decode, 153, 23, 185, 1, // 10684: decode to XXMULMULHIADD using decoder 185
5299 // 10684: }
5300 2, 43, // 10689: case 0x2: {
5301 OPC_SwitchField, 10, 1, // 10691: switch Inst[10] {
5302 0, 5, // 10694: case 0x0: {
5303 OPC_Decode, 154, 23, 186, 1, // 10696: decode to XXMULMULLOADD using decoder 186
5304 // 10696: }
5305 1, 0, // 10701: case 0x1: {
5306 OPC_SwitchField, 8, 2, // 10703: switch Inst[9:8] {
5307 0, 5, // 10706: case 0x0: {
5308 OPC_Decode, 170, 21, 181, 1, // 10708: decode to XSREBASE2T1UQM using decoder 181
5309 // 10708: }
5310 1, 5, // 10713: case 0x1: {
5311 OPC_Decode, 171, 21, 181, 1, // 10715: decode to XSREBASE2T2UQM using decoder 181
5312 // 10715: }
5313 2, 5, // 10720: case 0x2: {
5314 OPC_Decode, 172, 21, 181, 1, // 10722: decode to XSREBASE2T3UQM using decoder 181
5315 // 10722: }
5316 3, 0, // 10727: case 0x3: {
5317 OPC_Decode, 174, 21, 181, 1, // 10729: decode to XSREBASE3T1UQM using decoder 181
5318 // 10729: }
5319 // 10729: } // switch Inst[9:8]
5320 // 10729: }
5321 // 10729: } // switch Inst[10]
5322 // 10729: }
5323 3, 0, // 10734: case 0x3: {
5324 OPC_SwitchField, 8, 2, // 10736: switch Inst[9:8] {
5325 0, 5, // 10739: case 0x0: {
5326 OPC_Decode, 170, 23, 187, 1, // 10741: decode to XXSSUMUDM using decoder 187
5327 // 10741: }
5328 1, 5, // 10746: case 0x1: {
5329 OPC_Decode, 171, 23, 187, 1, // 10748: decode to XXSSUMUDMC using decoder 187
5330 // 10748: }
5331 2, 17, // 10753: case 0x2: {
5332 OPC_SwitchField, 10, 1, // 10755: switch Inst[10] {
5333 0, 5, // 10758: case 0x0: {
5334 OPC_Decode, 132, 21, 181, 1, // 10760: decode to XSMERGE2T3UQM using decoder 181
5335 // 10760: }
5336 1, 0, // 10765: case 0x1: {
5337 OPC_Decode, 173, 21, 181, 1, // 10767: decode to XSREBASE2T4UQM using decoder 181
5338 // 10767: }
5339 // 10767: } // switch Inst[10]
5340 // 10767: }
5341 3, 0, // 10772: case 0x3: {
5342 OPC_SwitchField, 10, 1, // 10774: switch Inst[10] {
5343 0, 5, // 10777: case 0x0: {
5344 OPC_Decode, 133, 21, 181, 1, // 10779: decode to XSMERGE3T1UQM using decoder 181
5345 // 10779: }
5346 1, 0, // 10784: case 0x1: {
5347 OPC_Decode, 175, 21, 181, 1, // 10786: decode to XSREBASE3T2UQM using decoder 181
5348 // 10786: }
5349 // 10786: } // switch Inst[10]
5350 // 10786: }
5351 // 10786: } // switch Inst[9:8]
5352 // 10786: }
5353 // 10786: } // switch Inst[7:6]
5354 // 10786: }
5355 2, 146, 3, // 10791: case 0x2: {
5356 OPC_SwitchField, 6, 5, // 10794: switch Inst[10:6] {
5357 0, 13, // 10797: case 0x0: {
5358 OPC_CheckField, 21, 2, 0, // 10799: check Inst[22:21] == 0x0
5359 OPC_CheckField, 0, 1, 0, // 10803: check Inst[0] == 0x0
5360 OPC_Decode, 171, 22, 188, 1, // 10807: decode to XVI8GER4PP using decoder 188
5361 // 10807: }
5362 1, 17, // 10812: case 0x1: {
5363 OPC_CheckField, 21, 2, 0, // 10814: check Inst[22:21] == 0x0
5364 OPC_CheckField, 16, 1, 0, // 10818: check Inst[16] == 0x0
5365 OPC_CheckField, 0, 1, 0, // 10822: check Inst[0] == 0x0
5366 OPC_Decode, 198, 6, 189, 1, // 10826: decode to DMXVI8GERX4PP using decoder 189
5367 // 10826: }
5368 2, 13, // 10831: case 0x2: {
5369 OPC_CheckField, 21, 2, 0, // 10833: check Inst[22:21] == 0x0
5370 OPC_CheckField, 0, 1, 0, // 10837: check Inst[0] == 0x0
5371 OPC_Decode, 132, 22, 188, 1, // 10841: decode to XVF16GER2PP using decoder 188
5372 // 10841: }
5373 3, 13, // 10846: case 0x3: {
5374 OPC_CheckField, 21, 2, 0, // 10848: check Inst[22:21] == 0x0
5375 OPC_CheckField, 0, 1, 0, // 10852: check Inst[0] == 0x0
5376 OPC_Decode, 142, 22, 188, 1, // 10856: decode to XVF32GERPP using decoder 188
5377 // 10856: }
5378 4, 13, // 10861: case 0x4: {
5379 OPC_CheckField, 21, 2, 0, // 10863: check Inst[22:21] == 0x0
5380 OPC_CheckField, 0, 1, 0, // 10867: check Inst[0] == 0x0
5381 OPC_Decode, 167, 22, 188, 1, // 10871: decode to XVI4GER8PP using decoder 188
5382 // 10871: }
5383 5, 13, // 10876: case 0x5: {
5384 OPC_CheckField, 21, 2, 0, // 10878: check Inst[22:21] == 0x0
5385 OPC_CheckField, 0, 1, 0, // 10882: check Inst[0] == 0x0
5386 OPC_Decode, 161, 22, 188, 1, // 10886: decode to XVI16GER2SPP using decoder 188
5387 // 10886: }
5388 6, 13, // 10891: case 0x6: {
5389 OPC_CheckField, 21, 2, 0, // 10893: check Inst[22:21] == 0x0
5390 OPC_CheckField, 0, 1, 0, // 10897: check Inst[0] == 0x0
5391 OPC_Decode, 212, 21, 188, 1, // 10901: decode to XVBF16GER2PP using decoder 188
5392 // 10901: }
5393 7, 13, // 10906: case 0x7: {
5394 OPC_CheckField, 21, 2, 0, // 10908: check Inst[22:21] == 0x0
5395 OPC_CheckField, 0, 1, 0, // 10912: check Inst[0] == 0x0
5396 OPC_Decode, 152, 22, 190, 1, // 10916: decode to XVF64GERPP using decoder 190
5397 // 10916: }
5398 8, 17, // 10921: case 0x8: {
5399 OPC_CheckField, 21, 2, 0, // 10923: check Inst[22:21] == 0x0
5400 OPC_CheckField, 16, 1, 0, // 10927: check Inst[16] == 0x0
5401 OPC_CheckField, 0, 1, 0, // 10931: check Inst[0] == 0x0
5402 OPC_Decode, 196, 6, 189, 1, // 10935: decode to DMXVF16GERX2PP using decoder 189
5403 // 10935: }
5404 9, 17, // 10940: case 0x9: {
5405 OPC_CheckField, 21, 2, 0, // 10942: check Inst[22:21] == 0x0
5406 OPC_CheckField, 16, 1, 0, // 10946: check Inst[16] == 0x0
5407 OPC_CheckField, 0, 1, 0, // 10950: check Inst[0] == 0x0
5408 OPC_Decode, 191, 6, 189, 1, // 10954: decode to DMXVBF16GERX2PP using decoder 189
5409 // 10954: }
5410 10, 13, // 10959: case 0xa: {
5411 OPC_CheckField, 21, 2, 0, // 10961: check Inst[22:21] == 0x0
5412 OPC_CheckField, 0, 1, 0, // 10965: check Inst[0] == 0x0
5413 OPC_Decode, 130, 22, 188, 1, // 10969: decode to XVF16GER2NP using decoder 188
5414 // 10969: }
5415 11, 13, // 10974: case 0xb: {
5416 OPC_CheckField, 21, 2, 0, // 10976: check Inst[22:21] == 0x0
5417 OPC_CheckField, 0, 1, 0, // 10980: check Inst[0] == 0x0
5418 OPC_Decode, 140, 22, 188, 1, // 10984: decode to XVF32GERNP using decoder 188
5419 // 10984: }
5420 12, 17, // 10989: case 0xc: {
5421 OPC_CheckField, 21, 2, 0, // 10991: check Inst[22:21] == 0x0
5422 OPC_CheckField, 16, 1, 0, // 10995: check Inst[16] == 0x0
5423 OPC_CheckField, 0, 1, 0, // 10999: check Inst[0] == 0x0
5424 OPC_Decode, 199, 6, 189, 1, // 11003: decode to DMXVI8GERX4SPP using decoder 189
5425 // 11003: }
5426 14, 13, // 11008: case 0xe: {
5427 OPC_CheckField, 21, 2, 0, // 11010: check Inst[22:21] == 0x0
5428 OPC_CheckField, 0, 1, 0, // 11014: check Inst[0] == 0x0
5429 OPC_Decode, 210, 21, 188, 1, // 11018: decode to XVBF16GER2NP using decoder 188
5430 // 11018: }
5431 15, 13, // 11023: case 0xf: {
5432 OPC_CheckField, 21, 2, 0, // 11025: check Inst[22:21] == 0x0
5433 OPC_CheckField, 0, 1, 0, // 11029: check Inst[0] == 0x0
5434 OPC_Decode, 150, 22, 190, 1, // 11033: decode to XVF64GERNP using decoder 190
5435 // 11033: }
5436 18, 13, // 11038: case 0x12: {
5437 OPC_CheckField, 21, 2, 0, // 11040: check Inst[22:21] == 0x0
5438 OPC_CheckField, 0, 1, 0, // 11044: check Inst[0] == 0x0
5439 OPC_Decode, 131, 22, 188, 1, // 11048: decode to XVF16GER2PN using decoder 188
5440 // 11048: }
5441 19, 13, // 11053: case 0x13: {
5442 OPC_CheckField, 21, 2, 0, // 11055: check Inst[22:21] == 0x0
5443 OPC_CheckField, 0, 1, 0, // 11059: check Inst[0] == 0x0
5444 OPC_Decode, 141, 22, 188, 1, // 11063: decode to XVF32GERPN using decoder 188
5445 // 11063: }
5446 22, 13, // 11068: case 0x16: {
5447 OPC_CheckField, 21, 2, 0, // 11070: check Inst[22:21] == 0x0
5448 OPC_CheckField, 0, 1, 0, // 11074: check Inst[0] == 0x0
5449 OPC_Decode, 211, 21, 188, 1, // 11078: decode to XVBF16GER2PN using decoder 188
5450 // 11078: }
5451 23, 13, // 11083: case 0x17: {
5452 OPC_CheckField, 21, 2, 0, // 11085: check Inst[22:21] == 0x0
5453 OPC_CheckField, 0, 1, 0, // 11089: check Inst[0] == 0x0
5454 OPC_Decode, 151, 22, 190, 1, // 11093: decode to XVF64GERPN using decoder 190
5455 // 11093: }
5456 25, 17, // 11098: case 0x19: {
5457 OPC_CheckField, 21, 2, 0, // 11100: check Inst[22:21] == 0x0
5458 OPC_CheckField, 16, 1, 0, // 11104: check Inst[16] == 0x0
5459 OPC_CheckField, 0, 1, 0, // 11108: check Inst[0] == 0x0
5460 OPC_Decode, 193, 6, 189, 1, // 11112: decode to DMXVF16GERX2NN using decoder 189
5461 // 11112: }
5462 26, 13, // 11117: case 0x1a: {
5463 OPC_CheckField, 21, 2, 0, // 11119: check Inst[22:21] == 0x0
5464 OPC_CheckField, 0, 1, 0, // 11123: check Inst[0] == 0x0
5465 OPC_Decode, 129, 22, 188, 1, // 11127: decode to XVF16GER2NN using decoder 188
5466 // 11127: }
5467 27, 13, // 11132: case 0x1b: {
5468 OPC_CheckField, 21, 2, 0, // 11134: check Inst[22:21] == 0x0
5469 OPC_CheckField, 0, 1, 0, // 11138: check Inst[0] == 0x0
5470 OPC_Decode, 139, 22, 188, 1, // 11142: decode to XVF32GERNN using decoder 188
5471 // 11142: }
5472 29, 17, // 11147: case 0x1d: {
5473 OPC_CheckField, 21, 2, 0, // 11149: check Inst[22:21] == 0x0
5474 OPC_CheckField, 16, 1, 0, // 11153: check Inst[16] == 0x0
5475 OPC_CheckField, 0, 1, 0, // 11157: check Inst[0] == 0x0
5476 OPC_Decode, 188, 6, 189, 1, // 11161: decode to DMXVBF16GERX2NN using decoder 189
5477 // 11161: }
5478 30, 13, // 11166: case 0x1e: {
5479 OPC_CheckField, 21, 2, 0, // 11168: check Inst[22:21] == 0x0
5480 OPC_CheckField, 0, 1, 0, // 11172: check Inst[0] == 0x0
5481 OPC_Decode, 209, 21, 188, 1, // 11176: decode to XVBF16GER2NN using decoder 188
5482 // 11176: }
5483 31, 0, // 11181: case 0x1f: {
5484 OPC_CheckField, 21, 2, 0, // 11183: check Inst[22:21] == 0x0
5485 OPC_CheckField, 0, 1, 0, // 11187: check Inst[0] == 0x0
5486 OPC_Decode, 149, 22, 190, 1, // 11191: decode to XVF64GERNN using decoder 190
5487 // 11191: }
5488 // 11191: } // switch Inst[10:6]
5489 // 11191: }
5490 3, 219, 2, // 11196: case 0x3: {
5491 OPC_SwitchField, 6, 5, // 11199: switch Inst[10:6] {
5492 0, 13, // 11202: case 0x0: {
5493 OPC_CheckField, 21, 2, 0, // 11204: check Inst[22:21] == 0x0
5494 OPC_CheckField, 0, 1, 0, // 11208: check Inst[0] == 0x0
5495 OPC_Decode, 170, 22, 191, 1, // 11212: decode to XVI8GER4 using decoder 191
5496 // 11212: }
5497 1, 17, // 11217: case 0x1: {
5498 OPC_CheckField, 21, 2, 0, // 11219: check Inst[22:21] == 0x0
5499 OPC_CheckField, 16, 1, 0, // 11223: check Inst[16] == 0x0
5500 OPC_CheckField, 0, 1, 0, // 11227: check Inst[0] == 0x0
5501 OPC_Decode, 197, 6, 192, 1, // 11231: decode to DMXVI8GERX4 using decoder 192
5502 // 11231: }
5503 2, 13, // 11236: case 0x2: {
5504 OPC_CheckField, 21, 2, 0, // 11238: check Inst[22:21] == 0x0
5505 OPC_CheckField, 0, 1, 0, // 11242: check Inst[0] == 0x0
5506 OPC_Decode, 128, 22, 191, 1, // 11246: decode to XVF16GER2 using decoder 191
5507 // 11246: }
5508 3, 13, // 11251: case 0x3: {
5509 OPC_CheckField, 21, 2, 0, // 11253: check Inst[22:21] == 0x0
5510 OPC_CheckField, 0, 1, 0, // 11257: check Inst[0] == 0x0
5511 OPC_Decode, 138, 22, 191, 1, // 11261: decode to XVF32GER using decoder 191
5512 // 11261: }
5513 4, 13, // 11266: case 0x4: {
5514 OPC_CheckField, 21, 2, 0, // 11268: check Inst[22:21] == 0x0
5515 OPC_CheckField, 0, 1, 0, // 11272: check Inst[0] == 0x0
5516 OPC_Decode, 166, 22, 191, 1, // 11276: decode to XVI4GER8 using decoder 191
5517 // 11276: }
5518 5, 13, // 11281: case 0x5: {
5519 OPC_CheckField, 21, 2, 0, // 11283: check Inst[22:21] == 0x0
5520 OPC_CheckField, 0, 1, 0, // 11287: check Inst[0] == 0x0
5521 OPC_Decode, 160, 22, 191, 1, // 11291: decode to XVI16GER2S using decoder 191
5522 // 11291: }
5523 6, 13, // 11296: case 0x6: {
5524 OPC_CheckField, 21, 2, 0, // 11298: check Inst[22:21] == 0x0
5525 OPC_CheckField, 0, 1, 0, // 11302: check Inst[0] == 0x0
5526 OPC_Decode, 208, 21, 191, 1, // 11306: decode to XVBF16GER2 using decoder 191
5527 // 11306: }
5528 7, 13, // 11311: case 0x7: {
5529 OPC_CheckField, 21, 2, 0, // 11313: check Inst[22:21] == 0x0
5530 OPC_CheckField, 0, 1, 0, // 11317: check Inst[0] == 0x0
5531 OPC_Decode, 148, 22, 193, 1, // 11321: decode to XVF64GER using decoder 193
5532 // 11321: }
5533 8, 17, // 11326: case 0x8: {
5534 OPC_CheckField, 21, 2, 0, // 11328: check Inst[22:21] == 0x0
5535 OPC_CheckField, 16, 1, 0, // 11332: check Inst[16] == 0x0
5536 OPC_CheckField, 0, 1, 0, // 11336: check Inst[0] == 0x0
5537 OPC_Decode, 192, 6, 192, 1, // 11340: decode to DMXVF16GERX2 using decoder 192
5538 // 11340: }
5539 9, 13, // 11345: case 0x9: {
5540 OPC_CheckField, 21, 2, 0, // 11347: check Inst[22:21] == 0x0
5541 OPC_CheckField, 0, 1, 0, // 11351: check Inst[0] == 0x0
5542 OPC_Decode, 158, 22, 191, 1, // 11355: decode to XVI16GER2 using decoder 191
5543 // 11355: }
5544 10, 17, // 11360: case 0xa: {
5545 OPC_CheckField, 21, 2, 0, // 11362: check Inst[22:21] == 0x0
5546 OPC_CheckField, 16, 1, 0, // 11366: check Inst[16] == 0x0
5547 OPC_CheckField, 0, 1, 0, // 11370: check Inst[0] == 0x0
5548 OPC_Decode, 194, 6, 189, 1, // 11374: decode to DMXVF16GERX2NP using decoder 189
5549 // 11374: }
5550 11, 17, // 11379: case 0xb: {
5551 OPC_CheckField, 21, 2, 0, // 11381: check Inst[22:21] == 0x0
5552 OPC_CheckField, 16, 1, 0, // 11385: check Inst[16] == 0x0
5553 OPC_CheckField, 0, 1, 0, // 11389: check Inst[0] == 0x0
5554 OPC_Decode, 187, 6, 192, 1, // 11393: decode to DMXVBF16GERX2 using decoder 192
5555 // 11393: }
5556 12, 13, // 11398: case 0xc: {
5557 OPC_CheckField, 21, 2, 0, // 11400: check Inst[22:21] == 0x0
5558 OPC_CheckField, 0, 1, 0, // 11404: check Inst[0] == 0x0
5559 OPC_Decode, 172, 22, 188, 1, // 11408: decode to XVI8GER4SPP using decoder 188
5560 // 11408: }
5561 13, 13, // 11413: case 0xd: {
5562 OPC_CheckField, 21, 2, 0, // 11415: check Inst[22:21] == 0x0
5563 OPC_CheckField, 0, 1, 0, // 11419: check Inst[0] == 0x0
5564 OPC_Decode, 159, 22, 188, 1, // 11423: decode to XVI16GER2PP using decoder 188
5565 // 11423: }
5566 14, 17, // 11428: case 0xe: {
5567 OPC_CheckField, 21, 2, 0, // 11430: check Inst[22:21] == 0x0
5568 OPC_CheckField, 16, 1, 0, // 11434: check Inst[16] == 0x0
5569 OPC_CheckField, 0, 1, 0, // 11438: check Inst[0] == 0x0
5570 OPC_Decode, 189, 6, 189, 1, // 11442: decode to DMXVBF16GERX2NP using decoder 189
5571 // 11442: }
5572 18, 17, // 11447: case 0x12: {
5573 OPC_CheckField, 21, 2, 0, // 11449: check Inst[22:21] == 0x0
5574 OPC_CheckField, 16, 1, 0, // 11453: check Inst[16] == 0x0
5575 OPC_CheckField, 0, 1, 0, // 11457: check Inst[0] == 0x0
5576 OPC_Decode, 195, 6, 189, 1, // 11461: decode to DMXVF16GERX2PN using decoder 189
5577 // 11461: }
5578 22, 17, // 11466: case 0x16: {
5579 OPC_CheckField, 21, 2, 0, // 11468: check Inst[22:21] == 0x0
5580 OPC_CheckField, 16, 1, 0, // 11472: check Inst[16] == 0x0
5581 OPC_CheckField, 0, 1, 0, // 11476: check Inst[0] == 0x0
5582 OPC_Decode, 190, 6, 189, 1, // 11480: decode to DMXVBF16GERX2PN using decoder 189
5583 // 11480: }
5584 24, 5, // 11485: case 0x18: {
5585 OPC_Decode, 176, 21, 181, 1, // 11487: decode to XSREBASE3T3UQM using decoder 181
5586 // 11487: }
5587 26, 25, // 11492: case 0x1a: {
5588 OPC_SwitchField, 0, 3, // 11494: switch Inst[2:0] {
5589 4, 9, // 11497: case 0x4: {
5590 OPC_CheckField, 16, 5, 0, // 11499: check Inst[20:16] == 0x0
5591 OPC_Decode, 176, 9, 194, 1, // 11503: decode to FCFIDS using decoder 194
5592 // 11503: }
5593 5, 0, // 11508: case 0x5: {
5594 OPC_CheckField, 16, 5, 0, // 11510: check Inst[20:16] == 0x0
5595 OPC_Decode, 177, 9, 194, 1, // 11514: decode to FCFIDS_rec using decoder 194
5596 // 11514: }
5597 // 11514: } // switch Inst[2:0]
5598 // 11514: }
5599 30, 0, // 11519: case 0x1e: {
5600 OPC_SwitchField, 0, 3, // 11521: switch Inst[2:0] {
5601 4, 9, // 11524: case 0x4: {
5602 OPC_CheckField, 16, 5, 0, // 11526: check Inst[20:16] == 0x0
5603 OPC_Decode, 179, 9, 194, 1, // 11530: decode to FCFIDUS using decoder 194
5604 // 11530: }
5605 5, 0, // 11535: case 0x5: {
5606 OPC_CheckField, 16, 5, 0, // 11537: check Inst[20:16] == 0x0
5607 OPC_Decode, 180, 9, 194, 1, // 11541: decode to FCFIDUS_rec using decoder 194
5608 // 11541: }
5609 // 11541: } // switch Inst[2:0]
5610 // 11541: }
5611 // 11541: } // switch Inst[10:6]
5612 // 11541: }
5613 4, 25, // 11546: case 0x4: {
5614 OPC_SwitchField, 0, 3, // 11548: switch Inst[2:0] {
5615 4, 9, // 11551: case 0x4: {
5616 OPC_CheckField, 6, 5, 0, // 11553: check Inst[10:6] == 0x0
5617 OPC_Decode, 208, 9, 195, 1, // 11557: decode to FDIVS using decoder 195
5618 // 11557: }
5619 5, 0, // 11562: case 0x5: {
5620 OPC_CheckField, 6, 5, 0, // 11564: check Inst[10:6] == 0x0
5621 OPC_Decode, 209, 9, 195, 1, // 11568: decode to FDIVS_rec using decoder 195
5622 // 11568: }
5623 // 11568: } // switch Inst[2:0]
5624 // 11568: }
5625 5, 77, // 11573: case 0x5: {
5626 OPC_SwitchField, 0, 3, // 11575: switch Inst[2:0] {
5627 0, 9, // 11578: case 0x0: {
5628 OPC_CheckField, 6, 5, 0, // 11580: check Inst[10:6] == 0x0
5629 OPC_Decode, 149, 10, 195, 1, // 11584: decode to FSUBS using decoder 195
5630 // 11584: }
5631 1, 9, // 11589: case 0x1: {
5632 OPC_CheckField, 6, 5, 0, // 11591: check Inst[10:6] == 0x0
5633 OPC_Decode, 150, 10, 195, 1, // 11595: decode to FSUBS_rec using decoder 195
5634 // 11595: }
5635 2, 9, // 11600: case 0x2: {
5636 OPC_CheckField, 6, 5, 0, // 11602: check Inst[10:6] == 0x0
5637 OPC_Decode, 171, 9, 195, 1, // 11606: decode to FADDS using decoder 195
5638 // 11606: }
5639 3, 9, // 11611: case 0x3: {
5640 OPC_CheckField, 6, 5, 0, // 11613: check Inst[10:6] == 0x0
5641 OPC_Decode, 172, 9, 195, 1, // 11617: decode to FADDS_rec using decoder 195
5642 // 11617: }
5643 4, 13, // 11622: case 0x4: {
5644 OPC_CheckField, 16, 5, 0, // 11624: check Inst[20:16] == 0x0
5645 OPC_CheckField, 6, 5, 0, // 11628: check Inst[10:6] == 0x0
5646 OPC_Decode, 145, 10, 196, 1, // 11632: decode to FSQRTS using decoder 196
5647 // 11632: }
5648 5, 0, // 11637: case 0x5: {
5649 OPC_CheckField, 16, 5, 0, // 11639: check Inst[20:16] == 0x0
5650 OPC_CheckField, 6, 5, 0, // 11643: check Inst[10:6] == 0x0
5651 OPC_Decode, 146, 10, 196, 1, // 11647: decode to FSQRTS_rec using decoder 196
5652 // 11647: }
5653 // 11647: } // switch Inst[2:0]
5654 // 11647: }
5655 6, 85, // 11652: case 0x6: {
5656 OPC_SwitchField, 0, 3, // 11654: switch Inst[2:0] {
5657 0, 13, // 11657: case 0x0: {
5658 OPC_CheckField, 16, 5, 0, // 11659: check Inst[20:16] == 0x0
5659 OPC_CheckField, 6, 5, 0, // 11663: check Inst[10:6] == 0x0
5660 OPC_Decode, 243, 9, 196, 1, // 11667: decode to FRES using decoder 196
5661 // 11667: }
5662 1, 13, // 11672: case 0x1: {
5663 OPC_CheckField, 16, 5, 0, // 11674: check Inst[20:16] == 0x0
5664 OPC_CheckField, 6, 5, 0, // 11678: check Inst[10:6] == 0x0
5665 OPC_Decode, 244, 9, 196, 1, // 11682: decode to FRES_rec using decoder 196
5666 // 11682: }
5667 2, 9, // 11687: case 0x2: {
5668 OPC_CheckField, 11, 5, 0, // 11689: check Inst[15:11] == 0x0
5669 OPC_Decode, 223, 9, 197, 1, // 11693: decode to FMULS using decoder 197
5670 // 11693: }
5671 3, 9, // 11698: case 0x3: {
5672 OPC_CheckField, 11, 5, 0, // 11700: check Inst[15:11] == 0x0
5673 OPC_Decode, 224, 9, 197, 1, // 11704: decode to FMULS_rec using decoder 197
5674 // 11704: }
5675 4, 13, // 11709: case 0x4: {
5676 OPC_CheckField, 16, 5, 0, // 11711: check Inst[20:16] == 0x0
5677 OPC_CheckField, 6, 5, 0, // 11715: check Inst[10:6] == 0x0
5678 OPC_Decode, 137, 10, 196, 1, // 11719: decode to FRSQRTES using decoder 196
5679 // 11719: }
5680 5, 0, // 11724: case 0x5: {
5681 OPC_CheckField, 16, 5, 0, // 11726: check Inst[20:16] == 0x0
5682 OPC_CheckField, 6, 5, 0, // 11730: check Inst[10:6] == 0x0
5683 OPC_Decode, 138, 10, 196, 1, // 11734: decode to FRSQRTES_rec using decoder 196
5684 // 11734: }
5685 // 11734: } // switch Inst[2:0]
5686 // 11734: }
5687 7, 0, // 11739: case 0x7: {
5688 OPC_SwitchField, 0, 3, // 11741: switch Inst[2:0] {
5689 0, 5, // 11744: case 0x0: {
5690 OPC_Decode, 219, 9, 198, 1, // 11746: decode to FMSUBS using decoder 198
5691 // 11746: }
5692 1, 5, // 11751: case 0x1: {
5693 OPC_Decode, 220, 9, 198, 1, // 11753: decode to FMSUBS_rec using decoder 198
5694 // 11753: }
5695 2, 5, // 11758: case 0x2: {
5696 OPC_Decode, 213, 9, 198, 1, // 11760: decode to FMADDS using decoder 198
5697 // 11760: }
5698 3, 5, // 11765: case 0x3: {
5699 OPC_Decode, 214, 9, 198, 1, // 11767: decode to FMADDS_rec using decoder 198
5700 // 11767: }
5701 4, 5, // 11772: case 0x4: {
5702 OPC_Decode, 239, 9, 198, 1, // 11774: decode to FNMSUBS using decoder 198
5703 // 11774: }
5704 5, 5, // 11779: case 0x5: {
5705 OPC_Decode, 240, 9, 198, 1, // 11781: decode to FNMSUBS_rec using decoder 198
5706 // 11781: }
5707 6, 5, // 11786: case 0x6: {
5708 OPC_Decode, 235, 9, 198, 1, // 11788: decode to FNMADDS using decoder 198
5709 // 11788: }
5710 7, 0, // 11793: case 0x7: {
5711 OPC_Decode, 236, 9, 198, 1, // 11795: decode to FNMADDS_rec using decoder 198
5712 // 11795: }
5713 // 11795: } // switch Inst[2:0]
5714 // 11795: }
5715 // 11795: } // switch Inst[5:3]
5716 // 11795: }
5717 60, 146, 21, // 11800: case 0x3c: {
5718 OPC_SwitchField, 4, 2, // 11803: switch Inst[5:4] {
5719 0, 227, 4, // 11806: case 0x0: {
5720 OPC_SwitchField, 6, 5, // 11809: switch Inst[10:6] {
5721 0, 17, // 11812: case 0x0: {
5722 OPC_SwitchField, 3, 1, // 11814: switch Inst[3] {
5723 0, 5, // 11817: case 0x0: {
5724 OPC_Decode, 194, 20, 199, 1, // 11819: decode to XSADDSP using decoder 199
5725 // 11819: }
5726 1, 0, // 11824: case 0x1: {
5727 OPC_Decode, 249, 20, 200, 1, // 11826: decode to XSMADDASP using decoder 200
5728 // 11826: }
5729 // 11826: } // switch Inst[3]
5730 // 11826: }
5731 1, 17, // 11831: case 0x1: {
5732 OPC_SwitchField, 3, 1, // 11833: switch Inst[3] {
5733 0, 5, // 11836: case 0x0: {
5734 OPC_Decode, 192, 21, 199, 1, // 11838: decode to XSSUBSP using decoder 199
5735 // 11838: }
5736 1, 0, // 11843: case 0x1: {
5737 OPC_Decode, 251, 20, 200, 1, // 11845: decode to XSMADDMSP using decoder 200
5738 // 11845: }
5739 // 11845: } // switch Inst[3]
5740 // 11845: }
5741 2, 17, // 11850: case 0x2: {
5742 OPC_SwitchField, 3, 1, // 11852: switch Inst[3] {
5743 0, 5, // 11855: case 0x0: {
5744 OPC_Decode, 147, 21, 199, 1, // 11857: decode to XSMULSP using decoder 199
5745 // 11857: }
5746 1, 0, // 11862: case 0x1: {
5747 OPC_Decode, 139, 21, 200, 1, // 11864: decode to XSMSUBASP using decoder 200
5748 // 11864: }
5749 // 11864: } // switch Inst[3]
5750 // 11864: }
5751 3, 17, // 11869: case 0x3: {
5752 OPC_SwitchField, 3, 1, // 11871: switch Inst[3] {
5753 0, 5, // 11874: case 0x0: {
5754 OPC_Decode, 245, 20, 199, 1, // 11876: decode to XSDIVSP using decoder 199
5755 // 11876: }
5756 1, 0, // 11881: case 0x1: {
5757 OPC_Decode, 141, 21, 200, 1, // 11883: decode to XSMSUBMSP using decoder 200
5758 // 11883: }
5759 // 11883: } // switch Inst[3]
5760 // 11883: }
5761 4, 17, // 11888: case 0x4: {
5762 OPC_SwitchField, 3, 1, // 11890: switch Inst[3] {
5763 0, 5, // 11893: case 0x0: {
5764 OPC_Decode, 191, 20, 201, 1, // 11895: decode to XSADDDP using decoder 201
5765 // 11895: }
5766 1, 0, // 11900: case 0x1: {
5767 OPC_Decode, 248, 20, 202, 1, // 11902: decode to XSMADDADP using decoder 202
5768 // 11902: }
5769 // 11902: } // switch Inst[3]
5770 // 11902: }
5771 5, 17, // 11907: case 0x5: {
5772 OPC_SwitchField, 3, 1, // 11909: switch Inst[3] {
5773 0, 5, // 11912: case 0x0: {
5774 OPC_Decode, 189, 21, 201, 1, // 11914: decode to XSSUBDP using decoder 201
5775 // 11914: }
5776 1, 0, // 11919: case 0x1: {
5777 OPC_Decode, 250, 20, 202, 1, // 11921: decode to XSMADDMDP using decoder 202
5778 // 11921: }
5779 // 11921: } // switch Inst[3]
5780 // 11921: }
5781 6, 17, // 11926: case 0x6: {
5782 OPC_SwitchField, 3, 1, // 11928: switch Inst[3] {
5783 0, 5, // 11931: case 0x0: {
5784 OPC_Decode, 144, 21, 201, 1, // 11933: decode to XSMULDP using decoder 201
5785 // 11933: }
5786 1, 0, // 11938: case 0x1: {
5787 OPC_Decode, 138, 21, 202, 1, // 11940: decode to XSMSUBADP using decoder 202
5788 // 11940: }
5789 // 11940: } // switch Inst[3]
5790 // 11940: }
5791 7, 17, // 11945: case 0x7: {
5792 OPC_SwitchField, 3, 1, // 11947: switch Inst[3] {
5793 0, 5, // 11950: case 0x0: {
5794 OPC_Decode, 242, 20, 201, 1, // 11952: decode to XSDIVDP using decoder 201
5795 // 11952: }
5796 1, 0, // 11957: case 0x1: {
5797 OPC_Decode, 140, 21, 202, 1, // 11959: decode to XSMSUBMDP using decoder 202
5798 // 11959: }
5799 // 11959: } // switch Inst[3]
5800 // 11959: }
5801 8, 17, // 11964: case 0x8: {
5802 OPC_SwitchField, 3, 1, // 11966: switch Inst[3] {
5803 0, 5, // 11969: case 0x0: {
5804 OPC_Decode, 205, 21, 181, 1, // 11971: decode to XVADDSP using decoder 181
5805 // 11971: }
5806 1, 0, // 11976: case 0x1: {
5807 OPC_Decode, 179, 22, 203, 1, // 11978: decode to XVMADDASP using decoder 203
5808 // 11978: }
5809 // 11978: } // switch Inst[3]
5810 // 11978: }
5811 9, 17, // 11983: case 0x9: {
5812 OPC_SwitchField, 3, 1, // 11985: switch Inst[3] {
5813 0, 5, // 11988: case 0x0: {
5814 OPC_Decode, 228, 22, 181, 1, // 11990: decode to XVSUBSP using decoder 181
5815 // 11990: }
5816 1, 0, // 11995: case 0x1: {
5817 OPC_Decode, 181, 22, 203, 1, // 11997: decode to XVMADDMSP using decoder 203
5818 // 11997: }
5819 // 11997: } // switch Inst[3]
5820 // 11997: }
5821 10, 17, // 12002: case 0xa: {
5822 OPC_SwitchField, 3, 1, // 12004: switch Inst[3] {
5823 0, 5, // 12007: case 0x0: {
5824 OPC_Decode, 195, 22, 181, 1, // 12009: decode to XVMULSP using decoder 181
5825 // 12009: }
5826 1, 0, // 12014: case 0x1: {
5827 OPC_Decode, 187, 22, 203, 1, // 12016: decode to XVMSUBASP using decoder 203
5828 // 12016: }
5829 // 12016: } // switch Inst[3]
5830 // 12016: }
5831 11, 17, // 12021: case 0xb: {
5832 OPC_SwitchField, 3, 1, // 12023: switch Inst[3] {
5833 0, 5, // 12026: case 0x0: {
5834 OPC_Decode, 255, 21, 181, 1, // 12028: decode to XVDIVSP using decoder 181
5835 // 12028: }
5836 1, 0, // 12033: case 0x1: {
5837 OPC_Decode, 189, 22, 203, 1, // 12035: decode to XVMSUBMSP using decoder 203
5838 // 12035: }
5839 // 12035: } // switch Inst[3]
5840 // 12035: }
5841 12, 17, // 12040: case 0xc: {
5842 OPC_SwitchField, 3, 1, // 12042: switch Inst[3] {
5843 0, 5, // 12045: case 0x0: {
5844 OPC_Decode, 204, 21, 181, 1, // 12047: decode to XVADDDP using decoder 181
5845 // 12047: }
5846 1, 0, // 12052: case 0x1: {
5847 OPC_Decode, 178, 22, 203, 1, // 12054: decode to XVMADDADP using decoder 203
5848 // 12054: }
5849 // 12054: } // switch Inst[3]
5850 // 12054: }
5851 13, 17, // 12059: case 0xd: {
5852 OPC_SwitchField, 3, 1, // 12061: switch Inst[3] {
5853 0, 5, // 12064: case 0x0: {
5854 OPC_Decode, 227, 22, 181, 1, // 12066: decode to XVSUBDP using decoder 181
5855 // 12066: }
5856 1, 0, // 12071: case 0x1: {
5857 OPC_Decode, 180, 22, 203, 1, // 12073: decode to XVMADDMDP using decoder 203
5858 // 12073: }
5859 // 12073: } // switch Inst[3]
5860 // 12073: }
5861 14, 17, // 12078: case 0xe: {
5862 OPC_SwitchField, 3, 1, // 12080: switch Inst[3] {
5863 0, 5, // 12083: case 0x0: {
5864 OPC_Decode, 190, 22, 181, 1, // 12085: decode to XVMULDP using decoder 181
5865 // 12085: }
5866 1, 0, // 12090: case 0x1: {
5867 OPC_Decode, 186, 22, 203, 1, // 12092: decode to XVMSUBADP using decoder 203
5868 // 12092: }
5869 // 12092: } // switch Inst[3]
5870 // 12092: }
5871 15, 17, // 12097: case 0xf: {
5872 OPC_SwitchField, 3, 1, // 12099: switch Inst[3] {
5873 0, 5, // 12102: case 0x0: {
5874 OPC_Decode, 254, 21, 181, 1, // 12104: decode to XVDIVDP using decoder 181
5875 // 12104: }
5876 1, 0, // 12109: case 0x1: {
5877 OPC_Decode, 188, 22, 203, 1, // 12111: decode to XVMSUBMDP using decoder 203
5878 // 12111: }
5879 // 12111: } // switch Inst[3]
5880 // 12111: }
5881 16, 17, // 12116: case 0x10: {
5882 OPC_SwitchField, 3, 1, // 12118: switch Inst[3] {
5883 0, 5, // 12121: case 0x0: {
5884 OPC_Decode, 254, 20, 201, 1, // 12123: decode to XSMAXCDP using decoder 201
5885 // 12123: }
5886 1, 0, // 12128: case 0x1: {
5887 OPC_Decode, 154, 21, 200, 1, // 12130: decode to XSNMADDASP using decoder 200
5888 // 12130: }
5889 // 12130: } // switch Inst[3]
5890 // 12130: }
5891 17, 17, // 12135: case 0x11: {
5892 OPC_SwitchField, 3, 1, // 12137: switch Inst[3] {
5893 0, 5, // 12140: case 0x0: {
5894 OPC_Decode, 134, 21, 201, 1, // 12142: decode to XSMINCDP using decoder 201
5895 // 12142: }
5896 1, 0, // 12147: case 0x1: {
5897 OPC_Decode, 156, 21, 200, 1, // 12149: decode to XSNMADDMSP using decoder 200
5898 // 12149: }
5899 // 12149: } // switch Inst[3]
5900 // 12149: }
5901 18, 17, // 12154: case 0x12: {
5902 OPC_SwitchField, 3, 1, // 12156: switch Inst[3] {
5903 0, 5, // 12159: case 0x0: {
5904 OPC_Decode, 129, 21, 204, 1, // 12161: decode to XSMAXJDP using decoder 204
5905 // 12161: }
5906 1, 0, // 12166: case 0x1: {
5907 OPC_Decode, 160, 21, 200, 1, // 12168: decode to XSNMSUBASP using decoder 200
5908 // 12168: }
5909 // 12168: } // switch Inst[3]
5910 // 12168: }
5911 19, 17, // 12173: case 0x13: {
5912 OPC_SwitchField, 3, 1, // 12175: switch Inst[3] {
5913 0, 5, // 12178: case 0x0: {
5914 OPC_Decode, 137, 21, 204, 1, // 12180: decode to XSMINJDP using decoder 204
5915 // 12180: }
5916 1, 0, // 12185: case 0x1: {
5917 OPC_Decode, 162, 21, 200, 1, // 12187: decode to XSNMSUBMSP using decoder 200
5918 // 12187: }
5919 // 12187: } // switch Inst[3]
5920 // 12187: }
5921 20, 17, // 12192: case 0x14: {
5922 OPC_SwitchField, 3, 1, // 12194: switch Inst[3] {
5923 0, 5, // 12197: case 0x0: {
5924 OPC_Decode, 128, 21, 201, 1, // 12199: decode to XSMAXDP using decoder 201
5925 // 12199: }
5926 1, 0, // 12204: case 0x1: {
5927 OPC_Decode, 153, 21, 202, 1, // 12206: decode to XSNMADDADP using decoder 202
5928 // 12206: }
5929 // 12206: } // switch Inst[3]
5930 // 12206: }
5931 21, 17, // 12211: case 0x15: {
5932 OPC_SwitchField, 3, 1, // 12213: switch Inst[3] {
5933 0, 5, // 12216: case 0x0: {
5934 OPC_Decode, 136, 21, 201, 1, // 12218: decode to XSMINDP using decoder 201
5935 // 12218: }
5936 1, 0, // 12223: case 0x1: {
5937 OPC_Decode, 155, 21, 202, 1, // 12225: decode to XSNMADDMDP using decoder 202
5938 // 12225: }
5939 // 12225: } // switch Inst[3]
5940 // 12225: }
5941 22, 17, // 12230: case 0x16: {
5942 OPC_SwitchField, 3, 1, // 12232: switch Inst[3] {
5943 0, 5, // 12235: case 0x0: {
5944 OPC_Decode, 209, 20, 201, 1, // 12237: decode to XSCPSGNDP using decoder 201
5945 // 12237: }
5946 1, 0, // 12242: case 0x1: {
5947 OPC_Decode, 159, 21, 202, 1, // 12244: decode to XSNMSUBADP using decoder 202
5948 // 12244: }
5949 // 12244: } // switch Inst[3]
5950 // 12244: }
5951 23, 17, // 12249: case 0x17: {
5952 OPC_SwitchField, 3, 1, // 12251: switch Inst[3] {
5953 0, 5, // 12254: case 0x0: {
5954 OPC_Decode, 217, 22, 181, 1, // 12256: decode to XVRLW using decoder 181
5955 // 12256: }
5956 1, 0, // 12261: case 0x1: {
5957 OPC_Decode, 161, 21, 202, 1, // 12263: decode to XSNMSUBMDP using decoder 202
5958 // 12263: }
5959 // 12263: } // switch Inst[3]
5960 // 12263: }
5961 24, 17, // 12268: case 0x18: {
5962 OPC_SwitchField, 3, 1, // 12270: switch Inst[3] {
5963 0, 5, // 12273: case 0x0: {
5964 OPC_Decode, 183, 22, 181, 1, // 12275: decode to XVMAXSP using decoder 181
5965 // 12275: }
5966 1, 0, // 12280: case 0x1: {
5967 OPC_Decode, 203, 22, 203, 1, // 12282: decode to XVNMADDASP using decoder 203
5968 // 12282: }
5969 // 12282: } // switch Inst[3]
5970 // 12282: }
5971 25, 17, // 12287: case 0x19: {
5972 OPC_SwitchField, 3, 1, // 12289: switch Inst[3] {
5973 0, 5, // 12292: case 0x0: {
5974 OPC_Decode, 185, 22, 181, 1, // 12294: decode to XVMINSP using decoder 181
5975 // 12294: }
5976 1, 0, // 12299: case 0x1: {
5977 OPC_Decode, 205, 22, 203, 1, // 12301: decode to XVNMADDMSP using decoder 203
5978 // 12301: }
5979 // 12301: } // switch Inst[3]
5980 // 12301: }
5981 26, 17, // 12306: case 0x1a: {
5982 OPC_SwitchField, 3, 1, // 12308: switch Inst[3] {
5983 0, 5, // 12311: case 0x0: {
5984 OPC_Decode, 231, 21, 181, 1, // 12313: decode to XVCPSGNSP using decoder 181
5985 // 12313: }
5986 1, 0, // 12318: case 0x1: {
5987 OPC_Decode, 207, 22, 203, 1, // 12320: decode to XVNMSUBASP using decoder 203
5988 // 12320: }
5989 // 12320: } // switch Inst[3]
5990 // 12320: }
5991 27, 17, // 12325: case 0x1b: {
5992 OPC_SwitchField, 3, 1, // 12327: switch Inst[3] {
5993 0, 5, // 12330: case 0x0: {
5994 OPC_Decode, 177, 22, 181, 1, // 12332: decode to XVIEXPSP using decoder 181
5995 // 12332: }
5996 1, 0, // 12337: case 0x1: {
5997 OPC_Decode, 209, 22, 203, 1, // 12339: decode to XVNMSUBMSP using decoder 203
5998 // 12339: }
5999 // 12339: } // switch Inst[3]
6000 // 12339: }
6001 28, 17, // 12344: case 0x1c: {
6002 OPC_SwitchField, 3, 1, // 12346: switch Inst[3] {
6003 0, 5, // 12349: case 0x0: {
6004 OPC_Decode, 182, 22, 181, 1, // 12351: decode to XVMAXDP using decoder 181
6005 // 12351: }
6006 1, 0, // 12356: case 0x1: {
6007 OPC_Decode, 202, 22, 203, 1, // 12358: decode to XVNMADDADP using decoder 203
6008 // 12358: }
6009 // 12358: } // switch Inst[3]
6010 // 12358: }
6011 29, 17, // 12363: case 0x1d: {
6012 OPC_SwitchField, 3, 1, // 12365: switch Inst[3] {
6013 0, 5, // 12368: case 0x0: {
6014 OPC_Decode, 184, 22, 181, 1, // 12370: decode to XVMINDP using decoder 181
6015 // 12370: }
6016 1, 0, // 12375: case 0x1: {
6017 OPC_Decode, 204, 22, 203, 1, // 12377: decode to XVNMADDMDP using decoder 203
6018 // 12377: }
6019 // 12377: } // switch Inst[3]
6020 // 12377: }
6021 30, 17, // 12382: case 0x1e: {
6022 OPC_SwitchField, 3, 1, // 12384: switch Inst[3] {
6023 0, 5, // 12387: case 0x0: {
6024 OPC_Decode, 230, 21, 181, 1, // 12389: decode to XVCPSGNDP using decoder 181
6025 // 12389: }
6026 1, 0, // 12394: case 0x1: {
6027 OPC_Decode, 206, 22, 203, 1, // 12396: decode to XVNMSUBADP using decoder 203
6028 // 12396: }
6029 // 12396: } // switch Inst[3]
6030 // 12396: }
6031 31, 0, // 12401: case 0x1f: {
6032 OPC_SwitchField, 3, 1, // 12403: switch Inst[3] {
6033 0, 5, // 12406: case 0x0: {
6034 OPC_Decode, 176, 22, 181, 1, // 12408: decode to XVIEXPDP using decoder 181
6035 // 12408: }
6036 1, 0, // 12413: case 0x1: {
6037 OPC_Decode, 208, 22, 203, 1, // 12415: decode to XVNMSUBMDP using decoder 203
6038 // 12415: }
6039 // 12415: } // switch Inst[3]
6040 // 12415: }
6041 // 12415: } // switch Inst[10:6]
6042 // 12415: }
6043 1, 178, 5, // 12420: case 0x1: {
6044 OPC_SwitchField, 6, 2, // 12423: switch Inst[7:6] {
6045 0, 153, 1, // 12426: case 0x0: {
6046 OPC_SwitchField, 3, 1, // 12429: switch Inst[3] {
6047 0, 79, // 12432: case 0x0: {
6048 OPC_SwitchField, 10, 1, // 12434: switch Inst[10] {
6049 0, 5, // 12437: case 0x0: {
6050 OPC_Decode, 162, 23, 205, 1, // 12439: decode to XXSLDWI using decoder 205
6051 // 12439: }
6052 1, 0, // 12444: case 0x1: {
6053 OPC_SwitchField, 8, 2, // 12446: switch Inst[9:8] {
6054 0, 5, // 12449: case 0x0: {
6055 OPC_Decode, 133, 23, 181, 1, // 12451: decode to XXLAND using decoder 181
6056 // 12451: }
6057 1, 5, // 12456: case 0x1: {
6058 OPC_Decode, 138, 23, 181, 1, // 12458: decode to XXLNOR using decoder 181
6059 // 12458: }
6060 2, 5, // 12463: case 0x2: {
6061 OPC_Decode, 243, 22, 206, 1, // 12465: decode to XXAESENCP using decoder 206
6062 // 12465: }
6063 3, 0, // 12470: case 0x3: {
6064 OPC_SwitchField, 16, 1, // 12472: switch Inst[16] {
6065 0, 17, // 12475: case 0x0: {
6066 OPC_CheckField, 21, 2, 0, // 12477: check Inst[22:21] == 0x0
6067 OPC_CheckField, 11, 1, 0, // 12481: check Inst[11] == 0x0
6068 OPC_CheckField, 0, 1, 0, // 12485: check Inst[0] == 0x0
6069 OPC_Decode, 201, 6, 207, 1, // 12489: decode to DMXXEXTFDMR512 using decoder 207
6070 // 12489: }
6071 1, 0, // 12494: case 0x1: {
6072 OPC_CheckField, 21, 2, 0, // 12496: check Inst[22:21] == 0x0
6073 OPC_CheckField, 11, 1, 0, // 12500: check Inst[11] == 0x0
6074 OPC_CheckField, 0, 1, 0, // 12504: check Inst[0] == 0x0
6075 OPC_Decode, 202, 6, 208, 1, // 12508: decode to DMXXEXTFDMR512_HI using decoder 208
6076 // 12508: }
6077 // 12508: } // switch Inst[16]
6078 // 12508: }
6079 // 12508: } // switch Inst[9:8]
6080 // 12508: }
6081 // 12508: } // switch Inst[10]
6082 // 12508: }
6083 1, 0, // 12513: case 0x1: {
6084 OPC_SwitchField, 8, 3, // 12515: switch Inst[10:8] {
6085 0, 5, // 12518: case 0x0: {
6086 OPC_Decode, 197, 20, 204, 1, // 12520: decode to XSCMPEQDP using decoder 204
6087 // 12520: }
6088 1, 13, // 12525: case 0x1: {
6089 OPC_CheckField, 21, 2, 0, // 12527: check Inst[22:21] == 0x0
6090 OPC_CheckField, 0, 1, 0, // 12531: check Inst[0] == 0x0
6091 OPC_Decode, 207, 20, 209, 1, // 12535: decode to XSCMPUDP using decoder 209
6092 // 12535: }
6093 2, 5, // 12540: case 0x2: {
6094 OPC_Decode, 220, 21, 181, 1, // 12542: decode to XVCMPEQSP using decoder 181
6095 // 12542: }
6096 3, 5, // 12547: case 0x3: {
6097 OPC_Decode, 218, 21, 181, 1, // 12549: decode to XVCMPEQDP using decoder 181
6098 // 12549: }
6099 4, 5, // 12554: case 0x4: {
6100 OPC_Decode, 207, 21, 181, 1, // 12556: decode to XVADDUWM using decoder 181
6101 // 12556: }
6102 5, 5, // 12561: case 0x5: {
6103 OPC_Decode, 197, 22, 181, 1, // 12563: decode to XVMULUWM using decoder 181
6104 // 12563: }
6105 6, 5, // 12568: case 0x6: {
6106 OPC_Decode, 221, 21, 181, 1, // 12570: decode to XVCMPEQSP_rec using decoder 181
6107 // 12570: }
6108 7, 0, // 12575: case 0x7: {
6109 OPC_Decode, 219, 21, 181, 1, // 12577: decode to XVCMPEQDP_rec using decoder 181
6110 // 12577: }
6111 // 12577: } // switch Inst[10:8]
6112 // 12577: }
6113 // 12577: } // switch Inst[3]
6114 // 12577: }
6115 1, 153, 1, // 12582: case 0x1: {
6116 OPC_SwitchField, 3, 1, // 12585: switch Inst[3] {
6117 0, 79, // 12588: case 0x0: {
6118 OPC_SwitchField, 10, 1, // 12590: switch Inst[10] {
6119 0, 5, // 12593: case 0x0: {
6120 OPC_Decode, 156, 23, 205, 1, // 12595: decode to XXPERMDI using decoder 205
6121 // 12595: }
6122 1, 0, // 12600: case 0x1: {
6123 OPC_SwitchField, 8, 2, // 12602: switch Inst[9:8] {
6124 0, 5, // 12605: case 0x0: {
6125 OPC_Decode, 134, 23, 181, 1, // 12607: decode to XXLANDC using decoder 181
6126 // 12607: }
6127 1, 5, // 12612: case 0x1: {
6128 OPC_Decode, 140, 23, 181, 1, // 12614: decode to XXLORC using decoder 181
6129 // 12614: }
6130 2, 5, // 12619: case 0x2: {
6131 OPC_Decode, 242, 22, 206, 1, // 12621: decode to XXAESDECP using decoder 206
6132 // 12621: }
6133 3, 0, // 12626: case 0x3: {
6134 OPC_SwitchField, 16, 1, // 12628: switch Inst[16] {
6135 0, 17, // 12631: case 0x0: {
6136 OPC_CheckField, 21, 2, 0, // 12633: check Inst[22:21] == 0x0
6137 OPC_CheckField, 11, 1, 0, // 12637: check Inst[11] == 0x0
6138 OPC_CheckField, 0, 1, 0, // 12641: check Inst[0] == 0x0
6139 OPC_Decode, 204, 6, 210, 1, // 12645: decode to DMXXINSTDMR512 using decoder 210
6140 // 12645: }
6141 1, 0, // 12650: case 0x1: {
6142 OPC_CheckField, 21, 2, 0, // 12652: check Inst[22:21] == 0x0
6143 OPC_CheckField, 11, 1, 0, // 12656: check Inst[11] == 0x0
6144 OPC_CheckField, 0, 1, 0, // 12660: check Inst[0] == 0x0
6145 OPC_Decode, 205, 6, 211, 1, // 12664: decode to DMXXINSTDMR512_HI using decoder 211
6146 // 12664: }
6147 // 12664: } // switch Inst[16]
6148 // 12664: }
6149 // 12664: } // switch Inst[9:8]
6150 // 12664: }
6151 // 12664: } // switch Inst[10]
6152 // 12664: }
6153 1, 0, // 12669: case 0x1: {
6154 OPC_SwitchField, 8, 3, // 12671: switch Inst[10:8] {
6155 0, 5, // 12674: case 0x0: {
6156 OPC_Decode, 203, 20, 204, 1, // 12676: decode to XSCMPGTDP using decoder 204
6157 // 12676: }
6158 1, 13, // 12681: case 0x1: {
6159 OPC_CheckField, 21, 2, 0, // 12683: check Inst[22:21] == 0x0
6160 OPC_CheckField, 0, 1, 0, // 12687: check Inst[0] == 0x0
6161 OPC_Decode, 205, 20, 209, 1, // 12691: decode to XSCMPODP using decoder 209
6162 // 12691: }
6163 2, 5, // 12696: case 0x2: {
6164 OPC_Decode, 228, 21, 181, 1, // 12698: decode to XVCMPGTSP using decoder 181
6165 // 12698: }
6166 3, 5, // 12703: case 0x3: {
6167 OPC_Decode, 226, 21, 181, 1, // 12705: decode to XVCMPGTDP using decoder 181
6168 // 12705: }
6169 4, 5, // 12710: case 0x4: {
6170 OPC_Decode, 206, 21, 181, 1, // 12712: decode to XVADDUHM using decoder 181
6171 // 12712: }
6172 5, 5, // 12717: case 0x5: {
6173 OPC_Decode, 196, 22, 181, 1, // 12719: decode to XVMULUHM using decoder 181
6174 // 12719: }
6175 6, 5, // 12724: case 0x6: {
6176 OPC_Decode, 229, 21, 181, 1, // 12726: decode to XVCMPGTSP_rec using decoder 181
6177 // 12726: }
6178 7, 0, // 12731: case 0x7: {
6179 OPC_Decode, 227, 21, 181, 1, // 12733: decode to XVCMPGTDP_rec using decoder 181
6180 // 12733: }
6181 // 12733: } // switch Inst[10:8]
6182 // 12733: }
6183 // 12733: } // switch Inst[3]
6184 // 12733: }
6185 2, 211, 1, // 12738: case 0x2: {
6186 OPC_SwitchField, 8, 3, // 12741: switch Inst[10:8] {
6187 0, 17, // 12744: case 0x0: {
6188 OPC_SwitchField, 3, 1, // 12746: switch Inst[3] {
6189 0, 5, // 12749: case 0x0: {
6190 OPC_Decode, 148, 23, 181, 1, // 12751: decode to XXMRGHW using decoder 181
6191 // 12751: }
6192 1, 0, // 12756: case 0x1: {
6193 OPC_Decode, 201, 20, 204, 1, // 12758: decode to XSCMPGEDP using decoder 204
6194 // 12758: }
6195 // 12758: } // switch Inst[3]
6196 // 12758: }
6197 1, 9, // 12763: case 0x1: {
6198 OPC_CheckField, 3, 1, 0, // 12765: check Inst[3] == 0x0
6199 OPC_Decode, 149, 23, 181, 1, // 12769: decode to XXMRGLW using decoder 181
6200 // 12769: }
6201 2, 33, // 12774: case 0x2: {
6202 OPC_SwitchField, 3, 1, // 12776: switch Inst[3] {
6203 0, 21, // 12779: case 0x0: {
6204 OPC_SwitchField, 2, 1, // 12781: switch Inst[2] {
6205 0, 9, // 12784: case 0x0: {
6206 OPC_CheckField, 18, 3, 0, // 12786: check Inst[20:18] == 0x0
6207 OPC_Decode, 168, 23, 212, 1, // 12790: decode to XXSPLTW using decoder 212
6208 // 12790: }
6209 1, 0, // 12795: case 0x1: {
6210 OPC_Decode, 254, 22, 213, 1, // 12797: decode to XXEXTRACTUW using decoder 213
6211 // 12797: }
6212 // 12797: } // switch Inst[2]
6213 // 12797: }
6214 1, 0, // 12802: case 0x1: {
6215 OPC_Decode, 224, 21, 181, 1, // 12804: decode to XVCMPGESP using decoder 181
6216 // 12804: }
6217 // 12804: } // switch Inst[3]
6218 // 12804: }
6219 3, 17, // 12809: case 0x3: {
6220 OPC_SwitchField, 3, 1, // 12811: switch Inst[3] {
6221 0, 5, // 12814: case 0x0: {
6222 OPC_Decode, 194, 22, 181, 1, // 12816: decode to XVMULHUW using decoder 181
6223 // 12816: }
6224 1, 0, // 12821: case 0x1: {
6225 OPC_Decode, 222, 21, 181, 1, // 12823: decode to XVCMPGEDP using decoder 181
6226 // 12823: }
6227 // 12823: } // switch Inst[3]
6228 // 12823: }
6229 4, 17, // 12828: case 0x4: {
6230 OPC_SwitchField, 3, 1, // 12830: switch Inst[3] {
6231 0, 5, // 12833: case 0x0: {
6232 OPC_Decode, 139, 23, 181, 1, // 12835: decode to XXLOR using decoder 181
6233 // 12835: }
6234 1, 0, // 12840: case 0x1: {
6235 OPC_Decode, 230, 22, 181, 1, // 12842: decode to XVSUBUWM using decoder 181
6236 // 12842: }
6237 // 12842: } // switch Inst[3]
6238 // 12842: }
6239 5, 17, // 12847: case 0x5: {
6240 OPC_SwitchField, 3, 1, // 12849: switch Inst[3] {
6241 0, 5, // 12852: case 0x0: {
6242 OPC_Decode, 137, 23, 181, 1, // 12854: decode to XXLNAND using decoder 181
6243 // 12854: }
6244 1, 0, // 12859: case 0x1: {
6245 OPC_Decode, 192, 22, 181, 1, // 12861: decode to XVMULHSW using decoder 181
6246 // 12861: }
6247 // 12861: } // switch Inst[3]
6248 // 12861: }
6249 6, 37, // 12866: case 0x6: {
6250 OPC_SwitchField, 3, 1, // 12868: switch Inst[3] {
6251 0, 25, // 12871: case 0x0: {
6252 OPC_SwitchField, 2, 1, // 12873: switch Inst[2] {
6253 0, 5, // 12876: case 0x0: {
6254 OPC_Decode, 244, 22, 214, 1, // 12878: decode to XXAESGENLKP using decoder 214
6255 // 12878: }
6256 1, 0, // 12883: case 0x1: {
6257 OPC_CheckField, 21, 2, 0, // 12885: check Inst[22:21] == 0x0
6258 OPC_CheckField, 0, 1, 0, // 12889: check Inst[0] == 0x0
6259 OPC_Decode, 207, 6, 215, 1, // 12893: decode to DMXXSHAPAD using decoder 215
6260 // 12893: }
6261 // 12893: } // switch Inst[2]
6262 // 12893: }
6263 1, 0, // 12898: case 0x1: {
6264 OPC_Decode, 225, 21, 181, 1, // 12900: decode to XVCMPGESP_rec using decoder 181
6265 // 12900: }
6266 // 12900: } // switch Inst[3]
6267 // 12900: }
6268 7, 0, // 12905: case 0x7: {
6269 OPC_SwitchField, 3, 1, // 12907: switch Inst[3] {
6270 0, 33, // 12910: case 0x0: {
6271 OPC_SwitchField, 2, 1, // 12912: switch Inst[2] {
6272 0, 13, // 12915: case 0x0: {
6273 OPC_CheckField, 17, 6, 0, // 12917: check Inst[22:17] == 0x0
6274 OPC_CheckField, 0, 1, 0, // 12921: check Inst[0] == 0x0
6275 OPC_Decode, 200, 6, 216, 1, // 12925: decode to DMXXEXTFDMR256 using decoder 216
6276 // 12925: }
6277 1, 0, // 12930: case 0x1: {
6278 OPC_CheckField, 17, 6, 0, // 12932: check Inst[22:17] == 0x0
6279 OPC_CheckField, 0, 1, 0, // 12936: check Inst[0] == 0x0
6280 OPC_Decode, 203, 6, 217, 1, // 12940: decode to DMXXINSTDMR256 using decoder 217
6281 // 12940: }
6282 // 12940: } // switch Inst[2]
6283 // 12940: }
6284 1, 0, // 12945: case 0x1: {
6285 OPC_Decode, 223, 21, 181, 1, // 12947: decode to XVCMPGEDP_rec using decoder 181
6286 // 12947: }
6287 // 12947: } // switch Inst[3]
6288 // 12947: }
6289 // 12947: } // switch Inst[10:8]
6290 // 12947: }
6291 3, 0, // 12952: case 0x3: {
6292 OPC_SwitchField, 9, 2, // 12954: switch Inst[10:9] {
6293 0, 41, // 12957: case 0x0: {
6294 OPC_SwitchField, 3, 1, // 12959: switch Inst[3] {
6295 0, 17, // 12962: case 0x0: {
6296 OPC_SwitchField, 8, 1, // 12964: switch Inst[8] {
6297 0, 5, // 12967: case 0x0: {
6298 OPC_Decode, 155, 23, 218, 1, // 12969: decode to XXPERM using decoder 218
6299 // 12969: }
6300 1, 0, // 12974: case 0x1: {
6301 OPC_Decode, 158, 23, 218, 1, // 12976: decode to XXPERMR using decoder 218
6302 // 12976: }
6303 // 12976: } // switch Inst[8]
6304 // 12976: }
6305 1, 0, // 12981: case 0x1: {
6306 OPC_CheckField, 21, 2, 0, // 12983: check Inst[22:21] == 0x0
6307 OPC_CheckField, 8, 1, 1, // 12987: check Inst[8] == 0x1
6308 OPC_CheckField, 0, 1, 0, // 12991: check Inst[0] == 0x0
6309 OPC_Decode, 199, 20, 209, 1, // 12995: decode to XSCMPEXPDP using decoder 209
6310 // 12995: }
6311 // 12995: } // switch Inst[3]
6312 // 12995: }
6313 1, 57, // 13000: case 0x1: {
6314 OPC_SwitchField, 8, 1, // 13002: switch Inst[8] {
6315 0, 41, // 13005: case 0x0: {
6316 OPC_SwitchField, 2, 2, // 13007: switch Inst[3:2] {
6317 0, 29, // 13010: case 0x0: {
6318 OPC_SwitchField, 19, 2, // 13012: switch Inst[20:19] {
6319 0, 9, // 13015: case 0x0: {
6320 OPC_CheckField, 1, 1, 0, // 13017: check Inst[1] == 0x0
6321 OPC_Decode, 165, 23, 219, 1, // 13021: decode to XXSPLTIB using decoder 219
6322 // 13021: }
6323 3, 0, // 13026: case 0x3: {
6324 OPC_CheckField, 16, 3, 7, // 13028: check Inst[18:16] == 0x7
6325 OPC_CheckField, 1, 1, 0, // 13032: check Inst[1] == 0x0
6326 OPC_Decode, 196, 11, 220, 1, // 13036: decode to LXVKQ using decoder 220
6327 // 13036: }
6328 // 13036: } // switch Inst[20:19]
6329 // 13036: }
6330 1, 0, // 13041: case 0x1: {
6331 OPC_Decode, 132, 23, 221, 1, // 13043: decode to XXINSERTW using decoder 221
6332 // 13043: }
6333 // 13043: } // switch Inst[3:2]
6334 // 13043: }
6335 1, 0, // 13048: case 0x1: {
6336 OPC_CheckField, 3, 1, 0, // 13050: check Inst[3] == 0x0
6337 OPC_Decode, 193, 22, 181, 1, // 13054: decode to XVMULHUH using decoder 181
6338 // 13054: }
6339 // 13054: } // switch Inst[8]
6340 // 13054: }
6341 2, 41, // 13059: case 0x2: {
6342 OPC_SwitchField, 3, 1, // 13061: switch Inst[3] {
6343 0, 17, // 13064: case 0x0: {
6344 OPC_SwitchField, 8, 1, // 13066: switch Inst[8] {
6345 0, 5, // 13069: case 0x0: {
6346 OPC_Decode, 142, 23, 181, 1, // 13071: decode to XXLXOR using decoder 181
6347 // 13071: }
6348 1, 0, // 13076: case 0x1: {
6349 OPC_Decode, 135, 23, 181, 1, // 13078: decode to XXLEQV using decoder 181
6350 // 13078: }
6351 // 13078: } // switch Inst[8]
6352 // 13078: }
6353 1, 0, // 13083: case 0x1: {
6354 OPC_SwitchField, 8, 1, // 13085: switch Inst[8] {
6355 0, 5, // 13088: case 0x0: {
6356 OPC_Decode, 229, 22, 181, 1, // 13090: decode to XVSUBUHM using decoder 181
6357 // 13090: }
6358 1, 0, // 13095: case 0x1: {
6359 OPC_Decode, 191, 22, 181, 1, // 13097: decode to XVMULHSH using decoder 181
6360 // 13097: }
6361 // 13097: } // switch Inst[8]
6362 // 13097: }
6363 // 13097: } // switch Inst[3]
6364 // 13097: }
6365 3, 0, // 13102: case 0x3: {
6366 OPC_CheckField, 3, 1, 0, // 13104: check Inst[3] == 0x0
6367 OPC_Decode, 131, 23, 222, 1, // 13108: decode to XXGFMUL128 using decoder 222
6368 // 13108: }
6369 // 13108: } // switch Inst[10:9]
6370 // 13108: }
6371 // 13108: } // switch Inst[7:6]
6372 // 13108: }
6373 2, 234, 10, // 13113: case 0x2: {
6374 OPC_SwitchField, 7, 4, // 13116: switch Inst[10:7] {
6375 0, 45, // 13119: case 0x0: {
6376 OPC_SwitchField, 2, 2, // 13121: switch Inst[3:2] {
6377 2, 25, // 13124: case 0x2: {
6378 OPC_SwitchField, 6, 1, // 13126: switch Inst[6] {
6379 0, 9, // 13129: case 0x0: {
6380 OPC_CheckField, 16, 5, 0, // 13131: check Inst[20:16] == 0x0
6381 OPC_Decode, 184, 21, 223, 1, // 13135: decode to XSRSQRTESP using decoder 223
6382 // 13135: }
6383 1, 0, // 13140: case 0x1: {
6384 OPC_CheckField, 16, 5, 0, // 13142: check Inst[20:16] == 0x0
6385 OPC_Decode, 178, 21, 223, 1, // 13146: decode to XSRESP using decoder 223
6386 // 13146: }
6387 // 13146: } // switch Inst[6]
6388 // 13146: }
6389 3, 0, // 13151: case 0x3: {
6390 OPC_CheckField, 16, 5, 0, // 13153: check Inst[20:16] == 0x0
6391 OPC_CheckField, 6, 1, 0, // 13157: check Inst[6] == 0x0
6392 OPC_Decode, 188, 21, 223, 1, // 13161: decode to XSSQRTSP using decoder 223
6393 // 13161: }
6394 // 13161: } // switch Inst[3:2]
6395 // 13161: }
6396 2, 99, // 13166: case 0x2: {
6397 OPC_SwitchField, 2, 2, // 13168: switch Inst[3:2] {
6398 0, 25, // 13171: case 0x0: {
6399 OPC_SwitchField, 6, 1, // 13173: switch Inst[6] {
6400 0, 9, // 13176: case 0x0: {
6401 OPC_CheckField, 16, 5, 0, // 13178: check Inst[20:16] == 0x0
6402 OPC_Decode, 221, 20, 224, 1, // 13182: decode to XSCVDPUXWS using decoder 224
6403 // 13182: }
6404 1, 0, // 13187: case 0x1: {
6405 OPC_CheckField, 16, 5, 0, // 13189: check Inst[20:16] == 0x0
6406 OPC_Decode, 217, 20, 224, 1, // 13193: decode to XSCVDPSXWS using decoder 224
6407 // 13193: }
6408 // 13193: } // switch Inst[6]
6409 // 13193: }
6410 1, 25, // 13198: case 0x1: {
6411 OPC_SwitchField, 6, 1, // 13200: switch Inst[6] {
6412 0, 9, // 13203: case 0x0: {
6413 OPC_CheckField, 16, 5, 0, // 13205: check Inst[20:16] == 0x0
6414 OPC_Decode, 165, 21, 224, 1, // 13209: decode to XSRDPI using decoder 224
6415 // 13209: }
6416 1, 0, // 13214: case 0x1: {
6417 OPC_CheckField, 16, 5, 0, // 13216: check Inst[20:16] == 0x0
6418 OPC_Decode, 169, 21, 224, 1, // 13220: decode to XSRDPIZ using decoder 224
6419 // 13220: }
6420 // 13220: } // switch Inst[6]
6421 // 13220: }
6422 2, 25, // 13225: case 0x2: {
6423 OPC_SwitchField, 6, 1, // 13227: switch Inst[6] {
6424 0, 9, // 13230: case 0x0: {
6425 OPC_CheckField, 16, 5, 0, // 13232: check Inst[20:16] == 0x0
6426 OPC_Decode, 183, 21, 224, 1, // 13236: decode to XSRSQRTEDP using decoder 224
6427 // 13236: }
6428 1, 0, // 13241: case 0x1: {
6429 OPC_CheckField, 16, 5, 0, // 13243: check Inst[20:16] == 0x0
6430 OPC_Decode, 177, 21, 224, 1, // 13247: decode to XSREDP using decoder 224
6431 // 13247: }
6432 // 13247: } // switch Inst[6]
6433 // 13247: }
6434 3, 0, // 13252: case 0x3: {
6435 OPC_CheckField, 16, 5, 0, // 13254: check Inst[20:16] == 0x0
6436 OPC_CheckField, 6, 1, 0, // 13258: check Inst[6] == 0x0
6437 OPC_Decode, 185, 21, 224, 1, // 13262: decode to XSSQRTDP using decoder 224
6438 // 13262: }
6439 // 13262: } // switch Inst[3:2]
6440 // 13262: }
6441 3, 89, // 13267: case 0x3: {
6442 OPC_SwitchField, 3, 1, // 13269: switch Inst[3] {
6443 0, 33, // 13272: case 0x0: {
6444 OPC_SwitchField, 6, 1, // 13274: switch Inst[6] {
6445 0, 13, // 13277: case 0x0: {
6446 OPC_CheckField, 16, 5, 0, // 13279: check Inst[20:16] == 0x0
6447 OPC_CheckField, 2, 1, 1, // 13283: check Inst[2] == 0x1
6448 OPC_Decode, 168, 21, 224, 1, // 13287: decode to XSRDPIP using decoder 224
6449 // 13287: }
6450 1, 0, // 13292: case 0x1: {
6451 OPC_CheckField, 16, 5, 0, // 13294: check Inst[20:16] == 0x0
6452 OPC_CheckField, 2, 1, 1, // 13298: check Inst[2] == 0x1
6453 OPC_Decode, 167, 21, 224, 1, // 13302: decode to XSRDPIM using decoder 224
6454 // 13302: }
6455 // 13302: } // switch Inst[6]
6456 // 13302: }
6457 1, 0, // 13307: case 0x1: {
6458 OPC_SwitchField, 6, 1, // 13309: switch Inst[6] {
6459 0, 29, // 13312: case 0x0: {
6460 OPC_SwitchField, 2, 1, // 13314: switch Inst[2] {
6461 0, 13, // 13317: case 0x0: {
6462 OPC_CheckField, 16, 7, 0, // 13319: check Inst[22:16] == 0x0
6463 OPC_CheckField, 0, 1, 0, // 13323: check Inst[0] == 0x0
6464 OPC_Decode, 194, 21, 225, 1, // 13327: decode to XSTSQRTDP using decoder 225
6465 // 13327: }
6466 1, 0, // 13332: case 0x1: {
6467 OPC_CheckField, 16, 5, 0, // 13334: check Inst[20:16] == 0x0
6468 OPC_Decode, 166, 21, 224, 1, // 13338: decode to XSRDPIC using decoder 224
6469 // 13338: }
6470 // 13338: } // switch Inst[2]
6471 // 13338: }
6472 1, 0, // 13343: case 0x1: {
6473 OPC_CheckField, 21, 2, 0, // 13345: check Inst[22:21] == 0x0
6474 OPC_CheckField, 0, 1, 0, // 13349: check Inst[0] == 0x0
6475 OPC_Decode, 193, 21, 209, 1, // 13353: decode to XSTDIVDP using decoder 209
6476 // 13353: }
6477 // 13353: } // switch Inst[6]
6478 // 13353: }
6479 // 13353: } // switch Inst[3]
6480 // 13353: }
6481 4, 99, // 13358: case 0x4: {
6482 OPC_SwitchField, 2, 2, // 13360: switch Inst[3:2] {
6483 0, 25, // 13363: case 0x0: {
6484 OPC_SwitchField, 6, 1, // 13365: switch Inst[6] {
6485 0, 9, // 13368: case 0x0: {
6486 OPC_CheckField, 16, 5, 0, // 13370: check Inst[20:16] == 0x0
6487 OPC_Decode, 245, 21, 226, 1, // 13374: decode to XVCVSPUXWS using decoder 226
6488 // 13374: }
6489 1, 0, // 13379: case 0x1: {
6490 OPC_CheckField, 16, 5, 0, // 13381: check Inst[20:16] == 0x0
6491 OPC_Decode, 243, 21, 226, 1, // 13385: decode to XVCVSPSXWS using decoder 226
6492 // 13385: }
6493 // 13385: } // switch Inst[6]
6494 // 13385: }
6495 1, 25, // 13390: case 0x1: {
6496 OPC_SwitchField, 6, 1, // 13392: switch Inst[6] {
6497 0, 9, // 13395: case 0x0: {
6498 OPC_CheckField, 16, 5, 0, // 13397: check Inst[20:16] == 0x0
6499 OPC_Decode, 218, 22, 226, 1, // 13401: decode to XVRSPI using decoder 226
6500 // 13401: }
6501 1, 0, // 13406: case 0x1: {
6502 OPC_CheckField, 16, 5, 0, // 13408: check Inst[20:16] == 0x0
6503 OPC_Decode, 222, 22, 226, 1, // 13412: decode to XVRSPIZ using decoder 226
6504 // 13412: }
6505 // 13412: } // switch Inst[6]
6506 // 13412: }
6507 2, 25, // 13417: case 0x2: {
6508 OPC_SwitchField, 6, 1, // 13419: switch Inst[6] {
6509 0, 9, // 13422: case 0x0: {
6510 OPC_CheckField, 16, 5, 0, // 13424: check Inst[20:16] == 0x0
6511 OPC_Decode, 224, 22, 226, 1, // 13428: decode to XVRSQRTESP using decoder 226
6512 // 13428: }
6513 1, 0, // 13433: case 0x1: {
6514 OPC_CheckField, 16, 5, 0, // 13435: check Inst[20:16] == 0x0
6515 OPC_Decode, 216, 22, 226, 1, // 13439: decode to XVRESP using decoder 226
6516 // 13439: }
6517 // 13439: } // switch Inst[6]
6518 // 13439: }
6519 3, 0, // 13444: case 0x3: {
6520 OPC_CheckField, 16, 5, 0, // 13446: check Inst[20:16] == 0x0
6521 OPC_CheckField, 6, 1, 0, // 13450: check Inst[6] == 0x0
6522 OPC_Decode, 226, 22, 226, 1, // 13454: decode to XVSQRTSP using decoder 226
6523 // 13454: }
6524 // 13454: } // switch Inst[3:2]
6525 // 13454: }
6526 5, 113, // 13459: case 0x5: {
6527 OPC_SwitchField, 3, 1, // 13461: switch Inst[3] {
6528 0, 57, // 13464: case 0x0: {
6529 OPC_SwitchField, 2, 1, // 13466: switch Inst[2] {
6530 0, 25, // 13469: case 0x0: {
6531 OPC_SwitchField, 6, 1, // 13471: switch Inst[6] {
6532 0, 9, // 13474: case 0x0: {
6533 OPC_CheckField, 16, 5, 0, // 13476: check Inst[20:16] == 0x0
6534 OPC_Decode, 253, 21, 226, 1, // 13480: decode to XVCVUXWSP using decoder 226
6535 // 13480: }
6536 1, 0, // 13485: case 0x1: {
6537 OPC_CheckField, 16, 5, 0, // 13487: check Inst[20:16] == 0x0
6538 OPC_Decode, 249, 21, 226, 1, // 13491: decode to XVCVSXWSP using decoder 226
6539 // 13491: }
6540 // 13491: } // switch Inst[6]
6541 // 13491: }
6542 1, 0, // 13496: case 0x1: {
6543 OPC_SwitchField, 6, 1, // 13498: switch Inst[6] {
6544 0, 9, // 13501: case 0x0: {
6545 OPC_CheckField, 16, 5, 0, // 13503: check Inst[20:16] == 0x0
6546 OPC_Decode, 221, 22, 226, 1, // 13507: decode to XVRSPIP using decoder 226
6547 // 13507: }
6548 1, 0, // 13512: case 0x1: {
6549 OPC_CheckField, 16, 5, 0, // 13514: check Inst[20:16] == 0x0
6550 OPC_Decode, 220, 22, 226, 1, // 13518: decode to XVRSPIM using decoder 226
6551 // 13518: }
6552 // 13518: } // switch Inst[6]
6553 // 13518: }
6554 // 13518: } // switch Inst[2]
6555 // 13518: }
6556 1, 0, // 13523: case 0x1: {
6557 OPC_SwitchField, 6, 1, // 13525: switch Inst[6] {
6558 0, 29, // 13528: case 0x0: {
6559 OPC_SwitchField, 2, 1, // 13530: switch Inst[2] {
6560 0, 13, // 13533: case 0x0: {
6561 OPC_CheckField, 16, 7, 0, // 13535: check Inst[22:16] == 0x0
6562 OPC_CheckField, 0, 1, 0, // 13539: check Inst[0] == 0x0
6563 OPC_Decode, 235, 22, 227, 1, // 13543: decode to XVTSQRTSP using decoder 227
6564 // 13543: }
6565 1, 0, // 13548: case 0x1: {
6566 OPC_CheckField, 16, 5, 0, // 13550: check Inst[20:16] == 0x0
6567 OPC_Decode, 219, 22, 226, 1, // 13554: decode to XVRSPIC using decoder 226
6568 // 13554: }
6569 // 13554: } // switch Inst[2]
6570 // 13554: }
6571 1, 0, // 13559: case 0x1: {
6572 OPC_CheckField, 21, 2, 0, // 13561: check Inst[22:21] == 0x0
6573 OPC_CheckField, 0, 1, 0, // 13565: check Inst[0] == 0x0
6574 OPC_Decode, 232, 22, 228, 1, // 13569: decode to XVTDIVSP using decoder 228
6575 // 13569: }
6576 // 13569: } // switch Inst[6]
6577 // 13569: }
6578 // 13569: } // switch Inst[3]
6579 // 13569: }
6580 6, 99, // 13574: case 0x6: {
6581 OPC_SwitchField, 2, 2, // 13576: switch Inst[3:2] {
6582 0, 25, // 13579: case 0x0: {
6583 OPC_SwitchField, 6, 1, // 13581: switch Inst[6] {
6584 0, 9, // 13584: case 0x0: {
6585 OPC_CheckField, 16, 5, 0, // 13586: check Inst[20:16] == 0x0
6586 OPC_Decode, 237, 21, 226, 1, // 13590: decode to XVCVDPUXWS using decoder 226
6587 // 13590: }
6588 1, 0, // 13595: case 0x1: {
6589 OPC_CheckField, 16, 5, 0, // 13597: check Inst[20:16] == 0x0
6590 OPC_Decode, 235, 21, 226, 1, // 13601: decode to XVCVDPSXWS using decoder 226
6591 // 13601: }
6592 // 13601: } // switch Inst[6]
6593 // 13601: }
6594 1, 25, // 13606: case 0x1: {
6595 OPC_SwitchField, 6, 1, // 13608: switch Inst[6] {
6596 0, 9, // 13611: case 0x0: {
6597 OPC_CheckField, 16, 5, 0, // 13613: check Inst[20:16] == 0x0
6598 OPC_Decode, 210, 22, 226, 1, // 13617: decode to XVRDPI using decoder 226
6599 // 13617: }
6600 1, 0, // 13622: case 0x1: {
6601 OPC_CheckField, 16, 5, 0, // 13624: check Inst[20:16] == 0x0
6602 OPC_Decode, 214, 22, 226, 1, // 13628: decode to XVRDPIZ using decoder 226
6603 // 13628: }
6604 // 13628: } // switch Inst[6]
6605 // 13628: }
6606 2, 25, // 13633: case 0x2: {
6607 OPC_SwitchField, 6, 1, // 13635: switch Inst[6] {
6608 0, 9, // 13638: case 0x0: {
6609 OPC_CheckField, 16, 5, 0, // 13640: check Inst[20:16] == 0x0
6610 OPC_Decode, 223, 22, 226, 1, // 13644: decode to XVRSQRTEDP using decoder 226
6611 // 13644: }
6612 1, 0, // 13649: case 0x1: {
6613 OPC_CheckField, 16, 5, 0, // 13651: check Inst[20:16] == 0x0
6614 OPC_Decode, 215, 22, 226, 1, // 13655: decode to XVREDP using decoder 226
6615 // 13655: }
6616 // 13655: } // switch Inst[6]
6617 // 13655: }
6618 3, 0, // 13660: case 0x3: {
6619 OPC_CheckField, 16, 5, 0, // 13662: check Inst[20:16] == 0x0
6620 OPC_CheckField, 6, 1, 0, // 13666: check Inst[6] == 0x0
6621 OPC_Decode, 225, 22, 226, 1, // 13670: decode to XVSQRTDP using decoder 226
6622 // 13670: }
6623 // 13670: } // switch Inst[3:2]
6624 // 13670: }
6625 7, 113, // 13675: case 0x7: {
6626 OPC_SwitchField, 3, 1, // 13677: switch Inst[3] {
6627 0, 57, // 13680: case 0x0: {
6628 OPC_SwitchField, 2, 1, // 13682: switch Inst[2] {
6629 0, 25, // 13685: case 0x0: {
6630 OPC_SwitchField, 6, 1, // 13687: switch Inst[6] {
6631 0, 9, // 13690: case 0x0: {
6632 OPC_CheckField, 16, 5, 0, // 13692: check Inst[20:16] == 0x0
6633 OPC_Decode, 252, 21, 226, 1, // 13696: decode to XVCVUXWDP using decoder 226
6634 // 13696: }
6635 1, 0, // 13701: case 0x1: {
6636 OPC_CheckField, 16, 5, 0, // 13703: check Inst[20:16] == 0x0
6637 OPC_Decode, 248, 21, 226, 1, // 13707: decode to XVCVSXWDP using decoder 226
6638 // 13707: }
6639 // 13707: } // switch Inst[6]
6640 // 13707: }
6641 1, 0, // 13712: case 0x1: {
6642 OPC_SwitchField, 6, 1, // 13714: switch Inst[6] {
6643 0, 9, // 13717: case 0x0: {
6644 OPC_CheckField, 16, 5, 0, // 13719: check Inst[20:16] == 0x0
6645 OPC_Decode, 213, 22, 226, 1, // 13723: decode to XVRDPIP using decoder 226
6646 // 13723: }
6647 1, 0, // 13728: case 0x1: {
6648 OPC_CheckField, 16, 5, 0, // 13730: check Inst[20:16] == 0x0
6649 OPC_Decode, 212, 22, 226, 1, // 13734: decode to XVRDPIM using decoder 226
6650 // 13734: }
6651 // 13734: } // switch Inst[6]
6652 // 13734: }
6653 // 13734: } // switch Inst[2]
6654 // 13734: }
6655 1, 0, // 13739: case 0x1: {
6656 OPC_SwitchField, 6, 1, // 13741: switch Inst[6] {
6657 0, 29, // 13744: case 0x0: {
6658 OPC_SwitchField, 2, 1, // 13746: switch Inst[2] {
6659 0, 13, // 13749: case 0x0: {
6660 OPC_CheckField, 16, 7, 0, // 13751: check Inst[22:16] == 0x0
6661 OPC_CheckField, 0, 1, 0, // 13755: check Inst[0] == 0x0
6662 OPC_Decode, 234, 22, 227, 1, // 13759: decode to XVTSQRTDP using decoder 227
6663 // 13759: }
6664 1, 0, // 13764: case 0x1: {
6665 OPC_CheckField, 16, 5, 0, // 13766: check Inst[20:16] == 0x0
6666 OPC_Decode, 211, 22, 226, 1, // 13770: decode to XVRDPIC using decoder 226
6667 // 13770: }
6668 // 13770: } // switch Inst[2]
6669 // 13770: }
6670 1, 0, // 13775: case 0x1: {
6671 OPC_CheckField, 21, 2, 0, // 13777: check Inst[22:21] == 0x0
6672 OPC_CheckField, 0, 1, 0, // 13781: check Inst[0] == 0x0
6673 OPC_Decode, 231, 22, 228, 1, // 13785: decode to XVTDIVDP using decoder 228
6674 // 13785: }
6675 // 13785: } // switch Inst[6]
6676 // 13785: }
6677 // 13785: } // switch Inst[3]
6678 // 13785: }
6679 8, 45, // 13790: case 0x8: {
6680 OPC_SwitchField, 2, 2, // 13792: switch Inst[3:2] {
6681 1, 25, // 13795: case 0x1: {
6682 OPC_SwitchField, 6, 1, // 13797: switch Inst[6] {
6683 0, 9, // 13800: case 0x0: {
6684 OPC_CheckField, 16, 5, 0, // 13802: check Inst[20:16] == 0x0
6685 OPC_Decode, 213, 20, 224, 1, // 13806: decode to XSCVDPSP using decoder 224
6686 // 13806: }
6687 1, 0, // 13811: case 0x1: {
6688 OPC_CheckField, 16, 5, 0, // 13813: check Inst[20:16] == 0x0
6689 OPC_Decode, 182, 21, 229, 1, // 13817: decode to XSRSP using decoder 229
6690 // 13817: }
6691 // 13817: } // switch Inst[6]
6692 // 13817: }
6693 3, 0, // 13822: case 0x3: {
6694 OPC_CheckField, 16, 5, 0, // 13824: check Inst[20:16] == 0x0
6695 OPC_CheckField, 6, 1, 0, // 13828: check Inst[6] == 0x0
6696 OPC_Decode, 214, 20, 230, 1, // 13832: decode to XSCVDPSPN using decoder 230
6697 // 13832: }
6698 // 13832: } // switch Inst[3:2]
6699 // 13832: }
6700 9, 45, // 13837: case 0x9: {
6701 OPC_SwitchField, 2, 2, // 13839: switch Inst[3:2] {
6702 0, 25, // 13842: case 0x0: {
6703 OPC_SwitchField, 6, 1, // 13844: switch Inst[6] {
6704 0, 9, // 13847: case 0x0: {
6705 OPC_CheckField, 16, 5, 0, // 13849: check Inst[20:16] == 0x0
6706 OPC_Decode, 241, 20, 229, 1, // 13853: decode to XSCVUXDSP using decoder 229
6707 // 13853: }
6708 1, 0, // 13858: case 0x1: {
6709 OPC_CheckField, 16, 5, 0, // 13860: check Inst[20:16] == 0x0
6710 OPC_Decode, 237, 20, 229, 1, // 13864: decode to XSCVSXDSP using decoder 229
6711 // 13864: }
6712 // 13864: } // switch Inst[6]
6713 // 13864: }
6714 2, 0, // 13869: case 0x2: {
6715 OPC_CheckField, 6, 1, 0, // 13871: check Inst[6] == 0x0
6716 OPC_CheckField, 0, 1, 0, // 13875: check Inst[0] == 0x0
6717 OPC_Decode, 197, 21, 231, 1, // 13879: decode to XSTSTDCSP using decoder 231
6718 // 13879: }
6719 // 13879: } // switch Inst[3:2]
6720 // 13879: }
6721 10, 118, // 13884: case 0xa: {
6722 OPC_SwitchField, 16, 5, // 13886: switch Inst[20:16] {
6723 0, 64, // 13889: case 0x0: {
6724 OPC_SwitchField, 2, 2, // 13891: switch Inst[3:2] {
6725 0, 17, // 13894: case 0x0: {
6726 OPC_SwitchField, 6, 1, // 13896: switch Inst[6] {
6727 0, 5, // 13899: case 0x0: {
6728 OPC_Decode, 219, 20, 224, 1, // 13901: decode to XSCVDPUXDS using decoder 224
6729 // 13901: }
6730 1, 0, // 13906: case 0x1: {
6731 OPC_Decode, 215, 20, 224, 1, // 13908: decode to XSCVDPSXDS using decoder 224
6732 // 13908: }
6733 // 13908: } // switch Inst[6]
6734 // 13908: }
6735 1, 17, // 13913: case 0x1: {
6736 OPC_SwitchField, 6, 1, // 13915: switch Inst[6] {
6737 0, 5, // 13918: case 0x0: {
6738 OPC_Decode, 233, 20, 224, 1, // 13920: decode to XSCVSPDP using decoder 224
6739 // 13920: }
6740 1, 0, // 13925: case 0x1: {
6741 OPC_Decode, 187, 20, 224, 1, // 13927: decode to XSABSDP using decoder 224
6742 // 13927: }
6743 // 13927: } // switch Inst[6]
6744 // 13927: }
6745 3, 0, // 13932: case 0x3: {
6746 OPC_SwitchField, 6, 1, // 13934: switch Inst[6] {
6747 0, 5, // 13937: case 0x0: {
6748 OPC_Decode, 234, 20, 232, 1, // 13939: decode to XSCVSPDPN using decoder 232
6749 // 13939: }
6750 1, 0, // 13944: case 0x1: {
6751 OPC_CheckField, 0, 1, 0, // 13946: check Inst[0] == 0x0
6752 OPC_Decode, 198, 21, 233, 1, // 13950: decode to XSXEXPDP using decoder 233
6753 // 13950: }
6754 // 13950: } // switch Inst[6]
6755 // 13950: }
6756 // 13950: } // switch Inst[3:2]
6757 // 13950: }
6758 1, 17, // 13955: case 0x1: {
6759 OPC_CheckField, 6, 1, 1, // 13957: check Inst[6] == 0x1
6760 OPC_CheckField, 2, 2, 3, // 13961: check Inst[3:2] == 0x3
6761 OPC_CheckField, 0, 1, 0, // 13965: check Inst[0] == 0x0
6762 OPC_Decode, 200, 21, 233, 1, // 13969: decode to XSXSIGDP using decoder 233
6763 // 13969: }
6764 16, 13, // 13974: case 0x10: {
6765 OPC_CheckField, 6, 1, 1, // 13976: check Inst[6] == 0x1
6766 OPC_CheckField, 2, 2, 3, // 13980: check Inst[3:2] == 0x3
6767 OPC_Decode, 223, 20, 224, 1, // 13984: decode to XSCVHPDP using decoder 224
6768 // 13984: }
6769 17, 0, // 13989: case 0x11: {
6770 OPC_CheckField, 6, 1, 1, // 13991: check Inst[6] == 0x1
6771 OPC_CheckField, 2, 2, 3, // 13995: check Inst[3:2] == 0x3
6772 OPC_Decode, 211, 20, 224, 1, // 13999: decode to XSCVDPHP using decoder 224
6773 // 13999: }
6774 // 13999: } // switch Inst[20:16]
6775 // 13999: }
6776 11, 72, // 14004: case 0xb: {
6777 OPC_SwitchField, 2, 2, // 14006: switch Inst[3:2] {
6778 0, 25, // 14009: case 0x0: {
6779 OPC_SwitchField, 6, 1, // 14011: switch Inst[6] {
6780 0, 9, // 14014: case 0x0: {
6781 OPC_CheckField, 16, 5, 0, // 14016: check Inst[20:16] == 0x0
6782 OPC_Decode, 240, 20, 224, 1, // 14020: decode to XSCVUXDDP using decoder 224
6783 // 14020: }
6784 1, 0, // 14025: case 0x1: {
6785 OPC_CheckField, 16, 5, 0, // 14027: check Inst[20:16] == 0x0
6786 OPC_Decode, 236, 20, 224, 1, // 14031: decode to XSCVSXDDP using decoder 224
6787 // 14031: }
6788 // 14031: } // switch Inst[6]
6789 // 14031: }
6790 1, 25, // 14036: case 0x1: {
6791 OPC_SwitchField, 6, 1, // 14038: switch Inst[6] {
6792 0, 9, // 14041: case 0x0: {
6793 OPC_CheckField, 16, 5, 0, // 14043: check Inst[20:16] == 0x0
6794 OPC_Decode, 148, 21, 224, 1, // 14047: decode to XSNABSDP using decoder 224
6795 // 14047: }
6796 1, 0, // 14052: case 0x1: {
6797 OPC_CheckField, 16, 5, 0, // 14054: check Inst[20:16] == 0x0
6798 OPC_Decode, 151, 21, 224, 1, // 14058: decode to XSNEGDP using decoder 224
6799 // 14058: }
6800 // 14058: } // switch Inst[6]
6801 // 14058: }
6802 2, 0, // 14063: case 0x2: {
6803 OPC_CheckField, 6, 1, 0, // 14065: check Inst[6] == 0x0
6804 OPC_CheckField, 0, 1, 0, // 14069: check Inst[0] == 0x0
6805 OPC_Decode, 195, 21, 234, 1, // 14073: decode to XSTSTDCDP using decoder 234
6806 // 14073: }
6807 // 14073: } // switch Inst[3:2]
6808 // 14073: }
6809 12, 57, // 14078: case 0xc: {
6810 OPC_SwitchField, 2, 2, // 14080: switch Inst[3:2] {
6811 0, 25, // 14083: case 0x0: {
6812 OPC_SwitchField, 6, 1, // 14085: switch Inst[6] {
6813 0, 9, // 14088: case 0x0: {
6814 OPC_CheckField, 16, 5, 0, // 14090: check Inst[20:16] == 0x0
6815 OPC_Decode, 244, 21, 226, 1, // 14094: decode to XVCVSPUXDS using decoder 226
6816 // 14094: }
6817 1, 0, // 14099: case 0x1: {
6818 OPC_CheckField, 16, 5, 0, // 14101: check Inst[20:16] == 0x0
6819 OPC_Decode, 242, 21, 226, 1, // 14105: decode to XVCVSPSXDS using decoder 226
6820 // 14105: }
6821 // 14105: } // switch Inst[6]
6822 // 14105: }
6823 1, 0, // 14110: case 0x1: {
6824 OPC_SwitchField, 6, 1, // 14112: switch Inst[6] {
6825 0, 9, // 14115: case 0x0: {
6826 OPC_CheckField, 16, 5, 0, // 14117: check Inst[20:16] == 0x0
6827 OPC_Decode, 233, 21, 226, 1, // 14121: decode to XVCVDPSP using decoder 226
6828 // 14121: }
6829 1, 0, // 14126: case 0x1: {
6830 OPC_CheckField, 16, 5, 0, // 14128: check Inst[20:16] == 0x0
6831 OPC_Decode, 203, 21, 226, 1, // 14132: decode to XVABSSP using decoder 226
6832 // 14132: }
6833 // 14132: } // switch Inst[6]
6834 // 14132: }
6835 // 14132: } // switch Inst[3:2]
6836 // 14132: }
6837 13, 69, // 14137: case 0xd: {
6838 OPC_SwitchField, 3, 1, // 14139: switch Inst[3] {
6839 0, 57, // 14142: case 0x0: {
6840 OPC_SwitchField, 2, 1, // 14144: switch Inst[2] {
6841 0, 25, // 14147: case 0x0: {
6842 OPC_SwitchField, 6, 1, // 14149: switch Inst[6] {
6843 0, 9, // 14152: case 0x0: {
6844 OPC_CheckField, 16, 5, 0, // 14154: check Inst[20:16] == 0x0
6845 OPC_Decode, 251, 21, 226, 1, // 14158: decode to XVCVUXDSP using decoder 226
6846 // 14158: }
6847 1, 0, // 14163: case 0x1: {
6848 OPC_CheckField, 16, 5, 0, // 14165: check Inst[20:16] == 0x0
6849 OPC_Decode, 247, 21, 226, 1, // 14169: decode to XVCVSXDSP using decoder 226
6850 // 14169: }
6851 // 14169: } // switch Inst[6]
6852 // 14169: }
6853 1, 0, // 14174: case 0x1: {
6854 OPC_SwitchField, 6, 1, // 14176: switch Inst[6] {
6855 0, 9, // 14179: case 0x0: {
6856 OPC_CheckField, 16, 5, 0, // 14181: check Inst[20:16] == 0x0
6857 OPC_Decode, 199, 22, 226, 1, // 14185: decode to XVNABSSP using decoder 226
6858 // 14185: }
6859 1, 0, // 14190: case 0x1: {
6860 OPC_CheckField, 16, 5, 0, // 14192: check Inst[20:16] == 0x0
6861 OPC_Decode, 201, 22, 226, 1, // 14196: decode to XVNEGSP using decoder 226
6862 // 14196: }
6863 // 14196: } // switch Inst[6]
6864 // 14196: }
6865 // 14196: } // switch Inst[2]
6866 // 14196: }
6867 1, 0, // 14201: case 0x1: {
6868 OPC_Decode, 237, 22, 235, 1, // 14203: decode to XVTSTDCSP using decoder 235
6869 // 14203: }
6870 // 14203: } // switch Inst[3]
6871 // 14203: }
6872 14, 220, 1, // 14208: case 0xe: {
6873 OPC_SwitchField, 2, 2, // 14211: switch Inst[3:2] {
6874 0, 25, // 14214: case 0x0: {
6875 OPC_SwitchField, 6, 1, // 14216: switch Inst[6] {
6876 0, 9, // 14219: case 0x0: {
6877 OPC_CheckField, 16, 5, 0, // 14221: check Inst[20:16] == 0x0
6878 OPC_Decode, 236, 21, 226, 1, // 14225: decode to XVCVDPUXDS using decoder 226
6879 // 14225: }
6880 1, 0, // 14230: case 0x1: {
6881 OPC_CheckField, 16, 5, 0, // 14232: check Inst[20:16] == 0x0
6882 OPC_Decode, 234, 21, 226, 1, // 14236: decode to XVCVDPSXDS using decoder 226
6883 // 14236: }
6884 // 14236: } // switch Inst[6]
6885 // 14236: }
6886 1, 25, // 14241: case 0x1: {
6887 OPC_SwitchField, 6, 1, // 14243: switch Inst[6] {
6888 0, 9, // 14246: case 0x0: {
6889 OPC_CheckField, 16, 5, 0, // 14248: check Inst[20:16] == 0x0
6890 OPC_Decode, 240, 21, 226, 1, // 14252: decode to XVCVSPDP using decoder 226
6891 // 14252: }
6892 1, 0, // 14257: case 0x1: {
6893 OPC_CheckField, 16, 5, 0, // 14259: check Inst[20:16] == 0x0
6894 OPC_Decode, 202, 21, 226, 1, // 14263: decode to XVABSDP using decoder 226
6895 // 14263: }
6896 // 14263: } // switch Inst[6]
6897 // 14263: }
6898 2, 41, // 14268: case 0x2: {
6899 OPC_SwitchField, 1, 1, // 14270: switch Inst[1] {
6900 0, 17, // 14273: case 0x0: {
6901 OPC_SwitchField, 6, 1, // 14275: switch Inst[6] {
6902 0, 5, // 14278: case 0x0: {
6903 OPC_Decode, 255, 22, 236, 1, // 14280: decode to XXGENPCVBM using decoder 236
6904 // 14280: }
6905 1, 0, // 14285: case 0x1: {
6906 OPC_Decode, 130, 23, 236, 1, // 14287: decode to XXGENPCVWM using decoder 236
6907 // 14287: }
6908 // 14287: } // switch Inst[6]
6909 // 14287: }
6910 1, 0, // 14292: case 0x1: {
6911 OPC_SwitchField, 6, 1, // 14294: switch Inst[6] {
6912 0, 5, // 14297: case 0x0: {
6913 OPC_Decode, 129, 23, 236, 1, // 14299: decode to XXGENPCVHM using decoder 236
6914 // 14299: }
6915 1, 0, // 14304: case 0x1: {
6916 OPC_Decode, 128, 23, 236, 1, // 14306: decode to XXGENPCVDM using decoder 236
6917 // 14306: }
6918 // 14306: } // switch Inst[6]
6919 // 14306: }
6920 // 14306: } // switch Inst[1]
6921 // 14306: }
6922 3, 0, // 14311: case 0x3: {
6923 OPC_SwitchField, 6, 1, // 14313: switch Inst[6] {
6924 0, 9, // 14316: case 0x0: {
6925 OPC_CheckField, 1, 1, 0, // 14318: check Inst[1] == 0x0
6926 OPC_Decode, 246, 20, 237, 1, // 14322: decode to XSIEXPDP using decoder 237
6927 // 14322: }
6928 1, 0, // 14327: case 0x1: {
6929 OPC_SwitchField, 16, 5, // 14329: switch Inst[20:16] {
6930 0, 5, // 14332: case 0x0: {
6931 OPC_Decode, 238, 22, 226, 1, // 14334: decode to XVXEXPDP using decoder 226
6932 // 14334: }
6933 1, 5, // 14339: case 0x1: {
6934 OPC_Decode, 240, 22, 226, 1, // 14341: decode to XVXSIGDP using decoder 226
6935 // 14341: }
6936 2, 13, // 14346: case 0x2: {
6937 OPC_CheckField, 21, 2, 0, // 14348: check Inst[22:21] == 0x0
6938 OPC_CheckField, 0, 1, 0, // 14352: check Inst[0] == 0x0
6939 OPC_Decode, 233, 22, 227, 1, // 14356: decode to XVTLSBB using decoder 227
6940 // 14356: }
6941 7, 5, // 14361: case 0x7: {
6942 OPC_Decode, 250, 22, 226, 1, // 14363: decode to XXBRH using decoder 226
6943 // 14363: }
6944 8, 5, // 14368: case 0x8: {
6945 OPC_Decode, 239, 22, 226, 1, // 14370: decode to XVXEXPSP using decoder 226
6946 // 14370: }
6947 9, 5, // 14375: case 0x9: {
6948 OPC_Decode, 241, 22, 226, 1, // 14377: decode to XVXSIGSP using decoder 226
6949 // 14377: }
6950 15, 5, // 14382: case 0xf: {
6951 OPC_Decode, 252, 22, 226, 1, // 14384: decode to XXBRW using decoder 226
6952 // 14384: }
6953 16, 5, // 14389: case 0x10: {
6954 OPC_Decode, 232, 21, 226, 1, // 14391: decode to XVCVBF16SPN using decoder 226
6955 // 14391: }
6956 17, 5, // 14396: case 0x11: {
6957 OPC_Decode, 239, 21, 226, 1, // 14398: decode to XVCVSPBF16 using decoder 226
6958 // 14398: }
6959 23, 5, // 14403: case 0x17: {
6960 OPC_Decode, 249, 22, 226, 1, // 14405: decode to XXBRD using decoder 226
6961 // 14405: }
6962 24, 5, // 14410: case 0x18: {
6963 OPC_Decode, 238, 21, 226, 1, // 14412: decode to XVCVHPSP using decoder 226
6964 // 14412: }
6965 25, 5, // 14417: case 0x19: {
6966 OPC_Decode, 241, 21, 226, 1, // 14419: decode to XVCVSPHP using decoder 226
6967 // 14419: }
6968 31, 0, // 14424: case 0x1f: {
6969 OPC_Decode, 251, 22, 226, 1, // 14426: decode to XXBRQ using decoder 226
6970 // 14426: }
6971 // 14426: } // switch Inst[20:16]
6972 // 14426: }
6973 // 14426: } // switch Inst[6]
6974 // 14426: }
6975 // 14426: } // switch Inst[3:2]
6976 // 14426: }
6977 15, 0, // 14431: case 0xf: {
6978 OPC_SwitchField, 3, 1, // 14433: switch Inst[3] {
6979 0, 57, // 14436: case 0x0: {
6980 OPC_SwitchField, 2, 1, // 14438: switch Inst[2] {
6981 0, 25, // 14441: case 0x0: {
6982 OPC_SwitchField, 6, 1, // 14443: switch Inst[6] {
6983 0, 9, // 14446: case 0x0: {
6984 OPC_CheckField, 16, 5, 0, // 14448: check Inst[20:16] == 0x0
6985 OPC_Decode, 250, 21, 226, 1, // 14452: decode to XVCVUXDDP using decoder 226
6986 // 14452: }
6987 1, 0, // 14457: case 0x1: {
6988 OPC_CheckField, 16, 5, 0, // 14459: check Inst[20:16] == 0x0
6989 OPC_Decode, 246, 21, 226, 1, // 14463: decode to XVCVSXDDP using decoder 226
6990 // 14463: }
6991 // 14463: } // switch Inst[6]
6992 // 14463: }
6993 1, 0, // 14468: case 0x1: {
6994 OPC_SwitchField, 6, 1, // 14470: switch Inst[6] {
6995 0, 9, // 14473: case 0x0: {
6996 OPC_CheckField, 16, 5, 0, // 14475: check Inst[20:16] == 0x0
6997 OPC_Decode, 198, 22, 226, 1, // 14479: decode to XVNABSDP using decoder 226
6998 // 14479: }
6999 1, 0, // 14484: case 0x1: {
7000 OPC_CheckField, 16, 5, 0, // 14486: check Inst[20:16] == 0x0
7001 OPC_Decode, 200, 22, 226, 1, // 14490: decode to XVNEGDP using decoder 226
7002 // 14490: }
7003 // 14490: } // switch Inst[6]
7004 // 14490: }
7005 // 14490: } // switch Inst[2]
7006 // 14490: }
7007 1, 0, // 14495: case 0x1: {
7008 OPC_Decode, 236, 22, 235, 1, // 14497: decode to XVTSTDCDP using decoder 235
7009 // 14497: }
7010 // 14497: } // switch Inst[3]
7011 // 14497: }
7012 // 14497: } // switch Inst[10:7]
7013 // 14497: }
7014 3, 0, // 14502: case 0x3: {
7015 OPC_Decode, 160, 23, 238, 1, // 14504: decode to XXSEL using decoder 238
7016 // 14504: }
7017 // 14504: } // switch Inst[5:4]
7018 // 14504: }
7019 61, 36, // 14509: case 0x3d: {
7020 OPC_SwitchField, 0, 2, // 14511: switch Inst[1:0] {
7021 1, 17, // 14514: case 0x1: {
7022 OPC_SwitchField, 2, 1, // 14516: switch Inst[2] {
7023 0, 5, // 14519: case 0x0: {
7024 OPC_Decode, 191, 11, 239, 1, // 14521: decode to LXV using decoder 239
7025 // 14521: }
7026 1, 0, // 14526: case 0x1: {
7027 OPC_Decode, 162, 16, 239, 1, // 14528: decode to STXV using decoder 239
7028 // 14528: }
7029 // 14528: } // switch Inst[2]
7030 // 14528: }
7031 2, 5, // 14533: case 0x2: {
7032 OPC_Decode, 153, 16, 169, 1, // 14535: decode to STXSD using decoder 169
7033 // 14535: }
7034 3, 0, // 14540: case 0x3: {
7035 OPC_Decode, 160, 16, 169, 1, // 14542: decode to STXSSP using decoder 169
7036 // 14542: }
7037 // 14542: } // switch Inst[1:0]
7038 // 14542: }
7039 62, 24, // 14547: case 0x3e: {
7040 OPC_SwitchField, 0, 2, // 14549: switch Inst[1:0] {
7041 0, 5, // 14552: case 0x0: {
7042 OPC_Decode, 215, 15, 170, 1, // 14554: decode to STD using decoder 170
7043 // 14554: }
7044 1, 5, // 14559: case 0x1: {
7045 OPC_Decode, 220, 15, 240, 1, // 14561: decode to STDU using decoder 240
7046 // 14561: }
7047 2, 0, // 14566: case 0x2: {
7048 OPC_Decode, 128, 16, 241, 1, // 14568: decode to STQ using decoder 241
7049 // 14568: }
7050 // 14568: } // switch Inst[1:0]
7051 // 14568: }
7052 63, 0, // 14573: case 0x3f: {
7053 OPC_SwitchField, 0, 6, // 14575: switch Inst[5:0] {
7054 0, 61, // 14578: case 0x0: {
7055 OPC_SwitchField, 6, 5, // 14580: switch Inst[10:6] {
7056 0, 9, // 14583: case 0x0: {
7057 OPC_CheckField, 21, 2, 0, // 14585: check Inst[22:21] == 0x0
7058 OPC_Decode, 186, 9, 242, 1, // 14589: decode to FCMPUS using decoder 242
7059 // 14589: }
7060 1, 9, // 14594: case 0x1: {
7061 OPC_CheckField, 21, 2, 0, // 14596: check Inst[22:21] == 0x0
7062 OPC_Decode, 184, 9, 242, 1, // 14600: decode to FCMPOS using decoder 242
7063 // 14600: }
7064 2, 12, // 14605: case 0x2: {
7065 OPC_CheckField, 21, 2, 0, // 14607: check Inst[22:21] == 0x0
7066 OPC_CheckField, 11, 7, 0, // 14611: check Inst[17:11] == 0x0
7067 OPC_Decode, 219, 11, 51, // 14615: decode to MCRFS using decoder 51
7068 // 14615: }
7069 4, 9, // 14619: case 0x4: {
7070 OPC_CheckField, 21, 2, 0, // 14621: check Inst[22:21] == 0x0
7071 OPC_Decode, 152, 10, 180, 1, // 14625: decode to FTDIV using decoder 180
7072 // 14625: }
7073 5, 0, // 14630: case 0x5: {
7074 OPC_CheckField, 16, 7, 0, // 14632: check Inst[22:16] == 0x0
7075 OPC_Decode, 153, 10, 243, 1, // 14636: decode to FTSQRT using decoder 243
7076 // 14636: }
7077 // 14636: } // switch Inst[10:6]
7078 // 14636: }
7079 4, 134, 2, // 14641: case 0x4: {
7080 OPC_SwitchField, 6, 4, // 14644: switch Inst[9:6] {
7081 0, 17, // 14647: case 0x0: {
7082 OPC_SwitchField, 10, 1, // 14649: switch Inst[10] {
7083 0, 5, // 14652: case 0x0: {
7084 OPC_Decode, 221, 5, 244, 1, // 14654: decode to DADDQ using decoder 244
7085 // 14654: }
7086 1, 0, // 14659: case 0x1: {
7087 OPC_Decode, 251, 6, 244, 1, // 14661: decode to DSUBQ using decoder 244
7088 // 14661: }
7089 // 14661: } // switch Inst[10]
7090 // 14661: }
7091 1, 17, // 14666: case 0x1: {
7092 OPC_SwitchField, 10, 1, // 14668: switch Inst[10] {
7093 0, 5, // 14671: case 0x0: {
7094 OPC_Decode, 183, 6, 244, 1, // 14673: decode to DMULQ using decoder 244
7095 // 14673: }
7096 1, 0, // 14678: case 0x1: {
7097 OPC_Decode, 135, 6, 244, 1, // 14680: decode to DDIVQ using decoder 244
7098 // 14680: }
7099 // 14680: } // switch Inst[10]
7100 // 14680: }
7101 2, 5, // 14685: case 0x2: {
7102 OPC_Decode, 233, 6, 245, 1, // 14687: decode to DSCLIQ using decoder 245
7103 // 14687: }
7104 3, 5, // 14692: case 0x3: {
7105 OPC_Decode, 237, 6, 245, 1, // 14694: decode to DSCRIQ using decoder 245
7106 // 14694: }
7107 4, 25, // 14699: case 0x4: {
7108 OPC_SwitchField, 10, 1, // 14701: switch Inst[10] {
7109 0, 9, // 14704: case 0x0: {
7110 OPC_CheckField, 21, 2, 0, // 14706: check Inst[22:21] == 0x0
7111 OPC_Decode, 246, 5, 246, 1, // 14710: decode to DCMPOQ using decoder 246
7112 // 14710: }
7113 1, 0, // 14715: case 0x1: {
7114 OPC_CheckField, 21, 2, 0, // 14717: check Inst[22:21] == 0x0
7115 OPC_Decode, 248, 5, 246, 1, // 14721: decode to DCMPUQ using decoder 246
7116 // 14721: }
7117 // 14721: } // switch Inst[10]
7118 // 14721: }
7119 5, 25, // 14726: case 0x5: {
7120 OPC_SwitchField, 10, 1, // 14728: switch Inst[10] {
7121 0, 9, // 14731: case 0x0: {
7122 OPC_CheckField, 21, 2, 0, // 14733: check Inst[22:21] == 0x0
7123 OPC_Decode, 131, 7, 246, 1, // 14737: decode to DTSTEXQ using decoder 246
7124 // 14737: }
7125 1, 0, // 14742: case 0x1: {
7126 OPC_CheckField, 21, 2, 0, // 14744: check Inst[22:21] == 0x0
7127 OPC_Decode, 135, 7, 247, 1, // 14748: decode to DTSTSFQ using decoder 247
7128 // 14748: }
7129 // 14748: } // switch Inst[10]
7130 // 14748: }
7131 6, 9, // 14753: case 0x6: {
7132 OPC_CheckField, 21, 2, 0, // 14755: check Inst[22:21] == 0x0
7133 OPC_Decode, 255, 6, 248, 1, // 14759: decode to DTSTDCQ using decoder 248
7134 // 14759: }
7135 7, 9, // 14764: case 0x7: {
7136 OPC_CheckField, 21, 2, 0, // 14766: check Inst[22:21] == 0x0
7137 OPC_Decode, 129, 7, 248, 1, // 14770: decode to DTSTDGQ using decoder 248
7138 // 14770: }
7139 8, 25, // 14775: case 0x8: {
7140 OPC_SwitchField, 10, 1, // 14777: switch Inst[10] {
7141 0, 9, // 14780: case 0x0: {
7142 OPC_CheckField, 16, 5, 0, // 14782: check Inst[20:16] == 0x0
7143 OPC_Decode, 128, 6, 249, 1, // 14786: decode to DCTQPQ using decoder 249
7144 // 14786: }
7145 1, 0, // 14791: case 0x1: {
7146 OPC_CheckField, 16, 5, 0, // 14793: check Inst[20:16] == 0x0
7147 OPC_Decode, 216, 6, 250, 1, // 14797: decode to DRDPQ using decoder 250
7148 // 14797: }
7149 // 14797: } // switch Inst[10]
7150 // 14797: }
7151 9, 25, // 14802: case 0x9: {
7152 OPC_SwitchField, 10, 1, // 14804: switch Inst[10] {
7153 0, 9, // 14807: case 0x0: {
7154 OPC_CheckField, 16, 5, 0, // 14809: check Inst[20:16] == 0x0
7155 OPC_Decode, 252, 5, 251, 1, // 14813: decode to DCTFIXQ using decoder 251
7156 // 14813: }
7157 1, 0, // 14818: case 0x1: {
7158 OPC_CheckField, 16, 5, 0, // 14820: check Inst[20:16] == 0x0
7159 OPC_Decode, 241, 5, 249, 1, // 14824: decode to DCFFIXQ using decoder 249
7160 // 14824: }
7161 // 14824: } // switch Inst[10]
7162 // 14824: }
7163 10, 25, // 14829: case 0xa: {
7164 OPC_SwitchField, 10, 1, // 14831: switch Inst[10] {
7165 0, 9, // 14834: case 0x0: {
7166 OPC_CheckField, 16, 3, 0, // 14836: check Inst[18:16] == 0x0
7167 OPC_Decode, 131, 6, 252, 1, // 14840: decode to DDEDPDQ using decoder 252
7168 // 14840: }
7169 1, 0, // 14845: case 0x1: {
7170 OPC_CheckField, 16, 4, 0, // 14847: check Inst[19:16] == 0x0
7171 OPC_Decode, 139, 6, 253, 1, // 14851: decode to DENBCDQ using decoder 253
7172 // 14851: }
7173 // 14851: } // switch Inst[10]
7174 // 14851: }
7175 11, 21, // 14856: case 0xb: {
7176 OPC_SwitchField, 10, 1, // 14858: switch Inst[10] {
7177 0, 9, // 14861: case 0x0: {
7178 OPC_CheckField, 16, 5, 0, // 14863: check Inst[20:16] == 0x0
7179 OPC_Decode, 137, 7, 251, 1, // 14867: decode to DXEXQ using decoder 251
7180 // 14867: }
7181 1, 0, // 14872: case 0x1: {
7182 OPC_Decode, 143, 6, 254, 1, // 14874: decode to DIEXQ using decoder 254
7183 // 14874: }
7184 // 14874: } // switch Inst[10]
7185 // 14874: }
7186 15, 0, // 14879: case 0xf: {
7187 OPC_SwitchField, 16, 5, // 14881: switch Inst[20:16] {
7188 0, 9, // 14884: case 0x0: {
7189 OPC_CheckField, 10, 1, 1, // 14886: check Inst[10] == 0x1
7190 OPC_Decode, 242, 5, 255, 1, // 14890: decode to DCFFIXQQ using decoder 255
7191 // 14890: }
7192 1, 0, // 14895: case 0x1: {
7193 OPC_CheckField, 10, 1, 1, // 14897: check Inst[10] == 0x1
7194 OPC_Decode, 253, 5, 128, 2, // 14901: decode to DCTFIXQQ using decoder 256
7195 // 14901: }
7196 // 14901: } // switch Inst[20:16]
7197 // 14901: }
7198 // 14901: } // switch Inst[9:6]
7199 // 14901: }
7200 5, 159, 1, // 14906: case 0x5: {
7201 OPC_SwitchField, 6, 4, // 14909: switch Inst[9:6] {
7202 0, 17, // 14912: case 0x0: {
7203 OPC_SwitchField, 10, 1, // 14914: switch Inst[10] {
7204 0, 5, // 14917: case 0x0: {
7205 OPC_Decode, 222, 5, 244, 1, // 14919: decode to DADDQ_rec using decoder 244
7206 // 14919: }
7207 1, 0, // 14924: case 0x1: {
7208 OPC_Decode, 252, 6, 244, 1, // 14926: decode to DSUBQ_rec using decoder 244
7209 // 14926: }
7210 // 14926: } // switch Inst[10]
7211 // 14926: }
7212 1, 17, // 14931: case 0x1: {
7213 OPC_SwitchField, 10, 1, // 14933: switch Inst[10] {
7214 0, 5, // 14936: case 0x0: {
7215 OPC_Decode, 184, 6, 244, 1, // 14938: decode to DMULQ_rec using decoder 244
7216 // 14938: }
7217 1, 0, // 14943: case 0x1: {
7218 OPC_Decode, 136, 6, 244, 1, // 14945: decode to DDIVQ_rec using decoder 244
7219 // 14945: }
7220 // 14945: } // switch Inst[10]
7221 // 14945: }
7222 2, 5, // 14950: case 0x2: {
7223 OPC_Decode, 234, 6, 245, 1, // 14952: decode to DSCLIQ_rec using decoder 245
7224 // 14952: }
7225 3, 5, // 14957: case 0x3: {
7226 OPC_Decode, 238, 6, 245, 1, // 14959: decode to DSCRIQ_rec using decoder 245
7227 // 14959: }
7228 8, 25, // 14964: case 0x8: {
7229 OPC_SwitchField, 10, 1, // 14966: switch Inst[10] {
7230 0, 9, // 14969: case 0x0: {
7231 OPC_CheckField, 16, 5, 0, // 14971: check Inst[20:16] == 0x0
7232 OPC_Decode, 129, 6, 249, 1, // 14975: decode to DCTQPQ_rec using decoder 249
7233 // 14975: }
7234 1, 0, // 14980: case 0x1: {
7235 OPC_CheckField, 16, 5, 0, // 14982: check Inst[20:16] == 0x0
7236 OPC_Decode, 217, 6, 250, 1, // 14986: decode to DRDPQ_rec using decoder 250
7237 // 14986: }
7238 // 14986: } // switch Inst[10]
7239 // 14986: }
7240 9, 25, // 14991: case 0x9: {
7241 OPC_SwitchField, 10, 1, // 14993: switch Inst[10] {
7242 0, 9, // 14996: case 0x0: {
7243 OPC_CheckField, 16, 5, 0, // 14998: check Inst[20:16] == 0x0
7244 OPC_Decode, 254, 5, 251, 1, // 15002: decode to DCTFIXQ_rec using decoder 251
7245 // 15002: }
7246 1, 0, // 15007: case 0x1: {
7247 OPC_CheckField, 16, 5, 0, // 15009: check Inst[20:16] == 0x0
7248 OPC_Decode, 243, 5, 249, 1, // 15013: decode to DCFFIXQ_rec using decoder 249
7249 // 15013: }
7250 // 15013: } // switch Inst[10]
7251 // 15013: }
7252 10, 25, // 15018: case 0xa: {
7253 OPC_SwitchField, 10, 1, // 15020: switch Inst[10] {
7254 0, 9, // 15023: case 0x0: {
7255 OPC_CheckField, 16, 3, 0, // 15025: check Inst[18:16] == 0x0
7256 OPC_Decode, 132, 6, 252, 1, // 15029: decode to DDEDPDQ_rec using decoder 252
7257 // 15029: }
7258 1, 0, // 15034: case 0x1: {
7259 OPC_CheckField, 16, 4, 0, // 15036: check Inst[19:16] == 0x0
7260 OPC_Decode, 140, 6, 253, 1, // 15040: decode to DENBCDQ_rec using decoder 253
7261 // 15040: }
7262 // 15040: } // switch Inst[10]
7263 // 15040: }
7264 11, 0, // 15045: case 0xb: {
7265 OPC_SwitchField, 10, 1, // 15047: switch Inst[10] {
7266 0, 9, // 15050: case 0x0: {
7267 OPC_CheckField, 16, 5, 0, // 15052: check Inst[20:16] == 0x0
7268 OPC_Decode, 138, 7, 251, 1, // 15056: decode to DXEXQ_rec using decoder 251
7269 // 15056: }
7270 1, 0, // 15061: case 0x1: {
7271 OPC_Decode, 144, 6, 254, 1, // 15063: decode to DIEXQ_rec using decoder 254
7272 // 15063: }
7273 // 15063: } // switch Inst[10]
7274 // 15063: }
7275 // 15063: } // switch Inst[9:6]
7276 // 15063: }
7277 6, 61, // 15068: case 0x6: {
7278 OPC_SwitchField, 6, 3, // 15070: switch Inst[8:6] {
7279 0, 5, // 15073: case 0x0: {
7280 OPC_Decode, 213, 6, 129, 2, // 15075: decode to DQUAQ using decoder 257
7281 // 15075: }
7282 1, 5, // 15080: case 0x1: {
7283 OPC_Decode, 227, 6, 130, 2, // 15082: decode to DRRNDQ using decoder 258
7284 // 15082: }
7285 2, 5, // 15087: case 0x2: {
7286 OPC_Decode, 210, 6, 131, 2, // 15089: decode to DQUAIQ using decoder 259
7287 // 15089: }
7288 3, 9, // 15094: case 0x3: {
7289 OPC_CheckField, 17, 4, 0, // 15096: check Inst[20:17] == 0x0
7290 OPC_Decode, 223, 6, 132, 2, // 15100: decode to DRINTXQ using decoder 260
7291 // 15100: }
7292 5, 13, // 15105: case 0x5: {
7293 OPC_CheckField, 22, 1, 0, // 15107: check Inst[22] == 0x0
7294 OPC_CheckField, 9, 2, 2, // 15111: check Inst[10:9] == 0x2
7295 OPC_Decode, 134, 7, 133, 2, // 15115: decode to DTSTSFIQ using decoder 261
7296 // 15115: }
7297 7, 0, // 15120: case 0x7: {
7298 OPC_CheckField, 17, 4, 0, // 15122: check Inst[20:17] == 0x0
7299 OPC_Decode, 219, 6, 132, 2, // 15126: decode to DRINTNQ using decoder 260
7300 // 15126: }
7301 // 15126: } // switch Inst[8:6]
7302 // 15126: }
7303 7, 46, // 15131: case 0x7: {
7304 OPC_SwitchField, 6, 3, // 15133: switch Inst[8:6] {
7305 0, 5, // 15136: case 0x0: {
7306 OPC_Decode, 214, 6, 129, 2, // 15138: decode to DQUAQ_rec using decoder 257
7307 // 15138: }
7308 1, 5, // 15143: case 0x1: {
7309 OPC_Decode, 228, 6, 130, 2, // 15145: decode to DRRNDQ_rec using decoder 258
7310 // 15145: }
7311 2, 5, // 15150: case 0x2: {
7312 OPC_Decode, 211, 6, 131, 2, // 15152: decode to DQUAIQ_rec using decoder 259
7313 // 15152: }
7314 3, 9, // 15157: case 0x3: {
7315 OPC_CheckField, 17, 4, 0, // 15159: check Inst[20:17] == 0x0
7316 OPC_Decode, 224, 6, 132, 2, // 15163: decode to DRINTXQ_rec using decoder 260
7317 // 15163: }
7318 7, 0, // 15168: case 0x7: {
7319 OPC_CheckField, 17, 4, 0, // 15170: check Inst[20:17] == 0x0
7320 OPC_Decode, 220, 6, 132, 2, // 15174: decode to DRINTNQ_rec using decoder 260
7321 // 15174: }
7322 // 15174: } // switch Inst[8:6]
7323 // 15174: }
7324 8, 129, 2, // 15179: case 0x8: {
7325 OPC_SwitchField, 6, 5, // 15182: switch Inst[10:6] {
7326 0, 4, // 15185: case 0x0: {
7327 OPC_Decode, 192, 20, 3, // 15187: decode to XSADDQP using decoder 3
7328 // 15187: }
7329 1, 4, // 15191: case 0x1: {
7330 OPC_Decode, 145, 21, 3, // 15193: decode to XSMULQP using decoder 3
7331 // 15193: }
7332 2, 4, // 15197: case 0x2: {
7333 OPC_Decode, 198, 20, 3, // 15199: decode to XSCMPEQQP using decoder 3
7334 // 15199: }
7335 3, 4, // 15203: case 0x3: {
7336 OPC_Decode, 210, 20, 3, // 15205: decode to XSCPSGNQP using decoder 3
7337 // 15205: }
7338 4, 8, // 15209: case 0x4: {
7339 OPC_CheckField, 21, 2, 0, // 15211: check Inst[22:21] == 0x0
7340 OPC_Decode, 206, 20, 6, // 15215: decode to XSCMPOQP using decoder 6
7341 // 15215: }
7342 5, 8, // 15219: case 0x5: {
7343 OPC_CheckField, 21, 2, 0, // 15221: check Inst[22:21] == 0x0
7344 OPC_Decode, 200, 20, 6, // 15225: decode to XSCMPEXPQP using decoder 6
7345 // 15225: }
7346 6, 4, // 15229: case 0x6: {
7347 OPC_Decode, 202, 20, 3, // 15231: decode to XSCMPGEQP using decoder 3
7348 // 15231: }
7349 7, 4, // 15235: case 0x7: {
7350 OPC_Decode, 204, 20, 3, // 15237: decode to XSCMPGTQP using decoder 3
7351 // 15237: }
7352 12, 5, // 15241: case 0xc: {
7353 OPC_Decode, 252, 20, 134, 2, // 15243: decode to XSMADDQP using decoder 262
7354 // 15243: }
7355 13, 5, // 15248: case 0xd: {
7356 OPC_Decode, 142, 21, 134, 2, // 15250: decode to XSMSUBQP using decoder 262
7357 // 15250: }
7358 14, 5, // 15255: case 0xe: {
7359 OPC_Decode, 157, 21, 134, 2, // 15257: decode to XSNMADDQP using decoder 262
7360 // 15257: }
7361 15, 5, // 15262: case 0xf: {
7362 OPC_Decode, 163, 21, 134, 2, // 15264: decode to XSNMSUBQP using decoder 262
7363 // 15264: }
7364 16, 4, // 15269: case 0x10: {
7365 OPC_Decode, 190, 21, 3, // 15271: decode to XSSUBQP using decoder 3
7366 // 15271: }
7367 17, 4, // 15275: case 0x11: {
7368 OPC_Decode, 243, 20, 3, // 15277: decode to XSDIVQP using decoder 3
7369 // 15277: }
7370 20, 8, // 15281: case 0x14: {
7371 OPC_CheckField, 21, 2, 0, // 15283: check Inst[22:21] == 0x0
7372 OPC_Decode, 208, 20, 6, // 15287: decode to XSCMPUQP using decoder 6
7373 // 15287: }
7374 21, 4, // 15291: case 0x15: {
7375 OPC_Decode, 255, 20, 3, // 15293: decode to XSMAXCQP using decoder 3
7376 // 15293: }
7377 22, 5, // 15297: case 0x16: {
7378 OPC_Decode, 196, 21, 135, 2, // 15299: decode to XSTSTDCQP using decoder 263
7379 // 15299: }
7380 23, 4, // 15304: case 0x17: {
7381 OPC_Decode, 135, 21, 3, // 15306: decode to XSMINCQP using decoder 3
7382 // 15306: }
7383 25, 39, // 15310: case 0x19: {
7384 OPC_SwitchField, 16, 5, // 15312: switch Inst[20:16] {
7385 0, 4, // 15315: case 0x0: {
7386 OPC_Decode, 188, 20, 7, // 15317: decode to XSABSQP using decoder 7
7387 // 15317: }
7388 2, 4, // 15321: case 0x2: {
7389 OPC_Decode, 199, 21, 7, // 15323: decode to XSXEXPQP using decoder 7
7390 // 15323: }
7391 8, 4, // 15327: case 0x8: {
7392 OPC_Decode, 150, 21, 7, // 15329: decode to XSNABSQP using decoder 7
7393 // 15329: }
7394 16, 4, // 15333: case 0x10: {
7395 OPC_Decode, 152, 21, 7, // 15335: decode to XSNEGQP using decoder 7
7396 // 15335: }
7397 18, 4, // 15339: case 0x12: {
7398 OPC_Decode, 201, 21, 7, // 15341: decode to XSXSIGQP using decoder 7
7399 // 15341: }
7400 27, 0, // 15345: case 0x1b: {
7401 OPC_Decode, 186, 21, 7, // 15347: decode to XSSQRTQP using decoder 7
7402 // 15347: }
7403 // 15347: } // switch Inst[20:16]
7404 // 15347: }
7405 26, 79, // 15351: case 0x1a: {
7406 OPC_SwitchField, 16, 5, // 15353: switch Inst[20:16] {
7407 0, 4, // 15356: case 0x0: {
7408 OPC_Decode, 230, 20, 7, // 15358: decode to XSCVQPUQZ using decoder 7
7409 // 15358: }
7410 1, 4, // 15362: case 0x1: {
7411 OPC_Decode, 231, 20, 7, // 15364: decode to XSCVQPUWZ using decoder 7
7412 // 15364: }
7413 2, 5, // 15368: case 0x2: {
7414 OPC_Decode, 238, 20, 136, 2, // 15370: decode to XSCVUDQP using decoder 264
7415 // 15370: }
7416 3, 4, // 15375: case 0x3: {
7417 OPC_Decode, 239, 20, 7, // 15377: decode to XSCVUQQP using decoder 7
7418 // 15377: }
7419 8, 4, // 15381: case 0x8: {
7420 OPC_Decode, 227, 20, 7, // 15383: decode to XSCVQPSQZ using decoder 7
7421 // 15383: }
7422 9, 4, // 15387: case 0x9: {
7423 OPC_Decode, 228, 20, 7, // 15389: decode to XSCVQPSWZ using decoder 7
7424 // 15389: }
7425 10, 5, // 15393: case 0xa: {
7426 OPC_Decode, 232, 20, 136, 2, // 15395: decode to XSCVSDQP using decoder 264
7427 // 15395: }
7428 11, 4, // 15400: case 0xb: {
7429 OPC_Decode, 235, 20, 7, // 15402: decode to XSCVSQQP using decoder 7
7430 // 15402: }
7431 17, 4, // 15406: case 0x11: {
7432 OPC_Decode, 229, 20, 7, // 15408: decode to XSCVQPUDZ using decoder 7
7433 // 15408: }
7434 20, 5, // 15412: case 0x14: {
7435 OPC_Decode, 224, 20, 137, 2, // 15414: decode to XSCVQPDP using decoder 265
7436 // 15414: }
7437 22, 5, // 15419: case 0x16: {
7438 OPC_Decode, 212, 20, 136, 2, // 15421: decode to XSCVDPQP using decoder 264
7439 // 15421: }
7440 25, 0, // 15426: case 0x19: {
7441 OPC_Decode, 226, 20, 7, // 15428: decode to XSCVQPSDZ using decoder 7
7442 // 15428: }
7443 // 15428: } // switch Inst[20:16]
7444 // 15428: }
7445 27, 0, // 15432: case 0x1b: {
7446 OPC_Decode, 247, 20, 138, 2, // 15434: decode to XSIEXPQP using decoder 266
7447 // 15434: }
7448 // 15434: } // switch Inst[10:6]
7449 // 15434: }
7450 9, 76, // 15439: case 0x9: {
7451 OPC_SwitchField, 6, 5, // 15441: switch Inst[10:6] {
7452 0, 4, // 15444: case 0x0: {
7453 OPC_Decode, 193, 20, 3, // 15446: decode to XSADDQPO using decoder 3
7454 // 15446: }
7455 1, 4, // 15450: case 0x1: {
7456 OPC_Decode, 146, 21, 3, // 15452: decode to XSMULQPO using decoder 3
7457 // 15452: }
7458 12, 5, // 15456: case 0xc: {
7459 OPC_Decode, 253, 20, 134, 2, // 15458: decode to XSMADDQPO using decoder 262
7460 // 15458: }
7461 13, 5, // 15463: case 0xd: {
7462 OPC_Decode, 143, 21, 134, 2, // 15465: decode to XSMSUBQPO using decoder 262
7463 // 15465: }
7464 14, 5, // 15470: case 0xe: {
7465 OPC_Decode, 158, 21, 134, 2, // 15472: decode to XSNMADDQPO using decoder 262
7466 // 15472: }
7467 15, 5, // 15477: case 0xf: {
7468 OPC_Decode, 164, 21, 134, 2, // 15479: decode to XSNMSUBQPO using decoder 262
7469 // 15479: }
7470 16, 4, // 15484: case 0x10: {
7471 OPC_Decode, 191, 21, 3, // 15486: decode to XSSUBQPO using decoder 3
7472 // 15486: }
7473 17, 4, // 15490: case 0x11: {
7474 OPC_Decode, 244, 20, 3, // 15492: decode to XSDIVQPO using decoder 3
7475 // 15492: }
7476 25, 8, // 15496: case 0x19: {
7477 OPC_CheckField, 16, 5, 27, // 15498: check Inst[20:16] == 0x1b
7478 OPC_Decode, 187, 21, 7, // 15502: decode to XSSQRTQPO using decoder 7
7479 // 15502: }
7480 26, 0, // 15506: case 0x1a: {
7481 OPC_CheckField, 16, 5, 20, // 15508: check Inst[20:16] == 0x14
7482 OPC_Decode, 225, 20, 137, 2, // 15512: decode to XSCVQPDPO using decoder 265
7483 // 15512: }
7484 // 15512: } // switch Inst[10:6]
7485 // 15512: }
7486 10, 25, // 15517: case 0xa: {
7487 OPC_SwitchField, 6, 3, // 15519: switch Inst[8:6] {
7488 0, 9, // 15522: case 0x0: {
7489 OPC_CheckField, 17, 4, 0, // 15524: check Inst[20:17] == 0x0
7490 OPC_Decode, 179, 21, 139, 2, // 15528: decode to XSRQPI using decoder 267
7491 // 15528: }
7492 1, 0, // 15533: case 0x1: {
7493 OPC_CheckField, 17, 4, 0, // 15535: check Inst[20:17] == 0x0
7494 OPC_Decode, 181, 21, 139, 2, // 15539: decode to XSRQPXP using decoder 267
7495 // 15539: }
7496 // 15539: } // switch Inst[8:6]
7497 // 15539: }
7498 11, 13, // 15544: case 0xb: {
7499 OPC_CheckField, 17, 4, 0, // 15546: check Inst[20:17] == 0x0
7500 OPC_CheckField, 6, 3, 0, // 15550: check Inst[8:6] == 0x0
7501 OPC_Decode, 180, 21, 139, 2, // 15554: decode to XSRQPIX using decoder 267
7502 // 15554: }
7503 12, 36, // 15559: case 0xc: {
7504 OPC_SwitchField, 6, 6, // 15561: switch Inst[11:6] {
7505 1, 9, // 15564: case 0x1: {
7506 OPC_CheckField, 12, 9, 0, // 15566: check Inst[20:12] == 0x0
7507 OPC_Decode, 144, 12, 149, 1, // 15570: decode to MTFSB1 using decoder 149
7508 // 15570: }
7509 2, 9, // 15575: case 0x2: {
7510 OPC_CheckField, 12, 9, 0, // 15577: check Inst[20:12] == 0x0
7511 OPC_Decode, 143, 12, 149, 1, // 15581: decode to MTFSB0 using decoder 149
7512 // 15581: }
7513 4, 0, // 15586: case 0x4: {
7514 OPC_CheckField, 17, 6, 0, // 15588: check Inst[22:17] == 0x0
7515 OPC_Decode, 146, 12, 140, 2, // 15592: decode to MTFSFI using decoder 268
7516 // 15592: }
7517 // 15592: } // switch Inst[11:6]
7518 // 15592: }
7519 13, 13, // 15597: case 0xd: {
7520 OPC_CheckField, 17, 6, 0, // 15599: check Inst[22:17] == 0x0
7521 OPC_CheckField, 6, 6, 4, // 15603: check Inst[11:6] == 0x4
7522 OPC_Decode, 147, 12, 141, 2, // 15607: decode to MTFSFI_rec using decoder 269
7523 // 15607: }
7524 14, 84, // 15612: case 0xe: {
7525 OPC_SwitchField, 6, 5, // 15614: switch Inst[10:6] {
7526 18, 72, // 15617: case 0x12: {
7527 OPC_SwitchField, 16, 5, // 15619: switch Inst[20:16] {
7528 0, 9, // 15622: case 0x0: {
7529 OPC_CheckField, 11, 5, 0, // 15624: check Inst[15:11] == 0x0
7530 OPC_Decode, 227, 11, 142, 2, // 15628: decode to MFFS using decoder 270
7531 // 15628: }
7532 1, 9, // 15633: case 0x1: {
7533 OPC_CheckField, 11, 5, 0, // 15635: check Inst[15:11] == 0x0
7534 OPC_Decode, 230, 11, 142, 2, // 15639: decode to MFFSCE using decoder 270
7535 // 15639: }
7536 20, 5, // 15644: case 0x14: {
7537 OPC_Decode, 228, 11, 173, 1, // 15646: decode to MFFSCDRN using decoder 173
7538 // 15646: }
7539 21, 9, // 15651: case 0x15: {
7540 OPC_CheckField, 14, 2, 0, // 15653: check Inst[15:14] == 0x0
7541 OPC_Decode, 229, 11, 143, 2, // 15657: decode to MFFSCDRNI using decoder 271
7542 // 15657: }
7543 22, 5, // 15662: case 0x16: {
7544 OPC_Decode, 231, 11, 173, 1, // 15664: decode to MFFSCRN using decoder 173
7545 // 15664: }
7546 23, 9, // 15669: case 0x17: {
7547 OPC_CheckField, 13, 3, 0, // 15671: check Inst[15:13] == 0x0
7548 OPC_Decode, 232, 11, 144, 2, // 15675: decode to MFFSCRNI using decoder 272
7549 // 15675: }
7550 24, 0, // 15680: case 0x18: {
7551 OPC_CheckField, 11, 5, 0, // 15682: check Inst[15:11] == 0x0
7552 OPC_Decode, 233, 11, 142, 2, // 15686: decode to MFFSL using decoder 270
7553 // 15686: }
7554 // 15686: } // switch Inst[20:16]
7555 // 15686: }
7556 22, 0, // 15691: case 0x16: {
7557 OPC_Decode, 145, 12, 145, 2, // 15693: decode to MTFSF using decoder 273
7558 // 15693: }
7559 // 15693: } // switch Inst[10:6]
7560 // 15693: }
7561 15, 21, // 15698: case 0xf: {
7562 OPC_SwitchField, 6, 5, // 15700: switch Inst[10:6] {
7563 18, 9, // 15703: case 0x12: {
7564 OPC_CheckField, 11, 10, 0, // 15705: check Inst[20:11] == 0x0
7565 OPC_Decode, 234, 11, 142, 2, // 15709: decode to MFFS_rec using decoder 270
7566 // 15709: }
7567 22, 0, // 15714: case 0x16: {
7568 OPC_Decode, 149, 12, 145, 2, // 15716: decode to MTFSF_rec using decoder 273
7569 // 15716: }
7570 // 15716: } // switch Inst[10:6]
7571 // 15716: }
7572 16, 98, // 15721: case 0x10: {
7573 OPC_SwitchField, 6, 5, // 15723: switch Inst[10:6] {
7574 0, 5, // 15726: case 0x0: {
7575 OPC_Decode, 189, 9, 195, 1, // 15728: decode to FCPSGNS using decoder 195
7576 // 15728: }
7577 1, 9, // 15733: case 0x1: {
7578 OPC_CheckField, 16, 5, 0, // 15735: check Inst[20:16] == 0x0
7579 OPC_Decode, 232, 9, 196, 1, // 15739: decode to FNEGS using decoder 196
7580 // 15739: }
7581 2, 9, // 15744: case 0x2: {
7582 OPC_CheckField, 16, 5, 0, // 15746: check Inst[20:16] == 0x0
7583 OPC_Decode, 216, 9, 196, 1, // 15750: decode to FMR using decoder 196
7584 // 15750: }
7585 4, 9, // 15755: case 0x4: {
7586 OPC_CheckField, 16, 5, 0, // 15757: check Inst[20:16] == 0x0
7587 OPC_Decode, 228, 9, 196, 1, // 15761: decode to FNABSS using decoder 196
7588 // 15761: }
7589 8, 9, // 15766: case 0x8: {
7590 OPC_CheckField, 16, 5, 0, // 15768: check Inst[20:16] == 0x0
7591 OPC_Decode, 168, 9, 196, 1, // 15772: decode to FABSS using decoder 196
7592 // 15772: }
7593 12, 9, // 15777: case 0xc: {
7594 OPC_CheckField, 16, 5, 0, // 15779: check Inst[20:16] == 0x0
7595 OPC_Decode, 252, 9, 196, 1, // 15783: decode to FRINS using decoder 196
7596 // 15783: }
7597 13, 9, // 15788: case 0xd: {
7598 OPC_CheckField, 16, 5, 0, // 15790: check Inst[20:16] == 0x0
7599 OPC_Decode, 132, 10, 196, 1, // 15794: decode to FRIZS using decoder 196
7600 // 15794: }
7601 14, 9, // 15799: case 0xe: {
7602 OPC_CheckField, 16, 5, 0, // 15801: check Inst[20:16] == 0x0
7603 OPC_Decode, 128, 10, 196, 1, // 15805: decode to FRIPS using decoder 196
7604 // 15805: }
7605 15, 0, // 15810: case 0xf: {
7606 OPC_CheckField, 16, 5, 0, // 15812: check Inst[20:16] == 0x0
7607 OPC_Decode, 248, 9, 196, 1, // 15816: decode to FRIMS using decoder 196
7608 // 15816: }
7609 // 15816: } // switch Inst[10:6]
7610 // 15816: }
7611 17, 98, // 15821: case 0x11: {
7612 OPC_SwitchField, 6, 5, // 15823: switch Inst[10:6] {
7613 0, 5, // 15826: case 0x0: {
7614 OPC_Decode, 190, 9, 195, 1, // 15828: decode to FCPSGNS_rec using decoder 195
7615 // 15828: }
7616 1, 9, // 15833: case 0x1: {
7617 OPC_CheckField, 16, 5, 0, // 15835: check Inst[20:16] == 0x0
7618 OPC_Decode, 233, 9, 196, 1, // 15839: decode to FNEGS_rec using decoder 196
7619 // 15839: }
7620 2, 9, // 15844: case 0x2: {
7621 OPC_CheckField, 16, 5, 0, // 15846: check Inst[20:16] == 0x0
7622 OPC_Decode, 217, 9, 196, 1, // 15850: decode to FMR_rec using decoder 196
7623 // 15850: }
7624 4, 9, // 15855: case 0x4: {
7625 OPC_CheckField, 16, 5, 0, // 15857: check Inst[20:16] == 0x0
7626 OPC_Decode, 229, 9, 196, 1, // 15861: decode to FNABSS_rec using decoder 196
7627 // 15861: }
7628 8, 9, // 15866: case 0x8: {
7629 OPC_CheckField, 16, 5, 0, // 15868: check Inst[20:16] == 0x0
7630 OPC_Decode, 169, 9, 196, 1, // 15872: decode to FABSS_rec using decoder 196
7631 // 15872: }
7632 12, 9, // 15877: case 0xc: {
7633 OPC_CheckField, 16, 5, 0, // 15879: check Inst[20:16] == 0x0
7634 OPC_Decode, 253, 9, 196, 1, // 15883: decode to FRINS_rec using decoder 196
7635 // 15883: }
7636 13, 9, // 15888: case 0xd: {
7637 OPC_CheckField, 16, 5, 0, // 15890: check Inst[20:16] == 0x0
7638 OPC_Decode, 133, 10, 196, 1, // 15894: decode to FRIZS_rec using decoder 196
7639 // 15894: }
7640 14, 9, // 15899: case 0xe: {
7641 OPC_CheckField, 16, 5, 0, // 15901: check Inst[20:16] == 0x0
7642 OPC_Decode, 129, 10, 196, 1, // 15905: decode to FRIPS_rec using decoder 196
7643 // 15905: }
7644 15, 0, // 15910: case 0xf: {
7645 OPC_CheckField, 16, 5, 0, // 15912: check Inst[20:16] == 0x0
7646 OPC_Decode, 249, 9, 196, 1, // 15916: decode to FRIMS_rec using decoder 196
7647 // 15916: }
7648 // 15916: } // switch Inst[10:6]
7649 // 15916: }
7650 24, 13, // 15921: case 0x18: {
7651 OPC_CheckField, 16, 5, 0, // 15923: check Inst[20:16] == 0x0
7652 OPC_CheckField, 6, 5, 0, // 15927: check Inst[10:6] == 0x0
7653 OPC_Decode, 134, 10, 194, 1, // 15931: decode to FRSP using decoder 194
7654 // 15931: }
7655 25, 13, // 15936: case 0x19: {
7656 OPC_CheckField, 16, 5, 0, // 15938: check Inst[20:16] == 0x0
7657 OPC_CheckField, 6, 5, 0, // 15942: check Inst[10:6] == 0x0
7658 OPC_Decode, 135, 10, 194, 1, // 15946: decode to FRSP_rec using decoder 194
7659 // 15946: }
7660 28, 69, // 15951: case 0x1c: {
7661 OPC_SwitchField, 6, 5, // 15953: switch Inst[10:6] {
7662 0, 9, // 15956: case 0x0: {
7663 OPC_CheckField, 16, 5, 0, // 15958: check Inst[20:16] == 0x0
7664 OPC_Decode, 199, 9, 173, 1, // 15962: decode to FCTIW using decoder 173
7665 // 15962: }
7666 4, 9, // 15967: case 0x4: {
7667 OPC_CheckField, 16, 5, 0, // 15969: check Inst[20:16] == 0x0
7668 OPC_Decode, 200, 9, 173, 1, // 15973: decode to FCTIWU using decoder 173
7669 // 15973: }
7670 25, 9, // 15978: case 0x19: {
7671 OPC_CheckField, 16, 5, 0, // 15980: check Inst[20:16] == 0x0
7672 OPC_Decode, 191, 9, 173, 1, // 15984: decode to FCTID using decoder 173
7673 // 15984: }
7674 26, 9, // 15989: case 0x1a: {
7675 OPC_CheckField, 16, 5, 0, // 15991: check Inst[20:16] == 0x0
7676 OPC_Decode, 175, 9, 173, 1, // 15995: decode to FCFID using decoder 173
7677 // 15995: }
7678 29, 9, // 16000: case 0x1d: {
7679 OPC_CheckField, 16, 5, 0, // 16002: check Inst[20:16] == 0x0
7680 OPC_Decode, 192, 9, 173, 1, // 16006: decode to FCTIDU using decoder 173
7681 // 16006: }
7682 30, 0, // 16011: case 0x1e: {
7683 OPC_CheckField, 16, 5, 0, // 16013: check Inst[20:16] == 0x0
7684 OPC_Decode, 178, 9, 173, 1, // 16017: decode to FCFIDU using decoder 173
7685 // 16017: }
7686 // 16017: } // switch Inst[10:6]
7687 // 16017: }
7688 29, 69, // 16022: case 0x1d: {
7689 OPC_SwitchField, 6, 5, // 16024: switch Inst[10:6] {
7690 0, 9, // 16027: case 0x0: {
7691 OPC_CheckField, 16, 5, 0, // 16029: check Inst[20:16] == 0x0
7692 OPC_Decode, 206, 9, 173, 1, // 16033: decode to FCTIW_rec using decoder 173
7693 // 16033: }
7694 4, 9, // 16038: case 0x4: {
7695 OPC_CheckField, 16, 5, 0, // 16040: check Inst[20:16] == 0x0
7696 OPC_Decode, 203, 9, 173, 1, // 16044: decode to FCTIWU_rec using decoder 173
7697 // 16044: }
7698 25, 9, // 16049: case 0x19: {
7699 OPC_CheckField, 16, 5, 0, // 16051: check Inst[20:16] == 0x0
7700 OPC_Decode, 198, 9, 173, 1, // 16055: decode to FCTID_rec using decoder 173
7701 // 16055: }
7702 26, 9, // 16060: case 0x1a: {
7703 OPC_CheckField, 16, 5, 0, // 16062: check Inst[20:16] == 0x0
7704 OPC_Decode, 182, 9, 173, 1, // 16066: decode to FCFID_rec using decoder 173
7705 // 16066: }
7706 29, 9, // 16071: case 0x1d: {
7707 OPC_CheckField, 16, 5, 0, // 16073: check Inst[20:16] == 0x0
7708 OPC_Decode, 195, 9, 173, 1, // 16077: decode to FCTIDU_rec using decoder 173
7709 // 16077: }
7710 30, 0, // 16082: case 0x1e: {
7711 OPC_CheckField, 16, 5, 0, // 16084: check Inst[20:16] == 0x0
7712 OPC_Decode, 181, 9, 173, 1, // 16088: decode to FCFIDU_rec using decoder 173
7713 // 16088: }
7714 // 16088: } // switch Inst[10:6]
7715 // 16088: }
7716 30, 47, // 16093: case 0x1e: {
7717 OPC_SwitchField, 6, 5, // 16095: switch Inst[10:6] {
7718 0, 9, // 16098: case 0x0: {
7719 OPC_CheckField, 16, 5, 0, // 16100: check Inst[20:16] == 0x0
7720 OPC_Decode, 204, 9, 173, 1, // 16104: decode to FCTIWZ using decoder 173
7721 // 16104: }
7722 4, 9, // 16109: case 0x4: {
7723 OPC_CheckField, 16, 5, 0, // 16111: check Inst[20:16] == 0x0
7724 OPC_Decode, 201, 9, 173, 1, // 16115: decode to FCTIWUZ using decoder 173
7725 // 16115: }
7726 25, 9, // 16120: case 0x19: {
7727 OPC_CheckField, 16, 5, 0, // 16122: check Inst[20:16] == 0x0
7728 OPC_Decode, 196, 9, 173, 1, // 16126: decode to FCTIDZ using decoder 173
7729 // 16126: }
7730 29, 0, // 16131: case 0x1d: {
7731 OPC_CheckField, 16, 5, 0, // 16133: check Inst[20:16] == 0x0
7732 OPC_Decode, 193, 9, 173, 1, // 16137: decode to FCTIDUZ using decoder 173
7733 // 16137: }
7734 // 16137: } // switch Inst[10:6]
7735 // 16137: }
7736 31, 47, // 16142: case 0x1f: {
7737 OPC_SwitchField, 6, 5, // 16144: switch Inst[10:6] {
7738 0, 9, // 16147: case 0x0: {
7739 OPC_CheckField, 16, 5, 0, // 16149: check Inst[20:16] == 0x0
7740 OPC_Decode, 205, 9, 173, 1, // 16153: decode to FCTIWZ_rec using decoder 173
7741 // 16153: }
7742 4, 9, // 16158: case 0x4: {
7743 OPC_CheckField, 16, 5, 0, // 16160: check Inst[20:16] == 0x0
7744 OPC_Decode, 202, 9, 173, 1, // 16164: decode to FCTIWUZ_rec using decoder 173
7745 // 16164: }
7746 25, 9, // 16169: case 0x19: {
7747 OPC_CheckField, 16, 5, 0, // 16171: check Inst[20:16] == 0x0
7748 OPC_Decode, 197, 9, 173, 1, // 16175: decode to FCTIDZ_rec using decoder 173
7749 // 16175: }
7750 29, 0, // 16180: case 0x1d: {
7751 OPC_CheckField, 16, 5, 0, // 16182: check Inst[20:16] == 0x0
7752 OPC_Decode, 194, 9, 173, 1, // 16186: decode to FCTIDUZ_rec using decoder 173
7753 // 16186: }
7754 // 16186: } // switch Inst[10:6]
7755 // 16186: }
7756 36, 9, // 16191: case 0x24: {
7757 OPC_CheckField, 6, 5, 0, // 16193: check Inst[10:6] == 0x0
7758 OPC_Decode, 207, 9, 172, 1, // 16197: decode to FDIV using decoder 172
7759 // 16197: }
7760 37, 9, // 16202: case 0x25: {
7761 OPC_CheckField, 6, 5, 0, // 16204: check Inst[10:6] == 0x0
7762 OPC_Decode, 210, 9, 172, 1, // 16208: decode to FDIV_rec using decoder 172
7763 // 16208: }
7764 40, 9, // 16213: case 0x28: {
7765 OPC_CheckField, 6, 5, 0, // 16215: check Inst[10:6] == 0x0
7766 OPC_Decode, 148, 10, 172, 1, // 16219: decode to FSUB using decoder 172
7767 // 16219: }
7768 41, 9, // 16224: case 0x29: {
7769 OPC_CheckField, 6, 5, 0, // 16226: check Inst[10:6] == 0x0
7770 OPC_Decode, 151, 10, 172, 1, // 16230: decode to FSUB_rec using decoder 172
7771 // 16230: }
7772 42, 9, // 16235: case 0x2a: {
7773 OPC_CheckField, 6, 5, 0, // 16237: check Inst[10:6] == 0x0
7774 OPC_Decode, 170, 9, 172, 1, // 16241: decode to FADD using decoder 172
7775 // 16241: }
7776 43, 9, // 16246: case 0x2b: {
7777 OPC_CheckField, 6, 5, 0, // 16248: check Inst[10:6] == 0x0
7778 OPC_Decode, 173, 9, 172, 1, // 16252: decode to FADD_rec using decoder 172
7779 // 16252: }
7780 44, 13, // 16257: case 0x2c: {
7781 OPC_CheckField, 16, 5, 0, // 16259: check Inst[20:16] == 0x0
7782 OPC_CheckField, 6, 5, 0, // 16263: check Inst[10:6] == 0x0
7783 OPC_Decode, 144, 10, 173, 1, // 16267: decode to FSQRT using decoder 173
7784 // 16267: }
7785 45, 13, // 16272: case 0x2d: {
7786 OPC_CheckField, 16, 5, 0, // 16274: check Inst[20:16] == 0x0
7787 OPC_CheckField, 6, 5, 0, // 16278: check Inst[10:6] == 0x0
7788 OPC_Decode, 147, 10, 173, 1, // 16282: decode to FSQRT_rec using decoder 173
7789 // 16282: }
7790 46, 5, // 16287: case 0x2e: {
7791 OPC_Decode, 142, 10, 146, 2, // 16289: decode to FSELS using decoder 274
7792 // 16289: }
7793 47, 5, // 16294: case 0x2f: {
7794 OPC_Decode, 143, 10, 146, 2, // 16296: decode to FSELS_rec using decoder 274
7795 // 16296: }
7796 48, 13, // 16301: case 0x30: {
7797 OPC_CheckField, 16, 5, 0, // 16303: check Inst[20:16] == 0x0
7798 OPC_CheckField, 6, 5, 0, // 16307: check Inst[10:6] == 0x0
7799 OPC_Decode, 242, 9, 173, 1, // 16311: decode to FRE using decoder 173
7800 // 16311: }
7801 49, 13, // 16316: case 0x31: {
7802 OPC_CheckField, 16, 5, 0, // 16318: check Inst[20:16] == 0x0
7803 OPC_CheckField, 6, 5, 0, // 16322: check Inst[10:6] == 0x0
7804 OPC_Decode, 245, 9, 173, 1, // 16326: decode to FRE_rec using decoder 173
7805 // 16326: }
7806 50, 9, // 16331: case 0x32: {
7807 OPC_CheckField, 11, 5, 0, // 16333: check Inst[15:11] == 0x0
7808 OPC_Decode, 222, 9, 147, 2, // 16337: decode to FMUL using decoder 275
7809 // 16337: }
7810 51, 9, // 16342: case 0x33: {
7811 OPC_CheckField, 11, 5, 0, // 16344: check Inst[15:11] == 0x0
7812 OPC_Decode, 225, 9, 147, 2, // 16348: decode to FMUL_rec using decoder 275
7813 // 16348: }
7814 52, 13, // 16353: case 0x34: {
7815 OPC_CheckField, 16, 5, 0, // 16355: check Inst[20:16] == 0x0
7816 OPC_CheckField, 6, 5, 0, // 16359: check Inst[10:6] == 0x0
7817 OPC_Decode, 136, 10, 173, 1, // 16363: decode to FRSQRTE using decoder 173
7818 // 16363: }
7819 53, 13, // 16368: case 0x35: {
7820 OPC_CheckField, 16, 5, 0, // 16370: check Inst[20:16] == 0x0
7821 OPC_CheckField, 6, 5, 0, // 16374: check Inst[10:6] == 0x0
7822 OPC_Decode, 139, 10, 173, 1, // 16378: decode to FRSQRTE_rec using decoder 173
7823 // 16378: }
7824 56, 5, // 16383: case 0x38: {
7825 OPC_Decode, 218, 9, 148, 2, // 16385: decode to FMSUB using decoder 276
7826 // 16385: }
7827 57, 5, // 16390: case 0x39: {
7828 OPC_Decode, 221, 9, 148, 2, // 16392: decode to FMSUB_rec using decoder 276
7829 // 16392: }
7830 58, 5, // 16397: case 0x3a: {
7831 OPC_Decode, 212, 9, 148, 2, // 16399: decode to FMADD using decoder 276
7832 // 16399: }
7833 59, 5, // 16404: case 0x3b: {
7834 OPC_Decode, 215, 9, 148, 2, // 16406: decode to FMADD_rec using decoder 276
7835 // 16406: }
7836 60, 5, // 16411: case 0x3c: {
7837 OPC_Decode, 238, 9, 148, 2, // 16413: decode to FNMSUB using decoder 276
7838 // 16413: }
7839 61, 5, // 16418: case 0x3d: {
7840 OPC_Decode, 241, 9, 148, 2, // 16420: decode to FNMSUB_rec using decoder 276
7841 // 16420: }
7842 62, 5, // 16425: case 0x3e: {
7843 OPC_Decode, 234, 9, 148, 2, // 16427: decode to FNMADD using decoder 276
7844 // 16427: }
7845 63, 0, // 16432: case 0x3f: {
7846 OPC_Decode, 237, 9, 148, 2, // 16434: decode to FNMADD_rec using decoder 276
7847 // 16434: }
7848 // 16434: } // switch Inst[5:0]
7849 // 16434: }
7850 // 16434: } // switch Inst[31:26]
7851};
7852static const uint8_t DecoderTableSPE32[3347] = {
7853 OPC_SwitchField, 3, 8, // 0: switch Inst[10:3] {
7854 64, 47, // 3: case 0x40: {
7855 OPC_SwitchField, 0, 3, // 5: switch Inst[2:0] {
7856 0, 9, // 8: case 0x0: {
7857 OPC_CheckField, 26, 6, 4, // 10: check Inst[31:26] == 0x4
7858 OPC_Decode, 213, 7, 149, 2, // 14: decode to EVADDW using decoder 277
7859 // 14: }
7860 2, 9, // 19: case 0x2: {
7861 OPC_CheckField, 26, 6, 4, // 21: check Inst[31:26] == 0x4
7862 OPC_Decode, 208, 7, 150, 2, // 25: decode to EVADDIW using decoder 278
7863 // 25: }
7864 4, 9, // 30: case 0x4: {
7865 OPC_CheckField, 26, 6, 4, // 32: check Inst[31:26] == 0x4
7866 OPC_Decode, 143, 9, 149, 2, // 36: decode to EVSUBFW using decoder 277
7867 // 36: }
7868 6, 0, // 41: case 0x6: {
7869 OPC_CheckField, 26, 6, 4, // 43: check Inst[31:26] == 0x4
7870 OPC_Decode, 144, 9, 151, 2, // 47: decode to EVSUBIFW using decoder 279
7871 // 47: }
7872 // 47: } // switch Inst[2:0]
7873 // 47: }
7874 65, 118, // 52: case 0x41: {
7875 OPC_SwitchField, 0, 3, // 54: switch Inst[2:0] {
7876 0, 13, // 57: case 0x0: {
7877 OPC_CheckField, 26, 6, 4, // 59: check Inst[31:26] == 0x4
7878 OPC_CheckField, 11, 5, 0, // 63: check Inst[15:11] == 0x0
7879 OPC_Decode, 207, 7, 152, 2, // 67: decode to EVABS using decoder 280
7880 // 67: }
7881 1, 13, // 72: case 0x1: {
7882 OPC_CheckField, 26, 6, 4, // 74: check Inst[31:26] == 0x4
7883 OPC_CheckField, 11, 5, 0, // 78: check Inst[15:11] == 0x0
7884 OPC_Decode, 237, 8, 152, 2, // 82: decode to EVNEG using decoder 280
7885 // 82: }
7886 2, 13, // 87: case 0x2: {
7887 OPC_CheckField, 26, 6, 4, // 89: check Inst[31:26] == 0x4
7888 OPC_CheckField, 11, 5, 0, // 93: check Inst[15:11] == 0x0
7889 OPC_Decode, 226, 7, 152, 2, // 97: decode to EVEXTSB using decoder 280
7890 // 97: }
7891 3, 13, // 102: case 0x3: {
7892 OPC_CheckField, 26, 6, 4, // 104: check Inst[31:26] == 0x4
7893 OPC_CheckField, 11, 5, 0, // 108: check Inst[15:11] == 0x0
7894 OPC_Decode, 227, 7, 152, 2, // 112: decode to EVEXTSH using decoder 280
7895 // 112: }
7896 4, 13, // 117: case 0x4: {
7897 OPC_CheckField, 26, 6, 4, // 119: check Inst[31:26] == 0x4
7898 OPC_CheckField, 11, 5, 0, // 123: check Inst[15:11] == 0x0
7899 OPC_Decode, 243, 8, 152, 2, // 127: decode to EVRNDW using decoder 280
7900 // 127: }
7901 5, 13, // 132: case 0x5: {
7902 OPC_CheckField, 26, 6, 4, // 134: check Inst[31:26] == 0x4
7903 OPC_CheckField, 11, 5, 0, // 138: check Inst[15:11] == 0x0
7904 OPC_Decode, 222, 7, 152, 2, // 142: decode to EVCNTLZW using decoder 280
7905 // 142: }
7906 6, 13, // 147: case 0x6: {
7907 OPC_CheckField, 26, 6, 4, // 149: check Inst[31:26] == 0x4
7908 OPC_CheckField, 11, 5, 0, // 153: check Inst[15:11] == 0x0
7909 OPC_Decode, 221, 7, 152, 2, // 157: decode to EVCNTLSW using decoder 280
7910 // 157: }
7911 7, 0, // 162: case 0x7: {
7912 OPC_CheckField, 26, 6, 4, // 164: check Inst[31:26] == 0x4
7913 OPC_Decode, 165, 5, 81, // 168: decode to BRINC using decoder 81
7914 // 168: }
7915 // 168: } // switch Inst[2:0]
7916 // 168: }
7917 66, 47, // 172: case 0x42: {
7918 OPC_SwitchField, 0, 3, // 174: switch Inst[2:0] {
7919 1, 9, // 177: case 0x1: {
7920 OPC_CheckField, 26, 6, 4, // 179: check Inst[31:26] == 0x4
7921 OPC_Decode, 214, 7, 149, 2, // 183: decode to EVAND using decoder 277
7922 // 183: }
7923 2, 9, // 188: case 0x2: {
7924 OPC_CheckField, 26, 6, 4, // 190: check Inst[31:26] == 0x4
7925 OPC_Decode, 215, 7, 149, 2, // 194: decode to EVANDC using decoder 277
7926 // 194: }
7927 6, 9, // 199: case 0x6: {
7928 OPC_CheckField, 26, 6, 4, // 201: check Inst[31:26] == 0x4
7929 OPC_Decode, 145, 9, 149, 2, // 205: decode to EVXOR using decoder 277
7930 // 205: }
7931 7, 0, // 210: case 0x7: {
7932 OPC_CheckField, 26, 6, 4, // 212: check Inst[31:26] == 0x4
7933 OPC_Decode, 239, 8, 149, 2, // 216: decode to EVOR using decoder 277
7934 // 216: }
7935 // 216: } // switch Inst[2:0]
7936 // 216: }
7937 67, 47, // 221: case 0x43: {
7938 OPC_SwitchField, 0, 3, // 223: switch Inst[2:0] {
7939 0, 9, // 226: case 0x0: {
7940 OPC_CheckField, 26, 6, 4, // 228: check Inst[31:26] == 0x4
7941 OPC_Decode, 238, 8, 149, 2, // 232: decode to EVNOR using decoder 277
7942 // 232: }
7943 1, 9, // 237: case 0x1: {
7944 OPC_CheckField, 26, 6, 4, // 239: check Inst[31:26] == 0x4
7945 OPC_Decode, 225, 7, 149, 2, // 243: decode to EVEQV using decoder 277
7946 // 243: }
7947 3, 9, // 248: case 0x3: {
7948 OPC_CheckField, 26, 6, 4, // 250: check Inst[31:26] == 0x4
7949 OPC_Decode, 240, 8, 149, 2, // 254: decode to EVORC using decoder 277
7950 // 254: }
7951 6, 0, // 259: case 0x6: {
7952 OPC_CheckField, 26, 6, 4, // 261: check Inst[31:26] == 0x4
7953 OPC_Decode, 236, 8, 149, 2, // 265: decode to EVNAND using decoder 277
7954 // 265: }
7955 // 265: } // switch Inst[2:0]
7956 // 265: }
7957 68, 69, // 270: case 0x44: {
7958 OPC_SwitchField, 0, 3, // 272: switch Inst[2:0] {
7959 0, 9, // 275: case 0x0: {
7960 OPC_CheckField, 26, 6, 4, // 277: check Inst[31:26] == 0x4
7961 OPC_Decode, 252, 8, 149, 2, // 281: decode to EVSRWU using decoder 277
7962 // 281: }
7963 1, 9, // 286: case 0x1: {
7964 OPC_CheckField, 26, 6, 4, // 288: check Inst[31:26] == 0x4
7965 OPC_Decode, 251, 8, 149, 2, // 292: decode to EVSRWS using decoder 277
7966 // 292: }
7967 2, 9, // 297: case 0x2: {
7968 OPC_CheckField, 26, 6, 4, // 299: check Inst[31:26] == 0x4
7969 OPC_Decode, 250, 8, 150, 2, // 303: decode to EVSRWIU using decoder 278
7970 // 303: }
7971 3, 9, // 308: case 0x3: {
7972 OPC_CheckField, 26, 6, 4, // 310: check Inst[31:26] == 0x4
7973 OPC_Decode, 249, 8, 150, 2, // 314: decode to EVSRWIS using decoder 278
7974 // 314: }
7975 4, 9, // 319: case 0x4: {
7976 OPC_CheckField, 26, 6, 4, // 321: check Inst[31:26] == 0x4
7977 OPC_Decode, 245, 8, 149, 2, // 325: decode to EVSLW using decoder 277
7978 // 325: }
7979 6, 0, // 330: case 0x6: {
7980 OPC_CheckField, 26, 6, 4, // 332: check Inst[31:26] == 0x4
7981 OPC_Decode, 246, 8, 150, 2, // 336: decode to EVSLWI using decoder 278
7982 // 336: }
7983 // 336: } // switch Inst[2:0]
7984 // 336: }
7985 69, 99, // 341: case 0x45: {
7986 OPC_SwitchField, 0, 3, // 343: switch Inst[2:0] {
7987 0, 9, // 346: case 0x0: {
7988 OPC_CheckField, 26, 6, 4, // 348: check Inst[31:26] == 0x4
7989 OPC_Decode, 241, 8, 149, 2, // 352: decode to EVRLW using decoder 277
7990 // 352: }
7991 1, 13, // 357: case 0x1: {
7992 OPC_CheckField, 26, 6, 4, // 359: check Inst[31:26] == 0x4
7993 OPC_CheckField, 11, 5, 0, // 363: check Inst[15:11] == 0x0
7994 OPC_Decode, 248, 8, 153, 2, // 367: decode to EVSPLATI using decoder 281
7995 // 367: }
7996 2, 9, // 372: case 0x2: {
7997 OPC_CheckField, 26, 6, 4, // 374: check Inst[31:26] == 0x4
7998 OPC_Decode, 242, 8, 150, 2, // 378: decode to EVRLWI using decoder 278
7999 // 378: }
8000 3, 13, // 383: case 0x3: {
8001 OPC_CheckField, 26, 6, 4, // 385: check Inst[31:26] == 0x4
8002 OPC_CheckField, 11, 5, 0, // 389: check Inst[15:11] == 0x0
8003 OPC_Decode, 247, 8, 153, 2, // 393: decode to EVSPLATFI using decoder 281
8004 // 393: }
8005 4, 9, // 398: case 0x4: {
8006 OPC_CheckField, 26, 6, 4, // 400: check Inst[31:26] == 0x4
8007 OPC_Decode, 145, 8, 149, 2, // 404: decode to EVMERGEHI using decoder 277
8008 // 404: }
8009 5, 9, // 409: case 0x5: {
8010 OPC_CheckField, 26, 6, 4, // 411: check Inst[31:26] == 0x4
8011 OPC_Decode, 147, 8, 154, 2, // 415: decode to EVMERGELO using decoder 282
8012 // 415: }
8013 6, 9, // 420: case 0x6: {
8014 OPC_CheckField, 26, 6, 4, // 422: check Inst[31:26] == 0x4
8015 OPC_Decode, 146, 8, 149, 2, // 426: decode to EVMERGEHILO using decoder 277
8016 // 426: }
8017 7, 0, // 431: case 0x7: {
8018 OPC_CheckField, 26, 6, 4, // 433: check Inst[31:26] == 0x4
8019 OPC_Decode, 148, 8, 149, 2, // 437: decode to EVMERGELOHI using decoder 277
8020 // 437: }
8021 // 437: } // switch Inst[2:0]
8022 // 437: }
8023 70, 78, // 442: case 0x46: {
8024 OPC_SwitchField, 0, 3, // 444: switch Inst[2:0] {
8025 0, 13, // 447: case 0x0: {
8026 OPC_CheckField, 26, 6, 4, // 449: check Inst[31:26] == 0x4
8027 OPC_CheckField, 21, 2, 0, // 453: check Inst[22:21] == 0x0
8028 OPC_Decode, 218, 7, 155, 2, // 457: decode to EVCMPGTU using decoder 283
8029 // 457: }
8030 1, 13, // 462: case 0x1: {
8031 OPC_CheckField, 26, 6, 4, // 464: check Inst[31:26] == 0x4
8032 OPC_CheckField, 21, 2, 0, // 468: check Inst[22:21] == 0x0
8033 OPC_Decode, 217, 7, 155, 2, // 472: decode to EVCMPGTS using decoder 283
8034 // 472: }
8035 2, 13, // 477: case 0x2: {
8036 OPC_CheckField, 26, 6, 4, // 479: check Inst[31:26] == 0x4
8037 OPC_CheckField, 21, 2, 0, // 483: check Inst[22:21] == 0x0
8038 OPC_Decode, 220, 7, 155, 2, // 487: decode to EVCMPLTU using decoder 283
8039 // 487: }
8040 3, 13, // 492: case 0x3: {
8041 OPC_CheckField, 26, 6, 4, // 494: check Inst[31:26] == 0x4
8042 OPC_CheckField, 21, 2, 0, // 498: check Inst[22:21] == 0x0
8043 OPC_Decode, 219, 7, 155, 2, // 502: decode to EVCMPLTS using decoder 283
8044 // 502: }
8045 4, 0, // 507: case 0x4: {
8046 OPC_CheckField, 26, 6, 4, // 509: check Inst[31:26] == 0x4
8047 OPC_CheckField, 21, 2, 0, // 513: check Inst[22:21] == 0x0
8048 OPC_Decode, 216, 7, 155, 2, // 517: decode to EVCMPEQ using decoder 283
8049 // 517: }
8050 // 517: } // switch Inst[2:0]
8051 // 517: }
8052 79, 9, // 522: case 0x4f: {
8053 OPC_CheckField, 26, 6, 4, // 524: check Inst[31:26] == 0x4
8054 OPC_Decode, 244, 8, 156, 2, // 528: decode to EVSEL using decoder 284
8055 // 528: }
8056 80, 70, // 533: case 0x50: {
8057 OPC_SwitchField, 0, 3, // 535: switch Inst[2:0] {
8058 0, 9, // 538: case 0x0: {
8059 OPC_CheckField, 26, 6, 4, // 540: check Inst[31:26] == 0x4
8060 OPC_Decode, 229, 7, 149, 2, // 544: decode to EVFSADD using decoder 277
8061 // 544: }
8062 1, 9, // 549: case 0x1: {
8063 OPC_CheckField, 26, 6, 4, // 551: check Inst[31:26] == 0x4
8064 OPC_Decode, 247, 7, 149, 2, // 555: decode to EVFSSUB using decoder 277
8065 // 555: }
8066 4, 13, // 560: case 0x4: {
8067 OPC_CheckField, 26, 6, 4, // 562: check Inst[31:26] == 0x4
8068 OPC_CheckField, 11, 5, 0, // 566: check Inst[15:11] == 0x0
8069 OPC_Decode, 228, 7, 152, 2, // 570: decode to EVFSABS using decoder 280
8070 // 570: }
8071 5, 13, // 575: case 0x5: {
8072 OPC_CheckField, 26, 6, 4, // 577: check Inst[31:26] == 0x4
8073 OPC_CheckField, 11, 5, 0, // 581: check Inst[15:11] == 0x0
8074 OPC_Decode, 245, 7, 152, 2, // 585: decode to EVFSNABS using decoder 280
8075 // 585: }
8076 6, 0, // 590: case 0x6: {
8077 OPC_CheckField, 26, 6, 4, // 592: check Inst[31:26] == 0x4
8078 OPC_CheckField, 11, 5, 0, // 596: check Inst[15:11] == 0x0
8079 OPC_Decode, 246, 7, 152, 2, // 600: decode to EVFSNEG using decoder 280
8080 // 600: }
8081 // 600: } // switch Inst[2:0]
8082 // 600: }
8083 81, 85, // 605: case 0x51: {
8084 OPC_SwitchField, 0, 3, // 607: switch Inst[2:0] {
8085 0, 9, // 610: case 0x0: {
8086 OPC_CheckField, 26, 6, 4, // 612: check Inst[31:26] == 0x4
8087 OPC_Decode, 244, 7, 149, 2, // 616: decode to EVFSMUL using decoder 277
8088 // 616: }
8089 1, 9, // 621: case 0x1: {
8090 OPC_CheckField, 26, 6, 4, // 623: check Inst[31:26] == 0x4
8091 OPC_Decode, 243, 7, 149, 2, // 627: decode to EVFSDIV using decoder 277
8092 // 627: }
8093 2, 13, // 632: case 0x2: {
8094 OPC_CheckField, 26, 6, 4, // 634: check Inst[31:26] == 0x4
8095 OPC_CheckField, 16, 5, 0, // 638: check Inst[20:16] == 0x0
8096 OPC_Decode, 233, 7, 157, 2, // 642: decode to EVFSCFUI using decoder 285
8097 // 642: }
8098 4, 13, // 647: case 0x4: {
8099 OPC_CheckField, 26, 6, 4, // 649: check Inst[31:26] == 0x4
8100 OPC_CheckField, 21, 2, 0, // 653: check Inst[22:21] == 0x0
8101 OPC_Decode, 235, 7, 155, 2, // 657: decode to EVFSCMPGT using decoder 283
8102 // 657: }
8103 5, 13, // 662: case 0x5: {
8104 OPC_CheckField, 26, 6, 4, // 664: check Inst[31:26] == 0x4
8105 OPC_CheckField, 21, 2, 0, // 668: check Inst[22:21] == 0x0
8106 OPC_Decode, 236, 7, 155, 2, // 672: decode to EVFSCMPLT using decoder 283
8107 // 672: }
8108 6, 0, // 677: case 0x6: {
8109 OPC_CheckField, 26, 6, 4, // 679: check Inst[31:26] == 0x4
8110 OPC_CheckField, 21, 2, 0, // 683: check Inst[22:21] == 0x0
8111 OPC_Decode, 234, 7, 155, 2, // 687: decode to EVFSCMPEQ using decoder 283
8112 // 687: }
8113 // 687: } // switch Inst[2:0]
8114 // 687: }
8115 82, 108, // 692: case 0x52: {
8116 OPC_SwitchField, 0, 3, // 694: switch Inst[2:0] {
8117 1, 13, // 697: case 0x1: {
8118 OPC_CheckField, 26, 6, 4, // 699: check Inst[31:26] == 0x4
8119 OPC_CheckField, 16, 5, 0, // 703: check Inst[20:16] == 0x0
8120 OPC_Decode, 231, 7, 157, 2, // 707: decode to EVFSCFSI using decoder 285
8121 // 707: }
8122 2, 13, // 712: case 0x2: {
8123 OPC_CheckField, 26, 6, 4, // 714: check Inst[31:26] == 0x4
8124 OPC_CheckField, 16, 5, 0, // 718: check Inst[20:16] == 0x0
8125 OPC_Decode, 232, 7, 157, 2, // 722: decode to EVFSCFUF using decoder 285
8126 // 722: }
8127 3, 13, // 727: case 0x3: {
8128 OPC_CheckField, 26, 6, 4, // 729: check Inst[31:26] == 0x4
8129 OPC_CheckField, 16, 5, 0, // 733: check Inst[20:16] == 0x0
8130 OPC_Decode, 230, 7, 157, 2, // 737: decode to EVFSCFSF using decoder 285
8131 // 737: }
8132 4, 13, // 742: case 0x4: {
8133 OPC_CheckField, 26, 6, 4, // 744: check Inst[31:26] == 0x4
8134 OPC_CheckField, 16, 5, 0, // 748: check Inst[20:16] == 0x0
8135 OPC_Decode, 241, 7, 157, 2, // 752: decode to EVFSCTUI using decoder 285
8136 // 752: }
8137 5, 13, // 757: case 0x5: {
8138 OPC_CheckField, 26, 6, 4, // 759: check Inst[31:26] == 0x4
8139 OPC_CheckField, 16, 5, 0, // 763: check Inst[20:16] == 0x0
8140 OPC_Decode, 238, 7, 157, 2, // 767: decode to EVFSCTSI using decoder 285
8141 // 767: }
8142 6, 13, // 772: case 0x6: {
8143 OPC_CheckField, 26, 6, 4, // 774: check Inst[31:26] == 0x4
8144 OPC_CheckField, 16, 5, 0, // 778: check Inst[20:16] == 0x0
8145 OPC_Decode, 240, 7, 157, 2, // 782: decode to EVFSCTUF using decoder 285
8146 // 782: }
8147 7, 0, // 787: case 0x7: {
8148 OPC_CheckField, 26, 6, 4, // 789: check Inst[31:26] == 0x4
8149 OPC_CheckField, 16, 5, 0, // 793: check Inst[20:16] == 0x0
8150 OPC_Decode, 237, 7, 157, 2, // 797: decode to EVFSCTSF using decoder 285
8151 // 797: }
8152 // 797: } // switch Inst[2:0]
8153 // 797: }
8154 83, 78, // 802: case 0x53: {
8155 OPC_SwitchField, 0, 3, // 804: switch Inst[2:0] {
8156 0, 13, // 807: case 0x0: {
8157 OPC_CheckField, 26, 6, 4, // 809: check Inst[31:26] == 0x4
8158 OPC_CheckField, 16, 5, 0, // 813: check Inst[20:16] == 0x0
8159 OPC_Decode, 242, 7, 157, 2, // 817: decode to EVFSCTUIZ using decoder 285
8160 // 817: }
8161 2, 13, // 822: case 0x2: {
8162 OPC_CheckField, 26, 6, 4, // 824: check Inst[31:26] == 0x4
8163 OPC_CheckField, 16, 5, 0, // 828: check Inst[20:16] == 0x0
8164 OPC_Decode, 239, 7, 157, 2, // 832: decode to EVFSCTSIZ using decoder 285
8165 // 832: }
8166 4, 13, // 837: case 0x4: {
8167 OPC_CheckField, 26, 6, 4, // 839: check Inst[31:26] == 0x4
8168 OPC_CheckField, 21, 2, 0, // 843: check Inst[22:21] == 0x0
8169 OPC_Decode, 249, 7, 155, 2, // 847: decode to EVFSTSTGT using decoder 283
8170 // 847: }
8171 5, 13, // 852: case 0x5: {
8172 OPC_CheckField, 26, 6, 4, // 854: check Inst[31:26] == 0x4
8173 OPC_CheckField, 21, 2, 0, // 858: check Inst[22:21] == 0x0
8174 OPC_Decode, 250, 7, 155, 2, // 862: decode to EVFSTSTLT using decoder 283
8175 // 862: }
8176 6, 0, // 867: case 0x6: {
8177 OPC_CheckField, 26, 6, 4, // 869: check Inst[31:26] == 0x4
8178 OPC_CheckField, 21, 2, 0, // 873: check Inst[22:21] == 0x0
8179 OPC_Decode, 248, 7, 155, 2, // 877: decode to EVFSTSTEQ using decoder 283
8180 // 877: }
8181 // 877: } // switch Inst[2:0]
8182 // 877: }
8183 88, 65, // 882: case 0x58: {
8184 OPC_SwitchField, 0, 3, // 884: switch Inst[2:0] {
8185 0, 8, // 887: case 0x0: {
8186 OPC_CheckField, 26, 6, 4, // 889: check Inst[31:26] == 0x4
8187 OPC_Decode, 175, 7, 81, // 893: decode to EFSADD using decoder 81
8188 // 893: }
8189 1, 8, // 897: case 0x1: {
8190 OPC_CheckField, 26, 6, 4, // 899: check Inst[31:26] == 0x4
8191 OPC_Decode, 194, 7, 81, // 903: decode to EFSSUB using decoder 81
8192 // 903: }
8193 4, 12, // 907: case 0x4: {
8194 OPC_CheckField, 26, 6, 4, // 909: check Inst[31:26] == 0x4
8195 OPC_CheckField, 11, 5, 0, // 913: check Inst[15:11] == 0x0
8196 OPC_Decode, 174, 7, 84, // 917: decode to EFSABS using decoder 84
8197 // 917: }
8198 5, 12, // 921: case 0x5: {
8199 OPC_CheckField, 26, 6, 4, // 923: check Inst[31:26] == 0x4
8200 OPC_CheckField, 11, 5, 0, // 927: check Inst[15:11] == 0x0
8201 OPC_Decode, 192, 7, 84, // 931: decode to EFSNABS using decoder 84
8202 // 931: }
8203 6, 0, // 935: case 0x6: {
8204 OPC_CheckField, 26, 6, 4, // 937: check Inst[31:26] == 0x4
8205 OPC_CheckField, 11, 5, 0, // 941: check Inst[15:11] == 0x0
8206 OPC_Decode, 193, 7, 84, // 945: decode to EFSNEG using decoder 84
8207 // 945: }
8208 // 945: } // switch Inst[2:0]
8209 // 945: }
8210 89, 80, // 949: case 0x59: {
8211 OPC_SwitchField, 0, 3, // 951: switch Inst[2:0] {
8212 0, 8, // 954: case 0x0: {
8213 OPC_CheckField, 26, 6, 4, // 956: check Inst[31:26] == 0x4
8214 OPC_Decode, 191, 7, 81, // 960: decode to EFSMUL using decoder 81
8215 // 960: }
8216 1, 8, // 964: case 0x1: {
8217 OPC_CheckField, 26, 6, 4, // 966: check Inst[31:26] == 0x4
8218 OPC_Decode, 190, 7, 81, // 970: decode to EFSDIV using decoder 81
8219 // 970: }
8220 4, 12, // 974: case 0x4: {
8221 OPC_CheckField, 26, 6, 4, // 976: check Inst[31:26] == 0x4
8222 OPC_CheckField, 21, 2, 0, // 980: check Inst[22:21] == 0x0
8223 OPC_Decode, 182, 7, 63, // 984: decode to EFSCMPGT using decoder 63
8224 // 984: }
8225 5, 12, // 988: case 0x5: {
8226 OPC_CheckField, 26, 6, 4, // 990: check Inst[31:26] == 0x4
8227 OPC_CheckField, 21, 2, 0, // 994: check Inst[22:21] == 0x0
8228 OPC_Decode, 183, 7, 63, // 998: decode to EFSCMPLT using decoder 63
8229 // 998: }
8230 6, 12, // 1002: case 0x6: {
8231 OPC_CheckField, 26, 6, 4, // 1004: check Inst[31:26] == 0x4
8232 OPC_CheckField, 21, 2, 0, // 1008: check Inst[22:21] == 0x0
8233 OPC_Decode, 181, 7, 63, // 1012: decode to EFSCMPEQ using decoder 63
8234 // 1012: }
8235 7, 0, // 1016: case 0x7: {
8236 OPC_CheckField, 26, 6, 4, // 1018: check Inst[31:26] == 0x4
8237 OPC_CheckField, 16, 5, 0, // 1022: check Inst[20:16] == 0x0
8238 OPC_Decode, 176, 7, 158, 2, // 1026: decode to EFSCFD using decoder 286
8239 // 1026: }
8240 // 1026: } // switch Inst[2:0]
8241 // 1026: }
8242 90, 116, // 1031: case 0x5a: {
8243 OPC_SwitchField, 0, 3, // 1033: switch Inst[2:0] {
8244 0, 12, // 1036: case 0x0: {
8245 OPC_CheckField, 26, 6, 4, // 1038: check Inst[31:26] == 0x4
8246 OPC_CheckField, 16, 5, 0, // 1042: check Inst[20:16] == 0x0
8247 OPC_Decode, 180, 7, 119, // 1046: decode to EFSCFUI using decoder 119
8248 // 1046: }
8249 1, 12, // 1050: case 0x1: {
8250 OPC_CheckField, 26, 6, 4, // 1052: check Inst[31:26] == 0x4
8251 OPC_CheckField, 16, 5, 0, // 1056: check Inst[20:16] == 0x0
8252 OPC_Decode, 178, 7, 119, // 1060: decode to EFSCFSI using decoder 119
8253 // 1060: }
8254 2, 12, // 1064: case 0x2: {
8255 OPC_CheckField, 26, 6, 4, // 1066: check Inst[31:26] == 0x4
8256 OPC_CheckField, 16, 5, 0, // 1070: check Inst[20:16] == 0x0
8257 OPC_Decode, 179, 7, 119, // 1074: decode to EFSCFUF using decoder 119
8258 // 1074: }
8259 3, 12, // 1078: case 0x3: {
8260 OPC_CheckField, 26, 6, 4, // 1080: check Inst[31:26] == 0x4
8261 OPC_CheckField, 16, 5, 0, // 1084: check Inst[20:16] == 0x0
8262 OPC_Decode, 177, 7, 119, // 1088: decode to EFSCFSF using decoder 119
8263 // 1088: }
8264 4, 12, // 1092: case 0x4: {
8265 OPC_CheckField, 26, 6, 4, // 1094: check Inst[31:26] == 0x4
8266 OPC_CheckField, 16, 5, 0, // 1098: check Inst[20:16] == 0x0
8267 OPC_Decode, 188, 7, 119, // 1102: decode to EFSCTUI using decoder 119
8268 // 1102: }
8269 5, 12, // 1106: case 0x5: {
8270 OPC_CheckField, 26, 6, 4, // 1108: check Inst[31:26] == 0x4
8271 OPC_CheckField, 16, 5, 0, // 1112: check Inst[20:16] == 0x0
8272 OPC_Decode, 185, 7, 119, // 1116: decode to EFSCTSI using decoder 119
8273 // 1116: }
8274 6, 13, // 1120: case 0x6: {
8275 OPC_CheckField, 26, 6, 4, // 1122: check Inst[31:26] == 0x4
8276 OPC_CheckField, 16, 5, 0, // 1126: check Inst[20:16] == 0x0
8277 OPC_Decode, 187, 7, 159, 2, // 1130: decode to EFSCTUF using decoder 287
8278 // 1130: }
8279 7, 0, // 1135: case 0x7: {
8280 OPC_CheckField, 26, 6, 4, // 1137: check Inst[31:26] == 0x4
8281 OPC_CheckField, 16, 5, 0, // 1141: check Inst[20:16] == 0x0
8282 OPC_Decode, 184, 7, 119, // 1145: decode to EFSCTSF using decoder 119
8283 // 1145: }
8284 // 1145: } // switch Inst[2:0]
8285 // 1145: }
8286 91, 76, // 1149: case 0x5b: {
8287 OPC_SwitchField, 0, 3, // 1151: switch Inst[2:0] {
8288 0, 12, // 1154: case 0x0: {
8289 OPC_CheckField, 26, 6, 4, // 1156: check Inst[31:26] == 0x4
8290 OPC_CheckField, 16, 5, 0, // 1160: check Inst[20:16] == 0x0
8291 OPC_Decode, 189, 7, 119, // 1164: decode to EFSCTUIZ using decoder 119
8292 // 1164: }
8293 2, 12, // 1168: case 0x2: {
8294 OPC_CheckField, 26, 6, 4, // 1170: check Inst[31:26] == 0x4
8295 OPC_CheckField, 16, 5, 0, // 1174: check Inst[20:16] == 0x0
8296 OPC_Decode, 186, 7, 119, // 1178: decode to EFSCTSIZ using decoder 119
8297 // 1178: }
8298 4, 13, // 1182: case 0x4: {
8299 OPC_CheckField, 26, 6, 4, // 1184: check Inst[31:26] == 0x4
8300 OPC_CheckField, 21, 2, 0, // 1188: check Inst[22:21] == 0x0
8301 OPC_Decode, 196, 7, 155, 2, // 1192: decode to EFSTSTGT using decoder 283
8302 // 1192: }
8303 5, 13, // 1197: case 0x5: {
8304 OPC_CheckField, 26, 6, 4, // 1199: check Inst[31:26] == 0x4
8305 OPC_CheckField, 21, 2, 0, // 1203: check Inst[22:21] == 0x0
8306 OPC_Decode, 197, 7, 155, 2, // 1207: decode to EFSTSTLT using decoder 283
8307 // 1207: }
8308 6, 0, // 1212: case 0x6: {
8309 OPC_CheckField, 26, 6, 4, // 1214: check Inst[31:26] == 0x4
8310 OPC_CheckField, 21, 2, 0, // 1218: check Inst[22:21] == 0x0
8311 OPC_Decode, 195, 7, 155, 2, // 1222: decode to EFSTSTEQ using decoder 283
8312 // 1222: }
8313 // 1222: } // switch Inst[2:0]
8314 // 1222: }
8315 92, 100, // 1227: case 0x5c: {
8316 OPC_SwitchField, 0, 3, // 1229: switch Inst[2:0] {
8317 0, 9, // 1232: case 0x0: {
8318 OPC_CheckField, 26, 6, 4, // 1234: check Inst[31:26] == 0x4
8319 OPC_Decode, 147, 7, 149, 2, // 1238: decode to EFDADD using decoder 277
8320 // 1238: }
8321 1, 9, // 1243: case 0x1: {
8322 OPC_CheckField, 26, 6, 4, // 1245: check Inst[31:26] == 0x4
8323 OPC_Decode, 170, 7, 149, 2, // 1249: decode to EFDSUB using decoder 277
8324 // 1249: }
8325 2, 13, // 1254: case 0x2: {
8326 OPC_CheckField, 26, 6, 4, // 1256: check Inst[31:26] == 0x4
8327 OPC_CheckField, 16, 5, 0, // 1260: check Inst[20:16] == 0x0
8328 OPC_Decode, 154, 7, 159, 2, // 1264: decode to EFDCFUID using decoder 287
8329 // 1264: }
8330 3, 13, // 1269: case 0x3: {
8331 OPC_CheckField, 26, 6, 4, // 1271: check Inst[31:26] == 0x4
8332 OPC_CheckField, 16, 5, 0, // 1275: check Inst[20:16] == 0x0
8333 OPC_Decode, 151, 7, 159, 2, // 1279: decode to EFDCFSID using decoder 287
8334 // 1279: }
8335 4, 13, // 1284: case 0x4: {
8336 OPC_CheckField, 26, 6, 4, // 1286: check Inst[31:26] == 0x4
8337 OPC_CheckField, 11, 5, 0, // 1290: check Inst[15:11] == 0x0
8338 OPC_Decode, 146, 7, 152, 2, // 1294: decode to EFDABS using decoder 280
8339 // 1294: }
8340 5, 13, // 1299: case 0x5: {
8341 OPC_CheckField, 26, 6, 4, // 1301: check Inst[31:26] == 0x4
8342 OPC_CheckField, 11, 5, 0, // 1305: check Inst[15:11] == 0x0
8343 OPC_Decode, 168, 7, 152, 2, // 1309: decode to EFDNABS using decoder 280
8344 // 1309: }
8345 6, 0, // 1314: case 0x6: {
8346 OPC_CheckField, 26, 6, 4, // 1316: check Inst[31:26] == 0x4
8347 OPC_CheckField, 11, 5, 0, // 1320: check Inst[15:11] == 0x0
8348 OPC_Decode, 169, 7, 152, 2, // 1324: decode to EFDNEG using decoder 280
8349 // 1324: }
8350 // 1324: } // switch Inst[2:0]
8351 // 1324: }
8352 93, 115, // 1329: case 0x5d: {
8353 OPC_SwitchField, 0, 3, // 1331: switch Inst[2:0] {
8354 0, 9, // 1334: case 0x0: {
8355 OPC_CheckField, 26, 6, 4, // 1336: check Inst[31:26] == 0x4
8356 OPC_Decode, 167, 7, 149, 2, // 1340: decode to EFDMUL using decoder 277
8357 // 1340: }
8358 1, 9, // 1345: case 0x1: {
8359 OPC_CheckField, 26, 6, 4, // 1347: check Inst[31:26] == 0x4
8360 OPC_Decode, 166, 7, 149, 2, // 1351: decode to EFDDIV using decoder 277
8361 // 1351: }
8362 2, 13, // 1356: case 0x2: {
8363 OPC_CheckField, 26, 6, 4, // 1358: check Inst[31:26] == 0x4
8364 OPC_CheckField, 16, 5, 0, // 1362: check Inst[20:16] == 0x0
8365 OPC_Decode, 164, 7, 158, 2, // 1366: decode to EFDCTUIDZ using decoder 286
8366 // 1366: }
8367 3, 13, // 1371: case 0x3: {
8368 OPC_CheckField, 26, 6, 4, // 1373: check Inst[31:26] == 0x4
8369 OPC_CheckField, 16, 5, 0, // 1377: check Inst[20:16] == 0x0
8370 OPC_Decode, 160, 7, 158, 2, // 1381: decode to EFDCTSIDZ using decoder 286
8371 // 1381: }
8372 4, 13, // 1386: case 0x4: {
8373 OPC_CheckField, 26, 6, 4, // 1388: check Inst[31:26] == 0x4
8374 OPC_CheckField, 21, 2, 0, // 1392: check Inst[22:21] == 0x0
8375 OPC_Decode, 156, 7, 155, 2, // 1396: decode to EFDCMPGT using decoder 283
8376 // 1396: }
8377 5, 13, // 1401: case 0x5: {
8378 OPC_CheckField, 26, 6, 4, // 1403: check Inst[31:26] == 0x4
8379 OPC_CheckField, 21, 2, 0, // 1407: check Inst[22:21] == 0x0
8380 OPC_Decode, 157, 7, 155, 2, // 1411: decode to EFDCMPLT using decoder 283
8381 // 1411: }
8382 6, 13, // 1416: case 0x6: {
8383 OPC_CheckField, 26, 6, 4, // 1418: check Inst[31:26] == 0x4
8384 OPC_CheckField, 21, 2, 0, // 1422: check Inst[22:21] == 0x0
8385 OPC_Decode, 155, 7, 155, 2, // 1426: decode to EFDCMPEQ using decoder 283
8386 // 1426: }
8387 7, 0, // 1431: case 0x7: {
8388 OPC_CheckField, 26, 6, 4, // 1433: check Inst[31:26] == 0x4
8389 OPC_CheckField, 16, 5, 0, // 1437: check Inst[20:16] == 0x0
8390 OPC_Decode, 148, 7, 159, 2, // 1441: decode to EFDCFS using decoder 287
8391 // 1441: }
8392 // 1441: } // switch Inst[2:0]
8393 // 1441: }
8394 94, 123, // 1446: case 0x5e: {
8395 OPC_SwitchField, 0, 3, // 1448: switch Inst[2:0] {
8396 0, 13, // 1451: case 0x0: {
8397 OPC_CheckField, 26, 6, 4, // 1453: check Inst[31:26] == 0x4
8398 OPC_CheckField, 16, 5, 0, // 1457: check Inst[20:16] == 0x0
8399 OPC_Decode, 153, 7, 159, 2, // 1461: decode to EFDCFUI using decoder 287
8400 // 1461: }
8401 1, 13, // 1466: case 0x1: {
8402 OPC_CheckField, 26, 6, 4, // 1468: check Inst[31:26] == 0x4
8403 OPC_CheckField, 16, 5, 0, // 1472: check Inst[20:16] == 0x0
8404 OPC_Decode, 150, 7, 159, 2, // 1476: decode to EFDCFSI using decoder 287
8405 // 1476: }
8406 2, 13, // 1481: case 0x2: {
8407 OPC_CheckField, 26, 6, 4, // 1483: check Inst[31:26] == 0x4
8408 OPC_CheckField, 16, 5, 0, // 1487: check Inst[20:16] == 0x0
8409 OPC_Decode, 152, 7, 159, 2, // 1491: decode to EFDCFUF using decoder 287
8410 // 1491: }
8411 3, 13, // 1496: case 0x3: {
8412 OPC_CheckField, 26, 6, 4, // 1498: check Inst[31:26] == 0x4
8413 OPC_CheckField, 16, 5, 0, // 1502: check Inst[20:16] == 0x0
8414 OPC_Decode, 149, 7, 159, 2, // 1506: decode to EFDCFSF using decoder 287
8415 // 1506: }
8416 4, 13, // 1511: case 0x4: {
8417 OPC_CheckField, 26, 6, 4, // 1513: check Inst[31:26] == 0x4
8418 OPC_CheckField, 16, 5, 0, // 1517: check Inst[20:16] == 0x0
8419 OPC_Decode, 163, 7, 158, 2, // 1521: decode to EFDCTUI using decoder 286
8420 // 1521: }
8421 5, 13, // 1526: case 0x5: {
8422 OPC_CheckField, 26, 6, 4, // 1528: check Inst[31:26] == 0x4
8423 OPC_CheckField, 16, 5, 0, // 1532: check Inst[20:16] == 0x0
8424 OPC_Decode, 159, 7, 158, 2, // 1536: decode to EFDCTSI using decoder 286
8425 // 1536: }
8426 6, 13, // 1541: case 0x6: {
8427 OPC_CheckField, 26, 6, 4, // 1543: check Inst[31:26] == 0x4
8428 OPC_CheckField, 16, 5, 0, // 1547: check Inst[20:16] == 0x0
8429 OPC_Decode, 162, 7, 159, 2, // 1551: decode to EFDCTUF using decoder 287
8430 // 1551: }
8431 7, 0, // 1556: case 0x7: {
8432 OPC_CheckField, 26, 6, 4, // 1558: check Inst[31:26] == 0x4
8433 OPC_CheckField, 16, 5, 0, // 1562: check Inst[20:16] == 0x0
8434 OPC_Decode, 158, 7, 159, 2, // 1566: decode to EFDCTSF using decoder 287
8435 // 1566: }
8436 // 1566: } // switch Inst[2:0]
8437 // 1566: }
8438 95, 78, // 1571: case 0x5f: {
8439 OPC_SwitchField, 0, 3, // 1573: switch Inst[2:0] {
8440 0, 13, // 1576: case 0x0: {
8441 OPC_CheckField, 26, 6, 4, // 1578: check Inst[31:26] == 0x4
8442 OPC_CheckField, 16, 5, 0, // 1582: check Inst[20:16] == 0x0
8443 OPC_Decode, 165, 7, 158, 2, // 1586: decode to EFDCTUIZ using decoder 286
8444 // 1586: }
8445 2, 13, // 1591: case 0x2: {
8446 OPC_CheckField, 26, 6, 4, // 1593: check Inst[31:26] == 0x4
8447 OPC_CheckField, 16, 5, 0, // 1597: check Inst[20:16] == 0x0
8448 OPC_Decode, 161, 7, 158, 2, // 1601: decode to EFDCTSIZ using decoder 286
8449 // 1601: }
8450 4, 13, // 1606: case 0x4: {
8451 OPC_CheckField, 26, 6, 4, // 1608: check Inst[31:26] == 0x4
8452 OPC_CheckField, 21, 2, 0, // 1612: check Inst[22:21] == 0x0
8453 OPC_Decode, 172, 7, 155, 2, // 1616: decode to EFDTSTGT using decoder 283
8454 // 1616: }
8455 5, 13, // 1621: case 0x5: {
8456 OPC_CheckField, 26, 6, 4, // 1623: check Inst[31:26] == 0x4
8457 OPC_CheckField, 21, 2, 0, // 1627: check Inst[22:21] == 0x0
8458 OPC_Decode, 173, 7, 155, 2, // 1631: decode to EFDTSTLT using decoder 283
8459 // 1631: }
8460 6, 0, // 1636: case 0x6: {
8461 OPC_CheckField, 26, 6, 4, // 1638: check Inst[31:26] == 0x4
8462 OPC_CheckField, 21, 2, 0, // 1642: check Inst[22:21] == 0x0
8463 OPC_Decode, 171, 7, 155, 2, // 1646: decode to EFDTSTEQ using decoder 283
8464 // 1646: }
8465 // 1646: } // switch Inst[2:0]
8466 // 1646: }
8467 96, 69, // 1651: case 0x60: {
8468 OPC_SwitchField, 0, 3, // 1653: switch Inst[2:0] {
8469 0, 9, // 1656: case 0x0: {
8470 OPC_CheckField, 26, 6, 4, // 1658: check Inst[31:26] == 0x4
8471 OPC_Decode, 252, 7, 160, 2, // 1662: decode to EVLDDX using decoder 288
8472 // 1662: }
8473 1, 9, // 1667: case 0x1: {
8474 OPC_CheckField, 26, 6, 4, // 1669: check Inst[31:26] == 0x4
8475 OPC_Decode, 251, 7, 161, 2, // 1673: decode to EVLDD using decoder 289
8476 // 1673: }
8477 2, 9, // 1678: case 0x2: {
8478 OPC_CheckField, 26, 6, 4, // 1680: check Inst[31:26] == 0x4
8479 OPC_Decode, 128, 8, 160, 2, // 1684: decode to EVLDWX using decoder 288
8480 // 1684: }
8481 3, 9, // 1689: case 0x3: {
8482 OPC_CheckField, 26, 6, 4, // 1691: check Inst[31:26] == 0x4
8483 OPC_Decode, 255, 7, 161, 2, // 1695: decode to EVLDW using decoder 289
8484 // 1695: }
8485 4, 9, // 1700: case 0x4: {
8486 OPC_CheckField, 26, 6, 4, // 1702: check Inst[31:26] == 0x4
8487 OPC_Decode, 254, 7, 160, 2, // 1706: decode to EVLDHX using decoder 288
8488 // 1706: }
8489 5, 0, // 1711: case 0x5: {
8490 OPC_CheckField, 26, 6, 4, // 1713: check Inst[31:26] == 0x4
8491 OPC_Decode, 253, 7, 161, 2, // 1717: decode to EVLDH using decoder 289
8492 // 1717: }
8493 // 1717: } // switch Inst[2:0]
8494 // 1717: }
8495 97, 69, // 1722: case 0x61: {
8496 OPC_SwitchField, 0, 3, // 1724: switch Inst[2:0] {
8497 0, 9, // 1727: case 0x0: {
8498 OPC_CheckField, 26, 6, 4, // 1729: check Inst[31:26] == 0x4
8499 OPC_Decode, 130, 8, 160, 2, // 1733: decode to EVLHHESPLATX using decoder 288
8500 // 1733: }
8501 1, 9, // 1738: case 0x1: {
8502 OPC_CheckField, 26, 6, 4, // 1740: check Inst[31:26] == 0x4
8503 OPC_Decode, 129, 8, 162, 2, // 1744: decode to EVLHHESPLAT using decoder 290
8504 // 1744: }
8505 4, 9, // 1749: case 0x4: {
8506 OPC_CheckField, 26, 6, 4, // 1751: check Inst[31:26] == 0x4
8507 OPC_Decode, 134, 8, 160, 2, // 1755: decode to EVLHHOUSPLATX using decoder 288
8508 // 1755: }
8509 5, 9, // 1760: case 0x5: {
8510 OPC_CheckField, 26, 6, 4, // 1762: check Inst[31:26] == 0x4
8511 OPC_Decode, 133, 8, 162, 2, // 1766: decode to EVLHHOUSPLAT using decoder 290
8512 // 1766: }
8513 6, 9, // 1771: case 0x6: {
8514 OPC_CheckField, 26, 6, 4, // 1773: check Inst[31:26] == 0x4
8515 OPC_Decode, 132, 8, 160, 2, // 1777: decode to EVLHHOSSPLATX using decoder 288
8516 // 1777: }
8517 7, 0, // 1782: case 0x7: {
8518 OPC_CheckField, 26, 6, 4, // 1784: check Inst[31:26] == 0x4
8519 OPC_Decode, 131, 8, 162, 2, // 1788: decode to EVLHHOSSPLAT using decoder 290
8520 // 1788: }
8521 // 1788: } // switch Inst[2:0]
8522 // 1788: }
8523 98, 69, // 1793: case 0x62: {
8524 OPC_SwitchField, 0, 3, // 1795: switch Inst[2:0] {
8525 0, 9, // 1798: case 0x0: {
8526 OPC_CheckField, 26, 6, 4, // 1800: check Inst[31:26] == 0x4
8527 OPC_Decode, 136, 8, 160, 2, // 1804: decode to EVLWHEX using decoder 288
8528 // 1804: }
8529 1, 9, // 1809: case 0x1: {
8530 OPC_CheckField, 26, 6, 4, // 1811: check Inst[31:26] == 0x4
8531 OPC_Decode, 135, 8, 163, 2, // 1815: decode to EVLWHE using decoder 291
8532 // 1815: }
8533 4, 9, // 1820: case 0x4: {
8534 OPC_CheckField, 26, 6, 4, // 1822: check Inst[31:26] == 0x4
8535 OPC_Decode, 140, 8, 160, 2, // 1826: decode to EVLWHOUX using decoder 288
8536 // 1826: }
8537 5, 9, // 1831: case 0x5: {
8538 OPC_CheckField, 26, 6, 4, // 1833: check Inst[31:26] == 0x4
8539 OPC_Decode, 139, 8, 163, 2, // 1837: decode to EVLWHOU using decoder 291
8540 // 1837: }
8541 6, 9, // 1842: case 0x6: {
8542 OPC_CheckField, 26, 6, 4, // 1844: check Inst[31:26] == 0x4
8543 OPC_Decode, 138, 8, 160, 2, // 1848: decode to EVLWHOSX using decoder 288
8544 // 1848: }
8545 7, 0, // 1853: case 0x7: {
8546 OPC_CheckField, 26, 6, 4, // 1855: check Inst[31:26] == 0x4
8547 OPC_Decode, 137, 8, 163, 2, // 1859: decode to EVLWHOS using decoder 291
8548 // 1859: }
8549 // 1859: } // switch Inst[2:0]
8550 // 1859: }
8551 99, 47, // 1864: case 0x63: {
8552 OPC_SwitchField, 0, 3, // 1866: switch Inst[2:0] {
8553 0, 9, // 1869: case 0x0: {
8554 OPC_CheckField, 26, 6, 4, // 1871: check Inst[31:26] == 0x4
8555 OPC_Decode, 144, 8, 160, 2, // 1875: decode to EVLWWSPLATX using decoder 288
8556 // 1875: }
8557 1, 9, // 1880: case 0x1: {
8558 OPC_CheckField, 26, 6, 4, // 1882: check Inst[31:26] == 0x4
8559 OPC_Decode, 143, 8, 163, 2, // 1886: decode to EVLWWSPLAT using decoder 291
8560 // 1886: }
8561 4, 9, // 1891: case 0x4: {
8562 OPC_CheckField, 26, 6, 4, // 1893: check Inst[31:26] == 0x4
8563 OPC_Decode, 142, 8, 160, 2, // 1897: decode to EVLWHSPLATX using decoder 288
8564 // 1897: }
8565 5, 0, // 1902: case 0x5: {
8566 OPC_CheckField, 26, 6, 4, // 1904: check Inst[31:26] == 0x4
8567 OPC_Decode, 141, 8, 163, 2, // 1908: decode to EVLWHSPLAT using decoder 291
8568 // 1908: }
8569 // 1908: } // switch Inst[2:0]
8570 // 1908: }
8571 100, 69, // 1913: case 0x64: {
8572 OPC_SwitchField, 0, 3, // 1915: switch Inst[2:0] {
8573 0, 9, // 1918: case 0x0: {
8574 OPC_CheckField, 26, 6, 4, // 1920: check Inst[31:26] == 0x4
8575 OPC_Decode, 254, 8, 160, 2, // 1924: decode to EVSTDDX using decoder 288
8576 // 1924: }
8577 1, 9, // 1929: case 0x1: {
8578 OPC_CheckField, 26, 6, 4, // 1931: check Inst[31:26] == 0x4
8579 OPC_Decode, 253, 8, 161, 2, // 1935: decode to EVSTDD using decoder 289
8580 // 1935: }
8581 2, 9, // 1940: case 0x2: {
8582 OPC_CheckField, 26, 6, 4, // 1942: check Inst[31:26] == 0x4
8583 OPC_Decode, 130, 9, 160, 2, // 1946: decode to EVSTDWX using decoder 288
8584 // 1946: }
8585 3, 9, // 1951: case 0x3: {
8586 OPC_CheckField, 26, 6, 4, // 1953: check Inst[31:26] == 0x4
8587 OPC_Decode, 129, 9, 161, 2, // 1957: decode to EVSTDW using decoder 289
8588 // 1957: }
8589 4, 9, // 1962: case 0x4: {
8590 OPC_CheckField, 26, 6, 4, // 1964: check Inst[31:26] == 0x4
8591 OPC_Decode, 128, 9, 160, 2, // 1968: decode to EVSTDHX using decoder 288
8592 // 1968: }
8593 5, 0, // 1973: case 0x5: {
8594 OPC_CheckField, 26, 6, 4, // 1975: check Inst[31:26] == 0x4
8595 OPC_Decode, 255, 8, 161, 2, // 1979: decode to EVSTDH using decoder 289
8596 // 1979: }
8597 // 1979: } // switch Inst[2:0]
8598 // 1979: }
8599 102, 47, // 1984: case 0x66: {
8600 OPC_SwitchField, 0, 3, // 1986: switch Inst[2:0] {
8601 0, 9, // 1989: case 0x0: {
8602 OPC_CheckField, 26, 6, 4, // 1991: check Inst[31:26] == 0x4
8603 OPC_Decode, 132, 9, 160, 2, // 1995: decode to EVSTWHEX using decoder 288
8604 // 1995: }
8605 1, 9, // 2000: case 0x1: {
8606 OPC_CheckField, 26, 6, 4, // 2002: check Inst[31:26] == 0x4
8607 OPC_Decode, 131, 9, 163, 2, // 2006: decode to EVSTWHE using decoder 291
8608 // 2006: }
8609 4, 9, // 2011: case 0x4: {
8610 OPC_CheckField, 26, 6, 4, // 2013: check Inst[31:26] == 0x4
8611 OPC_Decode, 134, 9, 160, 2, // 2017: decode to EVSTWHOX using decoder 288
8612 // 2017: }
8613 5, 0, // 2022: case 0x5: {
8614 OPC_CheckField, 26, 6, 4, // 2024: check Inst[31:26] == 0x4
8615 OPC_Decode, 133, 9, 163, 2, // 2028: decode to EVSTWHO using decoder 291
8616 // 2028: }
8617 // 2028: } // switch Inst[2:0]
8618 // 2028: }
8619 103, 47, // 2033: case 0x67: {
8620 OPC_SwitchField, 0, 3, // 2035: switch Inst[2:0] {
8621 0, 9, // 2038: case 0x0: {
8622 OPC_CheckField, 26, 6, 4, // 2040: check Inst[31:26] == 0x4
8623 OPC_Decode, 136, 9, 160, 2, // 2044: decode to EVSTWWEX using decoder 288
8624 // 2044: }
8625 1, 9, // 2049: case 0x1: {
8626 OPC_CheckField, 26, 6, 4, // 2051: check Inst[31:26] == 0x4
8627 OPC_Decode, 135, 9, 163, 2, // 2055: decode to EVSTWWE using decoder 291
8628 // 2055: }
8629 4, 9, // 2060: case 0x4: {
8630 OPC_CheckField, 26, 6, 4, // 2062: check Inst[31:26] == 0x4
8631 OPC_Decode, 138, 9, 160, 2, // 2066: decode to EVSTWWOX using decoder 288
8632 // 2066: }
8633 5, 0, // 2071: case 0x5: {
8634 OPC_CheckField, 26, 6, 4, // 2073: check Inst[31:26] == 0x4
8635 OPC_Decode, 137, 9, 163, 2, // 2077: decode to EVSTWWO using decoder 291
8636 // 2077: }
8637 // 2077: } // switch Inst[2:0]
8638 // 2077: }
8639 128, 1, 25, // 2082: case 0x80: {
8640 OPC_SwitchField, 0, 3, // 2085: switch Inst[2:0] {
8641 3, 9, // 2088: case 0x3: {
8642 OPC_CheckField, 26, 6, 4, // 2090: check Inst[31:26] == 0x4
8643 OPC_Decode, 163, 8, 149, 2, // 2094: decode to EVMHESSF using decoder 277
8644 // 2094: }
8645 7, 0, // 2099: case 0x7: {
8646 OPC_CheckField, 26, 6, 4, // 2101: check Inst[31:26] == 0x4
8647 OPC_Decode, 189, 8, 149, 2, // 2105: decode to EVMHOSSF using decoder 277
8648 // 2105: }
8649 // 2105: } // switch Inst[2:0]
8650 // 2105: }
8651 129, 1, 69, // 2110: case 0x81: {
8652 OPC_SwitchField, 0, 3, // 2113: switch Inst[2:0] {
8653 0, 9, // 2116: case 0x0: {
8654 OPC_CheckField, 26, 6, 4, // 2118: check Inst[31:26] == 0x4
8655 OPC_Decode, 169, 8, 149, 2, // 2122: decode to EVMHEUMI using decoder 277
8656 // 2122: }
8657 1, 9, // 2127: case 0x1: {
8658 OPC_CheckField, 26, 6, 4, // 2129: check Inst[31:26] == 0x4
8659 OPC_Decode, 159, 8, 149, 2, // 2133: decode to EVMHESMI using decoder 277
8660 // 2133: }
8661 3, 9, // 2138: case 0x3: {
8662 OPC_CheckField, 26, 6, 4, // 2140: check Inst[31:26] == 0x4
8663 OPC_Decode, 155, 8, 149, 2, // 2144: decode to EVMHESMF using decoder 277
8664 // 2144: }
8665 4, 9, // 2149: case 0x4: {
8666 OPC_CheckField, 26, 6, 4, // 2151: check Inst[31:26] == 0x4
8667 OPC_Decode, 195, 8, 149, 2, // 2155: decode to EVMHOUMI using decoder 277
8668 // 2155: }
8669 5, 9, // 2160: case 0x5: {
8670 OPC_CheckField, 26, 6, 4, // 2162: check Inst[31:26] == 0x4
8671 OPC_Decode, 185, 8, 149, 2, // 2166: decode to EVMHOSMI using decoder 277
8672 // 2166: }
8673 7, 0, // 2171: case 0x7: {
8674 OPC_CheckField, 26, 6, 4, // 2173: check Inst[31:26] == 0x4
8675 OPC_Decode, 181, 8, 149, 2, // 2177: decode to EVMHOSMF using decoder 277
8676 // 2177: }
8677 // 2177: } // switch Inst[2:0]
8678 // 2177: }
8679 132, 1, 25, // 2182: case 0x84: {
8680 OPC_SwitchField, 0, 3, // 2185: switch Inst[2:0] {
8681 3, 9, // 2188: case 0x3: {
8682 OPC_CheckField, 26, 6, 4, // 2190: check Inst[31:26] == 0x4
8683 OPC_Decode, 164, 8, 149, 2, // 2194: decode to EVMHESSFA using decoder 277
8684 // 2194: }
8685 7, 0, // 2199: case 0x7: {
8686 OPC_CheckField, 26, 6, 4, // 2201: check Inst[31:26] == 0x4
8687 OPC_Decode, 190, 8, 149, 2, // 2205: decode to EVMHOSSFA using decoder 277
8688 // 2205: }
8689 // 2205: } // switch Inst[2:0]
8690 // 2205: }
8691 133, 1, 69, // 2210: case 0x85: {
8692 OPC_SwitchField, 0, 3, // 2213: switch Inst[2:0] {
8693 0, 9, // 2216: case 0x0: {
8694 OPC_CheckField, 26, 6, 4, // 2218: check Inst[31:26] == 0x4
8695 OPC_Decode, 170, 8, 149, 2, // 2222: decode to EVMHEUMIA using decoder 277
8696 // 2222: }
8697 1, 9, // 2227: case 0x1: {
8698 OPC_CheckField, 26, 6, 4, // 2229: check Inst[31:26] == 0x4
8699 OPC_Decode, 160, 8, 149, 2, // 2233: decode to EVMHESMIA using decoder 277
8700 // 2233: }
8701 3, 9, // 2238: case 0x3: {
8702 OPC_CheckField, 26, 6, 4, // 2240: check Inst[31:26] == 0x4
8703 OPC_Decode, 156, 8, 149, 2, // 2244: decode to EVMHESMFA using decoder 277
8704 // 2244: }
8705 4, 9, // 2249: case 0x4: {
8706 OPC_CheckField, 26, 6, 4, // 2251: check Inst[31:26] == 0x4
8707 OPC_Decode, 196, 8, 149, 2, // 2255: decode to EVMHOUMIA using decoder 277
8708 // 2255: }
8709 5, 9, // 2260: case 0x5: {
8710 OPC_CheckField, 26, 6, 4, // 2262: check Inst[31:26] == 0x4
8711 OPC_Decode, 186, 8, 149, 2, // 2266: decode to EVMHOSMIA using decoder 277
8712 // 2266: }
8713 7, 0, // 2271: case 0x7: {
8714 OPC_CheckField, 26, 6, 4, // 2273: check Inst[31:26] == 0x4
8715 OPC_Decode, 182, 8, 149, 2, // 2277: decode to EVMHOSMFA using decoder 277
8716 // 2277: }
8717 // 2277: } // switch Inst[2:0]
8718 // 2277: }
8719 136, 1, 13, // 2282: case 0x88: {
8720 OPC_CheckField, 26, 6, 4, // 2285: check Inst[31:26] == 0x4
8721 OPC_CheckField, 0, 3, 7, // 2289: check Inst[2:0] == 0x7
8722 OPC_Decode, 206, 8, 149, 2, // 2293: decode to EVMWHSSF using decoder 277
8723 // 2293: }
8724 137, 1, 47, // 2298: case 0x89: {
8725 OPC_SwitchField, 0, 3, // 2301: switch Inst[2:0] {
8726 0, 9, // 2304: case 0x0: {
8727 OPC_CheckField, 26, 6, 4, // 2306: check Inst[31:26] == 0x4
8728 OPC_Decode, 214, 8, 149, 2, // 2310: decode to EVMWLUMI using decoder 277
8729 // 2310: }
8730 4, 9, // 2315: case 0x4: {
8731 OPC_CheckField, 26, 6, 4, // 2317: check Inst[31:26] == 0x4
8732 OPC_Decode, 208, 8, 149, 2, // 2321: decode to EVMWHUMI using decoder 277
8733 // 2321: }
8734 5, 9, // 2326: case 0x5: {
8735 OPC_CheckField, 26, 6, 4, // 2328: check Inst[31:26] == 0x4
8736 OPC_Decode, 204, 8, 149, 2, // 2332: decode to EVMWHSMI using decoder 277
8737 // 2332: }
8738 7, 0, // 2337: case 0x7: {
8739 OPC_CheckField, 26, 6, 4, // 2339: check Inst[31:26] == 0x4
8740 OPC_Decode, 202, 8, 149, 2, // 2343: decode to EVMWHSMF using decoder 277
8741 // 2343: }
8742 // 2343: } // switch Inst[2:0]
8743 // 2343: }
8744 138, 1, 13, // 2348: case 0x8a: {
8745 OPC_CheckField, 26, 6, 4, // 2351: check Inst[31:26] == 0x4
8746 OPC_CheckField, 0, 3, 3, // 2355: check Inst[2:0] == 0x3
8747 OPC_Decode, 228, 8, 149, 2, // 2359: decode to EVMWSSF using decoder 277
8748 // 2359: }
8749 139, 1, 36, // 2364: case 0x8b: {
8750 OPC_SwitchField, 0, 3, // 2367: switch Inst[2:0] {
8751 0, 9, // 2370: case 0x0: {
8752 OPC_CheckField, 26, 6, 4, // 2372: check Inst[31:26] == 0x4
8753 OPC_Decode, 232, 8, 149, 2, // 2376: decode to EVMWUMI using decoder 277
8754 // 2376: }
8755 1, 9, // 2381: case 0x1: {
8756 OPC_CheckField, 26, 6, 4, // 2383: check Inst[31:26] == 0x4
8757 OPC_Decode, 224, 8, 149, 2, // 2387: decode to EVMWSMI using decoder 277
8758 // 2387: }
8759 3, 0, // 2392: case 0x3: {
8760 OPC_CheckField, 26, 6, 4, // 2394: check Inst[31:26] == 0x4
8761 OPC_Decode, 220, 8, 149, 2, // 2398: decode to EVMWSMF using decoder 277
8762 // 2398: }
8763 // 2398: } // switch Inst[2:0]
8764 // 2398: }
8765 140, 1, 13, // 2403: case 0x8c: {
8766 OPC_CheckField, 26, 6, 4, // 2406: check Inst[31:26] == 0x4
8767 OPC_CheckField, 0, 3, 7, // 2410: check Inst[2:0] == 0x7
8768 OPC_Decode, 207, 8, 149, 2, // 2414: decode to EVMWHSSFA using decoder 277
8769 // 2414: }
8770 141, 1, 47, // 2419: case 0x8d: {
8771 OPC_SwitchField, 0, 3, // 2422: switch Inst[2:0] {
8772 0, 9, // 2425: case 0x0: {
8773 OPC_CheckField, 26, 6, 4, // 2427: check Inst[31:26] == 0x4
8774 OPC_Decode, 215, 8, 149, 2, // 2431: decode to EVMWLUMIA using decoder 277
8775 // 2431: }
8776 4, 9, // 2436: case 0x4: {
8777 OPC_CheckField, 26, 6, 4, // 2438: check Inst[31:26] == 0x4
8778 OPC_Decode, 209, 8, 149, 2, // 2442: decode to EVMWHUMIA using decoder 277
8779 // 2442: }
8780 5, 9, // 2447: case 0x5: {
8781 OPC_CheckField, 26, 6, 4, // 2449: check Inst[31:26] == 0x4
8782 OPC_Decode, 205, 8, 149, 2, // 2453: decode to EVMWHSMIA using decoder 277
8783 // 2453: }
8784 7, 0, // 2458: case 0x7: {
8785 OPC_CheckField, 26, 6, 4, // 2460: check Inst[31:26] == 0x4
8786 OPC_Decode, 203, 8, 149, 2, // 2464: decode to EVMWHSMFA using decoder 277
8787 // 2464: }
8788 // 2464: } // switch Inst[2:0]
8789 // 2464: }
8790 142, 1, 13, // 2469: case 0x8e: {
8791 OPC_CheckField, 26, 6, 4, // 2472: check Inst[31:26] == 0x4
8792 OPC_CheckField, 0, 3, 3, // 2476: check Inst[2:0] == 0x3
8793 OPC_Decode, 229, 8, 149, 2, // 2480: decode to EVMWSSFA using decoder 277
8794 // 2480: }
8795 143, 1, 36, // 2485: case 0x8f: {
8796 OPC_SwitchField, 0, 3, // 2488: switch Inst[2:0] {
8797 0, 9, // 2491: case 0x0: {
8798 OPC_CheckField, 26, 6, 4, // 2493: check Inst[31:26] == 0x4
8799 OPC_Decode, 233, 8, 149, 2, // 2497: decode to EVMWUMIA using decoder 277
8800 // 2497: }
8801 1, 9, // 2502: case 0x1: {
8802 OPC_CheckField, 26, 6, 4, // 2504: check Inst[31:26] == 0x4
8803 OPC_Decode, 225, 8, 149, 2, // 2508: decode to EVMWSMIA using decoder 277
8804 // 2508: }
8805 3, 0, // 2513: case 0x3: {
8806 OPC_CheckField, 26, 6, 4, // 2515: check Inst[31:26] == 0x4
8807 OPC_Decode, 221, 8, 149, 2, // 2519: decode to EVMWSMFA using decoder 277
8808 // 2519: }
8809 // 2519: } // switch Inst[2:0]
8810 // 2519: }
8811 152, 1, 100, // 2524: case 0x98: {
8812 OPC_SwitchField, 0, 3, // 2527: switch Inst[2:0] {
8813 0, 13, // 2530: case 0x0: {
8814 OPC_CheckField, 26, 6, 4, // 2532: check Inst[31:26] == 0x4
8815 OPC_CheckField, 11, 5, 0, // 2536: check Inst[15:11] == 0x0
8816 OPC_Decode, 212, 7, 152, 2, // 2540: decode to EVADDUSIAAW using decoder 280
8817 // 2540: }
8818 1, 13, // 2545: case 0x1: {
8819 OPC_CheckField, 26, 6, 4, // 2547: check Inst[31:26] == 0x4
8820 OPC_CheckField, 11, 5, 0, // 2551: check Inst[15:11] == 0x0
8821 OPC_Decode, 210, 7, 152, 2, // 2555: decode to EVADDSSIAAW using decoder 280
8822 // 2555: }
8823 2, 13, // 2560: case 0x2: {
8824 OPC_CheckField, 26, 6, 4, // 2562: check Inst[31:26] == 0x4
8825 OPC_CheckField, 11, 5, 0, // 2566: check Inst[15:11] == 0x0
8826 OPC_Decode, 142, 9, 152, 2, // 2570: decode to EVSUBFUSIAAW using decoder 280
8827 // 2570: }
8828 3, 13, // 2575: case 0x3: {
8829 OPC_CheckField, 26, 6, 4, // 2577: check Inst[31:26] == 0x4
8830 OPC_CheckField, 11, 5, 0, // 2581: check Inst[15:11] == 0x0
8831 OPC_Decode, 140, 9, 152, 2, // 2585: decode to EVSUBFSSIAAW using decoder 280
8832 // 2585: }
8833 4, 13, // 2590: case 0x4: {
8834 OPC_CheckField, 26, 6, 4, // 2592: check Inst[31:26] == 0x4
8835 OPC_CheckField, 11, 5, 0, // 2596: check Inst[15:11] == 0x0
8836 OPC_Decode, 201, 8, 152, 2, // 2600: decode to EVMRA using decoder 280
8837 // 2600: }
8838 6, 9, // 2605: case 0x6: {
8839 OPC_CheckField, 26, 6, 4, // 2607: check Inst[31:26] == 0x4
8840 OPC_Decode, 223, 7, 149, 2, // 2611: decode to EVDIVWS using decoder 277
8841 // 2611: }
8842 7, 0, // 2616: case 0x7: {
8843 OPC_CheckField, 26, 6, 4, // 2618: check Inst[31:26] == 0x4
8844 OPC_Decode, 224, 7, 149, 2, // 2622: decode to EVDIVWU using decoder 277
8845 // 2622: }
8846 // 2622: } // switch Inst[2:0]
8847 // 2622: }
8848 153, 1, 63, // 2627: case 0x99: {
8849 OPC_SwitchField, 0, 3, // 2630: switch Inst[2:0] {
8850 0, 13, // 2633: case 0x0: {
8851 OPC_CheckField, 26, 6, 4, // 2635: check Inst[31:26] == 0x4
8852 OPC_CheckField, 11, 5, 0, // 2639: check Inst[15:11] == 0x0
8853 OPC_Decode, 211, 7, 152, 2, // 2643: decode to EVADDUMIAAW using decoder 280
8854 // 2643: }
8855 1, 13, // 2648: case 0x1: {
8856 OPC_CheckField, 26, 6, 4, // 2650: check Inst[31:26] == 0x4
8857 OPC_CheckField, 11, 5, 0, // 2654: check Inst[15:11] == 0x0
8858 OPC_Decode, 209, 7, 152, 2, // 2658: decode to EVADDSMIAAW using decoder 280
8859 // 2658: }
8860 2, 13, // 2663: case 0x2: {
8861 OPC_CheckField, 26, 6, 4, // 2665: check Inst[31:26] == 0x4
8862 OPC_CheckField, 11, 5, 0, // 2669: check Inst[15:11] == 0x0
8863 OPC_Decode, 141, 9, 152, 2, // 2673: decode to EVSUBFUMIAAW using decoder 280
8864 // 2673: }
8865 3, 0, // 2678: case 0x3: {
8866 OPC_CheckField, 26, 6, 4, // 2680: check Inst[31:26] == 0x4
8867 OPC_CheckField, 11, 5, 0, // 2684: check Inst[15:11] == 0x0
8868 OPC_Decode, 139, 9, 152, 2, // 2688: decode to EVSUBFSMIAAW using decoder 280
8869 // 2688: }
8870 // 2688: } // switch Inst[2:0]
8871 // 2688: }
8872 160, 1, 69, // 2693: case 0xa0: {
8873 OPC_SwitchField, 0, 3, // 2696: switch Inst[2:0] {
8874 0, 9, // 2699: case 0x0: {
8875 OPC_CheckField, 26, 6, 4, // 2701: check Inst[31:26] == 0x4
8876 OPC_Decode, 173, 8, 149, 2, // 2705: decode to EVMHEUSIAAW using decoder 277
8877 // 2705: }
8878 1, 9, // 2710: case 0x1: {
8879 OPC_CheckField, 26, 6, 4, // 2712: check Inst[31:26] == 0x4
8880 OPC_Decode, 167, 8, 149, 2, // 2716: decode to EVMHESSIAAW using decoder 277
8881 // 2716: }
8882 3, 9, // 2721: case 0x3: {
8883 OPC_CheckField, 26, 6, 4, // 2723: check Inst[31:26] == 0x4
8884 OPC_Decode, 165, 8, 149, 2, // 2727: decode to EVMHESSFAAW using decoder 277
8885 // 2727: }
8886 4, 9, // 2732: case 0x4: {
8887 OPC_CheckField, 26, 6, 4, // 2734: check Inst[31:26] == 0x4
8888 OPC_Decode, 199, 8, 149, 2, // 2738: decode to EVMHOUSIAAW using decoder 277
8889 // 2738: }
8890 5, 9, // 2743: case 0x5: {
8891 OPC_CheckField, 26, 6, 4, // 2745: check Inst[31:26] == 0x4
8892 OPC_Decode, 193, 8, 149, 2, // 2749: decode to EVMHOSSIAAW using decoder 277
8893 // 2749: }
8894 7, 0, // 2754: case 0x7: {
8895 OPC_CheckField, 26, 6, 4, // 2756: check Inst[31:26] == 0x4
8896 OPC_Decode, 191, 8, 149, 2, // 2760: decode to EVMHOSSFAAW using decoder 277
8897 // 2760: }
8898 // 2760: } // switch Inst[2:0]
8899 // 2760: }
8900 161, 1, 69, // 2765: case 0xa1: {
8901 OPC_SwitchField, 0, 3, // 2768: switch Inst[2:0] {
8902 0, 9, // 2771: case 0x0: {
8903 OPC_CheckField, 26, 6, 4, // 2773: check Inst[31:26] == 0x4
8904 OPC_Decode, 171, 8, 149, 2, // 2777: decode to EVMHEUMIAAW using decoder 277
8905 // 2777: }
8906 1, 9, // 2782: case 0x1: {
8907 OPC_CheckField, 26, 6, 4, // 2784: check Inst[31:26] == 0x4
8908 OPC_Decode, 161, 8, 149, 2, // 2788: decode to EVMHESMIAAW using decoder 277
8909 // 2788: }
8910 3, 9, // 2793: case 0x3: {
8911 OPC_CheckField, 26, 6, 4, // 2795: check Inst[31:26] == 0x4
8912 OPC_Decode, 157, 8, 149, 2, // 2799: decode to EVMHESMFAAW using decoder 277
8913 // 2799: }
8914 4, 9, // 2804: case 0x4: {
8915 OPC_CheckField, 26, 6, 4, // 2806: check Inst[31:26] == 0x4
8916 OPC_Decode, 197, 8, 149, 2, // 2810: decode to EVMHOUMIAAW using decoder 277
8917 // 2810: }
8918 5, 9, // 2815: case 0x5: {
8919 OPC_CheckField, 26, 6, 4, // 2817: check Inst[31:26] == 0x4
8920 OPC_Decode, 187, 8, 149, 2, // 2821: decode to EVMHOSMIAAW using decoder 277
8921 // 2821: }
8922 7, 0, // 2826: case 0x7: {
8923 OPC_CheckField, 26, 6, 4, // 2828: check Inst[31:26] == 0x4
8924 OPC_Decode, 183, 8, 149, 2, // 2832: decode to EVMHOSMFAAW using decoder 277
8925 // 2832: }
8926 // 2832: } // switch Inst[2:0]
8927 // 2832: }
8928 165, 1, 69, // 2837: case 0xa5: {
8929 OPC_SwitchField, 0, 3, // 2840: switch Inst[2:0] {
8930 0, 9, // 2843: case 0x0: {
8931 OPC_CheckField, 26, 6, 4, // 2845: check Inst[31:26] == 0x4
8932 OPC_Decode, 153, 8, 149, 2, // 2849: decode to EVMHEGUMIAA using decoder 277
8933 // 2849: }
8934 1, 9, // 2854: case 0x1: {
8935 OPC_CheckField, 26, 6, 4, // 2856: check Inst[31:26] == 0x4
8936 OPC_Decode, 151, 8, 149, 2, // 2860: decode to EVMHEGSMIAA using decoder 277
8937 // 2860: }
8938 3, 9, // 2865: case 0x3: {
8939 OPC_CheckField, 26, 6, 4, // 2867: check Inst[31:26] == 0x4
8940 OPC_Decode, 149, 8, 149, 2, // 2871: decode to EVMHEGSMFAA using decoder 277
8941 // 2871: }
8942 4, 9, // 2876: case 0x4: {
8943 OPC_CheckField, 26, 6, 4, // 2878: check Inst[31:26] == 0x4
8944 OPC_Decode, 179, 8, 149, 2, // 2882: decode to EVMHOGUMIAA using decoder 277
8945 // 2882: }
8946 5, 9, // 2887: case 0x5: {
8947 OPC_CheckField, 26, 6, 4, // 2889: check Inst[31:26] == 0x4
8948 OPC_Decode, 177, 8, 149, 2, // 2893: decode to EVMHOGSMIAA using decoder 277
8949 // 2893: }
8950 7, 0, // 2898: case 0x7: {
8951 OPC_CheckField, 26, 6, 4, // 2900: check Inst[31:26] == 0x4
8952 OPC_Decode, 175, 8, 149, 2, // 2904: decode to EVMHOGSMFAA using decoder 277
8953 // 2904: }
8954 // 2904: } // switch Inst[2:0]
8955 // 2904: }
8956 168, 1, 25, // 2909: case 0xa8: {
8957 OPC_SwitchField, 0, 3, // 2912: switch Inst[2:0] {
8958 0, 9, // 2915: case 0x0: {
8959 OPC_CheckField, 26, 6, 4, // 2917: check Inst[31:26] == 0x4
8960 OPC_Decode, 218, 8, 149, 2, // 2921: decode to EVMWLUSIAAW using decoder 277
8961 // 2921: }
8962 1, 0, // 2926: case 0x1: {
8963 OPC_CheckField, 26, 6, 4, // 2928: check Inst[31:26] == 0x4
8964 OPC_Decode, 212, 8, 149, 2, // 2932: decode to EVMWLSSIAAW using decoder 277
8965 // 2932: }
8966 // 2932: } // switch Inst[2:0]
8967 // 2932: }
8968 169, 1, 25, // 2937: case 0xa9: {
8969 OPC_SwitchField, 0, 3, // 2940: switch Inst[2:0] {
8970 0, 9, // 2943: case 0x0: {
8971 OPC_CheckField, 26, 6, 4, // 2945: check Inst[31:26] == 0x4
8972 OPC_Decode, 216, 8, 149, 2, // 2949: decode to EVMWLUMIAAW using decoder 277
8973 // 2949: }
8974 1, 0, // 2954: case 0x1: {
8975 OPC_CheckField, 26, 6, 4, // 2956: check Inst[31:26] == 0x4
8976 OPC_Decode, 210, 8, 149, 2, // 2960: decode to EVMWLSMIAAW using decoder 277
8977 // 2960: }
8978 // 2960: } // switch Inst[2:0]
8979 // 2960: }
8980 170, 1, 13, // 2965: case 0xaa: {
8981 OPC_CheckField, 26, 6, 4, // 2968: check Inst[31:26] == 0x4
8982 OPC_CheckField, 0, 3, 3, // 2972: check Inst[2:0] == 0x3
8983 OPC_Decode, 230, 8, 149, 2, // 2976: decode to EVMWSSFAA using decoder 277
8984 // 2976: }
8985 171, 1, 36, // 2981: case 0xab: {
8986 OPC_SwitchField, 0, 3, // 2984: switch Inst[2:0] {
8987 0, 9, // 2987: case 0x0: {
8988 OPC_CheckField, 26, 6, 4, // 2989: check Inst[31:26] == 0x4
8989 OPC_Decode, 234, 8, 149, 2, // 2993: decode to EVMWUMIAA using decoder 277
8990 // 2993: }
8991 1, 9, // 2998: case 0x1: {
8992 OPC_CheckField, 26, 6, 4, // 3000: check Inst[31:26] == 0x4
8993 OPC_Decode, 226, 8, 149, 2, // 3004: decode to EVMWSMIAA using decoder 277
8994 // 3004: }
8995 3, 0, // 3009: case 0x3: {
8996 OPC_CheckField, 26, 6, 4, // 3011: check Inst[31:26] == 0x4
8997 OPC_Decode, 222, 8, 149, 2, // 3015: decode to EVMWSMFAA using decoder 277
8998 // 3015: }
8999 // 3015: } // switch Inst[2:0]
9000 // 3015: }
9001 176, 1, 69, // 3020: case 0xb0: {
9002 OPC_SwitchField, 0, 3, // 3023: switch Inst[2:0] {
9003 0, 9, // 3026: case 0x0: {
9004 OPC_CheckField, 26, 6, 4, // 3028: check Inst[31:26] == 0x4
9005 OPC_Decode, 174, 8, 149, 2, // 3032: decode to EVMHEUSIANW using decoder 277
9006 // 3032: }
9007 1, 9, // 3037: case 0x1: {
9008 OPC_CheckField, 26, 6, 4, // 3039: check Inst[31:26] == 0x4
9009 OPC_Decode, 168, 8, 149, 2, // 3043: decode to EVMHESSIANW using decoder 277
9010 // 3043: }
9011 3, 9, // 3048: case 0x3: {
9012 OPC_CheckField, 26, 6, 4, // 3050: check Inst[31:26] == 0x4
9013 OPC_Decode, 166, 8, 149, 2, // 3054: decode to EVMHESSFANW using decoder 277
9014 // 3054: }
9015 4, 9, // 3059: case 0x4: {
9016 OPC_CheckField, 26, 6, 4, // 3061: check Inst[31:26] == 0x4
9017 OPC_Decode, 200, 8, 149, 2, // 3065: decode to EVMHOUSIANW using decoder 277
9018 // 3065: }
9019 5, 9, // 3070: case 0x5: {
9020 OPC_CheckField, 26, 6, 4, // 3072: check Inst[31:26] == 0x4
9021 OPC_Decode, 194, 8, 149, 2, // 3076: decode to EVMHOSSIANW using decoder 277
9022 // 3076: }
9023 7, 0, // 3081: case 0x7: {
9024 OPC_CheckField, 26, 6, 4, // 3083: check Inst[31:26] == 0x4
9025 OPC_Decode, 192, 8, 149, 2, // 3087: decode to EVMHOSSFANW using decoder 277
9026 // 3087: }
9027 // 3087: } // switch Inst[2:0]
9028 // 3087: }
9029 177, 1, 69, // 3092: case 0xb1: {
9030 OPC_SwitchField, 0, 3, // 3095: switch Inst[2:0] {
9031 0, 9, // 3098: case 0x0: {
9032 OPC_CheckField, 26, 6, 4, // 3100: check Inst[31:26] == 0x4
9033 OPC_Decode, 172, 8, 149, 2, // 3104: decode to EVMHEUMIANW using decoder 277
9034 // 3104: }
9035 1, 9, // 3109: case 0x1: {
9036 OPC_CheckField, 26, 6, 4, // 3111: check Inst[31:26] == 0x4
9037 OPC_Decode, 162, 8, 149, 2, // 3115: decode to EVMHESMIANW using decoder 277
9038 // 3115: }
9039 3, 9, // 3120: case 0x3: {
9040 OPC_CheckField, 26, 6, 4, // 3122: check Inst[31:26] == 0x4
9041 OPC_Decode, 158, 8, 149, 2, // 3126: decode to EVMHESMFANW using decoder 277
9042 // 3126: }
9043 4, 9, // 3131: case 0x4: {
9044 OPC_CheckField, 26, 6, 4, // 3133: check Inst[31:26] == 0x4
9045 OPC_Decode, 198, 8, 149, 2, // 3137: decode to EVMHOUMIANW using decoder 277
9046 // 3137: }
9047 5, 9, // 3142: case 0x5: {
9048 OPC_CheckField, 26, 6, 4, // 3144: check Inst[31:26] == 0x4
9049 OPC_Decode, 188, 8, 149, 2, // 3148: decode to EVMHOSMIANW using decoder 277
9050 // 3148: }
9051 7, 0, // 3153: case 0x7: {
9052 OPC_CheckField, 26, 6, 4, // 3155: check Inst[31:26] == 0x4
9053 OPC_Decode, 184, 8, 149, 2, // 3159: decode to EVMHOSMFANW using decoder 277
9054 // 3159: }
9055 // 3159: } // switch Inst[2:0]
9056 // 3159: }
9057 181, 1, 69, // 3164: case 0xb5: {
9058 OPC_SwitchField, 0, 3, // 3167: switch Inst[2:0] {
9059 0, 9, // 3170: case 0x0: {
9060 OPC_CheckField, 26, 6, 4, // 3172: check Inst[31:26] == 0x4
9061 OPC_Decode, 154, 8, 149, 2, // 3176: decode to EVMHEGUMIAN using decoder 277
9062 // 3176: }
9063 1, 9, // 3181: case 0x1: {
9064 OPC_CheckField, 26, 6, 4, // 3183: check Inst[31:26] == 0x4
9065 OPC_Decode, 152, 8, 149, 2, // 3187: decode to EVMHEGSMIAN using decoder 277
9066 // 3187: }
9067 3, 9, // 3192: case 0x3: {
9068 OPC_CheckField, 26, 6, 4, // 3194: check Inst[31:26] == 0x4
9069 OPC_Decode, 150, 8, 149, 2, // 3198: decode to EVMHEGSMFAN using decoder 277
9070 // 3198: }
9071 4, 9, // 3203: case 0x4: {
9072 OPC_CheckField, 26, 6, 4, // 3205: check Inst[31:26] == 0x4
9073 OPC_Decode, 180, 8, 149, 2, // 3209: decode to EVMHOGUMIAN using decoder 277
9074 // 3209: }
9075 5, 9, // 3214: case 0x5: {
9076 OPC_CheckField, 26, 6, 4, // 3216: check Inst[31:26] == 0x4
9077 OPC_Decode, 178, 8, 149, 2, // 3220: decode to EVMHOGSMIAN using decoder 277
9078 // 3220: }
9079 7, 0, // 3225: case 0x7: {
9080 OPC_CheckField, 26, 6, 4, // 3227: check Inst[31:26] == 0x4
9081 OPC_Decode, 176, 8, 149, 2, // 3231: decode to EVMHOGSMFAN using decoder 277
9082 // 3231: }
9083 // 3231: } // switch Inst[2:0]
9084 // 3231: }
9085 184, 1, 25, // 3236: case 0xb8: {
9086 OPC_SwitchField, 0, 3, // 3239: switch Inst[2:0] {
9087 0, 9, // 3242: case 0x0: {
9088 OPC_CheckField, 26, 6, 4, // 3244: check Inst[31:26] == 0x4
9089 OPC_Decode, 219, 8, 149, 2, // 3248: decode to EVMWLUSIANW using decoder 277
9090 // 3248: }
9091 1, 0, // 3253: case 0x1: {
9092 OPC_CheckField, 26, 6, 4, // 3255: check Inst[31:26] == 0x4
9093 OPC_Decode, 213, 8, 149, 2, // 3259: decode to EVMWLSSIANW using decoder 277
9094 // 3259: }
9095 // 3259: } // switch Inst[2:0]
9096 // 3259: }
9097 185, 1, 25, // 3264: case 0xb9: {
9098 OPC_SwitchField, 0, 3, // 3267: switch Inst[2:0] {
9099 0, 9, // 3270: case 0x0: {
9100 OPC_CheckField, 26, 6, 4, // 3272: check Inst[31:26] == 0x4
9101 OPC_Decode, 217, 8, 149, 2, // 3276: decode to EVMWLUMIANW using decoder 277
9102 // 3276: }
9103 1, 0, // 3281: case 0x1: {
9104 OPC_CheckField, 26, 6, 4, // 3283: check Inst[31:26] == 0x4
9105 OPC_Decode, 211, 8, 149, 2, // 3287: decode to EVMWLSMIANW using decoder 277
9106 // 3287: }
9107 // 3287: } // switch Inst[2:0]
9108 // 3287: }
9109 186, 1, 13, // 3292: case 0xba: {
9110 OPC_CheckField, 26, 6, 4, // 3295: check Inst[31:26] == 0x4
9111 OPC_CheckField, 0, 3, 3, // 3299: check Inst[2:0] == 0x3
9112 OPC_Decode, 231, 8, 149, 2, // 3303: decode to EVMWSSFAN using decoder 277
9113 // 3303: }
9114 187, 1, 0, // 3308: case 0xbb: {
9115 OPC_SwitchField, 0, 3, // 3311: switch Inst[2:0] {
9116 0, 9, // 3314: case 0x0: {
9117 OPC_CheckField, 26, 6, 4, // 3316: check Inst[31:26] == 0x4
9118 OPC_Decode, 235, 8, 149, 2, // 3320: decode to EVMWUMIAN using decoder 277
9119 // 3320: }
9120 1, 9, // 3325: case 0x1: {
9121 OPC_CheckField, 26, 6, 4, // 3327: check Inst[31:26] == 0x4
9122 OPC_Decode, 227, 8, 149, 2, // 3331: decode to EVMWSMIAN using decoder 277
9123 // 3331: }
9124 3, 0, // 3336: case 0x3: {
9125 OPC_CheckField, 26, 6, 4, // 3338: check Inst[31:26] == 0x4
9126 OPC_Decode, 223, 8, 149, 2, // 3342: decode to EVMWSMFAN using decoder 277
9127 // 3342: }
9128 // 3342: } // switch Inst[2:0]
9129 // 3342: }
9130 // 3342: } // switch Inst[10:3]
9131};
9132static const uint8_t DecoderTable64[1965] = {
9133 OPC_SwitchField, 27, 5, // 0: switch Inst[31:27] {
9134 7, 62, // 3: case 0x7: {
9135 OPC_SwitchField, 26, 1, // 5: switch Inst[26] {
9136 0, 30, // 8: case 0x0: {
9137 OPC_SwitchField, 50, 14, // 10: switch Inst[63:50] {
9138 128, 3, 16, // 13: case 0x180: {
9139 OPC_Scope, 9, // 16: try {
9140 OPC_CheckField, 16, 5, 0, // 18: check Inst[20:16] == 0x0
9141 OPC_Decode, 158, 13, 164, 2, // 22: decode to PLI using decoder 292
9142 // 22: } else try {
9143 OPC_Decode, 235, 12, 165, 2, // 27: decode to PADDI using decoder 293
9144 // 27: }
9145 // 27: }
9146 132, 3, 0, // 32: case 0x184: {
9147 OPC_Decode, 243, 12, 166, 2, // 35: decode to PADDIpc using decoder 294
9148 // 35: }
9149 // 35: } // switch Inst[63:50]
9150 // 35: }
9151 1, 0, // 40: case 0x1: {
9152 OPC_SwitchField, 52, 1, // 42: switch Inst[52] {
9153 0, 9, // 45: case 0x0: {
9154 OPC_CheckField, 55, 9, 12, // 47: check Inst[63:55] == 0xc
9155 OPC_Decode, 238, 12, 167, 2, // 51: decode to PADDIS using decoder 295
9156 // 51: }
9157 1, 0, // 56: case 0x1: {
9158 OPC_CheckField, 55, 9, 12, // 58: check Inst[63:55] == 0xc
9159 OPC_Decode, 241, 12, 168, 2, // 62: decode to PADDISpc using decoder 296
9160 // 62: }
9161 // 62: } // switch Inst[52]
9162 // 62: }
9163 // 62: } // switch Inst[26]
9164 // 62: }
9165 16, 125, // 67: case 0x10: {
9166 OPC_SwitchField, 50, 14, // 69: switch Inst[63:50] {
9167 192, 2, 95, // 72: case 0x140: {
9168 OPC_SwitchField, 26, 1, // 75: switch Inst[26] {
9169 0, 41, // 78: case 0x0: {
9170 OPC_SwitchField, 18, 3, // 80: switch Inst[20:18] {
9171 0, 9, // 83: case 0x0: {
9172 OPC_CheckField, 48, 2, 0, // 85: check Inst[49:48] == 0x0
9173 OPC_Decode, 164, 23, 169, 2, // 89: decode to XXSPLTI32DX using decoder 297
9174 // 89: }
9175 1, 0, // 94: case 0x1: {
9176 OPC_SwitchField, 17, 1, // 96: switch Inst[17] {
9177 0, 9, // 99: case 0x0: {
9178 OPC_CheckField, 48, 2, 0, // 101: check Inst[49:48] == 0x0
9179 OPC_Decode, 166, 23, 170, 2, // 105: decode to XXSPLTIDP using decoder 298
9180 // 105: }
9181 1, 0, // 110: case 0x1: {
9182 OPC_CheckField, 48, 2, 0, // 112: check Inst[49:48] == 0x0
9183 OPC_Decode, 167, 23, 170, 2, // 116: decode to XXSPLTIW using decoder 298
9184 // 116: }
9185 // 116: } // switch Inst[17]
9186 // 116: }
9187 // 116: } // switch Inst[20:18]
9188 // 116: }
9189 1, 0, // 121: case 0x1: {
9190 OPC_SwitchField, 4, 2, // 123: switch Inst[5:4] {
9191 0, 9, // 126: case 0x0: {
9192 OPC_CheckField, 32, 18, 0, // 128: check Inst[49:32] == 0x0
9193 OPC_Decode, 245, 22, 238, 1, // 132: decode to XXBLENDVB using decoder 238
9194 // 132: }
9195 1, 9, // 137: case 0x1: {
9196 OPC_CheckField, 32, 18, 0, // 139: check Inst[49:32] == 0x0
9197 OPC_Decode, 247, 22, 238, 1, // 143: decode to XXBLENDVH using decoder 238
9198 // 143: }
9199 2, 9, // 148: case 0x2: {
9200 OPC_CheckField, 32, 18, 0, // 150: check Inst[49:32] == 0x0
9201 OPC_Decode, 248, 22, 238, 1, // 154: decode to XXBLENDVW using decoder 238
9202 // 154: }
9203 3, 0, // 159: case 0x3: {
9204 OPC_CheckField, 32, 18, 0, // 161: check Inst[49:32] == 0x0
9205 OPC_Decode, 246, 22, 238, 1, // 165: decode to XXBLENDVD using decoder 238
9206 // 165: }
9207 // 165: } // switch Inst[5:4]
9208 // 165: }
9209 // 165: } // switch Inst[26]
9210 // 165: }
9211 128, 3, 9, // 170: case 0x180: {
9212 OPC_CheckField, 26, 1, 0, // 173: check Inst[26] == 0x0
9213 OPC_Decode, 168, 13, 171, 2, // 177: decode to PLWZ using decoder 299
9214 // 177: }
9215 132, 3, 0, // 182: case 0x184: {
9216 OPC_CheckField, 26, 1, 0, // 185: check Inst[26] == 0x0
9217 OPC_Decode, 175, 13, 172, 2, // 189: decode to PLWZpc using decoder 300
9218 // 189: }
9219 // 189: } // switch Inst[63:50]
9220 // 189: }
9221 17, 84, // 194: case 0x11: {
9222 OPC_SwitchField, 52, 12, // 196: switch Inst[63:52] {
9223 80, 49, // 199: case 0x50: {
9224 OPC_SwitchField, 5, 1, // 201: switch Inst[5] {
9225 0, 33, // 204: case 0x0: {
9226 OPC_SwitchField, 4, 1, // 206: switch Inst[4] {
9227 0, 13, // 209: case 0x0: {
9228 OPC_CheckField, 35, 17, 0, // 211: check Inst[51:35] == 0x0
9229 OPC_CheckField, 26, 1, 0, // 215: check Inst[26] == 0x0
9230 OPC_Decode, 159, 23, 173, 2, // 219: decode to XXPERMX using decoder 301
9231 // 219: }
9232 1, 0, // 224: case 0x1: {
9233 OPC_CheckField, 40, 12, 0, // 226: check Inst[51:40] == 0x0
9234 OPC_CheckField, 26, 1, 0, // 230: check Inst[26] == 0x0
9235 OPC_Decode, 253, 22, 174, 2, // 234: decode to XXEVAL using decoder 302
9236 // 234: }
9237 // 234: } // switch Inst[4]
9238 // 234: }
9239 1, 0, // 239: case 0x1: {
9240 OPC_CheckField, 26, 1, 0, // 241: check Inst[26] == 0x0
9241 OPC_Decode, 172, 23, 175, 2, // 245: decode to XXSSUMUDMCEXT using decoder 303
9242 // 245: }
9243 // 245: } // switch Inst[5]
9244 // 245: }
9245 96, 13, // 250: case 0x60: {
9246 OPC_CheckField, 50, 2, 0, // 252: check Inst[51:50] == 0x0
9247 OPC_CheckField, 26, 1, 0, // 256: check Inst[26] == 0x0
9248 OPC_Decode, 250, 12, 171, 2, // 260: decode to PLBZ using decoder 299
9249 // 260: }
9250 97, 0, // 265: case 0x61: {
9251 OPC_CheckField, 50, 2, 0, // 267: check Inst[51:50] == 0x0
9252 OPC_CheckField, 26, 1, 0, // 271: check Inst[26] == 0x0
9253 OPC_Decode, 129, 13, 172, 2, // 275: decode to PLBZpc using decoder 300
9254 // 275: }
9255 // 275: } // switch Inst[63:52]
9256 // 275: }
9257 18, 27, // 280: case 0x12: {
9258 OPC_SwitchField, 50, 14, // 282: switch Inst[63:50] {
9259 128, 3, 9, // 285: case 0x180: {
9260 OPC_CheckField, 26, 1, 0, // 288: check Inst[26] == 0x0
9261 OPC_Decode, 177, 14, 171, 2, // 292: decode to PSTW using decoder 299
9262 // 292: }
9263 132, 3, 0, // 297: case 0x184: {
9264 OPC_CheckField, 26, 1, 0, // 300: check Inst[26] == 0x0
9265 OPC_Decode, 184, 14, 172, 2, // 304: decode to PSTWpc using decoder 300
9266 // 304: }
9267 // 304: } // switch Inst[63:50]
9268 // 304: }
9269 19, 27, // 309: case 0x13: {
9270 OPC_SwitchField, 50, 14, // 311: switch Inst[63:50] {
9271 128, 3, 9, // 314: case 0x180: {
9272 OPC_CheckField, 26, 1, 0, // 317: check Inst[26] == 0x0
9273 OPC_Decode, 149, 14, 171, 2, // 321: decode to PSTB using decoder 299
9274 // 321: }
9275 132, 3, 0, // 326: case 0x184: {
9276 OPC_CheckField, 26, 1, 0, // 329: check Inst[26] == 0x0
9277 OPC_Decode, 156, 14, 172, 2, // 333: decode to PSTBpc using decoder 300
9278 // 333: }
9279 // 333: } // switch Inst[63:50]
9280 // 333: }
9281 20, 51, // 338: case 0x14: {
9282 OPC_SwitchField, 50, 14, // 340: switch Inst[63:50] {
9283 128, 2, 9, // 343: case 0x100: {
9284 OPC_CheckField, 26, 1, 1, // 346: check Inst[26] == 0x1
9285 OPC_Decode, 160, 13, 171, 2, // 350: decode to PLWA using decoder 299
9286 // 350: }
9287 132, 2, 9, // 355: case 0x104: {
9288 OPC_CheckField, 26, 1, 1, // 358: check Inst[26] == 0x1
9289 OPC_Decode, 167, 13, 172, 2, // 362: decode to PLWApc using decoder 300
9290 // 362: }
9291 128, 3, 9, // 367: case 0x180: {
9292 OPC_CheckField, 26, 1, 0, // 370: check Inst[26] == 0x0
9293 OPC_Decode, 150, 13, 171, 2, // 374: decode to PLHZ using decoder 299
9294 // 374: }
9295 132, 3, 0, // 379: case 0x184: {
9296 OPC_CheckField, 26, 1, 0, // 382: check Inst[26] == 0x0
9297 OPC_Decode, 157, 13, 172, 2, // 386: decode to PLHZpc using decoder 300
9298 // 386: }
9299 // 386: } // switch Inst[63:50]
9300 // 386: }
9301 21, 67, // 391: case 0x15: {
9302 OPC_SwitchField, 50, 14, // 393: switch Inst[63:50] {
9303 128, 2, 17, // 396: case 0x100: {
9304 OPC_SwitchField, 26, 1, // 399: switch Inst[26] {
9305 0, 5, // 402: case 0x0: {
9306 OPC_Decode, 176, 13, 176, 2, // 404: decode to PLXSD using decoder 304
9307 // 404: }
9308 1, 0, // 409: case 0x1: {
9309 OPC_Decode, 180, 13, 176, 2, // 411: decode to PLXSSP using decoder 304
9310 // 411: }
9311 // 411: } // switch Inst[26]
9312 // 411: }
9313 132, 2, 17, // 416: case 0x104: {
9314 OPC_SwitchField, 26, 1, // 419: switch Inst[26] {
9315 0, 5, // 422: case 0x0: {
9316 OPC_Decode, 179, 13, 177, 2, // 424: decode to PLXSDpc using decoder 305
9317 // 424: }
9318 1, 0, // 429: case 0x1: {
9319 OPC_Decode, 183, 13, 177, 2, // 431: decode to PLXSSPpc using decoder 305
9320 // 431: }
9321 // 431: } // switch Inst[26]
9322 // 431: }
9323 128, 3, 9, // 436: case 0x180: {
9324 OPC_CheckField, 26, 1, 0, // 439: check Inst[26] == 0x0
9325 OPC_Decode, 142, 13, 171, 2, // 443: decode to PLHA using decoder 299
9326 // 443: }
9327 132, 3, 0, // 448: case 0x184: {
9328 OPC_CheckField, 26, 1, 0, // 451: check Inst[26] == 0x0
9329 OPC_Decode, 149, 13, 172, 2, // 455: decode to PLHApc using decoder 300
9330 // 455: }
9331 // 455: } // switch Inst[63:50]
9332 // 455: }
9333 22, 27, // 460: case 0x16: {
9334 OPC_SwitchField, 50, 14, // 462: switch Inst[63:50] {
9335 128, 3, 9, // 465: case 0x180: {
9336 OPC_CheckField, 26, 1, 0, // 468: check Inst[26] == 0x0
9337 OPC_Decode, 169, 14, 171, 2, // 472: decode to PSTH using decoder 299
9338 // 472: }
9339 132, 3, 0, // 477: case 0x184: {
9340 OPC_CheckField, 26, 1, 0, // 480: check Inst[26] == 0x0
9341 OPC_Decode, 176, 14, 172, 2, // 484: decode to PSTHpc using decoder 300
9342 // 484: }
9343 // 484: } // switch Inst[63:50]
9344 // 484: }
9345 23, 45, // 489: case 0x17: {
9346 OPC_SwitchField, 26, 1, // 491: switch Inst[26] {
9347 0, 19, // 494: case 0x0: {
9348 OPC_SwitchField, 50, 14, // 496: switch Inst[63:50] {
9349 128, 2, 5, // 499: case 0x100: {
9350 OPC_Decode, 185, 14, 176, 2, // 502: decode to PSTXSD using decoder 304
9351 // 502: }
9352 132, 2, 0, // 507: case 0x104: {
9353 OPC_Decode, 188, 14, 177, 2, // 510: decode to PSTXSDpc using decoder 305
9354 // 510: }
9355 // 510: } // switch Inst[63:50]
9356 // 510: }
9357 1, 0, // 515: case 0x1: {
9358 OPC_SwitchField, 50, 14, // 517: switch Inst[63:50] {
9359 128, 2, 5, // 520: case 0x100: {
9360 OPC_Decode, 189, 14, 176, 2, // 523: decode to PSTXSSP using decoder 304
9361 // 523: }
9362 132, 2, 0, // 528: case 0x104: {
9363 OPC_Decode, 192, 14, 177, 2, // 531: decode to PSTXSSPpc using decoder 305
9364 // 531: }
9365 // 531: } // switch Inst[63:50]
9366 // 531: }
9367 // 531: } // switch Inst[26]
9368 // 531: }
9369 24, 27, // 536: case 0x18: {
9370 OPC_SwitchField, 50, 14, // 538: switch Inst[63:50] {
9371 128, 3, 9, // 541: case 0x180: {
9372 OPC_CheckField, 26, 1, 0, // 544: check Inst[26] == 0x0
9373 OPC_Decode, 138, 13, 178, 2, // 548: decode to PLFS using decoder 306
9374 // 548: }
9375 132, 3, 0, // 553: case 0x184: {
9376 OPC_CheckField, 26, 1, 0, // 556: check Inst[26] == 0x0
9377 OPC_Decode, 141, 13, 179, 2, // 560: decode to PLFSpc using decoder 307
9378 // 560: }
9379 // 560: } // switch Inst[63:50]
9380 // 560: }
9381 25, 43, // 565: case 0x19: {
9382 OPC_SwitchField, 50, 14, // 567: switch Inst[63:50] {
9383 128, 2, 5, // 570: case 0x100: {
9384 OPC_Decode, 184, 13, 180, 2, // 573: decode to PLXV using decoder 308
9385 // 573: }
9386 132, 2, 5, // 578: case 0x104: {
9387 OPC_Decode, 191, 13, 181, 2, // 581: decode to PLXVpc using decoder 309
9388 // 581: }
9389 128, 3, 9, // 586: case 0x180: {
9390 OPC_CheckField, 26, 1, 0, // 589: check Inst[26] == 0x0
9391 OPC_Decode, 134, 13, 182, 2, // 593: decode to PLFD using decoder 310
9392 // 593: }
9393 132, 3, 0, // 598: case 0x184: {
9394 OPC_CheckField, 26, 1, 0, // 601: check Inst[26] == 0x0
9395 OPC_Decode, 137, 13, 183, 2, // 605: decode to PLFDpc using decoder 311
9396 // 605: }
9397 // 605: } // switch Inst[63:50]
9398 // 605: }
9399 26, 27, // 610: case 0x1a: {
9400 OPC_SwitchField, 50, 14, // 612: switch Inst[63:50] {
9401 128, 3, 9, // 615: case 0x180: {
9402 OPC_CheckField, 26, 1, 0, // 618: check Inst[26] == 0x0
9403 OPC_Decode, 165, 14, 178, 2, // 622: decode to PSTFS using decoder 306
9404 // 622: }
9405 132, 3, 0, // 627: case 0x184: {
9406 OPC_CheckField, 26, 1, 0, // 630: check Inst[26] == 0x0
9407 OPC_Decode, 168, 14, 179, 2, // 634: decode to PSTFSpc using decoder 307
9408 // 634: }
9409 // 634: } // switch Inst[63:50]
9410 // 634: }
9411 27, 43, // 639: case 0x1b: {
9412 OPC_SwitchField, 50, 14, // 641: switch Inst[63:50] {
9413 128, 2, 5, // 644: case 0x100: {
9414 OPC_Decode, 193, 14, 180, 2, // 647: decode to PSTXV using decoder 308
9415 // 647: }
9416 132, 2, 5, // 652: case 0x104: {
9417 OPC_Decode, 200, 14, 181, 2, // 655: decode to PSTXVpc using decoder 309
9418 // 655: }
9419 128, 3, 9, // 660: case 0x180: {
9420 OPC_CheckField, 26, 1, 0, // 663: check Inst[26] == 0x0
9421 OPC_Decode, 161, 14, 182, 2, // 667: decode to PSTFD using decoder 310
9422 // 667: }
9423 132, 3, 0, // 672: case 0x184: {
9424 OPC_CheckField, 26, 1, 0, // 675: check Inst[26] == 0x0
9425 OPC_Decode, 164, 14, 183, 2, // 679: decode to PSTFDpc using decoder 311
9426 // 679: }
9427 // 679: } // switch Inst[63:50]
9428 // 679: }
9429 28, 27, // 684: case 0x1c: {
9430 OPC_SwitchField, 50, 14, // 686: switch Inst[63:50] {
9431 128, 2, 9, // 689: case 0x100: {
9432 OPC_CheckField, 26, 1, 1, // 692: check Inst[26] == 0x1
9433 OPC_Decode, 130, 13, 184, 2, // 696: decode to PLD using decoder 312
9434 // 696: }
9435 132, 2, 0, // 701: case 0x104: {
9436 OPC_CheckField, 26, 1, 1, // 704: check Inst[26] == 0x1
9437 OPC_Decode, 133, 13, 185, 2, // 708: decode to PLDpc using decoder 313
9438 // 708: }
9439 // 708: } // switch Inst[63:50]
9440 // 708: }
9441 29, 167, 9, // 713: case 0x1d: {
9442 OPC_SwitchField, 50, 14, // 716: switch Inst[63:50] {
9443 128, 2, 9, // 719: case 0x100: {
9444 OPC_CheckField, 26, 1, 0, // 722: check Inst[26] == 0x0
9445 OPC_Decode, 185, 13, 186, 2, // 726: decode to PLXVP using decoder 314
9446 // 726: }
9447 132, 2, 9, // 731: case 0x104: {
9448 OPC_CheckField, 26, 1, 0, // 734: check Inst[26] == 0x0
9449 OPC_Decode, 188, 13, 187, 2, // 738: decode to PLXVPpc using decoder 315
9450 // 738: }
9451 228, 3, 0, // 743: case 0x1e4: {
9452 OPC_SwitchField, 3, 8, // 746: switch Inst[10:3] {
9453 2, 25, // 749: case 0x2: {
9454 OPC_CheckField, 48, 2, 0, // 751: check Inst[49:48] == 0x0
9455 OPC_CheckField, 40, 4, 0, // 755: check Inst[43:40] == 0x0
9456 OPC_CheckField, 26, 1, 1, // 759: check Inst[26] == 0x1
9457 OPC_CheckField, 21, 2, 0, // 763: check Inst[22:21] == 0x0
9458 OPC_CheckField, 0, 1, 0, // 767: check Inst[0] == 0x0
9459 OPC_Decode, 130, 14, 188, 2, // 771: decode to PMXVI8GER4PP using decoder 316
9460 // 771: }
9461 3, 25, // 776: case 0x3: {
9462 OPC_CheckField, 48, 2, 0, // 778: check Inst[49:48] == 0x0
9463 OPC_CheckField, 40, 4, 0, // 782: check Inst[43:40] == 0x0
9464 OPC_CheckField, 26, 1, 1, // 786: check Inst[26] == 0x1
9465 OPC_CheckField, 21, 2, 0, // 790: check Inst[22:21] == 0x0
9466 OPC_CheckField, 0, 1, 0, // 794: check Inst[0] == 0x0
9467 OPC_Decode, 129, 14, 189, 2, // 798: decode to PMXVI8GER4 using decoder 317
9468 // 798: }
9469 10, 25, // 803: case 0xa: {
9470 OPC_CheckField, 48, 2, 0, // 805: check Inst[49:48] == 0x0
9471 OPC_CheckField, 26, 1, 1, // 809: check Inst[26] == 0x1
9472 OPC_CheckField, 21, 2, 0, // 813: check Inst[22:21] == 0x0
9473 OPC_CheckField, 16, 1, 0, // 817: check Inst[16] == 0x0
9474 OPC_CheckField, 0, 1, 0, // 821: check Inst[0] == 0x0
9475 OPC_Decode, 203, 13, 190, 2, // 825: decode to PMDMXVI8GERX4PP using decoder 318
9476 // 825: }
9477 11, 25, // 830: case 0xb: {
9478 OPC_CheckField, 48, 2, 0, // 832: check Inst[49:48] == 0x0
9479 OPC_CheckField, 26, 1, 1, // 836: check Inst[26] == 0x1
9480 OPC_CheckField, 21, 2, 0, // 840: check Inst[22:21] == 0x0
9481 OPC_CheckField, 16, 1, 0, // 844: check Inst[16] == 0x0
9482 OPC_CheckField, 0, 1, 0, // 848: check Inst[0] == 0x0
9483 OPC_Decode, 202, 13, 191, 2, // 852: decode to PMDMXVI8GERX4 using decoder 319
9484 // 852: }
9485 18, 25, // 857: case 0x12: {
9486 OPC_CheckField, 48, 2, 0, // 859: check Inst[49:48] == 0x0
9487 OPC_CheckField, 40, 6, 0, // 863: check Inst[45:40] == 0x0
9488 OPC_CheckField, 26, 1, 1, // 867: check Inst[26] == 0x1
9489 OPC_CheckField, 21, 2, 0, // 871: check Inst[22:21] == 0x0
9490 OPC_CheckField, 0, 1, 0, // 875: check Inst[0] == 0x0
9491 OPC_Decode, 219, 13, 192, 2, // 879: decode to PMXVF16GER2PP using decoder 320
9492 // 879: }
9493 19, 25, // 884: case 0x13: {
9494 OPC_CheckField, 48, 2, 0, // 886: check Inst[49:48] == 0x0
9495 OPC_CheckField, 40, 6, 0, // 890: check Inst[45:40] == 0x0
9496 OPC_CheckField, 26, 1, 1, // 894: check Inst[26] == 0x1
9497 OPC_CheckField, 21, 2, 0, // 898: check Inst[22:21] == 0x0
9498 OPC_CheckField, 0, 1, 0, // 902: check Inst[0] == 0x0
9499 OPC_Decode, 215, 13, 193, 2, // 906: decode to PMXVF16GER2 using decoder 321
9500 // 906: }
9501 26, 21, // 911: case 0x1a: {
9502 OPC_CheckField, 40, 10, 0, // 913: check Inst[49:40] == 0x0
9503 OPC_CheckField, 26, 1, 1, // 917: check Inst[26] == 0x1
9504 OPC_CheckField, 21, 2, 0, // 921: check Inst[22:21] == 0x0
9505 OPC_CheckField, 0, 1, 0, // 925: check Inst[0] == 0x0
9506 OPC_Decode, 229, 13, 194, 2, // 929: decode to PMXVF32GERPP using decoder 322
9507 // 929: }
9508 27, 21, // 934: case 0x1b: {
9509 OPC_CheckField, 40, 10, 0, // 936: check Inst[49:40] == 0x0
9510 OPC_CheckField, 26, 1, 1, // 940: check Inst[26] == 0x1
9511 OPC_CheckField, 21, 2, 0, // 944: check Inst[22:21] == 0x0
9512 OPC_CheckField, 0, 1, 0, // 948: check Inst[0] == 0x0
9513 OPC_Decode, 225, 13, 195, 2, // 952: decode to PMXVF32GER using decoder 323
9514 // 952: }
9515 34, 21, // 957: case 0x22: {
9516 OPC_CheckField, 48, 2, 0, // 959: check Inst[49:48] == 0x0
9517 OPC_CheckField, 26, 1, 1, // 963: check Inst[26] == 0x1
9518 OPC_CheckField, 21, 2, 0, // 967: check Inst[22:21] == 0x0
9519 OPC_CheckField, 0, 1, 0, // 971: check Inst[0] == 0x0
9520 OPC_Decode, 254, 13, 196, 2, // 975: decode to PMXVI4GER8PP using decoder 324
9521 // 975: }
9522 35, 21, // 980: case 0x23: {
9523 OPC_CheckField, 48, 2, 0, // 982: check Inst[49:48] == 0x0
9524 OPC_CheckField, 26, 1, 1, // 986: check Inst[26] == 0x1
9525 OPC_CheckField, 21, 2, 0, // 990: check Inst[22:21] == 0x0
9526 OPC_CheckField, 0, 1, 0, // 994: check Inst[0] == 0x0
9527 OPC_Decode, 253, 13, 197, 2, // 998: decode to PMXVI4GER8 using decoder 325
9528 // 998: }
9529 42, 25, // 1003: case 0x2a: {
9530 OPC_CheckField, 48, 2, 0, // 1005: check Inst[49:48] == 0x0
9531 OPC_CheckField, 40, 6, 0, // 1009: check Inst[45:40] == 0x0
9532 OPC_CheckField, 26, 1, 1, // 1013: check Inst[26] == 0x1
9533 OPC_CheckField, 21, 2, 0, // 1017: check Inst[22:21] == 0x0
9534 OPC_CheckField, 0, 1, 0, // 1021: check Inst[0] == 0x0
9535 OPC_Decode, 248, 13, 192, 2, // 1025: decode to PMXVI16GER2SPP using decoder 320
9536 // 1025: }
9537 43, 25, // 1030: case 0x2b: {
9538 OPC_CheckField, 48, 2, 0, // 1032: check Inst[49:48] == 0x0
9539 OPC_CheckField, 40, 6, 0, // 1036: check Inst[45:40] == 0x0
9540 OPC_CheckField, 26, 1, 1, // 1040: check Inst[26] == 0x1
9541 OPC_CheckField, 21, 2, 0, // 1044: check Inst[22:21] == 0x0
9542 OPC_CheckField, 0, 1, 0, // 1048: check Inst[0] == 0x0
9543 OPC_Decode, 247, 13, 193, 2, // 1052: decode to PMXVI16GER2S using decoder 321
9544 // 1052: }
9545 50, 25, // 1057: case 0x32: {
9546 OPC_CheckField, 48, 2, 0, // 1059: check Inst[49:48] == 0x0
9547 OPC_CheckField, 40, 6, 0, // 1063: check Inst[45:40] == 0x0
9548 OPC_CheckField, 26, 1, 1, // 1067: check Inst[26] == 0x1
9549 OPC_CheckField, 21, 2, 0, // 1071: check Inst[22:21] == 0x0
9550 OPC_CheckField, 0, 1, 0, // 1075: check Inst[0] == 0x0
9551 OPC_Decode, 209, 13, 192, 2, // 1079: decode to PMXVBF16GER2PP using decoder 320
9552 // 1079: }
9553 51, 25, // 1084: case 0x33: {
9554 OPC_CheckField, 48, 2, 0, // 1086: check Inst[49:48] == 0x0
9555 OPC_CheckField, 40, 6, 0, // 1090: check Inst[45:40] == 0x0
9556 OPC_CheckField, 26, 1, 1, // 1094: check Inst[26] == 0x1
9557 OPC_CheckField, 21, 2, 0, // 1098: check Inst[22:21] == 0x0
9558 OPC_CheckField, 0, 1, 0, // 1102: check Inst[0] == 0x0
9559 OPC_Decode, 205, 13, 193, 2, // 1106: decode to PMXVBF16GER2 using decoder 321
9560 // 1106: }
9561 58, 25, // 1111: case 0x3a: {
9562 OPC_CheckField, 40, 10, 0, // 1113: check Inst[49:40] == 0x0
9563 OPC_CheckField, 32, 2, 0, // 1117: check Inst[33:32] == 0x0
9564 OPC_CheckField, 26, 1, 1, // 1121: check Inst[26] == 0x1
9565 OPC_CheckField, 21, 2, 0, // 1125: check Inst[22:21] == 0x0
9566 OPC_CheckField, 0, 1, 0, // 1129: check Inst[0] == 0x0
9567 OPC_Decode, 239, 13, 198, 2, // 1133: decode to PMXVF64GERPP using decoder 326
9568 // 1133: }
9569 59, 25, // 1138: case 0x3b: {
9570 OPC_CheckField, 40, 10, 0, // 1140: check Inst[49:40] == 0x0
9571 OPC_CheckField, 32, 2, 0, // 1144: check Inst[33:32] == 0x0
9572 OPC_CheckField, 26, 1, 1, // 1148: check Inst[26] == 0x1
9573 OPC_CheckField, 21, 2, 0, // 1152: check Inst[22:21] == 0x0
9574 OPC_CheckField, 0, 1, 0, // 1156: check Inst[0] == 0x0
9575 OPC_Decode, 235, 13, 199, 2, // 1160: decode to PMXVF64GER using decoder 327
9576 // 1160: }
9577 66, 29, // 1165: case 0x42: {
9578 OPC_CheckField, 48, 2, 0, // 1167: check Inst[49:48] == 0x0
9579 OPC_CheckField, 44, 2, 0, // 1171: check Inst[45:44] == 0x0
9580 OPC_CheckField, 26, 1, 1, // 1175: check Inst[26] == 0x1
9581 OPC_CheckField, 21, 2, 0, // 1179: check Inst[22:21] == 0x0
9582 OPC_CheckField, 16, 1, 0, // 1183: check Inst[16] == 0x0
9583 OPC_CheckField, 0, 1, 0, // 1187: check Inst[0] == 0x0
9584 OPC_Decode, 201, 13, 200, 2, // 1191: decode to PMDMXVF16GERX2PP using decoder 328
9585 // 1191: }
9586 67, 29, // 1196: case 0x43: {
9587 OPC_CheckField, 48, 2, 0, // 1198: check Inst[49:48] == 0x0
9588 OPC_CheckField, 44, 2, 0, // 1202: check Inst[45:44] == 0x0
9589 OPC_CheckField, 26, 1, 1, // 1206: check Inst[26] == 0x1
9590 OPC_CheckField, 21, 2, 0, // 1210: check Inst[22:21] == 0x0
9591 OPC_CheckField, 16, 1, 0, // 1214: check Inst[16] == 0x0
9592 OPC_CheckField, 0, 1, 0, // 1218: check Inst[0] == 0x0
9593 OPC_Decode, 197, 13, 201, 2, // 1222: decode to PMDMXVF16GERX2 using decoder 329
9594 // 1222: }
9595 74, 29, // 1227: case 0x4a: {
9596 OPC_CheckField, 48, 2, 0, // 1229: check Inst[49:48] == 0x0
9597 OPC_CheckField, 44, 2, 0, // 1233: check Inst[45:44] == 0x0
9598 OPC_CheckField, 26, 1, 1, // 1237: check Inst[26] == 0x1
9599 OPC_CheckField, 21, 2, 0, // 1241: check Inst[22:21] == 0x0
9600 OPC_CheckField, 16, 1, 0, // 1245: check Inst[16] == 0x0
9601 OPC_CheckField, 0, 1, 0, // 1249: check Inst[0] == 0x0
9602 OPC_Decode, 196, 13, 200, 2, // 1253: decode to PMDMXVBF16GERX2PP using decoder 328
9603 // 1253: }
9604 75, 25, // 1258: case 0x4b: {
9605 OPC_CheckField, 48, 2, 0, // 1260: check Inst[49:48] == 0x0
9606 OPC_CheckField, 40, 6, 0, // 1264: check Inst[45:40] == 0x0
9607 OPC_CheckField, 26, 1, 1, // 1268: check Inst[26] == 0x1
9608 OPC_CheckField, 21, 2, 0, // 1272: check Inst[22:21] == 0x0
9609 OPC_CheckField, 0, 1, 0, // 1276: check Inst[0] == 0x0
9610 OPC_Decode, 245, 13, 193, 2, // 1280: decode to PMXVI16GER2 using decoder 321
9611 // 1280: }
9612 82, 25, // 1285: case 0x52: {
9613 OPC_CheckField, 48, 2, 0, // 1287: check Inst[49:48] == 0x0
9614 OPC_CheckField, 40, 6, 0, // 1291: check Inst[45:40] == 0x0
9615 OPC_CheckField, 26, 1, 1, // 1295: check Inst[26] == 0x1
9616 OPC_CheckField, 21, 2, 0, // 1299: check Inst[22:21] == 0x0
9617 OPC_CheckField, 0, 1, 0, // 1303: check Inst[0] == 0x0
9618 OPC_Decode, 217, 13, 192, 2, // 1307: decode to PMXVF16GER2NP using decoder 320
9619 // 1307: }
9620 83, 29, // 1312: case 0x53: {
9621 OPC_CheckField, 48, 2, 0, // 1314: check Inst[49:48] == 0x0
9622 OPC_CheckField, 44, 2, 0, // 1318: check Inst[45:44] == 0x0
9623 OPC_CheckField, 26, 1, 1, // 1322: check Inst[26] == 0x1
9624 OPC_CheckField, 21, 2, 0, // 1326: check Inst[22:21] == 0x0
9625 OPC_CheckField, 16, 1, 0, // 1330: check Inst[16] == 0x0
9626 OPC_CheckField, 0, 1, 0, // 1334: check Inst[0] == 0x0
9627 OPC_Decode, 199, 13, 200, 2, // 1338: decode to PMDMXVF16GERX2NP using decoder 328
9628 // 1338: }
9629 90, 21, // 1343: case 0x5a: {
9630 OPC_CheckField, 40, 10, 0, // 1345: check Inst[49:40] == 0x0
9631 OPC_CheckField, 26, 1, 1, // 1349: check Inst[26] == 0x1
9632 OPC_CheckField, 21, 2, 0, // 1353: check Inst[22:21] == 0x0
9633 OPC_CheckField, 0, 1, 0, // 1357: check Inst[0] == 0x0
9634 OPC_Decode, 227, 13, 194, 2, // 1361: decode to PMXVF32GERNP using decoder 322
9635 // 1361: }
9636 91, 29, // 1366: case 0x5b: {
9637 OPC_CheckField, 48, 2, 0, // 1368: check Inst[49:48] == 0x0
9638 OPC_CheckField, 44, 2, 0, // 1372: check Inst[45:44] == 0x0
9639 OPC_CheckField, 26, 1, 1, // 1376: check Inst[26] == 0x1
9640 OPC_CheckField, 21, 2, 0, // 1380: check Inst[22:21] == 0x0
9641 OPC_CheckField, 16, 1, 0, // 1384: check Inst[16] == 0x0
9642 OPC_CheckField, 0, 1, 0, // 1388: check Inst[0] == 0x0
9643 OPC_Decode, 192, 13, 201, 2, // 1392: decode to PMDMXVBF16GERX2 using decoder 329
9644 // 1392: }
9645 98, 25, // 1397: case 0x62: {
9646 OPC_CheckField, 48, 2, 0, // 1399: check Inst[49:48] == 0x0
9647 OPC_CheckField, 26, 1, 1, // 1403: check Inst[26] == 0x1
9648 OPC_CheckField, 21, 2, 0, // 1407: check Inst[22:21] == 0x0
9649 OPC_CheckField, 16, 1, 0, // 1411: check Inst[16] == 0x0
9650 OPC_CheckField, 0, 1, 0, // 1415: check Inst[0] == 0x0
9651 OPC_Decode, 204, 13, 190, 2, // 1419: decode to PMDMXVI8GERX4SPP using decoder 318
9652 // 1419: }
9653 99, 25, // 1424: case 0x63: {
9654 OPC_CheckField, 48, 2, 0, // 1426: check Inst[49:48] == 0x0
9655 OPC_CheckField, 40, 4, 0, // 1430: check Inst[43:40] == 0x0
9656 OPC_CheckField, 26, 1, 1, // 1434: check Inst[26] == 0x1
9657 OPC_CheckField, 21, 2, 0, // 1438: check Inst[22:21] == 0x0
9658 OPC_CheckField, 0, 1, 0, // 1442: check Inst[0] == 0x0
9659 OPC_Decode, 131, 14, 188, 2, // 1446: decode to PMXVI8GER4SPP using decoder 316
9660 // 1446: }
9661 107, 25, // 1451: case 0x6b: {
9662 OPC_CheckField, 48, 2, 0, // 1453: check Inst[49:48] == 0x0
9663 OPC_CheckField, 40, 6, 0, // 1457: check Inst[45:40] == 0x0
9664 OPC_CheckField, 26, 1, 1, // 1461: check Inst[26] == 0x1
9665 OPC_CheckField, 21, 2, 0, // 1465: check Inst[22:21] == 0x0
9666 OPC_CheckField, 0, 1, 0, // 1469: check Inst[0] == 0x0
9667 OPC_Decode, 246, 13, 192, 2, // 1473: decode to PMXVI16GER2PP using decoder 320
9668 // 1473: }
9669 114, 25, // 1478: case 0x72: {
9670 OPC_CheckField, 48, 2, 0, // 1480: check Inst[49:48] == 0x0
9671 OPC_CheckField, 40, 6, 0, // 1484: check Inst[45:40] == 0x0
9672 OPC_CheckField, 26, 1, 1, // 1488: check Inst[26] == 0x1
9673 OPC_CheckField, 21, 2, 0, // 1492: check Inst[22:21] == 0x0
9674 OPC_CheckField, 0, 1, 0, // 1496: check Inst[0] == 0x0
9675 OPC_Decode, 207, 13, 192, 2, // 1500: decode to PMXVBF16GER2NP using decoder 320
9676 // 1500: }
9677 115, 29, // 1505: case 0x73: {
9678 OPC_CheckField, 48, 2, 0, // 1507: check Inst[49:48] == 0x0
9679 OPC_CheckField, 44, 2, 0, // 1511: check Inst[45:44] == 0x0
9680 OPC_CheckField, 26, 1, 1, // 1515: check Inst[26] == 0x1
9681 OPC_CheckField, 21, 2, 0, // 1519: check Inst[22:21] == 0x0
9682 OPC_CheckField, 16, 1, 0, // 1523: check Inst[16] == 0x0
9683 OPC_CheckField, 0, 1, 0, // 1527: check Inst[0] == 0x0
9684 OPC_Decode, 194, 13, 200, 2, // 1531: decode to PMDMXVBF16GERX2NP using decoder 328
9685 // 1531: }
9686 122, 25, // 1536: case 0x7a: {
9687 OPC_CheckField, 40, 10, 0, // 1538: check Inst[49:40] == 0x0
9688 OPC_CheckField, 32, 2, 0, // 1542: check Inst[33:32] == 0x0
9689 OPC_CheckField, 26, 1, 1, // 1546: check Inst[26] == 0x1
9690 OPC_CheckField, 21, 2, 0, // 1550: check Inst[22:21] == 0x0
9691 OPC_CheckField, 0, 1, 0, // 1554: check Inst[0] == 0x0
9692 OPC_Decode, 237, 13, 198, 2, // 1558: decode to PMXVF64GERNP using decoder 326
9693 // 1558: }
9694 146, 1, 25, // 1563: case 0x92: {
9695 OPC_CheckField, 48, 2, 0, // 1566: check Inst[49:48] == 0x0
9696 OPC_CheckField, 40, 6, 0, // 1570: check Inst[45:40] == 0x0
9697 OPC_CheckField, 26, 1, 1, // 1574: check Inst[26] == 0x1
9698 OPC_CheckField, 21, 2, 0, // 1578: check Inst[22:21] == 0x0
9699 OPC_CheckField, 0, 1, 0, // 1582: check Inst[0] == 0x0
9700 OPC_Decode, 218, 13, 192, 2, // 1586: decode to PMXVF16GER2PN using decoder 320
9701 // 1586: }
9702 147, 1, 29, // 1591: case 0x93: {
9703 OPC_CheckField, 48, 2, 0, // 1594: check Inst[49:48] == 0x0
9704 OPC_CheckField, 44, 2, 0, // 1598: check Inst[45:44] == 0x0
9705 OPC_CheckField, 26, 1, 1, // 1602: check Inst[26] == 0x1
9706 OPC_CheckField, 21, 2, 0, // 1606: check Inst[22:21] == 0x0
9707 OPC_CheckField, 16, 1, 0, // 1610: check Inst[16] == 0x0
9708 OPC_CheckField, 0, 1, 0, // 1614: check Inst[0] == 0x0
9709 OPC_Decode, 200, 13, 200, 2, // 1618: decode to PMDMXVF16GERX2PN using decoder 328
9710 // 1618: }
9711 154, 1, 21, // 1623: case 0x9a: {
9712 OPC_CheckField, 40, 10, 0, // 1626: check Inst[49:40] == 0x0
9713 OPC_CheckField, 26, 1, 1, // 1630: check Inst[26] == 0x1
9714 OPC_CheckField, 21, 2, 0, // 1634: check Inst[22:21] == 0x0
9715 OPC_CheckField, 0, 1, 0, // 1638: check Inst[0] == 0x0
9716 OPC_Decode, 228, 13, 194, 2, // 1642: decode to PMXVF32GERPN using decoder 322
9717 // 1642: }
9718 178, 1, 25, // 1647: case 0xb2: {
9719 OPC_CheckField, 48, 2, 0, // 1650: check Inst[49:48] == 0x0
9720 OPC_CheckField, 40, 6, 0, // 1654: check Inst[45:40] == 0x0
9721 OPC_CheckField, 26, 1, 1, // 1658: check Inst[26] == 0x1
9722 OPC_CheckField, 21, 2, 0, // 1662: check Inst[22:21] == 0x0
9723 OPC_CheckField, 0, 1, 0, // 1666: check Inst[0] == 0x0
9724 OPC_Decode, 208, 13, 192, 2, // 1670: decode to PMXVBF16GER2PN using decoder 320
9725 // 1670: }
9726 179, 1, 29, // 1675: case 0xb3: {
9727 OPC_CheckField, 48, 2, 0, // 1678: check Inst[49:48] == 0x0
9728 OPC_CheckField, 44, 2, 0, // 1682: check Inst[45:44] == 0x0
9729 OPC_CheckField, 26, 1, 1, // 1686: check Inst[26] == 0x1
9730 OPC_CheckField, 21, 2, 0, // 1690: check Inst[22:21] == 0x0
9731 OPC_CheckField, 16, 1, 0, // 1694: check Inst[16] == 0x0
9732 OPC_CheckField, 0, 1, 0, // 1698: check Inst[0] == 0x0
9733 OPC_Decode, 195, 13, 200, 2, // 1702: decode to PMDMXVBF16GERX2PN using decoder 328
9734 // 1702: }
9735 186, 1, 25, // 1707: case 0xba: {
9736 OPC_CheckField, 40, 10, 0, // 1710: check Inst[49:40] == 0x0
9737 OPC_CheckField, 32, 2, 0, // 1714: check Inst[33:32] == 0x0
9738 OPC_CheckField, 26, 1, 1, // 1718: check Inst[26] == 0x1
9739 OPC_CheckField, 21, 2, 0, // 1722: check Inst[22:21] == 0x0
9740 OPC_CheckField, 0, 1, 0, // 1726: check Inst[0] == 0x0
9741 OPC_Decode, 238, 13, 198, 2, // 1730: decode to PMXVF64GERPN using decoder 326
9742 // 1730: }
9743 202, 1, 29, // 1735: case 0xca: {
9744 OPC_CheckField, 48, 2, 0, // 1738: check Inst[49:48] == 0x0
9745 OPC_CheckField, 44, 2, 0, // 1742: check Inst[45:44] == 0x0
9746 OPC_CheckField, 26, 1, 1, // 1746: check Inst[26] == 0x1
9747 OPC_CheckField, 21, 2, 0, // 1750: check Inst[22:21] == 0x0
9748 OPC_CheckField, 16, 1, 0, // 1754: check Inst[16] == 0x0
9749 OPC_CheckField, 0, 1, 0, // 1758: check Inst[0] == 0x0
9750 OPC_Decode, 198, 13, 200, 2, // 1762: decode to PMDMXVF16GERX2NN using decoder 328
9751 // 1762: }
9752 210, 1, 25, // 1767: case 0xd2: {
9753 OPC_CheckField, 48, 2, 0, // 1770: check Inst[49:48] == 0x0
9754 OPC_CheckField, 40, 6, 0, // 1774: check Inst[45:40] == 0x0
9755 OPC_CheckField, 26, 1, 1, // 1778: check Inst[26] == 0x1
9756 OPC_CheckField, 21, 2, 0, // 1782: check Inst[22:21] == 0x0
9757 OPC_CheckField, 0, 1, 0, // 1786: check Inst[0] == 0x0
9758 OPC_Decode, 216, 13, 192, 2, // 1790: decode to PMXVF16GER2NN using decoder 320
9759 // 1790: }
9760 218, 1, 21, // 1795: case 0xda: {
9761 OPC_CheckField, 40, 10, 0, // 1798: check Inst[49:40] == 0x0
9762 OPC_CheckField, 26, 1, 1, // 1802: check Inst[26] == 0x1
9763 OPC_CheckField, 21, 2, 0, // 1806: check Inst[22:21] == 0x0
9764 OPC_CheckField, 0, 1, 0, // 1810: check Inst[0] == 0x0
9765 OPC_Decode, 226, 13, 194, 2, // 1814: decode to PMXVF32GERNN using decoder 322
9766 // 1814: }
9767 234, 1, 29, // 1819: case 0xea: {
9768 OPC_CheckField, 48, 2, 0, // 1822: check Inst[49:48] == 0x0
9769 OPC_CheckField, 44, 2, 0, // 1826: check Inst[45:44] == 0x0
9770 OPC_CheckField, 26, 1, 1, // 1830: check Inst[26] == 0x1
9771 OPC_CheckField, 21, 2, 0, // 1834: check Inst[22:21] == 0x0
9772 OPC_CheckField, 16, 1, 0, // 1838: check Inst[16] == 0x0
9773 OPC_CheckField, 0, 1, 0, // 1842: check Inst[0] == 0x0
9774 OPC_Decode, 193, 13, 200, 2, // 1846: decode to PMDMXVBF16GERX2NN using decoder 328
9775 // 1846: }
9776 242, 1, 25, // 1851: case 0xf2: {
9777 OPC_CheckField, 48, 2, 0, // 1854: check Inst[49:48] == 0x0
9778 OPC_CheckField, 40, 6, 0, // 1858: check Inst[45:40] == 0x0
9779 OPC_CheckField, 26, 1, 1, // 1862: check Inst[26] == 0x1
9780 OPC_CheckField, 21, 2, 0, // 1866: check Inst[22:21] == 0x0
9781 OPC_CheckField, 0, 1, 0, // 1870: check Inst[0] == 0x0
9782 OPC_Decode, 206, 13, 192, 2, // 1874: decode to PMXVBF16GER2NN using decoder 320
9783 // 1874: }
9784 250, 1, 0, // 1879: case 0xfa: {
9785 OPC_CheckField, 40, 10, 0, // 1882: check Inst[49:40] == 0x0
9786 OPC_CheckField, 32, 2, 0, // 1886: check Inst[33:32] == 0x0
9787 OPC_CheckField, 26, 1, 1, // 1890: check Inst[26] == 0x1
9788 OPC_CheckField, 21, 2, 0, // 1894: check Inst[22:21] == 0x0
9789 OPC_CheckField, 0, 1, 0, // 1898: check Inst[0] == 0x0
9790 OPC_Decode, 236, 13, 198, 2, // 1902: decode to PMXVF64GERNN using decoder 326
9791 // 1902: }
9792 // 1902: } // switch Inst[10:3]
9793 // 1902: }
9794 // 1902: } // switch Inst[63:50]
9795 // 1902: }
9796 30, 27, // 1907: case 0x1e: {
9797 OPC_SwitchField, 50, 14, // 1909: switch Inst[63:50] {
9798 128, 2, 9, // 1912: case 0x100: {
9799 OPC_CheckField, 26, 1, 1, // 1915: check Inst[26] == 0x1
9800 OPC_Decode, 157, 14, 184, 2, // 1919: decode to PSTD using decoder 312
9801 // 1919: }
9802 132, 2, 0, // 1924: case 0x104: {
9803 OPC_CheckField, 26, 1, 1, // 1927: check Inst[26] == 0x1
9804 OPC_Decode, 160, 14, 185, 2, // 1931: decode to PSTDpc using decoder 313
9805 // 1931: }
9806 // 1931: } // switch Inst[63:50]
9807 // 1931: }
9808 31, 0, // 1936: case 0x1f: {
9809 OPC_SwitchField, 50, 14, // 1938: switch Inst[63:50] {
9810 128, 2, 9, // 1941: case 0x100: {
9811 OPC_CheckField, 26, 1, 0, // 1944: check Inst[26] == 0x0
9812 OPC_Decode, 194, 14, 186, 2, // 1948: decode to PSTXVP using decoder 314
9813 // 1948: }
9814 132, 2, 0, // 1953: case 0x104: {
9815 OPC_CheckField, 26, 1, 0, // 1956: check Inst[26] == 0x0
9816 OPC_Decode, 197, 14, 187, 2, // 1960: decode to PSTXVPpc using decoder 315
9817 // 1960: }
9818 // 1960: } // switch Inst[63:50]
9819 // 1960: }
9820 // 1960: } // switch Inst[31:27]
9821};
9822// Handling 330 cases.
9823template <typename InsnType>
9824static DecodeStatus decodeToMCInst(unsigned Idx, DecodeStatus S, InsnType insn, MCInst &MI, uint64_t Address, const MCDisassembler *Decoder, bool &DecodeComplete) {
9825 DecodeComplete = true;
9826 using TmpType = std::conditional_t<std::is_integral<InsnType>::value, InsnType, uint64_t>;
9827 TmpType tmp;
9828 switch (Idx) {
9829 default: llvm_unreachable("Invalid decoder index!");
9830 case 0:
9831 return S;
9832 case 1:
9833 tmp = fieldFromInstruction(insn, 21, 5);
9834 if (!Check(S, decodeUImmOperand<5>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
9835 tmp = fieldFromInstruction(insn, 16, 5);
9836 if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
9837 tmp = fieldFromInstruction(insn, 0, 16);
9838 if (!Check(S, decodeSImmOperand<16>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
9839 return S;
9840 case 2:
9841 tmp = fieldFromInstruction(insn, 21, 5);
9842 if (!Check(S, decodeUImmOperand<5>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
9843 tmp = fieldFromInstruction(insn, 16, 5);
9844 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
9845 tmp = fieldFromInstruction(insn, 0, 16);
9846 if (!Check(S, decodeSImmOperand<16>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
9847 return S;
9848 case 3:
9849 tmp = fieldFromInstruction(insn, 21, 5);
9850 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
9851 tmp = fieldFromInstruction(insn, 16, 5);
9852 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
9853 tmp = fieldFromInstruction(insn, 11, 5);
9854 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
9855 return S;
9856 case 4:
9857 tmp = fieldFromInstruction(insn, 21, 5);
9858 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
9859 tmp = fieldFromInstruction(insn, 16, 5);
9860 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
9861 return S;
9862 case 5:
9863 tmp = fieldFromInstruction(insn, 21, 5);
9864 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
9865 tmp = fieldFromInstruction(insn, 16, 5);
9866 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
9867 tmp = fieldFromInstruction(insn, 11, 5);
9868 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
9869 tmp = fieldFromInstruction(insn, 9, 1);
9870 if (!Check(S, decodeUImmOperand<1>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
9871 return S;
9872 case 6:
9873 tmp = fieldFromInstruction(insn, 23, 3);
9874 if (!Check(S, DecodeCRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
9875 tmp = fieldFromInstruction(insn, 16, 5);
9876 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
9877 tmp = fieldFromInstruction(insn, 11, 5);
9878 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
9879 return S;
9880 case 7:
9881 tmp = fieldFromInstruction(insn, 21, 5);
9882 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
9883 tmp = fieldFromInstruction(insn, 11, 5);
9884 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
9885 return S;
9886 case 8:
9887 tmp = fieldFromInstruction(insn, 21, 5);
9888 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
9889 tmp = fieldFromInstruction(insn, 11, 5);
9890 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
9891 tmp = fieldFromInstruction(insn, 9, 1);
9892 if (!Check(S, decodeUImmOperand<1>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
9893 return S;
9894 case 9:
9895 tmp = fieldFromInstruction(insn, 21, 5);
9896 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
9897 tmp = fieldFromInstruction(insn, 11, 5);
9898 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
9899 tmp = fieldFromInstruction(insn, 16, 1);
9900 if (!Check(S, decodeUImmOperand<1>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
9901 return S;
9902 case 10:
9903 tmp = fieldFromInstruction(insn, 21, 5);
9904 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
9905 tmp = fieldFromInstruction(insn, 11, 5);
9906 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
9907 tmp = fieldFromInstruction(insn, 16, 2);
9908 if (!Check(S, decodeUImmOperand<2>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
9909 return S;
9910 case 11:
9911 tmp = fieldFromInstruction(insn, 21, 5);
9912 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
9913 tmp = fieldFromInstruction(insn, 11, 5);
9914 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
9915 tmp = fieldFromInstruction(insn, 16, 3);
9916 if (!Check(S, decodeUImmOperand<3>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
9917 return S;
9918 case 12:
9919 tmp = fieldFromInstruction(insn, 21, 5);
9920 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
9921 tmp = fieldFromInstruction(insn, 11, 5);
9922 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
9923 return S;
9924 case 13:
9925 tmp = fieldFromInstruction(insn, 21, 5);
9926 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
9927 tmp = fieldFromInstruction(insn, 11, 5);
9928 if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
9929 return S;
9930 case 14:
9931 tmp = fieldFromInstruction(insn, 21, 5);
9932 if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
9933 tmp = fieldFromInstruction(insn, 11, 5);
9934 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
9935 tmp = fieldFromInstruction(insn, 16, 1);
9936 if (!Check(S, decodeUImmOperand<1>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
9937 return S;
9938 case 15:
9939 tmp = fieldFromInstruction(insn, 21, 5);
9940 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
9941 tmp = fieldFromInstruction(insn, 16, 5);
9942 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
9943 tmp = fieldFromInstruction(insn, 15, 1);
9944 if (!Check(S, decodeUImmOperand<1>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
9945 tmp = fieldFromInstruction(insn, 11, 4);
9946 if (!Check(S, decodeUImmOperand<4>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
9947 return S;
9948 case 16:
9949 tmp = fieldFromInstruction(insn, 21, 5);
9950 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
9951 tmp = fieldFromInstruction(insn, 16, 5);
9952 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
9953 tmp = fieldFromInstruction(insn, 11, 5);
9954 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
9955 tmp = fieldFromInstruction(insn, 21, 5);
9956 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
9957 return S;
9958 case 17:
9959 tmp = fieldFromInstruction(insn, 21, 5);
9960 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
9961 return S;
9962 case 18:
9963 tmp = fieldFromInstruction(insn, 11, 5);
9964 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
9965 return S;
9966 case 19:
9967 tmp = fieldFromInstruction(insn, 21, 5);
9968 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
9969 tmp = fieldFromInstruction(insn, 16, 5);
9970 if (!Check(S, decodeUImmOperand<5>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
9971 tmp = fieldFromInstruction(insn, 11, 5);
9972 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
9973 return S;
9974 case 20:
9975 tmp = fieldFromInstruction(insn, 21, 5);
9976 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
9977 tmp = fieldFromInstruction(insn, 16, 5);
9978 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
9979 tmp = fieldFromInstruction(insn, 11, 5);
9980 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
9981 return S;
9982 case 21:
9983 tmp = fieldFromInstruction(insn, 21, 5);
9984 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
9985 tmp = fieldFromInstruction(insn, 16, 5);
9986 if (!Check(S, decodeUImmOperand<4>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
9987 tmp = fieldFromInstruction(insn, 11, 5);
9988 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
9989 return S;
9990 case 22:
9991 tmp = fieldFromInstruction(insn, 21, 5);
9992 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
9993 tmp = fieldFromInstruction(insn, 16, 5);
9994 if (!Check(S, decodeSImmOperand<5>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
9995 return S;
9996 case 23:
9997 tmp = fieldFromInstruction(insn, 21, 5);
9998 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
9999 tmp = fieldFromInstruction(insn, 21, 5);
10000 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10001 tmp = fieldFromInstruction(insn, 16, 5);
10002 if (!Check(S, decodeUImmOperand<4>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10003 tmp = fieldFromInstruction(insn, 11, 5);
10004 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10005 return S;
10006 case 24:
10007 tmp = fieldFromInstruction(insn, 21, 5);
10008 if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10009 tmp = fieldFromInstruction(insn, 11, 5);
10010 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10011 tmp = fieldFromInstruction(insn, 16, 3);
10012 if (!Check(S, decodeUImmOperand<3>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10013 return S;
10014 case 25:
10015 tmp = fieldFromInstruction(insn, 21, 5);
10016 if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10017 tmp = fieldFromInstruction(insn, 16, 5);
10018 if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10019 tmp = fieldFromInstruction(insn, 11, 5);
10020 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10021 return S;
10022 case 26:
10023 tmp = fieldFromInstruction(insn, 21, 5);
10024 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10025 tmp = fieldFromInstruction(insn, 21, 5);
10026 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10027 tmp = fieldFromInstruction(insn, 16, 5);
10028 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10029 tmp = fieldFromInstruction(insn, 11, 5);
10030 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10031 return S;
10032 case 27:
10033 tmp = fieldFromInstruction(insn, 21, 5);
10034 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10035 tmp = fieldFromInstruction(insn, 21, 5);
10036 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10037 tmp = fieldFromInstruction(insn, 16, 5);
10038 if (!Check(S, decodeUImmOperand<4>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10039 tmp = fieldFromInstruction(insn, 11, 5);
10040 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10041 return S;
10042 case 28:
10043 tmp = fieldFromInstruction(insn, 21, 5);
10044 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10045 tmp = fieldFromInstruction(insn, 21, 5);
10046 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10047 tmp = fieldFromInstruction(insn, 16, 5);
10048 if (!Check(S, decodeUImmOperand<4>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10049 tmp = fieldFromInstruction(insn, 11, 5);
10050 if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10051 return S;
10052 case 29:
10053 tmp = fieldFromInstruction(insn, 21, 5);
10054 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10055 tmp = fieldFromInstruction(insn, 21, 5);
10056 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10057 tmp = fieldFromInstruction(insn, 16, 5);
10058 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10059 tmp = fieldFromInstruction(insn, 11, 5);
10060 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10061 return S;
10062 case 30:
10063 tmp = fieldFromInstruction(insn, 21, 5);
10064 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10065 tmp = fieldFromInstruction(insn, 21, 5);
10066 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10067 tmp = fieldFromInstruction(insn, 16, 5);
10068 if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10069 tmp = fieldFromInstruction(insn, 11, 5);
10070 if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10071 return S;
10072 case 31:
10073 tmp = fieldFromInstruction(insn, 21, 5);
10074 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10075 tmp = 0x0;
10076 tmp |= fieldFromInstruction(insn, 0, 1);
10077 tmp |= fieldFromInstruction(insn, 6, 10) << 6;
10078 tmp |= fieldFromInstruction(insn, 16, 5) << 1;
10079 if (!Check(S, decodeUImmOperand<16>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10080 return S;
10081 case 32:
10082 tmp = fieldFromInstruction(insn, 21, 5);
10083 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10084 tmp = fieldFromInstruction(insn, 16, 5);
10085 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10086 tmp = fieldFromInstruction(insn, 11, 5);
10087 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10088 tmp = fieldFromInstruction(insn, 6, 3);
10089 if (!Check(S, decodeUImmOperand<3>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10090 return S;
10091 case 33:
10092 tmp = fieldFromInstruction(insn, 21, 5);
10093 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10094 tmp = fieldFromInstruction(insn, 16, 5);
10095 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10096 tmp = fieldFromInstruction(insn, 11, 5);
10097 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10098 tmp = fieldFromInstruction(insn, 6, 5);
10099 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10100 return S;
10101 case 34:
10102 tmp = fieldFromInstruction(insn, 21, 5);
10103 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10104 tmp = fieldFromInstruction(insn, 16, 5);
10105 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10106 tmp = fieldFromInstruction(insn, 11, 5);
10107 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10108 tmp = fieldFromInstruction(insn, 6, 5);
10109 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10110 return S;
10111 case 35:
10112 tmp = fieldFromInstruction(insn, 21, 5);
10113 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10114 tmp = fieldFromInstruction(insn, 16, 5);
10115 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10116 tmp = fieldFromInstruction(insn, 11, 5);
10117 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10118 tmp = fieldFromInstruction(insn, 6, 4);
10119 if (!Check(S, decodeUImmOperand<4>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10120 return S;
10121 case 36:
10122 tmp = fieldFromInstruction(insn, 21, 5);
10123 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10124 tmp = fieldFromInstruction(insn, 16, 5);
10125 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10126 tmp = fieldFromInstruction(insn, 6, 5);
10127 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10128 tmp = fieldFromInstruction(insn, 11, 5);
10129 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10130 return S;
10131 case 37:
10132 tmp = fieldFromInstruction(insn, 21, 5);
10133 if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10134 tmp = fieldFromInstruction(insn, 16, 5);
10135 if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10136 tmp = fieldFromInstruction(insn, 11, 5);
10137 if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10138 tmp = fieldFromInstruction(insn, 6, 5);
10139 if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10140 return S;
10141 case 38:
10142 tmp = fieldFromInstruction(insn, 21, 5);
10143 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10144 tmp = fieldFromInstruction(insn, 16, 5);
10145 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10146 tmp = fieldFromInstruction(insn, 11, 5);
10147 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10148 tmp = fieldFromInstruction(insn, 6, 5);
10149 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10150 return S;
10151 case 39:
10152 tmp = 0x0;
10153 tmp |= fieldFromInstruction(insn, 21, 1) << 4;
10154 tmp |= fieldFromInstruction(insn, 22, 4);
10155 if (!Check(S, DecodeVSRpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10156 tmp = fieldFromInstruction(insn, 4, 12);
10157 if (!Check(S, decodeDispRIX16Operand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10158 tmp = fieldFromInstruction(insn, 16, 5);
10159 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10160 return S;
10161 case 40:
10162 tmp = fieldFromInstruction(insn, 21, 5);
10163 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10164 tmp = fieldFromInstruction(insn, 16, 5);
10165 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10166 tmp = fieldFromInstruction(insn, 0, 16);
10167 if (!Check(S, decodeSImmOperand<16>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10168 return S;
10169 case 41:
10170 tmp = fieldFromInstruction(insn, 23, 3);
10171 if (!Check(S, DecodeCRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10172 tmp = fieldFromInstruction(insn, 16, 5);
10173 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10174 tmp = fieldFromInstruction(insn, 0, 16);
10175 if (!Check(S, decodeUImmOperand<16>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10176 return S;
10177 case 42:
10178 tmp = fieldFromInstruction(insn, 23, 3);
10179 if (!Check(S, DecodeCRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10180 tmp = fieldFromInstruction(insn, 16, 5);
10181 if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10182 tmp = fieldFromInstruction(insn, 0, 16);
10183 if (!Check(S, decodeUImmOperand<16>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10184 return S;
10185 case 43:
10186 tmp = fieldFromInstruction(insn, 23, 3);
10187 if (!Check(S, DecodeCRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10188 tmp = fieldFromInstruction(insn, 16, 5);
10189 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10190 tmp = fieldFromInstruction(insn, 0, 16);
10191 if (!Check(S, decodeSImmOperand<16>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10192 return S;
10193 case 44:
10194 tmp = fieldFromInstruction(insn, 23, 3);
10195 if (!Check(S, DecodeCRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10196 tmp = fieldFromInstruction(insn, 16, 5);
10197 if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10198 tmp = fieldFromInstruction(insn, 0, 16);
10199 if (!Check(S, decodeSImmOperand<16>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10200 return S;
10201 case 45:
10202 tmp = fieldFromInstruction(insn, 21, 5);
10203 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10204 tmp = fieldFromInstruction(insn, 0, 16);
10205 if (!Check(S, decodeSImmOperand<16>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10206 return S;
10207 case 46:
10208 tmp = fieldFromInstruction(insn, 21, 5);
10209 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10210 tmp = fieldFromInstruction(insn, 16, 5);
10211 if (!Check(S, DecodeGPRC_NOR0RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10212 tmp = fieldFromInstruction(insn, 0, 16);
10213 if (!Check(S, decodeSImmOperand<16>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10214 return S;
10215 case 47:
10216 tmp = fieldFromInstruction(insn, 2, 14);
10217 if (!Check(S, decodeCondBrTarget(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10218 return S;
10219 case 48:
10220 tmp = fieldFromInstruction(insn, 21, 5);
10221 if (!Check(S, decodeUImmOperand<5>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10222 tmp = fieldFromInstruction(insn, 16, 5);
10223 if (!Check(S, DecodeCRBITRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10224 tmp = fieldFromInstruction(insn, 2, 14);
10225 if (!Check(S, decodeCondBrTarget(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10226 return S;
10227 case 49:
10228 tmp = fieldFromInstruction(insn, 5, 7);
10229 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
10230 return S;
10231 case 50:
10232 tmp = fieldFromInstruction(insn, 2, 24);
10233 if (!Check(S, decodeDirectBrTarget(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10234 return S;
10235 case 51:
10236 tmp = fieldFromInstruction(insn, 23, 3);
10237 if (!Check(S, DecodeCRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10238 tmp = fieldFromInstruction(insn, 18, 3);
10239 if (!Check(S, DecodeCRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10240 return S;
10241 case 52:
10242 tmp = fieldFromInstruction(insn, 21, 5);
10243 if (!Check(S, DecodeCRBITRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10244 tmp = fieldFromInstruction(insn, 16, 5);
10245 if (!Check(S, DecodeCRBITRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10246 tmp = fieldFromInstruction(insn, 11, 5);
10247 if (!Check(S, DecodeCRBITRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10248 return S;
10249 case 53:
10250 tmp = fieldFromInstruction(insn, 21, 5);
10251 if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10252 tmp = 0x0;
10253 tmp |= fieldFromInstruction(insn, 0, 1);
10254 tmp |= fieldFromInstruction(insn, 6, 10) << 6;
10255 tmp |= fieldFromInstruction(insn, 16, 5) << 1;
10256 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
10257 return S;
10258 case 54:
10259 tmp = fieldFromInstruction(insn, 21, 5);
10260 if (!Check(S, decodeUImmOperand<5>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10261 tmp = fieldFromInstruction(insn, 16, 5);
10262 if (!Check(S, DecodeCRBITRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10263 tmp = fieldFromInstruction(insn, 11, 2);
10264 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
10265 return S;
10266 case 55:
10267 tmp = fieldFromInstruction(insn, 11, 1);
10268 if (!Check(S, decodeUImmOperand<1>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10269 return S;
10270 case 56:
10271 tmp = fieldFromInstruction(insn, 16, 5);
10272 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10273 tmp = fieldFromInstruction(insn, 16, 5);
10274 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10275 tmp = fieldFromInstruction(insn, 21, 5);
10276 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10277 tmp = fieldFromInstruction(insn, 11, 5);
10278 if (!Check(S, decodeUImmOperand<5>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10279 tmp = fieldFromInstruction(insn, 6, 5);
10280 if (!Check(S, decodeUImmOperand<5>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10281 tmp = fieldFromInstruction(insn, 1, 5);
10282 if (!Check(S, decodeUImmOperand<5>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10283 return S;
10284 case 57:
10285 tmp = fieldFromInstruction(insn, 16, 5);
10286 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10287 tmp = fieldFromInstruction(insn, 21, 5);
10288 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10289 tmp = fieldFromInstruction(insn, 11, 5);
10290 if (!Check(S, decodeUImmOperand<5>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10291 tmp = fieldFromInstruction(insn, 6, 5);
10292 if (!Check(S, decodeUImmOperand<5>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10293 tmp = fieldFromInstruction(insn, 1, 5);
10294 if (!Check(S, decodeUImmOperand<5>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10295 return S;
10296 case 58:
10297 tmp = fieldFromInstruction(insn, 16, 5);
10298 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10299 tmp = fieldFromInstruction(insn, 21, 5);
10300 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10301 tmp = fieldFromInstruction(insn, 11, 5);
10302 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10303 tmp = fieldFromInstruction(insn, 6, 5);
10304 if (!Check(S, decodeUImmOperand<5>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10305 tmp = fieldFromInstruction(insn, 1, 5);
10306 if (!Check(S, decodeUImmOperand<5>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10307 return S;
10308 case 59:
10309 tmp = fieldFromInstruction(insn, 16, 5);
10310 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10311 tmp = fieldFromInstruction(insn, 21, 5);
10312 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10313 tmp = fieldFromInstruction(insn, 0, 16);
10314 if (!Check(S, decodeUImmOperand<16>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10315 return S;
10316 case 60:
10317 tmp = fieldFromInstruction(insn, 16, 5);
10318 if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10319 tmp = fieldFromInstruction(insn, 21, 5);
10320 if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10321 tmp = 0x0;
10322 tmp |= fieldFromInstruction(insn, 1, 1) << 5;
10323 tmp |= fieldFromInstruction(insn, 11, 5);
10324 if (!Check(S, decodeUImmOperand<6>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10325 tmp = 0x0;
10326 tmp |= fieldFromInstruction(insn, 5, 1) << 5;
10327 tmp |= fieldFromInstruction(insn, 6, 5);
10328 if (!Check(S, decodeUImmOperand<6>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10329 return S;
10330 case 61:
10331 tmp = fieldFromInstruction(insn, 16, 5);
10332 if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10333 tmp = fieldFromInstruction(insn, 16, 5);
10334 if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10335 tmp = fieldFromInstruction(insn, 21, 5);
10336 if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10337 tmp = 0x0;
10338 tmp |= fieldFromInstruction(insn, 1, 1) << 5;
10339 tmp |= fieldFromInstruction(insn, 11, 5);
10340 if (!Check(S, decodeUImmOperand<6>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10341 tmp = 0x0;
10342 tmp |= fieldFromInstruction(insn, 5, 1) << 5;
10343 tmp |= fieldFromInstruction(insn, 6, 5);
10344 if (!Check(S, decodeUImmOperand<6>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10345 return S;
10346 case 62:
10347 tmp = fieldFromInstruction(insn, 16, 5);
10348 if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10349 tmp = fieldFromInstruction(insn, 21, 5);
10350 if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10351 tmp = fieldFromInstruction(insn, 11, 5);
10352 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10353 tmp = 0x0;
10354 tmp |= fieldFromInstruction(insn, 5, 1) << 5;
10355 tmp |= fieldFromInstruction(insn, 6, 5);
10356 if (!Check(S, decodeUImmOperand<6>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10357 return S;
10358 case 63:
10359 tmp = fieldFromInstruction(insn, 23, 3);
10360 if (!Check(S, DecodeCRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10361 tmp = fieldFromInstruction(insn, 16, 5);
10362 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10363 tmp = fieldFromInstruction(insn, 11, 5);
10364 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10365 return S;
10366 case 64:
10367 tmp = fieldFromInstruction(insn, 23, 3);
10368 if (!Check(S, DecodeCRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10369 tmp = fieldFromInstruction(insn, 16, 5);
10370 if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10371 tmp = fieldFromInstruction(insn, 11, 5);
10372 if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10373 return S;
10374 case 65:
10375 tmp = fieldFromInstruction(insn, 21, 5);
10376 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10377 tmp = fieldFromInstruction(insn, 18, 3);
10378 if (!Check(S, DecodeCRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10379 return S;
10380 case 66:
10381 tmp = fieldFromInstruction(insn, 23, 3);
10382 if (!Check(S, DecodeCRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10383 tmp = fieldFromInstruction(insn, 21, 1);
10384 if (!Check(S, decodeUImmOperand<1>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10385 tmp = fieldFromInstruction(insn, 16, 5);
10386 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10387 tmp = fieldFromInstruction(insn, 11, 5);
10388 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10389 return S;
10390 case 67:
10391 tmp = fieldFromInstruction(insn, 21, 5);
10392 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10393 tmp = fieldFromInstruction(insn, 16, 5);
10394 if (!Check(S, DecodeCRBITRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10395 return S;
10396 case 68:
10397 tmp = fieldFromInstruction(insn, 23, 3);
10398 if (!Check(S, DecodeCRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10399 return S;
10400 case 69:
10401 tmp = fieldFromInstruction(insn, 21, 5);
10402 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10403 return S;
10404 case 70:
10405 tmp = fieldFromInstruction(insn, 15, 1);
10406 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
10407 return S;
10408 case 71:
10409 tmp = fieldFromInstruction(insn, 21, 5);
10410 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10411 tmp = 0x0;
10412 tmp |= fieldFromInstruction(insn, 11, 5) << 5;
10413 tmp |= fieldFromInstruction(insn, 16, 5);
10414 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
10415 return S;
10416 case 72:
10417 tmp = fieldFromInstruction(insn, 21, 5);
10418 if (!Check(S, decodeUImmOperand<5>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10419 tmp = fieldFromInstruction(insn, 16, 5);
10420 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10421 tmp = fieldFromInstruction(insn, 11, 5);
10422 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10423 return S;
10424 case 73:
10425 tmp = fieldFromInstruction(insn, 21, 5);
10426 if (!Check(S, decodeUImmOperand<5>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10427 tmp = fieldFromInstruction(insn, 16, 5);
10428 if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10429 tmp = fieldFromInstruction(insn, 11, 5);
10430 if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10431 return S;
10432 case 74:
10433 tmp = fieldFromInstruction(insn, 21, 5);
10434 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10435 tmp = fieldFromInstruction(insn, 16, 5);
10436 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10437 tmp = fieldFromInstruction(insn, 11, 5);
10438 if (!Check(S, Decodeptr_rc_idx_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10439 return S;
10440 case 75:
10441 tmp = fieldFromInstruction(insn, 21, 4);
10442 if (!Check(S, decodeUImmOperand<4>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10443 tmp = fieldFromInstruction(insn, 16, 5);
10444 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10445 tmp = fieldFromInstruction(insn, 11, 5);
10446 if (!Check(S, Decodeptr_rc_idx_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10447 return S;
10448 case 76:
10449 tmp = fieldFromInstruction(insn, 16, 5);
10450 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10451 tmp = fieldFromInstruction(insn, 11, 5);
10452 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10453 return S;
10454 case 77:
10455 tmp = fieldFromInstruction(insn, 21, 5);
10456 if (!Check(S, DecodeG8pRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10457 tmp = fieldFromInstruction(insn, 21, 5);
10458 if (!Check(S, DecodeG8pRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10459 tmp = fieldFromInstruction(insn, 16, 5);
10460 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10461 tmp = fieldFromInstruction(insn, 11, 5);
10462 if (!Check(S, decodeUImmOperand<5>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10463 return S;
10464 case 78:
10465 tmp = fieldFromInstruction(insn, 21, 5);
10466 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10467 tmp = fieldFromInstruction(insn, 16, 5);
10468 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10469 tmp = fieldFromInstruction(insn, 11, 5);
10470 if (!Check(S, decodeUImmOperand<5>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10471 return S;
10472 case 79:
10473 tmp = fieldFromInstruction(insn, 21, 5);
10474 if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10475 tmp = fieldFromInstruction(insn, 16, 5);
10476 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10477 tmp = fieldFromInstruction(insn, 11, 5);
10478 if (!Check(S, decodeUImmOperand<5>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10479 return S;
10480 case 80:
10481 tmp = fieldFromInstruction(insn, 16, 5);
10482 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10483 tmp = fieldFromInstruction(insn, 11, 5);
10484 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10485 tmp = fieldFromInstruction(insn, 21, 1);
10486 if (!Check(S, decodeUImmOperand<1>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10487 return S;
10488 case 81:
10489 tmp = fieldFromInstruction(insn, 21, 5);
10490 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10491 tmp = fieldFromInstruction(insn, 16, 5);
10492 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10493 tmp = fieldFromInstruction(insn, 11, 5);
10494 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10495 return S;
10496 case 82:
10497 tmp = fieldFromInstruction(insn, 21, 5);
10498 if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10499 tmp = fieldFromInstruction(insn, 16, 5);
10500 if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10501 tmp = fieldFromInstruction(insn, 11, 5);
10502 if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10503 return S;
10504 case 83:
10505 tmp = fieldFromInstruction(insn, 21, 5);
10506 if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10507 tmp = fieldFromInstruction(insn, 16, 5);
10508 if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10509 tmp = fieldFromInstruction(insn, 11, 5);
10510 if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10511 tmp = fieldFromInstruction(insn, 10, 1);
10512 if (!Check(S, decodeUImmOperand<1>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10513 return S;
10514 case 84:
10515 tmp = fieldFromInstruction(insn, 21, 5);
10516 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10517 tmp = fieldFromInstruction(insn, 16, 5);
10518 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10519 return S;
10520 case 85:
10521 tmp = fieldFromInstruction(insn, 21, 5);
10522 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10523 tmp = fieldFromInstruction(insn, 16, 5);
10524 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10525 tmp = fieldFromInstruction(insn, 11, 5);
10526 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10527 tmp = fieldFromInstruction(insn, 9, 2);
10528 if (!Check(S, decodeUImmOperand<2>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10529 return S;
10530 case 86:
10531 tmp = 0x0;
10532 tmp |= fieldFromInstruction(insn, 0, 1) << 5;
10533 tmp |= fieldFromInstruction(insn, 21, 5);
10534 if (!Check(S, DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10535 tmp = fieldFromInstruction(insn, 16, 5);
10536 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10537 tmp = fieldFromInstruction(insn, 11, 5);
10538 if (!Check(S, Decodeptr_rc_idx_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10539 return S;
10540 case 87:
10541 tmp = 0x0;
10542 tmp |= fieldFromInstruction(insn, 0, 1) << 5;
10543 tmp |= fieldFromInstruction(insn, 21, 5);
10544 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10545 tmp = fieldFromInstruction(insn, 16, 5);
10546 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10547 tmp = fieldFromInstruction(insn, 11, 5);
10548 if (!Check(S, Decodeptr_rc_idx_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10549 return S;
10550 case 88:
10551 tmp = 0x0;
10552 tmp |= fieldFromInstruction(insn, 0, 1) << 5;
10553 tmp |= fieldFromInstruction(insn, 21, 5);
10554 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10555 tmp = fieldFromInstruction(insn, 16, 5);
10556 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10557 tmp = fieldFromInstruction(insn, 11, 5);
10558 if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10559 return S;
10560 case 89:
10561 tmp = 0x0;
10562 tmp |= fieldFromInstruction(insn, 21, 1) << 4;
10563 tmp |= fieldFromInstruction(insn, 22, 4);
10564 if (!Check(S, DecodeVSRpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10565 tmp = fieldFromInstruction(insn, 16, 5);
10566 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10567 tmp = fieldFromInstruction(insn, 11, 5);
10568 if (!Check(S, Decodeptr_rc_idx_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10569 return S;
10570 case 90:
10571 tmp = 0x0;
10572 tmp |= fieldFromInstruction(insn, 0, 1) << 5;
10573 tmp |= fieldFromInstruction(insn, 21, 5);
10574 if (!Check(S, DecodeVSSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10575 tmp = fieldFromInstruction(insn, 16, 5);
10576 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10577 tmp = fieldFromInstruction(insn, 11, 5);
10578 if (!Check(S, Decodeptr_rc_idx_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10579 return S;
10580 case 91:
10581 tmp = 0x0;
10582 tmp |= fieldFromInstruction(insn, 21, 1) << 4;
10583 tmp |= fieldFromInstruction(insn, 22, 4);
10584 if (!Check(S, DecodeVSRpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10585 tmp = fieldFromInstruction(insn, 16, 5);
10586 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10587 tmp = fieldFromInstruction(insn, 11, 5);
10588 if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10589 return S;
10590 case 92:
10591 tmp = fieldFromInstruction(insn, 11, 5);
10592 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10593 return S;
10594 case 93:
10595 tmp = fieldFromInstruction(insn, 21, 5);
10596 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10597 tmp = fieldFromInstruction(insn, 11, 10);
10598 if (!Check(S, decodeUImmOperand<10>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10599 return S;
10600 case 94:
10601 tmp = 0x0;
10602 tmp |= fieldFromInstruction(insn, 11, 5) << 5;
10603 tmp |= fieldFromInstruction(insn, 16, 5);
10604 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
10605 tmp = fieldFromInstruction(insn, 21, 5);
10606 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10607 return S;
10608 case 95:
10609 tmp = fieldFromInstruction(insn, 21, 1);
10610 if (!Check(S, decodeUImmOperand<1>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10611 return S;
10612 case 96:
10613 tmp = fieldFromInstruction(insn, 25, 1);
10614 if (!Check(S, decodeUImmOperand<1>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10615 return S;
10616 case 97:
10617 tmp = fieldFromInstruction(insn, 21, 5);
10618 if (!Check(S, decodeUImmOperand<5>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10619 tmp = fieldFromInstruction(insn, 16, 5);
10620 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10621 tmp = fieldFromInstruction(insn, 11, 5);
10622 if (!Check(S, decodeUImmOperand<5>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10623 return S;
10624 case 98:
10625 tmp = fieldFromInstruction(insn, 16, 5);
10626 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10627 return S;
10628 case 99:
10629 tmp = fieldFromInstruction(insn, 21, 5);
10630 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10631 tmp = fieldFromInstruction(insn, 16, 5);
10632 if (!Check(S, DecodeGPRC_NOR0RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10633 tmp = fieldFromInstruction(insn, 11, 5);
10634 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10635 tmp = fieldFromInstruction(insn, 6, 5);
10636 if (!Check(S, DecodeCRBITRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10637 return S;
10638 case 100:
10639 tmp = fieldFromInstruction(insn, 12, 8);
10640 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
10641 tmp = fieldFromInstruction(insn, 21, 5);
10642 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10643 return S;
10644 case 101:
10645 tmp = fieldFromInstruction(insn, 12, 8);
10646 if (!Check(S, decodeCRBitMOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10647 tmp = fieldFromInstruction(insn, 21, 5);
10648 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10649 return S;
10650 case 102:
10651 tmp = fieldFromInstruction(insn, 23, 3);
10652 if (!Check(S, DecodeACCRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10653 tmp = fieldFromInstruction(insn, 23, 3);
10654 if (!Check(S, DecodeACCRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10655 return S;
10656 case 103:
10657 tmp = fieldFromInstruction(insn, 23, 3);
10658 if (!Check(S, DecodeDMRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10659 return S;
10660 case 104:
10661 tmp = fieldFromInstruction(insn, 23, 3);
10662 if (!Check(S, DecodeACCRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10663 return S;
10664 case 105:
10665 tmp = fieldFromInstruction(insn, 23, 3);
10666 if (!Check(S, DecodeDMRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10667 tmp = fieldFromInstruction(insn, 13, 3);
10668 if (!Check(S, DecodeDMRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10669 return S;
10670 case 106:
10671 tmp = fieldFromInstruction(insn, 23, 3);
10672 if (!Check(S, DecodeDMRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10673 tmp = fieldFromInstruction(insn, 23, 3);
10674 if (!Check(S, DecodeDMRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10675 tmp = fieldFromInstruction(insn, 13, 3);
10676 if (!Check(S, DecodeDMRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10677 return S;
10678 case 107:
10679 tmp = fieldFromInstruction(insn, 23, 3);
10680 if (!Check(S, DecodeDMRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10681 tmp = fieldFromInstruction(insn, 23, 3);
10682 if (!Check(S, DecodeDMRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10683 tmp = fieldFromInstruction(insn, 13, 3);
10684 if (!Check(S, DecodeDMRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10685 tmp = fieldFromInstruction(insn, 21, 1);
10686 if (!Check(S, decodeUImmOperand<1>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10687 return S;
10688 case 108:
10689 tmp = fieldFromInstruction(insn, 24, 2);
10690 if (!Check(S, DecodeDMRpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10691 tmp = fieldFromInstruction(insn, 24, 2);
10692 if (!Check(S, DecodeDMRpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10693 tmp = fieldFromInstruction(insn, 11, 5);
10694 if (!Check(S, decodeUImmOperand<5>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10695 return S;
10696 case 109:
10697 tmp = fieldFromInstruction(insn, 11, 5);
10698 if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10699 tmp = fieldFromInstruction(insn, 21, 5);
10700 if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10701 tmp = fieldFromInstruction(insn, 18, 2);
10702 if (!Check(S, decodeUImmOperand<2>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10703 return S;
10704 case 110:
10705 tmp = fieldFromInstruction(insn, 21, 5);
10706 if (!Check(S, decodeUImmOperand<2>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10707 tmp = fieldFromInstruction(insn, 16, 5);
10708 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10709 tmp = fieldFromInstruction(insn, 11, 5);
10710 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10711 return S;
10712 case 111:
10713 tmp = fieldFromInstruction(insn, 21, 5);
10714 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10715 tmp = fieldFromInstruction(insn, 12, 8);
10716 if (!Check(S, decodeCRBitMOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10717 return S;
10718 case 112:
10719 tmp = fieldFromInstruction(insn, 11, 5);
10720 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10721 tmp = fieldFromInstruction(insn, 21, 5);
10722 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10723 tmp = fieldFromInstruction(insn, 18, 2);
10724 if (!Check(S, decodeUImmOperand<2>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10725 tmp = fieldFromInstruction(insn, 17, 1);
10726 if (!Check(S, decodeUImmOperand<1>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10727 tmp = fieldFromInstruction(insn, 16, 1);
10728 if (!Check(S, decodeUImmOperand<1>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10729 return S;
10730 case 113:
10731 tmp = fieldFromInstruction(insn, 16, 5);
10732 if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10733 tmp = 0x0;
10734 tmp |= fieldFromInstruction(insn, 0, 1) << 5;
10735 tmp |= fieldFromInstruction(insn, 21, 5);
10736 if (!Check(S, DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10737 return S;
10738 case 114:
10739 tmp = fieldFromInstruction(insn, 16, 5);
10740 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10741 tmp = 0x0;
10742 tmp |= fieldFromInstruction(insn, 0, 1) << 5;
10743 tmp |= fieldFromInstruction(insn, 21, 5);
10744 if (!Check(S, DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10745 return S;
10746 case 115:
10747 tmp = fieldFromInstruction(insn, 21, 5);
10748 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10749 tmp = fieldFromInstruction(insn, 16, 1);
10750 if (!Check(S, decodeUImmOperand<1>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10751 return S;
10752 case 116:
10753 tmp = 0x0;
10754 tmp |= fieldFromInstruction(insn, 0, 1) << 5;
10755 tmp |= fieldFromInstruction(insn, 21, 5);
10756 if (!Check(S, DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10757 tmp = fieldFromInstruction(insn, 16, 5);
10758 if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10759 return S;
10760 case 117:
10761 tmp = fieldFromInstruction(insn, 21, 5);
10762 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10763 tmp = fieldFromInstruction(insn, 16, 4);
10764 if (!Check(S, decodeUImmOperand<4>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10765 return S;
10766 case 118:
10767 tmp = 0x0;
10768 tmp |= fieldFromInstruction(insn, 0, 1) << 5;
10769 tmp |= fieldFromInstruction(insn, 21, 5);
10770 if (!Check(S, DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10771 tmp = fieldFromInstruction(insn, 16, 5);
10772 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10773 return S;
10774 case 119:
10775 tmp = fieldFromInstruction(insn, 21, 5);
10776 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10777 tmp = fieldFromInstruction(insn, 11, 5);
10778 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10779 return S;
10780 case 120:
10781 tmp = fieldFromInstruction(insn, 11, 5);
10782 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10783 tmp = fieldFromInstruction(insn, 21, 5);
10784 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10785 return S;
10786 case 121:
10787 tmp = fieldFromInstruction(insn, 16, 5);
10788 if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10789 tmp = 0x0;
10790 tmp |= fieldFromInstruction(insn, 0, 1) << 5;
10791 tmp |= fieldFromInstruction(insn, 21, 5);
10792 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10793 return S;
10794 case 122:
10795 tmp = 0x0;
10796 tmp |= fieldFromInstruction(insn, 0, 1) << 5;
10797 tmp |= fieldFromInstruction(insn, 21, 5);
10798 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10799 tmp = fieldFromInstruction(insn, 16, 5);
10800 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10801 return S;
10802 case 123:
10803 tmp = 0x0;
10804 tmp |= fieldFromInstruction(insn, 0, 1) << 5;
10805 tmp |= fieldFromInstruction(insn, 21, 5);
10806 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10807 tmp = fieldFromInstruction(insn, 16, 5);
10808 if (!Check(S, DecodeG8RC_NOX0RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10809 tmp = fieldFromInstruction(insn, 11, 5);
10810 if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10811 return S;
10812 case 124:
10813 tmp = fieldFromInstruction(insn, 11, 5);
10814 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10815 tmp = 0x0;
10816 tmp |= fieldFromInstruction(insn, 0, 1) << 5;
10817 tmp |= fieldFromInstruction(insn, 21, 5);
10818 if (!Check(S, decodeDispRIHashOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10819 tmp = fieldFromInstruction(insn, 16, 5);
10820 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10821 return S;
10822 case 125:
10823 tmp = fieldFromInstruction(insn, 21, 5);
10824 if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10825 tmp = fieldFromInstruction(insn, 16, 2);
10826 if (!Check(S, decodeUImmOperand<2>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10827 return S;
10828 case 126:
10829 tmp = fieldFromInstruction(insn, 21, 5);
10830 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10831 tmp = fieldFromInstruction(insn, 16, 5);
10832 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10833 tmp = fieldFromInstruction(insn, 11, 1);
10834 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
10835 return S;
10836 case 127:
10837 tmp = fieldFromInstruction(insn, 21, 5);
10838 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10839 tmp = fieldFromInstruction(insn, 16, 5);
10840 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10841 tmp = fieldFromInstruction(insn, 11, 5);
10842 if (!Check(S, Decodeptr_rc_idx_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10843 return S;
10844 case 128:
10845 tmp = fieldFromInstruction(insn, 21, 5);
10846 if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10847 tmp = fieldFromInstruction(insn, 16, 5);
10848 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10849 tmp = fieldFromInstruction(insn, 11, 5);
10850 if (!Check(S, Decodeptr_rc_idx_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10851 return S;
10852 case 129:
10853 tmp = fieldFromInstruction(insn, 21, 5);
10854 if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10855 tmp = fieldFromInstruction(insn, 16, 5);
10856 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10857 tmp = fieldFromInstruction(insn, 16, 5);
10858 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10859 tmp = fieldFromInstruction(insn, 11, 5);
10860 if (!Check(S, Decodeptr_rc_idx_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10861 return S;
10862 case 130:
10863 tmp = fieldFromInstruction(insn, 16, 5);
10864 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10865 tmp = fieldFromInstruction(insn, 21, 5);
10866 if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10867 tmp = fieldFromInstruction(insn, 16, 5);
10868 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10869 tmp = fieldFromInstruction(insn, 11, 5);
10870 if (!Check(S, Decodeptr_rc_idx_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10871 return S;
10872 case 131:
10873 tmp = fieldFromInstruction(insn, 21, 5);
10874 if (!Check(S, DecodeG8pRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10875 tmp = fieldFromInstruction(insn, 16, 5);
10876 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10877 tmp = fieldFromInstruction(insn, 11, 5);
10878 if (!Check(S, Decodeptr_rc_idx_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10879 return S;
10880 case 132:
10881 tmp = fieldFromInstruction(insn, 21, 5);
10882 if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10883 return S;
10884 case 133:
10885 tmp = fieldFromInstruction(insn, 21, 5);
10886 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10887 tmp = fieldFromInstruction(insn, 16, 5);
10888 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10889 tmp = fieldFromInstruction(insn, 11, 5);
10890 if (!Check(S, decodeUImmOperand<5>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10891 return S;
10892 case 134:
10893 tmp = fieldFromInstruction(insn, 16, 5);
10894 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10895 tmp = fieldFromInstruction(insn, 11, 5);
10896 if (!Check(S, Decodeptr_rc_idx_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10897 return S;
10898 case 135:
10899 tmp = fieldFromInstruction(insn, 21, 5);
10900 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10901 tmp = fieldFromInstruction(insn, 16, 5);
10902 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10903 tmp = fieldFromInstruction(insn, 16, 5);
10904 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10905 tmp = fieldFromInstruction(insn, 11, 5);
10906 if (!Check(S, Decodeptr_rc_idx_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10907 return S;
10908 case 136:
10909 tmp = fieldFromInstruction(insn, 21, 5);
10910 if (!Check(S, decodeUImmOperand<3>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10911 tmp = fieldFromInstruction(insn, 16, 5);
10912 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10913 tmp = fieldFromInstruction(insn, 11, 5);
10914 if (!Check(S, Decodeptr_rc_idx_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10915 return S;
10916 case 137:
10917 tmp = fieldFromInstruction(insn, 16, 5);
10918 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10919 tmp = fieldFromInstruction(insn, 21, 5);
10920 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10921 tmp = fieldFromInstruction(insn, 16, 5);
10922 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10923 tmp = fieldFromInstruction(insn, 11, 5);
10924 if (!Check(S, Decodeptr_rc_idx_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10925 return S;
10926 case 138:
10927 tmp = fieldFromInstruction(insn, 21, 5);
10928 if (!Check(S, decodeUImmOperand<5>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10929 tmp = fieldFromInstruction(insn, 16, 5);
10930 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10931 tmp = fieldFromInstruction(insn, 11, 5);
10932 if (!Check(S, Decodeptr_rc_idx_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10933 return S;
10934 case 139:
10935 tmp = fieldFromInstruction(insn, 21, 2);
10936 if (!Check(S, decodeUImmOperand<5>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10937 tmp = fieldFromInstruction(insn, 16, 5);
10938 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10939 tmp = fieldFromInstruction(insn, 11, 5);
10940 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10941 return S;
10942 case 140:
10943 tmp = fieldFromInstruction(insn, 21, 5);
10944 if (!Check(S, DecodeF4RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10945 tmp = fieldFromInstruction(insn, 16, 5);
10946 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10947 tmp = fieldFromInstruction(insn, 11, 5);
10948 if (!Check(S, Decodeptr_rc_idx_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10949 return S;
10950 case 141:
10951 tmp = fieldFromInstruction(insn, 21, 5);
10952 if (!Check(S, DecodeF4RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10953 tmp = fieldFromInstruction(insn, 16, 5);
10954 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10955 tmp = fieldFromInstruction(insn, 16, 5);
10956 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10957 tmp = fieldFromInstruction(insn, 11, 5);
10958 if (!Check(S, Decodeptr_rc_idx_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10959 return S;
10960 case 142:
10961 tmp = fieldFromInstruction(insn, 21, 2);
10962 if (!Check(S, decodeUImmOperand<2>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10963 return S;
10964 case 143:
10965 tmp = fieldFromInstruction(insn, 21, 3);
10966 if (!Check(S, decodeUImmOperand<3>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10967 tmp = fieldFromInstruction(insn, 16, 2);
10968 if (!Check(S, decodeUImmOperand<2>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10969 return S;
10970 case 144:
10971 tmp = fieldFromInstruction(insn, 21, 5);
10972 if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10973 tmp = fieldFromInstruction(insn, 16, 5);
10974 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10975 tmp = fieldFromInstruction(insn, 11, 5);
10976 if (!Check(S, Decodeptr_rc_idx_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10977 return S;
10978 case 145:
10979 tmp = fieldFromInstruction(insn, 21, 5);
10980 if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10981 tmp = fieldFromInstruction(insn, 16, 5);
10982 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10983 tmp = fieldFromInstruction(insn, 16, 5);
10984 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10985 tmp = fieldFromInstruction(insn, 11, 5);
10986 if (!Check(S, Decodeptr_rc_idx_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10987 return S;
10988 case 146:
10989 tmp = fieldFromInstruction(insn, 16, 5);
10990 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10991 tmp = fieldFromInstruction(insn, 21, 5);
10992 if (!Check(S, DecodeF4RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10993 tmp = fieldFromInstruction(insn, 16, 5);
10994 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10995 tmp = fieldFromInstruction(insn, 11, 5);
10996 if (!Check(S, Decodeptr_rc_idx_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10997 return S;
10998 case 147:
10999 tmp = fieldFromInstruction(insn, 16, 5);
11000 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11001 tmp = fieldFromInstruction(insn, 21, 5);
11002 if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11003 tmp = fieldFromInstruction(insn, 16, 5);
11004 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11005 tmp = fieldFromInstruction(insn, 11, 5);
11006 if (!Check(S, Decodeptr_rc_idx_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11007 return S;
11008 case 148:
11009 tmp = fieldFromInstruction(insn, 21, 2);
11010 if (!Check(S, decodeUImmOperand<5>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11011 return S;
11012 case 149:
11013 tmp = fieldFromInstruction(insn, 21, 5);
11014 if (!Check(S, decodeUImmOperand<5>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11015 return S;
11016 case 150:
11017 tmp = fieldFromInstruction(insn, 16, 5);
11018 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11019 tmp = fieldFromInstruction(insn, 21, 5);
11020 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11021 tmp = fieldFromInstruction(insn, 11, 5);
11022 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11023 return S;
11024 case 151:
11025 tmp = fieldFromInstruction(insn, 16, 5);
11026 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11027 tmp = fieldFromInstruction(insn, 21, 5);
11028 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11029 tmp = fieldFromInstruction(insn, 11, 5);
11030 if (!Check(S, decodeUImmOperand<5>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11031 return S;
11032 case 152:
11033 tmp = fieldFromInstruction(insn, 16, 5);
11034 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11035 tmp = fieldFromInstruction(insn, 21, 5);
11036 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11037 return S;
11038 case 153:
11039 tmp = fieldFromInstruction(insn, 16, 5);
11040 if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11041 tmp = fieldFromInstruction(insn, 21, 5);
11042 if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11043 tmp = fieldFromInstruction(insn, 11, 5);
11044 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11045 return S;
11046 case 154:
11047 tmp = fieldFromInstruction(insn, 16, 5);
11048 if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11049 tmp = fieldFromInstruction(insn, 21, 5);
11050 if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11051 return S;
11052 case 155:
11053 tmp = fieldFromInstruction(insn, 16, 5);
11054 if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11055 tmp = fieldFromInstruction(insn, 21, 5);
11056 if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11057 tmp = fieldFromInstruction(insn, 11, 5);
11058 if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11059 return S;
11060 case 156:
11061 tmp = fieldFromInstruction(insn, 16, 5);
11062 if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11063 tmp = fieldFromInstruction(insn, 21, 5);
11064 if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11065 tmp = 0x0;
11066 tmp |= fieldFromInstruction(insn, 1, 1) << 5;
11067 tmp |= fieldFromInstruction(insn, 11, 5);
11068 if (!Check(S, decodeUImmOperand<6>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11069 return S;
11070 case 157:
11071 tmp = fieldFromInstruction(insn, 21, 2);
11072 if (!Check(S, decodeUImmOperand<2>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11073 tmp = fieldFromInstruction(insn, 16, 2);
11074 if (!Check(S, decodeUImmOperand<2>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11075 return S;
11076 case 158:
11077 tmp = fieldFromInstruction(insn, 16, 5);
11078 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11079 tmp = fieldFromInstruction(insn, 11, 5);
11080 if (!Check(S, Decodeptr_rc_idx_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11081 tmp = fieldFromInstruction(insn, 21, 5);
11082 if (!Check(S, decodeUImmOperand<5>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11083 return S;
11084 case 159:
11085 tmp = fieldFromInstruction(insn, 21, 5);
11086 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11087 tmp = fieldFromInstruction(insn, 0, 16);
11088 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
11089 tmp = fieldFromInstruction(insn, 16, 5);
11090 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11091 return S;
11092 case 160:
11093 tmp = fieldFromInstruction(insn, 21, 5);
11094 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11095 tmp = fieldFromInstruction(insn, 16, 5);
11096 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11097 tmp = fieldFromInstruction(insn, 0, 16);
11098 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
11099 tmp = fieldFromInstruction(insn, 16, 5);
11100 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11101 return S;
11102 case 161:
11103 tmp = fieldFromInstruction(insn, 16, 5);
11104 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11105 tmp = fieldFromInstruction(insn, 21, 5);
11106 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11107 tmp = fieldFromInstruction(insn, 0, 16);
11108 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
11109 tmp = fieldFromInstruction(insn, 16, 5);
11110 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11111 return S;
11112 case 162:
11113 tmp = fieldFromInstruction(insn, 21, 5);
11114 if (!Check(S, DecodeF4RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11115 tmp = fieldFromInstruction(insn, 0, 16);
11116 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
11117 tmp = fieldFromInstruction(insn, 16, 5);
11118 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11119 return S;
11120 case 163:
11121 tmp = fieldFromInstruction(insn, 21, 5);
11122 if (!Check(S, DecodeF4RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11123 tmp = fieldFromInstruction(insn, 16, 5);
11124 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11125 tmp = fieldFromInstruction(insn, 0, 16);
11126 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
11127 tmp = fieldFromInstruction(insn, 16, 5);
11128 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11129 return S;
11130 case 164:
11131 tmp = fieldFromInstruction(insn, 21, 5);
11132 if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11133 tmp = fieldFromInstruction(insn, 0, 16);
11134 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
11135 tmp = fieldFromInstruction(insn, 16, 5);
11136 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11137 return S;
11138 case 165:
11139 tmp = fieldFromInstruction(insn, 21, 5);
11140 if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11141 tmp = fieldFromInstruction(insn, 16, 5);
11142 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11143 tmp = fieldFromInstruction(insn, 0, 16);
11144 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
11145 tmp = fieldFromInstruction(insn, 16, 5);
11146 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11147 return S;
11148 case 166:
11149 tmp = fieldFromInstruction(insn, 16, 5);
11150 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11151 tmp = fieldFromInstruction(insn, 21, 5);
11152 if (!Check(S, DecodeF4RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11153 tmp = fieldFromInstruction(insn, 0, 16);
11154 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
11155 tmp = fieldFromInstruction(insn, 16, 5);
11156 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11157 return S;
11158 case 167:
11159 tmp = fieldFromInstruction(insn, 16, 5);
11160 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11161 tmp = fieldFromInstruction(insn, 21, 5);
11162 if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11163 tmp = fieldFromInstruction(insn, 0, 16);
11164 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
11165 tmp = fieldFromInstruction(insn, 16, 5);
11166 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11167 return S;
11168 case 168:
11169 tmp = fieldFromInstruction(insn, 21, 5);
11170 if (!Check(S, DecodeG8pRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11171 tmp = fieldFromInstruction(insn, 4, 12);
11172 if (!Check(S, decodeDispRIX16Operand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11173 tmp = fieldFromInstruction(insn, 16, 5);
11174 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11175 return S;
11176 case 169:
11177 tmp = fieldFromInstruction(insn, 21, 5);
11178 if (!Check(S, DecodeVFRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11179 tmp = fieldFromInstruction(insn, 2, 14);
11180 if (!Check(S, decodeDispRIXOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11181 tmp = fieldFromInstruction(insn, 16, 5);
11182 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11183 return S;
11184 case 170:
11185 tmp = fieldFromInstruction(insn, 21, 5);
11186 if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11187 tmp = fieldFromInstruction(insn, 2, 14);
11188 if (!Check(S, decodeDispRIXOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11189 tmp = fieldFromInstruction(insn, 16, 5);
11190 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11191 return S;
11192 case 171:
11193 tmp = fieldFromInstruction(insn, 21, 5);
11194 if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11195 tmp = fieldFromInstruction(insn, 16, 5);
11196 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11197 tmp = fieldFromInstruction(insn, 2, 14);
11198 if (!Check(S, decodeDispRIXOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11199 tmp = fieldFromInstruction(insn, 16, 5);
11200 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11201 return S;
11202 case 172:
11203 tmp = fieldFromInstruction(insn, 21, 5);
11204 if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11205 tmp = fieldFromInstruction(insn, 16, 5);
11206 if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11207 tmp = fieldFromInstruction(insn, 11, 5);
11208 if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11209 return S;
11210 case 173:
11211 tmp = fieldFromInstruction(insn, 21, 5);
11212 if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11213 tmp = fieldFromInstruction(insn, 11, 5);
11214 if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11215 return S;
11216 case 174:
11217 tmp = fieldFromInstruction(insn, 21, 5);
11218 if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11219 tmp = fieldFromInstruction(insn, 16, 5);
11220 if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11221 tmp = fieldFromInstruction(insn, 11, 5);
11222 if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11223 tmp = fieldFromInstruction(insn, 9, 2);
11224 if (!Check(S, decodeUImmOperand<2>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11225 return S;
11226 case 175:
11227 tmp = fieldFromInstruction(insn, 21, 5);
11228 if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11229 tmp = fieldFromInstruction(insn, 16, 5);
11230 if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11231 tmp = fieldFromInstruction(insn, 10, 6);
11232 if (!Check(S, decodeUImmOperand<6>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11233 return S;
11234 case 176:
11235 tmp = fieldFromInstruction(insn, 21, 5);
11236 if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11237 tmp = fieldFromInstruction(insn, 19, 2);
11238 if (!Check(S, decodeUImmOperand<2>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11239 tmp = fieldFromInstruction(insn, 11, 5);
11240 if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11241 return S;
11242 case 177:
11243 tmp = fieldFromInstruction(insn, 21, 5);
11244 if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11245 tmp = fieldFromInstruction(insn, 20, 1);
11246 if (!Check(S, decodeUImmOperand<1>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11247 tmp = fieldFromInstruction(insn, 11, 5);
11248 if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11249 return S;
11250 case 178:
11251 tmp = fieldFromInstruction(insn, 21, 5);
11252 if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11253 tmp = fieldFromInstruction(insn, 16, 5);
11254 if (!Check(S, decodeSImmOperand<5>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11255 tmp = fieldFromInstruction(insn, 11, 5);
11256 if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11257 tmp = fieldFromInstruction(insn, 9, 2);
11258 if (!Check(S, decodeUImmOperand<2>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11259 return S;
11260 case 179:
11261 tmp = fieldFromInstruction(insn, 21, 5);
11262 if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11263 tmp = fieldFromInstruction(insn, 16, 1);
11264 if (!Check(S, decodeUImmOperand<1>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11265 tmp = fieldFromInstruction(insn, 11, 5);
11266 if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11267 tmp = fieldFromInstruction(insn, 9, 2);
11268 if (!Check(S, decodeUImmOperand<2>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11269 return S;
11270 case 180:
11271 tmp = fieldFromInstruction(insn, 23, 3);
11272 if (!Check(S, DecodeCRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11273 tmp = fieldFromInstruction(insn, 16, 5);
11274 if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11275 tmp = fieldFromInstruction(insn, 11, 5);
11276 if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11277 return S;
11278 case 181:
11279 tmp = 0x0;
11280 tmp |= fieldFromInstruction(insn, 0, 1) << 5;
11281 tmp |= fieldFromInstruction(insn, 21, 5);
11282 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11283 tmp = 0x0;
11284 tmp |= fieldFromInstruction(insn, 2, 1) << 5;
11285 tmp |= fieldFromInstruction(insn, 16, 5);
11286 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11287 tmp = 0x0;
11288 tmp |= fieldFromInstruction(insn, 1, 1) << 5;
11289 tmp |= fieldFromInstruction(insn, 11, 5);
11290 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11291 return S;
11292 case 182:
11293 tmp = fieldFromInstruction(insn, 23, 3);
11294 if (!Check(S, DecodeCRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11295 tmp = fieldFromInstruction(insn, 16, 6);
11296 if (!Check(S, decodeUImmOperand<6>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11297 tmp = fieldFromInstruction(insn, 11, 5);
11298 if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11299 return S;
11300 case 183:
11301 tmp = fieldFromInstruction(insn, 23, 3);
11302 if (!Check(S, DecodeCRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11303 tmp = fieldFromInstruction(insn, 16, 5);
11304 if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11305 tmp = fieldFromInstruction(insn, 10, 6);
11306 if (!Check(S, decodeUImmOperand<6>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11307 return S;
11308 case 184:
11309 tmp = 0x0;
11310 tmp |= fieldFromInstruction(insn, 0, 1) << 5;
11311 tmp |= fieldFromInstruction(insn, 21, 5);
11312 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11313 tmp = 0x0;
11314 tmp |= fieldFromInstruction(insn, 2, 1) << 5;
11315 tmp |= fieldFromInstruction(insn, 16, 5);
11316 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11317 tmp = 0x0;
11318 tmp |= fieldFromInstruction(insn, 1, 1) << 5;
11319 tmp |= fieldFromInstruction(insn, 11, 5);
11320 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11321 tmp = fieldFromInstruction(insn, 8, 3);
11322 if (!Check(S, decodeUImmOperand<3>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11323 return S;
11324 case 185:
11325 tmp = 0x0;
11326 tmp |= fieldFromInstruction(insn, 0, 1) << 5;
11327 tmp |= fieldFromInstruction(insn, 21, 5);
11328 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11329 tmp = 0x0;
11330 tmp |= fieldFromInstruction(insn, 2, 1) << 5;
11331 tmp |= fieldFromInstruction(insn, 16, 5);
11332 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11333 tmp = 0x0;
11334 tmp |= fieldFromInstruction(insn, 1, 1) << 5;
11335 tmp |= fieldFromInstruction(insn, 11, 5);
11336 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11337 tmp = fieldFromInstruction(insn, 10, 1);
11338 if (!Check(S, decodeUImmOperand<1>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11339 tmp = fieldFromInstruction(insn, 9, 1);
11340 if (!Check(S, decodeUImmOperand<1>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11341 tmp = fieldFromInstruction(insn, 8, 1);
11342 if (!Check(S, decodeUImmOperand<1>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11343 return S;
11344 case 186:
11345 tmp = 0x0;
11346 tmp |= fieldFromInstruction(insn, 0, 1) << 5;
11347 tmp |= fieldFromInstruction(insn, 21, 5);
11348 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11349 tmp = 0x0;
11350 tmp |= fieldFromInstruction(insn, 2, 1) << 5;
11351 tmp |= fieldFromInstruction(insn, 16, 5);
11352 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11353 tmp = 0x0;
11354 tmp |= fieldFromInstruction(insn, 1, 1) << 5;
11355 tmp |= fieldFromInstruction(insn, 11, 5);
11356 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11357 tmp = fieldFromInstruction(insn, 9, 1);
11358 if (!Check(S, decodeUImmOperand<1>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11359 tmp = fieldFromInstruction(insn, 8, 1);
11360 if (!Check(S, decodeUImmOperand<1>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11361 return S;
11362 case 187:
11363 tmp = 0x0;
11364 tmp |= fieldFromInstruction(insn, 0, 1) << 5;
11365 tmp |= fieldFromInstruction(insn, 21, 5);
11366 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11367 tmp = 0x0;
11368 tmp |= fieldFromInstruction(insn, 2, 1) << 5;
11369 tmp |= fieldFromInstruction(insn, 16, 5);
11370 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11371 tmp = 0x0;
11372 tmp |= fieldFromInstruction(insn, 1, 1) << 5;
11373 tmp |= fieldFromInstruction(insn, 11, 5);
11374 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11375 tmp = fieldFromInstruction(insn, 10, 1);
11376 if (!Check(S, decodeUImmOperand<1>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11377 return S;
11378 case 188:
11379 tmp = fieldFromInstruction(insn, 23, 3);
11380 if (!Check(S, DecodeACCRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11381 tmp = fieldFromInstruction(insn, 23, 3);
11382 if (!Check(S, DecodeACCRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11383 tmp = 0x0;
11384 tmp |= fieldFromInstruction(insn, 2, 1) << 5;
11385 tmp |= fieldFromInstruction(insn, 16, 5);
11386 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11387 tmp = 0x0;
11388 tmp |= fieldFromInstruction(insn, 1, 1) << 5;
11389 tmp |= fieldFromInstruction(insn, 11, 5);
11390 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11391 return S;
11392 case 189:
11393 tmp = fieldFromInstruction(insn, 23, 3);
11394 if (!Check(S, DecodeDMRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11395 tmp = fieldFromInstruction(insn, 23, 3);
11396 if (!Check(S, DecodeDMRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11397 tmp = 0x0;
11398 tmp |= fieldFromInstruction(insn, 2, 1) << 4;
11399 tmp |= fieldFromInstruction(insn, 17, 4);
11400 if (!Check(S, DecodeVSRpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11401 tmp = 0x0;
11402 tmp |= fieldFromInstruction(insn, 1, 1) << 5;
11403 tmp |= fieldFromInstruction(insn, 11, 5);
11404 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11405 return S;
11406 case 190:
11407 tmp = fieldFromInstruction(insn, 23, 3);
11408 if (!Check(S, DecodeACCRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11409 tmp = fieldFromInstruction(insn, 23, 3);
11410 if (!Check(S, DecodeACCRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11411 tmp = 0x0;
11412 tmp |= fieldFromInstruction(insn, 2, 1) << 5;
11413 tmp |= fieldFromInstruction(insn, 16, 5);
11414 if (!Check(S, decodeVSRpEvenOperands(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11415 tmp = 0x0;
11416 tmp |= fieldFromInstruction(insn, 1, 1) << 5;
11417 tmp |= fieldFromInstruction(insn, 11, 5);
11418 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11419 return S;
11420 case 191:
11421 tmp = fieldFromInstruction(insn, 23, 3);
11422 if (!Check(S, DecodeACCRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11423 tmp = 0x0;
11424 tmp |= fieldFromInstruction(insn, 2, 1) << 5;
11425 tmp |= fieldFromInstruction(insn, 16, 5);
11426 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11427 tmp = 0x0;
11428 tmp |= fieldFromInstruction(insn, 1, 1) << 5;
11429 tmp |= fieldFromInstruction(insn, 11, 5);
11430 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11431 return S;
11432 case 192:
11433 tmp = fieldFromInstruction(insn, 23, 3);
11434 if (!Check(S, DecodeDMRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11435 tmp = 0x0;
11436 tmp |= fieldFromInstruction(insn, 2, 1) << 4;
11437 tmp |= fieldFromInstruction(insn, 17, 4);
11438 if (!Check(S, DecodeVSRpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11439 tmp = 0x0;
11440 tmp |= fieldFromInstruction(insn, 1, 1) << 5;
11441 tmp |= fieldFromInstruction(insn, 11, 5);
11442 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11443 return S;
11444 case 193:
11445 tmp = fieldFromInstruction(insn, 23, 3);
11446 if (!Check(S, DecodeACCRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11447 tmp = 0x0;
11448 tmp |= fieldFromInstruction(insn, 2, 1) << 5;
11449 tmp |= fieldFromInstruction(insn, 16, 5);
11450 if (!Check(S, decodeVSRpEvenOperands(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11451 tmp = 0x0;
11452 tmp |= fieldFromInstruction(insn, 1, 1) << 5;
11453 tmp |= fieldFromInstruction(insn, 11, 5);
11454 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11455 return S;
11456 case 194:
11457 tmp = fieldFromInstruction(insn, 21, 5);
11458 if (!Check(S, DecodeF4RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11459 tmp = fieldFromInstruction(insn, 11, 5);
11460 if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11461 return S;
11462 case 195:
11463 tmp = fieldFromInstruction(insn, 21, 5);
11464 if (!Check(S, DecodeF4RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11465 tmp = fieldFromInstruction(insn, 16, 5);
11466 if (!Check(S, DecodeF4RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11467 tmp = fieldFromInstruction(insn, 11, 5);
11468 if (!Check(S, DecodeF4RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11469 return S;
11470 case 196:
11471 tmp = fieldFromInstruction(insn, 21, 5);
11472 if (!Check(S, DecodeF4RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11473 tmp = fieldFromInstruction(insn, 11, 5);
11474 if (!Check(S, DecodeF4RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11475 return S;
11476 case 197:
11477 tmp = fieldFromInstruction(insn, 21, 5);
11478 if (!Check(S, DecodeF4RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11479 tmp = fieldFromInstruction(insn, 16, 5);
11480 if (!Check(S, DecodeF4RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11481 tmp = fieldFromInstruction(insn, 6, 5);
11482 if (!Check(S, DecodeF4RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11483 return S;
11484 case 198:
11485 tmp = fieldFromInstruction(insn, 21, 5);
11486 if (!Check(S, DecodeF4RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11487 tmp = fieldFromInstruction(insn, 16, 5);
11488 if (!Check(S, DecodeF4RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11489 tmp = fieldFromInstruction(insn, 6, 5);
11490 if (!Check(S, DecodeF4RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11491 tmp = fieldFromInstruction(insn, 11, 5);
11492 if (!Check(S, DecodeF4RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11493 return S;
11494 case 199:
11495 tmp = 0x0;
11496 tmp |= fieldFromInstruction(insn, 0, 1) << 5;
11497 tmp |= fieldFromInstruction(insn, 21, 5);
11498 if (!Check(S, DecodeVSSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11499 tmp = 0x0;
11500 tmp |= fieldFromInstruction(insn, 2, 1) << 5;
11501 tmp |= fieldFromInstruction(insn, 16, 5);
11502 if (!Check(S, DecodeVSSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11503 tmp = 0x0;
11504 tmp |= fieldFromInstruction(insn, 1, 1) << 5;
11505 tmp |= fieldFromInstruction(insn, 11, 5);
11506 if (!Check(S, DecodeVSSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11507 return S;
11508 case 200:
11509 tmp = 0x0;
11510 tmp |= fieldFromInstruction(insn, 0, 1) << 5;
11511 tmp |= fieldFromInstruction(insn, 21, 5);
11512 if (!Check(S, DecodeVSSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11513 tmp = 0x0;
11514 tmp |= fieldFromInstruction(insn, 0, 1) << 5;
11515 tmp |= fieldFromInstruction(insn, 21, 5);
11516 if (!Check(S, DecodeVSSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11517 tmp = 0x0;
11518 tmp |= fieldFromInstruction(insn, 2, 1) << 5;
11519 tmp |= fieldFromInstruction(insn, 16, 5);
11520 if (!Check(S, DecodeVSSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11521 tmp = 0x0;
11522 tmp |= fieldFromInstruction(insn, 1, 1) << 5;
11523 tmp |= fieldFromInstruction(insn, 11, 5);
11524 if (!Check(S, DecodeVSSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11525 return S;
11526 case 201:
11527 tmp = 0x0;
11528 tmp |= fieldFromInstruction(insn, 0, 1) << 5;
11529 tmp |= fieldFromInstruction(insn, 21, 5);
11530 if (!Check(S, DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11531 tmp = 0x0;
11532 tmp |= fieldFromInstruction(insn, 2, 1) << 5;
11533 tmp |= fieldFromInstruction(insn, 16, 5);
11534 if (!Check(S, DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11535 tmp = 0x0;
11536 tmp |= fieldFromInstruction(insn, 1, 1) << 5;
11537 tmp |= fieldFromInstruction(insn, 11, 5);
11538 if (!Check(S, DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11539 return S;
11540 case 202:
11541 tmp = 0x0;
11542 tmp |= fieldFromInstruction(insn, 0, 1) << 5;
11543 tmp |= fieldFromInstruction(insn, 21, 5);
11544 if (!Check(S, DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11545 tmp = 0x0;
11546 tmp |= fieldFromInstruction(insn, 0, 1) << 5;
11547 tmp |= fieldFromInstruction(insn, 21, 5);
11548 if (!Check(S, DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11549 tmp = 0x0;
11550 tmp |= fieldFromInstruction(insn, 2, 1) << 5;
11551 tmp |= fieldFromInstruction(insn, 16, 5);
11552 if (!Check(S, DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11553 tmp = 0x0;
11554 tmp |= fieldFromInstruction(insn, 1, 1) << 5;
11555 tmp |= fieldFromInstruction(insn, 11, 5);
11556 if (!Check(S, DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11557 return S;
11558 case 203:
11559 tmp = 0x0;
11560 tmp |= fieldFromInstruction(insn, 0, 1) << 5;
11561 tmp |= fieldFromInstruction(insn, 21, 5);
11562 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11563 tmp = 0x0;
11564 tmp |= fieldFromInstruction(insn, 0, 1) << 5;
11565 tmp |= fieldFromInstruction(insn, 21, 5);
11566 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11567 tmp = 0x0;
11568 tmp |= fieldFromInstruction(insn, 2, 1) << 5;
11569 tmp |= fieldFromInstruction(insn, 16, 5);
11570 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11571 tmp = 0x0;
11572 tmp |= fieldFromInstruction(insn, 1, 1) << 5;
11573 tmp |= fieldFromInstruction(insn, 11, 5);
11574 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11575 return S;
11576 case 204:
11577 tmp = 0x0;
11578 tmp |= fieldFromInstruction(insn, 0, 1) << 5;
11579 tmp |= fieldFromInstruction(insn, 21, 5);
11580 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11581 tmp = 0x0;
11582 tmp |= fieldFromInstruction(insn, 2, 1) << 5;
11583 tmp |= fieldFromInstruction(insn, 16, 5);
11584 if (!Check(S, DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11585 tmp = 0x0;
11586 tmp |= fieldFromInstruction(insn, 1, 1) << 5;
11587 tmp |= fieldFromInstruction(insn, 11, 5);
11588 if (!Check(S, DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11589 return S;
11590 case 205:
11591 tmp = 0x0;
11592 tmp |= fieldFromInstruction(insn, 0, 1) << 5;
11593 tmp |= fieldFromInstruction(insn, 21, 5);
11594 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11595 tmp = 0x0;
11596 tmp |= fieldFromInstruction(insn, 2, 1) << 5;
11597 tmp |= fieldFromInstruction(insn, 16, 5);
11598 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11599 tmp = 0x0;
11600 tmp |= fieldFromInstruction(insn, 1, 1) << 5;
11601 tmp |= fieldFromInstruction(insn, 11, 5);
11602 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11603 tmp = fieldFromInstruction(insn, 8, 2);
11604 if (!Check(S, decodeUImmOperand<2>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11605 return S;
11606 case 206:
11607 tmp = 0x0;
11608 tmp |= fieldFromInstruction(insn, 21, 1) << 4;
11609 tmp |= fieldFromInstruction(insn, 22, 4);
11610 if (!Check(S, DecodeVSRpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11611 tmp = 0x0;
11612 tmp |= fieldFromInstruction(insn, 2, 1) << 4;
11613 tmp |= fieldFromInstruction(insn, 17, 4);
11614 if (!Check(S, DecodeVSRpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11615 tmp = 0x0;
11616 tmp |= fieldFromInstruction(insn, 1, 1) << 4;
11617 tmp |= fieldFromInstruction(insn, 12, 4);
11618 if (!Check(S, DecodeVSRpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11619 tmp = 0x0;
11620 tmp |= fieldFromInstruction(insn, 11, 1) << 1;
11621 tmp |= fieldFromInstruction(insn, 16, 1);
11622 if (!Check(S, decodeUImmOperand<2>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11623 return S;
11624 case 207:
11625 tmp = 0x0;
11626 tmp |= fieldFromInstruction(insn, 2, 1) << 4;
11627 tmp |= fieldFromInstruction(insn, 17, 4);
11628 if (!Check(S, DecodeVSRpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11629 tmp = 0x0;
11630 tmp |= fieldFromInstruction(insn, 1, 1) << 4;
11631 tmp |= fieldFromInstruction(insn, 12, 4);
11632 if (!Check(S, DecodeVSRpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11633 tmp = fieldFromInstruction(insn, 23, 3);
11634 if (!Check(S, DecodeWACCRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11635 return S;
11636 case 208:
11637 tmp = 0x0;
11638 tmp |= fieldFromInstruction(insn, 2, 1) << 4;
11639 tmp |= fieldFromInstruction(insn, 17, 4);
11640 if (!Check(S, DecodeVSRpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11641 tmp = 0x0;
11642 tmp |= fieldFromInstruction(insn, 1, 1) << 4;
11643 tmp |= fieldFromInstruction(insn, 12, 4);
11644 if (!Check(S, DecodeVSRpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11645 tmp = fieldFromInstruction(insn, 23, 3);
11646 if (!Check(S, DecodeWACC_HIRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11647 return S;
11648 case 209:
11649 tmp = fieldFromInstruction(insn, 23, 3);
11650 if (!Check(S, DecodeCRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11651 tmp = 0x0;
11652 tmp |= fieldFromInstruction(insn, 2, 1) << 5;
11653 tmp |= fieldFromInstruction(insn, 16, 5);
11654 if (!Check(S, DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11655 tmp = 0x0;
11656 tmp |= fieldFromInstruction(insn, 1, 1) << 5;
11657 tmp |= fieldFromInstruction(insn, 11, 5);
11658 if (!Check(S, DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11659 return S;
11660 case 210:
11661 tmp = fieldFromInstruction(insn, 23, 3);
11662 if (!Check(S, DecodeWACCRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11663 tmp = 0x0;
11664 tmp |= fieldFromInstruction(insn, 2, 1) << 4;
11665 tmp |= fieldFromInstruction(insn, 17, 4);
11666 if (!Check(S, DecodeVSRpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11667 tmp = 0x0;
11668 tmp |= fieldFromInstruction(insn, 1, 1) << 4;
11669 tmp |= fieldFromInstruction(insn, 12, 4);
11670 if (!Check(S, DecodeVSRpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11671 return S;
11672 case 211:
11673 tmp = fieldFromInstruction(insn, 23, 3);
11674 if (!Check(S, DecodeWACC_HIRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11675 tmp = 0x0;
11676 tmp |= fieldFromInstruction(insn, 2, 1) << 4;
11677 tmp |= fieldFromInstruction(insn, 17, 4);
11678 if (!Check(S, DecodeVSRpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11679 tmp = 0x0;
11680 tmp |= fieldFromInstruction(insn, 1, 1) << 4;
11681 tmp |= fieldFromInstruction(insn, 12, 4);
11682 if (!Check(S, DecodeVSRpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11683 return S;
11684 case 212:
11685 tmp = 0x0;
11686 tmp |= fieldFromInstruction(insn, 0, 1) << 5;
11687 tmp |= fieldFromInstruction(insn, 21, 5);
11688 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11689 tmp = 0x0;
11690 tmp |= fieldFromInstruction(insn, 1, 1) << 5;
11691 tmp |= fieldFromInstruction(insn, 11, 5);
11692 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11693 tmp = fieldFromInstruction(insn, 16, 2);
11694 if (!Check(S, decodeUImmOperand<2>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11695 return S;
11696 case 213:
11697 tmp = 0x0;
11698 tmp |= fieldFromInstruction(insn, 0, 1) << 5;
11699 tmp |= fieldFromInstruction(insn, 21, 5);
11700 if (!Check(S, DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11701 tmp = 0x0;
11702 tmp |= fieldFromInstruction(insn, 1, 1) << 5;
11703 tmp |= fieldFromInstruction(insn, 11, 5);
11704 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11705 tmp = fieldFromInstruction(insn, 16, 5);
11706 if (!Check(S, decodeUImmOperand<4>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11707 return S;
11708 case 214:
11709 tmp = 0x0;
11710 tmp |= fieldFromInstruction(insn, 21, 1) << 4;
11711 tmp |= fieldFromInstruction(insn, 22, 4);
11712 if (!Check(S, DecodeVSRpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11713 tmp = 0x0;
11714 tmp |= fieldFromInstruction(insn, 1, 1) << 4;
11715 tmp |= fieldFromInstruction(insn, 12, 4);
11716 if (!Check(S, DecodeVSRpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11717 tmp = 0x0;
11718 tmp |= fieldFromInstruction(insn, 11, 1) << 1;
11719 tmp |= fieldFromInstruction(insn, 16, 1);
11720 if (!Check(S, decodeUImmOperand<2>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11721 return S;
11722 case 215:
11723 tmp = fieldFromInstruction(insn, 23, 3);
11724 if (!Check(S, DecodeDMRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11725 tmp = fieldFromInstruction(insn, 23, 3);
11726 if (!Check(S, DecodeDMRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11727 tmp = 0x0;
11728 tmp |= fieldFromInstruction(insn, 1, 1) << 5;
11729 tmp |= fieldFromInstruction(insn, 11, 5);
11730 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11731 tmp = fieldFromInstruction(insn, 19, 2);
11732 if (!Check(S, decodeUImmOperand<2>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11733 tmp = fieldFromInstruction(insn, 18, 1);
11734 if (!Check(S, decodeUImmOperand<1>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11735 tmp = fieldFromInstruction(insn, 16, 2);
11736 if (!Check(S, decodeUImmOperand<2>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11737 return S;
11738 case 216:
11739 tmp = 0x0;
11740 tmp |= fieldFromInstruction(insn, 1, 1) << 4;
11741 tmp |= fieldFromInstruction(insn, 12, 4);
11742 if (!Check(S, DecodeVSRpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11743 tmp = fieldFromInstruction(insn, 23, 3);
11744 if (!Check(S, DecodeDMRROWpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11745 tmp = 0x0;
11746 tmp |= fieldFromInstruction(insn, 11, 1) << 1;
11747 tmp |= fieldFromInstruction(insn, 16, 1);
11748 if (!Check(S, decodeUImmOperand<2>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11749 return S;
11750 case 217:
11751 tmp = fieldFromInstruction(insn, 23, 3);
11752 if (!Check(S, DecodeDMRROWpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11753 tmp = 0x0;
11754 tmp |= fieldFromInstruction(insn, 1, 1) << 4;
11755 tmp |= fieldFromInstruction(insn, 12, 4);
11756 if (!Check(S, DecodeVSRpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11757 tmp = 0x0;
11758 tmp |= fieldFromInstruction(insn, 11, 1) << 1;
11759 tmp |= fieldFromInstruction(insn, 16, 1);
11760 if (!Check(S, decodeUImmOperand<2>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11761 return S;
11762 case 218:
11763 tmp = 0x0;
11764 tmp |= fieldFromInstruction(insn, 0, 1) << 5;
11765 tmp |= fieldFromInstruction(insn, 21, 5);
11766 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11767 tmp = 0x0;
11768 tmp |= fieldFromInstruction(insn, 2, 1) << 5;
11769 tmp |= fieldFromInstruction(insn, 16, 5);
11770 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11771 tmp = 0x0;
11772 tmp |= fieldFromInstruction(insn, 0, 1) << 5;
11773 tmp |= fieldFromInstruction(insn, 21, 5);
11774 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11775 tmp = 0x0;
11776 tmp |= fieldFromInstruction(insn, 1, 1) << 5;
11777 tmp |= fieldFromInstruction(insn, 11, 5);
11778 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11779 return S;
11780 case 219:
11781 tmp = 0x0;
11782 tmp |= fieldFromInstruction(insn, 0, 1) << 5;
11783 tmp |= fieldFromInstruction(insn, 21, 5);
11784 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11785 tmp = fieldFromInstruction(insn, 11, 8);
11786 if (!Check(S, decodeUImmOperand<8>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11787 return S;
11788 case 220:
11789 tmp = 0x0;
11790 tmp |= fieldFromInstruction(insn, 0, 1) << 5;
11791 tmp |= fieldFromInstruction(insn, 21, 5);
11792 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11793 tmp = fieldFromInstruction(insn, 11, 5);
11794 if (!Check(S, decodeUImmOperand<5>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11795 return S;
11796 case 221:
11797 tmp = 0x0;
11798 tmp |= fieldFromInstruction(insn, 0, 1) << 5;
11799 tmp |= fieldFromInstruction(insn, 21, 5);
11800 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11801 tmp = 0x0;
11802 tmp |= fieldFromInstruction(insn, 0, 1) << 5;
11803 tmp |= fieldFromInstruction(insn, 21, 5);
11804 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11805 tmp = 0x0;
11806 tmp |= fieldFromInstruction(insn, 1, 1) << 5;
11807 tmp |= fieldFromInstruction(insn, 11, 5);
11808 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11809 tmp = fieldFromInstruction(insn, 16, 5);
11810 if (!Check(S, decodeUImmOperand<4>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11811 return S;
11812 case 222:
11813 tmp = 0x0;
11814 tmp |= fieldFromInstruction(insn, 0, 1) << 5;
11815 tmp |= fieldFromInstruction(insn, 21, 5);
11816 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11817 tmp = 0x0;
11818 tmp |= fieldFromInstruction(insn, 2, 1) << 5;
11819 tmp |= fieldFromInstruction(insn, 16, 5);
11820 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11821 tmp = 0x0;
11822 tmp |= fieldFromInstruction(insn, 1, 1) << 5;
11823 tmp |= fieldFromInstruction(insn, 11, 5);
11824 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11825 tmp = fieldFromInstruction(insn, 8, 1);
11826 if (!Check(S, decodeUImmOperand<1>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11827 return S;
11828 case 223:
11829 tmp = 0x0;
11830 tmp |= fieldFromInstruction(insn, 0, 1) << 5;
11831 tmp |= fieldFromInstruction(insn, 21, 5);
11832 if (!Check(S, DecodeVSSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11833 tmp = 0x0;
11834 tmp |= fieldFromInstruction(insn, 1, 1) << 5;
11835 tmp |= fieldFromInstruction(insn, 11, 5);
11836 if (!Check(S, DecodeVSSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11837 return S;
11838 case 224:
11839 tmp = 0x0;
11840 tmp |= fieldFromInstruction(insn, 0, 1) << 5;
11841 tmp |= fieldFromInstruction(insn, 21, 5);
11842 if (!Check(S, DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11843 tmp = 0x0;
11844 tmp |= fieldFromInstruction(insn, 1, 1) << 5;
11845 tmp |= fieldFromInstruction(insn, 11, 5);
11846 if (!Check(S, DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11847 return S;
11848 case 225:
11849 tmp = fieldFromInstruction(insn, 23, 3);
11850 if (!Check(S, DecodeCRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11851 tmp = 0x0;
11852 tmp |= fieldFromInstruction(insn, 1, 1) << 5;
11853 tmp |= fieldFromInstruction(insn, 11, 5);
11854 if (!Check(S, DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11855 return S;
11856 case 226:
11857 tmp = 0x0;
11858 tmp |= fieldFromInstruction(insn, 0, 1) << 5;
11859 tmp |= fieldFromInstruction(insn, 21, 5);
11860 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11861 tmp = 0x0;
11862 tmp |= fieldFromInstruction(insn, 1, 1) << 5;
11863 tmp |= fieldFromInstruction(insn, 11, 5);
11864 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11865 return S;
11866 case 227:
11867 tmp = fieldFromInstruction(insn, 23, 3);
11868 if (!Check(S, DecodeCRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11869 tmp = 0x0;
11870 tmp |= fieldFromInstruction(insn, 1, 1) << 5;
11871 tmp |= fieldFromInstruction(insn, 11, 5);
11872 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11873 return S;
11874 case 228:
11875 tmp = fieldFromInstruction(insn, 23, 3);
11876 if (!Check(S, DecodeCRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11877 tmp = 0x0;
11878 tmp |= fieldFromInstruction(insn, 2, 1) << 5;
11879 tmp |= fieldFromInstruction(insn, 16, 5);
11880 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11881 tmp = 0x0;
11882 tmp |= fieldFromInstruction(insn, 1, 1) << 5;
11883 tmp |= fieldFromInstruction(insn, 11, 5);
11884 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11885 return S;
11886 case 229:
11887 tmp = 0x0;
11888 tmp |= fieldFromInstruction(insn, 0, 1) << 5;
11889 tmp |= fieldFromInstruction(insn, 21, 5);
11890 if (!Check(S, DecodeVSSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11891 tmp = 0x0;
11892 tmp |= fieldFromInstruction(insn, 1, 1) << 5;
11893 tmp |= fieldFromInstruction(insn, 11, 5);
11894 if (!Check(S, DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11895 return S;
11896 case 230:
11897 tmp = 0x0;
11898 tmp |= fieldFromInstruction(insn, 0, 1) << 5;
11899 tmp |= fieldFromInstruction(insn, 21, 5);
11900 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11901 tmp = 0x0;
11902 tmp |= fieldFromInstruction(insn, 1, 1) << 5;
11903 tmp |= fieldFromInstruction(insn, 11, 5);
11904 if (!Check(S, DecodeVSSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11905 return S;
11906 case 231:
11907 tmp = fieldFromInstruction(insn, 23, 3);
11908 if (!Check(S, DecodeCRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11909 tmp = fieldFromInstruction(insn, 16, 7);
11910 if (!Check(S, decodeUImmOperand<7>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11911 tmp = 0x0;
11912 tmp |= fieldFromInstruction(insn, 1, 1) << 5;
11913 tmp |= fieldFromInstruction(insn, 11, 5);
11914 if (!Check(S, DecodeVSSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11915 return S;
11916 case 232:
11917 tmp = 0x0;
11918 tmp |= fieldFromInstruction(insn, 0, 1) << 5;
11919 tmp |= fieldFromInstruction(insn, 21, 5);
11920 if (!Check(S, DecodeVSSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11921 tmp = 0x0;
11922 tmp |= fieldFromInstruction(insn, 1, 1) << 5;
11923 tmp |= fieldFromInstruction(insn, 11, 5);
11924 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11925 return S;
11926 case 233:
11927 tmp = fieldFromInstruction(insn, 21, 5);
11928 if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11929 tmp = 0x0;
11930 tmp |= fieldFromInstruction(insn, 1, 1) << 5;
11931 tmp |= fieldFromInstruction(insn, 11, 5);
11932 if (!Check(S, DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11933 return S;
11934 case 234:
11935 tmp = fieldFromInstruction(insn, 23, 3);
11936 if (!Check(S, DecodeCRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11937 tmp = fieldFromInstruction(insn, 16, 7);
11938 if (!Check(S, decodeUImmOperand<7>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11939 tmp = 0x0;
11940 tmp |= fieldFromInstruction(insn, 1, 1) << 5;
11941 tmp |= fieldFromInstruction(insn, 11, 5);
11942 if (!Check(S, DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11943 return S;
11944 case 235:
11945 tmp = 0x0;
11946 tmp |= fieldFromInstruction(insn, 0, 1) << 5;
11947 tmp |= fieldFromInstruction(insn, 21, 5);
11948 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11949 tmp = 0x0;
11950 tmp |= fieldFromInstruction(insn, 2, 1) << 5;
11951 tmp |= fieldFromInstruction(insn, 6, 1) << 6;
11952 tmp |= fieldFromInstruction(insn, 16, 5);
11953 if (!Check(S, decodeUImmOperand<7>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11954 tmp = 0x0;
11955 tmp |= fieldFromInstruction(insn, 1, 1) << 5;
11956 tmp |= fieldFromInstruction(insn, 11, 5);
11957 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11958 return S;
11959 case 236:
11960 tmp = 0x0;
11961 tmp |= fieldFromInstruction(insn, 0, 1) << 5;
11962 tmp |= fieldFromInstruction(insn, 21, 5);
11963 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11964 tmp = fieldFromInstruction(insn, 11, 5);
11965 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11966 tmp = fieldFromInstruction(insn, 16, 5);
11967 if (!Check(S, decodeSImmOperand<5>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11968 return S;
11969 case 237:
11970 tmp = 0x0;
11971 tmp |= fieldFromInstruction(insn, 0, 1) << 5;
11972 tmp |= fieldFromInstruction(insn, 21, 5);
11973 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11974 tmp = fieldFromInstruction(insn, 16, 5);
11975 if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11976 tmp = fieldFromInstruction(insn, 11, 5);
11977 if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11978 return S;
11979 case 238:
11980 tmp = 0x0;
11981 tmp |= fieldFromInstruction(insn, 0, 1) << 5;
11982 tmp |= fieldFromInstruction(insn, 21, 5);
11983 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11984 tmp = 0x0;
11985 tmp |= fieldFromInstruction(insn, 2, 1) << 5;
11986 tmp |= fieldFromInstruction(insn, 16, 5);
11987 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11988 tmp = 0x0;
11989 tmp |= fieldFromInstruction(insn, 1, 1) << 5;
11990 tmp |= fieldFromInstruction(insn, 11, 5);
11991 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11992 tmp = 0x0;
11993 tmp |= fieldFromInstruction(insn, 3, 1) << 5;
11994 tmp |= fieldFromInstruction(insn, 6, 5);
11995 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11996 return S;
11997 case 239:
11998 tmp = 0x0;
11999 tmp |= fieldFromInstruction(insn, 3, 1) << 5;
12000 tmp |= fieldFromInstruction(insn, 21, 5);
12001 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12002 tmp = fieldFromInstruction(insn, 4, 12);
12003 if (!Check(S, decodeDispRIX16Operand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12004 tmp = fieldFromInstruction(insn, 16, 5);
12005 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12006 return S;
12007 case 240:
12008 tmp = fieldFromInstruction(insn, 16, 5);
12009 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12010 tmp = fieldFromInstruction(insn, 21, 5);
12011 if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12012 tmp = fieldFromInstruction(insn, 2, 14);
12013 if (!Check(S, decodeDispRIXOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12014 tmp = fieldFromInstruction(insn, 16, 5);
12015 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12016 return S;
12017 case 241:
12018 tmp = fieldFromInstruction(insn, 21, 5);
12019 if (!Check(S, DecodeG8pRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12020 tmp = fieldFromInstruction(insn, 2, 14);
12021 if (!Check(S, decodeDispRIXOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12022 tmp = fieldFromInstruction(insn, 16, 5);
12023 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12024 return S;
12025 case 242:
12026 tmp = fieldFromInstruction(insn, 23, 3);
12027 if (!Check(S, DecodeCRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12028 tmp = fieldFromInstruction(insn, 16, 5);
12029 if (!Check(S, DecodeF4RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12030 tmp = fieldFromInstruction(insn, 11, 5);
12031 if (!Check(S, DecodeF4RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12032 return S;
12033 case 243:
12034 tmp = fieldFromInstruction(insn, 23, 3);
12035 if (!Check(S, DecodeCRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12036 tmp = fieldFromInstruction(insn, 11, 5);
12037 if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12038 return S;
12039 case 244:
12040 tmp = fieldFromInstruction(insn, 21, 5);
12041 if (!Check(S, DecodeFpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12042 tmp = fieldFromInstruction(insn, 16, 5);
12043 if (!Check(S, DecodeFpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12044 tmp = fieldFromInstruction(insn, 11, 5);
12045 if (!Check(S, DecodeFpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12046 return S;
12047 case 245:
12048 tmp = fieldFromInstruction(insn, 21, 5);
12049 if (!Check(S, DecodeFpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12050 tmp = fieldFromInstruction(insn, 16, 5);
12051 if (!Check(S, DecodeFpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12052 tmp = fieldFromInstruction(insn, 10, 6);
12053 if (!Check(S, decodeUImmOperand<6>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12054 return S;
12055 case 246:
12056 tmp = fieldFromInstruction(insn, 23, 3);
12057 if (!Check(S, DecodeCRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12058 tmp = fieldFromInstruction(insn, 16, 5);
12059 if (!Check(S, DecodeFpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12060 tmp = fieldFromInstruction(insn, 11, 5);
12061 if (!Check(S, DecodeFpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12062 return S;
12063 case 247:
12064 tmp = fieldFromInstruction(insn, 23, 3);
12065 if (!Check(S, DecodeCRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12066 tmp = fieldFromInstruction(insn, 16, 5);
12067 if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12068 tmp = fieldFromInstruction(insn, 11, 5);
12069 if (!Check(S, DecodeFpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12070 return S;
12071 case 248:
12072 tmp = fieldFromInstruction(insn, 23, 3);
12073 if (!Check(S, DecodeCRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12074 tmp = fieldFromInstruction(insn, 16, 5);
12075 if (!Check(S, DecodeFpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12076 tmp = fieldFromInstruction(insn, 10, 6);
12077 if (!Check(S, decodeUImmOperand<6>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12078 return S;
12079 case 249:
12080 tmp = fieldFromInstruction(insn, 21, 5);
12081 if (!Check(S, DecodeFpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12082 tmp = fieldFromInstruction(insn, 11, 5);
12083 if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12084 return S;
12085 case 250:
12086 tmp = fieldFromInstruction(insn, 21, 5);
12087 if (!Check(S, DecodeFpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12088 tmp = fieldFromInstruction(insn, 11, 5);
12089 if (!Check(S, DecodeFpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12090 return S;
12091 case 251:
12092 tmp = fieldFromInstruction(insn, 21, 5);
12093 if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12094 tmp = fieldFromInstruction(insn, 11, 5);
12095 if (!Check(S, DecodeFpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12096 return S;
12097 case 252:
12098 tmp = fieldFromInstruction(insn, 21, 5);
12099 if (!Check(S, DecodeFpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12100 tmp = fieldFromInstruction(insn, 19, 2);
12101 if (!Check(S, decodeUImmOperand<2>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12102 tmp = fieldFromInstruction(insn, 11, 5);
12103 if (!Check(S, DecodeFpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12104 return S;
12105 case 253:
12106 tmp = fieldFromInstruction(insn, 21, 5);
12107 if (!Check(S, DecodeFpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12108 tmp = fieldFromInstruction(insn, 20, 1);
12109 if (!Check(S, decodeUImmOperand<1>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12110 tmp = fieldFromInstruction(insn, 11, 5);
12111 if (!Check(S, DecodeFpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12112 return S;
12113 case 254:
12114 tmp = fieldFromInstruction(insn, 21, 5);
12115 if (!Check(S, DecodeFpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12116 tmp = fieldFromInstruction(insn, 16, 5);
12117 if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12118 tmp = fieldFromInstruction(insn, 11, 5);
12119 if (!Check(S, DecodeFpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12120 return S;
12121 case 255:
12122 tmp = fieldFromInstruction(insn, 21, 5);
12123 if (!Check(S, DecodeFpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12124 tmp = fieldFromInstruction(insn, 11, 5);
12125 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12126 return S;
12127 case 256:
12128 tmp = fieldFromInstruction(insn, 21, 5);
12129 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12130 tmp = fieldFromInstruction(insn, 11, 5);
12131 if (!Check(S, DecodeFpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12132 return S;
12133 case 257:
12134 tmp = fieldFromInstruction(insn, 21, 5);
12135 if (!Check(S, DecodeFpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12136 tmp = fieldFromInstruction(insn, 16, 5);
12137 if (!Check(S, DecodeFpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12138 tmp = fieldFromInstruction(insn, 11, 5);
12139 if (!Check(S, DecodeFpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12140 tmp = fieldFromInstruction(insn, 9, 2);
12141 if (!Check(S, decodeUImmOperand<2>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12142 return S;
12143 case 258:
12144 tmp = fieldFromInstruction(insn, 21, 5);
12145 if (!Check(S, DecodeFpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12146 tmp = fieldFromInstruction(insn, 16, 5);
12147 if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12148 tmp = fieldFromInstruction(insn, 11, 5);
12149 if (!Check(S, DecodeFpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12150 tmp = fieldFromInstruction(insn, 9, 2);
12151 if (!Check(S, decodeUImmOperand<2>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12152 return S;
12153 case 259:
12154 tmp = fieldFromInstruction(insn, 21, 5);
12155 if (!Check(S, DecodeFpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12156 tmp = fieldFromInstruction(insn, 16, 5);
12157 if (!Check(S, decodeSImmOperand<5>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12158 tmp = fieldFromInstruction(insn, 11, 5);
12159 if (!Check(S, DecodeFpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12160 tmp = fieldFromInstruction(insn, 9, 2);
12161 if (!Check(S, decodeUImmOperand<2>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12162 return S;
12163 case 260:
12164 tmp = fieldFromInstruction(insn, 21, 5);
12165 if (!Check(S, DecodeFpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12166 tmp = fieldFromInstruction(insn, 16, 1);
12167 if (!Check(S, decodeUImmOperand<1>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12168 tmp = fieldFromInstruction(insn, 11, 5);
12169 if (!Check(S, DecodeFpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12170 tmp = fieldFromInstruction(insn, 9, 2);
12171 if (!Check(S, decodeUImmOperand<2>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12172 return S;
12173 case 261:
12174 tmp = fieldFromInstruction(insn, 23, 3);
12175 if (!Check(S, DecodeCRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12176 tmp = fieldFromInstruction(insn, 16, 6);
12177 if (!Check(S, decodeUImmOperand<6>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12178 tmp = fieldFromInstruction(insn, 11, 5);
12179 if (!Check(S, DecodeFpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12180 return S;
12181 case 262:
12182 tmp = fieldFromInstruction(insn, 21, 5);
12183 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12184 tmp = fieldFromInstruction(insn, 21, 5);
12185 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12186 tmp = fieldFromInstruction(insn, 16, 5);
12187 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12188 tmp = fieldFromInstruction(insn, 11, 5);
12189 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12190 return S;
12191 case 263:
12192 tmp = fieldFromInstruction(insn, 23, 3);
12193 if (!Check(S, DecodeCRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12194 tmp = fieldFromInstruction(insn, 16, 7);
12195 if (!Check(S, decodeUImmOperand<7>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12196 tmp = fieldFromInstruction(insn, 11, 5);
12197 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12198 return S;
12199 case 264:
12200 tmp = fieldFromInstruction(insn, 21, 5);
12201 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12202 tmp = fieldFromInstruction(insn, 11, 5);
12203 if (!Check(S, DecodeVFRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12204 return S;
12205 case 265:
12206 tmp = fieldFromInstruction(insn, 21, 5);
12207 if (!Check(S, DecodeVFRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12208 tmp = fieldFromInstruction(insn, 11, 5);
12209 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12210 return S;
12211 case 266:
12212 tmp = fieldFromInstruction(insn, 21, 5);
12213 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12214 tmp = fieldFromInstruction(insn, 16, 5);
12215 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12216 tmp = fieldFromInstruction(insn, 11, 5);
12217 if (!Check(S, DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12218 return S;
12219 case 267:
12220 tmp = fieldFromInstruction(insn, 21, 5);
12221 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12222 tmp = fieldFromInstruction(insn, 16, 1);
12223 if (!Check(S, decodeUImmOperand<1>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12224 tmp = fieldFromInstruction(insn, 11, 5);
12225 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12226 tmp = fieldFromInstruction(insn, 9, 2);
12227 if (!Check(S, decodeUImmOperand<2>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12228 return S;
12229 case 268:
12230 tmp = fieldFromInstruction(insn, 23, 3);
12231 if (!Check(S, decodeUImmOperand<3>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12232 tmp = fieldFromInstruction(insn, 12, 4);
12233 if (!Check(S, decodeUImmOperand<4>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12234 tmp = fieldFromInstruction(insn, 16, 1);
12235 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
12236 return S;
12237 case 269:
12238 tmp = fieldFromInstruction(insn, 23, 3);
12239 if (!Check(S, decodeUImmOperand<3>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12240 tmp = fieldFromInstruction(insn, 12, 4);
12241 if (!Check(S, decodeUImmOperand<4>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12242 tmp = fieldFromInstruction(insn, 16, 1);
12243 if (!Check(S, decodeUImmOperand<1>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12244 return S;
12245 case 270:
12246 tmp = fieldFromInstruction(insn, 21, 5);
12247 if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12248 return S;
12249 case 271:
12250 tmp = fieldFromInstruction(insn, 21, 5);
12251 if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12252 tmp = fieldFromInstruction(insn, 11, 3);
12253 if (!Check(S, decodeUImmOperand<3>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12254 return S;
12255 case 272:
12256 tmp = fieldFromInstruction(insn, 21, 5);
12257 if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12258 tmp = fieldFromInstruction(insn, 11, 2);
12259 if (!Check(S, decodeUImmOperand<2>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12260 return S;
12261 case 273:
12262 tmp = fieldFromInstruction(insn, 17, 8);
12263 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
12264 tmp = fieldFromInstruction(insn, 11, 5);
12265 if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12266 tmp = fieldFromInstruction(insn, 25, 1);
12267 if (!Check(S, decodeUImmOperand<1>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12268 tmp = fieldFromInstruction(insn, 16, 1);
12269 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
12270 return S;
12271 case 274:
12272 tmp = fieldFromInstruction(insn, 21, 5);
12273 if (!Check(S, DecodeF4RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12274 tmp = fieldFromInstruction(insn, 16, 5);
12275 if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12276 tmp = fieldFromInstruction(insn, 6, 5);
12277 if (!Check(S, DecodeF4RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12278 tmp = fieldFromInstruction(insn, 11, 5);
12279 if (!Check(S, DecodeF4RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12280 return S;
12281 case 275:
12282 tmp = fieldFromInstruction(insn, 21, 5);
12283 if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12284 tmp = fieldFromInstruction(insn, 16, 5);
12285 if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12286 tmp = fieldFromInstruction(insn, 6, 5);
12287 if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12288 return S;
12289 case 276:
12290 tmp = fieldFromInstruction(insn, 21, 5);
12291 if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12292 tmp = fieldFromInstruction(insn, 16, 5);
12293 if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12294 tmp = fieldFromInstruction(insn, 6, 5);
12295 if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12296 tmp = fieldFromInstruction(insn, 11, 5);
12297 if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12298 return S;
12299 case 277:
12300 tmp = fieldFromInstruction(insn, 21, 5);
12301 if (!Check(S, DecodeSPERCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12302 tmp = fieldFromInstruction(insn, 16, 5);
12303 if (!Check(S, DecodeSPERCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12304 tmp = fieldFromInstruction(insn, 11, 5);
12305 if (!Check(S, DecodeSPERCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12306 return S;
12307 case 278:
12308 tmp = fieldFromInstruction(insn, 21, 5);
12309 if (!Check(S, DecodeSPERCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12310 tmp = fieldFromInstruction(insn, 16, 5);
12311 if (!Check(S, DecodeSPERCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12312 tmp = fieldFromInstruction(insn, 11, 5);
12313 if (!Check(S, decodeUImmOperand<5>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12314 return S;
12315 case 279:
12316 tmp = fieldFromInstruction(insn, 21, 5);
12317 if (!Check(S, DecodeSPERCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12318 tmp = fieldFromInstruction(insn, 16, 5);
12319 if (!Check(S, decodeUImmOperand<5>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12320 tmp = fieldFromInstruction(insn, 11, 5);
12321 if (!Check(S, DecodeSPERCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12322 return S;
12323 case 280:
12324 tmp = fieldFromInstruction(insn, 21, 5);
12325 if (!Check(S, DecodeSPERCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12326 tmp = fieldFromInstruction(insn, 16, 5);
12327 if (!Check(S, DecodeSPERCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12328 return S;
12329 case 281:
12330 tmp = fieldFromInstruction(insn, 21, 5);
12331 if (!Check(S, DecodeSPERCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12332 tmp = fieldFromInstruction(insn, 16, 5);
12333 if (!Check(S, decodeSImmOperand<5>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12334 return S;
12335 case 282:
12336 tmp = fieldFromInstruction(insn, 21, 5);
12337 if (!Check(S, DecodeSPERCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12338 tmp = fieldFromInstruction(insn, 16, 5);
12339 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12340 tmp = fieldFromInstruction(insn, 11, 5);
12341 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12342 return S;
12343 case 283:
12344 tmp = fieldFromInstruction(insn, 23, 3);
12345 if (!Check(S, DecodeCRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12346 tmp = fieldFromInstruction(insn, 16, 5);
12347 if (!Check(S, DecodeSPERCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12348 tmp = fieldFromInstruction(insn, 11, 5);
12349 if (!Check(S, DecodeSPERCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12350 return S;
12351 case 284:
12352 tmp = fieldFromInstruction(insn, 21, 5);
12353 if (!Check(S, DecodeSPERCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12354 tmp = fieldFromInstruction(insn, 16, 5);
12355 if (!Check(S, DecodeSPERCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12356 tmp = fieldFromInstruction(insn, 11, 5);
12357 if (!Check(S, DecodeSPERCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12358 tmp = fieldFromInstruction(insn, 0, 3);
12359 if (!Check(S, DecodeCRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12360 return S;
12361 case 285:
12362 tmp = fieldFromInstruction(insn, 21, 5);
12363 if (!Check(S, DecodeSPERCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12364 tmp = fieldFromInstruction(insn, 11, 5);
12365 if (!Check(S, DecodeSPERCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12366 return S;
12367 case 286:
12368 tmp = fieldFromInstruction(insn, 21, 5);
12369 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12370 tmp = fieldFromInstruction(insn, 11, 5);
12371 if (!Check(S, DecodeSPERCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12372 return S;
12373 case 287:
12374 tmp = fieldFromInstruction(insn, 21, 5);
12375 if (!Check(S, DecodeSPERCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12376 tmp = fieldFromInstruction(insn, 11, 5);
12377 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12378 return S;
12379 case 288:
12380 tmp = fieldFromInstruction(insn, 21, 5);
12381 if (!Check(S, DecodeSPERCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12382 tmp = fieldFromInstruction(insn, 16, 5);
12383 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12384 tmp = fieldFromInstruction(insn, 11, 5);
12385 if (!Check(S, Decodeptr_rc_idx_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12386 return S;
12387 case 289:
12388 tmp = fieldFromInstruction(insn, 21, 5);
12389 if (!Check(S, DecodeSPERCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12390 tmp = fieldFromInstruction(insn, 11, 5);
12391 if (!Check(S, decodeDispSPE8Operand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12392 tmp = fieldFromInstruction(insn, 16, 5);
12393 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12394 return S;
12395 case 290:
12396 tmp = fieldFromInstruction(insn, 21, 5);
12397 if (!Check(S, DecodeSPERCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12398 tmp = fieldFromInstruction(insn, 11, 5);
12399 if (!Check(S, decodeDispSPE2Operand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12400 tmp = fieldFromInstruction(insn, 16, 5);
12401 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12402 return S;
12403 case 291:
12404 tmp = fieldFromInstruction(insn, 21, 5);
12405 if (!Check(S, DecodeSPERCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12406 tmp = fieldFromInstruction(insn, 11, 5);
12407 if (!Check(S, decodeDispSPE4Operand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12408 tmp = fieldFromInstruction(insn, 16, 5);
12409 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12410 return S;
12411 case 292:
12412 tmp = fieldFromInstruction(insn, 21, 5);
12413 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12414 tmp = 0x0;
12415 tmp |= fieldFromInstruction(insn, 0, 16);
12416 tmp |= fieldFromInstruction(insn, 32, 18) << 16;
12417 if (!Check(S, decodeSImmOperand<34>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12418 return S;
12419 case 293:
12420 tmp = fieldFromInstruction(insn, 21, 5);
12421 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12422 tmp = fieldFromInstruction(insn, 16, 5);
12423 if (!Check(S, DecodeGPRC_NOR0RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12424 tmp = 0x0;
12425 tmp |= fieldFromInstruction(insn, 0, 16);
12426 tmp |= fieldFromInstruction(insn, 32, 18) << 16;
12427 if (!Check(S, decodeSImmOperand<34>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12428 return S;
12429 case 294:
12430 tmp = fieldFromInstruction(insn, 21, 5);
12431 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12432 tmp = fieldFromInstruction(insn, 16, 5);
12433 if (!Check(S, decodeImmZeroOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12434 tmp = 0x0;
12435 tmp |= fieldFromInstruction(insn, 0, 16);
12436 tmp |= fieldFromInstruction(insn, 32, 18) << 16;
12437 if (!Check(S, decodeSImmOperand<34>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12438 return S;
12439 case 295:
12440 tmp = fieldFromInstruction(insn, 21, 5);
12441 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12442 tmp = fieldFromInstruction(insn, 16, 5);
12443 if (!Check(S, DecodeGPRC_NOR0RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12444 tmp = 0x0;
12445 tmp |= fieldFromInstruction(insn, 0, 16);
12446 tmp |= fieldFromInstruction(insn, 32, 16) << 16;
12447 if (!Check(S, decodeSImmOperand<34>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12448 return S;
12449 case 296:
12450 tmp = fieldFromInstruction(insn, 21, 5);
12451 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12452 tmp = fieldFromInstruction(insn, 16, 5);
12453 if (!Check(S, decodeImmZeroOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12454 tmp = 0x0;
12455 tmp |= fieldFromInstruction(insn, 0, 16);
12456 tmp |= fieldFromInstruction(insn, 32, 16) << 16;
12457 if (!Check(S, decodeSImmOperand<34>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12458 return S;
12459 case 297:
12460 tmp = 0x0;
12461 tmp |= fieldFromInstruction(insn, 16, 1) << 5;
12462 tmp |= fieldFromInstruction(insn, 21, 5);
12463 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12464 tmp = 0x0;
12465 tmp |= fieldFromInstruction(insn, 16, 1) << 5;
12466 tmp |= fieldFromInstruction(insn, 21, 5);
12467 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12468 tmp = fieldFromInstruction(insn, 17, 1);
12469 if (!Check(S, decodeUImmOperand<1>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12470 tmp = 0x0;
12471 tmp |= fieldFromInstruction(insn, 0, 16);
12472 tmp |= fieldFromInstruction(insn, 32, 16) << 16;
12473 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
12474 return S;
12475 case 298:
12476 tmp = 0x0;
12477 tmp |= fieldFromInstruction(insn, 16, 1) << 5;
12478 tmp |= fieldFromInstruction(insn, 21, 5);
12479 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12480 tmp = 0x0;
12481 tmp |= fieldFromInstruction(insn, 0, 16);
12482 tmp |= fieldFromInstruction(insn, 32, 16) << 16;
12483 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
12484 return S;
12485 case 299:
12486 tmp = fieldFromInstruction(insn, 21, 5);
12487 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12488 tmp = 0x0;
12489 tmp |= fieldFromInstruction(insn, 0, 16);
12490 tmp |= fieldFromInstruction(insn, 32, 18) << 16;
12491 if (!Check(S, decodeSImmOperand<34>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12492 tmp = fieldFromInstruction(insn, 16, 5);
12493 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12494 return S;
12495 case 300:
12496 tmp = fieldFromInstruction(insn, 21, 5);
12497 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12498 tmp = 0x0;
12499 tmp |= fieldFromInstruction(insn, 0, 16);
12500 tmp |= fieldFromInstruction(insn, 32, 18) << 16;
12501 if (!Check(S, decodeSImmOperand<34>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12502 tmp = fieldFromInstruction(insn, 16, 5);
12503 if (!Check(S, decodeImmZeroOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12504 return S;
12505 case 301:
12506 tmp = 0x0;
12507 tmp |= fieldFromInstruction(insn, 0, 1) << 5;
12508 tmp |= fieldFromInstruction(insn, 21, 5);
12509 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12510 tmp = 0x0;
12511 tmp |= fieldFromInstruction(insn, 2, 1) << 5;
12512 tmp |= fieldFromInstruction(insn, 16, 5);
12513 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12514 tmp = 0x0;
12515 tmp |= fieldFromInstruction(insn, 1, 1) << 5;
12516 tmp |= fieldFromInstruction(insn, 11, 5);
12517 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12518 tmp = 0x0;
12519 tmp |= fieldFromInstruction(insn, 3, 1) << 5;
12520 tmp |= fieldFromInstruction(insn, 6, 5);
12521 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12522 tmp = fieldFromInstruction(insn, 32, 3);
12523 if (!Check(S, decodeUImmOperand<3>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12524 return S;
12525 case 302:
12526 tmp = 0x0;
12527 tmp |= fieldFromInstruction(insn, 0, 1) << 5;
12528 tmp |= fieldFromInstruction(insn, 21, 5);
12529 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12530 tmp = 0x0;
12531 tmp |= fieldFromInstruction(insn, 2, 1) << 5;
12532 tmp |= fieldFromInstruction(insn, 16, 5);
12533 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12534 tmp = 0x0;
12535 tmp |= fieldFromInstruction(insn, 1, 1) << 5;
12536 tmp |= fieldFromInstruction(insn, 11, 5);
12537 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12538 tmp = 0x0;
12539 tmp |= fieldFromInstruction(insn, 3, 1) << 5;
12540 tmp |= fieldFromInstruction(insn, 6, 5);
12541 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12542 tmp = fieldFromInstruction(insn, 32, 8);
12543 if (!Check(S, decodeUImmOperand<8>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12544 return S;
12545 case 303:
12546 tmp = 0x0;
12547 tmp |= fieldFromInstruction(insn, 0, 1) << 5;
12548 tmp |= fieldFromInstruction(insn, 21, 5);
12549 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12550 tmp = 0x0;
12551 tmp |= fieldFromInstruction(insn, 2, 1) << 5;
12552 tmp |= fieldFromInstruction(insn, 16, 5);
12553 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12554 tmp = 0x0;
12555 tmp |= fieldFromInstruction(insn, 1, 1) << 5;
12556 tmp |= fieldFromInstruction(insn, 11, 5);
12557 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12558 tmp = 0x0;
12559 tmp |= fieldFromInstruction(insn, 3, 1) << 5;
12560 tmp |= fieldFromInstruction(insn, 6, 5);
12561 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12562 tmp = fieldFromInstruction(insn, 4, 1);
12563 if (!Check(S, decodeUImmOperand<1>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12564 return S;
12565 case 304:
12566 tmp = fieldFromInstruction(insn, 21, 5);
12567 if (!Check(S, DecodeVFRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12568 tmp = 0x0;
12569 tmp |= fieldFromInstruction(insn, 0, 16);
12570 tmp |= fieldFromInstruction(insn, 32, 18) << 16;
12571 if (!Check(S, decodeSImmOperand<34>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12572 tmp = fieldFromInstruction(insn, 16, 5);
12573 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12574 return S;
12575 case 305:
12576 tmp = fieldFromInstruction(insn, 21, 5);
12577 if (!Check(S, DecodeVFRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12578 tmp = 0x0;
12579 tmp |= fieldFromInstruction(insn, 0, 16);
12580 tmp |= fieldFromInstruction(insn, 32, 18) << 16;
12581 if (!Check(S, decodeSImmOperand<34>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12582 tmp = fieldFromInstruction(insn, 16, 5);
12583 if (!Check(S, decodeImmZeroOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12584 return S;
12585 case 306:
12586 tmp = fieldFromInstruction(insn, 21, 5);
12587 if (!Check(S, DecodeF4RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12588 tmp = 0x0;
12589 tmp |= fieldFromInstruction(insn, 0, 16);
12590 tmp |= fieldFromInstruction(insn, 32, 18) << 16;
12591 if (!Check(S, decodeSImmOperand<34>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12592 tmp = fieldFromInstruction(insn, 16, 5);
12593 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12594 return S;
12595 case 307:
12596 tmp = fieldFromInstruction(insn, 21, 5);
12597 if (!Check(S, DecodeF4RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12598 tmp = 0x0;
12599 tmp |= fieldFromInstruction(insn, 0, 16);
12600 tmp |= fieldFromInstruction(insn, 32, 18) << 16;
12601 if (!Check(S, decodeSImmOperand<34>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12602 tmp = fieldFromInstruction(insn, 16, 5);
12603 if (!Check(S, decodeImmZeroOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12604 return S;
12605 case 308:
12606 tmp = fieldFromInstruction(insn, 21, 6);
12607 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12608 tmp = 0x0;
12609 tmp |= fieldFromInstruction(insn, 0, 16);
12610 tmp |= fieldFromInstruction(insn, 32, 18) << 16;
12611 if (!Check(S, decodeSImmOperand<34>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12612 tmp = fieldFromInstruction(insn, 16, 5);
12613 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12614 return S;
12615 case 309:
12616 tmp = fieldFromInstruction(insn, 21, 6);
12617 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12618 tmp = 0x0;
12619 tmp |= fieldFromInstruction(insn, 0, 16);
12620 tmp |= fieldFromInstruction(insn, 32, 18) << 16;
12621 if (!Check(S, decodeSImmOperand<34>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12622 tmp = fieldFromInstruction(insn, 16, 5);
12623 if (!Check(S, decodeImmZeroOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12624 return S;
12625 case 310:
12626 tmp = fieldFromInstruction(insn, 21, 5);
12627 if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12628 tmp = 0x0;
12629 tmp |= fieldFromInstruction(insn, 0, 16);
12630 tmp |= fieldFromInstruction(insn, 32, 18) << 16;
12631 if (!Check(S, decodeSImmOperand<34>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12632 tmp = fieldFromInstruction(insn, 16, 5);
12633 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12634 return S;
12635 case 311:
12636 tmp = fieldFromInstruction(insn, 21, 5);
12637 if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12638 tmp = 0x0;
12639 tmp |= fieldFromInstruction(insn, 0, 16);
12640 tmp |= fieldFromInstruction(insn, 32, 18) << 16;
12641 if (!Check(S, decodeSImmOperand<34>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12642 tmp = fieldFromInstruction(insn, 16, 5);
12643 if (!Check(S, decodeImmZeroOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12644 return S;
12645 case 312:
12646 tmp = fieldFromInstruction(insn, 21, 5);
12647 if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12648 tmp = 0x0;
12649 tmp |= fieldFromInstruction(insn, 0, 16);
12650 tmp |= fieldFromInstruction(insn, 32, 18) << 16;
12651 if (!Check(S, decodeSImmOperand<34>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12652 tmp = fieldFromInstruction(insn, 16, 5);
12653 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12654 return S;
12655 case 313:
12656 tmp = fieldFromInstruction(insn, 21, 5);
12657 if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12658 tmp = 0x0;
12659 tmp |= fieldFromInstruction(insn, 0, 16);
12660 tmp |= fieldFromInstruction(insn, 32, 18) << 16;
12661 if (!Check(S, decodeSImmOperand<34>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12662 tmp = fieldFromInstruction(insn, 16, 5);
12663 if (!Check(S, decodeImmZeroOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12664 return S;
12665 case 314:
12666 tmp = 0x0;
12667 tmp |= fieldFromInstruction(insn, 21, 1) << 4;
12668 tmp |= fieldFromInstruction(insn, 22, 4);
12669 if (!Check(S, DecodeVSRpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12670 tmp = 0x0;
12671 tmp |= fieldFromInstruction(insn, 0, 16);
12672 tmp |= fieldFromInstruction(insn, 32, 18) << 16;
12673 if (!Check(S, decodeSImmOperand<34>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12674 tmp = fieldFromInstruction(insn, 16, 5);
12675 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12676 return S;
12677 case 315:
12678 tmp = 0x0;
12679 tmp |= fieldFromInstruction(insn, 21, 1) << 4;
12680 tmp |= fieldFromInstruction(insn, 22, 4);
12681 if (!Check(S, DecodeVSRpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12682 tmp = 0x0;
12683 tmp |= fieldFromInstruction(insn, 0, 16);
12684 tmp |= fieldFromInstruction(insn, 32, 18) << 16;
12685 if (!Check(S, decodeSImmOperand<34>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12686 tmp = fieldFromInstruction(insn, 16, 5);
12687 if (!Check(S, decodeImmZeroOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12688 return S;
12689 case 316:
12690 tmp = fieldFromInstruction(insn, 23, 3);
12691 if (!Check(S, DecodeACCRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12692 tmp = fieldFromInstruction(insn, 23, 3);
12693 if (!Check(S, DecodeACCRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12694 tmp = 0x0;
12695 tmp |= fieldFromInstruction(insn, 2, 1) << 5;
12696 tmp |= fieldFromInstruction(insn, 16, 5);
12697 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12698 tmp = 0x0;
12699 tmp |= fieldFromInstruction(insn, 1, 1) << 5;
12700 tmp |= fieldFromInstruction(insn, 11, 5);
12701 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12702 tmp = fieldFromInstruction(insn, 36, 4);
12703 if (!Check(S, decodeUImmOperand<4>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12704 tmp = fieldFromInstruction(insn, 32, 4);
12705 if (!Check(S, decodeUImmOperand<4>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12706 tmp = fieldFromInstruction(insn, 44, 4);
12707 if (!Check(S, decodeUImmOperand<4>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12708 return S;
12709 case 317:
12710 tmp = fieldFromInstruction(insn, 23, 3);
12711 if (!Check(S, DecodeACCRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12712 tmp = 0x0;
12713 tmp |= fieldFromInstruction(insn, 2, 1) << 5;
12714 tmp |= fieldFromInstruction(insn, 16, 5);
12715 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12716 tmp = 0x0;
12717 tmp |= fieldFromInstruction(insn, 1, 1) << 5;
12718 tmp |= fieldFromInstruction(insn, 11, 5);
12719 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12720 tmp = fieldFromInstruction(insn, 36, 4);
12721 if (!Check(S, decodeUImmOperand<4>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12722 tmp = fieldFromInstruction(insn, 32, 4);
12723 if (!Check(S, decodeUImmOperand<4>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12724 tmp = fieldFromInstruction(insn, 44, 4);
12725 if (!Check(S, decodeUImmOperand<4>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12726 return S;
12727 case 318:
12728 tmp = fieldFromInstruction(insn, 23, 3);
12729 if (!Check(S, DecodeDMRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12730 tmp = fieldFromInstruction(insn, 23, 3);
12731 if (!Check(S, DecodeDMRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12732 tmp = 0x0;
12733 tmp |= fieldFromInstruction(insn, 2, 1) << 4;
12734 tmp |= fieldFromInstruction(insn, 17, 4);
12735 if (!Check(S, DecodeVSRpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12736 tmp = 0x0;
12737 tmp |= fieldFromInstruction(insn, 1, 1) << 5;
12738 tmp |= fieldFromInstruction(insn, 11, 5);
12739 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12740 tmp = fieldFromInstruction(insn, 36, 8);
12741 if (!Check(S, decodeUImmOperand<8>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12742 tmp = fieldFromInstruction(insn, 32, 4);
12743 if (!Check(S, decodeUImmOperand<4>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12744 tmp = fieldFromInstruction(insn, 44, 4);
12745 if (!Check(S, decodeUImmOperand<4>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12746 return S;
12747 case 319:
12748 tmp = fieldFromInstruction(insn, 23, 3);
12749 if (!Check(S, DecodeDMRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12750 tmp = 0x0;
12751 tmp |= fieldFromInstruction(insn, 2, 1) << 4;
12752 tmp |= fieldFromInstruction(insn, 17, 4);
12753 if (!Check(S, DecodeVSRpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12754 tmp = 0x0;
12755 tmp |= fieldFromInstruction(insn, 1, 1) << 5;
12756 tmp |= fieldFromInstruction(insn, 11, 5);
12757 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12758 tmp = fieldFromInstruction(insn, 36, 8);
12759 if (!Check(S, decodeUImmOperand<8>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12760 tmp = fieldFromInstruction(insn, 32, 4);
12761 if (!Check(S, decodeUImmOperand<4>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12762 tmp = fieldFromInstruction(insn, 44, 4);
12763 if (!Check(S, decodeUImmOperand<4>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12764 return S;
12765 case 320:
12766 tmp = fieldFromInstruction(insn, 23, 3);
12767 if (!Check(S, DecodeACCRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12768 tmp = fieldFromInstruction(insn, 23, 3);
12769 if (!Check(S, DecodeACCRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12770 tmp = 0x0;
12771 tmp |= fieldFromInstruction(insn, 2, 1) << 5;
12772 tmp |= fieldFromInstruction(insn, 16, 5);
12773 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12774 tmp = 0x0;
12775 tmp |= fieldFromInstruction(insn, 1, 1) << 5;
12776 tmp |= fieldFromInstruction(insn, 11, 5);
12777 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12778 tmp = fieldFromInstruction(insn, 36, 4);
12779 if (!Check(S, decodeUImmOperand<4>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12780 tmp = fieldFromInstruction(insn, 32, 4);
12781 if (!Check(S, decodeUImmOperand<4>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12782 tmp = fieldFromInstruction(insn, 46, 2);
12783 if (!Check(S, decodeUImmOperand<2>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12784 return S;
12785 case 321:
12786 tmp = fieldFromInstruction(insn, 23, 3);
12787 if (!Check(S, DecodeACCRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12788 tmp = 0x0;
12789 tmp |= fieldFromInstruction(insn, 2, 1) << 5;
12790 tmp |= fieldFromInstruction(insn, 16, 5);
12791 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12792 tmp = 0x0;
12793 tmp |= fieldFromInstruction(insn, 1, 1) << 5;
12794 tmp |= fieldFromInstruction(insn, 11, 5);
12795 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12796 tmp = fieldFromInstruction(insn, 36, 4);
12797 if (!Check(S, decodeUImmOperand<4>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12798 tmp = fieldFromInstruction(insn, 32, 4);
12799 if (!Check(S, decodeUImmOperand<4>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12800 tmp = fieldFromInstruction(insn, 46, 2);
12801 if (!Check(S, decodeUImmOperand<2>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12802 return S;
12803 case 322:
12804 tmp = fieldFromInstruction(insn, 23, 3);
12805 if (!Check(S, DecodeACCRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12806 tmp = fieldFromInstruction(insn, 23, 3);
12807 if (!Check(S, DecodeACCRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12808 tmp = 0x0;
12809 tmp |= fieldFromInstruction(insn, 2, 1) << 5;
12810 tmp |= fieldFromInstruction(insn, 16, 5);
12811 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12812 tmp = 0x0;
12813 tmp |= fieldFromInstruction(insn, 1, 1) << 5;
12814 tmp |= fieldFromInstruction(insn, 11, 5);
12815 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12816 tmp = fieldFromInstruction(insn, 36, 4);
12817 if (!Check(S, decodeUImmOperand<4>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12818 tmp = fieldFromInstruction(insn, 32, 4);
12819 if (!Check(S, decodeUImmOperand<4>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12820 return S;
12821 case 323:
12822 tmp = fieldFromInstruction(insn, 23, 3);
12823 if (!Check(S, DecodeACCRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12824 tmp = 0x0;
12825 tmp |= fieldFromInstruction(insn, 2, 1) << 5;
12826 tmp |= fieldFromInstruction(insn, 16, 5);
12827 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12828 tmp = 0x0;
12829 tmp |= fieldFromInstruction(insn, 1, 1) << 5;
12830 tmp |= fieldFromInstruction(insn, 11, 5);
12831 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12832 tmp = fieldFromInstruction(insn, 36, 4);
12833 if (!Check(S, decodeUImmOperand<4>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12834 tmp = fieldFromInstruction(insn, 32, 4);
12835 if (!Check(S, decodeUImmOperand<4>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12836 return S;
12837 case 324:
12838 tmp = fieldFromInstruction(insn, 23, 3);
12839 if (!Check(S, DecodeACCRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12840 tmp = fieldFromInstruction(insn, 23, 3);
12841 if (!Check(S, DecodeACCRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12842 tmp = 0x0;
12843 tmp |= fieldFromInstruction(insn, 2, 1) << 5;
12844 tmp |= fieldFromInstruction(insn, 16, 5);
12845 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12846 tmp = 0x0;
12847 tmp |= fieldFromInstruction(insn, 1, 1) << 5;
12848 tmp |= fieldFromInstruction(insn, 11, 5);
12849 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12850 tmp = fieldFromInstruction(insn, 36, 4);
12851 if (!Check(S, decodeUImmOperand<4>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12852 tmp = fieldFromInstruction(insn, 32, 4);
12853 if (!Check(S, decodeUImmOperand<4>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12854 tmp = fieldFromInstruction(insn, 40, 8);
12855 if (!Check(S, decodeUImmOperand<8>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12856 return S;
12857 case 325:
12858 tmp = fieldFromInstruction(insn, 23, 3);
12859 if (!Check(S, DecodeACCRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12860 tmp = 0x0;
12861 tmp |= fieldFromInstruction(insn, 2, 1) << 5;
12862 tmp |= fieldFromInstruction(insn, 16, 5);
12863 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12864 tmp = 0x0;
12865 tmp |= fieldFromInstruction(insn, 1, 1) << 5;
12866 tmp |= fieldFromInstruction(insn, 11, 5);
12867 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12868 tmp = fieldFromInstruction(insn, 36, 4);
12869 if (!Check(S, decodeUImmOperand<4>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12870 tmp = fieldFromInstruction(insn, 32, 4);
12871 if (!Check(S, decodeUImmOperand<4>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12872 tmp = fieldFromInstruction(insn, 40, 8);
12873 if (!Check(S, decodeUImmOperand<8>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12874 return S;
12875 case 326:
12876 tmp = fieldFromInstruction(insn, 23, 3);
12877 if (!Check(S, DecodeACCRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12878 tmp = fieldFromInstruction(insn, 23, 3);
12879 if (!Check(S, DecodeACCRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12880 tmp = 0x0;
12881 tmp |= fieldFromInstruction(insn, 2, 1) << 5;
12882 tmp |= fieldFromInstruction(insn, 16, 5);
12883 if (!Check(S, decodeVSRpEvenOperands(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12884 tmp = 0x0;
12885 tmp |= fieldFromInstruction(insn, 1, 1) << 5;
12886 tmp |= fieldFromInstruction(insn, 11, 5);
12887 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12888 tmp = fieldFromInstruction(insn, 36, 4);
12889 if (!Check(S, decodeUImmOperand<4>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12890 tmp = fieldFromInstruction(insn, 34, 2);
12891 if (!Check(S, decodeUImmOperand<2>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12892 return S;
12893 case 327:
12894 tmp = fieldFromInstruction(insn, 23, 3);
12895 if (!Check(S, DecodeACCRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12896 tmp = 0x0;
12897 tmp |= fieldFromInstruction(insn, 2, 1) << 5;
12898 tmp |= fieldFromInstruction(insn, 16, 5);
12899 if (!Check(S, decodeVSRpEvenOperands(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12900 tmp = 0x0;
12901 tmp |= fieldFromInstruction(insn, 1, 1) << 5;
12902 tmp |= fieldFromInstruction(insn, 11, 5);
12903 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12904 tmp = fieldFromInstruction(insn, 36, 4);
12905 if (!Check(S, decodeUImmOperand<4>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12906 tmp = fieldFromInstruction(insn, 34, 2);
12907 if (!Check(S, decodeUImmOperand<2>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12908 return S;
12909 case 328:
12910 tmp = fieldFromInstruction(insn, 23, 3);
12911 if (!Check(S, DecodeDMRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12912 tmp = fieldFromInstruction(insn, 23, 3);
12913 if (!Check(S, DecodeDMRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12914 tmp = 0x0;
12915 tmp |= fieldFromInstruction(insn, 2, 1) << 4;
12916 tmp |= fieldFromInstruction(insn, 17, 4);
12917 if (!Check(S, DecodeVSRpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12918 tmp = 0x0;
12919 tmp |= fieldFromInstruction(insn, 1, 1) << 5;
12920 tmp |= fieldFromInstruction(insn, 11, 5);
12921 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12922 tmp = fieldFromInstruction(insn, 36, 8);
12923 if (!Check(S, decodeUImmOperand<8>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12924 tmp = fieldFromInstruction(insn, 32, 4);
12925 if (!Check(S, decodeUImmOperand<4>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12926 tmp = fieldFromInstruction(insn, 46, 2);
12927 if (!Check(S, decodeUImmOperand<2>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12928 return S;
12929 case 329:
12930 tmp = fieldFromInstruction(insn, 23, 3);
12931 if (!Check(S, DecodeDMRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12932 tmp = 0x0;
12933 tmp |= fieldFromInstruction(insn, 2, 1) << 4;
12934 tmp |= fieldFromInstruction(insn, 17, 4);
12935 if (!Check(S, DecodeVSRpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12936 tmp = 0x0;
12937 tmp |= fieldFromInstruction(insn, 1, 1) << 5;
12938 tmp |= fieldFromInstruction(insn, 11, 5);
12939 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12940 tmp = fieldFromInstruction(insn, 36, 8);
12941 if (!Check(S, decodeUImmOperand<8>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12942 tmp = fieldFromInstruction(insn, 32, 4);
12943 if (!Check(S, decodeUImmOperand<4>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12944 tmp = fieldFromInstruction(insn, 46, 2);
12945 if (!Check(S, decodeUImmOperand<2>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12946 return S;
12947 }
12948}
12949
12950template <typename InsnType>
12951static DecodeStatus decodeInstruction(const uint8_t DecodeTable[], MCInst &MI,
12952 InsnType insn, uint64_t Address,
12953 const MCDisassembler *DisAsm,
12954 const MCSubtargetInfo &STI) {
12955 const uint8_t *Ptr = DecodeTable;
12956
12957 SmallVector<const uint8_t *, 8> ScopeStack;
12958 DecodeStatus S = MCDisassembler::Success;
12959 while (true) {
12960 ptrdiff_t Loc = Ptr - DecodeTable;
12961 const uint8_t DecoderOp = *Ptr++;
12962 switch (DecoderOp) {
12963 default:
12964 errs() << Loc << ": Unexpected decode table opcode: "
12965 << (int)DecoderOp << '\n';
12966 return MCDisassembler::Fail;
12967 case OPC_Scope: {
12968 unsigned NumToSkip = decodeULEB128AndIncUnsafe(p&: Ptr);
12969 const uint8_t *SkipTo = Ptr + NumToSkip;
12970 ScopeStack.push_back(Elt: SkipTo);
12971 LLVM_DEBUG(dbgs() << Loc << ": OPC_Scope(" << SkipTo - DecodeTable
12972 << ")\n");
12973 continue;
12974 }
12975 case OPC_SwitchField: {
12976 // Decode the start value.
12977 unsigned Start = decodeULEB128AndIncUnsafe(p&: Ptr);
12978 unsigned Len = *Ptr++;
12979 uint64_t FieldValue = fieldFromInstruction(insn, Start, Len);
12980 uint64_t CaseValue;
12981 unsigned CaseSize;
12982 while (true) {
12983 CaseValue = decodeULEB128AndIncUnsafe(p&: Ptr);
12984 CaseSize = decodeULEB128AndIncUnsafe(p&: Ptr);
12985 if (FieldValue == CaseValue || !CaseSize)
12986 break;
12987 Ptr += CaseSize;
12988 }
12989 if (FieldValue == CaseValue) {
12990 LLVM_DEBUG(dbgs() << Loc << ": OPC_SwitchField(" << Start << ", " << Len
12991 << "): " << FieldValue << '\n');
12992 continue;
12993 }
12994 break;
12995 }
12996 case OPC_CheckField: {
12997 // Decode the start value.
12998 unsigned Start = decodeULEB128AndIncUnsafe(p&: Ptr);
12999 unsigned Len = *Ptr;
13000 uint64_t FieldValue = fieldFromInstruction(insn, Start, Len);
13001 // Decode the field value.
13002 unsigned PtrLen = 0;
13003 uint64_t ExpectedValue = decodeULEB128(p: ++Ptr, n: &PtrLen);
13004 Ptr += PtrLen;
13005 bool Failed = ExpectedValue != FieldValue;
13006
13007 LLVM_DEBUG(dbgs() << Loc << ": OPC_CheckField(" << Start << ", " << Len
13008 << ", " << ExpectedValue << "): FieldValue = "
13009 << FieldValue << ", ExpectedValue = " << ExpectedValue
13010 << ": " << (Failed ? "FAIL, " : "PASS\n"););
13011 if (!Failed)
13012 continue;
13013 break;
13014 }
13015 case OPC_Decode: {
13016 // Decode the Opcode value.
13017 unsigned Opc = decodeULEB128AndIncUnsafe(p&: Ptr);
13018 unsigned DecodeIdx = decodeULEB128AndIncUnsafe(p&: Ptr);
13019
13020 MI.clear();
13021 MI.setOpcode(Opc);
13022 bool DecodeComplete;
13023 S = decodeToMCInst(DecodeIdx, S, insn, MI, Address, DisAsm,
13024 DecodeComplete);
13025 LLVM_DEBUG(dbgs() << Loc << ": OPC_Decode: opcode " << Opc
13026 << ", using decoder " << DecodeIdx << ": "
13027 << (S ? "PASS, " : "FAIL, "));
13028
13029 if (DecodeComplete) {
13030 LLVM_DEBUG(dbgs() << "decoding complete\n");
13031 return S;
13032 }
13033 assert(S == MCDisassembler::Fail);
13034 // Reset decode status. This also drops a SoftFail status that could be
13035 // set before the decode attempt.
13036 S = MCDisassembler::Success;
13037 break;
13038 }
13039 }
13040 if (ScopeStack.empty()) {
13041 LLVM_DEBUG(dbgs() << "returning Fail\n");
13042 return MCDisassembler::Fail;
13043 }
13044 Ptr = ScopeStack.pop_back_val();
13045 LLVM_DEBUG(dbgs() << "continuing at " << Ptr - DecodeTable << '\n');
13046 }
13047 llvm_unreachable("bogosity detected in disassembler state machine!");
13048}
13049
13050
13051} // namespace
13052