1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* * PPC Disassembler *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9
10#include "llvm/MC/MCInst.h"
11#include "llvm/MC/MCSubtargetInfo.h"
12#include "llvm/Support/DataTypes.h"
13#include "llvm/Support/Debug.h"
14#include "llvm/Support/LEB128.h"
15#include "llvm/Support/raw_ostream.h"
16#include "llvm/TargetParser/SubtargetFeature.h"
17#include <assert.h>
18
19namespace {
20
21// InsnBitWidth is essentially a type trait used by the decoder emitter to query
22// the supported bitwidth for a given type. But default, the value is 0, making
23// it an invalid type for use as `InsnType` when instantiating the decoder.
24// Individual targets are expected to provide specializations for these based
25// on their usage.
26template <typename T> constexpr uint32_t InsnBitWidth = 0;
27
28[[maybe_unused]]
29static DecodeStatus Decodeppc_ptr_rcRegClassByHwMode(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder) {
30 switch (Decoder->getSubtargetInfo().getHwMode(type: MCSubtargetInfo::HwMode_RegInfo)) {
31 case 0: // DefaultMode
32 return DecodeGPRCRegisterClass(Inst, RegNo: Imm, Address: Addr, Decoder);
33 case 1: // PPC64
34 return DecodeG8RCRegisterClass(Inst, RegNo: Imm, Address: Addr, Decoder);
35 default:
36 llvm_unreachable("no decoder for hwmode");
37 }
38}
39
40[[maybe_unused]]
41static DecodeStatus Decodeptr_rc_idx_by_hwmodeRegClassByHwMode(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder) {
42 switch (Decoder->getSubtargetInfo().getHwMode(type: MCSubtargetInfo::HwMode_RegInfo)) {
43 case 0: // DefaultMode
44 return DecodeGPRCRegisterClass(Inst, RegNo: Imm, Address: Addr, Decoder);
45 case 1: // PPC64
46 return DecodeG8RCRegisterClass(Inst, RegNo: Imm, Address: Addr, Decoder);
47 default:
48 llvm_unreachable("no decoder for hwmode");
49 }
50}
51
52[[maybe_unused]]
53static DecodeStatus Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder) {
54 switch (Decoder->getSubtargetInfo().getHwMode(type: MCSubtargetInfo::HwMode_RegInfo)) {
55 case 0: // DefaultMode
56 return DecodeGPRC_NOR0RegisterClass(Inst, RegNo: Imm, Address: Addr, Decoder);
57 case 1: // PPC64
58 return DecodeG8RC_NOX0RegisterClass(Inst, RegNo: Imm, Address: Addr, Decoder);
59 default:
60 llvm_unreachable("no decoder for hwmode");
61 }
62}
63
64
65static const uint8_t DecoderTable32[16429] = {
66 OPC_SwitchField, 26, 6, // 0: switch Inst[31:26] {
67 0, 9, // 3: case 0x0: {
68 OPC_CheckField, 1, 10, 128, 2, // 5: check Inst[10:1] == 0x100
69 OPC_Decode, 170, 4, 0, // 10: decode to ATTN using decoder 0
70 // 10: }
71 2, 4, // 14: case 0x2: {
72 OPC_Decode, 247, 16, 1, // 16: decode to TDI using decoder 1
73 // 16: }
74 3, 4, // 20: case 0x3: {
75 OPC_Decode, 151, 17, 2, // 22: decode to TWI using decoder 2
76 // 22: }
77 4, 186, 31, // 26: case 0x4: {
78 OPC_SwitchField, 1, 5, // 29: switch Inst[5:1] {
79 0, 215, 3, // 32: case 0x0: {
80 OPC_SwitchField, 6, 3, // 35: switch Inst[8:6] {
81 0, 68, // 38: case 0x0: {
82 OPC_SwitchField, 0, 1, // 40: switch Inst[0] {
83 0, 27, // 43: case 0x0: {
84 OPC_SwitchField, 9, 2, // 45: switch Inst[10:9] {
85 0, 4, // 48: case 0x0: {
86 OPC_Decode, 165, 17, 3, // 50: decode to VADDUBM using decoder 3
87 // 50: }
88 1, 4, // 54: case 0x1: {
89 OPC_Decode, 166, 17, 3, // 56: decode to VADDUBS using decoder 3
90 // 56: }
91 2, 4, // 60: case 0x2: {
92 OPC_Decode, 133, 20, 3, // 62: decode to VSUBUBM using decoder 3
93 // 62: }
94 3, 0, // 66: case 0x3: {
95 OPC_Decode, 134, 20, 3, // 68: decode to VSUBUBS using decoder 3
96 // 68: }
97 // 68: } // switch Inst[10:9]
98 // 68: }
99 1, 0, // 72: case 0x1: {
100 OPC_SwitchField, 10, 1, // 74: switch Inst[10] {
101 0, 23, // 77: case 0x0: {
102 OPC_SwitchField, 9, 1, // 79: switch Inst[9] {
103 0, 8, // 82: case 0x0: {
104 OPC_CheckField, 11, 5, 0, // 84: check Inst[15:11] == 0x0
105 OPC_Decode, 128, 19, 4, // 88: decode to VMUL10CUQ using decoder 4
106 // 88: }
107 1, 0, // 92: case 0x1: {
108 OPC_CheckField, 11, 5, 0, // 94: check Inst[15:11] == 0x0
109 OPC_Decode, 131, 19, 4, // 98: decode to VMUL10UQ using decoder 4
110 // 98: }
111 // 98: } // switch Inst[9]
112 // 98: }
113 1, 0, // 102: case 0x1: {
114 OPC_Decode, 192, 4, 5, // 104: decode to BCDADD_rec using decoder 5
115 // 104: }
116 // 104: } // switch Inst[10]
117 // 104: }
118 // 104: } // switch Inst[0]
119 // 104: }
120 1, 60, // 108: case 0x1: {
121 OPC_SwitchField, 0, 1, // 110: switch Inst[0] {
122 0, 27, // 113: case 0x0: {
123 OPC_SwitchField, 9, 2, // 115: switch Inst[10:9] {
124 0, 4, // 118: case 0x0: {
125 OPC_Decode, 168, 17, 3, // 120: decode to VADDUHM using decoder 3
126 // 120: }
127 1, 4, // 124: case 0x1: {
128 OPC_Decode, 169, 17, 3, // 126: decode to VADDUHS using decoder 3
129 // 126: }
130 2, 4, // 130: case 0x2: {
131 OPC_Decode, 136, 20, 3, // 132: decode to VSUBUHM using decoder 3
132 // 132: }
133 3, 0, // 136: case 0x3: {
134 OPC_Decode, 137, 20, 3, // 138: decode to VSUBUHS using decoder 3
135 // 138: }
136 // 138: } // switch Inst[10:9]
137 // 138: }
138 1, 0, // 142: case 0x1: {
139 OPC_SwitchField, 10, 1, // 144: switch Inst[10] {
140 0, 15, // 147: case 0x0: {
141 OPC_SwitchField, 9, 1, // 149: switch Inst[9] {
142 0, 4, // 152: case 0x0: {
143 OPC_Decode, 129, 19, 3, // 154: decode to VMUL10ECUQ using decoder 3
144 // 154: }
145 1, 0, // 158: case 0x1: {
146 OPC_Decode, 130, 19, 3, // 160: decode to VMUL10EUQ using decoder 3
147 // 160: }
148 // 160: } // switch Inst[9]
149 // 160: }
150 1, 0, // 164: case 0x1: {
151 OPC_Decode, 202, 4, 5, // 166: decode to BCDSUB_rec using decoder 5
152 // 166: }
153 // 166: } // switch Inst[10]
154 // 166: }
155 // 166: } // switch Inst[0]
156 // 166: }
157 2, 50, // 170: case 0x2: {
158 OPC_SwitchField, 9, 2, // 172: switch Inst[10:9] {
159 0, 8, // 175: case 0x0: {
160 OPC_CheckField, 0, 1, 0, // 177: check Inst[0] == 0x0
161 OPC_Decode, 171, 17, 3, // 181: decode to VADDUWM using decoder 3
162 // 181: }
163 1, 8, // 185: case 0x1: {
164 OPC_CheckField, 0, 1, 0, // 187: check Inst[0] == 0x0
165 OPC_Decode, 172, 17, 3, // 191: decode to VADDUWS using decoder 3
166 // 191: }
167 2, 15, // 195: case 0x2: {
168 OPC_SwitchField, 0, 1, // 197: switch Inst[0] {
169 0, 4, // 200: case 0x0: {
170 OPC_Decode, 139, 20, 3, // 202: decode to VSUBUWM using decoder 3
171 // 202: }
172 1, 0, // 206: case 0x1: {
173 OPC_Decode, 205, 4, 3, // 208: decode to BCDUS_rec using decoder 3
174 // 208: }
175 // 208: } // switch Inst[0]
176 // 208: }
177 3, 0, // 212: case 0x3: {
178 OPC_CheckField, 0, 1, 0, // 214: check Inst[0] == 0x0
179 OPC_Decode, 140, 20, 3, // 218: decode to VSUBUWS using decoder 3
180 // 218: }
181 // 218: } // switch Inst[10:9]
182 // 218: }
183 3, 30, // 222: case 0x3: {
184 OPC_SwitchField, 0, 1, // 224: switch Inst[0] {
185 0, 15, // 227: case 0x0: {
186 OPC_SwitchField, 9, 2, // 229: switch Inst[10:9] {
187 0, 4, // 232: case 0x0: {
188 OPC_Decode, 167, 17, 3, // 234: decode to VADDUDM using decoder 3
189 // 234: }
190 2, 0, // 238: case 0x2: {
191 OPC_Decode, 135, 20, 3, // 240: decode to VSUBUDM using decoder 3
192 // 240: }
193 // 240: } // switch Inst[10:9]
194 // 240: }
195 1, 0, // 244: case 0x1: {
196 OPC_CheckField, 10, 1, 1, // 246: check Inst[10] == 0x1
197 OPC_Decode, 203, 4, 5, // 250: decode to BCDS_rec using decoder 5
198 // 250: }
199 // 250: } // switch Inst[0]
200 // 250: }
201 4, 57, // 254: case 0x4: {
202 OPC_SwitchField, 0, 1, // 256: switch Inst[0] {
203 0, 27, // 259: case 0x0: {
204 OPC_SwitchField, 9, 2, // 261: switch Inst[10:9] {
205 0, 4, // 264: case 0x0: {
206 OPC_Decode, 170, 17, 3, // 266: decode to VADDUQM using decoder 3
207 // 266: }
208 1, 4, // 270: case 0x1: {
209 OPC_Decode, 162, 17, 3, // 272: decode to VADDSBS using decoder 3
210 // 272: }
211 2, 4, // 276: case 0x2: {
212 OPC_Decode, 138, 20, 3, // 278: decode to VSUBUQM using decoder 3
213 // 278: }
214 3, 0, // 282: case 0x3: {
215 OPC_Decode, 130, 20, 3, // 284: decode to VSUBSBS using decoder 3
216 // 284: }
217 // 284: } // switch Inst[10:9]
218 // 284: }
219 1, 0, // 288: case 0x1: {
220 OPC_SwitchField, 10, 1, // 290: switch Inst[10] {
221 0, 12, // 293: case 0x0: {
222 OPC_CheckField, 21, 2, 0, // 295: check Inst[22:21] == 0x0
223 OPC_CheckField, 9, 1, 0, // 299: check Inst[9] == 0x0
224 OPC_Decode, 249, 17, 6, // 303: decode to VCMPUQ using decoder 6
225 // 303: }
226 1, 0, // 307: case 0x1: {
227 OPC_Decode, 204, 4, 5, // 309: decode to BCDTRUNC_rec using decoder 5
228 // 309: }
229 // 309: } // switch Inst[10]
230 // 309: }
231 // 309: } // switch Inst[0]
232 // 309: }
233 5, 68, // 313: case 0x5: {
234 OPC_SwitchField, 9, 2, // 315: switch Inst[10:9] {
235 0, 19, // 318: case 0x0: {
236 OPC_SwitchField, 0, 1, // 320: switch Inst[0] {
237 0, 4, // 323: case 0x0: {
238 OPC_Decode, 157, 17, 3, // 325: decode to VADDCUQ using decoder 3
239 // 325: }
240 1, 0, // 329: case 0x1: {
241 OPC_CheckField, 21, 2, 0, // 331: check Inst[22:21] == 0x0
242 OPC_Decode, 248, 17, 6, // 335: decode to VCMPSQ using decoder 6
243 // 335: }
244 // 335: } // switch Inst[0]
245 // 335: }
246 1, 15, // 339: case 0x1: {
247 OPC_SwitchField, 0, 1, // 341: switch Inst[0] {
248 0, 4, // 344: case 0x0: {
249 OPC_Decode, 163, 17, 3, // 346: decode to VADDSHS using decoder 3
250 // 346: }
251 1, 0, // 350: case 0x1: {
252 OPC_Decode, 196, 4, 3, // 352: decode to BCDCPSGN_rec using decoder 3
253 // 352: }
254 // 352: } // switch Inst[0]
255 // 352: }
256 2, 15, // 356: case 0x2: {
257 OPC_SwitchField, 0, 1, // 358: switch Inst[0] {
258 0, 4, // 361: case 0x0: {
259 OPC_Decode, 253, 19, 3, // 363: decode to VSUBCUQ using decoder 3
260 // 363: }
261 1, 0, // 367: case 0x1: {
262 OPC_Decode, 206, 4, 3, // 369: decode to BCDUTRUNC_rec using decoder 3
263 // 369: }
264 // 369: } // switch Inst[0]
265 // 369: }
266 3, 0, // 373: case 0x3: {
267 OPC_CheckField, 0, 1, 0, // 375: check Inst[0] == 0x0
268 OPC_Decode, 131, 20, 3, // 379: decode to VSUBSHS using decoder 3
269 // 379: }
270 // 379: } // switch Inst[10:9]
271 // 379: }
272 6, 107, // 383: case 0x6: {
273 OPC_SwitchField, 0, 1, // 385: switch Inst[0] {
274 0, 27, // 388: case 0x0: {
275 OPC_SwitchField, 9, 2, // 390: switch Inst[10:9] {
276 0, 4, // 393: case 0x0: {
277 OPC_Decode, 158, 17, 3, // 395: decode to VADDCUW using decoder 3
278 // 395: }
279 1, 4, // 399: case 0x1: {
280 OPC_Decode, 164, 17, 3, // 401: decode to VADDSWS using decoder 3
281 // 401: }
282 2, 4, // 405: case 0x2: {
283 OPC_Decode, 254, 19, 3, // 407: decode to VSUBCUW using decoder 3
284 // 407: }
285 3, 0, // 411: case 0x3: {
286 OPC_Decode, 132, 20, 3, // 413: decode to VSUBSWS using decoder 3
287 // 413: }
288 // 413: } // switch Inst[10:9]
289 // 413: }
290 1, 0, // 417: case 0x1: {
291 OPC_SwitchField, 16, 5, // 419: switch Inst[20:16] {
292 0, 8, // 422: case 0x0: {
293 OPC_CheckField, 9, 2, 2, // 424: check Inst[10:9] == 0x2
294 OPC_Decode, 198, 4, 7, // 428: decode to BCDCTSQ_rec using decoder 7
295 // 428: }
296 2, 8, // 432: case 0x2: {
297 OPC_CheckField, 10, 1, 1, // 434: check Inst[10] == 0x1
298 OPC_Decode, 194, 4, 8, // 438: decode to BCDCFSQ_rec using decoder 8
299 // 438: }
300 4, 8, // 442: case 0x4: {
301 OPC_CheckField, 10, 1, 1, // 444: check Inst[10] == 0x1
302 OPC_Decode, 199, 4, 8, // 448: decode to BCDCTZ_rec using decoder 8
303 // 448: }
304 5, 8, // 452: case 0x5: {
305 OPC_CheckField, 9, 2, 2, // 454: check Inst[10:9] == 0x2
306 OPC_Decode, 197, 4, 7, // 458: decode to BCDCTN_rec using decoder 7
307 // 458: }
308 6, 8, // 462: case 0x6: {
309 OPC_CheckField, 10, 1, 1, // 464: check Inst[10] == 0x1
310 OPC_Decode, 195, 4, 8, // 468: decode to BCDCFZ_rec using decoder 8
311 // 468: }
312 7, 8, // 472: case 0x7: {
313 OPC_CheckField, 10, 1, 1, // 474: check Inst[10] == 0x1
314 OPC_Decode, 193, 4, 8, // 478: decode to BCDCFN_rec using decoder 8
315 // 478: }
316 31, 0, // 482: case 0x1f: {
317 OPC_CheckField, 10, 1, 1, // 484: check Inst[10] == 0x1
318 OPC_Decode, 200, 4, 8, // 488: decode to BCDSETSGN_rec using decoder 8
319 // 488: }
320 // 488: } // switch Inst[20:16]
321 // 488: }
322 // 488: } // switch Inst[0]
323 // 488: }
324 7, 0, // 492: case 0x7: {
325 OPC_CheckField, 10, 1, 1, // 494: check Inst[10] == 0x1
326 OPC_CheckField, 0, 1, 1, // 498: check Inst[0] == 0x1
327 OPC_Decode, 201, 4, 5, // 502: decode to BCDSR_rec using decoder 5
328 // 502: }
329 // 502: } // switch Inst[8:6]
330 // 502: }
331 1, 237, 6, // 506: case 0x1: {
332 OPC_SwitchField, 6, 5, // 509: switch Inst[10:6] {
333 0, 15, // 512: case 0x0: {
334 OPC_SwitchField, 0, 1, // 514: switch Inst[0] {
335 0, 4, // 517: case 0x0: {
336 OPC_Decode, 218, 18, 3, // 519: decode to VMAXUB using decoder 3
337 // 519: }
338 1, 0, // 523: case 0x1: {
339 OPC_Decode, 148, 20, 3, // 525: decode to VUCMPRHN using decoder 3
340 // 525: }
341 // 525: } // switch Inst[0]
342 // 525: }
343 1, 15, // 529: case 0x1: {
344 OPC_SwitchField, 0, 1, // 531: switch Inst[0] {
345 0, 4, // 534: case 0x0: {
346 OPC_Decode, 220, 18, 3, // 536: decode to VMAXUH using decoder 3
347 // 536: }
348 1, 0, // 540: case 0x1: {
349 OPC_Decode, 151, 20, 3, // 542: decode to VUCMPRLN using decoder 3
350 // 542: }
351 // 542: } // switch Inst[0]
352 // 542: }
353 2, 15, // 546: case 0x2: {
354 OPC_SwitchField, 0, 1, // 548: switch Inst[0] {
355 0, 4, // 551: case 0x0: {
356 OPC_Decode, 221, 18, 3, // 553: decode to VMAXUW using decoder 3
357 // 553: }
358 1, 0, // 557: case 0x1: {
359 OPC_Decode, 146, 20, 3, // 559: decode to VUCMPRHB using decoder 3
360 // 559: }
361 // 559: } // switch Inst[0]
362 // 559: }
363 3, 15, // 563: case 0x3: {
364 OPC_SwitchField, 0, 1, // 565: switch Inst[0] {
365 0, 4, // 568: case 0x0: {
366 OPC_Decode, 219, 18, 3, // 570: decode to VMAXUD using decoder 3
367 // 570: }
368 1, 0, // 574: case 0x1: {
369 OPC_Decode, 149, 20, 3, // 576: decode to VUCMPRLB using decoder 3
370 // 576: }
371 // 576: } // switch Inst[0]
372 // 576: }
373 4, 15, // 580: case 0x4: {
374 OPC_SwitchField, 0, 1, // 582: switch Inst[0] {
375 0, 4, // 585: case 0x0: {
376 OPC_Decode, 214, 18, 3, // 587: decode to VMAXSB using decoder 3
377 // 587: }
378 1, 0, // 591: case 0x1: {
379 OPC_Decode, 147, 20, 3, // 593: decode to VUCMPRHH using decoder 3
380 // 593: }
381 // 593: } // switch Inst[0]
382 // 593: }
383 5, 15, // 597: case 0x5: {
384 OPC_SwitchField, 0, 1, // 599: switch Inst[0] {
385 0, 4, // 602: case 0x0: {
386 OPC_Decode, 216, 18, 3, // 604: decode to VMAXSH using decoder 3
387 // 604: }
388 1, 0, // 608: case 0x1: {
389 OPC_Decode, 150, 20, 3, // 610: decode to VUCMPRLH using decoder 3
390 // 610: }
391 // 610: } // switch Inst[0]
392 // 610: }
393 6, 65, // 614: case 0x6: {
394 OPC_SwitchField, 0, 1, // 616: switch Inst[0] {
395 0, 4, // 619: case 0x0: {
396 OPC_Decode, 217, 18, 3, // 621: decode to VMAXSW using decoder 3
397 // 621: }
398 1, 0, // 625: case 0x1: {
399 OPC_SwitchField, 19, 2, // 627: switch Inst[20:19] {
400 0, 26, // 630: case 0x0: {
401 OPC_SwitchField, 17, 2, // 632: switch Inst[18:17] {
402 0, 15, // 635: case 0x0: {
403 OPC_SwitchField, 16, 1, // 637: switch Inst[16] {
404 0, 4, // 640: case 0x0: {
405 OPC_Decode, 155, 20, 7, // 642: decode to VUPKHSNTOB using decoder 7
406 // 642: }
407 1, 0, // 646: case 0x1: {
408 OPC_Decode, 164, 20, 7, // 648: decode to VUPKLSNTOB using decoder 7
409 // 648: }
410 // 648: } // switch Inst[16]
411 // 648: }
412 1, 0, // 652: case 0x1: {
413 OPC_Decode, 159, 20, 9, // 654: decode to VUPKINT8TOBF16 using decoder 9
414 // 654: }
415 // 654: } // switch Inst[18:17]
416 // 654: }
417 1, 15, // 658: case 0x1: {
418 OPC_SwitchField, 18, 1, // 660: switch Inst[18] {
419 0, 4, // 663: case 0x0: {
420 OPC_Decode, 157, 20, 10, // 665: decode to VUPKINT4TOBF16 using decoder 10
421 // 665: }
422 1, 0, // 669: case 0x1: {
423 OPC_Decode, 160, 20, 10, // 671: decode to VUPKINT8TOFP32 using decoder 10
424 // 671: }
425 // 671: } // switch Inst[18]
426 // 671: }
427 2, 0, // 675: case 0x2: {
428 OPC_Decode, 158, 20, 11, // 677: decode to VUPKINT4TOFP32 using decoder 11
429 // 677: }
430 // 677: } // switch Inst[20:19]
431 // 677: }
432 // 677: } // switch Inst[0]
433 // 677: }
434 7, 8, // 681: case 0x7: {
435 OPC_CheckField, 0, 1, 0, // 683: check Inst[0] == 0x0
436 OPC_Decode, 215, 18, 3, // 687: decode to VMAXSD using decoder 3
437 // 687: }
438 8, 8, // 691: case 0x8: {
439 OPC_CheckField, 0, 1, 0, // 693: check Inst[0] == 0x0
440 OPC_Decode, 229, 18, 3, // 697: decode to VMINUB using decoder 3
441 // 697: }
442 9, 8, // 701: case 0x9: {
443 OPC_CheckField, 0, 1, 0, // 703: check Inst[0] == 0x0
444 OPC_Decode, 231, 18, 3, // 707: decode to VMINUH using decoder 3
445 // 707: }
446 10, 8, // 711: case 0xa: {
447 OPC_CheckField, 0, 1, 0, // 713: check Inst[0] == 0x0
448 OPC_Decode, 232, 18, 3, // 717: decode to VMINUW using decoder 3
449 // 717: }
450 11, 8, // 721: case 0xb: {
451 OPC_CheckField, 0, 1, 0, // 723: check Inst[0] == 0x0
452 OPC_Decode, 230, 18, 3, // 727: decode to VMINUD using decoder 3
453 // 727: }
454 12, 8, // 731: case 0xc: {
455 OPC_CheckField, 0, 1, 0, // 733: check Inst[0] == 0x0
456 OPC_Decode, 225, 18, 3, // 737: decode to VMINSB using decoder 3
457 // 737: }
458 13, 8, // 741: case 0xd: {
459 OPC_CheckField, 0, 1, 0, // 743: check Inst[0] == 0x0
460 OPC_Decode, 227, 18, 3, // 747: decode to VMINSH using decoder 3
461 // 747: }
462 14, 8, // 751: case 0xe: {
463 OPC_CheckField, 0, 1, 0, // 753: check Inst[0] == 0x0
464 OPC_Decode, 228, 18, 3, // 757: decode to VMINSW using decoder 3
465 // 757: }
466 15, 8, // 761: case 0xf: {
467 OPC_CheckField, 0, 1, 0, // 763: check Inst[0] == 0x0
468 OPC_Decode, 226, 18, 3, // 767: decode to VMINSD using decoder 3
469 // 767: }
470 16, 15, // 771: case 0x10: {
471 OPC_SwitchField, 0, 1, // 773: switch Inst[0] {
472 0, 4, // 776: case 0x0: {
473 OPC_Decode, 178, 17, 3, // 778: decode to VAVGUB using decoder 3
474 // 778: }
475 1, 0, // 782: case 0x1: {
476 OPC_Decode, 154, 17, 3, // 784: decode to VABSDUB using decoder 3
477 // 784: }
478 // 784: } // switch Inst[0]
479 // 784: }
480 17, 15, // 788: case 0x11: {
481 OPC_SwitchField, 0, 1, // 790: switch Inst[0] {
482 0, 4, // 793: case 0x0: {
483 OPC_Decode, 179, 17, 3, // 795: decode to VAVGUH using decoder 3
484 // 795: }
485 1, 0, // 799: case 0x1: {
486 OPC_Decode, 155, 17, 3, // 801: decode to VABSDUH using decoder 3
487 // 801: }
488 // 801: } // switch Inst[0]
489 // 801: }
490 18, 15, // 805: case 0x12: {
491 OPC_SwitchField, 0, 1, // 807: switch Inst[0] {
492 0, 4, // 810: case 0x0: {
493 OPC_Decode, 180, 17, 3, // 812: decode to VAVGUW using decoder 3
494 // 812: }
495 1, 0, // 816: case 0x1: {
496 OPC_Decode, 156, 17, 3, // 818: decode to VABSDUW using decoder 3
497 // 818: }
498 // 818: } // switch Inst[0]
499 // 818: }
500 20, 8, // 822: case 0x14: {
501 OPC_CheckField, 0, 1, 0, // 824: check Inst[0] == 0x0
502 OPC_Decode, 175, 17, 3, // 828: decode to VAVGSB using decoder 3
503 // 828: }
504 21, 8, // 832: case 0x15: {
505 OPC_CheckField, 0, 1, 0, // 834: check Inst[0] == 0x0
506 OPC_Decode, 176, 17, 3, // 838: decode to VAVGSH using decoder 3
507 // 838: }
508 22, 8, // 842: case 0x16: {
509 OPC_CheckField, 0, 1, 0, // 844: check Inst[0] == 0x0
510 OPC_Decode, 177, 17, 3, // 848: decode to VAVGSW using decoder 3
511 // 848: }
512 24, 173, 1, // 852: case 0x18: {
513 OPC_SwitchField, 16, 5, // 855: switch Inst[20:16] {
514 0, 8, // 858: case 0x0: {
515 OPC_CheckField, 0, 1, 0, // 860: check Inst[0] == 0x0
516 OPC_Decode, 196, 17, 12, // 864: decode to VCLZLSBB using decoder 12
517 // 864: }
518 1, 8, // 868: case 0x1: {
519 OPC_CheckField, 0, 1, 0, // 870: check Inst[0] == 0x0
520 OPC_Decode, 134, 18, 12, // 874: decode to VCTZLSBB using decoder 12
521 // 874: }
522 6, 8, // 878: case 0x6: {
523 OPC_CheckField, 0, 1, 0, // 880: check Inst[0] == 0x0
524 OPC_Decode, 158, 19, 7, // 884: decode to VNEGW using decoder 7
525 // 884: }
526 7, 8, // 888: case 0x7: {
527 OPC_CheckField, 0, 1, 0, // 890: check Inst[0] == 0x0
528 OPC_Decode, 157, 19, 7, // 894: decode to VNEGD using decoder 7
529 // 894: }
530 8, 8, // 898: case 0x8: {
531 OPC_CheckField, 0, 1, 0, // 900: check Inst[0] == 0x0
532 OPC_Decode, 191, 19, 7, // 904: decode to VPRTYBW using decoder 7
533 // 904: }
534 9, 8, // 908: case 0x9: {
535 OPC_CheckField, 0, 1, 0, // 910: check Inst[0] == 0x0
536 OPC_Decode, 189, 19, 7, // 914: decode to VPRTYBD using decoder 7
537 // 914: }
538 10, 8, // 918: case 0xa: {
539 OPC_CheckField, 0, 1, 0, // 920: check Inst[0] == 0x0
540 OPC_Decode, 190, 19, 7, // 924: decode to VPRTYBQ using decoder 7
541 // 924: }
542 16, 8, // 928: case 0x10: {
543 OPC_CheckField, 0, 1, 0, // 930: check Inst[0] == 0x0
544 OPC_Decode, 174, 18, 7, // 934: decode to VEXTSB2W using decoder 7
545 // 934: }
546 17, 8, // 938: case 0x11: {
547 OPC_CheckField, 0, 1, 0, // 940: check Inst[0] == 0x0
548 OPC_Decode, 179, 18, 7, // 944: decode to VEXTSH2W using decoder 7
549 // 944: }
550 24, 8, // 948: case 0x18: {
551 OPC_CheckField, 0, 1, 0, // 950: check Inst[0] == 0x0
552 OPC_Decode, 172, 18, 7, // 954: decode to VEXTSB2D using decoder 7
553 // 954: }
554 25, 8, // 958: case 0x19: {
555 OPC_CheckField, 0, 1, 0, // 960: check Inst[0] == 0x0
556 OPC_Decode, 177, 18, 7, // 964: decode to VEXTSH2D using decoder 7
557 // 964: }
558 26, 8, // 968: case 0x1a: {
559 OPC_CheckField, 0, 1, 0, // 970: check Inst[0] == 0x0
560 OPC_Decode, 181, 18, 7, // 974: decode to VEXTSW2D using decoder 7
561 // 974: }
562 27, 8, // 978: case 0x1b: {
563 OPC_CheckField, 0, 1, 0, // 980: check Inst[0] == 0x0
564 OPC_Decode, 176, 18, 7, // 984: decode to VEXTSD2Q using decoder 7
565 // 984: }
566 28, 8, // 988: case 0x1c: {
567 OPC_CheckField, 0, 1, 0, // 990: check Inst[0] == 0x0
568 OPC_Decode, 130, 18, 7, // 994: decode to VCTZB using decoder 7
569 // 994: }
570 29, 8, // 998: case 0x1d: {
571 OPC_CheckField, 0, 1, 0, // 1000: check Inst[0] == 0x0
572 OPC_Decode, 133, 18, 7, // 1004: decode to VCTZH using decoder 7
573 // 1004: }
574 30, 8, // 1008: case 0x1e: {
575 OPC_CheckField, 0, 1, 0, // 1010: check Inst[0] == 0x0
576 OPC_Decode, 135, 18, 7, // 1014: decode to VCTZW using decoder 7
577 // 1014: }
578 31, 0, // 1018: case 0x1f: {
579 OPC_CheckField, 0, 1, 0, // 1020: check Inst[0] == 0x0
580 OPC_Decode, 131, 18, 7, // 1024: decode to VCTZD using decoder 7
581 // 1024: }
582 // 1024: } // switch Inst[20:16]
583 // 1024: }
584 25, 235, 1, // 1028: case 0x19: {
585 OPC_SwitchField, 17, 4, // 1031: switch Inst[20:17] {
586 0, 23, // 1034: case 0x0: {
587 OPC_SwitchField, 16, 1, // 1036: switch Inst[16] {
588 0, 8, // 1039: case 0x0: {
589 OPC_CheckField, 0, 1, 0, // 1041: check Inst[0] == 0x0
590 OPC_Decode, 149, 18, 7, // 1045: decode to VEXPANDBM using decoder 7
591 // 1045: }
592 1, 0, // 1049: case 0x1: {
593 OPC_CheckField, 0, 1, 0, // 1051: check Inst[0] == 0x0
594 OPC_Decode, 151, 18, 7, // 1055: decode to VEXPANDHM using decoder 7
595 // 1055: }
596 // 1055: } // switch Inst[16]
597 // 1055: }
598 1, 23, // 1059: case 0x1: {
599 OPC_SwitchField, 16, 1, // 1061: switch Inst[16] {
600 0, 8, // 1064: case 0x0: {
601 OPC_CheckField, 0, 1, 0, // 1066: check Inst[0] == 0x0
602 OPC_Decode, 153, 18, 7, // 1070: decode to VEXPANDWM using decoder 7
603 // 1070: }
604 1, 0, // 1074: case 0x1: {
605 OPC_CheckField, 0, 1, 0, // 1076: check Inst[0] == 0x0
606 OPC_Decode, 150, 18, 7, // 1080: decode to VEXPANDDM using decoder 7
607 // 1080: }
608 // 1080: } // switch Inst[16]
609 // 1080: }
610 2, 12, // 1084: case 0x2: {
611 OPC_CheckField, 16, 1, 0, // 1086: check Inst[16] == 0x0
612 OPC_CheckField, 0, 1, 0, // 1090: check Inst[0] == 0x0
613 OPC_Decode, 152, 18, 7, // 1094: decode to VEXPANDQM using decoder 7
614 // 1094: }
615 4, 23, // 1098: case 0x4: {
616 OPC_SwitchField, 16, 1, // 1100: switch Inst[16] {
617 0, 8, // 1103: case 0x0: {
618 OPC_CheckField, 0, 1, 0, // 1105: check Inst[0] == 0x0
619 OPC_Decode, 163, 18, 12, // 1109: decode to VEXTRACTBM using decoder 12
620 // 1109: }
621 1, 0, // 1113: case 0x1: {
622 OPC_CheckField, 0, 1, 0, // 1115: check Inst[0] == 0x0
623 OPC_Decode, 166, 18, 12, // 1119: decode to VEXTRACTHM using decoder 12
624 // 1119: }
625 // 1119: } // switch Inst[16]
626 // 1119: }
627 5, 23, // 1123: case 0x5: {
628 OPC_SwitchField, 16, 1, // 1125: switch Inst[16] {
629 0, 8, // 1128: case 0x0: {
630 OPC_CheckField, 0, 1, 0, // 1130: check Inst[0] == 0x0
631 OPC_Decode, 171, 18, 12, // 1134: decode to VEXTRACTWM using decoder 12
632 // 1134: }
633 1, 0, // 1138: case 0x1: {
634 OPC_CheckField, 0, 1, 0, // 1140: check Inst[0] == 0x0
635 OPC_Decode, 165, 18, 12, // 1144: decode to VEXTRACTDM using decoder 12
636 // 1144: }
637 // 1144: } // switch Inst[16]
638 // 1144: }
639 6, 12, // 1148: case 0x6: {
640 OPC_CheckField, 16, 1, 0, // 1150: check Inst[16] == 0x0
641 OPC_CheckField, 0, 1, 0, // 1154: check Inst[0] == 0x0
642 OPC_Decode, 167, 18, 12, // 1158: decode to VEXTRACTQM using decoder 12
643 // 1158: }
644 8, 23, // 1162: case 0x8: {
645 OPC_SwitchField, 16, 1, // 1164: switch Inst[16] {
646 0, 8, // 1167: case 0x0: {
647 OPC_CheckField, 0, 1, 0, // 1169: check Inst[0] == 0x0
648 OPC_Decode, 169, 12, 13, // 1173: decode to MTVSRBM using decoder 13
649 // 1173: }
650 1, 0, // 1177: case 0x1: {
651 OPC_CheckField, 0, 1, 0, // 1179: check Inst[0] == 0x0
652 OPC_Decode, 174, 12, 13, // 1183: decode to MTVSRHM using decoder 13
653 // 1183: }
654 // 1183: } // switch Inst[16]
655 // 1183: }
656 9, 23, // 1187: case 0x9: {
657 OPC_SwitchField, 16, 1, // 1189: switch Inst[16] {
658 0, 8, // 1192: case 0x0: {
659 OPC_CheckField, 0, 1, 0, // 1194: check Inst[0] == 0x0
660 OPC_Decode, 177, 12, 13, // 1198: decode to MTVSRWM using decoder 13
661 // 1198: }
662 1, 0, // 1202: case 0x1: {
663 OPC_CheckField, 0, 1, 0, // 1204: check Inst[0] == 0x0
664 OPC_Decode, 173, 12, 13, // 1208: decode to MTVSRDM using decoder 13
665 // 1208: }
666 // 1208: } // switch Inst[16]
667 // 1208: }
668 10, 12, // 1212: case 0xa: {
669 OPC_CheckField, 16, 1, 0, // 1214: check Inst[16] == 0x0
670 OPC_CheckField, 0, 1, 0, // 1218: check Inst[0] == 0x0
671 OPC_Decode, 175, 12, 13, // 1222: decode to MTVSRQM using decoder 13
672 // 1222: }
673 12, 8, // 1226: case 0xc: {
674 OPC_CheckField, 0, 1, 0, // 1228: check Inst[0] == 0x0
675 OPC_Decode, 250, 17, 14, // 1232: decode to VCNTMBB using decoder 14
676 // 1232: }
677 13, 8, // 1236: case 0xd: {
678 OPC_CheckField, 0, 1, 0, // 1238: check Inst[0] == 0x0
679 OPC_Decode, 252, 17, 14, // 1242: decode to VCNTMBH using decoder 14
680 // 1242: }
681 14, 8, // 1246: case 0xe: {
682 OPC_CheckField, 0, 1, 0, // 1248: check Inst[0] == 0x0
683 OPC_Decode, 253, 17, 14, // 1252: decode to VCNTMBW using decoder 14
684 // 1252: }
685 15, 0, // 1256: case 0xf: {
686 OPC_CheckField, 0, 1, 0, // 1258: check Inst[0] == 0x0
687 OPC_Decode, 251, 17, 14, // 1262: decode to VCNTMBD using decoder 14
688 // 1262: }
689 // 1262: } // switch Inst[20:17]
690 // 1262: }
691 26, 8, // 1266: case 0x1a: {
692 OPC_CheckField, 0, 1, 0, // 1268: check Inst[0] == 0x0
693 OPC_Decode, 212, 19, 15, // 1272: decode to VSHASIGMAW using decoder 15
694 // 1272: }
695 27, 8, // 1276: case 0x1b: {
696 OPC_CheckField, 0, 1, 0, // 1278: check Inst[0] == 0x0
697 OPC_Decode, 211, 19, 15, // 1282: decode to VSHASIGMAD using decoder 15
698 // 1282: }
699 28, 23, // 1286: case 0x1c: {
700 OPC_SwitchField, 0, 1, // 1288: switch Inst[0] {
701 0, 8, // 1291: case 0x0: {
702 OPC_CheckField, 16, 5, 0, // 1293: check Inst[20:16] == 0x0
703 OPC_Decode, 192, 17, 7, // 1297: decode to VCLZB using decoder 7
704 // 1297: }
705 1, 0, // 1301: case 0x1: {
706 OPC_CheckField, 16, 5, 0, // 1303: check Inst[20:16] == 0x0
707 OPC_Decode, 185, 19, 7, // 1307: decode to VPOPCNTB using decoder 7
708 // 1307: }
709 // 1307: } // switch Inst[0]
710 // 1307: }
711 29, 23, // 1311: case 0x1d: {
712 OPC_SwitchField, 0, 1, // 1313: switch Inst[0] {
713 0, 8, // 1316: case 0x0: {
714 OPC_CheckField, 16, 5, 0, // 1318: check Inst[20:16] == 0x0
715 OPC_Decode, 195, 17, 7, // 1322: decode to VCLZH using decoder 7
716 // 1322: }
717 1, 0, // 1326: case 0x1: {
718 OPC_CheckField, 16, 5, 0, // 1328: check Inst[20:16] == 0x0
719 OPC_Decode, 187, 19, 7, // 1332: decode to VPOPCNTH using decoder 7
720 // 1332: }
721 // 1332: } // switch Inst[0]
722 // 1332: }
723 30, 23, // 1336: case 0x1e: {
724 OPC_SwitchField, 0, 1, // 1338: switch Inst[0] {
725 0, 8, // 1341: case 0x0: {
726 OPC_CheckField, 16, 5, 0, // 1343: check Inst[20:16] == 0x0
727 OPC_Decode, 197, 17, 7, // 1347: decode to VCLZW using decoder 7
728 // 1347: }
729 1, 0, // 1351: case 0x1: {
730 OPC_CheckField, 16, 5, 0, // 1353: check Inst[20:16] == 0x0
731 OPC_Decode, 188, 19, 7, // 1357: decode to VPOPCNTW using decoder 7
732 // 1357: }
733 // 1357: } // switch Inst[0]
734 // 1357: }
735 31, 0, // 1361: case 0x1f: {
736 OPC_SwitchField, 0, 1, // 1363: switch Inst[0] {
737 0, 8, // 1366: case 0x0: {
738 OPC_CheckField, 16, 5, 0, // 1368: check Inst[20:16] == 0x0
739 OPC_Decode, 193, 17, 7, // 1372: decode to VCLZD using decoder 7
740 // 1372: }
741 1, 0, // 1376: case 0x1: {
742 OPC_CheckField, 16, 5, 0, // 1378: check Inst[20:16] == 0x0
743 OPC_Decode, 186, 19, 7, // 1382: decode to VPOPCNTD using decoder 7
744 // 1382: }
745 // 1382: } // switch Inst[0]
746 // 1382: }
747 // 1382: } // switch Inst[10:6]
748 // 1382: }
749 2, 145, 3, // 1386: case 0x2: {
750 OPC_SwitchField, 6, 5, // 1389: switch Inst[10:6] {
751 0, 15, // 1392: case 0x0: {
752 OPC_SwitchField, 0, 1, // 1394: switch Inst[0] {
753 0, 4, // 1397: case 0x0: {
754 OPC_Decode, 197, 19, 3, // 1399: decode to VRLB using decoder 3
755 // 1399: }
756 1, 0, // 1403: case 0x1: {
757 OPC_Decode, 202, 19, 3, // 1405: decode to VRLQ using decoder 3
758 // 1405: }
759 // 1405: } // switch Inst[0]
760 // 1405: }
761 1, 15, // 1409: case 0x1: {
762 OPC_SwitchField, 0, 1, // 1411: switch Inst[0] {
763 0, 4, // 1414: case 0x0: {
764 OPC_Decode, 201, 19, 3, // 1416: decode to VRLH using decoder 3
765 // 1416: }
766 1, 0, // 1420: case 0x1: {
767 OPC_Decode, 203, 19, 16, // 1422: decode to VRLQMI using decoder 16
768 // 1422: }
769 // 1422: } // switch Inst[0]
770 // 1422: }
771 2, 15, // 1426: case 0x2: {
772 OPC_SwitchField, 0, 1, // 1428: switch Inst[0] {
773 0, 4, // 1431: case 0x0: {
774 OPC_Decode, 205, 19, 3, // 1433: decode to VRLW using decoder 3
775 // 1433: }
776 1, 0, // 1437: case 0x1: {
777 OPC_Decode, 206, 19, 16, // 1439: decode to VRLWMI using decoder 16
778 // 1439: }
779 // 1439: } // switch Inst[0]
780 // 1439: }
781 3, 15, // 1443: case 0x3: {
782 OPC_SwitchField, 0, 1, // 1445: switch Inst[0] {
783 0, 4, // 1448: case 0x0: {
784 OPC_Decode, 198, 19, 3, // 1450: decode to VRLD using decoder 3
785 // 1450: }
786 1, 0, // 1454: case 0x1: {
787 OPC_Decode, 199, 19, 16, // 1456: decode to VRLDMI using decoder 16
788 // 1456: }
789 // 1456: } // switch Inst[0]
790 // 1456: }
791 4, 15, // 1460: case 0x4: {
792 OPC_SwitchField, 0, 1, // 1462: switch Inst[0] {
793 0, 4, // 1465: case 0x0: {
794 OPC_Decode, 214, 19, 3, // 1467: decode to VSLB using decoder 3
795 // 1467: }
796 1, 0, // 1471: case 0x1: {
797 OPC_Decode, 220, 19, 3, // 1473: decode to VSLQ using decoder 3
798 // 1473: }
799 // 1473: } // switch Inst[0]
800 // 1473: }
801 5, 15, // 1477: case 0x5: {
802 OPC_SwitchField, 0, 1, // 1479: switch Inst[0] {
803 0, 4, // 1482: case 0x0: {
804 OPC_Decode, 218, 19, 3, // 1484: decode to VSLH using decoder 3
805 // 1484: }
806 1, 0, // 1488: case 0x1: {
807 OPC_Decode, 204, 19, 3, // 1490: decode to VRLQNM using decoder 3
808 // 1490: }
809 // 1490: } // switch Inst[0]
810 // 1490: }
811 6, 15, // 1494: case 0x6: {
812 OPC_SwitchField, 0, 1, // 1496: switch Inst[0] {
813 0, 4, // 1499: case 0x0: {
814 OPC_Decode, 222, 19, 3, // 1501: decode to VSLW using decoder 3
815 // 1501: }
816 1, 0, // 1505: case 0x1: {
817 OPC_Decode, 207, 19, 3, // 1507: decode to VRLWNM using decoder 3
818 // 1507: }
819 // 1507: } // switch Inst[0]
820 // 1507: }
821 7, 15, // 1511: case 0x7: {
822 OPC_SwitchField, 0, 1, // 1513: switch Inst[0] {
823 0, 4, // 1516: case 0x0: {
824 OPC_Decode, 213, 19, 3, // 1518: decode to VSL using decoder 3
825 // 1518: }
826 1, 0, // 1522: case 0x1: {
827 OPC_Decode, 200, 19, 3, // 1524: decode to VRLDNM using decoder 3
828 // 1524: }
829 // 1524: } // switch Inst[0]
830 // 1524: }
831 8, 15, // 1528: case 0x8: {
832 OPC_SwitchField, 0, 1, // 1530: switch Inst[0] {
833 0, 4, // 1533: case 0x0: {
834 OPC_Decode, 237, 19, 3, // 1535: decode to VSRB using decoder 3
835 // 1535: }
836 1, 0, // 1539: case 0x1: {
837 OPC_Decode, 242, 19, 3, // 1541: decode to VSRQ using decoder 3
838 // 1541: }
839 // 1541: } // switch Inst[0]
840 // 1541: }
841 9, 8, // 1545: case 0x9: {
842 OPC_CheckField, 0, 1, 0, // 1547: check Inst[0] == 0x0
843 OPC_Decode, 240, 19, 3, // 1551: decode to VSRH using decoder 3
844 // 1551: }
845 10, 8, // 1555: case 0xa: {
846 OPC_CheckField, 0, 1, 0, // 1557: check Inst[0] == 0x0
847 OPC_Decode, 244, 19, 3, // 1561: decode to VSRW using decoder 3
848 // 1561: }
849 11, 8, // 1565: case 0xb: {
850 OPC_CheckField, 0, 1, 0, // 1567: check Inst[0] == 0x0
851 OPC_Decode, 231, 19, 3, // 1571: decode to VSR using decoder 3
852 // 1571: }
853 12, 15, // 1575: case 0xc: {
854 OPC_SwitchField, 0, 1, // 1577: switch Inst[0] {
855 0, 4, // 1580: case 0x0: {
856 OPC_Decode, 232, 19, 3, // 1582: decode to VSRAB using decoder 3
857 // 1582: }
858 1, 0, // 1586: case 0x1: {
859 OPC_Decode, 235, 19, 3, // 1588: decode to VSRAQ using decoder 3
860 // 1588: }
861 // 1588: } // switch Inst[0]
862 // 1588: }
863 13, 8, // 1592: case 0xd: {
864 OPC_CheckField, 0, 1, 0, // 1594: check Inst[0] == 0x0
865 OPC_Decode, 234, 19, 3, // 1598: decode to VSRAH using decoder 3
866 // 1598: }
867 14, 8, // 1602: case 0xe: {
868 OPC_CheckField, 0, 1, 0, // 1604: check Inst[0] == 0x0
869 OPC_Decode, 236, 19, 3, // 1608: decode to VSRAW using decoder 3
870 // 1608: }
871 15, 8, // 1612: case 0xf: {
872 OPC_CheckField, 0, 1, 0, // 1614: check Inst[0] == 0x0
873 OPC_Decode, 233, 19, 3, // 1618: decode to VSRAD using decoder 3
874 // 1618: }
875 16, 8, // 1622: case 0x10: {
876 OPC_CheckField, 0, 1, 0, // 1624: check Inst[0] == 0x0
877 OPC_Decode, 173, 17, 3, // 1628: decode to VAND using decoder 3
878 // 1628: }
879 17, 8, // 1632: case 0x11: {
880 OPC_CheckField, 0, 1, 0, // 1634: check Inst[0] == 0x0
881 OPC_Decode, 174, 17, 3, // 1638: decode to VANDC using decoder 3
882 // 1638: }
883 18, 8, // 1642: case 0x12: {
884 OPC_CheckField, 0, 1, 0, // 1644: check Inst[0] == 0x0
885 OPC_Decode, 161, 19, 3, // 1648: decode to VOR using decoder 3
886 // 1648: }
887 19, 8, // 1652: case 0x13: {
888 OPC_CheckField, 0, 1, 0, // 1654: check Inst[0] == 0x0
889 OPC_Decode, 166, 20, 3, // 1658: decode to VXOR using decoder 3
890 // 1658: }
891 20, 8, // 1662: case 0x14: {
892 OPC_CheckField, 0, 1, 0, // 1664: check Inst[0] == 0x0
893 OPC_Decode, 160, 19, 3, // 1668: decode to VNOR using decoder 3
894 // 1668: }
895 21, 8, // 1672: case 0x15: {
896 OPC_CheckField, 0, 1, 0, // 1674: check Inst[0] == 0x0
897 OPC_Decode, 162, 19, 3, // 1678: decode to VORC using decoder 3
898 // 1678: }
899 22, 8, // 1682: case 0x16: {
900 OPC_CheckField, 0, 1, 0, // 1684: check Inst[0] == 0x0
901 OPC_Decode, 154, 19, 3, // 1688: decode to VNAND using decoder 3
902 // 1688: }
903 23, 8, // 1692: case 0x17: {
904 OPC_CheckField, 0, 1, 0, // 1694: check Inst[0] == 0x0
905 OPC_Decode, 215, 19, 3, // 1698: decode to VSLD using decoder 3
906 // 1698: }
907 24, 12, // 1702: case 0x18: {
908 OPC_CheckField, 11, 10, 0, // 1704: check Inst[20:11] == 0x0
909 OPC_CheckField, 0, 1, 0, // 1708: check Inst[0] == 0x0
910 OPC_Decode, 252, 11, 17, // 1712: decode to MFVSCR using decoder 17
911 // 1712: }
912 25, 12, // 1716: case 0x19: {
913 OPC_CheckField, 16, 10, 0, // 1718: check Inst[25:16] == 0x0
914 OPC_CheckField, 0, 1, 0, // 1722: check Inst[0] == 0x0
915 OPC_Decode, 168, 12, 18, // 1726: decode to MTVSCR using decoder 18
916 // 1726: }
917 26, 8, // 1730: case 0x1a: {
918 OPC_CheckField, 0, 1, 0, // 1732: check Inst[0] == 0x0
919 OPC_Decode, 148, 18, 3, // 1736: decode to VEQV using decoder 3
920 // 1736: }
921 27, 8, // 1740: case 0x1b: {
922 OPC_CheckField, 0, 1, 0, // 1742: check Inst[0] == 0x0
923 OPC_Decode, 238, 19, 3, // 1746: decode to VSRD using decoder 3
924 // 1746: }
925 28, 8, // 1750: case 0x1c: {
926 OPC_CheckField, 0, 1, 0, // 1752: check Inst[0] == 0x0
927 OPC_Decode, 243, 19, 3, // 1756: decode to VSRV using decoder 3
928 // 1756: }
929 29, 8, // 1760: case 0x1d: {
930 OPC_CheckField, 0, 1, 0, // 1762: check Inst[0] == 0x0
931 OPC_Decode, 221, 19, 3, // 1766: decode to VSLV using decoder 3
932 // 1766: }
933 30, 8, // 1770: case 0x1e: {
934 OPC_CheckField, 0, 1, 0, // 1772: check Inst[0] == 0x0
935 OPC_Decode, 194, 17, 3, // 1776: decode to VCLZDM using decoder 3
936 // 1776: }
937 31, 0, // 1780: case 0x1f: {
938 OPC_CheckField, 0, 1, 0, // 1782: check Inst[0] == 0x0
939 OPC_Decode, 132, 18, 3, // 1786: decode to VCTZDM using decoder 3
940 // 1786: }
941 // 1786: } // switch Inst[10:6]
942 // 1786: }
943 3, 193, 3, // 1790: case 0x3: {
944 OPC_SwitchField, 6, 5, // 1793: switch Inst[10:6] {
945 0, 15, // 1796: case 0x0: {
946 OPC_SwitchField, 0, 1, // 1798: switch Inst[0] {
947 0, 4, // 1801: case 0x0: {
948 OPC_Decode, 202, 17, 3, // 1803: decode to VCMPEQUB using decoder 3
949 // 1803: }
950 1, 0, // 1807: case 0x1: {
951 OPC_Decode, 236, 17, 3, // 1809: decode to VCMPNEB using decoder 3
952 // 1809: }
953 // 1809: } // switch Inst[0]
954 // 1809: }
955 1, 15, // 1813: case 0x1: {
956 OPC_SwitchField, 0, 1, // 1815: switch Inst[0] {
957 0, 4, // 1818: case 0x0: {
958 OPC_Decode, 206, 17, 3, // 1820: decode to VCMPEQUH using decoder 3
959 // 1820: }
960 1, 0, // 1824: case 0x1: {
961 OPC_Decode, 238, 17, 3, // 1826: decode to VCMPNEH using decoder 3
962 // 1826: }
963 // 1826: } // switch Inst[0]
964 // 1826: }
965 2, 15, // 1830: case 0x2: {
966 OPC_SwitchField, 0, 1, // 1832: switch Inst[0] {
967 0, 4, // 1835: case 0x0: {
968 OPC_Decode, 210, 17, 3, // 1837: decode to VCMPEQUW using decoder 3
969 // 1837: }
970 1, 0, // 1841: case 0x1: {
971 OPC_Decode, 240, 17, 3, // 1843: decode to VCMPNEW using decoder 3
972 // 1843: }
973 // 1843: } // switch Inst[0]
974 // 1843: }
975 3, 15, // 1847: case 0x3: {
976 OPC_SwitchField, 0, 1, // 1849: switch Inst[0] {
977 0, 4, // 1852: case 0x0: {
978 OPC_Decode, 200, 17, 3, // 1854: decode to VCMPEQFP using decoder 3
979 // 1854: }
980 1, 0, // 1858: case 0x1: {
981 OPC_Decode, 204, 17, 3, // 1860: decode to VCMPEQUD using decoder 3
982 // 1860: }
983 // 1860: } // switch Inst[0]
984 // 1860: }
985 4, 8, // 1864: case 0x4: {
986 OPC_CheckField, 0, 1, 1, // 1866: check Inst[0] == 0x1
987 OPC_Decode, 242, 17, 3, // 1870: decode to VCMPNEZB using decoder 3
988 // 1870: }
989 5, 8, // 1874: case 0x5: {
990 OPC_CheckField, 0, 1, 1, // 1876: check Inst[0] == 0x1
991 OPC_Decode, 244, 17, 3, // 1880: decode to VCMPNEZH using decoder 3
992 // 1880: }
993 6, 8, // 1884: case 0x6: {
994 OPC_CheckField, 0, 1, 1, // 1886: check Inst[0] == 0x1
995 OPC_Decode, 246, 17, 3, // 1890: decode to VCMPNEZW using decoder 3
996 // 1890: }
997 7, 15, // 1894: case 0x7: {
998 OPC_SwitchField, 0, 1, // 1896: switch Inst[0] {
999 0, 4, // 1899: case 0x0: {
1000 OPC_Decode, 212, 17, 3, // 1901: decode to VCMPGEFP using decoder 3
1001 // 1901: }
1002 1, 0, // 1905: case 0x1: {
1003 OPC_Decode, 208, 17, 3, // 1907: decode to VCMPEQUQ using decoder 3
1004 // 1907: }
1005 // 1907: } // switch Inst[0]
1006 // 1907: }
1007 8, 8, // 1911: case 0x8: {
1008 OPC_CheckField, 0, 1, 0, // 1913: check Inst[0] == 0x0
1009 OPC_Decode, 226, 17, 3, // 1917: decode to VCMPGTUB using decoder 3
1010 // 1917: }
1011 9, 8, // 1921: case 0x9: {
1012 OPC_CheckField, 0, 1, 0, // 1923: check Inst[0] == 0x0
1013 OPC_Decode, 230, 17, 3, // 1927: decode to VCMPGTUH using decoder 3
1014 // 1927: }
1015 10, 15, // 1931: case 0xa: {
1016 OPC_SwitchField, 0, 1, // 1933: switch Inst[0] {
1017 0, 4, // 1936: case 0x0: {
1018 OPC_Decode, 234, 17, 3, // 1938: decode to VCMPGTUW using decoder 3
1019 // 1938: }
1020 1, 0, // 1942: case 0x1: {
1021 OPC_Decode, 232, 17, 3, // 1944: decode to VCMPGTUQ using decoder 3
1022 // 1944: }
1023 // 1944: } // switch Inst[0]
1024 // 1944: }
1025 11, 15, // 1948: case 0xb: {
1026 OPC_SwitchField, 0, 1, // 1950: switch Inst[0] {
1027 0, 4, // 1953: case 0x0: {
1028 OPC_Decode, 214, 17, 3, // 1955: decode to VCMPGTFP using decoder 3
1029 // 1955: }
1030 1, 0, // 1959: case 0x1: {
1031 OPC_Decode, 228, 17, 3, // 1961: decode to VCMPGTUD using decoder 3
1032 // 1961: }
1033 // 1961: } // switch Inst[0]
1034 // 1961: }
1035 12, 8, // 1965: case 0xc: {
1036 OPC_CheckField, 0, 1, 0, // 1967: check Inst[0] == 0x0
1037 OPC_Decode, 216, 17, 3, // 1971: decode to VCMPGTSB using decoder 3
1038 // 1971: }
1039 13, 8, // 1975: case 0xd: {
1040 OPC_CheckField, 0, 1, 0, // 1977: check Inst[0] == 0x0
1041 OPC_Decode, 220, 17, 3, // 1981: decode to VCMPGTSH using decoder 3
1042 // 1981: }
1043 14, 15, // 1985: case 0xe: {
1044 OPC_SwitchField, 0, 1, // 1987: switch Inst[0] {
1045 0, 4, // 1990: case 0x0: {
1046 OPC_Decode, 224, 17, 3, // 1992: decode to VCMPGTSW using decoder 3
1047 // 1992: }
1048 1, 0, // 1996: case 0x1: {
1049 OPC_Decode, 222, 17, 3, // 1998: decode to VCMPGTSQ using decoder 3
1050 // 1998: }
1051 // 1998: } // switch Inst[0]
1052 // 1998: }
1053 15, 15, // 2002: case 0xf: {
1054 OPC_SwitchField, 0, 1, // 2004: switch Inst[0] {
1055 0, 4, // 2007: case 0x0: {
1056 OPC_Decode, 198, 17, 3, // 2009: decode to VCMPBFP using decoder 3
1057 // 2009: }
1058 1, 0, // 2013: case 0x1: {
1059 OPC_Decode, 218, 17, 3, // 2015: decode to VCMPGTSD using decoder 3
1060 // 2015: }
1061 // 2015: } // switch Inst[0]
1062 // 2015: }
1063 16, 15, // 2019: case 0x10: {
1064 OPC_SwitchField, 0, 1, // 2021: switch Inst[0] {
1065 0, 4, // 2024: case 0x0: {
1066 OPC_Decode, 203, 17, 3, // 2026: decode to VCMPEQUB_rec using decoder 3
1067 // 2026: }
1068 1, 0, // 2030: case 0x1: {
1069 OPC_Decode, 237, 17, 3, // 2032: decode to VCMPNEB_rec using decoder 3
1070 // 2032: }
1071 // 2032: } // switch Inst[0]
1072 // 2032: }
1073 17, 15, // 2036: case 0x11: {
1074 OPC_SwitchField, 0, 1, // 2038: switch Inst[0] {
1075 0, 4, // 2041: case 0x0: {
1076 OPC_Decode, 207, 17, 3, // 2043: decode to VCMPEQUH_rec using decoder 3
1077 // 2043: }
1078 1, 0, // 2047: case 0x1: {
1079 OPC_Decode, 239, 17, 3, // 2049: decode to VCMPNEH_rec using decoder 3
1080 // 2049: }
1081 // 2049: } // switch Inst[0]
1082 // 2049: }
1083 18, 15, // 2053: case 0x12: {
1084 OPC_SwitchField, 0, 1, // 2055: switch Inst[0] {
1085 0, 4, // 2058: case 0x0: {
1086 OPC_Decode, 211, 17, 3, // 2060: decode to VCMPEQUW_rec using decoder 3
1087 // 2060: }
1088 1, 0, // 2064: case 0x1: {
1089 OPC_Decode, 241, 17, 3, // 2066: decode to VCMPNEW_rec using decoder 3
1090 // 2066: }
1091 // 2066: } // switch Inst[0]
1092 // 2066: }
1093 19, 15, // 2070: case 0x13: {
1094 OPC_SwitchField, 0, 1, // 2072: switch Inst[0] {
1095 0, 4, // 2075: case 0x0: {
1096 OPC_Decode, 201, 17, 3, // 2077: decode to VCMPEQFP_rec using decoder 3
1097 // 2077: }
1098 1, 0, // 2081: case 0x1: {
1099 OPC_Decode, 205, 17, 3, // 2083: decode to VCMPEQUD_rec using decoder 3
1100 // 2083: }
1101 // 2083: } // switch Inst[0]
1102 // 2083: }
1103 20, 8, // 2087: case 0x14: {
1104 OPC_CheckField, 0, 1, 1, // 2089: check Inst[0] == 0x1
1105 OPC_Decode, 243, 17, 3, // 2093: decode to VCMPNEZB_rec using decoder 3
1106 // 2093: }
1107 21, 8, // 2097: case 0x15: {
1108 OPC_CheckField, 0, 1, 1, // 2099: check Inst[0] == 0x1
1109 OPC_Decode, 245, 17, 3, // 2103: decode to VCMPNEZH_rec using decoder 3
1110 // 2103: }
1111 22, 8, // 2107: case 0x16: {
1112 OPC_CheckField, 0, 1, 1, // 2109: check Inst[0] == 0x1
1113 OPC_Decode, 247, 17, 3, // 2113: decode to VCMPNEZW_rec using decoder 3
1114 // 2113: }
1115 23, 15, // 2117: case 0x17: {
1116 OPC_SwitchField, 0, 1, // 2119: switch Inst[0] {
1117 0, 4, // 2122: case 0x0: {
1118 OPC_Decode, 213, 17, 3, // 2124: decode to VCMPGEFP_rec using decoder 3
1119 // 2124: }
1120 1, 0, // 2128: case 0x1: {
1121 OPC_Decode, 209, 17, 3, // 2130: decode to VCMPEQUQ_rec using decoder 3
1122 // 2130: }
1123 // 2130: } // switch Inst[0]
1124 // 2130: }
1125 24, 8, // 2134: case 0x18: {
1126 OPC_CheckField, 0, 1, 0, // 2136: check Inst[0] == 0x0
1127 OPC_Decode, 227, 17, 3, // 2140: decode to VCMPGTUB_rec using decoder 3
1128 // 2140: }
1129 25, 8, // 2144: case 0x19: {
1130 OPC_CheckField, 0, 1, 0, // 2146: check Inst[0] == 0x0
1131 OPC_Decode, 231, 17, 3, // 2150: decode to VCMPGTUH_rec using decoder 3
1132 // 2150: }
1133 26, 15, // 2154: case 0x1a: {
1134 OPC_SwitchField, 0, 1, // 2156: switch Inst[0] {
1135 0, 4, // 2159: case 0x0: {
1136 OPC_Decode, 235, 17, 3, // 2161: decode to VCMPGTUW_rec using decoder 3
1137 // 2161: }
1138 1, 0, // 2165: case 0x1: {
1139 OPC_Decode, 233, 17, 3, // 2167: decode to VCMPGTUQ_rec using decoder 3
1140 // 2167: }
1141 // 2167: } // switch Inst[0]
1142 // 2167: }
1143 27, 15, // 2171: case 0x1b: {
1144 OPC_SwitchField, 0, 1, // 2173: switch Inst[0] {
1145 0, 4, // 2176: case 0x0: {
1146 OPC_Decode, 215, 17, 3, // 2178: decode to VCMPGTFP_rec using decoder 3
1147 // 2178: }
1148 1, 0, // 2182: case 0x1: {
1149 OPC_Decode, 229, 17, 3, // 2184: decode to VCMPGTUD_rec using decoder 3
1150 // 2184: }
1151 // 2184: } // switch Inst[0]
1152 // 2184: }
1153 28, 8, // 2188: case 0x1c: {
1154 OPC_CheckField, 0, 1, 0, // 2190: check Inst[0] == 0x0
1155 OPC_Decode, 217, 17, 3, // 2194: decode to VCMPGTSB_rec using decoder 3
1156 // 2194: }
1157 29, 8, // 2198: case 0x1d: {
1158 OPC_CheckField, 0, 1, 0, // 2200: check Inst[0] == 0x0
1159 OPC_Decode, 221, 17, 3, // 2204: decode to VCMPGTSH_rec using decoder 3
1160 // 2204: }
1161 30, 15, // 2208: case 0x1e: {
1162 OPC_SwitchField, 0, 1, // 2210: switch Inst[0] {
1163 0, 4, // 2213: case 0x0: {
1164 OPC_Decode, 225, 17, 3, // 2215: decode to VCMPGTSW_rec using decoder 3
1165 // 2215: }
1166 1, 0, // 2219: case 0x1: {
1167 OPC_Decode, 223, 17, 3, // 2221: decode to VCMPGTSQ_rec using decoder 3
1168 // 2221: }
1169 // 2221: } // switch Inst[0]
1170 // 2221: }
1171 31, 0, // 2225: case 0x1f: {
1172 OPC_SwitchField, 0, 1, // 2227: switch Inst[0] {
1173 0, 4, // 2230: case 0x0: {
1174 OPC_Decode, 199, 17, 3, // 2232: decode to VCMPBFP_rec using decoder 3
1175 // 2232: }
1176 1, 0, // 2236: case 0x1: {
1177 OPC_Decode, 219, 17, 3, // 2238: decode to VCMPGTSD_rec using decoder 3
1178 // 2238: }
1179 // 2238: } // switch Inst[0]
1180 // 2238: }
1181 // 2238: } // switch Inst[10:6]
1182 // 2238: }
1183 4, 215, 2, // 2242: case 0x4: {
1184 OPC_SwitchField, 6, 5, // 2245: switch Inst[10:6] {
1185 0, 8, // 2248: case 0x0: {
1186 OPC_CheckField, 0, 1, 0, // 2250: check Inst[0] == 0x0
1187 OPC_Decode, 149, 19, 3, // 2254: decode to VMULOUB using decoder 3
1188 // 2254: }
1189 1, 8, // 2258: case 0x1: {
1190 OPC_CheckField, 0, 1, 0, // 2260: check Inst[0] == 0x0
1191 OPC_Decode, 151, 19, 3, // 2264: decode to VMULOUH using decoder 3
1192 // 2264: }
1193 2, 15, // 2268: case 0x2: {
1194 OPC_SwitchField, 0, 1, // 2270: switch Inst[0] {
1195 0, 4, // 2273: case 0x0: {
1196 OPC_Decode, 152, 19, 3, // 2275: decode to VMULOUW using decoder 3
1197 // 2275: }
1198 1, 0, // 2279: case 0x1: {
1199 OPC_Decode, 153, 19, 3, // 2281: decode to VMULUWM using decoder 3
1200 // 2281: }
1201 // 2281: } // switch Inst[0]
1202 // 2281: }
1203 3, 8, // 2285: case 0x3: {
1204 OPC_CheckField, 0, 1, 0, // 2287: check Inst[0] == 0x0
1205 OPC_Decode, 150, 19, 3, // 2291: decode to VMULOUD using decoder 3
1206 // 2291: }
1207 4, 8, // 2295: case 0x4: {
1208 OPC_CheckField, 0, 1, 0, // 2297: check Inst[0] == 0x0
1209 OPC_Decode, 145, 19, 3, // 2301: decode to VMULOSB using decoder 3
1210 // 2301: }
1211 5, 8, // 2305: case 0x5: {
1212 OPC_CheckField, 0, 1, 0, // 2307: check Inst[0] == 0x0
1213 OPC_Decode, 147, 19, 3, // 2311: decode to VMULOSH using decoder 3
1214 // 2311: }
1215 6, 8, // 2315: case 0x6: {
1216 OPC_CheckField, 0, 1, 0, // 2317: check Inst[0] == 0x0
1217 OPC_Decode, 148, 19, 3, // 2321: decode to VMULOSW using decoder 3
1218 // 2321: }
1219 7, 15, // 2325: case 0x7: {
1220 OPC_SwitchField, 0, 1, // 2327: switch Inst[0] {
1221 0, 4, // 2330: case 0x0: {
1222 OPC_Decode, 146, 19, 3, // 2332: decode to VMULOSD using decoder 3
1223 // 2332: }
1224 1, 0, // 2336: case 0x1: {
1225 OPC_Decode, 144, 19, 3, // 2338: decode to VMULLD using decoder 3
1226 // 2338: }
1227 // 2338: } // switch Inst[0]
1228 // 2338: }
1229 8, 8, // 2342: case 0x8: {
1230 OPC_CheckField, 0, 1, 0, // 2344: check Inst[0] == 0x0
1231 OPC_Decode, 136, 19, 3, // 2348: decode to VMULEUB using decoder 3
1232 // 2348: }
1233 9, 8, // 2352: case 0x9: {
1234 OPC_CheckField, 0, 1, 0, // 2354: check Inst[0] == 0x0
1235 OPC_Decode, 138, 19, 3, // 2358: decode to VMULEUH using decoder 3
1236 // 2358: }
1237 10, 15, // 2362: case 0xa: {
1238 OPC_SwitchField, 0, 1, // 2364: switch Inst[0] {
1239 0, 4, // 2367: case 0x0: {
1240 OPC_Decode, 139, 19, 3, // 2369: decode to VMULEUW using decoder 3
1241 // 2369: }
1242 1, 0, // 2373: case 0x1: {
1243 OPC_Decode, 143, 19, 3, // 2375: decode to VMULHUW using decoder 3
1244 // 2375: }
1245 // 2375: } // switch Inst[0]
1246 // 2375: }
1247 11, 15, // 2379: case 0xb: {
1248 OPC_SwitchField, 0, 1, // 2381: switch Inst[0] {
1249 0, 4, // 2384: case 0x0: {
1250 OPC_Decode, 137, 19, 3, // 2386: decode to VMULEUD using decoder 3
1251 // 2386: }
1252 1, 0, // 2390: case 0x1: {
1253 OPC_Decode, 142, 19, 3, // 2392: decode to VMULHUD using decoder 3
1254 // 2392: }
1255 // 2392: } // switch Inst[0]
1256 // 2392: }
1257 12, 8, // 2396: case 0xc: {
1258 OPC_CheckField, 0, 1, 0, // 2398: check Inst[0] == 0x0
1259 OPC_Decode, 132, 19, 3, // 2402: decode to VMULESB using decoder 3
1260 // 2402: }
1261 13, 8, // 2406: case 0xd: {
1262 OPC_CheckField, 0, 1, 0, // 2408: check Inst[0] == 0x0
1263 OPC_Decode, 134, 19, 3, // 2412: decode to VMULESH using decoder 3
1264 // 2412: }
1265 14, 15, // 2416: case 0xe: {
1266 OPC_SwitchField, 0, 1, // 2418: switch Inst[0] {
1267 0, 4, // 2421: case 0x0: {
1268 OPC_Decode, 135, 19, 3, // 2423: decode to VMULESW using decoder 3
1269 // 2423: }
1270 1, 0, // 2427: case 0x1: {
1271 OPC_Decode, 141, 19, 3, // 2429: decode to VMULHSW using decoder 3
1272 // 2429: }
1273 // 2429: } // switch Inst[0]
1274 // 2429: }
1275 15, 15, // 2433: case 0xf: {
1276 OPC_SwitchField, 0, 1, // 2435: switch Inst[0] {
1277 0, 4, // 2438: case 0x0: {
1278 OPC_Decode, 133, 19, 3, // 2440: decode to VMULESD using decoder 3
1279 // 2440: }
1280 1, 0, // 2444: case 0x1: {
1281 OPC_Decode, 140, 19, 3, // 2446: decode to VMULHSD using decoder 3
1282 // 2446: }
1283 // 2446: } // switch Inst[0]
1284 // 2446: }
1285 16, 8, // 2450: case 0x10: {
1286 OPC_CheckField, 0, 1, 0, // 2452: check Inst[0] == 0x0
1287 OPC_Decode, 181, 19, 3, // 2456: decode to VPMSUMB using decoder 3
1288 // 2456: }
1289 17, 8, // 2460: case 0x11: {
1290 OPC_CheckField, 0, 1, 0, // 2462: check Inst[0] == 0x0
1291 OPC_Decode, 183, 19, 3, // 2466: decode to VPMSUMH using decoder 3
1292 // 2466: }
1293 18, 8, // 2470: case 0x12: {
1294 OPC_CheckField, 0, 1, 0, // 2472: check Inst[0] == 0x0
1295 OPC_Decode, 184, 19, 3, // 2476: decode to VPMSUMW using decoder 3
1296 // 2476: }
1297 19, 8, // 2480: case 0x13: {
1298 OPC_CheckField, 0, 1, 0, // 2482: check Inst[0] == 0x0
1299 OPC_Decode, 182, 19, 3, // 2486: decode to VPMSUMD using decoder 3
1300 // 2486: }
1301 20, 15, // 2490: case 0x14: {
1302 OPC_SwitchField, 0, 1, // 2492: switch Inst[0] {
1303 0, 4, // 2495: case 0x0: {
1304 OPC_Decode, 188, 17, 3, // 2497: decode to VCIPHER using decoder 3
1305 // 2497: }
1306 1, 0, // 2501: case 0x1: {
1307 OPC_Decode, 189, 17, 3, // 2503: decode to VCIPHERLAST using decoder 3
1308 // 2503: }
1309 // 2503: } // switch Inst[0]
1310 // 2503: }
1311 21, 15, // 2507: case 0x15: {
1312 OPC_SwitchField, 0, 1, // 2509: switch Inst[0] {
1313 0, 4, // 2512: case 0x0: {
1314 OPC_Decode, 155, 19, 3, // 2514: decode to VNCIPHER using decoder 3
1315 // 2514: }
1316 1, 0, // 2518: case 0x1: {
1317 OPC_Decode, 156, 19, 3, // 2520: decode to VNCIPHERLAST using decoder 3
1318 // 2520: }
1319 // 2520: } // switch Inst[0]
1320 // 2520: }
1321 23, 12, // 2524: case 0x17: {
1322 OPC_CheckField, 11, 5, 0, // 2526: check Inst[15:11] == 0x0
1323 OPC_CheckField, 0, 1, 0, // 2530: check Inst[0] == 0x0
1324 OPC_Decode, 209, 19, 4, // 2534: decode to VSBOX using decoder 4
1325 // 2534: }
1326 24, 8, // 2538: case 0x18: {
1327 OPC_CheckField, 0, 1, 0, // 2540: check Inst[0] == 0x0
1328 OPC_Decode, 144, 20, 3, // 2544: decode to VSUM4UBS using decoder 3
1329 // 2544: }
1330 25, 8, // 2548: case 0x19: {
1331 OPC_CheckField, 0, 1, 0, // 2550: check Inst[0] == 0x0
1332 OPC_Decode, 143, 20, 3, // 2554: decode to VSUM4SHS using decoder 3
1333 // 2554: }
1334 26, 8, // 2558: case 0x1a: {
1335 OPC_CheckField, 0, 1, 0, // 2560: check Inst[0] == 0x0
1336 OPC_Decode, 141, 20, 3, // 2564: decode to VSUM2SWS using decoder 3
1337 // 2564: }
1338 28, 8, // 2568: case 0x1c: {
1339 OPC_CheckField, 0, 1, 0, // 2570: check Inst[0] == 0x0
1340 OPC_Decode, 142, 20, 3, // 2574: decode to VSUM4SBS using decoder 3
1341 // 2574: }
1342 30, 0, // 2578: case 0x1e: {
1343 OPC_CheckField, 0, 1, 0, // 2580: check Inst[0] == 0x0
1344 OPC_Decode, 145, 20, 3, // 2584: decode to VSUMSWS using decoder 3
1345 // 2584: }
1346 // 2584: } // switch Inst[10:6]
1347 // 2584: }
1348 5, 217, 2, // 2588: case 0x5: {
1349 OPC_SwitchField, 6, 5, // 2591: switch Inst[10:6] {
1350 0, 15, // 2594: case 0x0: {
1351 OPC_SwitchField, 0, 1, // 2596: switch Inst[0] {
1352 0, 4, // 2599: case 0x0: {
1353 OPC_Decode, 161, 17, 3, // 2601: decode to VADDFP using decoder 3
1354 // 2601: }
1355 1, 0, // 2605: case 0x1: {
1356 OPC_Decode, 146, 18, 3, // 2607: decode to VDIVUQ using decoder 3
1357 // 2607: }
1358 // 2607: } // switch Inst[0]
1359 // 2607: }
1360 1, 8, // 2611: case 0x1: {
1361 OPC_CheckField, 0, 1, 0, // 2613: check Inst[0] == 0x0
1362 OPC_Decode, 129, 20, 3, // 2617: decode to VSUBFP using decoder 3
1363 // 2617: }
1364 2, 8, // 2621: case 0x2: {
1365 OPC_CheckField, 0, 1, 1, // 2623: check Inst[0] == 0x1
1366 OPC_Decode, 147, 18, 3, // 2627: decode to VDIVUW using decoder 3
1367 // 2627: }
1368 3, 8, // 2631: case 0x3: {
1369 OPC_CheckField, 0, 1, 1, // 2633: check Inst[0] == 0x1
1370 OPC_Decode, 145, 18, 3, // 2637: decode to VDIVUD using decoder 3
1371 // 2637: }
1372 4, 19, // 2641: case 0x4: {
1373 OPC_SwitchField, 0, 1, // 2643: switch Inst[0] {
1374 0, 8, // 2646: case 0x0: {
1375 OPC_CheckField, 16, 5, 0, // 2648: check Inst[20:16] == 0x0
1376 OPC_Decode, 192, 19, 7, // 2652: decode to VREFP using decoder 7
1377 // 2652: }
1378 1, 0, // 2656: case 0x1: {
1379 OPC_Decode, 143, 18, 3, // 2658: decode to VDIVSQ using decoder 3
1380 // 2658: }
1381 // 2658: } // switch Inst[0]
1382 // 2658: }
1383 5, 12, // 2662: case 0x5: {
1384 OPC_CheckField, 16, 5, 0, // 2664: check Inst[20:16] == 0x0
1385 OPC_CheckField, 0, 1, 0, // 2668: check Inst[0] == 0x0
1386 OPC_Decode, 208, 19, 7, // 2672: decode to VRSQRTEFP using decoder 7
1387 // 2672: }
1388 6, 19, // 2676: case 0x6: {
1389 OPC_SwitchField, 0, 1, // 2678: switch Inst[0] {
1390 0, 8, // 2681: case 0x0: {
1391 OPC_CheckField, 16, 5, 0, // 2683: check Inst[20:16] == 0x0
1392 OPC_Decode, 154, 18, 7, // 2687: decode to VEXPTEFP using decoder 7
1393 // 2687: }
1394 1, 0, // 2691: case 0x1: {
1395 OPC_Decode, 144, 18, 3, // 2693: decode to VDIVSW using decoder 3
1396 // 2693: }
1397 // 2693: } // switch Inst[0]
1398 // 2693: }
1399 7, 19, // 2697: case 0x7: {
1400 OPC_SwitchField, 0, 1, // 2699: switch Inst[0] {
1401 0, 8, // 2702: case 0x0: {
1402 OPC_CheckField, 16, 5, 0, // 2704: check Inst[20:16] == 0x0
1403 OPC_Decode, 211, 18, 7, // 2708: decode to VLOGEFP using decoder 7
1404 // 2708: }
1405 1, 0, // 2712: case 0x1: {
1406 OPC_Decode, 142, 18, 3, // 2714: decode to VDIVSD using decoder 3
1407 // 2714: }
1408 // 2714: } // switch Inst[0]
1409 // 2714: }
1410 8, 19, // 2718: case 0x8: {
1411 OPC_SwitchField, 0, 1, // 2720: switch Inst[0] {
1412 0, 8, // 2723: case 0x0: {
1413 OPC_CheckField, 16, 5, 0, // 2725: check Inst[20:16] == 0x0
1414 OPC_Decode, 194, 19, 7, // 2729: decode to VRFIN using decoder 7
1415 // 2729: }
1416 1, 0, // 2733: case 0x1: {
1417 OPC_Decode, 140, 18, 3, // 2735: decode to VDIVEUQ using decoder 3
1418 // 2735: }
1419 // 2735: } // switch Inst[0]
1420 // 2735: }
1421 9, 12, // 2739: case 0x9: {
1422 OPC_CheckField, 16, 5, 0, // 2741: check Inst[20:16] == 0x0
1423 OPC_CheckField, 0, 1, 0, // 2745: check Inst[0] == 0x0
1424 OPC_Decode, 196, 19, 7, // 2749: decode to VRFIZ using decoder 7
1425 // 2749: }
1426 10, 19, // 2753: case 0xa: {
1427 OPC_SwitchField, 0, 1, // 2755: switch Inst[0] {
1428 0, 8, // 2758: case 0x0: {
1429 OPC_CheckField, 16, 5, 0, // 2760: check Inst[20:16] == 0x0
1430 OPC_Decode, 195, 19, 7, // 2764: decode to VRFIP using decoder 7
1431 // 2764: }
1432 1, 0, // 2768: case 0x1: {
1433 OPC_Decode, 141, 18, 3, // 2770: decode to VDIVEUW using decoder 3
1434 // 2770: }
1435 // 2770: } // switch Inst[0]
1436 // 2770: }
1437 11, 19, // 2774: case 0xb: {
1438 OPC_SwitchField, 0, 1, // 2776: switch Inst[0] {
1439 0, 8, // 2779: case 0x0: {
1440 OPC_CheckField, 16, 5, 0, // 2781: check Inst[20:16] == 0x0
1441 OPC_Decode, 193, 19, 7, // 2785: decode to VRFIM using decoder 7
1442 // 2785: }
1443 1, 0, // 2789: case 0x1: {
1444 OPC_Decode, 139, 18, 3, // 2791: decode to VDIVEUD using decoder 3
1445 // 2791: }
1446 // 2791: } // switch Inst[0]
1447 // 2791: }
1448 12, 15, // 2795: case 0xc: {
1449 OPC_SwitchField, 0, 1, // 2797: switch Inst[0] {
1450 0, 4, // 2800: case 0x0: {
1451 OPC_Decode, 186, 17, 19, // 2802: decode to VCFUX using decoder 19
1452 // 2802: }
1453 1, 0, // 2806: case 0x1: {
1454 OPC_Decode, 137, 18, 3, // 2808: decode to VDIVESQ using decoder 3
1455 // 2808: }
1456 // 2808: } // switch Inst[0]
1457 // 2808: }
1458 13, 8, // 2812: case 0xd: {
1459 OPC_CheckField, 0, 1, 0, // 2814: check Inst[0] == 0x0
1460 OPC_Decode, 183, 17, 19, // 2818: decode to VCFSX using decoder 19
1461 // 2818: }
1462 14, 15, // 2822: case 0xe: {
1463 OPC_SwitchField, 0, 1, // 2824: switch Inst[0] {
1464 0, 4, // 2827: case 0x0: {
1465 OPC_Decode, 128, 18, 19, // 2829: decode to VCTUXS using decoder 19
1466 // 2829: }
1467 1, 0, // 2833: case 0x1: {
1468 OPC_Decode, 138, 18, 3, // 2835: decode to VDIVESW using decoder 3
1469 // 2835: }
1470 // 2835: } // switch Inst[0]
1471 // 2835: }
1472 15, 15, // 2839: case 0xf: {
1473 OPC_SwitchField, 0, 1, // 2841: switch Inst[0] {
1474 0, 4, // 2844: case 0x0: {
1475 OPC_Decode, 254, 17, 19, // 2846: decode to VCTSXS using decoder 19
1476 // 2846: }
1477 1, 0, // 2850: case 0x1: {
1478 OPC_Decode, 136, 18, 3, // 2852: decode to VDIVESD using decoder 3
1479 // 2852: }
1480 // 2852: } // switch Inst[0]
1481 // 2852: }
1482 16, 8, // 2856: case 0x10: {
1483 OPC_CheckField, 0, 1, 0, // 2858: check Inst[0] == 0x0
1484 OPC_Decode, 213, 18, 3, // 2862: decode to VMAXFP using decoder 3
1485 // 2862: }
1486 17, 8, // 2866: case 0x11: {
1487 OPC_CheckField, 0, 1, 0, // 2868: check Inst[0] == 0x0
1488 OPC_Decode, 224, 18, 3, // 2872: decode to VMINFP using decoder 3
1489 // 2872: }
1490 24, 8, // 2876: case 0x18: {
1491 OPC_CheckField, 0, 1, 1, // 2878: check Inst[0] == 0x1
1492 OPC_Decode, 238, 18, 3, // 2882: decode to VMODUQ using decoder 3
1493 // 2882: }
1494 26, 8, // 2886: case 0x1a: {
1495 OPC_CheckField, 0, 1, 1, // 2888: check Inst[0] == 0x1
1496 OPC_Decode, 239, 18, 3, // 2892: decode to VMODUW using decoder 3
1497 // 2892: }
1498 27, 8, // 2896: case 0x1b: {
1499 OPC_CheckField, 0, 1, 1, // 2898: check Inst[0] == 0x1
1500 OPC_Decode, 237, 18, 3, // 2902: decode to VMODUD using decoder 3
1501 // 2902: }
1502 28, 8, // 2906: case 0x1c: {
1503 OPC_CheckField, 0, 1, 1, // 2908: check Inst[0] == 0x1
1504 OPC_Decode, 235, 18, 3, // 2912: decode to VMODSQ using decoder 3
1505 // 2912: }
1506 30, 8, // 2916: case 0x1e: {
1507 OPC_CheckField, 0, 1, 1, // 2918: check Inst[0] == 0x1
1508 OPC_Decode, 236, 18, 3, // 2922: decode to VMODSW using decoder 3
1509 // 2922: }
1510 31, 0, // 2926: case 0x1f: {
1511 OPC_CheckField, 0, 1, 1, // 2928: check Inst[0] == 0x1
1512 OPC_Decode, 234, 18, 3, // 2932: decode to VMODSD using decoder 3
1513 // 2932: }
1514 // 2932: } // switch Inst[10:6]
1515 // 2932: }
1516 6, 184, 3, // 2936: case 0x6: {
1517 OPC_SwitchField, 6, 5, // 2939: switch Inst[10:6] {
1518 0, 38, // 2942: case 0x0: {
1519 OPC_SwitchField, 0, 1, // 2944: switch Inst[0] {
1520 0, 4, // 2947: case 0x0: {
1521 OPC_Decode, 241, 18, 3, // 2949: decode to VMRGHB using decoder 3
1522 // 2949: }
1523 1, 0, // 2953: case 0x1: {
1524 OPC_SwitchField, 16, 5, // 2955: switch Inst[20:16] {
1525 0, 4, // 2958: case 0x0: {
1526 OPC_Decode, 245, 19, 7, // 2960: decode to VSTRIBL using decoder 7
1527 // 2960: }
1528 1, 4, // 2964: case 0x1: {
1529 OPC_Decode, 247, 19, 7, // 2966: decode to VSTRIBR using decoder 7
1530 // 2966: }
1531 2, 4, // 2970: case 0x2: {
1532 OPC_Decode, 249, 19, 7, // 2972: decode to VSTRIHL using decoder 7
1533 // 2972: }
1534 3, 0, // 2976: case 0x3: {
1535 OPC_Decode, 251, 19, 7, // 2978: decode to VSTRIHR using decoder 7
1536 // 2978: }
1537 // 2978: } // switch Inst[20:16]
1538 // 2978: }
1539 // 2978: } // switch Inst[0]
1540 // 2978: }
1541 1, 8, // 2982: case 0x1: {
1542 OPC_CheckField, 0, 1, 0, // 2984: check Inst[0] == 0x0
1543 OPC_Decode, 242, 18, 3, // 2988: decode to VMRGHH using decoder 3
1544 // 2988: }
1545 2, 8, // 2992: case 0x2: {
1546 OPC_CheckField, 0, 1, 0, // 2994: check Inst[0] == 0x0
1547 OPC_Decode, 243, 18, 3, // 2998: decode to VMRGHW using decoder 3
1548 // 2998: }
1549 4, 8, // 3002: case 0x4: {
1550 OPC_CheckField, 0, 1, 0, // 3004: check Inst[0] == 0x0
1551 OPC_Decode, 244, 18, 3, // 3008: decode to VMRGLB using decoder 3
1552 // 3008: }
1553 5, 8, // 3012: case 0x5: {
1554 OPC_CheckField, 0, 1, 0, // 3014: check Inst[0] == 0x0
1555 OPC_Decode, 245, 18, 3, // 3018: decode to VMRGLH using decoder 3
1556 // 3018: }
1557 6, 15, // 3022: case 0x6: {
1558 OPC_SwitchField, 0, 1, // 3024: switch Inst[0] {
1559 0, 4, // 3027: case 0x0: {
1560 OPC_Decode, 246, 18, 3, // 3029: decode to VMRGLW using decoder 3
1561 // 3029: }
1562 1, 0, // 3033: case 0x1: {
1563 OPC_Decode, 190, 17, 20, // 3035: decode to VCLRLB using decoder 20
1564 // 3035: }
1565 // 3035: } // switch Inst[0]
1566 // 3035: }
1567 7, 8, // 3039: case 0x7: {
1568 OPC_CheckField, 0, 1, 1, // 3041: check Inst[0] == 0x1
1569 OPC_Decode, 191, 17, 20, // 3045: decode to VCLRRB using decoder 20
1570 // 3045: }
1571 8, 15, // 3049: case 0x8: {
1572 OPC_SwitchField, 0, 1, // 3051: switch Inst[0] {
1573 0, 4, // 3054: case 0x0: {
1574 OPC_Decode, 223, 19, 19, // 3056: decode to VSPLTB using decoder 19
1575 // 3056: }
1576 1, 0, // 3060: case 0x1: {
1577 OPC_Decode, 168, 18, 21, // 3062: decode to VEXTRACTUB using decoder 21
1578 // 3062: }
1579 // 3062: } // switch Inst[0]
1580 // 3062: }
1581 9, 15, // 3066: case 0x9: {
1582 OPC_SwitchField, 0, 1, // 3068: switch Inst[0] {
1583 0, 4, // 3071: case 0x0: {
1584 OPC_Decode, 225, 19, 19, // 3073: decode to VSPLTH using decoder 19
1585 // 3073: }
1586 1, 0, // 3077: case 0x1: {
1587 OPC_Decode, 169, 18, 21, // 3079: decode to VEXTRACTUH using decoder 21
1588 // 3079: }
1589 // 3079: } // switch Inst[0]
1590 // 3079: }
1591 10, 15, // 3083: case 0xa: {
1592 OPC_SwitchField, 0, 1, // 3085: switch Inst[0] {
1593 0, 4, // 3088: case 0x0: {
1594 OPC_Decode, 230, 19, 19, // 3090: decode to VSPLTW using decoder 19
1595 // 3090: }
1596 1, 0, // 3094: case 0x1: {
1597 OPC_Decode, 170, 18, 21, // 3096: decode to VEXTRACTUW using decoder 21
1598 // 3096: }
1599 // 3096: } // switch Inst[0]
1600 // 3096: }
1601 11, 8, // 3100: case 0xb: {
1602 OPC_CheckField, 0, 1, 1, // 3102: check Inst[0] == 0x1
1603 OPC_Decode, 164, 18, 21, // 3106: decode to VEXTRACTD using decoder 21
1604 // 3106: }
1605 12, 19, // 3110: case 0xc: {
1606 OPC_SwitchField, 0, 1, // 3112: switch Inst[0] {
1607 0, 8, // 3115: case 0x0: {
1608 OPC_CheckField, 11, 5, 0, // 3117: check Inst[15:11] == 0x0
1609 OPC_Decode, 227, 19, 22, // 3121: decode to VSPLTISB using decoder 22
1610 // 3121: }
1611 1, 0, // 3125: case 0x1: {
1612 OPC_Decode, 198, 18, 23, // 3127: decode to VINSERTB using decoder 23
1613 // 3127: }
1614 // 3127: } // switch Inst[0]
1615 // 3127: }
1616 13, 19, // 3131: case 0xd: {
1617 OPC_SwitchField, 0, 1, // 3133: switch Inst[0] {
1618 0, 8, // 3136: case 0x0: {
1619 OPC_CheckField, 11, 5, 0, // 3138: check Inst[15:11] == 0x0
1620 OPC_Decode, 228, 19, 22, // 3142: decode to VSPLTISH using decoder 22
1621 // 3142: }
1622 1, 0, // 3146: case 0x1: {
1623 OPC_Decode, 200, 18, 23, // 3148: decode to VINSERTH using decoder 23
1624 // 3148: }
1625 // 3148: } // switch Inst[0]
1626 // 3148: }
1627 14, 19, // 3152: case 0xe: {
1628 OPC_SwitchField, 0, 1, // 3154: switch Inst[0] {
1629 0, 8, // 3157: case 0x0: {
1630 OPC_CheckField, 11, 5, 0, // 3159: check Inst[15:11] == 0x0
1631 OPC_Decode, 229, 19, 22, // 3163: decode to VSPLTISW using decoder 22
1632 // 3163: }
1633 1, 0, // 3167: case 0x1: {
1634 OPC_Decode, 201, 18, 21, // 3169: decode to VINSERTW using decoder 21
1635 // 3169: }
1636 // 3169: } // switch Inst[0]
1637 // 3169: }
1638 15, 8, // 3173: case 0xf: {
1639 OPC_CheckField, 0, 1, 1, // 3175: check Inst[0] == 0x1
1640 OPC_Decode, 199, 18, 21, // 3179: decode to VINSERTD using decoder 21
1641 // 3179: }
1642 16, 38, // 3183: case 0x10: {
1643 OPC_SwitchField, 0, 1, // 3185: switch Inst[0] {
1644 0, 4, // 3188: case 0x0: {
1645 OPC_Decode, 219, 19, 3, // 3190: decode to VSLO using decoder 3
1646 // 3190: }
1647 1, 0, // 3194: case 0x1: {
1648 OPC_SwitchField, 16, 5, // 3196: switch Inst[20:16] {
1649 0, 4, // 3199: case 0x0: {
1650 OPC_Decode, 246, 19, 7, // 3201: decode to VSTRIBL_rec using decoder 7
1651 // 3201: }
1652 1, 4, // 3205: case 0x1: {
1653 OPC_Decode, 248, 19, 7, // 3207: decode to VSTRIBR_rec using decoder 7
1654 // 3207: }
1655 2, 4, // 3211: case 0x2: {
1656 OPC_Decode, 250, 19, 7, // 3213: decode to VSTRIHL_rec using decoder 7
1657 // 3213: }
1658 3, 0, // 3217: case 0x3: {
1659 OPC_Decode, 252, 19, 7, // 3219: decode to VSTRIHR_rec using decoder 7
1660 // 3219: }
1661 // 3219: } // switch Inst[20:16]
1662 // 3219: }
1663 // 3219: } // switch Inst[0]
1664 // 3219: }
1665 17, 8, // 3223: case 0x11: {
1666 OPC_CheckField, 0, 1, 0, // 3225: check Inst[0] == 0x0
1667 OPC_Decode, 241, 19, 3, // 3229: decode to VSRO using decoder 3
1668 // 3229: }
1669 19, 12, // 3233: case 0x13: {
1670 OPC_CheckField, 19, 2, 0, // 3235: check Inst[20:19] == 0x0
1671 OPC_CheckField, 0, 1, 0, // 3239: check Inst[0] == 0x0
1672 OPC_Decode, 190, 18, 24, // 3243: decode to VGNB using decoder 24
1673 // 3243: }
1674 20, 12, // 3247: case 0x14: {
1675 OPC_CheckField, 16, 5, 0, // 3249: check Inst[20:16] == 0x0
1676 OPC_CheckField, 0, 1, 0, // 3253: check Inst[0] == 0x0
1677 OPC_Decode, 189, 18, 7, // 3257: decode to VGBBD using decoder 7
1678 // 3257: }
1679 21, 15, // 3261: case 0x15: {
1680 OPC_SwitchField, 0, 1, // 3263: switch Inst[0] {
1681 0, 4, // 3266: case 0x0: {
1682 OPC_Decode, 182, 17, 3, // 3268: decode to VBPERMQ using decoder 3
1683 // 3268: }
1684 1, 0, // 3272: case 0x1: {
1685 OPC_Decode, 185, 17, 3, // 3274: decode to VCFUGED using decoder 3
1686 // 3274: }
1687 // 3274: } // switch Inst[0]
1688 // 3274: }
1689 22, 8, // 3278: case 0x16: {
1690 OPC_CheckField, 0, 1, 1, // 3280: check Inst[0] == 0x1
1691 OPC_Decode, 167, 19, 3, // 3284: decode to VPEXTD using decoder 3
1692 // 3284: }
1693 23, 15, // 3288: case 0x17: {
1694 OPC_SwitchField, 0, 1, // 3290: switch Inst[0] {
1695 0, 4, // 3293: case 0x0: {
1696 OPC_Decode, 181, 17, 3, // 3295: decode to VBPERMD using decoder 3
1697 // 3295: }
1698 1, 0, // 3299: case 0x1: {
1699 OPC_Decode, 163, 19, 3, // 3301: decode to VPDEPD using decoder 3
1700 // 3301: }
1701 // 3301: } // switch Inst[0]
1702 // 3301: }
1703 24, 8, // 3305: case 0x18: {
1704 OPC_CheckField, 0, 1, 1, // 3307: check Inst[0] == 0x1
1705 OPC_Decode, 183, 18, 25, // 3311: decode to VEXTUBLX using decoder 25
1706 // 3311: }
1707 25, 8, // 3315: case 0x19: {
1708 OPC_CheckField, 0, 1, 1, // 3317: check Inst[0] == 0x1
1709 OPC_Decode, 185, 18, 25, // 3321: decode to VEXTUHLX using decoder 25
1710 // 3321: }
1711 26, 15, // 3325: case 0x1a: {
1712 OPC_SwitchField, 0, 1, // 3327: switch Inst[0] {
1713 0, 4, // 3330: case 0x0: {
1714 OPC_Decode, 247, 18, 3, // 3332: decode to VMRGOW using decoder 3
1715 // 3332: }
1716 1, 0, // 3336: case 0x1: {
1717 OPC_Decode, 187, 18, 25, // 3338: decode to VEXTUWLX using decoder 25
1718 // 3338: }
1719 // 3338: } // switch Inst[0]
1720 // 3338: }
1721 28, 8, // 3342: case 0x1c: {
1722 OPC_CheckField, 0, 1, 1, // 3344: check Inst[0] == 0x1
1723 OPC_Decode, 184, 18, 25, // 3348: decode to VEXTUBRX using decoder 25
1724 // 3348: }
1725 29, 8, // 3352: case 0x1d: {
1726 OPC_CheckField, 0, 1, 1, // 3354: check Inst[0] == 0x1
1727 OPC_Decode, 186, 18, 25, // 3358: decode to VEXTUHRX using decoder 25
1728 // 3358: }
1729 30, 0, // 3362: case 0x1e: {
1730 OPC_SwitchField, 0, 1, // 3364: switch Inst[0] {
1731 0, 4, // 3367: case 0x0: {
1732 OPC_Decode, 240, 18, 3, // 3369: decode to VMRGEW using decoder 3
1733 // 3369: }
1734 1, 0, // 3373: case 0x1: {
1735 OPC_Decode, 188, 18, 25, // 3375: decode to VEXTUWRX using decoder 25
1736 // 3375: }
1737 // 3375: } // switch Inst[0]
1738 // 3375: }
1739 // 3375: } // switch Inst[10:6]
1740 // 3375: }
1741 7, 232, 2, // 3379: case 0x7: {
1742 OPC_SwitchField, 6, 5, // 3382: switch Inst[10:6] {
1743 0, 15, // 3385: case 0x0: {
1744 OPC_SwitchField, 0, 1, // 3387: switch Inst[0] {
1745 0, 4, // 3390: case 0x0: {
1746 OPC_Decode, 177, 19, 3, // 3392: decode to VPKUHUM using decoder 3
1747 // 3392: }
1748 1, 0, // 3396: case 0x1: {
1749 OPC_Decode, 193, 18, 26, // 3398: decode to VINSBVLX using decoder 26
1750 // 3398: }
1751 // 3398: } // switch Inst[0]
1752 // 3398: }
1753 1, 15, // 3402: case 0x1: {
1754 OPC_SwitchField, 0, 1, // 3404: switch Inst[0] {
1755 0, 4, // 3407: case 0x0: {
1756 OPC_Decode, 179, 19, 3, // 3409: decode to VPKUWUM using decoder 3
1757 // 3409: }
1758 1, 0, // 3413: case 0x1: {
1759 OPC_Decode, 204, 18, 26, // 3415: decode to VINSHVLX using decoder 26
1760 // 3415: }
1761 // 3415: } // switch Inst[0]
1762 // 3415: }
1763 2, 15, // 3419: case 0x2: {
1764 OPC_SwitchField, 0, 1, // 3421: switch Inst[0] {
1765 0, 4, // 3424: case 0x0: {
1766 OPC_Decode, 178, 19, 3, // 3426: decode to VPKUHUS using decoder 3
1767 // 3426: }
1768 1, 0, // 3430: case 0x1: {
1769 OPC_Decode, 209, 18, 26, // 3432: decode to VINSWVLX using decoder 26
1770 // 3432: }
1771 // 3432: } // switch Inst[0]
1772 // 3432: }
1773 3, 15, // 3436: case 0x3: {
1774 OPC_SwitchField, 0, 1, // 3438: switch Inst[0] {
1775 0, 4, // 3441: case 0x0: {
1776 OPC_Decode, 180, 19, 3, // 3443: decode to VPKUWUS using decoder 3
1777 // 3443: }
1778 1, 0, // 3447: case 0x1: {
1779 OPC_Decode, 206, 18, 27, // 3449: decode to VINSW using decoder 27
1780 // 3449: }
1781 // 3449: } // switch Inst[0]
1782 // 3449: }
1783 4, 15, // 3453: case 0x4: {
1784 OPC_SwitchField, 0, 1, // 3455: switch Inst[0] {
1785 0, 4, // 3458: case 0x0: {
1786 OPC_Decode, 172, 19, 3, // 3460: decode to VPKSHUS using decoder 3
1787 // 3460: }
1788 1, 0, // 3464: case 0x1: {
1789 OPC_Decode, 194, 18, 26, // 3466: decode to VINSBVRX using decoder 26
1790 // 3466: }
1791 // 3466: } // switch Inst[0]
1792 // 3466: }
1793 5, 15, // 3470: case 0x5: {
1794 OPC_SwitchField, 0, 1, // 3472: switch Inst[0] {
1795 0, 4, // 3475: case 0x0: {
1796 OPC_Decode, 174, 19, 3, // 3477: decode to VPKSWUS using decoder 3
1797 // 3477: }
1798 1, 0, // 3481: case 0x1: {
1799 OPC_Decode, 205, 18, 26, // 3483: decode to VINSHVRX using decoder 26
1800 // 3483: }
1801 // 3483: } // switch Inst[0]
1802 // 3483: }
1803 6, 15, // 3487: case 0x6: {
1804 OPC_SwitchField, 0, 1, // 3489: switch Inst[0] {
1805 0, 4, // 3492: case 0x0: {
1806 OPC_Decode, 171, 19, 3, // 3494: decode to VPKSHSS using decoder 3
1807 // 3494: }
1808 1, 0, // 3498: case 0x1: {
1809 OPC_Decode, 210, 18, 26, // 3500: decode to VINSWVRX using decoder 26
1810 // 3500: }
1811 // 3500: } // switch Inst[0]
1812 // 3500: }
1813 7, 15, // 3504: case 0x7: {
1814 OPC_SwitchField, 0, 1, // 3506: switch Inst[0] {
1815 0, 4, // 3509: case 0x0: {
1816 OPC_Decode, 173, 19, 3, // 3511: decode to VPKSWSS using decoder 3
1817 // 3511: }
1818 1, 0, // 3515: case 0x1: {
1819 OPC_Decode, 195, 18, 28, // 3517: decode to VINSD using decoder 28
1820 // 3517: }
1821 // 3517: } // switch Inst[0]
1822 // 3517: }
1823 8, 19, // 3521: case 0x8: {
1824 OPC_SwitchField, 0, 1, // 3523: switch Inst[0] {
1825 0, 8, // 3526: case 0x0: {
1826 OPC_CheckField, 16, 5, 0, // 3528: check Inst[20:16] == 0x0
1827 OPC_Decode, 153, 20, 7, // 3532: decode to VUPKHSB using decoder 7
1828 // 3532: }
1829 1, 0, // 3536: case 0x1: {
1830 OPC_Decode, 191, 18, 29, // 3538: decode to VINSBLX using decoder 29
1831 // 3538: }
1832 // 3538: } // switch Inst[0]
1833 // 3538: }
1834 9, 19, // 3542: case 0x9: {
1835 OPC_SwitchField, 0, 1, // 3544: switch Inst[0] {
1836 0, 8, // 3547: case 0x0: {
1837 OPC_CheckField, 16, 5, 0, // 3549: check Inst[20:16] == 0x0
1838 OPC_Decode, 154, 20, 7, // 3553: decode to VUPKHSH using decoder 7
1839 // 3553: }
1840 1, 0, // 3557: case 0x1: {
1841 OPC_Decode, 202, 18, 29, // 3559: decode to VINSHLX using decoder 29
1842 // 3559: }
1843 // 3559: } // switch Inst[0]
1844 // 3559: }
1845 10, 19, // 3563: case 0xa: {
1846 OPC_SwitchField, 0, 1, // 3565: switch Inst[0] {
1847 0, 8, // 3568: case 0x0: {
1848 OPC_CheckField, 16, 5, 0, // 3570: check Inst[20:16] == 0x0
1849 OPC_Decode, 162, 20, 7, // 3574: decode to VUPKLSB using decoder 7
1850 // 3574: }
1851 1, 0, // 3578: case 0x1: {
1852 OPC_Decode, 207, 18, 29, // 3580: decode to VINSWLX using decoder 29
1853 // 3580: }
1854 // 3580: } // switch Inst[0]
1855 // 3580: }
1856 11, 19, // 3584: case 0xb: {
1857 OPC_SwitchField, 0, 1, // 3586: switch Inst[0] {
1858 0, 8, // 3589: case 0x0: {
1859 OPC_CheckField, 16, 5, 0, // 3591: check Inst[20:16] == 0x0
1860 OPC_Decode, 163, 20, 7, // 3595: decode to VUPKLSH using decoder 7
1861 // 3595: }
1862 1, 0, // 3599: case 0x1: {
1863 OPC_Decode, 196, 18, 30, // 3601: decode to VINSDLX using decoder 30
1864 // 3601: }
1865 // 3601: } // switch Inst[0]
1866 // 3601: }
1867 12, 15, // 3605: case 0xc: {
1868 OPC_SwitchField, 0, 1, // 3607: switch Inst[0] {
1869 0, 4, // 3610: case 0x0: {
1870 OPC_Decode, 168, 19, 3, // 3612: decode to VPKPX using decoder 3
1871 // 3612: }
1872 1, 0, // 3616: case 0x1: {
1873 OPC_Decode, 192, 18, 29, // 3618: decode to VINSBRX using decoder 29
1874 // 3618: }
1875 // 3618: } // switch Inst[0]
1876 // 3618: }
1877 13, 19, // 3622: case 0xd: {
1878 OPC_SwitchField, 0, 1, // 3624: switch Inst[0] {
1879 0, 8, // 3627: case 0x0: {
1880 OPC_CheckField, 16, 5, 0, // 3629: check Inst[20:16] == 0x0
1881 OPC_Decode, 152, 20, 7, // 3633: decode to VUPKHPX using decoder 7
1882 // 3633: }
1883 1, 0, // 3637: case 0x1: {
1884 OPC_Decode, 203, 18, 29, // 3639: decode to VINSHRX using decoder 29
1885 // 3639: }
1886 // 3639: } // switch Inst[0]
1887 // 3639: }
1888 14, 8, // 3643: case 0xe: {
1889 OPC_CheckField, 0, 1, 1, // 3645: check Inst[0] == 0x1
1890 OPC_Decode, 208, 18, 29, // 3649: decode to VINSWRX using decoder 29
1891 // 3649: }
1892 15, 19, // 3653: case 0xf: {
1893 OPC_SwitchField, 0, 1, // 3655: switch Inst[0] {
1894 0, 8, // 3658: case 0x0: {
1895 OPC_CheckField, 16, 5, 0, // 3660: check Inst[20:16] == 0x0
1896 OPC_Decode, 161, 20, 7, // 3664: decode to VUPKLPX using decoder 7
1897 // 3664: }
1898 1, 0, // 3668: case 0x1: {
1899 OPC_Decode, 197, 18, 30, // 3670: decode to VINSDRX using decoder 30
1900 // 3670: }
1901 // 3670: } // switch Inst[0]
1902 // 3670: }
1903 17, 8, // 3674: case 0x11: {
1904 OPC_CheckField, 0, 1, 0, // 3676: check Inst[0] == 0x0
1905 OPC_Decode, 175, 19, 3, // 3680: decode to VPKUDUM using decoder 3
1906 // 3680: }
1907 19, 8, // 3684: case 0x13: {
1908 OPC_CheckField, 0, 1, 0, // 3686: check Inst[0] == 0x0
1909 OPC_Decode, 176, 19, 3, // 3690: decode to VPKUDUS using decoder 3
1910 // 3690: }
1911 21, 8, // 3694: case 0x15: {
1912 OPC_CheckField, 0, 1, 0, // 3696: check Inst[0] == 0x0
1913 OPC_Decode, 170, 19, 3, // 3700: decode to VPKSDUS using decoder 3
1914 // 3700: }
1915 23, 8, // 3704: case 0x17: {
1916 OPC_CheckField, 0, 1, 0, // 3706: check Inst[0] == 0x0
1917 OPC_Decode, 169, 19, 3, // 3710: decode to VPKSDSS using decoder 3
1918 // 3710: }
1919 25, 12, // 3714: case 0x19: {
1920 OPC_CheckField, 16, 5, 0, // 3716: check Inst[20:16] == 0x0
1921 OPC_CheckField, 0, 1, 0, // 3720: check Inst[0] == 0x0
1922 OPC_Decode, 156, 20, 7, // 3724: decode to VUPKHSW using decoder 7
1923 // 3724: }
1924 27, 0, // 3728: case 0x1b: {
1925 OPC_CheckField, 16, 5, 0, // 3730: check Inst[20:16] == 0x0
1926 OPC_CheckField, 0, 1, 0, // 3734: check Inst[0] == 0x0
1927 OPC_Decode, 165, 20, 7, // 3738: decode to VUPKLSW using decoder 7
1928 // 3738: }
1929 // 3738: } // switch Inst[10:6]
1930 // 3738: }
1931 10, 4, // 3742: case 0xa: {
1932 OPC_Decode, 170, 12, 31, // 3744: decode to MTVSRBMI using decoder 31
1933 // 3744: }
1934 11, 26, // 3748: case 0xb: {
1935 OPC_SwitchField, 0, 1, // 3750: switch Inst[0] {
1936 0, 15, // 3753: case 0x0: {
1937 OPC_SwitchField, 9, 2, // 3755: switch Inst[10:9] {
1938 0, 4, // 3758: case 0x0: {
1939 OPC_Decode, 216, 19, 32, // 3760: decode to VSLDBI using decoder 32
1940 // 3760: }
1941 1, 0, // 3764: case 0x1: {
1942 OPC_Decode, 239, 19, 32, // 3766: decode to VSRDBI using decoder 32
1943 // 3766: }
1944 // 3766: } // switch Inst[10:9]
1945 // 3766: }
1946 1, 0, // 3770: case 0x1: {
1947 OPC_Decode, 248, 18, 33, // 3772: decode to VMSUMCUD using decoder 33
1948 // 3772: }
1949 // 3772: } // switch Inst[0]
1950 // 3772: }
1951 12, 15, // 3776: case 0xc: {
1952 OPC_SwitchField, 0, 1, // 3778: switch Inst[0] {
1953 0, 4, // 3781: case 0x0: {
1954 OPC_Decode, 157, 18, 34, // 3783: decode to VEXTDUBVLX using decoder 34
1955 // 3783: }
1956 1, 0, // 3787: case 0x1: {
1957 OPC_Decode, 158, 18, 34, // 3789: decode to VEXTDUBVRX using decoder 34
1958 // 3789: }
1959 // 3789: } // switch Inst[0]
1960 // 3789: }
1961 13, 15, // 3793: case 0xd: {
1962 OPC_SwitchField, 0, 1, // 3795: switch Inst[0] {
1963 0, 4, // 3798: case 0x0: {
1964 OPC_Decode, 159, 18, 34, // 3800: decode to VEXTDUHVLX using decoder 34
1965 // 3800: }
1966 1, 0, // 3804: case 0x1: {
1967 OPC_Decode, 160, 18, 34, // 3806: decode to VEXTDUHVRX using decoder 34
1968 // 3806: }
1969 // 3806: } // switch Inst[0]
1970 // 3806: }
1971 14, 15, // 3810: case 0xe: {
1972 OPC_SwitchField, 0, 1, // 3812: switch Inst[0] {
1973 0, 4, // 3815: case 0x0: {
1974 OPC_Decode, 161, 18, 34, // 3817: decode to VEXTDUWVLX using decoder 34
1975 // 3817: }
1976 1, 0, // 3821: case 0x1: {
1977 OPC_Decode, 162, 18, 34, // 3823: decode to VEXTDUWVRX using decoder 34
1978 // 3823: }
1979 // 3823: } // switch Inst[0]
1980 // 3823: }
1981 15, 15, // 3827: case 0xf: {
1982 OPC_SwitchField, 0, 1, // 3829: switch Inst[0] {
1983 0, 4, // 3832: case 0x0: {
1984 OPC_Decode, 155, 18, 34, // 3834: decode to VEXTDDVLX using decoder 34
1985 // 3834: }
1986 1, 0, // 3838: case 0x1: {
1987 OPC_Decode, 156, 18, 34, // 3840: decode to VEXTDDVRX using decoder 34
1988 // 3840: }
1989 // 3840: } // switch Inst[0]
1990 // 3840: }
1991 16, 15, // 3844: case 0x10: {
1992 OPC_SwitchField, 0, 1, // 3846: switch Inst[0] {
1993 0, 4, // 3849: case 0x0: {
1994 OPC_Decode, 222, 18, 33, // 3851: decode to VMHADDSHS using decoder 33
1995 // 3851: }
1996 1, 0, // 3855: case 0x1: {
1997 OPC_Decode, 223, 18, 33, // 3857: decode to VMHRADDSHS using decoder 33
1998 // 3857: }
1999 // 3857: } // switch Inst[0]
2000 // 3857: }
2001 17, 15, // 3861: case 0x11: {
2002 OPC_SwitchField, 0, 1, // 3863: switch Inst[0] {
2003 0, 4, // 3866: case 0x0: {
2004 OPC_Decode, 233, 18, 33, // 3868: decode to VMLADDUHM using decoder 33
2005 // 3868: }
2006 1, 0, // 3872: case 0x1: {
2007 OPC_Decode, 253, 18, 33, // 3874: decode to VMSUMUDM using decoder 33
2008 // 3874: }
2009 // 3874: } // switch Inst[0]
2010 // 3874: }
2011 18, 15, // 3878: case 0x12: {
2012 OPC_SwitchField, 0, 1, // 3880: switch Inst[0] {
2013 0, 4, // 3883: case 0x0: {
2014 OPC_Decode, 252, 18, 33, // 3885: decode to VMSUMUBM using decoder 33
2015 // 3885: }
2016 1, 0, // 3889: case 0x1: {
2017 OPC_Decode, 249, 18, 33, // 3891: decode to VMSUMMBM using decoder 33
2018 // 3891: }
2019 // 3891: } // switch Inst[0]
2020 // 3891: }
2021 19, 15, // 3895: case 0x13: {
2022 OPC_SwitchField, 0, 1, // 3897: switch Inst[0] {
2023 0, 4, // 3900: case 0x0: {
2024 OPC_Decode, 254, 18, 33, // 3902: decode to VMSUMUHM using decoder 33
2025 // 3902: }
2026 1, 0, // 3906: case 0x1: {
2027 OPC_Decode, 255, 18, 33, // 3908: decode to VMSUMUHS using decoder 33
2028 // 3908: }
2029 // 3908: } // switch Inst[0]
2030 // 3908: }
2031 20, 15, // 3912: case 0x14: {
2032 OPC_SwitchField, 0, 1, // 3914: switch Inst[0] {
2033 0, 4, // 3917: case 0x0: {
2034 OPC_Decode, 250, 18, 33, // 3919: decode to VMSUMSHM using decoder 33
2035 // 3919: }
2036 1, 0, // 3923: case 0x1: {
2037 OPC_Decode, 251, 18, 33, // 3925: decode to VMSUMSHS using decoder 33
2038 // 3925: }
2039 // 3925: } // switch Inst[0]
2040 // 3925: }
2041 21, 15, // 3929: case 0x15: {
2042 OPC_SwitchField, 0, 1, // 3931: switch Inst[0] {
2043 0, 4, // 3934: case 0x0: {
2044 OPC_Decode, 210, 19, 33, // 3936: decode to VSEL using decoder 33
2045 // 3936: }
2046 1, 0, // 3940: case 0x1: {
2047 OPC_Decode, 164, 19, 33, // 3942: decode to VPERM using decoder 33
2048 // 3942: }
2049 // 3942: } // switch Inst[0]
2050 // 3942: }
2051 22, 19, // 3946: case 0x16: {
2052 OPC_SwitchField, 0, 1, // 3948: switch Inst[0] {
2053 0, 8, // 3951: case 0x0: {
2054 OPC_CheckField, 10, 1, 0, // 3953: check Inst[10] == 0x0
2055 OPC_Decode, 217, 19, 35, // 3957: decode to VSLDOI using decoder 35
2056 // 3957: }
2057 1, 0, // 3961: case 0x1: {
2058 OPC_Decode, 166, 19, 33, // 3963: decode to VPERMXOR using decoder 33
2059 // 3963: }
2060 // 3963: } // switch Inst[0]
2061 // 3963: }
2062 23, 15, // 3967: case 0x17: {
2063 OPC_SwitchField, 0, 1, // 3969: switch Inst[0] {
2064 0, 4, // 3972: case 0x0: {
2065 OPC_Decode, 212, 18, 36, // 3974: decode to VMADDFP using decoder 36
2066 // 3974: }
2067 1, 0, // 3978: case 0x1: {
2068 OPC_Decode, 159, 19, 36, // 3980: decode to VNMSUBFP using decoder 36
2069 // 3980: }
2070 // 3980: } // switch Inst[0]
2071 // 3980: }
2072 24, 15, // 3984: case 0x18: {
2073 OPC_SwitchField, 0, 1, // 3986: switch Inst[0] {
2074 0, 4, // 3989: case 0x0: {
2075 OPC_Decode, 213, 11, 37, // 3991: decode to MADDHD using decoder 37
2076 // 3991: }
2077 1, 0, // 3995: case 0x1: {
2078 OPC_Decode, 214, 11, 37, // 3997: decode to MADDHDU using decoder 37
2079 // 3997: }
2080 // 3997: } // switch Inst[0]
2081 // 3997: }
2082 25, 8, // 4001: case 0x19: {
2083 OPC_CheckField, 0, 1, 1, // 4003: check Inst[0] == 0x1
2084 OPC_Decode, 215, 11, 38, // 4007: decode to MADDLD using decoder 38
2085 // 4007: }
2086 29, 8, // 4011: case 0x1d: {
2087 OPC_CheckField, 0, 1, 1, // 4013: check Inst[0] == 0x1
2088 OPC_Decode, 165, 19, 33, // 4017: decode to VPERMR using decoder 33
2089 // 4017: }
2090 30, 15, // 4021: case 0x1e: {
2091 OPC_SwitchField, 0, 1, // 4023: switch Inst[0] {
2092 0, 4, // 4026: case 0x0: {
2093 OPC_Decode, 160, 17, 33, // 4028: decode to VADDEUQM using decoder 33
2094 // 4028: }
2095 1, 0, // 4032: case 0x1: {
2096 OPC_Decode, 159, 17, 33, // 4034: decode to VADDECUQ using decoder 33
2097 // 4034: }
2098 // 4034: } // switch Inst[0]
2099 // 4034: }
2100 31, 0, // 4038: case 0x1f: {
2101 OPC_SwitchField, 0, 1, // 4040: switch Inst[0] {
2102 0, 4, // 4043: case 0x0: {
2103 OPC_Decode, 128, 20, 33, // 4045: decode to VSUBEUQM using decoder 33
2104 // 4045: }
2105 1, 0, // 4049: case 0x1: {
2106 OPC_Decode, 255, 19, 33, // 4051: decode to VSUBECUQ using decoder 33
2107 // 4051: }
2108 // 4051: } // switch Inst[0]
2109 // 4051: }
2110 // 4051: } // switch Inst[5:1]
2111 // 4051: }
2112 6, 15, // 4055: case 0x6: {
2113 OPC_SwitchField, 0, 4, // 4057: switch Inst[3:0] {
2114 0, 4, // 4060: case 0x0: {
2115 OPC_Decode, 199, 11, 39, // 4062: decode to LXVP using decoder 39
2116 // 4062: }
2117 1, 0, // 4066: case 0x1: {
2118 OPC_Decode, 166, 16, 39, // 4068: decode to STXVP using decoder 39
2119 // 4068: }
2120 // 4068: } // switch Inst[3:0]
2121 // 4068: }
2122 7, 4, // 4072: case 0x7: {
2123 OPC_Decode, 192, 12, 40, // 4074: decode to MULLI using decoder 40
2124 // 4074: }
2125 8, 4, // 4078: case 0x8: {
2126 OPC_Decode, 200, 16, 40, // 4080: decode to SUBFIC using decoder 40
2127 // 4080: }
2128 10, 15, // 4084: case 0xa: {
2129 OPC_SwitchField, 21, 2, // 4086: switch Inst[22:21] {
2130 0, 4, // 4089: case 0x0: {
2131 OPC_Decode, 182, 5, 41, // 4091: decode to CMPLWI using decoder 41
2132 // 4091: }
2133 1, 0, // 4095: case 0x1: {
2134 OPC_Decode, 180, 5, 42, // 4097: decode to CMPLDI using decoder 42
2135 // 4097: }
2136 // 4097: } // switch Inst[22:21]
2137 // 4097: }
2138 11, 15, // 4101: case 0xb: {
2139 OPC_SwitchField, 21, 2, // 4103: switch Inst[22:21] {
2140 0, 4, // 4106: case 0x0: {
2141 OPC_Decode, 186, 5, 43, // 4108: decode to CMPWI using decoder 43
2142 // 4108: }
2143 1, 0, // 4112: case 0x1: {
2144 OPC_Decode, 177, 5, 44, // 4114: decode to CMPDI using decoder 44
2145 // 4114: }
2146 // 4114: } // switch Inst[22:21]
2147 // 4114: }
2148 12, 4, // 4118: case 0xc: {
2149 OPC_Decode, 189, 3, 40, // 4120: decode to ADDIC using decoder 40
2150 // 4120: }
2151 13, 4, // 4124: case 0xd: {
2152 OPC_Decode, 191, 3, 40, // 4126: decode to ADDIC_rec using decoder 40
2153 // 4126: }
2154 14, 14, // 4130: case 0xe: {
2155 OPC_Scope, 8, // 4132: try {
2156 OPC_CheckField, 16, 5, 0, // 4134: check Inst[20:16] == 0x0
2157 OPC_Decode, 136, 11, 45, // 4138: decode to LI using decoder 45
2158 // 4138: } else try {
2159 OPC_Decode, 187, 3, 46, // 4142: decode to ADDI using decoder 46
2160 // 4142: }
2161 // 4142: }
2162 15, 14, // 4146: case 0xf: {
2163 OPC_Scope, 8, // 4148: try {
2164 OPC_CheckField, 16, 5, 0, // 4150: check Inst[20:16] == 0x0
2165 OPC_Decode, 138, 11, 45, // 4154: decode to LIS using decoder 45
2166 // 4154: } else try {
2167 OPC_Decode, 192, 3, 46, // 4158: decode to ADDIS using decoder 46
2168 // 4158: }
2169 // 4158: }
2170 16, 215, 1, // 4162: case 0x10: {
2171 OPC_SwitchField, 0, 2, // 4165: switch Inst[1:0] {
2172 0, 51, // 4168: case 0x0: {
2173 OPC_Scope, 45, // 4170: try {
2174 OPC_SwitchField, 16, 10, // 4172: switch Inst[25:16] {
2175 128, 4, 4, // 4175: case 0x200: {
2176 OPC_Decode, 225, 4, 47, // 4178: decode to BDNZ using decoder 47
2177 // 4178: }
2178 192, 4, 4, // 4182: case 0x240: {
2179 OPC_Decode, 245, 4, 47, // 4185: decode to BDZ using decoder 47
2180 // 4185: }
2181 128, 6, 4, // 4189: case 0x300: {
2182 OPC_Decode, 243, 4, 47, // 4192: decode to BDNZm using decoder 47
2183 // 4192: }
2184 160, 6, 4, // 4196: case 0x320: {
2185 OPC_Decode, 244, 4, 47, // 4199: decode to BDNZp using decoder 47
2186 // 4199: }
2187 192, 6, 4, // 4203: case 0x340: {
2188 OPC_Decode, 135, 5, 47, // 4206: decode to BDZm using decoder 47
2189 // 4206: }
2190 224, 6, 0, // 4210: case 0x360: {
2191 OPC_Decode, 136, 5, 47, // 4213: decode to BDZp using decoder 47
2192 // 4213: }
2193 // 4213: } // switch Inst[25:16]
2194 // 4213: } else try {
2195 OPC_Decode, 171, 23, 48, // 4217: decode to gBC using decoder 48
2196 // 4217: }
2197 // 4217: }
2198 1, 51, // 4221: case 0x1: {
2199 OPC_Scope, 45, // 4223: try {
2200 OPC_SwitchField, 16, 10, // 4225: switch Inst[25:16] {
2201 128, 4, 4, // 4228: case 0x200: {
2202 OPC_Decode, 230, 4, 47, // 4231: decode to BDNZL using decoder 47
2203 // 4231: }
2204 192, 4, 4, // 4235: case 0x240: {
2205 OPC_Decode, 250, 4, 47, // 4238: decode to BDZL using decoder 47
2206 // 4238: }
2207 128, 6, 4, // 4242: case 0x300: {
2208 OPC_Decode, 241, 4, 47, // 4245: decode to BDNZLm using decoder 47
2209 // 4245: }
2210 160, 6, 4, // 4249: case 0x320: {
2211 OPC_Decode, 242, 4, 47, // 4252: decode to BDNZLp using decoder 47
2212 // 4252: }
2213 192, 6, 4, // 4256: case 0x340: {
2214 OPC_Decode, 133, 5, 47, // 4259: decode to BDZLm using decoder 47
2215 // 4259: }
2216 224, 6, 0, // 4263: case 0x360: {
2217 OPC_Decode, 134, 5, 47, // 4266: decode to BDZLp using decoder 47
2218 // 4266: }
2219 // 4266: } // switch Inst[25:16]
2220 // 4266: } else try {
2221 OPC_Decode, 176, 23, 48, // 4270: decode to gBCL using decoder 48
2222 // 4270: }
2223 // 4270: }
2224 2, 51, // 4274: case 0x2: {
2225 OPC_Scope, 45, // 4276: try {
2226 OPC_SwitchField, 16, 10, // 4278: switch Inst[25:16] {
2227 128, 4, 4, // 4281: case 0x200: {
2228 OPC_Decode, 227, 4, 47, // 4284: decode to BDNZA using decoder 47
2229 // 4284: }
2230 192, 4, 4, // 4288: case 0x240: {
2231 OPC_Decode, 247, 4, 47, // 4291: decode to BDZA using decoder 47
2232 // 4291: }
2233 128, 6, 4, // 4295: case 0x300: {
2234 OPC_Decode, 228, 4, 47, // 4298: decode to BDNZAm using decoder 47
2235 // 4298: }
2236 160, 6, 4, // 4302: case 0x320: {
2237 OPC_Decode, 229, 4, 47, // 4305: decode to BDNZAp using decoder 47
2238 // 4305: }
2239 192, 6, 4, // 4309: case 0x340: {
2240 OPC_Decode, 248, 4, 47, // 4312: decode to BDZAm using decoder 47
2241 // 4312: }
2242 224, 6, 0, // 4316: case 0x360: {
2243 OPC_Decode, 249, 4, 47, // 4319: decode to BDZAp using decoder 47
2244 // 4319: }
2245 // 4319: } // switch Inst[25:16]
2246 // 4319: } else try {
2247 OPC_Decode, 172, 23, 48, // 4323: decode to gBCA using decoder 48
2248 // 4323: }
2249 // 4323: }
2250 3, 0, // 4327: case 0x3: {
2251 OPC_Scope, 45, // 4329: try {
2252 OPC_SwitchField, 16, 10, // 4331: switch Inst[25:16] {
2253 128, 4, 4, // 4334: case 0x200: {
2254 OPC_Decode, 231, 4, 47, // 4337: decode to BDNZLA using decoder 47
2255 // 4337: }
2256 192, 4, 4, // 4341: case 0x240: {
2257 OPC_Decode, 251, 4, 47, // 4344: decode to BDZLA using decoder 47
2258 // 4344: }
2259 128, 6, 4, // 4348: case 0x300: {
2260 OPC_Decode, 232, 4, 47, // 4351: decode to BDNZLAm using decoder 47
2261 // 4351: }
2262 160, 6, 4, // 4355: case 0x320: {
2263 OPC_Decode, 233, 4, 47, // 4358: decode to BDNZLAp using decoder 47
2264 // 4358: }
2265 192, 6, 4, // 4362: case 0x340: {
2266 OPC_Decode, 252, 4, 47, // 4365: decode to BDZLAm using decoder 47
2267 // 4365: }
2268 224, 6, 0, // 4369: case 0x360: {
2269 OPC_Decode, 253, 4, 47, // 4372: decode to BDZLAp using decoder 47
2270 // 4372: }
2271 // 4372: } // switch Inst[25:16]
2272 // 4372: } else try {
2273 OPC_Decode, 177, 23, 48, // 4376: decode to gBCLA using decoder 48
2274 // 4376: }
2275 // 4376: }
2276 // 4376: } // switch Inst[1:0]
2277 // 4376: }
2278 17, 15, // 4380: case 0x11: {
2279 OPC_SwitchField, 0, 2, // 4382: switch Inst[1:0] {
2280 1, 4, // 4385: case 0x1: {
2281 OPC_Decode, 245, 14, 49, // 4387: decode to SCV using decoder 49
2282 // 4387: }
2283 2, 0, // 4391: case 0x2: {
2284 OPC_Decode, 244, 14, 49, // 4393: decode to SC using decoder 49
2285 // 4393: }
2286 // 4393: } // switch Inst[1:0]
2287 // 4393: }
2288 18, 27, // 4397: case 0x12: {
2289 OPC_SwitchField, 0, 2, // 4399: switch Inst[1:0] {
2290 0, 4, // 4402: case 0x0: {
2291 OPC_Decode, 171, 4, 50, // 4404: decode to B using decoder 50
2292 // 4404: }
2293 1, 4, // 4408: case 0x1: {
2294 OPC_Decode, 137, 5, 50, // 4410: decode to BL using decoder 50
2295 // 4410: }
2296 2, 4, // 4414: case 0x2: {
2297 OPC_Decode, 172, 4, 50, // 4416: decode to BA using decoder 50
2298 // 4416: }
2299 3, 0, // 4420: case 0x3: {
2300 OPC_Decode, 148, 5, 50, // 4422: decode to BLA using decoder 50
2301 // 4422: }
2302 // 4422: } // switch Inst[1:0]
2303 // 4422: }
2304 19, 251, 3, // 4426: case 0x13: {
2305 OPC_SwitchField, 1, 5, // 4429: switch Inst[5:1] {
2306 0, 16, // 4432: case 0x0: {
2307 OPC_CheckField, 21, 2, 0, // 4434: check Inst[22:21] == 0x0
2308 OPC_CheckField, 6, 12, 0, // 4438: check Inst[17:6] == 0x0
2309 OPC_CheckField, 0, 1, 0, // 4442: check Inst[0] == 0x0
2310 OPC_Decode, 218, 11, 51, // 4446: decode to MCRF using decoder 51
2311 // 4446: }
2312 1, 83, // 4450: case 0x1: {
2313 OPC_SwitchField, 6, 5, // 4452: switch Inst[10:6] {
2314 1, 8, // 4455: case 0x1: {
2315 OPC_CheckField, 0, 1, 0, // 4457: check Inst[0] == 0x0
2316 OPC_Decode, 212, 5, 52, // 4461: decode to CRNOR using decoder 52
2317 // 4461: }
2318 4, 8, // 4465: case 0x4: {
2319 OPC_CheckField, 0, 1, 0, // 4467: check Inst[0] == 0x0
2320 OPC_Decode, 209, 5, 52, // 4471: decode to CRANDC using decoder 52
2321 // 4471: }
2322 6, 8, // 4475: case 0x6: {
2323 OPC_CheckField, 0, 1, 0, // 4477: check Inst[0] == 0x0
2324 OPC_Decode, 218, 5, 52, // 4481: decode to CRXOR using decoder 52
2325 // 4481: }
2326 7, 8, // 4485: case 0x7: {
2327 OPC_CheckField, 0, 1, 0, // 4487: check Inst[0] == 0x0
2328 OPC_Decode, 211, 5, 52, // 4491: decode to CRNAND using decoder 52
2329 // 4491: }
2330 8, 8, // 4495: case 0x8: {
2331 OPC_CheckField, 0, 1, 0, // 4497: check Inst[0] == 0x0
2332 OPC_Decode, 208, 5, 52, // 4501: decode to CRAND using decoder 52
2333 // 4501: }
2334 9, 8, // 4505: case 0x9: {
2335 OPC_CheckField, 0, 1, 0, // 4507: check Inst[0] == 0x0
2336 OPC_Decode, 210, 5, 52, // 4511: decode to CREQV using decoder 52
2337 // 4511: }
2338 13, 8, // 4515: case 0xd: {
2339 OPC_CheckField, 0, 1, 0, // 4517: check Inst[0] == 0x0
2340 OPC_Decode, 215, 5, 52, // 4521: decode to CRORC using decoder 52
2341 // 4521: }
2342 14, 0, // 4525: case 0xe: {
2343 OPC_CheckField, 0, 1, 0, // 4527: check Inst[0] == 0x0
2344 OPC_Decode, 214, 5, 52, // 4531: decode to CROR using decoder 52
2345 // 4531: }
2346 // 4531: } // switch Inst[10:6]
2347 // 4531: }
2348 2, 4, // 4535: case 0x2: {
2349 OPC_Decode, 223, 3, 53, // 4537: decode to ADDPCIS using decoder 53
2350 // 4537: }
2351 6, 12, // 4541: case 0x6: {
2352 OPC_CheckField, 6, 20, 1, // 4543: check Inst[25:6] == 0x1
2353 OPC_CheckField, 0, 1, 0, // 4547: check Inst[0] == 0x0
2354 OPC_Decode, 214, 14, 0, // 4551: decode to RFMCI using decoder 0
2355 // 4551: }
2356 7, 12, // 4555: case 0x7: {
2357 OPC_CheckField, 6, 20, 1, // 4557: check Inst[25:6] == 0x1
2358 OPC_CheckField, 0, 1, 0, // 4561: check Inst[0] == 0x0
2359 OPC_Decode, 210, 14, 0, // 4565: decode to RFDI using decoder 0
2360 // 4565: }
2361 16, 247, 1, // 4569: case 0x10: {
2362 OPC_SwitchField, 0, 1, // 4572: switch Inst[0] {
2363 0, 120, // 4575: case 0x0: {
2364 OPC_SwitchField, 6, 5, // 4577: switch Inst[10:6] {
2365 0, 90, // 4580: case 0x0: {
2366 OPC_CheckField, 13, 3, 0, // 4582: check Inst[15:13] == 0x0
2367 OPC_Scope, 80, // 4586: try {
2368 OPC_SwitchField, 16, 10, // 4588: switch Inst[25:16] {
2369 128, 4, 8, // 4591: case 0x200: {
2370 OPC_CheckField, 11, 2, 0, // 4594: check Inst[12:11] == 0x0
2371 OPC_Decode, 234, 4, 0, // 4598: decode to BDNZLR using decoder 0
2372 // 4598: }
2373 192, 4, 8, // 4602: case 0x240: {
2374 OPC_CheckField, 11, 2, 0, // 4605: check Inst[12:11] == 0x0
2375 OPC_Decode, 254, 4, 0, // 4609: decode to BDZLR using decoder 0
2376 // 4609: }
2377 128, 5, 8, // 4613: case 0x280: {
2378 OPC_CheckField, 11, 2, 0, // 4616: check Inst[12:11] == 0x0
2379 OPC_Decode, 154, 5, 0, // 4620: decode to BLR using decoder 0
2380 // 4620: }
2381 128, 6, 8, // 4624: case 0x300: {
2382 OPC_CheckField, 11, 2, 0, // 4627: check Inst[12:11] == 0x0
2383 OPC_Decode, 239, 4, 0, // 4631: decode to BDNZLRm using decoder 0
2384 // 4631: }
2385 160, 6, 8, // 4635: case 0x320: {
2386 OPC_CheckField, 11, 2, 0, // 4638: check Inst[12:11] == 0x0
2387 OPC_Decode, 240, 4, 0, // 4642: decode to BDNZLRp using decoder 0
2388 // 4642: }
2389 192, 6, 8, // 4646: case 0x340: {
2390 OPC_CheckField, 11, 2, 0, // 4649: check Inst[12:11] == 0x0
2391 OPC_Decode, 131, 5, 0, // 4653: decode to BDZLRm using decoder 0
2392 // 4653: }
2393 224, 6, 0, // 4657: case 0x360: {
2394 OPC_CheckField, 11, 2, 0, // 4660: check Inst[12:11] == 0x0
2395 OPC_Decode, 132, 5, 0, // 4664: decode to BDZLRp using decoder 0
2396 // 4664: }
2397 // 4664: } // switch Inst[25:16]
2398 // 4664: } else try {
2399 OPC_Decode, 179, 23, 54, // 4668: decode to gBCLR using decoder 54
2400 // 4668: }
2401 // 4668: }
2402 16, 0, // 4672: case 0x10: {
2403 OPC_CheckField, 13, 3, 0, // 4674: check Inst[15:13] == 0x0
2404 OPC_Scope, 13, // 4678: try {
2405 OPC_CheckField, 11, 2, 0, // 4680: check Inst[12:11] == 0x0
2406 OPC_CheckField, 16, 10, 128, 5, // 4684: check Inst[25:16] == 0x280
2407 OPC_Decode, 214, 4, 0, // 4689: decode to BCTR using decoder 0
2408 // 4689: } else try {
2409 OPC_Decode, 174, 23, 54, // 4693: decode to gBCCTR using decoder 54
2410 // 4693: }
2411 // 4693: }
2412 // 4693: } // switch Inst[10:6]
2413 // 4693: }
2414 1, 0, // 4697: case 0x1: {
2415 OPC_SwitchField, 6, 5, // 4699: switch Inst[10:6] {
2416 0, 90, // 4702: case 0x0: {
2417 OPC_CheckField, 13, 3, 0, // 4704: check Inst[15:13] == 0x0
2418 OPC_Scope, 80, // 4708: try {
2419 OPC_SwitchField, 16, 10, // 4710: switch Inst[25:16] {
2420 128, 4, 8, // 4713: case 0x200: {
2421 OPC_CheckField, 11, 2, 0, // 4716: check Inst[12:11] == 0x0
2422 OPC_Decode, 236, 4, 0, // 4720: decode to BDNZLRL using decoder 0
2423 // 4720: }
2424 192, 4, 8, // 4724: case 0x240: {
2425 OPC_CheckField, 11, 2, 0, // 4727: check Inst[12:11] == 0x0
2426 OPC_Decode, 128, 5, 0, // 4731: decode to BDZLRL using decoder 0
2427 // 4731: }
2428 128, 5, 8, // 4735: case 0x280: {
2429 OPC_CheckField, 11, 2, 0, // 4738: check Inst[12:11] == 0x0
2430 OPC_Decode, 156, 5, 0, // 4742: decode to BLRL using decoder 0
2431 // 4742: }
2432 128, 6, 8, // 4746: case 0x300: {
2433 OPC_CheckField, 11, 2, 0, // 4749: check Inst[12:11] == 0x0
2434 OPC_Decode, 237, 4, 0, // 4753: decode to BDNZLRLm using decoder 0
2435 // 4753: }
2436 160, 6, 8, // 4757: case 0x320: {
2437 OPC_CheckField, 11, 2, 0, // 4760: check Inst[12:11] == 0x0
2438 OPC_Decode, 238, 4, 0, // 4764: decode to BDNZLRLp using decoder 0
2439 // 4764: }
2440 192, 6, 8, // 4768: case 0x340: {
2441 OPC_CheckField, 11, 2, 0, // 4771: check Inst[12:11] == 0x0
2442 OPC_Decode, 129, 5, 0, // 4775: decode to BDZLRLm using decoder 0
2443 // 4775: }
2444 224, 6, 0, // 4779: case 0x360: {
2445 OPC_CheckField, 11, 2, 0, // 4782: check Inst[12:11] == 0x0
2446 OPC_Decode, 130, 5, 0, // 4786: decode to BDZLRLp using decoder 0
2447 // 4786: }
2448 // 4786: } // switch Inst[25:16]
2449 // 4786: } else try {
2450 OPC_Decode, 180, 23, 54, // 4790: decode to gBCLRL using decoder 54
2451 // 4790: }
2452 // 4790: }
2453 16, 0, // 4794: case 0x10: {
2454 OPC_CheckField, 13, 3, 0, // 4796: check Inst[15:13] == 0x0
2455 OPC_Scope, 13, // 4800: try {
2456 OPC_CheckField, 11, 2, 0, // 4802: check Inst[12:11] == 0x0
2457 OPC_CheckField, 16, 10, 128, 5, // 4806: check Inst[25:16] == 0x280
2458 OPC_Decode, 216, 4, 0, // 4811: decode to BCTRL using decoder 0
2459 // 4811: } else try {
2460 OPC_Decode, 175, 23, 54, // 4815: decode to gBCCTRL using decoder 54
2461 // 4815: }
2462 // 4815: }
2463 // 4815: } // switch Inst[10:6]
2464 // 4815: }
2465 // 4815: } // switch Inst[0]
2466 // 4815: }
2467 18, 87, // 4819: case 0x12: {
2468 OPC_SwitchField, 6, 5, // 4821: switch Inst[10:6] {
2469 0, 12, // 4824: case 0x0: {
2470 OPC_CheckField, 11, 15, 0, // 4826: check Inst[25:11] == 0x0
2471 OPC_CheckField, 0, 1, 0, // 4830: check Inst[0] == 0x0
2472 OPC_Decode, 213, 14, 0, // 4834: decode to RFID using decoder 0
2473 // 4834: }
2474 1, 12, // 4838: case 0x1: {
2475 OPC_CheckField, 11, 15, 0, // 4840: check Inst[25:11] == 0x0
2476 OPC_CheckField, 0, 1, 0, // 4844: check Inst[0] == 0x0
2477 OPC_Decode, 212, 14, 0, // 4848: decode to RFI using decoder 0
2478 // 4848: }
2479 4, 12, // 4852: case 0x4: {
2480 OPC_CheckField, 12, 14, 0, // 4854: check Inst[25:12] == 0x0
2481 OPC_CheckField, 0, 1, 0, // 4858: check Inst[0] == 0x0
2482 OPC_Decode, 211, 14, 55, // 4862: decode to RFEBB using decoder 55
2483 // 4862: }
2484 8, 12, // 4866: case 0x8: {
2485 OPC_CheckField, 11, 15, 0, // 4868: check Inst[25:11] == 0x0
2486 OPC_CheckField, 0, 1, 0, // 4872: check Inst[0] == 0x0
2487 OPC_Decode, 173, 10, 0, // 4876: decode to HRFID using decoder 0
2488 // 4876: }
2489 11, 12, // 4880: case 0xb: {
2490 OPC_CheckField, 11, 15, 0, // 4882: check Inst[25:11] == 0x0
2491 OPC_CheckField, 0, 1, 0, // 4886: check Inst[0] == 0x0
2492 OPC_Decode, 253, 15, 0, // 4890: decode to STOP using decoder 0
2493 // 4890: }
2494 13, 0, // 4894: case 0xd: {
2495 OPC_CheckField, 11, 15, 0, // 4896: check Inst[25:11] == 0x0
2496 OPC_CheckField, 0, 1, 0, // 4900: check Inst[0] == 0x0
2497 OPC_Decode, 205, 12, 0, // 4904: decode to NAP using decoder 0
2498 // 4904: }
2499 // 4904: } // switch Inst[10:6]
2500 // 4904: }
2501 19, 12, // 4908: case 0x13: {
2502 OPC_CheckField, 6, 20, 1, // 4910: check Inst[25:6] == 0x1
2503 OPC_CheckField, 0, 1, 0, // 4914: check Inst[0] == 0x0
2504 OPC_Decode, 209, 14, 0, // 4918: decode to RFCI using decoder 0
2505 // 4918: }
2506 22, 0, // 4922: case 0x16: {
2507 OPC_CheckField, 6, 20, 4, // 4924: check Inst[25:6] == 0x4
2508 OPC_CheckField, 0, 1, 0, // 4928: check Inst[0] == 0x0
2509 OPC_Decode, 183, 10, 0, // 4932: decode to ISYNC using decoder 0
2510 // 4932: }
2511 // 4932: } // switch Inst[5:1]
2512 // 4932: }
2513 20, 15, // 4936: case 0x14: {
2514 OPC_SwitchField, 0, 1, // 4938: switch Inst[0] {
2515 0, 4, // 4941: case 0x0: {
2516 OPC_Decode, 231, 14, 56, // 4943: decode to RLWIMI using decoder 56
2517 // 4943: }
2518 1, 0, // 4947: case 0x1: {
2519 OPC_Decode, 234, 14, 56, // 4949: decode to RLWIMI_rec using decoder 56
2520 // 4949: }
2521 // 4949: } // switch Inst[0]
2522 // 4949: }
2523 21, 15, // 4953: case 0x15: {
2524 OPC_SwitchField, 0, 1, // 4955: switch Inst[0] {
2525 0, 4, // 4958: case 0x0: {
2526 OPC_Decode, 235, 14, 57, // 4960: decode to RLWINM using decoder 57
2527 // 4960: }
2528 1, 0, // 4964: case 0x1: {
2529 OPC_Decode, 238, 14, 57, // 4966: decode to RLWINM_rec using decoder 57
2530 // 4966: }
2531 // 4966: } // switch Inst[0]
2532 // 4966: }
2533 23, 15, // 4970: case 0x17: {
2534 OPC_SwitchField, 0, 1, // 4972: switch Inst[0] {
2535 0, 4, // 4975: case 0x0: {
2536 OPC_Decode, 239, 14, 58, // 4977: decode to RLWNM using decoder 58
2537 // 4977: }
2538 1, 0, // 4981: case 0x1: {
2539 OPC_Decode, 242, 14, 58, // 4983: decode to RLWNM_rec using decoder 58
2540 // 4983: }
2541 // 4983: } // switch Inst[0]
2542 // 4983: }
2543 24, 14, // 4987: case 0x18: {
2544 OPC_Scope, 8, // 4989: try {
2545 OPC_CheckField, 0, 26, 0, // 4991: check Inst[25:0] == 0x0
2546 OPC_Decode, 214, 12, 0, // 4995: decode to NOP using decoder 0
2547 // 4995: } else try {
2548 OPC_Decode, 228, 12, 59, // 4999: decode to ORI using decoder 59
2549 // 4999: }
2550 // 4999: }
2551 25, 4, // 5003: case 0x19: {
2552 OPC_Decode, 230, 12, 59, // 5005: decode to ORIS using decoder 59
2553 // 5005: }
2554 26, 4, // 5009: case 0x1a: {
2555 OPC_Decode, 180, 20, 59, // 5011: decode to XORI using decoder 59
2556 // 5011: }
2557 27, 4, // 5015: case 0x1b: {
2558 OPC_Decode, 182, 20, 59, // 5017: decode to XORIS using decoder 59
2559 // 5017: }
2560 28, 4, // 5021: case 0x1c: {
2561 OPC_Decode, 244, 3, 59, // 5023: decode to ANDI_rec using decoder 59
2562 // 5023: }
2563 29, 4, // 5027: case 0x1d: {
2564 OPC_Decode, 243, 3, 59, // 5029: decode to ANDIS_rec using decoder 59
2565 // 5029: }
2566 30, 100, // 5033: case 0x1e: {
2567 OPC_SwitchField, 2, 3, // 5035: switch Inst[4:2] {
2568 0, 15, // 5038: case 0x0: {
2569 OPC_SwitchField, 0, 1, // 5040: switch Inst[0] {
2570 0, 4, // 5043: case 0x0: {
2571 OPC_Decode, 220, 14, 60, // 5045: decode to RLDICL using decoder 60
2572 // 5045: }
2573 1, 0, // 5049: case 0x1: {
2574 OPC_Decode, 224, 14, 60, // 5051: decode to RLDICL_rec using decoder 60
2575 // 5051: }
2576 // 5051: } // switch Inst[0]
2577 // 5051: }
2578 1, 15, // 5055: case 0x1: {
2579 OPC_SwitchField, 0, 1, // 5057: switch Inst[0] {
2580 0, 4, // 5060: case 0x0: {
2581 OPC_Decode, 225, 14, 60, // 5062: decode to RLDICR using decoder 60
2582 // 5062: }
2583 1, 0, // 5066: case 0x1: {
2584 OPC_Decode, 227, 14, 60, // 5068: decode to RLDICR_rec using decoder 60
2585 // 5068: }
2586 // 5068: } // switch Inst[0]
2587 // 5068: }
2588 2, 15, // 5072: case 0x2: {
2589 OPC_SwitchField, 0, 1, // 5074: switch Inst[0] {
2590 0, 4, // 5077: case 0x0: {
2591 OPC_Decode, 219, 14, 60, // 5079: decode to RLDIC using decoder 60
2592 // 5079: }
2593 1, 0, // 5083: case 0x1: {
2594 OPC_Decode, 228, 14, 60, // 5085: decode to RLDIC_rec using decoder 60
2595 // 5085: }
2596 // 5085: } // switch Inst[0]
2597 // 5085: }
2598 3, 15, // 5089: case 0x3: {
2599 OPC_SwitchField, 0, 1, // 5091: switch Inst[0] {
2600 0, 4, // 5094: case 0x0: {
2601 OPC_Decode, 229, 14, 61, // 5096: decode to RLDIMI using decoder 61
2602 // 5096: }
2603 1, 0, // 5100: case 0x1: {
2604 OPC_Decode, 230, 14, 61, // 5102: decode to RLDIMI_rec using decoder 61
2605 // 5102: }
2606 // 5102: } // switch Inst[0]
2607 // 5102: }
2608 4, 0, // 5106: case 0x4: {
2609 OPC_SwitchField, 0, 2, // 5108: switch Inst[1:0] {
2610 0, 4, // 5111: case 0x0: {
2611 OPC_Decode, 215, 14, 62, // 5113: decode to RLDCL using decoder 62
2612 // 5113: }
2613 1, 4, // 5117: case 0x1: {
2614 OPC_Decode, 216, 14, 62, // 5119: decode to RLDCL_rec using decoder 62
2615 // 5119: }
2616 2, 4, // 5123: case 0x2: {
2617 OPC_Decode, 217, 14, 62, // 5125: decode to RLDCR using decoder 62
2618 // 5125: }
2619 3, 0, // 5129: case 0x3: {
2620 OPC_Decode, 218, 14, 62, // 5131: decode to RLDCR_rec using decoder 62
2621 // 5131: }
2622 // 5131: } // switch Inst[1:0]
2623 // 5131: }
2624 // 5131: } // switch Inst[4:2]
2625 // 5131: }
2626 31, 219, 36, // 5135: case 0x1f: {
2627 OPC_SwitchField, 2, 4, // 5138: switch Inst[5:2] {
2628 0, 165, 1, // 5141: case 0x0: {
2629 OPC_SwitchField, 6, 5, // 5144: switch Inst[10:6] {
2630 0, 23, // 5147: case 0x0: {
2631 OPC_SwitchField, 21, 2, // 5149: switch Inst[22:21] {
2632 0, 8, // 5152: case 0x0: {
2633 OPC_CheckField, 0, 2, 0, // 5154: check Inst[1:0] == 0x0
2634 OPC_Decode, 185, 5, 63, // 5158: decode to CMPW using decoder 63
2635 // 5158: }
2636 1, 0, // 5162: case 0x1: {
2637 OPC_CheckField, 0, 2, 0, // 5164: check Inst[1:0] == 0x0
2638 OPC_Decode, 176, 5, 64, // 5168: decode to CMPD using decoder 64
2639 // 5168: }
2640 // 5168: } // switch Inst[22:21]
2641 // 5168: }
2642 1, 23, // 5172: case 0x1: {
2643 OPC_SwitchField, 21, 2, // 5174: switch Inst[22:21] {
2644 0, 8, // 5177: case 0x0: {
2645 OPC_CheckField, 0, 2, 0, // 5179: check Inst[1:0] == 0x0
2646 OPC_Decode, 181, 5, 63, // 5183: decode to CMPLW using decoder 63
2647 // 5183: }
2648 1, 0, // 5187: case 0x1: {
2649 OPC_CheckField, 0, 2, 0, // 5189: check Inst[1:0] == 0x0
2650 OPC_Decode, 179, 5, 64, // 5193: decode to CMPLD using decoder 64
2651 // 5193: }
2652 // 5193: } // switch Inst[22:21]
2653 // 5193: }
2654 4, 12, // 5197: case 0x4: {
2655 OPC_CheckField, 11, 7, 0, // 5199: check Inst[17:11] == 0x0
2656 OPC_CheckField, 0, 2, 0, // 5203: check Inst[1:0] == 0x0
2657 OPC_Decode, 140, 15, 65, // 5207: decode to SETB using decoder 65
2658 // 5207: }
2659 6, 12, // 5211: case 0x6: {
2660 OPC_CheckField, 22, 1, 0, // 5213: check Inst[22] == 0x0
2661 OPC_CheckField, 0, 2, 0, // 5217: check Inst[1:0] == 0x0
2662 OPC_Decode, 183, 5, 66, // 5221: decode to CMPRB using decoder 66
2663 // 5221: }
2664 7, 12, // 5225: case 0x7: {
2665 OPC_CheckField, 21, 2, 0, // 5227: check Inst[22:21] == 0x0
2666 OPC_CheckField, 0, 2, 0, // 5231: check Inst[1:0] == 0x0
2667 OPC_Decode, 178, 5, 64, // 5235: decode to CMPEQB using decoder 64
2668 // 5235: }
2669 12, 12, // 5239: case 0xc: {
2670 OPC_CheckField, 11, 5, 0, // 5241: check Inst[15:11] == 0x0
2671 OPC_CheckField, 0, 2, 0, // 5245: check Inst[1:0] == 0x0
2672 OPC_Decode, 142, 15, 67, // 5249: decode to SETBC using decoder 67
2673 // 5249: }
2674 13, 12, // 5253: case 0xd: {
2675 OPC_CheckField, 11, 5, 0, // 5255: check Inst[15:11] == 0x0
2676 OPC_CheckField, 0, 2, 0, // 5259: check Inst[1:0] == 0x0
2677 OPC_Decode, 144, 15, 67, // 5263: decode to SETBCR using decoder 67
2678 // 5263: }
2679 14, 12, // 5267: case 0xe: {
2680 OPC_CheckField, 11, 5, 0, // 5269: check Inst[15:11] == 0x0
2681 OPC_CheckField, 0, 2, 0, // 5273: check Inst[1:0] == 0x0
2682 OPC_Decode, 147, 15, 67, // 5277: decode to SETNBC using decoder 67
2683 // 5277: }
2684 15, 12, // 5281: case 0xf: {
2685 OPC_CheckField, 11, 5, 0, // 5283: check Inst[15:11] == 0x0
2686 OPC_CheckField, 0, 2, 0, // 5287: check Inst[1:0] == 0x0
2687 OPC_Decode, 149, 15, 67, // 5291: decode to SETNBCR using decoder 67
2688 // 5291: }
2689 18, 0, // 5295: case 0x12: {
2690 OPC_CheckField, 11, 12, 0, // 5297: check Inst[22:11] == 0x0
2691 OPC_CheckField, 0, 2, 0, // 5301: check Inst[1:0] == 0x0
2692 OPC_Decode, 220, 11, 68, // 5305: decode to MCRXRX using decoder 68
2693 // 5305: }
2694 // 5305: } // switch Inst[10:6]
2695 // 5305: }
2696 1, 47, // 5309: case 0x1: {
2697 OPC_SwitchField, 6, 5, // 5311: switch Inst[10:6] {
2698 4, 12, // 5314: case 0x4: {
2699 OPC_CheckField, 16, 1, 0, // 5316: check Inst[16] == 0x0
2700 OPC_CheckField, 1, 1, 1, // 5320: check Inst[1] == 0x1
2701 OPC_Decode, 175, 20, 69, // 5324: decode to WRTEE using decoder 69
2702 // 5324: }
2703 5, 8, // 5328: case 0x5: {
2704 OPC_CheckField, 1, 1, 1, // 5330: check Inst[1] == 0x1
2705 OPC_Decode, 176, 20, 70, // 5334: decode to WRTEEI using decoder 70
2706 // 5334: }
2707 10, 8, // 5338: case 0xa: {
2708 OPC_CheckField, 0, 2, 2, // 5340: check Inst[1:0] == 0x2
2709 OPC_Decode, 226, 11, 71, // 5344: decode to MFDCR using decoder 71
2710 // 5344: }
2711 14, 0, // 5348: case 0xe: {
2712 OPC_CheckField, 0, 2, 2, // 5350: check Inst[1:0] == 0x2
2713 OPC_Decode, 140, 12, 71, // 5354: decode to MTDCR using decoder 71
2714 // 5354: }
2715 // 5354: } // switch Inst[10:6]
2716 // 5354: }
2717 2, 35, // 5358: case 0x2: {
2718 OPC_SwitchField, 6, 5, // 5360: switch Inst[10:6] {
2719 0, 20, // 5363: case 0x0: {
2720 OPC_CheckField, 0, 2, 0, // 5365: check Inst[1:0] == 0x0
2721 OPC_Scope, 10, // 5369: try {
2722 OPC_CheckField, 11, 15, 128, 248, 1, // 5371: check Inst[25:11] == 0x7c00
2723 OPC_Decode, 146, 17, 0, // 5377: decode to TRAP using decoder 0
2724 // 5377: } else try {
2725 OPC_Decode, 150, 17, 72, // 5381: decode to TW using decoder 72
2726 // 5381: }
2727 // 5381: }
2728 2, 0, // 5385: case 0x2: {
2729 OPC_CheckField, 0, 2, 0, // 5387: check Inst[1:0] == 0x0
2730 OPC_Decode, 246, 16, 73, // 5391: decode to TD using decoder 73
2731 // 5391: }
2732 // 5391: } // switch Inst[10:6]
2733 // 5391: }
2734 3, 132, 2, // 5395: case 0x3: {
2735 OPC_SwitchField, 6, 5, // 5398: switch Inst[10:6] {
2736 0, 15, // 5401: case 0x0: {
2737 OPC_SwitchField, 0, 2, // 5403: switch Inst[1:0] {
2738 0, 4, // 5406: case 0x0: {
2739 OPC_Decode, 149, 11, 74, // 5408: decode to LVSL using decoder 74
2740 // 5408: }
2741 2, 0, // 5412: case 0x2: {
2742 OPC_Decode, 146, 11, 74, // 5414: decode to LVEBX using decoder 74
2743 // 5414: }
2744 // 5414: } // switch Inst[1:0]
2745 // 5414: }
2746 1, 15, // 5418: case 0x1: {
2747 OPC_SwitchField, 0, 2, // 5420: switch Inst[1:0] {
2748 0, 4, // 5423: case 0x0: {
2749 OPC_Decode, 150, 11, 74, // 5425: decode to LVSR using decoder 74
2750 // 5425: }
2751 2, 0, // 5429: case 0x2: {
2752 OPC_Decode, 147, 11, 74, // 5431: decode to LVEHX using decoder 74
2753 // 5431: }
2754 // 5431: } // switch Inst[1:0]
2755 // 5431: }
2756 2, 8, // 5435: case 0x2: {
2757 OPC_CheckField, 0, 2, 2, // 5437: check Inst[1:0] == 0x2
2758 OPC_Decode, 148, 11, 74, // 5441: decode to LVEWX using decoder 74
2759 // 5441: }
2760 3, 8, // 5445: case 0x3: {
2761 OPC_CheckField, 0, 2, 2, // 5447: check Inst[1:0] == 0x2
2762 OPC_Decode, 151, 11, 74, // 5451: decode to LVX using decoder 74
2763 // 5451: }
2764 4, 8, // 5455: case 0x4: {
2765 OPC_CheckField, 0, 2, 2, // 5457: check Inst[1:0] == 0x2
2766 OPC_Decode, 130, 16, 74, // 5461: decode to STVEBX using decoder 74
2767 // 5461: }
2768 5, 8, // 5465: case 0x5: {
2769 OPC_CheckField, 0, 2, 2, // 5467: check Inst[1:0] == 0x2
2770 OPC_Decode, 131, 16, 74, // 5471: decode to STVEHX using decoder 74
2771 // 5471: }
2772 6, 19, // 5475: case 0x6: {
2773 OPC_SwitchField, 0, 2, // 5477: switch Inst[1:0] {
2774 0, 8, // 5480: case 0x0: {
2775 OPC_CheckField, 25, 1, 0, // 5482: check Inst[25] == 0x0
2776 OPC_Decode, 177, 10, 75, // 5486: decode to ICBLQ using decoder 75
2777 // 5486: }
2778 2, 0, // 5490: case 0x2: {
2779 OPC_Decode, 132, 16, 74, // 5492: decode to STVEWX using decoder 74
2780 // 5492: }
2781 // 5492: } // switch Inst[1:0]
2782 // 5492: }
2783 7, 19, // 5496: case 0x7: {
2784 OPC_SwitchField, 0, 2, // 5498: switch Inst[1:0] {
2785 0, 8, // 5501: case 0x0: {
2786 OPC_CheckField, 25, 1, 0, // 5503: check Inst[25] == 0x0
2787 OPC_Decode, 176, 10, 75, // 5507: decode to ICBLC using decoder 75
2788 // 5507: }
2789 2, 0, // 5511: case 0x2: {
2790 OPC_Decode, 133, 16, 74, // 5513: decode to STVX using decoder 74
2791 // 5513: }
2792 // 5513: } // switch Inst[1:0]
2793 // 5513: }
2794 11, 8, // 5517: case 0xb: {
2795 OPC_CheckField, 0, 2, 2, // 5519: check Inst[1:0] == 0x2
2796 OPC_Decode, 152, 11, 74, // 5523: decode to LVXL using decoder 74
2797 // 5523: }
2798 14, 12, // 5527: case 0xe: {
2799 OPC_CheckField, 21, 5, 0, // 5529: check Inst[25:21] == 0x0
2800 OPC_CheckField, 0, 2, 0, // 5533: check Inst[1:0] == 0x0
2801 OPC_Decode, 239, 5, 76, // 5537: decode to DCCCI using decoder 76
2802 // 5537: }
2803 15, 19, // 5541: case 0xf: {
2804 OPC_SwitchField, 0, 2, // 5543: switch Inst[1:0] {
2805 0, 8, // 5546: case 0x0: {
2806 OPC_CheckField, 25, 1, 0, // 5548: check Inst[25] == 0x0
2807 OPC_Decode, 179, 10, 75, // 5552: decode to ICBTLS using decoder 75
2808 // 5552: }
2809 2, 0, // 5556: case 0x2: {
2810 OPC_Decode, 134, 16, 74, // 5558: decode to STVXL using decoder 74
2811 // 5558: }
2812 // 5558: } // switch Inst[1:0]
2813 // 5558: }
2814 18, 8, // 5562: case 0x12: {
2815 OPC_CheckField, 0, 2, 0, // 5564: check Inst[1:0] == 0x0
2816 OPC_Decode, 156, 11, 77, // 5568: decode to LWAT using decoder 77
2817 // 5568: }
2818 19, 8, // 5572: case 0x13: {
2819 OPC_CheckField, 0, 2, 0, // 5574: check Inst[1:0] == 0x0
2820 OPC_Decode, 204, 10, 77, // 5578: decode to LDAT using decoder 77
2821 // 5578: }
2822 22, 8, // 5582: case 0x16: {
2823 OPC_CheckField, 0, 2, 0, // 5584: check Inst[1:0] == 0x0
2824 OPC_Decode, 137, 16, 78, // 5588: decode to STWAT using decoder 78
2825 // 5588: }
2826 23, 8, // 5592: case 0x17: {
2827 OPC_CheckField, 0, 2, 0, // 5594: check Inst[1:0] == 0x0
2828 OPC_Decode, 214, 15, 79, // 5598: decode to STDAT using decoder 79
2829 // 5598: }
2830 24, 12, // 5602: case 0x18: {
2831 OPC_CheckField, 21, 5, 1, // 5604: check Inst[25:21] == 0x1
2832 OPC_CheckField, 0, 2, 0, // 5608: check Inst[1:0] == 0x0
2833 OPC_Decode, 202, 5, 76, // 5612: decode to CP_COPY using decoder 76
2834 // 5612: }
2835 26, 12, // 5616: case 0x1a: {
2836 OPC_CheckField, 11, 15, 0, // 5618: check Inst[25:11] == 0x0
2837 OPC_CheckField, 0, 2, 0, // 5622: check Inst[1:0] == 0x0
2838 OPC_Decode, 201, 5, 0, // 5626: decode to CP_ABORT using decoder 0
2839 // 5626: }
2840 28, 12, // 5630: case 0x1c: {
2841 OPC_CheckField, 22, 4, 0, // 5632: check Inst[25:22] == 0x0
2842 OPC_CheckField, 0, 2, 1, // 5636: check Inst[1:0] == 0x1
2843 OPC_Decode, 205, 5, 80, // 5640: decode to CP_PASTE_rec using decoder 80
2844 // 5640: }
2845 30, 0, // 5644: case 0x1e: {
2846 OPC_CheckField, 21, 5, 0, // 5646: check Inst[25:21] == 0x0
2847 OPC_CheckField, 0, 2, 0, // 5650: check Inst[1:0] == 0x0
2848 OPC_Decode, 180, 10, 76, // 5654: decode to ICCCI using decoder 76
2849 // 5654: }
2850 // 5654: } // switch Inst[10:6]
2851 // 5654: }
2852 4, 253, 3, // 5658: case 0x4: {
2853 OPC_SwitchField, 6, 4, // 5661: switch Inst[9:6] {
2854 0, 57, // 5664: case 0x0: {
2855 OPC_SwitchField, 0, 2, // 5666: switch Inst[1:0] {
2856 0, 15, // 5669: case 0x0: {
2857 OPC_SwitchField, 10, 1, // 5671: switch Inst[10] {
2858 0, 4, // 5674: case 0x0: {
2859 OPC_Decode, 184, 16, 81, // 5676: decode to SUBFC using decoder 81
2860 // 5676: }
2861 1, 0, // 5680: case 0x1: {
2862 OPC_Decode, 189, 16, 81, // 5682: decode to SUBFCO using decoder 81
2863 // 5682: }
2864 // 5682: } // switch Inst[10]
2865 // 5682: }
2866 1, 15, // 5686: case 0x1: {
2867 OPC_SwitchField, 10, 1, // 5688: switch Inst[10] {
2868 0, 4, // 5691: case 0x0: {
2869 OPC_Decode, 191, 16, 81, // 5693: decode to SUBFC_rec using decoder 81
2870 // 5693: }
2871 1, 0, // 5697: case 0x1: {
2872 OPC_Decode, 190, 16, 81, // 5699: decode to SUBFCO_rec using decoder 81
2873 // 5699: }
2874 // 5699: } // switch Inst[10]
2875 // 5699: }
2876 2, 8, // 5703: case 0x2: {
2877 OPC_CheckField, 10, 1, 0, // 5705: check Inst[10] == 0x0
2878 OPC_Decode, 181, 12, 82, // 5709: decode to MULHDU using decoder 82
2879 // 5709: }
2880 3, 0, // 5713: case 0x3: {
2881 OPC_CheckField, 10, 1, 0, // 5715: check Inst[10] == 0x0
2882 OPC_Decode, 182, 12, 82, // 5719: decode to MULHDU_rec using decoder 82
2883 // 5719: }
2884 // 5719: } // switch Inst[1:0]
2885 // 5719: }
2886 1, 37, // 5723: case 0x1: {
2887 OPC_SwitchField, 0, 2, // 5725: switch Inst[1:0] {
2888 0, 15, // 5728: case 0x0: {
2889 OPC_SwitchField, 10, 1, // 5730: switch Inst[10] {
2890 0, 4, // 5733: case 0x0: {
2891 OPC_Decode, 179, 16, 81, // 5735: decode to SUBF using decoder 81
2892 // 5735: }
2893 1, 0, // 5739: case 0x1: {
2894 OPC_Decode, 210, 16, 81, // 5741: decode to SUBFO using decoder 81
2895 // 5741: }
2896 // 5741: } // switch Inst[10]
2897 // 5741: }
2898 1, 0, // 5745: case 0x1: {
2899 OPC_SwitchField, 10, 1, // 5747: switch Inst[10] {
2900 0, 4, // 5750: case 0x0: {
2901 OPC_Decode, 222, 16, 81, // 5752: decode to SUBF_rec using decoder 81
2902 // 5752: }
2903 1, 0, // 5756: case 0x1: {
2904 OPC_Decode, 211, 16, 81, // 5758: decode to SUBFO_rec using decoder 81
2905 // 5758: }
2906 // 5758: } // switch Inst[10]
2907 // 5758: }
2908 // 5758: } // switch Inst[1:0]
2909 // 5758: }
2910 2, 35, // 5762: case 0x2: {
2911 OPC_SwitchField, 0, 2, // 5764: switch Inst[1:0] {
2912 0, 4, // 5767: case 0x0: {
2913 OPC_Decode, 212, 16, 83, // 5769: decode to SUBFUS using decoder 83
2914 // 5769: }
2915 1, 4, // 5773: case 0x1: {
2916 OPC_Decode, 213, 16, 83, // 5775: decode to SUBFUS_rec using decoder 83
2917 // 5775: }
2918 2, 8, // 5779: case 0x2: {
2919 OPC_CheckField, 10, 1, 0, // 5781: check Inst[10] == 0x0
2920 OPC_Decode, 180, 12, 82, // 5785: decode to MULHD using decoder 82
2921 // 5785: }
2922 3, 0, // 5789: case 0x3: {
2923 OPC_CheckField, 10, 1, 0, // 5791: check Inst[10] == 0x0
2924 OPC_Decode, 183, 12, 82, // 5795: decode to MULHD_rec using decoder 82
2925 // 5795: }
2926 // 5795: } // switch Inst[1:0]
2927 // 5795: }
2928 3, 37, // 5799: case 0x3: {
2929 OPC_SwitchField, 0, 2, // 5801: switch Inst[1:0] {
2930 0, 15, // 5804: case 0x0: {
2931 OPC_SwitchField, 10, 6, // 5806: switch Inst[15:10] {
2932 0, 4, // 5809: case 0x0: {
2933 OPC_Decode, 206, 12, 84, // 5811: decode to NEG using decoder 84
2934 // 5811: }
2935 1, 0, // 5815: case 0x1: {
2936 OPC_Decode, 211, 12, 84, // 5817: decode to NEGO using decoder 84
2937 // 5817: }
2938 // 5817: } // switch Inst[15:10]
2939 // 5817: }
2940 1, 0, // 5821: case 0x1: {
2941 OPC_SwitchField, 10, 6, // 5823: switch Inst[15:10] {
2942 0, 4, // 5826: case 0x0: {
2943 OPC_Decode, 213, 12, 84, // 5828: decode to NEG_rec using decoder 84
2944 // 5828: }
2945 1, 0, // 5832: case 0x1: {
2946 OPC_Decode, 212, 12, 84, // 5834: decode to NEGO_rec using decoder 84
2947 // 5834: }
2948 // 5834: } // switch Inst[15:10]
2949 // 5834: }
2950 // 5834: } // switch Inst[1:0]
2951 // 5834: }
2952 4, 37, // 5838: case 0x4: {
2953 OPC_SwitchField, 0, 2, // 5840: switch Inst[1:0] {
2954 0, 15, // 5843: case 0x0: {
2955 OPC_SwitchField, 10, 1, // 5845: switch Inst[10] {
2956 0, 4, // 5848: case 0x0: {
2957 OPC_Decode, 192, 16, 81, // 5850: decode to SUBFE using decoder 81
2958 // 5850: }
2959 1, 0, // 5854: case 0x1: {
2960 OPC_Decode, 197, 16, 81, // 5856: decode to SUBFEO using decoder 81
2961 // 5856: }
2962 // 5856: } // switch Inst[10]
2963 // 5856: }
2964 1, 0, // 5860: case 0x1: {
2965 OPC_SwitchField, 10, 1, // 5862: switch Inst[10] {
2966 0, 4, // 5865: case 0x0: {
2967 OPC_Decode, 199, 16, 81, // 5867: decode to SUBFE_rec using decoder 81
2968 // 5867: }
2969 1, 0, // 5871: case 0x1: {
2970 OPC_Decode, 198, 16, 81, // 5873: decode to SUBFEO_rec using decoder 81
2971 // 5873: }
2972 // 5873: } // switch Inst[10]
2973 // 5873: }
2974 // 5873: } // switch Inst[1:0]
2975 // 5873: }
2976 6, 37, // 5877: case 0x6: {
2977 OPC_SwitchField, 0, 2, // 5879: switch Inst[1:0] {
2978 0, 15, // 5882: case 0x0: {
2979 OPC_SwitchField, 10, 6, // 5884: switch Inst[15:10] {
2980 0, 4, // 5887: case 0x0: {
2981 OPC_Decode, 214, 16, 84, // 5889: decode to SUBFZE using decoder 84
2982 // 5889: }
2983 1, 0, // 5893: case 0x1: {
2984 OPC_Decode, 219, 16, 84, // 5895: decode to SUBFZEO using decoder 84
2985 // 5895: }
2986 // 5895: } // switch Inst[15:10]
2987 // 5895: }
2988 1, 0, // 5899: case 0x1: {
2989 OPC_SwitchField, 10, 6, // 5901: switch Inst[15:10] {
2990 0, 4, // 5904: case 0x0: {
2991 OPC_Decode, 221, 16, 84, // 5906: decode to SUBFZE_rec using decoder 84
2992 // 5906: }
2993 1, 0, // 5910: case 0x1: {
2994 OPC_Decode, 220, 16, 84, // 5912: decode to SUBFZEO_rec using decoder 84
2995 // 5912: }
2996 // 5912: } // switch Inst[15:10]
2997 // 5912: }
2998 // 5912: } // switch Inst[1:0]
2999 // 5912: }
3000 7, 71, // 5916: case 0x7: {
3001 OPC_SwitchField, 0, 2, // 5918: switch Inst[1:0] {
3002 0, 15, // 5921: case 0x0: {
3003 OPC_SwitchField, 10, 6, // 5923: switch Inst[15:10] {
3004 0, 4, // 5926: case 0x0: {
3005 OPC_Decode, 202, 16, 84, // 5928: decode to SUBFME using decoder 84
3006 // 5928: }
3007 1, 0, // 5932: case 0x1: {
3008 OPC_Decode, 207, 16, 84, // 5934: decode to SUBFMEO using decoder 84
3009 // 5934: }
3010 // 5934: } // switch Inst[15:10]
3011 // 5934: }
3012 1, 15, // 5938: case 0x1: {
3013 OPC_SwitchField, 10, 6, // 5940: switch Inst[15:10] {
3014 0, 4, // 5943: case 0x0: {
3015 OPC_Decode, 209, 16, 84, // 5945: decode to SUBFME_rec using decoder 84
3016 // 5945: }
3017 1, 0, // 5949: case 0x1: {
3018 OPC_Decode, 208, 16, 84, // 5951: decode to SUBFMEO_rec using decoder 84
3019 // 5951: }
3020 // 5951: } // switch Inst[15:10]
3021 // 5951: }
3022 2, 15, // 5955: case 0x2: {
3023 OPC_SwitchField, 10, 1, // 5957: switch Inst[10] {
3024 0, 4, // 5960: case 0x0: {
3025 OPC_Decode, 188, 12, 82, // 5962: decode to MULLD using decoder 82
3026 // 5962: }
3027 1, 0, // 5966: case 0x1: {
3028 OPC_Decode, 189, 12, 82, // 5968: decode to MULLDO using decoder 82
3029 // 5968: }
3030 // 5968: } // switch Inst[10]
3031 // 5968: }
3032 3, 0, // 5972: case 0x3: {
3033 OPC_SwitchField, 10, 1, // 5974: switch Inst[10] {
3034 0, 4, // 5977: case 0x0: {
3035 OPC_Decode, 191, 12, 82, // 5979: decode to MULLD_rec using decoder 82
3036 // 5979: }
3037 1, 0, // 5983: case 0x1: {
3038 OPC_Decode, 190, 12, 82, // 5985: decode to MULLDO_rec using decoder 82
3039 // 5985: }
3040 // 5985: } // switch Inst[10]
3041 // 5985: }
3042 // 5985: } // switch Inst[1:0]
3043 // 5985: }
3044 8, 23, // 5989: case 0x8: {
3045 OPC_SwitchField, 10, 1, // 5991: switch Inst[10] {
3046 0, 8, // 5994: case 0x0: {
3047 OPC_CheckField, 0, 2, 2, // 5996: check Inst[1:0] == 0x2
3048 OPC_Decode, 130, 12, 82, // 6000: decode to MODUD using decoder 82
3049 // 6000: }
3050 1, 0, // 6004: case 0x1: {
3051 OPC_CheckField, 0, 2, 2, // 6006: check Inst[1:0] == 0x2
3052 OPC_Decode, 128, 12, 82, // 6010: decode to MODSD using decoder 82
3053 // 6010: }
3054 // 6010: } // switch Inst[10]
3055 // 6010: }
3056 12, 37, // 6014: case 0xc: {
3057 OPC_SwitchField, 0, 2, // 6016: switch Inst[1:0] {
3058 2, 15, // 6019: case 0x2: {
3059 OPC_SwitchField, 10, 1, // 6021: switch Inst[10] {
3060 0, 4, // 6024: case 0x0: {
3061 OPC_Decode, 150, 6, 82, // 6026: decode to DIVDEU using decoder 82
3062 // 6026: }
3063 1, 0, // 6030: case 0x1: {
3064 OPC_Decode, 151, 6, 82, // 6032: decode to DIVDEUO using decoder 82
3065 // 6032: }
3066 // 6032: } // switch Inst[10]
3067 // 6032: }
3068 3, 0, // 6036: case 0x3: {
3069 OPC_SwitchField, 10, 1, // 6038: switch Inst[10] {
3070 0, 4, // 6041: case 0x0: {
3071 OPC_Decode, 153, 6, 82, // 6043: decode to DIVDEU_rec using decoder 82
3072 // 6043: }
3073 1, 0, // 6047: case 0x1: {
3074 OPC_Decode, 152, 6, 82, // 6049: decode to DIVDEUO_rec using decoder 82
3075 // 6049: }
3076 // 6049: } // switch Inst[10]
3077 // 6049: }
3078 // 6049: } // switch Inst[1:0]
3079 // 6049: }
3080 13, 37, // 6053: case 0xd: {
3081 OPC_SwitchField, 0, 2, // 6055: switch Inst[1:0] {
3082 2, 15, // 6058: case 0x2: {
3083 OPC_SwitchField, 10, 1, // 6060: switch Inst[10] {
3084 0, 4, // 6063: case 0x0: {
3085 OPC_Decode, 147, 6, 82, // 6065: decode to DIVDE using decoder 82
3086 // 6065: }
3087 1, 0, // 6069: case 0x1: {
3088 OPC_Decode, 148, 6, 82, // 6071: decode to DIVDEO using decoder 82
3089 // 6071: }
3090 // 6071: } // switch Inst[10]
3091 // 6071: }
3092 3, 0, // 6075: case 0x3: {
3093 OPC_SwitchField, 10, 1, // 6077: switch Inst[10] {
3094 0, 4, // 6080: case 0x0: {
3095 OPC_Decode, 154, 6, 82, // 6082: decode to DIVDE_rec using decoder 82
3096 // 6082: }
3097 1, 0, // 6086: case 0x1: {
3098 OPC_Decode, 149, 6, 82, // 6088: decode to DIVDEO_rec using decoder 82
3099 // 6088: }
3100 // 6088: } // switch Inst[10]
3101 // 6088: }
3102 // 6088: } // switch Inst[1:0]
3103 // 6088: }
3104 14, 37, // 6092: case 0xe: {
3105 OPC_SwitchField, 0, 2, // 6094: switch Inst[1:0] {
3106 2, 15, // 6097: case 0x2: {
3107 OPC_SwitchField, 10, 1, // 6099: switch Inst[10] {
3108 0, 4, // 6102: case 0x0: {
3109 OPC_Decode, 157, 6, 82, // 6104: decode to DIVDU using decoder 82
3110 // 6104: }
3111 1, 0, // 6108: case 0x1: {
3112 OPC_Decode, 158, 6, 82, // 6110: decode to DIVDUO using decoder 82
3113 // 6110: }
3114 // 6110: } // switch Inst[10]
3115 // 6110: }
3116 3, 0, // 6114: case 0x3: {
3117 OPC_SwitchField, 10, 1, // 6116: switch Inst[10] {
3118 0, 4, // 6119: case 0x0: {
3119 OPC_Decode, 160, 6, 82, // 6121: decode to DIVDU_rec using decoder 82
3120 // 6121: }
3121 1, 0, // 6125: case 0x1: {
3122 OPC_Decode, 159, 6, 82, // 6127: decode to DIVDUO_rec using decoder 82
3123 // 6127: }
3124 // 6127: } // switch Inst[10]
3125 // 6127: }
3126 // 6127: } // switch Inst[1:0]
3127 // 6127: }
3128 15, 0, // 6131: case 0xf: {
3129 OPC_SwitchField, 0, 2, // 6133: switch Inst[1:0] {
3130 2, 15, // 6136: case 0x2: {
3131 OPC_SwitchField, 10, 1, // 6138: switch Inst[10] {
3132 0, 4, // 6141: case 0x0: {
3133 OPC_Decode, 146, 6, 82, // 6143: decode to DIVD using decoder 82
3134 // 6143: }
3135 1, 0, // 6147: case 0x1: {
3136 OPC_Decode, 155, 6, 82, // 6149: decode to DIVDO using decoder 82
3137 // 6149: }
3138 // 6149: } // switch Inst[10]
3139 // 6149: }
3140 3, 0, // 6153: case 0x3: {
3141 OPC_SwitchField, 10, 1, // 6155: switch Inst[10] {
3142 0, 4, // 6158: case 0x0: {
3143 OPC_Decode, 161, 6, 82, // 6160: decode to DIVD_rec using decoder 82
3144 // 6160: }
3145 1, 0, // 6164: case 0x1: {
3146 OPC_Decode, 156, 6, 82, // 6166: decode to DIVDO_rec using decoder 82
3147 // 6166: }
3148 // 6166: } // switch Inst[10]
3149 // 6166: }
3150 // 6166: } // switch Inst[1:0]
3151 // 6166: }
3152 // 6166: } // switch Inst[9:6]
3153 // 6166: }
3154 5, 166, 3, // 6170: case 0x5: {
3155 OPC_SwitchField, 6, 3, // 6173: switch Inst[8:6] {
3156 0, 94, // 6176: case 0x0: {
3157 OPC_SwitchField, 0, 2, // 6178: switch Inst[1:0] {
3158 0, 27, // 6181: case 0x0: {
3159 OPC_SwitchField, 9, 2, // 6183: switch Inst[10:9] {
3160 0, 4, // 6186: case 0x0: {
3161 OPC_Decode, 167, 3, 81, // 6188: decode to ADDC using decoder 81
3162 // 6188: }
3163 1, 4, // 6192: case 0x1: {
3164 OPC_Decode, 156, 3, 81, // 6194: decode to ADD4 using decoder 81
3165 // 6194: }
3166 2, 4, // 6198: case 0x2: {
3167 OPC_Decode, 172, 3, 81, // 6200: decode to ADDCO using decoder 81
3168 // 6200: }
3169 3, 0, // 6204: case 0x3: {
3170 OPC_Decode, 157, 3, 81, // 6206: decode to ADD4O using decoder 81
3171 // 6206: }
3172 // 6206: } // switch Inst[10:9]
3173 // 6206: }
3174 1, 27, // 6210: case 0x1: {
3175 OPC_SwitchField, 9, 2, // 6212: switch Inst[10:9] {
3176 0, 4, // 6215: case 0x0: {
3177 OPC_Decode, 174, 3, 81, // 6217: decode to ADDC_rec using decoder 81
3178 // 6217: }
3179 1, 4, // 6221: case 0x1: {
3180 OPC_Decode, 160, 3, 81, // 6223: decode to ADD4_rec using decoder 81
3181 // 6223: }
3182 2, 4, // 6227: case 0x2: {
3183 OPC_Decode, 173, 3, 81, // 6229: decode to ADDCO_rec using decoder 81
3184 // 6229: }
3185 3, 0, // 6233: case 0x3: {
3186 OPC_Decode, 158, 3, 81, // 6235: decode to ADD4O_rec using decoder 81
3187 // 6235: }
3188 // 6235: } // switch Inst[10:9]
3189 // 6235: }
3190 2, 21, // 6239: case 0x2: {
3191 OPC_SwitchField, 9, 2, // 6241: switch Inst[10:9] {
3192 0, 4, // 6244: case 0x0: {
3193 OPC_Decode, 185, 12, 81, // 6246: decode to MULHWU using decoder 81
3194 // 6246: }
3195 1, 4, // 6250: case 0x1: {
3196 OPC_Decode, 131, 12, 81, // 6252: decode to MODUW using decoder 81
3197 // 6252: }
3198 3, 0, // 6256: case 0x3: {
3199 OPC_Decode, 129, 12, 81, // 6258: decode to MODSW using decoder 81
3200 // 6258: }
3201 // 6258: } // switch Inst[10:9]
3202 // 6258: }
3203 3, 0, // 6262: case 0x3: {
3204 OPC_CheckField, 9, 2, 0, // 6264: check Inst[10:9] == 0x0
3205 OPC_Decode, 186, 12, 81, // 6268: decode to MULHWU_rec using decoder 81
3206 // 6268: }
3207 // 6268: } // switch Inst[1:0]
3208 // 6268: }
3209 2, 33, // 6272: case 0x2: {
3210 OPC_SwitchField, 0, 2, // 6274: switch Inst[1:0] {
3211 0, 8, // 6277: case 0x0: {
3212 OPC_CheckField, 9, 2, 0, // 6279: check Inst[10:9] == 0x0
3213 OPC_Decode, 185, 3, 81, // 6283: decode to ADDG6S using decoder 81
3214 // 6283: }
3215 2, 8, // 6287: case 0x2: {
3216 OPC_CheckField, 9, 2, 0, // 6289: check Inst[10:9] == 0x0
3217 OPC_Decode, 184, 12, 81, // 6293: decode to MULHW using decoder 81
3218 // 6293: }
3219 3, 0, // 6297: case 0x3: {
3220 OPC_CheckField, 9, 2, 0, // 6299: check Inst[10:9] == 0x0
3221 OPC_Decode, 187, 12, 81, // 6303: decode to MULHW_rec using decoder 81
3222 // 6303: }
3223 // 6303: } // switch Inst[1:0]
3224 // 6303: }
3225 4, 71, // 6307: case 0x4: {
3226 OPC_SwitchField, 0, 2, // 6309: switch Inst[1:0] {
3227 0, 15, // 6312: case 0x0: {
3228 OPC_SwitchField, 9, 2, // 6314: switch Inst[10:9] {
3229 0, 4, // 6317: case 0x0: {
3230 OPC_Decode, 175, 3, 81, // 6319: decode to ADDE using decoder 81
3231 // 6319: }
3232 2, 0, // 6323: case 0x2: {
3233 OPC_Decode, 180, 3, 81, // 6325: decode to ADDEO using decoder 81
3234 // 6325: }
3235 // 6325: } // switch Inst[10:9]
3236 // 6325: }
3237 1, 15, // 6329: case 0x1: {
3238 OPC_SwitchField, 9, 2, // 6331: switch Inst[10:9] {
3239 0, 4, // 6334: case 0x0: {
3240 OPC_Decode, 184, 3, 81, // 6336: decode to ADDE_rec using decoder 81
3241 // 6336: }
3242 2, 0, // 6340: case 0x2: {
3243 OPC_Decode, 181, 3, 81, // 6342: decode to ADDEO_rec using decoder 81
3244 // 6342: }
3245 // 6342: } // switch Inst[10:9]
3246 // 6342: }
3247 2, 15, // 6346: case 0x2: {
3248 OPC_SwitchField, 9, 2, // 6348: switch Inst[10:9] {
3249 1, 4, // 6351: case 0x1: {
3250 OPC_Decode, 166, 6, 81, // 6353: decode to DIVWEU using decoder 81
3251 // 6353: }
3252 3, 0, // 6357: case 0x3: {
3253 OPC_Decode, 167, 6, 81, // 6359: decode to DIVWEUO using decoder 81
3254 // 6359: }
3255 // 6359: } // switch Inst[10:9]
3256 // 6359: }
3257 3, 0, // 6363: case 0x3: {
3258 OPC_SwitchField, 9, 2, // 6365: switch Inst[10:9] {
3259 1, 4, // 6368: case 0x1: {
3260 OPC_Decode, 169, 6, 81, // 6370: decode to DIVWEU_rec using decoder 81
3261 // 6370: }
3262 3, 0, // 6374: case 0x3: {
3263 OPC_Decode, 168, 6, 81, // 6376: decode to DIVWEUO_rec using decoder 81
3264 // 6376: }
3265 // 6376: } // switch Inst[10:9]
3266 // 6376: }
3267 // 6376: } // switch Inst[1:0]
3268 // 6376: }
3269 5, 43, // 6380: case 0x5: {
3270 OPC_SwitchField, 0, 2, // 6382: switch Inst[1:0] {
3271 0, 4, // 6385: case 0x0: {
3272 OPC_Decode, 182, 3, 85, // 6387: decode to ADDEX using decoder 85
3273 // 6387: }
3274 2, 15, // 6391: case 0x2: {
3275 OPC_SwitchField, 9, 2, // 6393: switch Inst[10:9] {
3276 1, 4, // 6396: case 0x1: {
3277 OPC_Decode, 163, 6, 81, // 6398: decode to DIVWE using decoder 81
3278 // 6398: }
3279 3, 0, // 6402: case 0x3: {
3280 OPC_Decode, 164, 6, 81, // 6404: decode to DIVWEO using decoder 81
3281 // 6404: }
3282 // 6404: } // switch Inst[10:9]
3283 // 6404: }
3284 3, 0, // 6408: case 0x3: {
3285 OPC_SwitchField, 9, 2, // 6410: switch Inst[10:9] {
3286 1, 4, // 6413: case 0x1: {
3287 OPC_Decode, 170, 6, 81, // 6415: decode to DIVWE_rec using decoder 81
3288 // 6415: }
3289 3, 0, // 6419: case 0x3: {
3290 OPC_Decode, 165, 6, 81, // 6421: decode to DIVWEO_rec using decoder 81
3291 // 6421: }
3292 // 6421: } // switch Inst[10:9]
3293 // 6421: }
3294 // 6421: } // switch Inst[1:0]
3295 // 6421: }
3296 6, 71, // 6425: case 0x6: {
3297 OPC_SwitchField, 0, 2, // 6427: switch Inst[1:0] {
3298 0, 15, // 6430: case 0x0: {
3299 OPC_SwitchField, 9, 7, // 6432: switch Inst[15:9] {
3300 0, 4, // 6435: case 0x0: {
3301 OPC_Decode, 224, 3, 84, // 6437: decode to ADDZE using decoder 84
3302 // 6437: }
3303 2, 0, // 6441: case 0x2: {
3304 OPC_Decode, 229, 3, 84, // 6443: decode to ADDZEO using decoder 84
3305 // 6443: }
3306 // 6443: } // switch Inst[15:9]
3307 // 6443: }
3308 1, 15, // 6447: case 0x1: {
3309 OPC_SwitchField, 9, 7, // 6449: switch Inst[15:9] {
3310 0, 4, // 6452: case 0x0: {
3311 OPC_Decode, 231, 3, 84, // 6454: decode to ADDZE_rec using decoder 84
3312 // 6454: }
3313 2, 0, // 6458: case 0x2: {
3314 OPC_Decode, 230, 3, 84, // 6460: decode to ADDZEO_rec using decoder 84
3315 // 6460: }
3316 // 6460: } // switch Inst[15:9]
3317 // 6460: }
3318 2, 15, // 6464: case 0x2: {
3319 OPC_SwitchField, 9, 2, // 6466: switch Inst[10:9] {
3320 1, 4, // 6469: case 0x1: {
3321 OPC_Decode, 173, 6, 81, // 6471: decode to DIVWU using decoder 81
3322 // 6471: }
3323 3, 0, // 6475: case 0x3: {
3324 OPC_Decode, 174, 6, 81, // 6477: decode to DIVWUO using decoder 81
3325 // 6477: }
3326 // 6477: } // switch Inst[10:9]
3327 // 6477: }
3328 3, 0, // 6481: case 0x3: {
3329 OPC_SwitchField, 9, 2, // 6483: switch Inst[10:9] {
3330 1, 4, // 6486: case 0x1: {
3331 OPC_Decode, 176, 6, 81, // 6488: decode to DIVWU_rec using decoder 81
3332 // 6488: }
3333 3, 0, // 6492: case 0x3: {
3334 OPC_Decode, 175, 6, 81, // 6494: decode to DIVWUO_rec using decoder 81
3335 // 6494: }
3336 // 6494: } // switch Inst[10:9]
3337 // 6494: }
3338 // 6494: } // switch Inst[1:0]
3339 // 6494: }
3340 7, 0, // 6498: case 0x7: {
3341 OPC_SwitchField, 0, 2, // 6500: switch Inst[1:0] {
3342 0, 15, // 6503: case 0x0: {
3343 OPC_SwitchField, 9, 7, // 6505: switch Inst[15:9] {
3344 0, 4, // 6508: case 0x0: {
3345 OPC_Decode, 215, 3, 84, // 6510: decode to ADDME using decoder 84
3346 // 6510: }
3347 2, 0, // 6514: case 0x2: {
3348 OPC_Decode, 220, 3, 84, // 6516: decode to ADDMEO using decoder 84
3349 // 6516: }
3350 // 6516: } // switch Inst[15:9]
3351 // 6516: }
3352 1, 15, // 6520: case 0x1: {
3353 OPC_SwitchField, 9, 7, // 6522: switch Inst[15:9] {
3354 0, 4, // 6525: case 0x0: {
3355 OPC_Decode, 222, 3, 84, // 6527: decode to ADDME_rec using decoder 84
3356 // 6527: }
3357 2, 0, // 6531: case 0x2: {
3358 OPC_Decode, 221, 3, 84, // 6533: decode to ADDMEO_rec using decoder 84
3359 // 6533: }
3360 // 6533: } // switch Inst[15:9]
3361 // 6533: }
3362 2, 27, // 6537: case 0x2: {
3363 OPC_SwitchField, 9, 2, // 6539: switch Inst[10:9] {
3364 0, 4, // 6542: case 0x0: {
3365 OPC_Decode, 194, 12, 81, // 6544: decode to MULLW using decoder 81
3366 // 6544: }
3367 1, 4, // 6548: case 0x1: {
3368 OPC_Decode, 162, 6, 81, // 6550: decode to DIVW using decoder 81
3369 // 6550: }
3370 2, 4, // 6554: case 0x2: {
3371 OPC_Decode, 195, 12, 81, // 6556: decode to MULLWO using decoder 81
3372 // 6556: }
3373 3, 0, // 6560: case 0x3: {
3374 OPC_Decode, 171, 6, 81, // 6562: decode to DIVWO using decoder 81
3375 // 6562: }
3376 // 6562: } // switch Inst[10:9]
3377 // 6562: }
3378 3, 0, // 6566: case 0x3: {
3379 OPC_SwitchField, 9, 2, // 6568: switch Inst[10:9] {
3380 0, 4, // 6571: case 0x0: {
3381 OPC_Decode, 197, 12, 81, // 6573: decode to MULLW_rec using decoder 81
3382 // 6573: }
3383 1, 4, // 6577: case 0x1: {
3384 OPC_Decode, 177, 6, 81, // 6579: decode to DIVW_rec using decoder 81
3385 // 6579: }
3386 2, 4, // 6583: case 0x2: {
3387 OPC_Decode, 196, 12, 81, // 6585: decode to MULLWO_rec using decoder 81
3388 // 6585: }
3389 3, 0, // 6589: case 0x3: {
3390 OPC_Decode, 172, 6, 81, // 6591: decode to DIVWO_rec using decoder 81
3391 // 6591: }
3392 // 6591: } // switch Inst[10:9]
3393 // 6591: }
3394 // 6591: } // switch Inst[1:0]
3395 // 6591: }
3396 // 6591: } // switch Inst[8:6]
3397 // 6591: }
3398 6, 189, 3, // 6595: case 0x6: {
3399 OPC_SwitchField, 6, 5, // 6598: switch Inst[10:6] {
3400 0, 15, // 6601: case 0x0: {
3401 OPC_SwitchField, 1, 1, // 6603: switch Inst[1] {
3402 0, 4, // 6606: case 0x0: {
3403 OPC_Decode, 188, 11, 86, // 6608: decode to LXSIWZX using decoder 86
3404 // 6608: }
3405 1, 0, // 6612: case 0x1: {
3406 OPC_Decode, 204, 11, 87, // 6614: decode to LXVRBX using decoder 87
3407 // 6614: }
3408 // 6614: } // switch Inst[1]
3409 // 6614: }
3410 1, 8, // 6618: case 0x1: {
3411 OPC_CheckField, 1, 1, 1, // 6620: check Inst[1] == 0x1
3412 OPC_Decode, 206, 11, 87, // 6624: decode to LXVRHX using decoder 87
3413 // 6624: }
3414 2, 15, // 6628: case 0x2: {
3415 OPC_SwitchField, 1, 1, // 6630: switch Inst[1] {
3416 0, 4, // 6633: case 0x0: {
3417 OPC_Decode, 187, 11, 86, // 6635: decode to LXSIWAX using decoder 86
3418 // 6635: }
3419 1, 0, // 6639: case 0x1: {
3420 OPC_Decode, 209, 11, 87, // 6641: decode to LXVRWX using decoder 87
3421 // 6641: }
3422 // 6641: } // switch Inst[1]
3423 // 6641: }
3424 3, 8, // 6645: case 0x3: {
3425 OPC_CheckField, 1, 1, 1, // 6647: check Inst[1] == 0x1
3426 OPC_Decode, 205, 11, 87, // 6651: decode to LXVRDX using decoder 87
3427 // 6651: }
3428 4, 15, // 6655: case 0x4: {
3429 OPC_SwitchField, 1, 1, // 6657: switch Inst[1] {
3430 0, 4, // 6660: case 0x0: {
3431 OPC_Decode, 157, 16, 86, // 6662: decode to STXSIWX using decoder 86
3432 // 6662: }
3433 1, 0, // 6666: case 0x1: {
3434 OPC_Decode, 171, 16, 87, // 6668: decode to STXVRBX using decoder 87
3435 // 6668: }
3436 // 6668: } // switch Inst[1]
3437 // 6668: }
3438 5, 8, // 6672: case 0x5: {
3439 OPC_CheckField, 1, 1, 1, // 6674: check Inst[1] == 0x1
3440 OPC_Decode, 173, 16, 87, // 6678: decode to STXVRHX using decoder 87
3441 // 6678: }
3442 6, 8, // 6682: case 0x6: {
3443 OPC_CheckField, 1, 1, 1, // 6684: check Inst[1] == 0x1
3444 OPC_Decode, 176, 16, 87, // 6688: decode to STXVRWX using decoder 87
3445 // 6688: }
3446 7, 8, // 6692: case 0x7: {
3447 OPC_CheckField, 1, 1, 1, // 6694: check Inst[1] == 0x1
3448 OPC_Decode, 172, 16, 87, // 6698: decode to STXVRDX using decoder 87
3449 // 6698: }
3450 8, 15, // 6702: case 0x8: {
3451 OPC_SwitchField, 1, 1, // 6704: switch Inst[1] {
3452 0, 4, // 6707: case 0x0: {
3453 OPC_Decode, 212, 11, 87, // 6709: decode to LXVX using decoder 87
3454 // 6709: }
3455 1, 0, // 6713: case 0x1: {
3456 OPC_Decode, 197, 11, 88, // 6715: decode to LXVL using decoder 88
3457 // 6715: }
3458 // 6715: } // switch Inst[1]
3459 // 6715: }
3460 9, 8, // 6719: case 0x9: {
3461 OPC_CheckField, 1, 1, 1, // 6721: check Inst[1] == 0x1
3462 OPC_Decode, 198, 11, 88, // 6725: decode to LXVLL using decoder 88
3463 // 6725: }
3464 10, 19, // 6729: case 0xa: {
3465 OPC_SwitchField, 1, 1, // 6731: switch Inst[1] {
3466 0, 4, // 6734: case 0x0: {
3467 OPC_Decode, 194, 11, 87, // 6736: decode to LXVDSX using decoder 87
3468 // 6736: }
3469 1, 0, // 6740: case 0x1: {
3470 OPC_CheckField, 0, 1, 0, // 6742: check Inst[0] == 0x0
3471 OPC_Decode, 203, 11, 89, // 6746: decode to LXVPX using decoder 89
3472 // 6746: }
3473 // 6746: } // switch Inst[1]
3474 // 6746: }
3475 11, 8, // 6750: case 0xb: {
3476 OPC_CheckField, 1, 1, 0, // 6752: check Inst[1] == 0x0
3477 OPC_Decode, 211, 11, 87, // 6756: decode to LXVWSX using decoder 87
3478 // 6756: }
3479 12, 15, // 6760: case 0xc: {
3480 OPC_SwitchField, 1, 1, // 6762: switch Inst[1] {
3481 0, 4, // 6765: case 0x0: {
3482 OPC_Decode, 178, 16, 87, // 6767: decode to STXVX using decoder 87
3483 // 6767: }
3484 1, 0, // 6771: case 0x1: {
3485 OPC_Decode, 164, 16, 88, // 6773: decode to STXVL using decoder 88
3486 // 6773: }
3487 // 6773: } // switch Inst[1]
3488 // 6773: }
3489 13, 8, // 6777: case 0xd: {
3490 OPC_CheckField, 1, 1, 1, // 6779: check Inst[1] == 0x1
3491 OPC_Decode, 165, 16, 88, // 6783: decode to STXVLL using decoder 88
3492 // 6783: }
3493 14, 8, // 6787: case 0xe: {
3494 OPC_CheckField, 0, 2, 2, // 6789: check Inst[1:0] == 0x2
3495 OPC_Decode, 170, 16, 89, // 6793: decode to STXVPX using decoder 89
3496 // 6793: }
3497 16, 15, // 6797: case 0x10: {
3498 OPC_SwitchField, 1, 1, // 6799: switch Inst[1] {
3499 0, 4, // 6802: case 0x0: {
3500 OPC_Decode, 190, 11, 90, // 6804: decode to LXSSPX using decoder 90
3501 // 6804: }
3502 1, 0, // 6808: case 0x1: {
3503 OPC_Decode, 207, 11, 88, // 6810: decode to LXVRL using decoder 88
3504 // 6810: }
3505 // 6810: } // switch Inst[1]
3506 // 6810: }
3507 17, 8, // 6814: case 0x11: {
3508 OPC_CheckField, 1, 1, 1, // 6816: check Inst[1] == 0x1
3509 OPC_Decode, 208, 11, 88, // 6820: decode to LXVRLL using decoder 88
3510 // 6820: }
3511 18, 19, // 6824: case 0x12: {
3512 OPC_SwitchField, 1, 1, // 6826: switch Inst[1] {
3513 0, 4, // 6829: case 0x0: {
3514 OPC_Decode, 184, 11, 86, // 6831: decode to LXSDX using decoder 86
3515 // 6831: }
3516 1, 0, // 6835: case 0x1: {
3517 OPC_CheckField, 0, 1, 0, // 6837: check Inst[0] == 0x0
3518 OPC_Decode, 201, 11, 91, // 6841: decode to LXVPRL using decoder 91
3519 // 6841: }
3520 // 6841: } // switch Inst[1]
3521 // 6841: }
3522 19, 8, // 6845: case 0x13: {
3523 OPC_CheckField, 0, 2, 2, // 6847: check Inst[1:0] == 0x2
3524 OPC_Decode, 202, 11, 91, // 6851: decode to LXVPRLL using decoder 91
3525 // 6851: }
3526 20, 15, // 6855: case 0x14: {
3527 OPC_SwitchField, 1, 1, // 6857: switch Inst[1] {
3528 0, 4, // 6860: case 0x0: {
3529 OPC_Decode, 159, 16, 90, // 6862: decode to STXSSPX using decoder 90
3530 // 6862: }
3531 1, 0, // 6866: case 0x1: {
3532 OPC_Decode, 174, 16, 88, // 6868: decode to STXVRL using decoder 88
3533 // 6868: }
3534 // 6868: } // switch Inst[1]
3535 // 6868: }
3536 21, 8, // 6872: case 0x15: {
3537 OPC_CheckField, 1, 1, 1, // 6874: check Inst[1] == 0x1
3538 OPC_Decode, 175, 16, 88, // 6878: decode to STXVRLL using decoder 88
3539 // 6878: }
3540 22, 19, // 6882: case 0x16: {
3541 OPC_SwitchField, 1, 1, // 6884: switch Inst[1] {
3542 0, 4, // 6887: case 0x0: {
3543 OPC_Decode, 152, 16, 86, // 6889: decode to STXSDX using decoder 86
3544 // 6889: }
3545 1, 0, // 6893: case 0x1: {
3546 OPC_CheckField, 0, 1, 0, // 6895: check Inst[0] == 0x0
3547 OPC_Decode, 168, 16, 91, // 6899: decode to STXVPRL using decoder 91
3548 // 6899: }
3549 // 6899: } // switch Inst[1]
3550 // 6899: }
3551 23, 8, // 6903: case 0x17: {
3552 OPC_CheckField, 0, 2, 2, // 6905: check Inst[1:0] == 0x2
3553 OPC_Decode, 169, 16, 91, // 6909: decode to STXVPRLL using decoder 91
3554 // 6909: }
3555 24, 15, // 6913: case 0x18: {
3556 OPC_SwitchField, 1, 1, // 6915: switch Inst[1] {
3557 0, 4, // 6918: case 0x0: {
3558 OPC_Decode, 210, 11, 87, // 6920: decode to LXVW4X using decoder 87
3559 // 6920: }
3560 1, 0, // 6924: case 0x1: {
3561 OPC_Decode, 185, 11, 86, // 6926: decode to LXSIBZX using decoder 86
3562 // 6926: }
3563 // 6926: } // switch Inst[1]
3564 // 6926: }
3565 25, 15, // 6930: case 0x19: {
3566 OPC_SwitchField, 1, 1, // 6932: switch Inst[1] {
3567 0, 4, // 6935: case 0x0: {
3568 OPC_Decode, 195, 11, 87, // 6937: decode to LXVH8X using decoder 87
3569 // 6937: }
3570 1, 0, // 6941: case 0x1: {
3571 OPC_Decode, 186, 11, 86, // 6943: decode to LXSIHZX using decoder 86
3572 // 6943: }
3573 // 6943: } // switch Inst[1]
3574 // 6943: }
3575 26, 8, // 6947: case 0x1a: {
3576 OPC_CheckField, 1, 1, 0, // 6949: check Inst[1] == 0x0
3577 OPC_Decode, 193, 11, 87, // 6953: decode to LXVD2X using decoder 87
3578 // 6953: }
3579 27, 19, // 6957: case 0x1b: {
3580 OPC_SwitchField, 1, 1, // 6959: switch Inst[1] {
3581 0, 4, // 6962: case 0x0: {
3582 OPC_Decode, 192, 11, 87, // 6964: decode to LXVB16X using decoder 87
3583 // 6964: }
3584 1, 0, // 6968: case 0x1: {
3585 OPC_CheckField, 0, 1, 0, // 6970: check Inst[0] == 0x0
3586 OPC_Decode, 200, 11, 91, // 6974: decode to LXVPB32X using decoder 91
3587 // 6974: }
3588 // 6974: } // switch Inst[1]
3589 // 6974: }
3590 28, 15, // 6978: case 0x1c: {
3591 OPC_SwitchField, 1, 1, // 6980: switch Inst[1] {
3592 0, 4, // 6983: case 0x0: {
3593 OPC_Decode, 177, 16, 87, // 6985: decode to STXVW4X using decoder 87
3594 // 6985: }
3595 1, 0, // 6989: case 0x1: {
3596 OPC_Decode, 153, 16, 86, // 6991: decode to STXSIBX using decoder 86
3597 // 6991: }
3598 // 6991: } // switch Inst[1]
3599 // 6991: }
3600 29, 15, // 6995: case 0x1d: {
3601 OPC_SwitchField, 1, 1, // 6997: switch Inst[1] {
3602 0, 4, // 7000: case 0x0: {
3603 OPC_Decode, 163, 16, 87, // 7002: decode to STXVH8X using decoder 87
3604 // 7002: }
3605 1, 0, // 7006: case 0x1: {
3606 OPC_Decode, 155, 16, 86, // 7008: decode to STXSIHX using decoder 86
3607 // 7008: }
3608 // 7008: } // switch Inst[1]
3609 // 7008: }
3610 30, 8, // 7012: case 0x1e: {
3611 OPC_CheckField, 1, 1, 0, // 7014: check Inst[1] == 0x0
3612 OPC_Decode, 162, 16, 87, // 7018: decode to STXVD2X using decoder 87
3613 // 7018: }
3614 31, 0, // 7022: case 0x1f: {
3615 OPC_SwitchField, 1, 1, // 7024: switch Inst[1] {
3616 0, 4, // 7027: case 0x0: {
3617 OPC_Decode, 161, 16, 87, // 7029: decode to STXVB16X using decoder 87
3618 // 7029: }
3619 1, 0, // 7033: case 0x1: {
3620 OPC_CheckField, 0, 1, 0, // 7035: check Inst[0] == 0x0
3621 OPC_Decode, 167, 16, 91, // 7039: decode to STXVPB32X using decoder 91
3622 // 7039: }
3623 // 7039: } // switch Inst[1]
3624 // 7039: }
3625 // 7039: } // switch Inst[10:6]
3626 // 7039: }
3627 7, 157, 1, // 7043: case 0x7: {
3628 OPC_SwitchField, 0, 2, // 7046: switch Inst[1:0] {
3629 0, 41, // 7049: case 0x0: {
3630 OPC_SwitchField, 6, 5, // 7051: switch Inst[10:6] {
3631 9, 4, // 7054: case 0x9: {
3632 OPC_Decode, 221, 11, 92, // 7056: decode to MFBHRBE using decoder 92
3633 // 7056: }
3634 10, 4, // 7060: case 0xa: {
3635 OPC_Decode, 240, 11, 71, // 7062: decode to MFPMR using decoder 71
3636 // 7062: }
3637 13, 8, // 7066: case 0xd: {
3638 OPC_CheckField, 11, 15, 0, // 7068: check Inst[25:11] == 0x0
3639 OPC_Decode, 173, 5, 0, // 7072: decode to CLRBHRB using decoder 0
3640 // 7072: }
3641 14, 4, // 7076: case 0xe: {
3642 OPC_Decode, 157, 12, 93, // 7078: decode to MTPMR using decoder 93
3643 // 7078: }
3644 22, 0, // 7082: case 0x16: {
3645 OPC_CheckField, 11, 12, 0, // 7084: check Inst[22:11] == 0x0
3646 OPC_Decode, 238, 16, 68, // 7088: decode to TCHECK using decoder 68
3647 // 7088: }
3648 // 7088: } // switch Inst[10:6]
3649 // 7088: }
3650 1, 103, // 7092: case 0x1: {
3651 OPC_SwitchField, 6, 5, // 7094: switch Inst[10:6] {
3652 20, 12, // 7097: case 0x14: {
3653 OPC_CheckField, 22, 4, 0, // 7099: check Inst[25:22] == 0x0
3654 OPC_CheckField, 11, 10, 0, // 7103: check Inst[20:11] == 0x0
3655 OPC_Decode, 236, 16, 94, // 7107: decode to TBEGIN using decoder 94
3656 // 7107: }
3657 21, 8, // 7111: case 0x15: {
3658 OPC_CheckField, 11, 14, 0, // 7113: check Inst[24:11] == 0x0
3659 OPC_Decode, 248, 16, 95, // 7117: decode to TEND using decoder 95
3660 // 7117: }
3661 23, 12, // 7121: case 0x17: {
3662 OPC_CheckField, 22, 3, 0, // 7123: check Inst[24:22] == 0x0
3663 OPC_CheckField, 11, 10, 0, // 7127: check Inst[20:11] == 0x0
3664 OPC_Decode, 149, 17, 94, // 7131: decode to TSR using decoder 94
3665 // 7131: }
3666 24, 4, // 7135: case 0x18: {
3667 OPC_Decode, 228, 16, 72, // 7137: decode to TABORTWC using decoder 72
3668 // 7137: }
3669 25, 4, // 7141: case 0x19: {
3670 OPC_Decode, 226, 16, 72, // 7143: decode to TABORTDC using decoder 72
3671 // 7143: }
3672 26, 4, // 7147: case 0x1a: {
3673 OPC_Decode, 229, 16, 96, // 7149: decode to TABORTWCI using decoder 96
3674 // 7149: }
3675 27, 4, // 7153: case 0x1b: {
3676 OPC_Decode, 227, 16, 96, // 7155: decode to TABORTDCI using decoder 96
3677 // 7155: }
3678 28, 12, // 7159: case 0x1c: {
3679 OPC_CheckField, 21, 5, 0, // 7161: check Inst[25:21] == 0x0
3680 OPC_CheckField, 11, 5, 0, // 7165: check Inst[15:11] == 0x0
3681 OPC_Decode, 225, 16, 97, // 7169: decode to TABORT using decoder 97
3682 // 7169: }
3683 29, 12, // 7173: case 0x1d: {
3684 OPC_CheckField, 21, 5, 0, // 7175: check Inst[25:21] == 0x0
3685 OPC_CheckField, 11, 5, 0, // 7179: check Inst[15:11] == 0x0
3686 OPC_Decode, 148, 17, 97, // 7183: decode to TRECLAIM using decoder 97
3687 // 7183: }
3688 31, 0, // 7187: case 0x1f: {
3689 OPC_CheckField, 11, 15, 0, // 7189: check Inst[25:11] == 0x0
3690 OPC_Decode, 147, 17, 0, // 7193: decode to TRECHKPT using decoder 0
3691 // 7193: }
3692 // 7193: } // switch Inst[10:6]
3693 // 7193: }
3694 2, 0, // 7197: case 0x2: {
3695 OPC_Decode, 181, 10, 98, // 7199: decode to ISEL using decoder 98
3696 // 7199: }
3697 // 7199: } // switch Inst[1:0]
3698 // 7199: }
3699 8, 145, 1, // 7203: case 0x8: {
3700 OPC_SwitchField, 0, 2, // 7206: switch Inst[1:0] {
3701 0, 23, // 7209: case 0x0: {
3702 OPC_SwitchField, 20, 1, // 7211: switch Inst[20] {
3703 0, 8, // 7214: case 0x0: {
3704 OPC_CheckField, 6, 6, 4, // 7216: check Inst[11:6] == 0x4
3705 OPC_Decode, 134, 12, 99, // 7220: decode to MTCRF using decoder 99
3706 // 7220: }
3707 1, 0, // 7224: case 0x1: {
3708 OPC_CheckField, 6, 6, 4, // 7226: check Inst[11:6] == 0x4
3709 OPC_Decode, 155, 12, 100, // 7230: decode to MTOCRF using decoder 100
3710 // 7230: }
3711 // 7230: } // switch Inst[20]
3712 // 7230: }
3713 2, 0, // 7234: case 0x2: {
3714 OPC_SwitchField, 16, 5, // 7236: switch Inst[20:16] {
3715 0, 12, // 7239: case 0x0: {
3716 OPC_CheckField, 21, 2, 0, // 7241: check Inst[22:21] == 0x0
3717 OPC_CheckField, 6, 10, 5, // 7245: check Inst[15:6] == 0x5
3718 OPC_Decode, 144, 23, 101, // 7249: decode to XXMFACC using decoder 101
3719 // 7249: }
3720 1, 12, // 7253: case 0x1: {
3721 OPC_CheckField, 21, 2, 0, // 7255: check Inst[22:21] == 0x0
3722 OPC_CheckField, 6, 10, 5, // 7259: check Inst[15:6] == 0x5
3723 OPC_Decode, 148, 23, 101, // 7263: decode to XXMTACC using decoder 101
3724 // 7263: }
3725 2, 12, // 7267: case 0x2: {
3726 OPC_CheckField, 21, 2, 0, // 7269: check Inst[22:21] == 0x0
3727 OPC_CheckField, 6, 10, 5, // 7273: check Inst[15:6] == 0x5
3728 OPC_Decode, 179, 6, 102, // 7277: decode to DMSETDMRZ using decoder 102
3729 // 7277: }
3730 3, 12, // 7281: case 0x3: {
3731 OPC_CheckField, 21, 2, 0, // 7283: check Inst[22:21] == 0x0
3732 OPC_CheckField, 6, 10, 5, // 7287: check Inst[15:6] == 0x5
3733 OPC_Decode, 159, 23, 103, // 7291: decode to XXSETACCZ using decoder 103
3734 // 7291: }
3735 6, 12, // 7295: case 0x6: {
3736 OPC_CheckField, 21, 2, 0, // 7297: check Inst[22:21] == 0x0
3737 OPC_CheckField, 6, 7, 5, // 7301: check Inst[12:6] == 0x5
3738 OPC_Decode, 178, 6, 104, // 7305: decode to DMMR using decoder 104
3739 // 7305: }
3740 7, 12, // 7309: case 0x7: {
3741 OPC_CheckField, 21, 2, 0, // 7311: check Inst[22:21] == 0x0
3742 OPC_CheckField, 6, 7, 5, // 7315: check Inst[12:6] == 0x5
3743 OPC_Decode, 186, 6, 105, // 7319: decode to DMXOR using decoder 105
3744 // 7319: }
3745 14, 12, // 7323: case 0xe: {
3746 OPC_CheckField, 22, 1, 0, // 7325: check Inst[22] == 0x0
3747 OPC_CheckField, 6, 7, 5, // 7329: check Inst[12:6] == 0x5
3748 OPC_Decode, 180, 6, 106, // 7333: decode to DMSHA2HASH using decoder 106
3749 // 7333: }
3750 15, 0, // 7337: case 0xf: {
3751 OPC_CheckField, 21, 3, 0, // 7339: check Inst[23:21] == 0x0
3752 OPC_CheckField, 6, 5, 5, // 7343: check Inst[10:6] == 0x5
3753 OPC_Decode, 181, 6, 107, // 7347: decode to DMSHA3HASH using decoder 107
3754 // 7347: }
3755 // 7347: } // switch Inst[20:16]
3756 // 7347: }
3757 // 7347: } // switch Inst[1:0]
3758 // 7347: }
3759 9, 132, 5, // 7351: case 0x9: {
3760 OPC_SwitchField, 6, 5, // 7354: switch Inst[10:6] {
3761 0, 48, // 7357: case 0x0: {
3762 OPC_SwitchField, 0, 2, // 7359: switch Inst[1:0] {
3763 0, 18, // 7362: case 0x0: {
3764 OPC_Scope, 12, // 7364: try {
3765 OPC_CheckField, 16, 2, 0, // 7366: check Inst[17:16] == 0x0
3766 OPC_CheckField, 20, 1, 0, // 7370: check Inst[20] == 0x0
3767 OPC_Decode, 252, 16, 108, // 7374: decode to TLBIEIO using decoder 108
3768 // 7374: } else try {
3769 OPC_Decode, 129, 17, 109, // 7378: decode to TLBILX using decoder 109
3770 // 7378: }
3771 // 7378: }
3772 2, 0, // 7382: case 0x2: {
3773 OPC_SwitchField, 20, 1, // 7384: switch Inst[20] {
3774 0, 8, // 7387: case 0x0: {
3775 OPC_CheckField, 11, 9, 0, // 7389: check Inst[19:11] == 0x0
3776 OPC_Decode, 222, 11, 69, // 7393: decode to MFCR using decoder 69
3777 // 7393: }
3778 1, 0, // 7397: case 0x1: {
3779 OPC_CheckField, 11, 1, 0, // 7399: check Inst[11] == 0x0
3780 OPC_Decode, 238, 11, 110, // 7403: decode to MFOCRF using decoder 110
3781 // 7403: }
3782 // 7403: } // switch Inst[20]
3783 // 7403: }
3784 // 7403: } // switch Inst[1:0]
3785 // 7403: }
3786 1, 27, // 7407: case 0x1: {
3787 OPC_SwitchField, 1, 1, // 7409: switch Inst[1] {
3788 0, 12, // 7412: case 0x0: {
3789 OPC_CheckField, 20, 1, 0, // 7414: check Inst[20] == 0x0
3790 OPC_CheckField, 0, 1, 0, // 7418: check Inst[0] == 0x0
3791 OPC_Decode, 254, 16, 111, // 7422: decode to TLBIEP using decoder 111
3792 // 7422: }
3793 1, 0, // 7426: case 0x1: {
3794 OPC_CheckField, 11, 5, 0, // 7428: check Inst[15:11] == 0x0
3795 OPC_Decode, 253, 11, 112, // 7432: decode to MFVSRD using decoder 112
3796 // 7432: }
3797 // 7432: } // switch Inst[1]
3798 // 7432: }
3799 2, 12, // 7436: case 0x2: {
3800 OPC_CheckField, 11, 10, 0, // 7438: check Inst[20:11] == 0x0
3801 OPC_CheckField, 0, 2, 2, // 7442: check Inst[1:0] == 0x2
3802 OPC_Decode, 237, 11, 69, // 7446: decode to MFMSR using decoder 69
3803 // 7446: }
3804 3, 12, // 7450: case 0x3: {
3805 OPC_CheckField, 11, 5, 0, // 7452: check Inst[15:11] == 0x0
3806 OPC_CheckField, 1, 1, 1, // 7456: check Inst[1] == 0x1
3807 OPC_Decode, 255, 11, 113, // 7460: decode to MFVSRWZ using decoder 113
3808 // 7460: }
3809 4, 8, // 7464: case 0x4: {
3810 OPC_CheckField, 1, 1, 0, // 7466: check Inst[1] == 0x0
3811 OPC_Decode, 153, 12, 114, // 7470: decode to MTMSR using decoder 114
3812 // 7470: }
3813 5, 19, // 7474: case 0x5: {
3814 OPC_SwitchField, 1, 1, // 7476: switch Inst[1] {
3815 0, 4, // 7479: case 0x0: {
3816 OPC_Decode, 154, 12, 114, // 7481: decode to MTMSRD using decoder 114
3817 // 7481: }
3818 1, 0, // 7485: case 0x1: {
3819 OPC_CheckField, 11, 5, 0, // 7487: check Inst[15:11] == 0x0
3820 OPC_Decode, 171, 12, 115, // 7491: decode to MTVSRD using decoder 115
3821 // 7491: }
3822 // 7491: } // switch Inst[1]
3823 // 7491: }
3824 6, 19, // 7495: case 0x6: {
3825 OPC_SwitchField, 1, 1, // 7497: switch Inst[1] {
3826 0, 4, // 7500: case 0x0: {
3827 OPC_Decode, 160, 12, 116, // 7502: decode to MTSR using decoder 116
3828 // 7502: }
3829 1, 0, // 7506: case 0x1: {
3830 OPC_CheckField, 11, 5, 0, // 7508: check Inst[15:11] == 0x0
3831 OPC_Decode, 176, 12, 117, // 7512: decode to MTVSRWA using decoder 117
3832 // 7512: }
3833 // 7512: } // switch Inst[1]
3834 // 7512: }
3835 7, 19, // 7516: case 0x7: {
3836 OPC_SwitchField, 1, 1, // 7518: switch Inst[1] {
3837 0, 4, // 7521: case 0x0: {
3838 OPC_Decode, 161, 12, 118, // 7523: decode to MTSRIN using decoder 118
3839 // 7523: }
3840 1, 0, // 7527: case 0x1: {
3841 OPC_CheckField, 11, 5, 0, // 7529: check Inst[15:11] == 0x0
3842 OPC_Decode, 179, 12, 117, // 7533: decode to MTVSRWZ using decoder 117
3843 // 7533: }
3844 // 7533: } // switch Inst[1]
3845 // 7533: }
3846 8, 23, // 7537: case 0x8: {
3847 OPC_SwitchField, 0, 2, // 7539: switch Inst[1:0] {
3848 0, 8, // 7542: case 0x0: {
3849 OPC_CheckField, 16, 10, 0, // 7544: check Inst[25:16] == 0x0
3850 OPC_Decode, 253, 16, 119, // 7548: decode to TLBIEL using decoder 119
3851 // 7548: }
3852 2, 0, // 7552: case 0x2: {
3853 OPC_CheckField, 16, 5, 0, // 7554: check Inst[20:16] == 0x0
3854 OPC_Decode, 149, 12, 120, // 7558: decode to MTLPL using decoder 120
3855 // 7558: }
3856 // 7558: } // switch Inst[1:0]
3857 // 7558: }
3858 9, 37, // 7562: case 0x9: {
3859 OPC_SwitchField, 1, 1, // 7564: switch Inst[1] {
3860 0, 22, // 7567: case 0x0: {
3861 OPC_CheckField, 0, 1, 0, // 7569: check Inst[0] == 0x0
3862 OPC_CheckField, 20, 1, 0, // 7573: check Inst[20] == 0x0
3863 OPC_Scope, 8, // 7577: try {
3864 OPC_CheckField, 16, 4, 0, // 7579: check Inst[19:16] == 0x0
3865 OPC_Decode, 250, 16, 118, // 7583: decode to TLBIE using decoder 118
3866 // 7583: } else try {
3867 OPC_Decode, 128, 17, 111, // 7587: decode to TLBIEP9 using decoder 111
3868 // 7587: }
3869 // 7587: }
3870 1, 0, // 7591: case 0x1: {
3871 OPC_CheckField, 11, 5, 0, // 7593: check Inst[15:11] == 0x0
3872 OPC_Decode, 254, 11, 121, // 7597: decode to MFVSRLD using decoder 121
3873 // 7597: }
3874 // 7597: } // switch Inst[1]
3875 // 7597: }
3876 10, 44, // 7601: case 0xa: {
3877 OPC_SwitchField, 0, 2, // 7603: switch Inst[1:0] {
3878 0, 8, // 7606: case 0x0: {
3879 OPC_CheckField, 11, 15, 0, // 7608: check Inst[25:11] == 0x0
3880 OPC_Decode, 160, 15, 0, // 7612: decode to SLBSYNC using decoder 0
3881 // 7612: }
3882 2, 0, // 7616: case 0x2: {
3883 OPC_Scope, 23, // 7618: try {
3884 OPC_SwitchField, 11, 10, // 7620: switch Inst[20:11] {
3885 96, 4, // 7623: case 0x60: {
3886 OPC_Decode, 247, 11, 69, // 7625: decode to MFUDSCR using decoder 69
3887 // 7625: }
3888 128, 2, 4, // 7629: case 0x100: {
3889 OPC_Decode, 235, 11, 69, // 7632: decode to MFLR using decoder 69
3890 // 7632: }
3891 160, 2, 0, // 7636: case 0x120: {
3892 OPC_Decode, 224, 11, 69, // 7639: decode to MFCTR using decoder 69
3893 // 7639: }
3894 // 7639: } // switch Inst[20:11]
3895 // 7639: } else try {
3896 OPC_Decode, 241, 11, 71, // 7643: decode to MFSPR using decoder 71
3897 // 7643: }
3898 // 7643: }
3899 // 7643: } // switch Inst[1:0]
3900 // 7643: }
3901 11, 19, // 7647: case 0xb: {
3902 OPC_SwitchField, 0, 2, // 7649: switch Inst[1:0] {
3903 0, 8, // 7652: case 0x0: {
3904 OPC_CheckField, 11, 15, 0, // 7654: check Inst[25:11] == 0x0
3905 OPC_Decode, 249, 16, 0, // 7658: decode to TLBIA using decoder 0
3906 // 7658: }
3907 2, 0, // 7662: case 0x2: {
3908 OPC_Decode, 245, 11, 71, // 7664: decode to MFTB using decoder 71
3909 // 7664: }
3910 // 7664: } // switch Inst[1:0]
3911 // 7664: }
3912 12, 27, // 7668: case 0xc: {
3913 OPC_SwitchField, 1, 1, // 7670: switch Inst[1] {
3914 0, 12, // 7673: case 0x0: {
3915 OPC_CheckField, 16, 5, 0, // 7675: check Inst[20:16] == 0x0
3916 OPC_CheckField, 0, 1, 0, // 7679: check Inst[0] == 0x0
3917 OPC_Decode, 159, 15, 118, // 7683: decode to SLBMTE using decoder 118
3918 // 7683: }
3919 1, 0, // 7687: case 0x1: {
3920 OPC_CheckField, 11, 5, 0, // 7689: check Inst[15:11] == 0x0
3921 OPC_Decode, 178, 12, 122, // 7693: decode to MTVSRWS using decoder 122
3922 // 7693: }
3923 // 7693: } // switch Inst[1]
3924 // 7693: }
3925 13, 23, // 7697: case 0xd: {
3926 OPC_SwitchField, 1, 1, // 7699: switch Inst[1] {
3927 0, 12, // 7702: case 0x0: {
3928 OPC_CheckField, 16, 10, 0, // 7704: check Inst[25:16] == 0x0
3929 OPC_CheckField, 0, 1, 0, // 7708: check Inst[0] == 0x0
3930 OPC_Decode, 155, 15, 119, // 7712: decode to SLBIE using decoder 119
3931 // 7712: }
3932 1, 0, // 7716: case 0x1: {
3933 OPC_Decode, 172, 12, 123, // 7718: decode to MTVSRDD using decoder 123
3934 // 7718: }
3935 // 7718: } // switch Inst[1]
3936 // 7718: }
3937 14, 44, // 7722: case 0xe: {
3938 OPC_SwitchField, 0, 2, // 7724: switch Inst[1:0] {
3939 0, 8, // 7727: case 0x0: {
3940 OPC_CheckField, 16, 5, 0, // 7729: check Inst[20:16] == 0x0
3941 OPC_Decode, 156, 15, 118, // 7733: decode to SLBIEG using decoder 118
3942 // 7733: }
3943 2, 0, // 7737: case 0x2: {
3944 OPC_Scope, 23, // 7739: try {
3945 OPC_SwitchField, 11, 10, // 7741: switch Inst[20:11] {
3946 96, 4, // 7744: case 0x60: {
3947 OPC_Decode, 162, 12, 69, // 7746: decode to MTUDSCR using decoder 69
3948 // 7746: }
3949 128, 2, 4, // 7750: case 0x100: {
3950 OPC_Decode, 151, 12, 69, // 7753: decode to MTLR using decoder 69
3951 // 7753: }
3952 160, 2, 0, // 7757: case 0x120: {
3953 OPC_Decode, 136, 12, 69, // 7760: decode to MTCTR using decoder 69
3954 // 7760: }
3955 // 7760: } // switch Inst[20:11]
3956 // 7760: } else try {
3957 OPC_Decode, 158, 12, 93, // 7764: decode to MTSPR using decoder 93
3958 // 7764: }
3959 // 7764: }
3960 // 7764: } // switch Inst[1:0]
3961 // 7764: }
3962 15, 12, // 7768: case 0xf: {
3963 OPC_CheckField, 11, 15, 0, // 7770: check Inst[25:11] == 0x0
3964 OPC_CheckField, 0, 2, 0, // 7774: check Inst[1:0] == 0x0
3965 OPC_Decode, 154, 15, 0, // 7778: decode to SLBIA using decoder 0
3966 // 7778: }
3967 18, 8, // 7782: case 0x12: {
3968 OPC_CheckField, 1, 1, 1, // 7784: check Inst[1] == 0x1
3969 OPC_Decode, 243, 11, 116, // 7788: decode to MFSR using decoder 116
3970 // 7788: }
3971 20, 15, // 7792: case 0x14: {
3972 OPC_SwitchField, 1, 1, // 7794: switch Inst[1] {
3973 0, 4, // 7797: case 0x0: {
3974 OPC_Decode, 171, 10, 124, // 7799: decode to HASHSTP using decoder 124
3975 // 7799: }
3976 1, 0, // 7803: case 0x1: {
3977 OPC_Decode, 244, 11, 118, // 7805: decode to MFSRIN using decoder 118
3978 // 7805: }
3979 // 7805: } // switch Inst[1]
3980 // 7805: }
3981 21, 8, // 7809: case 0x15: {
3982 OPC_CheckField, 1, 1, 0, // 7811: check Inst[1] == 0x0
3983 OPC_Decode, 167, 10, 124, // 7815: decode to HASHCHKP using decoder 124
3984 // 7815: }
3985 22, 8, // 7819: case 0x16: {
3986 OPC_CheckField, 1, 1, 0, // 7821: check Inst[1] == 0x0
3987 OPC_Decode, 169, 10, 124, // 7825: decode to HASHST using decoder 124
3988 // 7825: }
3989 23, 27, // 7829: case 0x17: {
3990 OPC_SwitchField, 1, 1, // 7831: switch Inst[1] {
3991 0, 4, // 7834: case 0x0: {
3992 OPC_Decode, 165, 10, 124, // 7836: decode to HASHCHK using decoder 124
3993 // 7836: }
3994 1, 0, // 7840: case 0x1: {
3995 OPC_CheckField, 18, 3, 0, // 7842: check Inst[20:18] == 0x0
3996 OPC_CheckField, 11, 5, 0, // 7846: check Inst[15:11] == 0x0
3997 OPC_CheckField, 0, 1, 0, // 7850: check Inst[0] == 0x0
3998 OPC_Decode, 224, 5, 125, // 7854: decode to DARN using decoder 125
3999 // 7854: }
4000 // 7854: } // switch Inst[1]
4001 // 7854: }
4002 24, 12, // 7858: case 0x18: {
4003 OPC_CheckField, 21, 5, 0, // 7860: check Inst[25:21] == 0x0
4004 OPC_CheckField, 0, 2, 0, // 7864: check Inst[1:0] == 0x0
4005 OPC_Decode, 130, 17, 76, // 7868: decode to TLBIVAX using decoder 76
4006 // 7868: }
4007 26, 12, // 7872: case 0x1a: {
4008 OPC_CheckField, 16, 5, 0, // 7874: check Inst[20:16] == 0x0
4009 OPC_CheckField, 0, 2, 2, // 7878: check Inst[1:0] == 0x2
4010 OPC_Decode, 158, 15, 118, // 7882: decode to SLBMFEV using decoder 118
4011 // 7882: }
4012 28, 35, // 7886: case 0x1c: {
4013 OPC_SwitchField, 0, 2, // 7888: switch Inst[1:0] {
4014 0, 14, // 7891: case 0x0: {
4015 OPC_Scope, 8, // 7893: try {
4016 OPC_CheckField, 21, 5, 0, // 7895: check Inst[25:21] == 0x0
4017 OPC_Decode, 135, 17, 76, // 7899: decode to TLBSX using decoder 76
4018 // 7899: } else try {
4019 OPC_Decode, 136, 17, 81, // 7903: decode to TLBSX2 using decoder 81
4020 // 7903: }
4021 // 7903: }
4022 1, 4, // 7907: case 0x1: {
4023 OPC_Decode, 137, 17, 81, // 7909: decode to TLBSX2D using decoder 81
4024 // 7909: }
4025 2, 0, // 7913: case 0x2: {
4026 OPC_CheckField, 16, 5, 0, // 7915: check Inst[20:16] == 0x0
4027 OPC_Decode, 157, 15, 118, // 7919: decode to SLBMFEE using decoder 118
4028 // 7919: }
4029 // 7919: } // switch Inst[1:0]
4030 // 7919: }
4031 29, 18, // 7923: case 0x1d: {
4032 OPC_CheckField, 0, 2, 0, // 7925: check Inst[1:0] == 0x0
4033 OPC_Scope, 8, // 7929: try {
4034 OPC_CheckField, 11, 15, 0, // 7931: check Inst[25:11] == 0x0
4035 OPC_Decode, 133, 17, 0, // 7935: decode to TLBRE using decoder 0
4036 // 7935: } else try {
4037 OPC_Decode, 134, 17, 126, // 7939: decode to TLBRE2 using decoder 126
4038 // 7939: }
4039 // 7939: }
4040 30, 39, // 7943: case 0x1e: {
4041 OPC_SwitchField, 0, 2, // 7945: switch Inst[1:0] {
4042 0, 24, // 7948: case 0x0: {
4043 OPC_Scope, 8, // 7950: try {
4044 OPC_CheckField, 11, 15, 0, // 7952: check Inst[25:11] == 0x0
4045 OPC_Decode, 140, 17, 0, // 7956: decode to TLBWE using decoder 0
4046 OPC_Scope, 8, // 7960: } else try {
4047 OPC_CheckField, 16, 10, 0, // 7962: check Inst[25:16] == 0x0
4048 OPC_Decode, 131, 17, 119, // 7966: decode to TLBLD using decoder 119
4049 // 7966: } else try {
4050 OPC_Decode, 141, 17, 126, // 7970: decode to TLBWE2 using decoder 126
4051 // 7970: }
4052 // 7970: }
4053 3, 0, // 7974: case 0x3: {
4054 OPC_CheckField, 16, 5, 0, // 7976: check Inst[20:16] == 0x0
4055 OPC_Decode, 153, 15, 118, // 7980: decode to SLBFEE_rec using decoder 118
4056 // 7980: }
4057 // 7980: } // switch Inst[1:0]
4058 // 7980: }
4059 31, 0, // 7984: case 0x1f: {
4060 OPC_CheckField, 16, 10, 0, // 7986: check Inst[25:16] == 0x0
4061 OPC_CheckField, 0, 2, 0, // 7990: check Inst[1:0] == 0x0
4062 OPC_Decode, 132, 17, 119, // 7994: decode to TLBLI using decoder 119
4063 // 7994: }
4064 // 7994: } // switch Inst[10:6]
4065 // 7994: }
4066 10, 173, 2, // 7998: case 0xa: {
4067 OPC_SwitchField, 6, 5, // 8001: switch Inst[10:6] {
4068 0, 22, // 8004: case 0x0: {
4069 OPC_SwitchField, 0, 2, // 8006: switch Inst[1:0] {
4070 0, 4, // 8009: case 0x0: {
4071 OPC_Decode, 154, 11, 127, // 8011: decode to LWARX using decoder 127
4072 // 8011: }
4073 1, 4, // 8015: case 0x1: {
4074 OPC_Decode, 155, 11, 127, // 8017: decode to LWARXL using decoder 127
4075 // 8017: }
4076 2, 0, // 8021: case 0x2: {
4077 OPC_Decode, 211, 10, 128, 1, // 8023: decode to LDX using decoder 128
4078 // 8023: }
4079 // 8023: } // switch Inst[1:0]
4080 // 8023: }
4081 1, 22, // 8028: case 0x1: {
4082 OPC_SwitchField, 0, 2, // 8030: switch Inst[1:0] {
4083 0, 4, // 8033: case 0x0: {
4084 OPC_Decode, 186, 10, 127, // 8035: decode to LBARX using decoder 127
4085 // 8035: }
4086 1, 4, // 8039: case 0x1: {
4087 OPC_Decode, 187, 10, 127, // 8041: decode to LBARXL using decoder 127
4088 // 8041: }
4089 2, 0, // 8045: case 0x2: {
4090 OPC_Decode, 210, 10, 129, 1, // 8047: decode to LDUX using decoder 129
4091 // 8047: }
4092 // 8047: } // switch Inst[1:0]
4093 // 8047: }
4094 2, 17, // 8052: case 0x2: {
4095 OPC_SwitchField, 0, 2, // 8054: switch Inst[1:0] {
4096 0, 5, // 8057: case 0x0: {
4097 OPC_Decode, 202, 10, 128, 1, // 8059: decode to LDARX using decoder 128
4098 // 8059: }
4099 1, 0, // 8064: case 0x1: {
4100 OPC_Decode, 203, 10, 128, 1, // 8066: decode to LDARXL using decoder 128
4101 // 8066: }
4102 // 8066: } // switch Inst[1:0]
4103 // 8066: }
4104 3, 15, // 8071: case 0x3: {
4105 OPC_SwitchField, 0, 2, // 8073: switch Inst[1:0] {
4106 0, 4, // 8076: case 0x0: {
4107 OPC_Decode, 238, 10, 127, // 8078: decode to LHARX using decoder 127
4108 // 8078: }
4109 1, 0, // 8082: case 0x1: {
4110 OPC_Decode, 239, 10, 127, // 8084: decode to LHARXL using decoder 127
4111 // 8084: }
4112 // 8084: } // switch Inst[1:0]
4113 // 8084: }
4114 4, 9, // 8088: case 0x4: {
4115 OPC_CheckField, 0, 2, 2, // 8090: check Inst[1:0] == 0x2
4116 OPC_Decode, 220, 15, 128, 1, // 8094: decode to STDX using decoder 128
4117 // 8094: }
4118 5, 9, // 8099: case 0x5: {
4119 OPC_CheckField, 0, 2, 2, // 8101: check Inst[1:0] == 0x2
4120 OPC_Decode, 219, 15, 130, 1, // 8105: decode to STDUX using decoder 130
4121 // 8105: }
4122 8, 17, // 8110: case 0x8: {
4123 OPC_SwitchField, 0, 2, // 8112: switch Inst[1:0] {
4124 0, 5, // 8115: case 0x0: {
4125 OPC_Decode, 142, 11, 131, 1, // 8117: decode to LQARX using decoder 131
4126 // 8117: }
4127 1, 0, // 8122: case 0x1: {
4128 OPC_Decode, 143, 11, 131, 1, // 8124: decode to LQARXL using decoder 131
4129 // 8124: }
4130 // 8124: } // switch Inst[1:0]
4131 // 8124: }
4132 10, 9, // 8129: case 0xa: {
4133 OPC_CheckField, 0, 2, 2, // 8131: check Inst[1:0] == 0x2
4134 OPC_Decode, 160, 11, 128, 1, // 8135: decode to LWAX using decoder 128
4135 // 8135: }
4136 11, 9, // 8140: case 0xb: {
4137 OPC_CheckField, 0, 2, 2, // 8142: check Inst[1:0] == 0x2
4138 OPC_Decode, 159, 11, 129, 1, // 8146: decode to LWAUX using decoder 129
4139 // 8146: }
4140 16, 9, // 8151: case 0x10: {
4141 OPC_CheckField, 0, 2, 0, // 8153: check Inst[1:0] == 0x0
4142 OPC_Decode, 207, 10, 128, 1, // 8157: decode to LDBRX using decoder 128
4143 // 8157: }
4144 17, 13, // 8162: case 0x11: {
4145 OPC_CheckField, 11, 10, 0, // 8164: check Inst[20:11] == 0x0
4146 OPC_CheckField, 0, 2, 0, // 8168: check Inst[1:0] == 0x0
4147 OPC_Decode, 139, 17, 132, 1, // 8172: decode to TLBSYNCIO using decoder 132
4148 // 8172: }
4149 18, 21, // 8177: case 0x12: {
4150 OPC_SwitchField, 0, 2, // 8179: switch Inst[1:0] {
4151 0, 9, // 8182: case 0x0: {
4152 OPC_CheckField, 11, 10, 0, // 8184: check Inst[20:11] == 0x0
4153 OPC_Decode, 199, 14, 132, 1, // 8188: decode to PTESYNCIO using decoder 132
4154 // 8188: }
4155 2, 0, // 8193: case 0x2: {
4156 OPC_Decode, 145, 11, 133, 1, // 8195: decode to LSWI using decoder 133
4157 // 8195: }
4158 // 8195: } // switch Inst[1:0]
4159 // 8195: }
4160 20, 9, // 8200: case 0x14: {
4161 OPC_CheckField, 0, 2, 0, // 8202: check Inst[1:0] == 0x0
4162 OPC_Decode, 215, 15, 128, 1, // 8206: decode to STDBRX using decoder 128
4163 // 8206: }
4164 22, 9, // 8211: case 0x16: {
4165 OPC_CheckField, 0, 2, 2, // 8213: check Inst[1:0] == 0x2
4166 OPC_Decode, 129, 16, 133, 1, // 8217: decode to STSWI using decoder 133
4167 // 8217: }
4168 24, 8, // 8222: case 0x18: {
4169 OPC_CheckField, 0, 2, 2, // 8224: check Inst[1:0] == 0x2
4170 OPC_Decode, 171, 11, 81, // 8228: decode to LWZCIX using decoder 81
4171 // 8228: }
4172 25, 8, // 8232: case 0x19: {
4173 OPC_CheckField, 0, 2, 2, // 8234: check Inst[1:0] == 0x2
4174 OPC_Decode, 254, 10, 81, // 8238: decode to LHZCIX using decoder 81
4175 // 8238: }
4176 26, 8, // 8242: case 0x1a: {
4177 OPC_CheckField, 0, 2, 2, // 8244: check Inst[1:0] == 0x2
4178 OPC_Decode, 191, 10, 81, // 8248: decode to LBZCIX using decoder 81
4179 // 8248: }
4180 27, 8, // 8252: case 0x1b: {
4181 OPC_CheckField, 0, 2, 2, // 8254: check Inst[1:0] == 0x2
4182 OPC_Decode, 208, 10, 81, // 8258: decode to LDCIX using decoder 81
4183 // 8258: }
4184 28, 8, // 8262: case 0x1c: {
4185 OPC_CheckField, 0, 2, 2, // 8264: check Inst[1:0] == 0x2
4186 OPC_Decode, 139, 16, 81, // 8268: decode to STWCIX using decoder 81
4187 // 8268: }
4188 29, 8, // 8272: case 0x1d: {
4189 OPC_CheckField, 0, 2, 2, // 8274: check Inst[1:0] == 0x2
4190 OPC_Decode, 240, 15, 81, // 8278: decode to STHCIX using decoder 81
4191 // 8278: }
4192 30, 8, // 8282: case 0x1e: {
4193 OPC_CheckField, 0, 2, 2, // 8284: check Inst[1:0] == 0x2
4194 OPC_Decode, 201, 15, 81, // 8288: decode to STBCIX using decoder 81
4195 // 8288: }
4196 31, 0, // 8292: case 0x1f: {
4197 OPC_CheckField, 0, 2, 2, // 8294: check Inst[1:0] == 0x2
4198 OPC_Decode, 216, 15, 81, // 8298: decode to STDCIX using decoder 81
4199 // 8298: }
4200 // 8298: } // switch Inst[10:6]
4201 // 8298: }
4202 11, 228, 4, // 8302: case 0xb: {
4203 OPC_SwitchField, 6, 5, // 8305: switch Inst[10:6] {
4204 0, 19, // 8308: case 0x0: {
4205 OPC_SwitchField, 0, 2, // 8310: switch Inst[1:0] {
4206 0, 8, // 8313: case 0x0: {
4207 OPC_CheckField, 25, 1, 0, // 8315: check Inst[25] == 0x0
4208 OPC_Decode, 178, 10, 75, // 8319: decode to ICBT using decoder 75
4209 // 8319: }
4210 2, 0, // 8323: case 0x2: {
4211 OPC_Decode, 176, 11, 127, // 8325: decode to LWZX using decoder 127
4212 // 8325: }
4213 // 8325: } // switch Inst[1:0]
4214 // 8325: }
4215 1, 21, // 8329: case 0x1: {
4216 OPC_SwitchField, 0, 2, // 8331: switch Inst[1:0] {
4217 0, 9, // 8334: case 0x0: {
4218 OPC_CheckField, 21, 5, 0, // 8336: check Inst[25:21] == 0x0
4219 OPC_Decode, 229, 5, 134, 1, // 8340: decode to DCBST using decoder 134
4220 // 8340: }
4221 2, 0, // 8345: case 0x2: {
4222 OPC_Decode, 174, 11, 135, 1, // 8347: decode to LWZUX using decoder 135
4223 // 8347: }
4224 // 8347: } // switch Inst[1:0]
4225 // 8347: }
4226 2, 16, // 8352: case 0x2: {
4227 OPC_SwitchField, 0, 2, // 8354: switch Inst[1:0] {
4228 0, 5, // 8357: case 0x0: {
4229 OPC_Decode, 226, 5, 136, 1, // 8359: decode to DCBF using decoder 136
4230 // 8359: }
4231 2, 0, // 8364: case 0x2: {
4232 OPC_Decode, 196, 10, 127, // 8366: decode to LBZX using decoder 127
4233 // 8366: }
4234 // 8366: } // switch Inst[1:0]
4235 // 8366: }
4236 3, 9, // 8370: case 0x3: {
4237 OPC_CheckField, 0, 2, 2, // 8372: check Inst[1:0] == 0x2
4238 OPC_Decode, 194, 10, 135, 1, // 8376: decode to LBZUX using decoder 135
4239 // 8376: }
4240 4, 15, // 8381: case 0x4: {
4241 OPC_SwitchField, 0, 2, // 8383: switch Inst[1:0] {
4242 1, 4, // 8386: case 0x1: {
4243 OPC_Decode, 140, 16, 127, // 8388: decode to STWCX using decoder 127
4244 // 8388: }
4245 2, 0, // 8392: case 0x2: {
4246 OPC_Decode, 146, 16, 127, // 8394: decode to STWX using decoder 127
4247 // 8394: }
4248 // 8394: } // switch Inst[1:0]
4249 // 8394: }
4250 5, 17, // 8398: case 0x5: {
4251 OPC_SwitchField, 0, 2, // 8400: switch Inst[1:0] {
4252 1, 5, // 8403: case 0x1: {
4253 OPC_Decode, 255, 15, 131, 1, // 8405: decode to STQCX using decoder 131
4254 // 8405: }
4255 2, 0, // 8410: case 0x2: {
4256 OPC_Decode, 144, 16, 137, 1, // 8412: decode to STWUX using decoder 137
4257 // 8412: }
4258 // 8412: } // switch Inst[1:0]
4259 // 8412: }
4260 6, 16, // 8417: case 0x6: {
4261 OPC_SwitchField, 0, 2, // 8419: switch Inst[1:0] {
4262 1, 5, // 8422: case 0x1: {
4263 OPC_Decode, 217, 15, 128, 1, // 8424: decode to STDCX using decoder 128
4264 // 8424: }
4265 2, 0, // 8429: case 0x2: {
4266 OPC_Decode, 208, 15, 127, // 8431: decode to STBX using decoder 127
4267 // 8431: }
4268 // 8431: } // switch Inst[1:0]
4269 // 8431: }
4270 7, 17, // 8435: case 0x7: {
4271 OPC_SwitchField, 0, 2, // 8437: switch Inst[1:0] {
4272 0, 5, // 8440: case 0x0: {
4273 OPC_Decode, 233, 5, 138, 1, // 8442: decode to DCBTST using decoder 138
4274 // 8442: }
4275 2, 0, // 8447: case 0x2: {
4276 OPC_Decode, 206, 15, 137, 1, // 8449: decode to STBUX using decoder 137
4277 // 8449: }
4278 // 8449: } // switch Inst[1:0]
4279 // 8449: }
4280 8, 16, // 8454: case 0x8: {
4281 OPC_SwitchField, 0, 2, // 8456: switch Inst[1:0] {
4282 0, 5, // 8459: case 0x0: {
4283 OPC_Decode, 231, 5, 138, 1, // 8461: decode to DCBT using decoder 138
4284 // 8461: }
4285 2, 0, // 8466: case 0x2: {
4286 OPC_Decode, 131, 11, 127, // 8468: decode to LHZX using decoder 127
4287 // 8468: }
4288 // 8468: } // switch Inst[1:0]
4289 // 8468: }
4290 9, 9, // 8472: case 0x9: {
4291 OPC_CheckField, 0, 2, 2, // 8474: check Inst[1:0] == 0x2
4292 OPC_Decode, 129, 11, 135, 1, // 8478: decode to LHZUX using decoder 135
4293 // 8478: }
4294 10, 28, // 8483: case 0xa: {
4295 OPC_SwitchField, 0, 2, // 8485: switch Inst[1:0] {
4296 0, 17, // 8488: case 0x0: {
4297 OPC_SwitchField, 23, 3, // 8490: switch Inst[25:23] {
4298 0, 5, // 8493: case 0x0: {
4299 OPC_Decode, 242, 6, 139, 1, // 8495: decode to DST using decoder 139
4300 // 8495: }
4301 4, 0, // 8500: case 0x4: {
4302 OPC_Decode, 248, 6, 139, 1, // 8502: decode to DSTT using decoder 139
4303 // 8502: }
4304 // 8502: } // switch Inst[25:23]
4305 // 8502: }
4306 2, 0, // 8507: case 0x2: {
4307 OPC_Decode, 244, 10, 127, // 8509: decode to LHAX using decoder 127
4308 // 8509: }
4309 // 8509: } // switch Inst[1:0]
4310 // 8509: }
4311 11, 29, // 8513: case 0xb: {
4312 OPC_SwitchField, 0, 2, // 8515: switch Inst[1:0] {
4313 0, 17, // 8518: case 0x0: {
4314 OPC_SwitchField, 23, 3, // 8520: switch Inst[25:23] {
4315 0, 5, // 8523: case 0x0: {
4316 OPC_Decode, 244, 6, 139, 1, // 8525: decode to DSTST using decoder 139
4317 // 8525: }
4318 4, 0, // 8530: case 0x4: {
4319 OPC_Decode, 246, 6, 139, 1, // 8532: decode to DSTSTT using decoder 139
4320 // 8532: }
4321 // 8532: } // switch Inst[25:23]
4322 // 8532: }
4323 2, 0, // 8537: case 0x2: {
4324 OPC_Decode, 242, 10, 135, 1, // 8539: decode to LHAUX using decoder 135
4325 // 8539: }
4326 // 8539: } // switch Inst[1:0]
4327 // 8539: }
4328 12, 8, // 8544: case 0xc: {
4329 OPC_CheckField, 0, 2, 2, // 8546: check Inst[1:0] == 0x2
4330 OPC_Decode, 247, 15, 127, // 8550: decode to STHX using decoder 127
4331 // 8550: }
4332 13, 9, // 8554: case 0xd: {
4333 OPC_CheckField, 0, 2, 2, // 8556: check Inst[1:0] == 0x2
4334 OPC_Decode, 245, 15, 137, 1, // 8560: decode to STHUX using decoder 137
4335 // 8560: }
4336 14, 13, // 8565: case 0xe: {
4337 OPC_CheckField, 21, 5, 0, // 8567: check Inst[25:21] == 0x0
4338 OPC_CheckField, 0, 2, 0, // 8571: check Inst[1:0] == 0x0
4339 OPC_Decode, 228, 5, 134, 1, // 8575: decode to DCBI using decoder 134
4340 // 8575: }
4341 16, 16, // 8580: case 0x10: {
4342 OPC_SwitchField, 0, 2, // 8582: switch Inst[1:0] {
4343 0, 4, // 8585: case 0x0: {
4344 OPC_Decode, 166, 11, 127, // 8587: decode to LWBRX using decoder 127
4345 // 8587: }
4346 2, 0, // 8591: case 0x2: {
4347 OPC_Decode, 233, 10, 140, 1, // 8593: decode to LFSX using decoder 140
4348 // 8593: }
4349 // 8593: } // switch Inst[1:0]
4350 // 8593: }
4351 17, 20, // 8598: case 0x11: {
4352 OPC_SwitchField, 0, 2, // 8600: switch Inst[1:0] {
4353 0, 8, // 8603: case 0x0: {
4354 OPC_CheckField, 11, 15, 0, // 8605: check Inst[25:11] == 0x0
4355 OPC_Decode, 138, 17, 0, // 8609: decode to TLBSYNC using decoder 0
4356 // 8609: }
4357 2, 0, // 8613: case 0x2: {
4358 OPC_Decode, 232, 10, 141, 1, // 8615: decode to LFSUX using decoder 141
4359 // 8615: }
4360 // 8615: } // switch Inst[1:0]
4361 // 8615: }
4362 18, 44, // 8620: case 0x12: {
4363 OPC_SwitchField, 0, 2, // 8622: switch Inst[1:0] {
4364 0, 32, // 8625: case 0x0: {
4365 OPC_CheckField, 11, 5, 0, // 8627: check Inst[15:11] == 0x0
4366 OPC_CheckField, 18, 3, 0, // 8631: check Inst[20:18] == 0x0
4367 OPC_CheckField, 24, 2, 0, // 8635: check Inst[25:24] == 0x0
4368 OPC_Scope, 13, // 8639: try {
4369 OPC_CheckField, 16, 2, 0, // 8641: check Inst[17:16] == 0x0
4370 OPC_CheckField, 23, 1, 0, // 8645: check Inst[23] == 0x0
4371 OPC_Decode, 223, 16, 142, 1, // 8649: decode to SYNC using decoder 142
4372 // 8649: } else try {
4373 OPC_Decode, 224, 16, 143, 1, // 8654: decode to SYNCP10 using decoder 143
4374 // 8654: }
4375 // 8654: }
4376 2, 0, // 8659: case 0x2: {
4377 OPC_Decode, 225, 10, 144, 1, // 8661: decode to LFDX using decoder 144
4378 // 8661: }
4379 // 8661: } // switch Inst[1:0]
4380 // 8661: }
4381 19, 9, // 8666: case 0x13: {
4382 OPC_CheckField, 0, 2, 2, // 8668: check Inst[1:0] == 0x2
4383 OPC_Decode, 224, 10, 145, 1, // 8672: decode to LFDUX using decoder 145
4384 // 8672: }
4385 20, 16, // 8677: case 0x14: {
4386 OPC_SwitchField, 0, 2, // 8679: switch Inst[1:0] {
4387 0, 4, // 8682: case 0x0: {
4388 OPC_Decode, 138, 16, 127, // 8684: decode to STWBRX using decoder 127
4389 // 8684: }
4390 2, 0, // 8688: case 0x2: {
4391 OPC_Decode, 234, 15, 140, 1, // 8690: decode to STFSX using decoder 140
4392 // 8690: }
4393 // 8690: } // switch Inst[1:0]
4394 // 8690: }
4395 21, 16, // 8695: case 0x15: {
4396 OPC_SwitchField, 0, 2, // 8697: switch Inst[1:0] {
4397 1, 4, // 8700: case 0x1: {
4398 OPC_Decode, 202, 15, 127, // 8702: decode to STBCX using decoder 127
4399 // 8702: }
4400 2, 0, // 8706: case 0x2: {
4401 OPC_Decode, 233, 15, 146, 1, // 8708: decode to STFSUX using decoder 146
4402 // 8708: }
4403 // 8708: } // switch Inst[1:0]
4404 // 8708: }
4405 22, 16, // 8713: case 0x16: {
4406 OPC_SwitchField, 0, 2, // 8715: switch Inst[1:0] {
4407 1, 4, // 8718: case 0x1: {
4408 OPC_Decode, 241, 15, 127, // 8720: decode to STHCX using decoder 127
4409 // 8720: }
4410 2, 0, // 8724: case 0x2: {
4411 OPC_Decode, 227, 15, 144, 1, // 8726: decode to STFDX using decoder 144
4412 // 8726: }
4413 // 8726: } // switch Inst[1:0]
4414 // 8726: }
4415 23, 21, // 8731: case 0x17: {
4416 OPC_SwitchField, 0, 2, // 8733: switch Inst[1:0] {
4417 0, 9, // 8736: case 0x0: {
4418 OPC_CheckField, 21, 5, 0, // 8738: check Inst[25:21] == 0x0
4419 OPC_Decode, 225, 5, 134, 1, // 8742: decode to DCBA using decoder 134
4420 // 8742: }
4421 2, 0, // 8747: case 0x2: {
4422 OPC_Decode, 226, 15, 147, 1, // 8749: decode to STFDUX using decoder 147
4423 // 8749: }
4424 // 8749: } // switch Inst[1:0]
4425 // 8749: }
4426 24, 8, // 8754: case 0x18: {
4427 OPC_CheckField, 0, 2, 0, // 8756: check Inst[1:0] == 0x0
4428 OPC_Decode, 249, 10, 127, // 8760: decode to LHBRX using decoder 127
4429 // 8760: }
4430 25, 32, // 8764: case 0x19: {
4431 OPC_SwitchField, 23, 3, // 8766: switch Inst[25:23] {
4432 0, 13, // 8769: case 0x0: {
4433 OPC_CheckField, 11, 10, 0, // 8771: check Inst[20:11] == 0x0
4434 OPC_CheckField, 0, 2, 0, // 8775: check Inst[1:0] == 0x0
4435 OPC_Decode, 240, 6, 148, 1, // 8779: decode to DSS using decoder 148
4436 // 8779: }
4437 4, 0, // 8784: case 0x4: {
4438 OPC_CheckField, 11, 12, 0, // 8786: check Inst[22:11] == 0x0
4439 OPC_CheckField, 0, 2, 0, // 8790: check Inst[1:0] == 0x0
4440 OPC_Decode, 241, 6, 0, // 8794: decode to DSSALL using decoder 0
4441 // 8794: }
4442 // 8794: } // switch Inst[25:23]
4443 // 8794: }
4444 26, 35, // 8798: case 0x1a: {
4445 OPC_SwitchField, 1, 1, // 8800: switch Inst[1] {
4446 0, 19, // 8803: case 0x0: {
4447 OPC_Scope, 12, // 8805: try {
4448 OPC_CheckField, 0, 1, 0, // 8807: check Inst[0] == 0x0
4449 OPC_CheckField, 11, 15, 0, // 8811: check Inst[25:11] == 0x0
4450 OPC_Decode, 165, 9, 0, // 8815: decode to EnforceIEIO using decoder 0
4451 // 8815: } else try {
4452 OPC_Decode, 217, 11, 149, 1, // 8819: decode to MBAR using decoder 149
4453 // 8819: }
4454 // 8819: }
4455 1, 0, // 8824: case 0x1: {
4456 OPC_CheckField, 0, 1, 0, // 8826: check Inst[0] == 0x0
4457 OPC_Decode, 228, 10, 144, 1, // 8830: decode to LFIWAX using decoder 144
4458 // 8830: }
4459 // 8830: } // switch Inst[1]
4460 // 8830: }
4461 27, 20, // 8835: case 0x1b: {
4462 OPC_SwitchField, 0, 2, // 8837: switch Inst[1:0] {
4463 0, 8, // 8840: case 0x0: {
4464 OPC_CheckField, 11, 15, 0, // 8842: check Inst[25:11] == 0x0
4465 OPC_Decode, 132, 12, 0, // 8846: decode to MSGSYNC using decoder 0
4466 // 8846: }
4467 2, 0, // 8850: case 0x2: {
4468 OPC_Decode, 229, 10, 144, 1, // 8852: decode to LFIWZX using decoder 144
4469 // 8852: }
4470 // 8852: } // switch Inst[1:0]
4471 // 8852: }
4472 28, 8, // 8857: case 0x1c: {
4473 OPC_CheckField, 0, 2, 0, // 8859: check Inst[1:0] == 0x0
4474 OPC_Decode, 239, 15, 127, // 8863: decode to STHBRX using decoder 127
4475 // 8863: }
4476 30, 21, // 8867: case 0x1e: {
4477 OPC_SwitchField, 0, 2, // 8869: switch Inst[1:0] {
4478 0, 9, // 8872: case 0x0: {
4479 OPC_CheckField, 21, 5, 0, // 8874: check Inst[25:21] == 0x0
4480 OPC_Decode, 174, 10, 134, 1, // 8878: decode to ICBI using decoder 134
4481 // 8878: }
4482 2, 0, // 8883: case 0x2: {
4483 OPC_Decode, 230, 15, 144, 1, // 8885: decode to STFIWX using decoder 144
4484 // 8885: }
4485 // 8885: } // switch Inst[1:0]
4486 // 8885: }
4487 31, 0, // 8890: case 0x1f: {
4488 OPC_SwitchField, 21, 5, // 8892: switch Inst[25:21] {
4489 0, 9, // 8895: case 0x0: {
4490 OPC_CheckField, 0, 2, 0, // 8897: check Inst[1:0] == 0x0
4491 OPC_Decode, 235, 5, 134, 1, // 8901: decode to DCBZ using decoder 134
4492 // 8901: }
4493 1, 0, // 8906: case 0x1: {
4494 OPC_CheckField, 0, 2, 0, // 8908: check Inst[1:0] == 0x0
4495 OPC_Decode, 237, 5, 134, 1, // 8912: decode to DCBZL using decoder 134
4496 // 8912: }
4497 // 8912: } // switch Inst[25:21]
4498 // 8912: }
4499 // 8912: } // switch Inst[10:6]
4500 // 8912: }
4501 12, 79, // 8917: case 0xc: {
4502 OPC_SwitchField, 6, 5, // 8919: switch Inst[10:6] {
4503 0, 17, // 8922: case 0x0: {
4504 OPC_SwitchField, 0, 2, // 8924: switch Inst[1:0] {
4505 0, 5, // 8927: case 0x0: {
4506 OPC_Decode, 163, 15, 150, 1, // 8929: decode to SLW using decoder 150
4507 // 8929: }
4508 1, 0, // 8934: case 0x1: {
4509 OPC_Decode, 166, 15, 150, 1, // 8936: decode to SLW_rec using decoder 150
4510 // 8936: }
4511 // 8936: } // switch Inst[1:0]
4512 // 8936: }
4513 16, 17, // 8941: case 0x10: {
4514 OPC_SwitchField, 0, 2, // 8943: switch Inst[1:0] {
4515 0, 5, // 8946: case 0x0: {
4516 OPC_Decode, 195, 15, 150, 1, // 8948: decode to SRW using decoder 150
4517 // 8948: }
4518 1, 0, // 8953: case 0x1: {
4519 OPC_Decode, 198, 15, 150, 1, // 8955: decode to SRW_rec using decoder 150
4520 // 8955: }
4521 // 8955: } // switch Inst[1:0]
4522 // 8955: }
4523 24, 17, // 8960: case 0x18: {
4524 OPC_SwitchField, 0, 2, // 8962: switch Inst[1:0] {
4525 0, 5, // 8965: case 0x0: {
4526 OPC_Decode, 185, 15, 150, 1, // 8967: decode to SRAW using decoder 150
4527 // 8967: }
4528 1, 0, // 8972: case 0x1: {
4529 OPC_Decode, 192, 15, 150, 1, // 8974: decode to SRAW_rec using decoder 150
4530 // 8974: }
4531 // 8974: } // switch Inst[1:0]
4532 // 8974: }
4533 25, 0, // 8979: case 0x19: {
4534 OPC_SwitchField, 0, 2, // 8981: switch Inst[1:0] {
4535 0, 5, // 8984: case 0x0: {
4536 OPC_Decode, 188, 15, 151, 1, // 8986: decode to SRAWI using decoder 151
4537 // 8986: }
4538 1, 0, // 8991: case 0x1: {
4539 OPC_Decode, 191, 15, 151, 1, // 8993: decode to SRAWI_rec using decoder 151
4540 // 8993: }
4541 // 8993: } // switch Inst[1:0]
4542 // 8993: }
4543 // 8993: } // switch Inst[10:6]
4544 // 8993: }
4545 13, 155, 3, // 8998: case 0xd: {
4546 OPC_SwitchField, 6, 5, // 9001: switch Inst[10:6] {
4547 0, 39, // 9004: case 0x0: {
4548 OPC_SwitchField, 0, 2, // 9006: switch Inst[1:0] {
4549 0, 9, // 9009: case 0x0: {
4550 OPC_CheckField, 11, 5, 0, // 9011: check Inst[15:11] == 0x0
4551 OPC_Decode, 190, 5, 152, 1, // 9015: decode to CNTLZW using decoder 152
4552 // 9015: }
4553 1, 9, // 9020: case 0x1: {
4554 OPC_CheckField, 11, 5, 0, // 9022: check Inst[15:11] == 0x0
4555 OPC_Decode, 193, 5, 152, 1, // 9026: decode to CNTLZW_rec using decoder 152
4556 // 9026: }
4557 2, 5, // 9031: case 0x2: {
4558 OPC_Decode, 161, 15, 153, 1, // 9033: decode to SLD using decoder 153
4559 // 9033: }
4560 3, 0, // 9038: case 0x3: {
4561 OPC_Decode, 162, 15, 153, 1, // 9040: decode to SLD_rec using decoder 153
4562 // 9040: }
4563 // 9040: } // switch Inst[1:0]
4564 // 9040: }
4565 1, 32, // 9045: case 0x1: {
4566 OPC_SwitchField, 0, 2, // 9047: switch Inst[1:0] {
4567 0, 9, // 9050: case 0x0: {
4568 OPC_CheckField, 11, 5, 0, // 9052: check Inst[15:11] == 0x0
4569 OPC_Decode, 187, 5, 154, 1, // 9056: decode to CNTLZD using decoder 154
4570 // 9056: }
4571 1, 9, // 9061: case 0x1: {
4572 OPC_CheckField, 11, 5, 0, // 9063: check Inst[15:11] == 0x0
4573 OPC_Decode, 189, 5, 154, 1, // 9067: decode to CNTLZD_rec using decoder 154
4574 // 9067: }
4575 2, 0, // 9072: case 0x2: {
4576 OPC_Decode, 188, 5, 155, 1, // 9074: decode to CNTLZDM using decoder 155
4577 // 9074: }
4578 // 9074: } // switch Inst[1:0]
4579 // 9074: }
4580 3, 13, // 9079: case 0x3: {
4581 OPC_CheckField, 11, 5, 0, // 9081: check Inst[15:11] == 0x0
4582 OPC_CheckField, 0, 2, 0, // 9085: check Inst[1:0] == 0x0
4583 OPC_Decode, 133, 14, 152, 1, // 9089: decode to POPCNTB using decoder 152
4584 // 9089: }
4585 4, 13, // 9094: case 0x4: {
4586 OPC_CheckField, 11, 5, 0, // 9096: check Inst[15:11] == 0x0
4587 OPC_CheckField, 0, 2, 2, // 9100: check Inst[1:0] == 0x2
4588 OPC_Decode, 166, 5, 152, 1, // 9104: decode to BRW using decoder 152
4589 // 9104: }
4590 5, 13, // 9109: case 0x5: {
4591 OPC_CheckField, 11, 5, 0, // 9111: check Inst[15:11] == 0x0
4592 OPC_CheckField, 0, 2, 2, // 9115: check Inst[1:0] == 0x2
4593 OPC_Decode, 162, 5, 154, 1, // 9119: decode to BRD using decoder 154
4594 // 9119: }
4595 6, 13, // 9124: case 0x6: {
4596 OPC_CheckField, 11, 5, 0, // 9126: check Inst[15:11] == 0x0
4597 OPC_CheckField, 0, 2, 2, // 9130: check Inst[1:0] == 0x2
4598 OPC_Decode, 163, 5, 152, 1, // 9134: decode to BRH using decoder 152
4599 // 9134: }
4600 8, 13, // 9139: case 0x8: {
4601 OPC_CheckField, 11, 5, 0, // 9141: check Inst[15:11] == 0x0
4602 OPC_CheckField, 0, 2, 0, // 9145: check Inst[1:0] == 0x0
4603 OPC_Decode, 170, 5, 152, 1, // 9149: decode to CDTBCD using decoder 152
4604 // 9149: }
4605 9, 13, // 9154: case 0x9: {
4606 OPC_CheckField, 11, 5, 0, // 9156: check Inst[15:11] == 0x0
4607 OPC_CheckField, 0, 2, 0, // 9160: check Inst[1:0] == 0x0
4608 OPC_Decode, 168, 5, 152, 1, // 9164: decode to CBCDTD using decoder 152
4609 // 9164: }
4610 11, 13, // 9169: case 0xb: {
4611 OPC_CheckField, 11, 5, 0, // 9171: check Inst[15:11] == 0x0
4612 OPC_CheckField, 0, 2, 0, // 9175: check Inst[1:0] == 0x0
4613 OPC_Decode, 136, 14, 152, 1, // 9179: decode to POPCNTW using decoder 152
4614 // 9179: }
4615 15, 13, // 9184: case 0xf: {
4616 OPC_CheckField, 11, 5, 0, // 9186: check Inst[15:11] == 0x0
4617 OPC_CheckField, 0, 2, 0, // 9190: check Inst[1:0] == 0x0
4618 OPC_Decode, 135, 14, 154, 1, // 9194: decode to POPCNTD using decoder 154
4619 // 9194: }
4620 16, 39, // 9199: case 0x10: {
4621 OPC_SwitchField, 0, 2, // 9201: switch Inst[1:0] {
4622 0, 9, // 9204: case 0x0: {
4623 OPC_CheckField, 11, 5, 0, // 9206: check Inst[15:11] == 0x0
4624 OPC_Decode, 197, 5, 152, 1, // 9210: decode to CNTTZW using decoder 152
4625 // 9210: }
4626 1, 9, // 9215: case 0x1: {
4627 OPC_CheckField, 11, 5, 0, // 9217: check Inst[15:11] == 0x0
4628 OPC_Decode, 200, 5, 152, 1, // 9221: decode to CNTTZW_rec using decoder 152
4629 // 9221: }
4630 2, 5, // 9226: case 0x2: {
4631 OPC_Decode, 193, 15, 153, 1, // 9228: decode to SRD using decoder 153
4632 // 9228: }
4633 3, 0, // 9233: case 0x3: {
4634 OPC_Decode, 194, 15, 153, 1, // 9235: decode to SRD_rec using decoder 153
4635 // 9235: }
4636 // 9235: } // switch Inst[1:0]
4637 // 9235: }
4638 17, 32, // 9240: case 0x11: {
4639 OPC_SwitchField, 0, 2, // 9242: switch Inst[1:0] {
4640 0, 9, // 9245: case 0x0: {
4641 OPC_CheckField, 11, 5, 0, // 9247: check Inst[15:11] == 0x0
4642 OPC_Decode, 194, 5, 154, 1, // 9251: decode to CNTTZD using decoder 154
4643 // 9251: }
4644 1, 9, // 9256: case 0x1: {
4645 OPC_CheckField, 11, 5, 0, // 9258: check Inst[15:11] == 0x0
4646 OPC_Decode, 196, 5, 154, 1, // 9262: decode to CNTTZD_rec using decoder 154
4647 // 9262: }
4648 2, 0, // 9267: case 0x2: {
4649 OPC_Decode, 195, 5, 155, 1, // 9269: decode to CNTTZDM using decoder 155
4650 // 9269: }
4651 // 9269: } // switch Inst[1:0]
4652 // 9269: }
4653 24, 17, // 9274: case 0x18: {
4654 OPC_SwitchField, 0, 2, // 9276: switch Inst[1:0] {
4655 0, 5, // 9279: case 0x0: {
4656 OPC_Decode, 180, 15, 153, 1, // 9281: decode to SRAD using decoder 153
4657 // 9281: }
4658 1, 0, // 9286: case 0x1: {
4659 OPC_Decode, 184, 15, 153, 1, // 9288: decode to SRAD_rec using decoder 153
4660 // 9288: }
4661 // 9288: } // switch Inst[1:0]
4662 // 9288: }
4663 25, 17, // 9293: case 0x19: {
4664 OPC_SwitchField, 0, 1, // 9295: switch Inst[0] {
4665 0, 5, // 9298: case 0x0: {
4666 OPC_Decode, 181, 15, 156, 1, // 9300: decode to SRADI using decoder 156
4667 // 9300: }
4668 1, 0, // 9305: case 0x1: {
4669 OPC_Decode, 183, 15, 156, 1, // 9307: decode to SRADI_rec using decoder 156
4670 // 9307: }
4671 // 9307: } // switch Inst[0]
4672 // 9307: }
4673 27, 17, // 9312: case 0x1b: {
4674 OPC_SwitchField, 0, 1, // 9314: switch Inst[0] {
4675 0, 5, // 9317: case 0x0: {
4676 OPC_Decode, 157, 9, 156, 1, // 9319: decode to EXTSWSLI using decoder 156
4677 // 9319: }
4678 1, 0, // 9324: case 0x1: {
4679 OPC_Decode, 160, 9, 156, 1, // 9326: decode to EXTSWSLI_rec using decoder 156
4680 // 9326: }
4681 // 9326: } // switch Inst[0]
4682 // 9326: }
4683 28, 25, // 9331: case 0x1c: {
4684 OPC_SwitchField, 0, 2, // 9333: switch Inst[1:0] {
4685 0, 9, // 9336: case 0x0: {
4686 OPC_CheckField, 11, 5, 0, // 9338: check Inst[15:11] == 0x0
4687 OPC_Decode, 151, 9, 152, 1, // 9342: decode to EXTSH using decoder 152
4688 // 9342: }
4689 1, 0, // 9347: case 0x1: {
4690 OPC_CheckField, 11, 5, 0, // 9349: check Inst[15:11] == 0x0
4691 OPC_Decode, 155, 9, 152, 1, // 9353: decode to EXTSH_rec using decoder 152
4692 // 9353: }
4693 // 9353: } // switch Inst[1:0]
4694 // 9353: }
4695 29, 25, // 9358: case 0x1d: {
4696 OPC_SwitchField, 0, 2, // 9360: switch Inst[1:0] {
4697 0, 9, // 9363: case 0x0: {
4698 OPC_CheckField, 11, 5, 0, // 9365: check Inst[15:11] == 0x0
4699 OPC_Decode, 146, 9, 152, 1, // 9369: decode to EXTSB using decoder 152
4700 // 9369: }
4701 1, 0, // 9374: case 0x1: {
4702 OPC_CheckField, 11, 5, 0, // 9376: check Inst[15:11] == 0x0
4703 OPC_Decode, 150, 9, 152, 1, // 9380: decode to EXTSB_rec using decoder 152
4704 // 9380: }
4705 // 9380: } // switch Inst[1:0]
4706 // 9380: }
4707 30, 0, // 9385: case 0x1e: {
4708 OPC_SwitchField, 0, 2, // 9387: switch Inst[1:0] {
4709 0, 9, // 9390: case 0x0: {
4710 OPC_CheckField, 11, 5, 0, // 9392: check Inst[15:11] == 0x0
4711 OPC_Decode, 156, 9, 154, 1, // 9396: decode to EXTSW using decoder 154
4712 // 9396: }
4713 1, 0, // 9401: case 0x1: {
4714 OPC_CheckField, 11, 5, 0, // 9403: check Inst[15:11] == 0x0
4715 OPC_Decode, 164, 9, 154, 1, // 9407: decode to EXTSW_rec using decoder 154
4716 // 9407: }
4717 // 9407: } // switch Inst[1:0]
4718 // 9407: }
4719 // 9407: } // switch Inst[10:6]
4720 // 9407: }
4721 14, 210, 1, // 9412: case 0xe: {
4722 OPC_SwitchField, 6, 5, // 9415: switch Inst[10:6] {
4723 0, 17, // 9418: case 0x0: {
4724 OPC_SwitchField, 0, 2, // 9420: switch Inst[1:0] {
4725 0, 5, // 9423: case 0x0: {
4726 OPC_Decode, 234, 3, 150, 1, // 9425: decode to AND using decoder 150
4727 // 9425: }
4728 1, 0, // 9430: case 0x1: {
4729 OPC_Decode, 249, 3, 150, 1, // 9432: decode to AND_rec using decoder 150
4730 // 9432: }
4731 // 9432: } // switch Inst[1:0]
4732 // 9432: }
4733 1, 17, // 9437: case 0x1: {
4734 OPC_SwitchField, 0, 2, // 9439: switch Inst[1:0] {
4735 0, 5, // 9442: case 0x0: {
4736 OPC_Decode, 237, 3, 150, 1, // 9444: decode to ANDC using decoder 150
4737 // 9444: }
4738 1, 0, // 9449: case 0x1: {
4739 OPC_Decode, 240, 3, 150, 1, // 9451: decode to ANDC_rec using decoder 150
4740 // 9451: }
4741 // 9451: } // switch Inst[1:0]
4742 // 9451: }
4743 3, 17, // 9456: case 0x3: {
4744 OPC_SwitchField, 0, 2, // 9458: switch Inst[1:0] {
4745 0, 5, // 9461: case 0x0: {
4746 OPC_Decode, 217, 12, 150, 1, // 9463: decode to NOR using decoder 150
4747 // 9463: }
4748 1, 0, // 9468: case 0x1: {
4749 OPC_Decode, 220, 12, 150, 1, // 9470: decode to NOR_rec using decoder 150
4750 // 9470: }
4751 // 9470: } // switch Inst[1:0]
4752 // 9470: }
4753 4, 9, // 9475: case 0x4: {
4754 OPC_CheckField, 0, 2, 0, // 9477: check Inst[1:0] == 0x0
4755 OPC_Decode, 242, 12, 155, 1, // 9481: decode to PDEPD using decoder 155
4756 // 9481: }
4757 5, 9, // 9486: case 0x5: {
4758 OPC_CheckField, 0, 2, 0, // 9488: check Inst[1:0] == 0x0
4759 OPC_Decode, 243, 12, 155, 1, // 9492: decode to PEXTD using decoder 155
4760 // 9492: }
4761 6, 9, // 9497: case 0x6: {
4762 OPC_CheckField, 0, 2, 0, // 9499: check Inst[1:0] == 0x0
4763 OPC_Decode, 172, 5, 155, 1, // 9503: decode to CFUGED using decoder 155
4764 // 9503: }
4765 7, 9, // 9508: case 0x7: {
4766 OPC_CheckField, 0, 2, 0, // 9510: check Inst[1:0] == 0x0
4767 OPC_Decode, 161, 5, 155, 1, // 9514: decode to BPERMD using decoder 155
4768 // 9514: }
4769 8, 17, // 9519: case 0x8: {
4770 OPC_SwitchField, 0, 2, // 9521: switch Inst[1:0] {
4771 0, 5, // 9524: case 0x0: {
4772 OPC_Decode, 203, 7, 150, 1, // 9526: decode to EQV using decoder 150
4773 // 9526: }
4774 1, 0, // 9531: case 0x1: {
4775 OPC_Decode, 206, 7, 150, 1, // 9533: decode to EQV_rec using decoder 150
4776 // 9533: }
4777 // 9533: } // switch Inst[1:0]
4778 // 9533: }
4779 9, 17, // 9538: case 0x9: {
4780 OPC_SwitchField, 0, 2, // 9540: switch Inst[1:0] {
4781 0, 5, // 9543: case 0x0: {
4782 OPC_Decode, 177, 20, 150, 1, // 9545: decode to XOR using decoder 150
4783 // 9545: }
4784 1, 0, // 9550: case 0x1: {
4785 OPC_Decode, 184, 20, 150, 1, // 9552: decode to XOR_rec using decoder 150
4786 // 9552: }
4787 // 9552: } // switch Inst[1:0]
4788 // 9552: }
4789 12, 17, // 9557: case 0xc: {
4790 OPC_SwitchField, 0, 2, // 9559: switch Inst[1:0] {
4791 0, 5, // 9562: case 0x0: {
4792 OPC_Decode, 224, 12, 150, 1, // 9564: decode to ORC using decoder 150
4793 // 9564: }
4794 1, 0, // 9569: case 0x1: {
4795 OPC_Decode, 227, 12, 150, 1, // 9571: decode to ORC_rec using decoder 150
4796 // 9571: }
4797 // 9571: } // switch Inst[1:0]
4798 // 9571: }
4799 13, 17, // 9576: case 0xd: {
4800 OPC_SwitchField, 0, 2, // 9578: switch Inst[1:0] {
4801 0, 5, // 9581: case 0x0: {
4802 OPC_Decode, 221, 12, 150, 1, // 9583: decode to OR using decoder 150
4803 // 9583: }
4804 1, 0, // 9588: case 0x1: {
4805 OPC_Decode, 232, 12, 150, 1, // 9590: decode to OR_rec using decoder 150
4806 // 9590: }
4807 // 9590: } // switch Inst[1:0]
4808 // 9590: }
4809 14, 17, // 9595: case 0xe: {
4810 OPC_SwitchField, 0, 2, // 9597: switch Inst[1:0] {
4811 0, 5, // 9600: case 0x0: {
4812 OPC_Decode, 201, 12, 150, 1, // 9602: decode to NAND using decoder 150
4813 // 9602: }
4814 1, 0, // 9607: case 0x1: {
4815 OPC_Decode, 204, 12, 150, 1, // 9609: decode to NAND_rec using decoder 150
4816 // 9609: }
4817 // 9609: } // switch Inst[1:0]
4818 // 9609: }
4819 15, 0, // 9614: case 0xf: {
4820 OPC_CheckField, 0, 2, 0, // 9616: check Inst[1:0] == 0x0
4821 OPC_Decode, 174, 5, 150, 1, // 9620: decode to CMPB using decoder 150
4822 // 9620: }
4823 // 9620: } // switch Inst[10:6]
4824 // 9620: }
4825 15, 0, // 9625: case 0xf: {
4826 OPC_SwitchField, 6, 5, // 9627: switch Inst[10:6] {
4827 0, 39, // 9630: case 0x0: {
4828 OPC_SwitchField, 0, 2, // 9632: switch Inst[1:0] {
4829 0, 28, // 9635: case 0x0: {
4830 OPC_CheckField, 11, 5, 0, // 9637: check Inst[15:11] == 0x0
4831 OPC_CheckField, 18, 3, 0, // 9641: check Inst[20:18] == 0x0
4832 OPC_CheckField, 23, 3, 0, // 9645: check Inst[25:23] == 0x0
4833 OPC_Scope, 9, // 9649: try {
4834 OPC_CheckField, 16, 2, 0, // 9651: check Inst[17:16] == 0x0
4835 OPC_Decode, 173, 20, 142, 1, // 9655: decode to WAIT using decoder 142
4836 // 9655: } else try {
4837 OPC_Decode, 174, 20, 157, 1, // 9660: decode to WAITP10 using decoder 157
4838 // 9660: }
4839 // 9660: }
4840 2, 0, // 9665: case 0x2: {
4841 OPC_Decode, 168, 11, 127, // 9667: decode to LWEPX using decoder 127
4842 // 9667: }
4843 // 9667: } // switch Inst[1:0]
4844 // 9667: }
4845 1, 13, // 9671: case 0x1: {
4846 OPC_CheckField, 21, 5, 0, // 9673: check Inst[25:21] == 0x0
4847 OPC_CheckField, 0, 2, 2, // 9677: check Inst[1:0] == 0x2
4848 OPC_Decode, 230, 5, 134, 1, // 9681: decode to DCBSTEP using decoder 134
4849 // 9681: }
4850 2, 8, // 9686: case 0x2: {
4851 OPC_CheckField, 0, 2, 2, // 9688: check Inst[1:0] == 0x2
4852 OPC_Decode, 188, 10, 127, // 9692: decode to LBEPX using decoder 127
4853 // 9692: }
4854 3, 13, // 9696: case 0x3: {
4855 OPC_CheckField, 21, 5, 0, // 9698: check Inst[25:21] == 0x0
4856 OPC_CheckField, 0, 2, 2, // 9702: check Inst[1:0] == 0x2
4857 OPC_Decode, 227, 5, 134, 1, // 9706: decode to DCBFEP using decoder 134
4858 // 9706: }
4859 4, 8, // 9711: case 0x4: {
4860 OPC_CheckField, 0, 2, 2, // 9713: check Inst[1:0] == 0x2
4861 OPC_Decode, 141, 16, 127, // 9717: decode to STWEPX using decoder 127
4862 // 9717: }
4863 6, 8, // 9721: case 0x6: {
4864 OPC_CheckField, 0, 2, 2, // 9723: check Inst[1:0] == 0x2
4865 OPC_Decode, 203, 15, 127, // 9727: decode to STBEPX using decoder 127
4866 // 9727: }
4867 7, 9, // 9731: case 0x7: {
4868 OPC_CheckField, 0, 2, 2, // 9733: check Inst[1:0] == 0x2
4869 OPC_Decode, 234, 5, 158, 1, // 9737: decode to DCBTSTEP using decoder 158
4870 // 9737: }
4871 8, 8, // 9742: case 0x8: {
4872 OPC_CheckField, 0, 2, 2, // 9744: check Inst[1:0] == 0x2
4873 OPC_Decode, 251, 10, 127, // 9748: decode to LHEPX using decoder 127
4874 // 9748: }
4875 9, 9, // 9752: case 0x9: {
4876 OPC_CheckField, 0, 2, 2, // 9754: check Inst[1:0] == 0x2
4877 OPC_Decode, 232, 5, 158, 1, // 9758: decode to DCBTEP using decoder 158
4878 // 9758: }
4879 12, 8, // 9763: case 0xc: {
4880 OPC_CheckField, 0, 2, 2, // 9765: check Inst[1:0] == 0x2
4881 OPC_Decode, 242, 15, 127, // 9769: decode to STHEPX using decoder 127
4882 // 9769: }
4883 18, 9, // 9773: case 0x12: {
4884 OPC_CheckField, 0, 2, 2, // 9775: check Inst[1:0] == 0x2
4885 OPC_Decode, 222, 10, 144, 1, // 9779: decode to LFDEPX using decoder 144
4886 // 9779: }
4887 22, 9, // 9784: case 0x16: {
4888 OPC_CheckField, 0, 2, 2, // 9786: check Inst[1:0] == 0x2
4889 OPC_Decode, 224, 15, 144, 1, // 9790: decode to STFDEPX using decoder 144
4890 // 9790: }
4891 30, 13, // 9795: case 0x1e: {
4892 OPC_CheckField, 21, 5, 0, // 9797: check Inst[25:21] == 0x0
4893 OPC_CheckField, 0, 2, 2, // 9801: check Inst[1:0] == 0x2
4894 OPC_Decode, 175, 10, 134, 1, // 9805: decode to ICBIEP using decoder 134
4895 // 9805: }
4896 31, 0, // 9810: case 0x1f: {
4897 OPC_SwitchField, 21, 5, // 9812: switch Inst[25:21] {
4898 0, 9, // 9815: case 0x0: {
4899 OPC_CheckField, 0, 2, 2, // 9817: check Inst[1:0] == 0x2
4900 OPC_Decode, 236, 5, 134, 1, // 9821: decode to DCBZEP using decoder 134
4901 // 9821: }
4902 1, 0, // 9826: case 0x1: {
4903 OPC_CheckField, 0, 2, 2, // 9828: check Inst[1:0] == 0x2
4904 OPC_Decode, 238, 5, 134, 1, // 9832: decode to DCBZLEP using decoder 134
4905 // 9832: }
4906 // 9832: } // switch Inst[25:21]
4907 // 9832: }
4908 // 9832: } // switch Inst[10:6]
4909 // 9832: }
4910 // 9832: } // switch Inst[5:2]
4911 // 9832: }
4912 32, 5, // 9837: case 0x20: {
4913 OPC_Decode, 169, 11, 159, 1, // 9839: decode to LWZ using decoder 159
4914 // 9839: }
4915 33, 5, // 9844: case 0x21: {
4916 OPC_Decode, 172, 11, 160, 1, // 9846: decode to LWZU using decoder 160
4917 // 9846: }
4918 34, 5, // 9851: case 0x22: {
4919 OPC_Decode, 189, 10, 159, 1, // 9853: decode to LBZ using decoder 159
4920 // 9853: }
4921 35, 5, // 9858: case 0x23: {
4922 OPC_Decode, 192, 10, 160, 1, // 9860: decode to LBZU using decoder 160
4923 // 9860: }
4924 36, 5, // 9865: case 0x24: {
4925 OPC_Decode, 135, 16, 159, 1, // 9867: decode to STW using decoder 159
4926 // 9867: }
4927 37, 5, // 9872: case 0x25: {
4928 OPC_Decode, 142, 16, 161, 1, // 9874: decode to STWU using decoder 161
4929 // 9874: }
4930 38, 5, // 9879: case 0x26: {
4931 OPC_Decode, 199, 15, 159, 1, // 9881: decode to STB using decoder 159
4932 // 9881: }
4933 39, 5, // 9886: case 0x27: {
4934 OPC_Decode, 204, 15, 161, 1, // 9888: decode to STBU using decoder 161
4935 // 9888: }
4936 40, 5, // 9893: case 0x28: {
4937 OPC_Decode, 252, 10, 159, 1, // 9895: decode to LHZ using decoder 159
4938 // 9895: }
4939 41, 5, // 9900: case 0x29: {
4940 OPC_Decode, 255, 10, 160, 1, // 9902: decode to LHZU using decoder 160
4941 // 9902: }
4942 42, 5, // 9907: case 0x2a: {
4943 OPC_Decode, 236, 10, 159, 1, // 9909: decode to LHA using decoder 159
4944 // 9909: }
4945 43, 5, // 9914: case 0x2b: {
4946 OPC_Decode, 240, 10, 160, 1, // 9916: decode to LHAU using decoder 160
4947 // 9916: }
4948 44, 5, // 9921: case 0x2c: {
4949 OPC_Decode, 237, 15, 159, 1, // 9923: decode to STH using decoder 159
4950 // 9923: }
4951 45, 5, // 9928: case 0x2d: {
4952 OPC_Decode, 243, 15, 161, 1, // 9930: decode to STHU using decoder 161
4953 // 9930: }
4954 46, 5, // 9935: case 0x2e: {
4955 OPC_Decode, 140, 11, 159, 1, // 9937: decode to LMW using decoder 159
4956 // 9937: }
4957 47, 5, // 9942: case 0x2f: {
4958 OPC_Decode, 252, 15, 159, 1, // 9944: decode to STMW using decoder 159
4959 // 9944: }
4960 48, 5, // 9949: case 0x30: {
4961 OPC_Decode, 230, 10, 162, 1, // 9951: decode to LFS using decoder 162
4962 // 9951: }
4963 49, 5, // 9956: case 0x31: {
4964 OPC_Decode, 231, 10, 163, 1, // 9958: decode to LFSU using decoder 163
4965 // 9958: }
4966 50, 5, // 9963: case 0x32: {
4967 OPC_Decode, 221, 10, 164, 1, // 9965: decode to LFD using decoder 164
4968 // 9965: }
4969 51, 5, // 9970: case 0x33: {
4970 OPC_Decode, 223, 10, 165, 1, // 9972: decode to LFDU using decoder 165
4971 // 9972: }
4972 52, 5, // 9977: case 0x34: {
4973 OPC_Decode, 231, 15, 162, 1, // 9979: decode to STFS using decoder 162
4974 // 9979: }
4975 53, 5, // 9984: case 0x35: {
4976 OPC_Decode, 232, 15, 166, 1, // 9986: decode to STFSU using decoder 166
4977 // 9986: }
4978 54, 5, // 9991: case 0x36: {
4979 OPC_Decode, 223, 15, 164, 1, // 9993: decode to STFD using decoder 164
4980 // 9993: }
4981 55, 5, // 9998: case 0x37: {
4982 OPC_Decode, 225, 15, 167, 1, // 10000: decode to STFDU using decoder 167
4983 // 10000: }
4984 56, 9, // 10005: case 0x38: {
4985 OPC_CheckField, 0, 4, 0, // 10007: check Inst[3:0] == 0x0
4986 OPC_Decode, 141, 11, 168, 1, // 10011: decode to LQ using decoder 168
4987 // 10011: }
4988 57, 17, // 10016: case 0x39: {
4989 OPC_SwitchField, 0, 2, // 10018: switch Inst[1:0] {
4990 2, 5, // 10021: case 0x2: {
4991 OPC_Decode, 183, 11, 169, 1, // 10023: decode to LXSD using decoder 169
4992 // 10023: }
4993 3, 0, // 10028: case 0x3: {
4994 OPC_Decode, 189, 11, 169, 1, // 10030: decode to LXSSP using decoder 169
4995 // 10030: }
4996 // 10030: } // switch Inst[1:0]
4997 // 10030: }
4998 58, 24, // 10035: case 0x3a: {
4999 OPC_SwitchField, 0, 2, // 10037: switch Inst[1:0] {
5000 0, 5, // 10040: case 0x0: {
5001 OPC_Decode, 201, 10, 170, 1, // 10042: decode to LD using decoder 170
5002 // 10042: }
5003 1, 5, // 10047: case 0x1: {
5004 OPC_Decode, 209, 10, 171, 1, // 10049: decode to LDU using decoder 171
5005 // 10049: }
5006 2, 0, // 10054: case 0x2: {
5007 OPC_Decode, 153, 11, 170, 1, // 10056: decode to LWA using decoder 170
5008 // 10056: }
5009 // 10056: } // switch Inst[1:0]
5010 // 10056: }
5011 59, 190, 13, // 10061: case 0x3b: {
5012 OPC_SwitchField, 3, 3, // 10064: switch Inst[5:3] {
5013 0, 206, 4, // 10067: case 0x0: {
5014 OPC_SwitchField, 6, 3, // 10070: switch Inst[8:6] {
5015 0, 99, // 10073: case 0x0: {
5016 OPC_SwitchField, 0, 3, // 10075: switch Inst[2:0] {
5017 4, 39, // 10078: case 0x4: {
5018 OPC_SwitchField, 9, 2, // 10080: switch Inst[10:9] {
5019 0, 5, // 10083: case 0x0: {
5020 OPC_Decode, 220, 5, 172, 1, // 10085: decode to DADD using decoder 172
5021 // 10085: }
5022 1, 9, // 10090: case 0x1: {
5023 OPC_CheckField, 16, 5, 0, // 10092: check Inst[20:16] == 0x0
5024 OPC_Decode, 249, 5, 173, 1, // 10096: decode to DCTDP using decoder 173
5025 // 10096: }
5026 2, 5, // 10101: case 0x2: {
5027 OPC_Decode, 250, 6, 172, 1, // 10103: decode to DSUB using decoder 172
5028 // 10103: }
5029 3, 0, // 10108: case 0x3: {
5030 OPC_CheckField, 16, 5, 0, // 10110: check Inst[20:16] == 0x0
5031 OPC_Decode, 230, 6, 173, 1, // 10114: decode to DRSP using decoder 173
5032 // 10114: }
5033 // 10114: } // switch Inst[10:9]
5034 // 10114: }
5035 5, 39, // 10119: case 0x5: {
5036 OPC_SwitchField, 9, 2, // 10121: switch Inst[10:9] {
5037 0, 5, // 10124: case 0x0: {
5038 OPC_Decode, 223, 5, 172, 1, // 10126: decode to DADD_rec using decoder 172
5039 // 10126: }
5040 1, 9, // 10131: case 0x1: {
5041 OPC_CheckField, 16, 5, 0, // 10133: check Inst[20:16] == 0x0
5042 OPC_Decode, 250, 5, 173, 1, // 10137: decode to DCTDP_rec using decoder 173
5043 // 10137: }
5044 2, 5, // 10142: case 0x2: {
5045 OPC_Decode, 253, 6, 172, 1, // 10144: decode to DSUB_rec using decoder 172
5046 // 10144: }
5047 3, 0, // 10149: case 0x3: {
5048 OPC_CheckField, 16, 5, 0, // 10151: check Inst[20:16] == 0x0
5049 OPC_Decode, 231, 6, 173, 1, // 10155: decode to DRSP_rec using decoder 173
5050 // 10155: }
5051 // 10155: } // switch Inst[10:9]
5052 // 10155: }
5053 6, 5, // 10160: case 0x6: {
5054 OPC_Decode, 208, 6, 174, 1, // 10162: decode to DQUA using decoder 174
5055 // 10162: }
5056 7, 0, // 10167: case 0x7: {
5057 OPC_Decode, 215, 6, 174, 1, // 10169: decode to DQUA_rec using decoder 174
5058 // 10169: }
5059 // 10169: } // switch Inst[2:0]
5060 // 10169: }
5061 1, 99, // 10174: case 0x1: {
5062 OPC_SwitchField, 0, 3, // 10176: switch Inst[2:0] {
5063 4, 39, // 10179: case 0x4: {
5064 OPC_SwitchField, 9, 2, // 10181: switch Inst[10:9] {
5065 0, 5, // 10184: case 0x0: {
5066 OPC_Decode, 182, 6, 172, 1, // 10186: decode to DMUL using decoder 172
5067 // 10186: }
5068 1, 9, // 10191: case 0x1: {
5069 OPC_CheckField, 16, 5, 0, // 10193: check Inst[20:16] == 0x0
5070 OPC_Decode, 251, 5, 173, 1, // 10197: decode to DCTFIX using decoder 173
5071 // 10197: }
5072 2, 5, // 10202: case 0x2: {
5073 OPC_Decode, 134, 6, 172, 1, // 10204: decode to DDIV using decoder 172
5074 // 10204: }
5075 3, 0, // 10209: case 0x3: {
5076 OPC_CheckField, 16, 5, 0, // 10211: check Inst[20:16] == 0x0
5077 OPC_Decode, 240, 5, 173, 1, // 10215: decode to DCFFIX using decoder 173
5078 // 10215: }
5079 // 10215: } // switch Inst[10:9]
5080 // 10215: }
5081 5, 39, // 10220: case 0x5: {
5082 OPC_SwitchField, 9, 2, // 10222: switch Inst[10:9] {
5083 0, 5, // 10225: case 0x0: {
5084 OPC_Decode, 185, 6, 172, 1, // 10227: decode to DMUL_rec using decoder 172
5085 // 10227: }
5086 1, 9, // 10232: case 0x1: {
5087 OPC_CheckField, 16, 5, 0, // 10234: check Inst[20:16] == 0x0
5088 OPC_Decode, 255, 5, 173, 1, // 10238: decode to DCTFIX_rec using decoder 173
5089 // 10238: }
5090 2, 5, // 10243: case 0x2: {
5091 OPC_Decode, 137, 6, 172, 1, // 10245: decode to DDIV_rec using decoder 172
5092 // 10245: }
5093 3, 0, // 10250: case 0x3: {
5094 OPC_CheckField, 16, 5, 0, // 10252: check Inst[20:16] == 0x0
5095 OPC_Decode, 244, 5, 173, 1, // 10256: decode to DCFFIX_rec using decoder 173
5096 // 10256: }
5097 // 10256: } // switch Inst[10:9]
5098 // 10256: }
5099 6, 5, // 10261: case 0x6: {
5100 OPC_Decode, 226, 6, 174, 1, // 10263: decode to DRRND using decoder 174
5101 // 10263: }
5102 7, 0, // 10268: case 0x7: {
5103 OPC_Decode, 229, 6, 174, 1, // 10270: decode to DRRND_rec using decoder 174
5104 // 10270: }
5105 // 10270: } // switch Inst[2:0]
5106 // 10270: }
5107 2, 95, // 10275: case 0x2: {
5108 OPC_SwitchField, 0, 3, // 10277: switch Inst[2:0] {
5109 4, 37, // 10280: case 0x4: {
5110 OPC_SwitchField, 9, 1, // 10282: switch Inst[9] {
5111 0, 5, // 10285: case 0x0: {
5112 OPC_Decode, 232, 6, 175, 1, // 10287: decode to DSCLI using decoder 175
5113 // 10287: }
5114 1, 0, // 10292: case 0x1: {
5115 OPC_SwitchField, 10, 1, // 10294: switch Inst[10] {
5116 0, 9, // 10297: case 0x0: {
5117 OPC_CheckField, 16, 3, 0, // 10299: check Inst[18:16] == 0x0
5118 OPC_Decode, 130, 6, 176, 1, // 10303: decode to DDEDPD using decoder 176
5119 // 10303: }
5120 1, 0, // 10308: case 0x1: {
5121 OPC_CheckField, 16, 4, 0, // 10310: check Inst[19:16] == 0x0
5122 OPC_Decode, 138, 6, 177, 1, // 10314: decode to DENBCD using decoder 177
5123 // 10314: }
5124 // 10314: } // switch Inst[10]
5125 // 10314: }
5126 // 10314: } // switch Inst[9]
5127 // 10314: }
5128 5, 37, // 10319: case 0x5: {
5129 OPC_SwitchField, 9, 1, // 10321: switch Inst[9] {
5130 0, 5, // 10324: case 0x0: {
5131 OPC_Decode, 235, 6, 175, 1, // 10326: decode to DSCLI_rec using decoder 175
5132 // 10326: }
5133 1, 0, // 10331: case 0x1: {
5134 OPC_SwitchField, 10, 1, // 10333: switch Inst[10] {
5135 0, 9, // 10336: case 0x0: {
5136 OPC_CheckField, 16, 3, 0, // 10338: check Inst[18:16] == 0x0
5137 OPC_Decode, 133, 6, 176, 1, // 10342: decode to DDEDPD_rec using decoder 176
5138 // 10342: }
5139 1, 0, // 10347: case 0x1: {
5140 OPC_CheckField, 16, 4, 0, // 10349: check Inst[19:16] == 0x0
5141 OPC_Decode, 141, 6, 177, 1, // 10353: decode to DENBCD_rec using decoder 177
5142 // 10353: }
5143 // 10353: } // switch Inst[10]
5144 // 10353: }
5145 // 10353: } // switch Inst[9]
5146 // 10353: }
5147 6, 5, // 10358: case 0x6: {
5148 OPC_Decode, 209, 6, 178, 1, // 10360: decode to DQUAI using decoder 178
5149 // 10360: }
5150 7, 0, // 10365: case 0x7: {
5151 OPC_Decode, 212, 6, 178, 1, // 10367: decode to DQUAI_rec using decoder 178
5152 // 10367: }
5153 // 10367: } // switch Inst[2:0]
5154 // 10367: }
5155 3, 95, // 10372: case 0x3: {
5156 OPC_SwitchField, 0, 3, // 10374: switch Inst[2:0] {
5157 4, 33, // 10377: case 0x4: {
5158 OPC_SwitchField, 9, 1, // 10379: switch Inst[9] {
5159 0, 5, // 10382: case 0x0: {
5160 OPC_Decode, 236, 6, 175, 1, // 10384: decode to DSCRI using decoder 175
5161 // 10384: }
5162 1, 0, // 10389: case 0x1: {
5163 OPC_SwitchField, 10, 1, // 10391: switch Inst[10] {
5164 0, 9, // 10394: case 0x0: {
5165 OPC_CheckField, 16, 5, 0, // 10396: check Inst[20:16] == 0x0
5166 OPC_Decode, 136, 7, 173, 1, // 10400: decode to DXEX using decoder 173
5167 // 10400: }
5168 1, 0, // 10405: case 0x1: {
5169 OPC_Decode, 142, 6, 172, 1, // 10407: decode to DIEX using decoder 172
5170 // 10407: }
5171 // 10407: } // switch Inst[10]
5172 // 10407: }
5173 // 10407: } // switch Inst[9]
5174 // 10407: }
5175 5, 33, // 10412: case 0x5: {
5176 OPC_SwitchField, 9, 1, // 10414: switch Inst[9] {
5177 0, 5, // 10417: case 0x0: {
5178 OPC_Decode, 239, 6, 175, 1, // 10419: decode to DSCRI_rec using decoder 175
5179 // 10419: }
5180 1, 0, // 10424: case 0x1: {
5181 OPC_SwitchField, 10, 1, // 10426: switch Inst[10] {
5182 0, 9, // 10429: case 0x0: {
5183 OPC_CheckField, 16, 5, 0, // 10431: check Inst[20:16] == 0x0
5184 OPC_Decode, 139, 7, 173, 1, // 10435: decode to DXEX_rec using decoder 173
5185 // 10435: }
5186 1, 0, // 10440: case 0x1: {
5187 OPC_Decode, 145, 6, 172, 1, // 10442: decode to DIEX_rec using decoder 172
5188 // 10442: }
5189 // 10442: } // switch Inst[10]
5190 // 10442: }
5191 // 10442: } // switch Inst[9]
5192 // 10442: }
5193 6, 9, // 10447: case 0x6: {
5194 OPC_CheckField, 17, 4, 0, // 10449: check Inst[20:17] == 0x0
5195 OPC_Decode, 222, 6, 179, 1, // 10453: decode to DRINTX using decoder 179
5196 // 10453: }
5197 7, 0, // 10458: case 0x7: {
5198 OPC_CheckField, 17, 4, 0, // 10460: check Inst[20:17] == 0x0
5199 OPC_Decode, 225, 6, 179, 1, // 10464: decode to DRINTX_rec using decoder 179
5200 // 10464: }
5201 // 10464: } // switch Inst[2:0]
5202 // 10464: }
5203 4, 47, // 10469: case 0x4: {
5204 OPC_SwitchField, 9, 2, // 10471: switch Inst[10:9] {
5205 0, 13, // 10474: case 0x0: {
5206 OPC_CheckField, 21, 2, 0, // 10476: check Inst[22:21] == 0x0
5207 OPC_CheckField, 0, 3, 4, // 10480: check Inst[2:0] == 0x4
5208 OPC_Decode, 245, 5, 180, 1, // 10484: decode to DCMPO using decoder 180
5209 // 10484: }
5210 1, 5, // 10489: case 0x1: {
5211 OPC_Decode, 188, 20, 181, 1, // 10491: decode to XSADDADDUQM using decoder 181
5212 // 10491: }
5213 2, 13, // 10496: case 0x2: {
5214 OPC_CheckField, 21, 2, 0, // 10498: check Inst[22:21] == 0x0
5215 OPC_CheckField, 0, 3, 4, // 10502: check Inst[2:0] == 0x4
5216 OPC_Decode, 247, 5, 180, 1, // 10506: decode to DCMPU using decoder 180
5217 // 10506: }
5218 3, 0, // 10511: case 0x3: {
5219 OPC_Decode, 193, 20, 181, 1, // 10513: decode to XSADDSUBSUQM using decoder 181
5220 // 10513: }
5221 // 10513: } // switch Inst[10:9]
5222 // 10513: }
5223 5, 59, // 10518: case 0x5: {
5224 OPC_SwitchField, 9, 2, // 10520: switch Inst[10:9] {
5225 0, 13, // 10523: case 0x0: {
5226 OPC_CheckField, 21, 2, 0, // 10525: check Inst[22:21] == 0x0
5227 OPC_CheckField, 0, 3, 4, // 10529: check Inst[2:0] == 0x4
5228 OPC_Decode, 130, 7, 180, 1, // 10533: decode to DTSTEX using decoder 180
5229 // 10533: }
5230 1, 5, // 10538: case 0x1: {
5231 OPC_Decode, 187, 20, 181, 1, // 10540: decode to XSADDADDSUQM using decoder 181
5232 // 10540: }
5233 2, 25, // 10545: case 0x2: {
5234 OPC_SwitchField, 0, 3, // 10547: switch Inst[2:0] {
5235 4, 9, // 10550: case 0x4: {
5236 OPC_CheckField, 21, 2, 0, // 10552: check Inst[22:21] == 0x0
5237 OPC_Decode, 132, 7, 180, 1, // 10556: decode to DTSTSF using decoder 180
5238 // 10556: }
5239 6, 0, // 10561: case 0x6: {
5240 OPC_CheckField, 22, 1, 0, // 10563: check Inst[22] == 0x0
5241 OPC_Decode, 133, 7, 182, 1, // 10567: decode to DTSTSFI using decoder 182
5242 // 10567: }
5243 // 10567: } // switch Inst[2:0]
5244 // 10567: }
5245 3, 0, // 10572: case 0x3: {
5246 OPC_Decode, 128, 21, 181, 1, // 10574: decode to XSMERGE2T1UQM using decoder 181
5247 // 10574: }
5248 // 10574: } // switch Inst[10:9]
5249 // 10574: }
5250 6, 37, // 10579: case 0x6: {
5251 OPC_SwitchField, 9, 1, // 10581: switch Inst[9] {
5252 0, 13, // 10584: case 0x0: {
5253 OPC_CheckField, 21, 2, 0, // 10586: check Inst[22:21] == 0x0
5254 OPC_CheckField, 0, 3, 4, // 10590: check Inst[2:0] == 0x4
5255 OPC_Decode, 254, 6, 183, 1, // 10594: decode to DTSTDC using decoder 183
5256 // 10594: }
5257 1, 0, // 10599: case 0x1: {
5258 OPC_SwitchField, 10, 1, // 10601: switch Inst[10] {
5259 0, 5, // 10604: case 0x0: {
5260 OPC_Decode, 194, 20, 181, 1, // 10606: decode to XSADDSUBUQM using decoder 181
5261 // 10606: }
5262 1, 0, // 10611: case 0x1: {
5263 OPC_Decode, 129, 21, 181, 1, // 10613: decode to XSMERGE2T2UQM using decoder 181
5264 // 10613: }
5265 // 10613: } // switch Inst[10]
5266 // 10613: }
5267 // 10613: } // switch Inst[9]
5268 // 10613: }
5269 7, 0, // 10618: case 0x7: {
5270 OPC_SwitchField, 0, 3, // 10620: switch Inst[2:0] {
5271 4, 13, // 10623: case 0x4: {
5272 OPC_CheckField, 21, 2, 0, // 10625: check Inst[22:21] == 0x0
5273 OPC_CheckField, 9, 1, 0, // 10629: check Inst[9] == 0x0
5274 OPC_Decode, 128, 7, 183, 1, // 10633: decode to DTSTDG using decoder 183
5275 // 10633: }
5276 6, 9, // 10638: case 0x6: {
5277 OPC_CheckField, 17, 4, 0, // 10640: check Inst[20:17] == 0x0
5278 OPC_Decode, 218, 6, 179, 1, // 10644: decode to DRINTN using decoder 179
5279 // 10644: }
5280 7, 0, // 10649: case 0x7: {
5281 OPC_CheckField, 17, 4, 0, // 10651: check Inst[20:17] == 0x0
5282 OPC_Decode, 221, 6, 179, 1, // 10655: decode to DRINTN_rec using decoder 179
5283 // 10655: }
5284 // 10655: } // switch Inst[2:0]
5285 // 10655: }
5286 // 10655: } // switch Inst[8:6]
5287 // 10655: }
5288 1, 119, // 10660: case 0x1: {
5289 OPC_SwitchField, 6, 2, // 10662: switch Inst[7:6] {
5290 0, 5, // 10665: case 0x0: {
5291 OPC_Decode, 150, 23, 184, 1, // 10667: decode to XXMULMUL using decoder 184
5292 // 10667: }
5293 1, 5, // 10672: case 0x1: {
5294 OPC_Decode, 151, 23, 185, 1, // 10674: decode to XXMULMULHIADD using decoder 185
5295 // 10674: }
5296 2, 43, // 10679: case 0x2: {
5297 OPC_SwitchField, 10, 1, // 10681: switch Inst[10] {
5298 0, 5, // 10684: case 0x0: {
5299 OPC_Decode, 152, 23, 186, 1, // 10686: decode to XXMULMULLOADD using decoder 186
5300 // 10686: }
5301 1, 0, // 10691: case 0x1: {
5302 OPC_SwitchField, 8, 2, // 10693: switch Inst[9:8] {
5303 0, 5, // 10696: case 0x0: {
5304 OPC_Decode, 168, 21, 181, 1, // 10698: decode to XSREBASE2T1UQM using decoder 181
5305 // 10698: }
5306 1, 5, // 10703: case 0x1: {
5307 OPC_Decode, 169, 21, 181, 1, // 10705: decode to XSREBASE2T2UQM using decoder 181
5308 // 10705: }
5309 2, 5, // 10710: case 0x2: {
5310 OPC_Decode, 170, 21, 181, 1, // 10712: decode to XSREBASE2T3UQM using decoder 181
5311 // 10712: }
5312 3, 0, // 10717: case 0x3: {
5313 OPC_Decode, 172, 21, 181, 1, // 10719: decode to XSREBASE3T1UQM using decoder 181
5314 // 10719: }
5315 // 10719: } // switch Inst[9:8]
5316 // 10719: }
5317 // 10719: } // switch Inst[10]
5318 // 10719: }
5319 3, 0, // 10724: case 0x3: {
5320 OPC_SwitchField, 8, 2, // 10726: switch Inst[9:8] {
5321 0, 5, // 10729: case 0x0: {
5322 OPC_Decode, 168, 23, 187, 1, // 10731: decode to XXSSUMUDM using decoder 187
5323 // 10731: }
5324 1, 5, // 10736: case 0x1: {
5325 OPC_Decode, 169, 23, 187, 1, // 10738: decode to XXSSUMUDMC using decoder 187
5326 // 10738: }
5327 2, 17, // 10743: case 0x2: {
5328 OPC_SwitchField, 10, 1, // 10745: switch Inst[10] {
5329 0, 5, // 10748: case 0x0: {
5330 OPC_Decode, 130, 21, 181, 1, // 10750: decode to XSMERGE2T3UQM using decoder 181
5331 // 10750: }
5332 1, 0, // 10755: case 0x1: {
5333 OPC_Decode, 171, 21, 181, 1, // 10757: decode to XSREBASE2T4UQM using decoder 181
5334 // 10757: }
5335 // 10757: } // switch Inst[10]
5336 // 10757: }
5337 3, 0, // 10762: case 0x3: {
5338 OPC_SwitchField, 10, 1, // 10764: switch Inst[10] {
5339 0, 5, // 10767: case 0x0: {
5340 OPC_Decode, 131, 21, 181, 1, // 10769: decode to XSMERGE3T1UQM using decoder 181
5341 // 10769: }
5342 1, 0, // 10774: case 0x1: {
5343 OPC_Decode, 173, 21, 181, 1, // 10776: decode to XSREBASE3T2UQM using decoder 181
5344 // 10776: }
5345 // 10776: } // switch Inst[10]
5346 // 10776: }
5347 // 10776: } // switch Inst[9:8]
5348 // 10776: }
5349 // 10776: } // switch Inst[7:6]
5350 // 10776: }
5351 2, 146, 3, // 10781: case 0x2: {
5352 OPC_SwitchField, 6, 5, // 10784: switch Inst[10:6] {
5353 0, 13, // 10787: case 0x0: {
5354 OPC_CheckField, 21, 2, 0, // 10789: check Inst[22:21] == 0x0
5355 OPC_CheckField, 0, 1, 0, // 10793: check Inst[0] == 0x0
5356 OPC_Decode, 169, 22, 188, 1, // 10797: decode to XVI8GER4PP using decoder 188
5357 // 10797: }
5358 1, 17, // 10802: case 0x1: {
5359 OPC_CheckField, 21, 2, 0, // 10804: check Inst[22:21] == 0x0
5360 OPC_CheckField, 16, 1, 0, // 10808: check Inst[16] == 0x0
5361 OPC_CheckField, 0, 1, 0, // 10812: check Inst[0] == 0x0
5362 OPC_Decode, 198, 6, 189, 1, // 10816: decode to DMXVI8GERX4PP using decoder 189
5363 // 10816: }
5364 2, 13, // 10821: case 0x2: {
5365 OPC_CheckField, 21, 2, 0, // 10823: check Inst[22:21] == 0x0
5366 OPC_CheckField, 0, 1, 0, // 10827: check Inst[0] == 0x0
5367 OPC_Decode, 130, 22, 188, 1, // 10831: decode to XVF16GER2PP using decoder 188
5368 // 10831: }
5369 3, 13, // 10836: case 0x3: {
5370 OPC_CheckField, 21, 2, 0, // 10838: check Inst[22:21] == 0x0
5371 OPC_CheckField, 0, 1, 0, // 10842: check Inst[0] == 0x0
5372 OPC_Decode, 140, 22, 188, 1, // 10846: decode to XVF32GERPP using decoder 188
5373 // 10846: }
5374 4, 13, // 10851: case 0x4: {
5375 OPC_CheckField, 21, 2, 0, // 10853: check Inst[22:21] == 0x0
5376 OPC_CheckField, 0, 1, 0, // 10857: check Inst[0] == 0x0
5377 OPC_Decode, 165, 22, 188, 1, // 10861: decode to XVI4GER8PP using decoder 188
5378 // 10861: }
5379 5, 13, // 10866: case 0x5: {
5380 OPC_CheckField, 21, 2, 0, // 10868: check Inst[22:21] == 0x0
5381 OPC_CheckField, 0, 1, 0, // 10872: check Inst[0] == 0x0
5382 OPC_Decode, 159, 22, 188, 1, // 10876: decode to XVI16GER2SPP using decoder 188
5383 // 10876: }
5384 6, 13, // 10881: case 0x6: {
5385 OPC_CheckField, 21, 2, 0, // 10883: check Inst[22:21] == 0x0
5386 OPC_CheckField, 0, 1, 0, // 10887: check Inst[0] == 0x0
5387 OPC_Decode, 210, 21, 188, 1, // 10891: decode to XVBF16GER2PP using decoder 188
5388 // 10891: }
5389 7, 13, // 10896: case 0x7: {
5390 OPC_CheckField, 21, 2, 0, // 10898: check Inst[22:21] == 0x0
5391 OPC_CheckField, 0, 1, 0, // 10902: check Inst[0] == 0x0
5392 OPC_Decode, 150, 22, 190, 1, // 10906: decode to XVF64GERPP using decoder 190
5393 // 10906: }
5394 8, 17, // 10911: case 0x8: {
5395 OPC_CheckField, 21, 2, 0, // 10913: check Inst[22:21] == 0x0
5396 OPC_CheckField, 16, 1, 0, // 10917: check Inst[16] == 0x0
5397 OPC_CheckField, 0, 1, 0, // 10921: check Inst[0] == 0x0
5398 OPC_Decode, 196, 6, 189, 1, // 10925: decode to DMXVF16GERX2PP using decoder 189
5399 // 10925: }
5400 9, 17, // 10930: case 0x9: {
5401 OPC_CheckField, 21, 2, 0, // 10932: check Inst[22:21] == 0x0
5402 OPC_CheckField, 16, 1, 0, // 10936: check Inst[16] == 0x0
5403 OPC_CheckField, 0, 1, 0, // 10940: check Inst[0] == 0x0
5404 OPC_Decode, 191, 6, 189, 1, // 10944: decode to DMXVBF16GERX2PP using decoder 189
5405 // 10944: }
5406 10, 13, // 10949: case 0xa: {
5407 OPC_CheckField, 21, 2, 0, // 10951: check Inst[22:21] == 0x0
5408 OPC_CheckField, 0, 1, 0, // 10955: check Inst[0] == 0x0
5409 OPC_Decode, 128, 22, 188, 1, // 10959: decode to XVF16GER2NP using decoder 188
5410 // 10959: }
5411 11, 13, // 10964: case 0xb: {
5412 OPC_CheckField, 21, 2, 0, // 10966: check Inst[22:21] == 0x0
5413 OPC_CheckField, 0, 1, 0, // 10970: check Inst[0] == 0x0
5414 OPC_Decode, 138, 22, 188, 1, // 10974: decode to XVF32GERNP using decoder 188
5415 // 10974: }
5416 12, 17, // 10979: case 0xc: {
5417 OPC_CheckField, 21, 2, 0, // 10981: check Inst[22:21] == 0x0
5418 OPC_CheckField, 16, 1, 0, // 10985: check Inst[16] == 0x0
5419 OPC_CheckField, 0, 1, 0, // 10989: check Inst[0] == 0x0
5420 OPC_Decode, 199, 6, 189, 1, // 10993: decode to DMXVI8GERX4SPP using decoder 189
5421 // 10993: }
5422 14, 13, // 10998: case 0xe: {
5423 OPC_CheckField, 21, 2, 0, // 11000: check Inst[22:21] == 0x0
5424 OPC_CheckField, 0, 1, 0, // 11004: check Inst[0] == 0x0
5425 OPC_Decode, 208, 21, 188, 1, // 11008: decode to XVBF16GER2NP using decoder 188
5426 // 11008: }
5427 15, 13, // 11013: case 0xf: {
5428 OPC_CheckField, 21, 2, 0, // 11015: check Inst[22:21] == 0x0
5429 OPC_CheckField, 0, 1, 0, // 11019: check Inst[0] == 0x0
5430 OPC_Decode, 148, 22, 190, 1, // 11023: decode to XVF64GERNP using decoder 190
5431 // 11023: }
5432 18, 13, // 11028: case 0x12: {
5433 OPC_CheckField, 21, 2, 0, // 11030: check Inst[22:21] == 0x0
5434 OPC_CheckField, 0, 1, 0, // 11034: check Inst[0] == 0x0
5435 OPC_Decode, 129, 22, 188, 1, // 11038: decode to XVF16GER2PN using decoder 188
5436 // 11038: }
5437 19, 13, // 11043: case 0x13: {
5438 OPC_CheckField, 21, 2, 0, // 11045: check Inst[22:21] == 0x0
5439 OPC_CheckField, 0, 1, 0, // 11049: check Inst[0] == 0x0
5440 OPC_Decode, 139, 22, 188, 1, // 11053: decode to XVF32GERPN using decoder 188
5441 // 11053: }
5442 22, 13, // 11058: case 0x16: {
5443 OPC_CheckField, 21, 2, 0, // 11060: check Inst[22:21] == 0x0
5444 OPC_CheckField, 0, 1, 0, // 11064: check Inst[0] == 0x0
5445 OPC_Decode, 209, 21, 188, 1, // 11068: decode to XVBF16GER2PN using decoder 188
5446 // 11068: }
5447 23, 13, // 11073: case 0x17: {
5448 OPC_CheckField, 21, 2, 0, // 11075: check Inst[22:21] == 0x0
5449 OPC_CheckField, 0, 1, 0, // 11079: check Inst[0] == 0x0
5450 OPC_Decode, 149, 22, 190, 1, // 11083: decode to XVF64GERPN using decoder 190
5451 // 11083: }
5452 25, 17, // 11088: case 0x19: {
5453 OPC_CheckField, 21, 2, 0, // 11090: check Inst[22:21] == 0x0
5454 OPC_CheckField, 16, 1, 0, // 11094: check Inst[16] == 0x0
5455 OPC_CheckField, 0, 1, 0, // 11098: check Inst[0] == 0x0
5456 OPC_Decode, 193, 6, 189, 1, // 11102: decode to DMXVF16GERX2NN using decoder 189
5457 // 11102: }
5458 26, 13, // 11107: case 0x1a: {
5459 OPC_CheckField, 21, 2, 0, // 11109: check Inst[22:21] == 0x0
5460 OPC_CheckField, 0, 1, 0, // 11113: check Inst[0] == 0x0
5461 OPC_Decode, 255, 21, 188, 1, // 11117: decode to XVF16GER2NN using decoder 188
5462 // 11117: }
5463 27, 13, // 11122: case 0x1b: {
5464 OPC_CheckField, 21, 2, 0, // 11124: check Inst[22:21] == 0x0
5465 OPC_CheckField, 0, 1, 0, // 11128: check Inst[0] == 0x0
5466 OPC_Decode, 137, 22, 188, 1, // 11132: decode to XVF32GERNN using decoder 188
5467 // 11132: }
5468 29, 17, // 11137: case 0x1d: {
5469 OPC_CheckField, 21, 2, 0, // 11139: check Inst[22:21] == 0x0
5470 OPC_CheckField, 16, 1, 0, // 11143: check Inst[16] == 0x0
5471 OPC_CheckField, 0, 1, 0, // 11147: check Inst[0] == 0x0
5472 OPC_Decode, 188, 6, 189, 1, // 11151: decode to DMXVBF16GERX2NN using decoder 189
5473 // 11151: }
5474 30, 13, // 11156: case 0x1e: {
5475 OPC_CheckField, 21, 2, 0, // 11158: check Inst[22:21] == 0x0
5476 OPC_CheckField, 0, 1, 0, // 11162: check Inst[0] == 0x0
5477 OPC_Decode, 207, 21, 188, 1, // 11166: decode to XVBF16GER2NN using decoder 188
5478 // 11166: }
5479 31, 0, // 11171: case 0x1f: {
5480 OPC_CheckField, 21, 2, 0, // 11173: check Inst[22:21] == 0x0
5481 OPC_CheckField, 0, 1, 0, // 11177: check Inst[0] == 0x0
5482 OPC_Decode, 147, 22, 190, 1, // 11181: decode to XVF64GERNN using decoder 190
5483 // 11181: }
5484 // 11181: } // switch Inst[10:6]
5485 // 11181: }
5486 3, 219, 2, // 11186: case 0x3: {
5487 OPC_SwitchField, 6, 5, // 11189: switch Inst[10:6] {
5488 0, 13, // 11192: case 0x0: {
5489 OPC_CheckField, 21, 2, 0, // 11194: check Inst[22:21] == 0x0
5490 OPC_CheckField, 0, 1, 0, // 11198: check Inst[0] == 0x0
5491 OPC_Decode, 168, 22, 191, 1, // 11202: decode to XVI8GER4 using decoder 191
5492 // 11202: }
5493 1, 17, // 11207: case 0x1: {
5494 OPC_CheckField, 21, 2, 0, // 11209: check Inst[22:21] == 0x0
5495 OPC_CheckField, 16, 1, 0, // 11213: check Inst[16] == 0x0
5496 OPC_CheckField, 0, 1, 0, // 11217: check Inst[0] == 0x0
5497 OPC_Decode, 197, 6, 192, 1, // 11221: decode to DMXVI8GERX4 using decoder 192
5498 // 11221: }
5499 2, 13, // 11226: case 0x2: {
5500 OPC_CheckField, 21, 2, 0, // 11228: check Inst[22:21] == 0x0
5501 OPC_CheckField, 0, 1, 0, // 11232: check Inst[0] == 0x0
5502 OPC_Decode, 254, 21, 191, 1, // 11236: decode to XVF16GER2 using decoder 191
5503 // 11236: }
5504 3, 13, // 11241: case 0x3: {
5505 OPC_CheckField, 21, 2, 0, // 11243: check Inst[22:21] == 0x0
5506 OPC_CheckField, 0, 1, 0, // 11247: check Inst[0] == 0x0
5507 OPC_Decode, 136, 22, 191, 1, // 11251: decode to XVF32GER using decoder 191
5508 // 11251: }
5509 4, 13, // 11256: case 0x4: {
5510 OPC_CheckField, 21, 2, 0, // 11258: check Inst[22:21] == 0x0
5511 OPC_CheckField, 0, 1, 0, // 11262: check Inst[0] == 0x0
5512 OPC_Decode, 164, 22, 191, 1, // 11266: decode to XVI4GER8 using decoder 191
5513 // 11266: }
5514 5, 13, // 11271: case 0x5: {
5515 OPC_CheckField, 21, 2, 0, // 11273: check Inst[22:21] == 0x0
5516 OPC_CheckField, 0, 1, 0, // 11277: check Inst[0] == 0x0
5517 OPC_Decode, 158, 22, 191, 1, // 11281: decode to XVI16GER2S using decoder 191
5518 // 11281: }
5519 6, 13, // 11286: case 0x6: {
5520 OPC_CheckField, 21, 2, 0, // 11288: check Inst[22:21] == 0x0
5521 OPC_CheckField, 0, 1, 0, // 11292: check Inst[0] == 0x0
5522 OPC_Decode, 206, 21, 191, 1, // 11296: decode to XVBF16GER2 using decoder 191
5523 // 11296: }
5524 7, 13, // 11301: case 0x7: {
5525 OPC_CheckField, 21, 2, 0, // 11303: check Inst[22:21] == 0x0
5526 OPC_CheckField, 0, 1, 0, // 11307: check Inst[0] == 0x0
5527 OPC_Decode, 146, 22, 193, 1, // 11311: decode to XVF64GER using decoder 193
5528 // 11311: }
5529 8, 17, // 11316: case 0x8: {
5530 OPC_CheckField, 21, 2, 0, // 11318: check Inst[22:21] == 0x0
5531 OPC_CheckField, 16, 1, 0, // 11322: check Inst[16] == 0x0
5532 OPC_CheckField, 0, 1, 0, // 11326: check Inst[0] == 0x0
5533 OPC_Decode, 192, 6, 192, 1, // 11330: decode to DMXVF16GERX2 using decoder 192
5534 // 11330: }
5535 9, 13, // 11335: case 0x9: {
5536 OPC_CheckField, 21, 2, 0, // 11337: check Inst[22:21] == 0x0
5537 OPC_CheckField, 0, 1, 0, // 11341: check Inst[0] == 0x0
5538 OPC_Decode, 156, 22, 191, 1, // 11345: decode to XVI16GER2 using decoder 191
5539 // 11345: }
5540 10, 17, // 11350: case 0xa: {
5541 OPC_CheckField, 21, 2, 0, // 11352: check Inst[22:21] == 0x0
5542 OPC_CheckField, 16, 1, 0, // 11356: check Inst[16] == 0x0
5543 OPC_CheckField, 0, 1, 0, // 11360: check Inst[0] == 0x0
5544 OPC_Decode, 194, 6, 189, 1, // 11364: decode to DMXVF16GERX2NP using decoder 189
5545 // 11364: }
5546 11, 17, // 11369: case 0xb: {
5547 OPC_CheckField, 21, 2, 0, // 11371: check Inst[22:21] == 0x0
5548 OPC_CheckField, 16, 1, 0, // 11375: check Inst[16] == 0x0
5549 OPC_CheckField, 0, 1, 0, // 11379: check Inst[0] == 0x0
5550 OPC_Decode, 187, 6, 192, 1, // 11383: decode to DMXVBF16GERX2 using decoder 192
5551 // 11383: }
5552 12, 13, // 11388: case 0xc: {
5553 OPC_CheckField, 21, 2, 0, // 11390: check Inst[22:21] == 0x0
5554 OPC_CheckField, 0, 1, 0, // 11394: check Inst[0] == 0x0
5555 OPC_Decode, 170, 22, 188, 1, // 11398: decode to XVI8GER4SPP using decoder 188
5556 // 11398: }
5557 13, 13, // 11403: case 0xd: {
5558 OPC_CheckField, 21, 2, 0, // 11405: check Inst[22:21] == 0x0
5559 OPC_CheckField, 0, 1, 0, // 11409: check Inst[0] == 0x0
5560 OPC_Decode, 157, 22, 188, 1, // 11413: decode to XVI16GER2PP using decoder 188
5561 // 11413: }
5562 14, 17, // 11418: case 0xe: {
5563 OPC_CheckField, 21, 2, 0, // 11420: check Inst[22:21] == 0x0
5564 OPC_CheckField, 16, 1, 0, // 11424: check Inst[16] == 0x0
5565 OPC_CheckField, 0, 1, 0, // 11428: check Inst[0] == 0x0
5566 OPC_Decode, 189, 6, 189, 1, // 11432: decode to DMXVBF16GERX2NP using decoder 189
5567 // 11432: }
5568 18, 17, // 11437: case 0x12: {
5569 OPC_CheckField, 21, 2, 0, // 11439: check Inst[22:21] == 0x0
5570 OPC_CheckField, 16, 1, 0, // 11443: check Inst[16] == 0x0
5571 OPC_CheckField, 0, 1, 0, // 11447: check Inst[0] == 0x0
5572 OPC_Decode, 195, 6, 189, 1, // 11451: decode to DMXVF16GERX2PN using decoder 189
5573 // 11451: }
5574 22, 17, // 11456: case 0x16: {
5575 OPC_CheckField, 21, 2, 0, // 11458: check Inst[22:21] == 0x0
5576 OPC_CheckField, 16, 1, 0, // 11462: check Inst[16] == 0x0
5577 OPC_CheckField, 0, 1, 0, // 11466: check Inst[0] == 0x0
5578 OPC_Decode, 190, 6, 189, 1, // 11470: decode to DMXVBF16GERX2PN using decoder 189
5579 // 11470: }
5580 24, 5, // 11475: case 0x18: {
5581 OPC_Decode, 174, 21, 181, 1, // 11477: decode to XSREBASE3T3UQM using decoder 181
5582 // 11477: }
5583 26, 25, // 11482: case 0x1a: {
5584 OPC_SwitchField, 0, 3, // 11484: switch Inst[2:0] {
5585 4, 9, // 11487: case 0x4: {
5586 OPC_CheckField, 16, 5, 0, // 11489: check Inst[20:16] == 0x0
5587 OPC_Decode, 176, 9, 194, 1, // 11493: decode to FCFIDS using decoder 194
5588 // 11493: }
5589 5, 0, // 11498: case 0x5: {
5590 OPC_CheckField, 16, 5, 0, // 11500: check Inst[20:16] == 0x0
5591 OPC_Decode, 177, 9, 194, 1, // 11504: decode to FCFIDS_rec using decoder 194
5592 // 11504: }
5593 // 11504: } // switch Inst[2:0]
5594 // 11504: }
5595 30, 0, // 11509: case 0x1e: {
5596 OPC_SwitchField, 0, 3, // 11511: switch Inst[2:0] {
5597 4, 9, // 11514: case 0x4: {
5598 OPC_CheckField, 16, 5, 0, // 11516: check Inst[20:16] == 0x0
5599 OPC_Decode, 179, 9, 194, 1, // 11520: decode to FCFIDUS using decoder 194
5600 // 11520: }
5601 5, 0, // 11525: case 0x5: {
5602 OPC_CheckField, 16, 5, 0, // 11527: check Inst[20:16] == 0x0
5603 OPC_Decode, 180, 9, 194, 1, // 11531: decode to FCFIDUS_rec using decoder 194
5604 // 11531: }
5605 // 11531: } // switch Inst[2:0]
5606 // 11531: }
5607 // 11531: } // switch Inst[10:6]
5608 // 11531: }
5609 4, 25, // 11536: case 0x4: {
5610 OPC_SwitchField, 0, 3, // 11538: switch Inst[2:0] {
5611 4, 9, // 11541: case 0x4: {
5612 OPC_CheckField, 6, 5, 0, // 11543: check Inst[10:6] == 0x0
5613 OPC_Decode, 208, 9, 195, 1, // 11547: decode to FDIVS using decoder 195
5614 // 11547: }
5615 5, 0, // 11552: case 0x5: {
5616 OPC_CheckField, 6, 5, 0, // 11554: check Inst[10:6] == 0x0
5617 OPC_Decode, 209, 9, 195, 1, // 11558: decode to FDIVS_rec using decoder 195
5618 // 11558: }
5619 // 11558: } // switch Inst[2:0]
5620 // 11558: }
5621 5, 77, // 11563: case 0x5: {
5622 OPC_SwitchField, 0, 3, // 11565: switch Inst[2:0] {
5623 0, 9, // 11568: case 0x0: {
5624 OPC_CheckField, 6, 5, 0, // 11570: check Inst[10:6] == 0x0
5625 OPC_Decode, 149, 10, 195, 1, // 11574: decode to FSUBS using decoder 195
5626 // 11574: }
5627 1, 9, // 11579: case 0x1: {
5628 OPC_CheckField, 6, 5, 0, // 11581: check Inst[10:6] == 0x0
5629 OPC_Decode, 150, 10, 195, 1, // 11585: decode to FSUBS_rec using decoder 195
5630 // 11585: }
5631 2, 9, // 11590: case 0x2: {
5632 OPC_CheckField, 6, 5, 0, // 11592: check Inst[10:6] == 0x0
5633 OPC_Decode, 171, 9, 195, 1, // 11596: decode to FADDS using decoder 195
5634 // 11596: }
5635 3, 9, // 11601: case 0x3: {
5636 OPC_CheckField, 6, 5, 0, // 11603: check Inst[10:6] == 0x0
5637 OPC_Decode, 172, 9, 195, 1, // 11607: decode to FADDS_rec using decoder 195
5638 // 11607: }
5639 4, 13, // 11612: case 0x4: {
5640 OPC_CheckField, 16, 5, 0, // 11614: check Inst[20:16] == 0x0
5641 OPC_CheckField, 6, 5, 0, // 11618: check Inst[10:6] == 0x0
5642 OPC_Decode, 145, 10, 196, 1, // 11622: decode to FSQRTS using decoder 196
5643 // 11622: }
5644 5, 0, // 11627: case 0x5: {
5645 OPC_CheckField, 16, 5, 0, // 11629: check Inst[20:16] == 0x0
5646 OPC_CheckField, 6, 5, 0, // 11633: check Inst[10:6] == 0x0
5647 OPC_Decode, 146, 10, 196, 1, // 11637: decode to FSQRTS_rec using decoder 196
5648 // 11637: }
5649 // 11637: } // switch Inst[2:0]
5650 // 11637: }
5651 6, 85, // 11642: case 0x6: {
5652 OPC_SwitchField, 0, 3, // 11644: switch Inst[2:0] {
5653 0, 13, // 11647: case 0x0: {
5654 OPC_CheckField, 16, 5, 0, // 11649: check Inst[20:16] == 0x0
5655 OPC_CheckField, 6, 5, 0, // 11653: check Inst[10:6] == 0x0
5656 OPC_Decode, 243, 9, 196, 1, // 11657: decode to FRES using decoder 196
5657 // 11657: }
5658 1, 13, // 11662: case 0x1: {
5659 OPC_CheckField, 16, 5, 0, // 11664: check Inst[20:16] == 0x0
5660 OPC_CheckField, 6, 5, 0, // 11668: check Inst[10:6] == 0x0
5661 OPC_Decode, 244, 9, 196, 1, // 11672: decode to FRES_rec using decoder 196
5662 // 11672: }
5663 2, 9, // 11677: case 0x2: {
5664 OPC_CheckField, 11, 5, 0, // 11679: check Inst[15:11] == 0x0
5665 OPC_Decode, 223, 9, 197, 1, // 11683: decode to FMULS using decoder 197
5666 // 11683: }
5667 3, 9, // 11688: case 0x3: {
5668 OPC_CheckField, 11, 5, 0, // 11690: check Inst[15:11] == 0x0
5669 OPC_Decode, 224, 9, 197, 1, // 11694: decode to FMULS_rec using decoder 197
5670 // 11694: }
5671 4, 13, // 11699: case 0x4: {
5672 OPC_CheckField, 16, 5, 0, // 11701: check Inst[20:16] == 0x0
5673 OPC_CheckField, 6, 5, 0, // 11705: check Inst[10:6] == 0x0
5674 OPC_Decode, 137, 10, 196, 1, // 11709: decode to FRSQRTES using decoder 196
5675 // 11709: }
5676 5, 0, // 11714: case 0x5: {
5677 OPC_CheckField, 16, 5, 0, // 11716: check Inst[20:16] == 0x0
5678 OPC_CheckField, 6, 5, 0, // 11720: check Inst[10:6] == 0x0
5679 OPC_Decode, 138, 10, 196, 1, // 11724: decode to FRSQRTES_rec using decoder 196
5680 // 11724: }
5681 // 11724: } // switch Inst[2:0]
5682 // 11724: }
5683 7, 0, // 11729: case 0x7: {
5684 OPC_SwitchField, 0, 3, // 11731: switch Inst[2:0] {
5685 0, 5, // 11734: case 0x0: {
5686 OPC_Decode, 219, 9, 198, 1, // 11736: decode to FMSUBS using decoder 198
5687 // 11736: }
5688 1, 5, // 11741: case 0x1: {
5689 OPC_Decode, 220, 9, 198, 1, // 11743: decode to FMSUBS_rec using decoder 198
5690 // 11743: }
5691 2, 5, // 11748: case 0x2: {
5692 OPC_Decode, 213, 9, 198, 1, // 11750: decode to FMADDS using decoder 198
5693 // 11750: }
5694 3, 5, // 11755: case 0x3: {
5695 OPC_Decode, 214, 9, 198, 1, // 11757: decode to FMADDS_rec using decoder 198
5696 // 11757: }
5697 4, 5, // 11762: case 0x4: {
5698 OPC_Decode, 239, 9, 198, 1, // 11764: decode to FNMSUBS using decoder 198
5699 // 11764: }
5700 5, 5, // 11769: case 0x5: {
5701 OPC_Decode, 240, 9, 198, 1, // 11771: decode to FNMSUBS_rec using decoder 198
5702 // 11771: }
5703 6, 5, // 11776: case 0x6: {
5704 OPC_Decode, 235, 9, 198, 1, // 11778: decode to FNMADDS using decoder 198
5705 // 11778: }
5706 7, 0, // 11783: case 0x7: {
5707 OPC_Decode, 236, 9, 198, 1, // 11785: decode to FNMADDS_rec using decoder 198
5708 // 11785: }
5709 // 11785: } // switch Inst[2:0]
5710 // 11785: }
5711 // 11785: } // switch Inst[5:3]
5712 // 11785: }
5713 60, 146, 21, // 11790: case 0x3c: {
5714 OPC_SwitchField, 4, 2, // 11793: switch Inst[5:4] {
5715 0, 227, 4, // 11796: case 0x0: {
5716 OPC_SwitchField, 6, 5, // 11799: switch Inst[10:6] {
5717 0, 17, // 11802: case 0x0: {
5718 OPC_SwitchField, 3, 1, // 11804: switch Inst[3] {
5719 0, 5, // 11807: case 0x0: {
5720 OPC_Decode, 192, 20, 199, 1, // 11809: decode to XSADDSP using decoder 199
5721 // 11809: }
5722 1, 0, // 11814: case 0x1: {
5723 OPC_Decode, 247, 20, 200, 1, // 11816: decode to XSMADDASP using decoder 200
5724 // 11816: }
5725 // 11816: } // switch Inst[3]
5726 // 11816: }
5727 1, 17, // 11821: case 0x1: {
5728 OPC_SwitchField, 3, 1, // 11823: switch Inst[3] {
5729 0, 5, // 11826: case 0x0: {
5730 OPC_Decode, 190, 21, 199, 1, // 11828: decode to XSSUBSP using decoder 199
5731 // 11828: }
5732 1, 0, // 11833: case 0x1: {
5733 OPC_Decode, 249, 20, 200, 1, // 11835: decode to XSMADDMSP using decoder 200
5734 // 11835: }
5735 // 11835: } // switch Inst[3]
5736 // 11835: }
5737 2, 17, // 11840: case 0x2: {
5738 OPC_SwitchField, 3, 1, // 11842: switch Inst[3] {
5739 0, 5, // 11845: case 0x0: {
5740 OPC_Decode, 145, 21, 199, 1, // 11847: decode to XSMULSP using decoder 199
5741 // 11847: }
5742 1, 0, // 11852: case 0x1: {
5743 OPC_Decode, 137, 21, 200, 1, // 11854: decode to XSMSUBASP using decoder 200
5744 // 11854: }
5745 // 11854: } // switch Inst[3]
5746 // 11854: }
5747 3, 17, // 11859: case 0x3: {
5748 OPC_SwitchField, 3, 1, // 11861: switch Inst[3] {
5749 0, 5, // 11864: case 0x0: {
5750 OPC_Decode, 243, 20, 199, 1, // 11866: decode to XSDIVSP using decoder 199
5751 // 11866: }
5752 1, 0, // 11871: case 0x1: {
5753 OPC_Decode, 139, 21, 200, 1, // 11873: decode to XSMSUBMSP using decoder 200
5754 // 11873: }
5755 // 11873: } // switch Inst[3]
5756 // 11873: }
5757 4, 17, // 11878: case 0x4: {
5758 OPC_SwitchField, 3, 1, // 11880: switch Inst[3] {
5759 0, 5, // 11883: case 0x0: {
5760 OPC_Decode, 189, 20, 201, 1, // 11885: decode to XSADDDP using decoder 201
5761 // 11885: }
5762 1, 0, // 11890: case 0x1: {
5763 OPC_Decode, 246, 20, 202, 1, // 11892: decode to XSMADDADP using decoder 202
5764 // 11892: }
5765 // 11892: } // switch Inst[3]
5766 // 11892: }
5767 5, 17, // 11897: case 0x5: {
5768 OPC_SwitchField, 3, 1, // 11899: switch Inst[3] {
5769 0, 5, // 11902: case 0x0: {
5770 OPC_Decode, 187, 21, 201, 1, // 11904: decode to XSSUBDP using decoder 201
5771 // 11904: }
5772 1, 0, // 11909: case 0x1: {
5773 OPC_Decode, 248, 20, 202, 1, // 11911: decode to XSMADDMDP using decoder 202
5774 // 11911: }
5775 // 11911: } // switch Inst[3]
5776 // 11911: }
5777 6, 17, // 11916: case 0x6: {
5778 OPC_SwitchField, 3, 1, // 11918: switch Inst[3] {
5779 0, 5, // 11921: case 0x0: {
5780 OPC_Decode, 142, 21, 201, 1, // 11923: decode to XSMULDP using decoder 201
5781 // 11923: }
5782 1, 0, // 11928: case 0x1: {
5783 OPC_Decode, 136, 21, 202, 1, // 11930: decode to XSMSUBADP using decoder 202
5784 // 11930: }
5785 // 11930: } // switch Inst[3]
5786 // 11930: }
5787 7, 17, // 11935: case 0x7: {
5788 OPC_SwitchField, 3, 1, // 11937: switch Inst[3] {
5789 0, 5, // 11940: case 0x0: {
5790 OPC_Decode, 240, 20, 201, 1, // 11942: decode to XSDIVDP using decoder 201
5791 // 11942: }
5792 1, 0, // 11947: case 0x1: {
5793 OPC_Decode, 138, 21, 202, 1, // 11949: decode to XSMSUBMDP using decoder 202
5794 // 11949: }
5795 // 11949: } // switch Inst[3]
5796 // 11949: }
5797 8, 17, // 11954: case 0x8: {
5798 OPC_SwitchField, 3, 1, // 11956: switch Inst[3] {
5799 0, 5, // 11959: case 0x0: {
5800 OPC_Decode, 203, 21, 181, 1, // 11961: decode to XVADDSP using decoder 181
5801 // 11961: }
5802 1, 0, // 11966: case 0x1: {
5803 OPC_Decode, 177, 22, 203, 1, // 11968: decode to XVMADDASP using decoder 203
5804 // 11968: }
5805 // 11968: } // switch Inst[3]
5806 // 11968: }
5807 9, 17, // 11973: case 0x9: {
5808 OPC_SwitchField, 3, 1, // 11975: switch Inst[3] {
5809 0, 5, // 11978: case 0x0: {
5810 OPC_Decode, 226, 22, 181, 1, // 11980: decode to XVSUBSP using decoder 181
5811 // 11980: }
5812 1, 0, // 11985: case 0x1: {
5813 OPC_Decode, 179, 22, 203, 1, // 11987: decode to XVMADDMSP using decoder 203
5814 // 11987: }
5815 // 11987: } // switch Inst[3]
5816 // 11987: }
5817 10, 17, // 11992: case 0xa: {
5818 OPC_SwitchField, 3, 1, // 11994: switch Inst[3] {
5819 0, 5, // 11997: case 0x0: {
5820 OPC_Decode, 193, 22, 181, 1, // 11999: decode to XVMULSP using decoder 181
5821 // 11999: }
5822 1, 0, // 12004: case 0x1: {
5823 OPC_Decode, 185, 22, 203, 1, // 12006: decode to XVMSUBASP using decoder 203
5824 // 12006: }
5825 // 12006: } // switch Inst[3]
5826 // 12006: }
5827 11, 17, // 12011: case 0xb: {
5828 OPC_SwitchField, 3, 1, // 12013: switch Inst[3] {
5829 0, 5, // 12016: case 0x0: {
5830 OPC_Decode, 253, 21, 181, 1, // 12018: decode to XVDIVSP using decoder 181
5831 // 12018: }
5832 1, 0, // 12023: case 0x1: {
5833 OPC_Decode, 187, 22, 203, 1, // 12025: decode to XVMSUBMSP using decoder 203
5834 // 12025: }
5835 // 12025: } // switch Inst[3]
5836 // 12025: }
5837 12, 17, // 12030: case 0xc: {
5838 OPC_SwitchField, 3, 1, // 12032: switch Inst[3] {
5839 0, 5, // 12035: case 0x0: {
5840 OPC_Decode, 202, 21, 181, 1, // 12037: decode to XVADDDP using decoder 181
5841 // 12037: }
5842 1, 0, // 12042: case 0x1: {
5843 OPC_Decode, 176, 22, 203, 1, // 12044: decode to XVMADDADP using decoder 203
5844 // 12044: }
5845 // 12044: } // switch Inst[3]
5846 // 12044: }
5847 13, 17, // 12049: case 0xd: {
5848 OPC_SwitchField, 3, 1, // 12051: switch Inst[3] {
5849 0, 5, // 12054: case 0x0: {
5850 OPC_Decode, 225, 22, 181, 1, // 12056: decode to XVSUBDP using decoder 181
5851 // 12056: }
5852 1, 0, // 12061: case 0x1: {
5853 OPC_Decode, 178, 22, 203, 1, // 12063: decode to XVMADDMDP using decoder 203
5854 // 12063: }
5855 // 12063: } // switch Inst[3]
5856 // 12063: }
5857 14, 17, // 12068: case 0xe: {
5858 OPC_SwitchField, 3, 1, // 12070: switch Inst[3] {
5859 0, 5, // 12073: case 0x0: {
5860 OPC_Decode, 188, 22, 181, 1, // 12075: decode to XVMULDP using decoder 181
5861 // 12075: }
5862 1, 0, // 12080: case 0x1: {
5863 OPC_Decode, 184, 22, 203, 1, // 12082: decode to XVMSUBADP using decoder 203
5864 // 12082: }
5865 // 12082: } // switch Inst[3]
5866 // 12082: }
5867 15, 17, // 12087: case 0xf: {
5868 OPC_SwitchField, 3, 1, // 12089: switch Inst[3] {
5869 0, 5, // 12092: case 0x0: {
5870 OPC_Decode, 252, 21, 181, 1, // 12094: decode to XVDIVDP using decoder 181
5871 // 12094: }
5872 1, 0, // 12099: case 0x1: {
5873 OPC_Decode, 186, 22, 203, 1, // 12101: decode to XVMSUBMDP using decoder 203
5874 // 12101: }
5875 // 12101: } // switch Inst[3]
5876 // 12101: }
5877 16, 17, // 12106: case 0x10: {
5878 OPC_SwitchField, 3, 1, // 12108: switch Inst[3] {
5879 0, 5, // 12111: case 0x0: {
5880 OPC_Decode, 252, 20, 201, 1, // 12113: decode to XSMAXCDP using decoder 201
5881 // 12113: }
5882 1, 0, // 12118: case 0x1: {
5883 OPC_Decode, 152, 21, 200, 1, // 12120: decode to XSNMADDASP using decoder 200
5884 // 12120: }
5885 // 12120: } // switch Inst[3]
5886 // 12120: }
5887 17, 17, // 12125: case 0x11: {
5888 OPC_SwitchField, 3, 1, // 12127: switch Inst[3] {
5889 0, 5, // 12130: case 0x0: {
5890 OPC_Decode, 132, 21, 201, 1, // 12132: decode to XSMINCDP using decoder 201
5891 // 12132: }
5892 1, 0, // 12137: case 0x1: {
5893 OPC_Decode, 154, 21, 200, 1, // 12139: decode to XSNMADDMSP using decoder 200
5894 // 12139: }
5895 // 12139: } // switch Inst[3]
5896 // 12139: }
5897 18, 17, // 12144: case 0x12: {
5898 OPC_SwitchField, 3, 1, // 12146: switch Inst[3] {
5899 0, 5, // 12149: case 0x0: {
5900 OPC_Decode, 255, 20, 204, 1, // 12151: decode to XSMAXJDP using decoder 204
5901 // 12151: }
5902 1, 0, // 12156: case 0x1: {
5903 OPC_Decode, 158, 21, 200, 1, // 12158: decode to XSNMSUBASP using decoder 200
5904 // 12158: }
5905 // 12158: } // switch Inst[3]
5906 // 12158: }
5907 19, 17, // 12163: case 0x13: {
5908 OPC_SwitchField, 3, 1, // 12165: switch Inst[3] {
5909 0, 5, // 12168: case 0x0: {
5910 OPC_Decode, 135, 21, 204, 1, // 12170: decode to XSMINJDP using decoder 204
5911 // 12170: }
5912 1, 0, // 12175: case 0x1: {
5913 OPC_Decode, 160, 21, 200, 1, // 12177: decode to XSNMSUBMSP using decoder 200
5914 // 12177: }
5915 // 12177: } // switch Inst[3]
5916 // 12177: }
5917 20, 17, // 12182: case 0x14: {
5918 OPC_SwitchField, 3, 1, // 12184: switch Inst[3] {
5919 0, 5, // 12187: case 0x0: {
5920 OPC_Decode, 254, 20, 201, 1, // 12189: decode to XSMAXDP using decoder 201
5921 // 12189: }
5922 1, 0, // 12194: case 0x1: {
5923 OPC_Decode, 151, 21, 202, 1, // 12196: decode to XSNMADDADP using decoder 202
5924 // 12196: }
5925 // 12196: } // switch Inst[3]
5926 // 12196: }
5927 21, 17, // 12201: case 0x15: {
5928 OPC_SwitchField, 3, 1, // 12203: switch Inst[3] {
5929 0, 5, // 12206: case 0x0: {
5930 OPC_Decode, 134, 21, 201, 1, // 12208: decode to XSMINDP using decoder 201
5931 // 12208: }
5932 1, 0, // 12213: case 0x1: {
5933 OPC_Decode, 153, 21, 202, 1, // 12215: decode to XSNMADDMDP using decoder 202
5934 // 12215: }
5935 // 12215: } // switch Inst[3]
5936 // 12215: }
5937 22, 17, // 12220: case 0x16: {
5938 OPC_SwitchField, 3, 1, // 12222: switch Inst[3] {
5939 0, 5, // 12225: case 0x0: {
5940 OPC_Decode, 207, 20, 201, 1, // 12227: decode to XSCPSGNDP using decoder 201
5941 // 12227: }
5942 1, 0, // 12232: case 0x1: {
5943 OPC_Decode, 157, 21, 202, 1, // 12234: decode to XSNMSUBADP using decoder 202
5944 // 12234: }
5945 // 12234: } // switch Inst[3]
5946 // 12234: }
5947 23, 17, // 12239: case 0x17: {
5948 OPC_SwitchField, 3, 1, // 12241: switch Inst[3] {
5949 0, 5, // 12244: case 0x0: {
5950 OPC_Decode, 215, 22, 181, 1, // 12246: decode to XVRLW using decoder 181
5951 // 12246: }
5952 1, 0, // 12251: case 0x1: {
5953 OPC_Decode, 159, 21, 202, 1, // 12253: decode to XSNMSUBMDP using decoder 202
5954 // 12253: }
5955 // 12253: } // switch Inst[3]
5956 // 12253: }
5957 24, 17, // 12258: case 0x18: {
5958 OPC_SwitchField, 3, 1, // 12260: switch Inst[3] {
5959 0, 5, // 12263: case 0x0: {
5960 OPC_Decode, 181, 22, 181, 1, // 12265: decode to XVMAXSP using decoder 181
5961 // 12265: }
5962 1, 0, // 12270: case 0x1: {
5963 OPC_Decode, 201, 22, 203, 1, // 12272: decode to XVNMADDASP using decoder 203
5964 // 12272: }
5965 // 12272: } // switch Inst[3]
5966 // 12272: }
5967 25, 17, // 12277: case 0x19: {
5968 OPC_SwitchField, 3, 1, // 12279: switch Inst[3] {
5969 0, 5, // 12282: case 0x0: {
5970 OPC_Decode, 183, 22, 181, 1, // 12284: decode to XVMINSP using decoder 181
5971 // 12284: }
5972 1, 0, // 12289: case 0x1: {
5973 OPC_Decode, 203, 22, 203, 1, // 12291: decode to XVNMADDMSP using decoder 203
5974 // 12291: }
5975 // 12291: } // switch Inst[3]
5976 // 12291: }
5977 26, 17, // 12296: case 0x1a: {
5978 OPC_SwitchField, 3, 1, // 12298: switch Inst[3] {
5979 0, 5, // 12301: case 0x0: {
5980 OPC_Decode, 229, 21, 181, 1, // 12303: decode to XVCPSGNSP using decoder 181
5981 // 12303: }
5982 1, 0, // 12308: case 0x1: {
5983 OPC_Decode, 205, 22, 203, 1, // 12310: decode to XVNMSUBASP using decoder 203
5984 // 12310: }
5985 // 12310: } // switch Inst[3]
5986 // 12310: }
5987 27, 17, // 12315: case 0x1b: {
5988 OPC_SwitchField, 3, 1, // 12317: switch Inst[3] {
5989 0, 5, // 12320: case 0x0: {
5990 OPC_Decode, 175, 22, 181, 1, // 12322: decode to XVIEXPSP using decoder 181
5991 // 12322: }
5992 1, 0, // 12327: case 0x1: {
5993 OPC_Decode, 207, 22, 203, 1, // 12329: decode to XVNMSUBMSP using decoder 203
5994 // 12329: }
5995 // 12329: } // switch Inst[3]
5996 // 12329: }
5997 28, 17, // 12334: case 0x1c: {
5998 OPC_SwitchField, 3, 1, // 12336: switch Inst[3] {
5999 0, 5, // 12339: case 0x0: {
6000 OPC_Decode, 180, 22, 181, 1, // 12341: decode to XVMAXDP using decoder 181
6001 // 12341: }
6002 1, 0, // 12346: case 0x1: {
6003 OPC_Decode, 200, 22, 203, 1, // 12348: decode to XVNMADDADP using decoder 203
6004 // 12348: }
6005 // 12348: } // switch Inst[3]
6006 // 12348: }
6007 29, 17, // 12353: case 0x1d: {
6008 OPC_SwitchField, 3, 1, // 12355: switch Inst[3] {
6009 0, 5, // 12358: case 0x0: {
6010 OPC_Decode, 182, 22, 181, 1, // 12360: decode to XVMINDP using decoder 181
6011 // 12360: }
6012 1, 0, // 12365: case 0x1: {
6013 OPC_Decode, 202, 22, 203, 1, // 12367: decode to XVNMADDMDP using decoder 203
6014 // 12367: }
6015 // 12367: } // switch Inst[3]
6016 // 12367: }
6017 30, 17, // 12372: case 0x1e: {
6018 OPC_SwitchField, 3, 1, // 12374: switch Inst[3] {
6019 0, 5, // 12377: case 0x0: {
6020 OPC_Decode, 228, 21, 181, 1, // 12379: decode to XVCPSGNDP using decoder 181
6021 // 12379: }
6022 1, 0, // 12384: case 0x1: {
6023 OPC_Decode, 204, 22, 203, 1, // 12386: decode to XVNMSUBADP using decoder 203
6024 // 12386: }
6025 // 12386: } // switch Inst[3]
6026 // 12386: }
6027 31, 0, // 12391: case 0x1f: {
6028 OPC_SwitchField, 3, 1, // 12393: switch Inst[3] {
6029 0, 5, // 12396: case 0x0: {
6030 OPC_Decode, 174, 22, 181, 1, // 12398: decode to XVIEXPDP using decoder 181
6031 // 12398: }
6032 1, 0, // 12403: case 0x1: {
6033 OPC_Decode, 206, 22, 203, 1, // 12405: decode to XVNMSUBMDP using decoder 203
6034 // 12405: }
6035 // 12405: } // switch Inst[3]
6036 // 12405: }
6037 // 12405: } // switch Inst[10:6]
6038 // 12405: }
6039 1, 178, 5, // 12410: case 0x1: {
6040 OPC_SwitchField, 6, 2, // 12413: switch Inst[7:6] {
6041 0, 153, 1, // 12416: case 0x0: {
6042 OPC_SwitchField, 3, 1, // 12419: switch Inst[3] {
6043 0, 79, // 12422: case 0x0: {
6044 OPC_SwitchField, 10, 1, // 12424: switch Inst[10] {
6045 0, 5, // 12427: case 0x0: {
6046 OPC_Decode, 160, 23, 205, 1, // 12429: decode to XXSLDWI using decoder 205
6047 // 12429: }
6048 1, 0, // 12434: case 0x1: {
6049 OPC_SwitchField, 8, 2, // 12436: switch Inst[9:8] {
6050 0, 5, // 12439: case 0x0: {
6051 OPC_Decode, 131, 23, 181, 1, // 12441: decode to XXLAND using decoder 181
6052 // 12441: }
6053 1, 5, // 12446: case 0x1: {
6054 OPC_Decode, 136, 23, 181, 1, // 12448: decode to XXLNOR using decoder 181
6055 // 12448: }
6056 2, 5, // 12453: case 0x2: {
6057 OPC_Decode, 241, 22, 206, 1, // 12455: decode to XXAESENCP using decoder 206
6058 // 12455: }
6059 3, 0, // 12460: case 0x3: {
6060 OPC_SwitchField, 16, 1, // 12462: switch Inst[16] {
6061 0, 17, // 12465: case 0x0: {
6062 OPC_CheckField, 21, 2, 0, // 12467: check Inst[22:21] == 0x0
6063 OPC_CheckField, 11, 1, 0, // 12471: check Inst[11] == 0x0
6064 OPC_CheckField, 0, 1, 0, // 12475: check Inst[0] == 0x0
6065 OPC_Decode, 201, 6, 207, 1, // 12479: decode to DMXXEXTFDMR512 using decoder 207
6066 // 12479: }
6067 1, 0, // 12484: case 0x1: {
6068 OPC_CheckField, 21, 2, 0, // 12486: check Inst[22:21] == 0x0
6069 OPC_CheckField, 11, 1, 0, // 12490: check Inst[11] == 0x0
6070 OPC_CheckField, 0, 1, 0, // 12494: check Inst[0] == 0x0
6071 OPC_Decode, 202, 6, 208, 1, // 12498: decode to DMXXEXTFDMR512_HI using decoder 208
6072 // 12498: }
6073 // 12498: } // switch Inst[16]
6074 // 12498: }
6075 // 12498: } // switch Inst[9:8]
6076 // 12498: }
6077 // 12498: } // switch Inst[10]
6078 // 12498: }
6079 1, 0, // 12503: case 0x1: {
6080 OPC_SwitchField, 8, 3, // 12505: switch Inst[10:8] {
6081 0, 5, // 12508: case 0x0: {
6082 OPC_Decode, 195, 20, 204, 1, // 12510: decode to XSCMPEQDP using decoder 204
6083 // 12510: }
6084 1, 13, // 12515: case 0x1: {
6085 OPC_CheckField, 21, 2, 0, // 12517: check Inst[22:21] == 0x0
6086 OPC_CheckField, 0, 1, 0, // 12521: check Inst[0] == 0x0
6087 OPC_Decode, 205, 20, 209, 1, // 12525: decode to XSCMPUDP using decoder 209
6088 // 12525: }
6089 2, 5, // 12530: case 0x2: {
6090 OPC_Decode, 218, 21, 181, 1, // 12532: decode to XVCMPEQSP using decoder 181
6091 // 12532: }
6092 3, 5, // 12537: case 0x3: {
6093 OPC_Decode, 216, 21, 181, 1, // 12539: decode to XVCMPEQDP using decoder 181
6094 // 12539: }
6095 4, 5, // 12544: case 0x4: {
6096 OPC_Decode, 205, 21, 181, 1, // 12546: decode to XVADDUWM using decoder 181
6097 // 12546: }
6098 5, 5, // 12551: case 0x5: {
6099 OPC_Decode, 195, 22, 181, 1, // 12553: decode to XVMULUWM using decoder 181
6100 // 12553: }
6101 6, 5, // 12558: case 0x6: {
6102 OPC_Decode, 219, 21, 181, 1, // 12560: decode to XVCMPEQSP_rec using decoder 181
6103 // 12560: }
6104 7, 0, // 12565: case 0x7: {
6105 OPC_Decode, 217, 21, 181, 1, // 12567: decode to XVCMPEQDP_rec using decoder 181
6106 // 12567: }
6107 // 12567: } // switch Inst[10:8]
6108 // 12567: }
6109 // 12567: } // switch Inst[3]
6110 // 12567: }
6111 1, 153, 1, // 12572: case 0x1: {
6112 OPC_SwitchField, 3, 1, // 12575: switch Inst[3] {
6113 0, 79, // 12578: case 0x0: {
6114 OPC_SwitchField, 10, 1, // 12580: switch Inst[10] {
6115 0, 5, // 12583: case 0x0: {
6116 OPC_Decode, 154, 23, 205, 1, // 12585: decode to XXPERMDI using decoder 205
6117 // 12585: }
6118 1, 0, // 12590: case 0x1: {
6119 OPC_SwitchField, 8, 2, // 12592: switch Inst[9:8] {
6120 0, 5, // 12595: case 0x0: {
6121 OPC_Decode, 132, 23, 181, 1, // 12597: decode to XXLANDC using decoder 181
6122 // 12597: }
6123 1, 5, // 12602: case 0x1: {
6124 OPC_Decode, 138, 23, 181, 1, // 12604: decode to XXLORC using decoder 181
6125 // 12604: }
6126 2, 5, // 12609: case 0x2: {
6127 OPC_Decode, 240, 22, 206, 1, // 12611: decode to XXAESDECP using decoder 206
6128 // 12611: }
6129 3, 0, // 12616: case 0x3: {
6130 OPC_SwitchField, 16, 1, // 12618: switch Inst[16] {
6131 0, 17, // 12621: case 0x0: {
6132 OPC_CheckField, 21, 2, 0, // 12623: check Inst[22:21] == 0x0
6133 OPC_CheckField, 11, 1, 0, // 12627: check Inst[11] == 0x0
6134 OPC_CheckField, 0, 1, 0, // 12631: check Inst[0] == 0x0
6135 OPC_Decode, 204, 6, 210, 1, // 12635: decode to DMXXINSTDMR512 using decoder 210
6136 // 12635: }
6137 1, 0, // 12640: case 0x1: {
6138 OPC_CheckField, 21, 2, 0, // 12642: check Inst[22:21] == 0x0
6139 OPC_CheckField, 11, 1, 0, // 12646: check Inst[11] == 0x0
6140 OPC_CheckField, 0, 1, 0, // 12650: check Inst[0] == 0x0
6141 OPC_Decode, 205, 6, 211, 1, // 12654: decode to DMXXINSTDMR512_HI using decoder 211
6142 // 12654: }
6143 // 12654: } // switch Inst[16]
6144 // 12654: }
6145 // 12654: } // switch Inst[9:8]
6146 // 12654: }
6147 // 12654: } // switch Inst[10]
6148 // 12654: }
6149 1, 0, // 12659: case 0x1: {
6150 OPC_SwitchField, 8, 3, // 12661: switch Inst[10:8] {
6151 0, 5, // 12664: case 0x0: {
6152 OPC_Decode, 201, 20, 204, 1, // 12666: decode to XSCMPGTDP using decoder 204
6153 // 12666: }
6154 1, 13, // 12671: case 0x1: {
6155 OPC_CheckField, 21, 2, 0, // 12673: check Inst[22:21] == 0x0
6156 OPC_CheckField, 0, 1, 0, // 12677: check Inst[0] == 0x0
6157 OPC_Decode, 203, 20, 209, 1, // 12681: decode to XSCMPODP using decoder 209
6158 // 12681: }
6159 2, 5, // 12686: case 0x2: {
6160 OPC_Decode, 226, 21, 181, 1, // 12688: decode to XVCMPGTSP using decoder 181
6161 // 12688: }
6162 3, 5, // 12693: case 0x3: {
6163 OPC_Decode, 224, 21, 181, 1, // 12695: decode to XVCMPGTDP using decoder 181
6164 // 12695: }
6165 4, 5, // 12700: case 0x4: {
6166 OPC_Decode, 204, 21, 181, 1, // 12702: decode to XVADDUHM using decoder 181
6167 // 12702: }
6168 5, 5, // 12707: case 0x5: {
6169 OPC_Decode, 194, 22, 181, 1, // 12709: decode to XVMULUHM using decoder 181
6170 // 12709: }
6171 6, 5, // 12714: case 0x6: {
6172 OPC_Decode, 227, 21, 181, 1, // 12716: decode to XVCMPGTSP_rec using decoder 181
6173 // 12716: }
6174 7, 0, // 12721: case 0x7: {
6175 OPC_Decode, 225, 21, 181, 1, // 12723: decode to XVCMPGTDP_rec using decoder 181
6176 // 12723: }
6177 // 12723: } // switch Inst[10:8]
6178 // 12723: }
6179 // 12723: } // switch Inst[3]
6180 // 12723: }
6181 2, 211, 1, // 12728: case 0x2: {
6182 OPC_SwitchField, 8, 3, // 12731: switch Inst[10:8] {
6183 0, 17, // 12734: case 0x0: {
6184 OPC_SwitchField, 3, 1, // 12736: switch Inst[3] {
6185 0, 5, // 12739: case 0x0: {
6186 OPC_Decode, 146, 23, 181, 1, // 12741: decode to XXMRGHW using decoder 181
6187 // 12741: }
6188 1, 0, // 12746: case 0x1: {
6189 OPC_Decode, 199, 20, 204, 1, // 12748: decode to XSCMPGEDP using decoder 204
6190 // 12748: }
6191 // 12748: } // switch Inst[3]
6192 // 12748: }
6193 1, 9, // 12753: case 0x1: {
6194 OPC_CheckField, 3, 1, 0, // 12755: check Inst[3] == 0x0
6195 OPC_Decode, 147, 23, 181, 1, // 12759: decode to XXMRGLW using decoder 181
6196 // 12759: }
6197 2, 33, // 12764: case 0x2: {
6198 OPC_SwitchField, 3, 1, // 12766: switch Inst[3] {
6199 0, 21, // 12769: case 0x0: {
6200 OPC_SwitchField, 2, 1, // 12771: switch Inst[2] {
6201 0, 9, // 12774: case 0x0: {
6202 OPC_CheckField, 18, 3, 0, // 12776: check Inst[20:18] == 0x0
6203 OPC_Decode, 166, 23, 212, 1, // 12780: decode to XXSPLTW using decoder 212
6204 // 12780: }
6205 1, 0, // 12785: case 0x1: {
6206 OPC_Decode, 252, 22, 213, 1, // 12787: decode to XXEXTRACTUW using decoder 213
6207 // 12787: }
6208 // 12787: } // switch Inst[2]
6209 // 12787: }
6210 1, 0, // 12792: case 0x1: {
6211 OPC_Decode, 222, 21, 181, 1, // 12794: decode to XVCMPGESP using decoder 181
6212 // 12794: }
6213 // 12794: } // switch Inst[3]
6214 // 12794: }
6215 3, 17, // 12799: case 0x3: {
6216 OPC_SwitchField, 3, 1, // 12801: switch Inst[3] {
6217 0, 5, // 12804: case 0x0: {
6218 OPC_Decode, 192, 22, 181, 1, // 12806: decode to XVMULHUW using decoder 181
6219 // 12806: }
6220 1, 0, // 12811: case 0x1: {
6221 OPC_Decode, 220, 21, 181, 1, // 12813: decode to XVCMPGEDP using decoder 181
6222 // 12813: }
6223 // 12813: } // switch Inst[3]
6224 // 12813: }
6225 4, 17, // 12818: case 0x4: {
6226 OPC_SwitchField, 3, 1, // 12820: switch Inst[3] {
6227 0, 5, // 12823: case 0x0: {
6228 OPC_Decode, 137, 23, 181, 1, // 12825: decode to XXLOR using decoder 181
6229 // 12825: }
6230 1, 0, // 12830: case 0x1: {
6231 OPC_Decode, 228, 22, 181, 1, // 12832: decode to XVSUBUWM using decoder 181
6232 // 12832: }
6233 // 12832: } // switch Inst[3]
6234 // 12832: }
6235 5, 17, // 12837: case 0x5: {
6236 OPC_SwitchField, 3, 1, // 12839: switch Inst[3] {
6237 0, 5, // 12842: case 0x0: {
6238 OPC_Decode, 135, 23, 181, 1, // 12844: decode to XXLNAND using decoder 181
6239 // 12844: }
6240 1, 0, // 12849: case 0x1: {
6241 OPC_Decode, 190, 22, 181, 1, // 12851: decode to XVMULHSW using decoder 181
6242 // 12851: }
6243 // 12851: } // switch Inst[3]
6244 // 12851: }
6245 6, 37, // 12856: case 0x6: {
6246 OPC_SwitchField, 3, 1, // 12858: switch Inst[3] {
6247 0, 25, // 12861: case 0x0: {
6248 OPC_SwitchField, 2, 1, // 12863: switch Inst[2] {
6249 0, 5, // 12866: case 0x0: {
6250 OPC_Decode, 242, 22, 214, 1, // 12868: decode to XXAESGENLKP using decoder 214
6251 // 12868: }
6252 1, 0, // 12873: case 0x1: {
6253 OPC_CheckField, 21, 2, 0, // 12875: check Inst[22:21] == 0x0
6254 OPC_CheckField, 0, 1, 0, // 12879: check Inst[0] == 0x0
6255 OPC_Decode, 207, 6, 215, 1, // 12883: decode to DMXXSHAPAD using decoder 215
6256 // 12883: }
6257 // 12883: } // switch Inst[2]
6258 // 12883: }
6259 1, 0, // 12888: case 0x1: {
6260 OPC_Decode, 223, 21, 181, 1, // 12890: decode to XVCMPGESP_rec using decoder 181
6261 // 12890: }
6262 // 12890: } // switch Inst[3]
6263 // 12890: }
6264 7, 0, // 12895: case 0x7: {
6265 OPC_SwitchField, 3, 1, // 12897: switch Inst[3] {
6266 0, 33, // 12900: case 0x0: {
6267 OPC_SwitchField, 2, 1, // 12902: switch Inst[2] {
6268 0, 13, // 12905: case 0x0: {
6269 OPC_CheckField, 17, 6, 0, // 12907: check Inst[22:17] == 0x0
6270 OPC_CheckField, 0, 1, 0, // 12911: check Inst[0] == 0x0
6271 OPC_Decode, 200, 6, 216, 1, // 12915: decode to DMXXEXTFDMR256 using decoder 216
6272 // 12915: }
6273 1, 0, // 12920: case 0x1: {
6274 OPC_CheckField, 17, 6, 0, // 12922: check Inst[22:17] == 0x0
6275 OPC_CheckField, 0, 1, 0, // 12926: check Inst[0] == 0x0
6276 OPC_Decode, 203, 6, 217, 1, // 12930: decode to DMXXINSTDMR256 using decoder 217
6277 // 12930: }
6278 // 12930: } // switch Inst[2]
6279 // 12930: }
6280 1, 0, // 12935: case 0x1: {
6281 OPC_Decode, 221, 21, 181, 1, // 12937: decode to XVCMPGEDP_rec using decoder 181
6282 // 12937: }
6283 // 12937: } // switch Inst[3]
6284 // 12937: }
6285 // 12937: } // switch Inst[10:8]
6286 // 12937: }
6287 3, 0, // 12942: case 0x3: {
6288 OPC_SwitchField, 9, 2, // 12944: switch Inst[10:9] {
6289 0, 41, // 12947: case 0x0: {
6290 OPC_SwitchField, 3, 1, // 12949: switch Inst[3] {
6291 0, 17, // 12952: case 0x0: {
6292 OPC_SwitchField, 8, 1, // 12954: switch Inst[8] {
6293 0, 5, // 12957: case 0x0: {
6294 OPC_Decode, 153, 23, 218, 1, // 12959: decode to XXPERM using decoder 218
6295 // 12959: }
6296 1, 0, // 12964: case 0x1: {
6297 OPC_Decode, 156, 23, 218, 1, // 12966: decode to XXPERMR using decoder 218
6298 // 12966: }
6299 // 12966: } // switch Inst[8]
6300 // 12966: }
6301 1, 0, // 12971: case 0x1: {
6302 OPC_CheckField, 21, 2, 0, // 12973: check Inst[22:21] == 0x0
6303 OPC_CheckField, 8, 1, 1, // 12977: check Inst[8] == 0x1
6304 OPC_CheckField, 0, 1, 0, // 12981: check Inst[0] == 0x0
6305 OPC_Decode, 197, 20, 209, 1, // 12985: decode to XSCMPEXPDP using decoder 209
6306 // 12985: }
6307 // 12985: } // switch Inst[3]
6308 // 12985: }
6309 1, 57, // 12990: case 0x1: {
6310 OPC_SwitchField, 8, 1, // 12992: switch Inst[8] {
6311 0, 41, // 12995: case 0x0: {
6312 OPC_SwitchField, 2, 2, // 12997: switch Inst[3:2] {
6313 0, 29, // 13000: case 0x0: {
6314 OPC_SwitchField, 19, 2, // 13002: switch Inst[20:19] {
6315 0, 9, // 13005: case 0x0: {
6316 OPC_CheckField, 1, 1, 0, // 13007: check Inst[1] == 0x0
6317 OPC_Decode, 163, 23, 219, 1, // 13011: decode to XXSPLTIB using decoder 219
6318 // 13011: }
6319 3, 0, // 13016: case 0x3: {
6320 OPC_CheckField, 16, 3, 7, // 13018: check Inst[18:16] == 0x7
6321 OPC_CheckField, 1, 1, 0, // 13022: check Inst[1] == 0x0
6322 OPC_Decode, 196, 11, 220, 1, // 13026: decode to LXVKQ using decoder 220
6323 // 13026: }
6324 // 13026: } // switch Inst[20:19]
6325 // 13026: }
6326 1, 0, // 13031: case 0x1: {
6327 OPC_Decode, 130, 23, 221, 1, // 13033: decode to XXINSERTW using decoder 221
6328 // 13033: }
6329 // 13033: } // switch Inst[3:2]
6330 // 13033: }
6331 1, 0, // 13038: case 0x1: {
6332 OPC_CheckField, 3, 1, 0, // 13040: check Inst[3] == 0x0
6333 OPC_Decode, 191, 22, 181, 1, // 13044: decode to XVMULHUH using decoder 181
6334 // 13044: }
6335 // 13044: } // switch Inst[8]
6336 // 13044: }
6337 2, 41, // 13049: case 0x2: {
6338 OPC_SwitchField, 3, 1, // 13051: switch Inst[3] {
6339 0, 17, // 13054: case 0x0: {
6340 OPC_SwitchField, 8, 1, // 13056: switch Inst[8] {
6341 0, 5, // 13059: case 0x0: {
6342 OPC_Decode, 140, 23, 181, 1, // 13061: decode to XXLXOR using decoder 181
6343 // 13061: }
6344 1, 0, // 13066: case 0x1: {
6345 OPC_Decode, 133, 23, 181, 1, // 13068: decode to XXLEQV using decoder 181
6346 // 13068: }
6347 // 13068: } // switch Inst[8]
6348 // 13068: }
6349 1, 0, // 13073: case 0x1: {
6350 OPC_SwitchField, 8, 1, // 13075: switch Inst[8] {
6351 0, 5, // 13078: case 0x0: {
6352 OPC_Decode, 227, 22, 181, 1, // 13080: decode to XVSUBUHM using decoder 181
6353 // 13080: }
6354 1, 0, // 13085: case 0x1: {
6355 OPC_Decode, 189, 22, 181, 1, // 13087: decode to XVMULHSH using decoder 181
6356 // 13087: }
6357 // 13087: } // switch Inst[8]
6358 // 13087: }
6359 // 13087: } // switch Inst[3]
6360 // 13087: }
6361 3, 0, // 13092: case 0x3: {
6362 OPC_CheckField, 3, 1, 0, // 13094: check Inst[3] == 0x0
6363 OPC_Decode, 129, 23, 222, 1, // 13098: decode to XXGFMUL128 using decoder 222
6364 // 13098: }
6365 // 13098: } // switch Inst[10:9]
6366 // 13098: }
6367 // 13098: } // switch Inst[7:6]
6368 // 13098: }
6369 2, 234, 10, // 13103: case 0x2: {
6370 OPC_SwitchField, 7, 4, // 13106: switch Inst[10:7] {
6371 0, 45, // 13109: case 0x0: {
6372 OPC_SwitchField, 2, 2, // 13111: switch Inst[3:2] {
6373 2, 25, // 13114: case 0x2: {
6374 OPC_SwitchField, 6, 1, // 13116: switch Inst[6] {
6375 0, 9, // 13119: case 0x0: {
6376 OPC_CheckField, 16, 5, 0, // 13121: check Inst[20:16] == 0x0
6377 OPC_Decode, 182, 21, 223, 1, // 13125: decode to XSRSQRTESP using decoder 223
6378 // 13125: }
6379 1, 0, // 13130: case 0x1: {
6380 OPC_CheckField, 16, 5, 0, // 13132: check Inst[20:16] == 0x0
6381 OPC_Decode, 176, 21, 223, 1, // 13136: decode to XSRESP using decoder 223
6382 // 13136: }
6383 // 13136: } // switch Inst[6]
6384 // 13136: }
6385 3, 0, // 13141: case 0x3: {
6386 OPC_CheckField, 16, 5, 0, // 13143: check Inst[20:16] == 0x0
6387 OPC_CheckField, 6, 1, 0, // 13147: check Inst[6] == 0x0
6388 OPC_Decode, 186, 21, 223, 1, // 13151: decode to XSSQRTSP using decoder 223
6389 // 13151: }
6390 // 13151: } // switch Inst[3:2]
6391 // 13151: }
6392 2, 99, // 13156: case 0x2: {
6393 OPC_SwitchField, 2, 2, // 13158: switch Inst[3:2] {
6394 0, 25, // 13161: case 0x0: {
6395 OPC_SwitchField, 6, 1, // 13163: switch Inst[6] {
6396 0, 9, // 13166: case 0x0: {
6397 OPC_CheckField, 16, 5, 0, // 13168: check Inst[20:16] == 0x0
6398 OPC_Decode, 219, 20, 224, 1, // 13172: decode to XSCVDPUXWS using decoder 224
6399 // 13172: }
6400 1, 0, // 13177: case 0x1: {
6401 OPC_CheckField, 16, 5, 0, // 13179: check Inst[20:16] == 0x0
6402 OPC_Decode, 215, 20, 224, 1, // 13183: decode to XSCVDPSXWS using decoder 224
6403 // 13183: }
6404 // 13183: } // switch Inst[6]
6405 // 13183: }
6406 1, 25, // 13188: case 0x1: {
6407 OPC_SwitchField, 6, 1, // 13190: switch Inst[6] {
6408 0, 9, // 13193: case 0x0: {
6409 OPC_CheckField, 16, 5, 0, // 13195: check Inst[20:16] == 0x0
6410 OPC_Decode, 163, 21, 224, 1, // 13199: decode to XSRDPI using decoder 224
6411 // 13199: }
6412 1, 0, // 13204: case 0x1: {
6413 OPC_CheckField, 16, 5, 0, // 13206: check Inst[20:16] == 0x0
6414 OPC_Decode, 167, 21, 224, 1, // 13210: decode to XSRDPIZ using decoder 224
6415 // 13210: }
6416 // 13210: } // switch Inst[6]
6417 // 13210: }
6418 2, 25, // 13215: case 0x2: {
6419 OPC_SwitchField, 6, 1, // 13217: switch Inst[6] {
6420 0, 9, // 13220: case 0x0: {
6421 OPC_CheckField, 16, 5, 0, // 13222: check Inst[20:16] == 0x0
6422 OPC_Decode, 181, 21, 224, 1, // 13226: decode to XSRSQRTEDP using decoder 224
6423 // 13226: }
6424 1, 0, // 13231: case 0x1: {
6425 OPC_CheckField, 16, 5, 0, // 13233: check Inst[20:16] == 0x0
6426 OPC_Decode, 175, 21, 224, 1, // 13237: decode to XSREDP using decoder 224
6427 // 13237: }
6428 // 13237: } // switch Inst[6]
6429 // 13237: }
6430 3, 0, // 13242: case 0x3: {
6431 OPC_CheckField, 16, 5, 0, // 13244: check Inst[20:16] == 0x0
6432 OPC_CheckField, 6, 1, 0, // 13248: check Inst[6] == 0x0
6433 OPC_Decode, 183, 21, 224, 1, // 13252: decode to XSSQRTDP using decoder 224
6434 // 13252: }
6435 // 13252: } // switch Inst[3:2]
6436 // 13252: }
6437 3, 89, // 13257: case 0x3: {
6438 OPC_SwitchField, 3, 1, // 13259: switch Inst[3] {
6439 0, 33, // 13262: case 0x0: {
6440 OPC_SwitchField, 6, 1, // 13264: switch Inst[6] {
6441 0, 13, // 13267: case 0x0: {
6442 OPC_CheckField, 16, 5, 0, // 13269: check Inst[20:16] == 0x0
6443 OPC_CheckField, 2, 1, 1, // 13273: check Inst[2] == 0x1
6444 OPC_Decode, 166, 21, 224, 1, // 13277: decode to XSRDPIP using decoder 224
6445 // 13277: }
6446 1, 0, // 13282: case 0x1: {
6447 OPC_CheckField, 16, 5, 0, // 13284: check Inst[20:16] == 0x0
6448 OPC_CheckField, 2, 1, 1, // 13288: check Inst[2] == 0x1
6449 OPC_Decode, 165, 21, 224, 1, // 13292: decode to XSRDPIM using decoder 224
6450 // 13292: }
6451 // 13292: } // switch Inst[6]
6452 // 13292: }
6453 1, 0, // 13297: case 0x1: {
6454 OPC_SwitchField, 6, 1, // 13299: switch Inst[6] {
6455 0, 29, // 13302: case 0x0: {
6456 OPC_SwitchField, 2, 1, // 13304: switch Inst[2] {
6457 0, 13, // 13307: case 0x0: {
6458 OPC_CheckField, 16, 7, 0, // 13309: check Inst[22:16] == 0x0
6459 OPC_CheckField, 0, 1, 0, // 13313: check Inst[0] == 0x0
6460 OPC_Decode, 192, 21, 225, 1, // 13317: decode to XSTSQRTDP using decoder 225
6461 // 13317: }
6462 1, 0, // 13322: case 0x1: {
6463 OPC_CheckField, 16, 5, 0, // 13324: check Inst[20:16] == 0x0
6464 OPC_Decode, 164, 21, 224, 1, // 13328: decode to XSRDPIC using decoder 224
6465 // 13328: }
6466 // 13328: } // switch Inst[2]
6467 // 13328: }
6468 1, 0, // 13333: case 0x1: {
6469 OPC_CheckField, 21, 2, 0, // 13335: check Inst[22:21] == 0x0
6470 OPC_CheckField, 0, 1, 0, // 13339: check Inst[0] == 0x0
6471 OPC_Decode, 191, 21, 209, 1, // 13343: decode to XSTDIVDP using decoder 209
6472 // 13343: }
6473 // 13343: } // switch Inst[6]
6474 // 13343: }
6475 // 13343: } // switch Inst[3]
6476 // 13343: }
6477 4, 99, // 13348: case 0x4: {
6478 OPC_SwitchField, 2, 2, // 13350: switch Inst[3:2] {
6479 0, 25, // 13353: case 0x0: {
6480 OPC_SwitchField, 6, 1, // 13355: switch Inst[6] {
6481 0, 9, // 13358: case 0x0: {
6482 OPC_CheckField, 16, 5, 0, // 13360: check Inst[20:16] == 0x0
6483 OPC_Decode, 243, 21, 226, 1, // 13364: decode to XVCVSPUXWS using decoder 226
6484 // 13364: }
6485 1, 0, // 13369: case 0x1: {
6486 OPC_CheckField, 16, 5, 0, // 13371: check Inst[20:16] == 0x0
6487 OPC_Decode, 241, 21, 226, 1, // 13375: decode to XVCVSPSXWS using decoder 226
6488 // 13375: }
6489 // 13375: } // switch Inst[6]
6490 // 13375: }
6491 1, 25, // 13380: case 0x1: {
6492 OPC_SwitchField, 6, 1, // 13382: switch Inst[6] {
6493 0, 9, // 13385: case 0x0: {
6494 OPC_CheckField, 16, 5, 0, // 13387: check Inst[20:16] == 0x0
6495 OPC_Decode, 216, 22, 226, 1, // 13391: decode to XVRSPI using decoder 226
6496 // 13391: }
6497 1, 0, // 13396: case 0x1: {
6498 OPC_CheckField, 16, 5, 0, // 13398: check Inst[20:16] == 0x0
6499 OPC_Decode, 220, 22, 226, 1, // 13402: decode to XVRSPIZ using decoder 226
6500 // 13402: }
6501 // 13402: } // switch Inst[6]
6502 // 13402: }
6503 2, 25, // 13407: case 0x2: {
6504 OPC_SwitchField, 6, 1, // 13409: switch Inst[6] {
6505 0, 9, // 13412: case 0x0: {
6506 OPC_CheckField, 16, 5, 0, // 13414: check Inst[20:16] == 0x0
6507 OPC_Decode, 222, 22, 226, 1, // 13418: decode to XVRSQRTESP using decoder 226
6508 // 13418: }
6509 1, 0, // 13423: case 0x1: {
6510 OPC_CheckField, 16, 5, 0, // 13425: check Inst[20:16] == 0x0
6511 OPC_Decode, 214, 22, 226, 1, // 13429: decode to XVRESP using decoder 226
6512 // 13429: }
6513 // 13429: } // switch Inst[6]
6514 // 13429: }
6515 3, 0, // 13434: case 0x3: {
6516 OPC_CheckField, 16, 5, 0, // 13436: check Inst[20:16] == 0x0
6517 OPC_CheckField, 6, 1, 0, // 13440: check Inst[6] == 0x0
6518 OPC_Decode, 224, 22, 226, 1, // 13444: decode to XVSQRTSP using decoder 226
6519 // 13444: }
6520 // 13444: } // switch Inst[3:2]
6521 // 13444: }
6522 5, 113, // 13449: case 0x5: {
6523 OPC_SwitchField, 3, 1, // 13451: switch Inst[3] {
6524 0, 57, // 13454: case 0x0: {
6525 OPC_SwitchField, 2, 1, // 13456: switch Inst[2] {
6526 0, 25, // 13459: case 0x0: {
6527 OPC_SwitchField, 6, 1, // 13461: switch Inst[6] {
6528 0, 9, // 13464: case 0x0: {
6529 OPC_CheckField, 16, 5, 0, // 13466: check Inst[20:16] == 0x0
6530 OPC_Decode, 251, 21, 226, 1, // 13470: decode to XVCVUXWSP using decoder 226
6531 // 13470: }
6532 1, 0, // 13475: case 0x1: {
6533 OPC_CheckField, 16, 5, 0, // 13477: check Inst[20:16] == 0x0
6534 OPC_Decode, 247, 21, 226, 1, // 13481: decode to XVCVSXWSP using decoder 226
6535 // 13481: }
6536 // 13481: } // switch Inst[6]
6537 // 13481: }
6538 1, 0, // 13486: case 0x1: {
6539 OPC_SwitchField, 6, 1, // 13488: switch Inst[6] {
6540 0, 9, // 13491: case 0x0: {
6541 OPC_CheckField, 16, 5, 0, // 13493: check Inst[20:16] == 0x0
6542 OPC_Decode, 219, 22, 226, 1, // 13497: decode to XVRSPIP using decoder 226
6543 // 13497: }
6544 1, 0, // 13502: case 0x1: {
6545 OPC_CheckField, 16, 5, 0, // 13504: check Inst[20:16] == 0x0
6546 OPC_Decode, 218, 22, 226, 1, // 13508: decode to XVRSPIM using decoder 226
6547 // 13508: }
6548 // 13508: } // switch Inst[6]
6549 // 13508: }
6550 // 13508: } // switch Inst[2]
6551 // 13508: }
6552 1, 0, // 13513: case 0x1: {
6553 OPC_SwitchField, 6, 1, // 13515: switch Inst[6] {
6554 0, 29, // 13518: case 0x0: {
6555 OPC_SwitchField, 2, 1, // 13520: switch Inst[2] {
6556 0, 13, // 13523: case 0x0: {
6557 OPC_CheckField, 16, 7, 0, // 13525: check Inst[22:16] == 0x0
6558 OPC_CheckField, 0, 1, 0, // 13529: check Inst[0] == 0x0
6559 OPC_Decode, 233, 22, 227, 1, // 13533: decode to XVTSQRTSP using decoder 227
6560 // 13533: }
6561 1, 0, // 13538: case 0x1: {
6562 OPC_CheckField, 16, 5, 0, // 13540: check Inst[20:16] == 0x0
6563 OPC_Decode, 217, 22, 226, 1, // 13544: decode to XVRSPIC using decoder 226
6564 // 13544: }
6565 // 13544: } // switch Inst[2]
6566 // 13544: }
6567 1, 0, // 13549: case 0x1: {
6568 OPC_CheckField, 21, 2, 0, // 13551: check Inst[22:21] == 0x0
6569 OPC_CheckField, 0, 1, 0, // 13555: check Inst[0] == 0x0
6570 OPC_Decode, 230, 22, 228, 1, // 13559: decode to XVTDIVSP using decoder 228
6571 // 13559: }
6572 // 13559: } // switch Inst[6]
6573 // 13559: }
6574 // 13559: } // switch Inst[3]
6575 // 13559: }
6576 6, 99, // 13564: case 0x6: {
6577 OPC_SwitchField, 2, 2, // 13566: switch Inst[3:2] {
6578 0, 25, // 13569: case 0x0: {
6579 OPC_SwitchField, 6, 1, // 13571: switch Inst[6] {
6580 0, 9, // 13574: case 0x0: {
6581 OPC_CheckField, 16, 5, 0, // 13576: check Inst[20:16] == 0x0
6582 OPC_Decode, 235, 21, 226, 1, // 13580: decode to XVCVDPUXWS using decoder 226
6583 // 13580: }
6584 1, 0, // 13585: case 0x1: {
6585 OPC_CheckField, 16, 5, 0, // 13587: check Inst[20:16] == 0x0
6586 OPC_Decode, 233, 21, 226, 1, // 13591: decode to XVCVDPSXWS using decoder 226
6587 // 13591: }
6588 // 13591: } // switch Inst[6]
6589 // 13591: }
6590 1, 25, // 13596: case 0x1: {
6591 OPC_SwitchField, 6, 1, // 13598: switch Inst[6] {
6592 0, 9, // 13601: case 0x0: {
6593 OPC_CheckField, 16, 5, 0, // 13603: check Inst[20:16] == 0x0
6594 OPC_Decode, 208, 22, 226, 1, // 13607: decode to XVRDPI using decoder 226
6595 // 13607: }
6596 1, 0, // 13612: case 0x1: {
6597 OPC_CheckField, 16, 5, 0, // 13614: check Inst[20:16] == 0x0
6598 OPC_Decode, 212, 22, 226, 1, // 13618: decode to XVRDPIZ using decoder 226
6599 // 13618: }
6600 // 13618: } // switch Inst[6]
6601 // 13618: }
6602 2, 25, // 13623: case 0x2: {
6603 OPC_SwitchField, 6, 1, // 13625: switch Inst[6] {
6604 0, 9, // 13628: case 0x0: {
6605 OPC_CheckField, 16, 5, 0, // 13630: check Inst[20:16] == 0x0
6606 OPC_Decode, 221, 22, 226, 1, // 13634: decode to XVRSQRTEDP using decoder 226
6607 // 13634: }
6608 1, 0, // 13639: case 0x1: {
6609 OPC_CheckField, 16, 5, 0, // 13641: check Inst[20:16] == 0x0
6610 OPC_Decode, 213, 22, 226, 1, // 13645: decode to XVREDP using decoder 226
6611 // 13645: }
6612 // 13645: } // switch Inst[6]
6613 // 13645: }
6614 3, 0, // 13650: case 0x3: {
6615 OPC_CheckField, 16, 5, 0, // 13652: check Inst[20:16] == 0x0
6616 OPC_CheckField, 6, 1, 0, // 13656: check Inst[6] == 0x0
6617 OPC_Decode, 223, 22, 226, 1, // 13660: decode to XVSQRTDP using decoder 226
6618 // 13660: }
6619 // 13660: } // switch Inst[3:2]
6620 // 13660: }
6621 7, 113, // 13665: case 0x7: {
6622 OPC_SwitchField, 3, 1, // 13667: switch Inst[3] {
6623 0, 57, // 13670: case 0x0: {
6624 OPC_SwitchField, 2, 1, // 13672: switch Inst[2] {
6625 0, 25, // 13675: case 0x0: {
6626 OPC_SwitchField, 6, 1, // 13677: switch Inst[6] {
6627 0, 9, // 13680: case 0x0: {
6628 OPC_CheckField, 16, 5, 0, // 13682: check Inst[20:16] == 0x0
6629 OPC_Decode, 250, 21, 226, 1, // 13686: decode to XVCVUXWDP using decoder 226
6630 // 13686: }
6631 1, 0, // 13691: case 0x1: {
6632 OPC_CheckField, 16, 5, 0, // 13693: check Inst[20:16] == 0x0
6633 OPC_Decode, 246, 21, 226, 1, // 13697: decode to XVCVSXWDP using decoder 226
6634 // 13697: }
6635 // 13697: } // switch Inst[6]
6636 // 13697: }
6637 1, 0, // 13702: case 0x1: {
6638 OPC_SwitchField, 6, 1, // 13704: switch Inst[6] {
6639 0, 9, // 13707: case 0x0: {
6640 OPC_CheckField, 16, 5, 0, // 13709: check Inst[20:16] == 0x0
6641 OPC_Decode, 211, 22, 226, 1, // 13713: decode to XVRDPIP using decoder 226
6642 // 13713: }
6643 1, 0, // 13718: case 0x1: {
6644 OPC_CheckField, 16, 5, 0, // 13720: check Inst[20:16] == 0x0
6645 OPC_Decode, 210, 22, 226, 1, // 13724: decode to XVRDPIM using decoder 226
6646 // 13724: }
6647 // 13724: } // switch Inst[6]
6648 // 13724: }
6649 // 13724: } // switch Inst[2]
6650 // 13724: }
6651 1, 0, // 13729: case 0x1: {
6652 OPC_SwitchField, 6, 1, // 13731: switch Inst[6] {
6653 0, 29, // 13734: case 0x0: {
6654 OPC_SwitchField, 2, 1, // 13736: switch Inst[2] {
6655 0, 13, // 13739: case 0x0: {
6656 OPC_CheckField, 16, 7, 0, // 13741: check Inst[22:16] == 0x0
6657 OPC_CheckField, 0, 1, 0, // 13745: check Inst[0] == 0x0
6658 OPC_Decode, 232, 22, 227, 1, // 13749: decode to XVTSQRTDP using decoder 227
6659 // 13749: }
6660 1, 0, // 13754: case 0x1: {
6661 OPC_CheckField, 16, 5, 0, // 13756: check Inst[20:16] == 0x0
6662 OPC_Decode, 209, 22, 226, 1, // 13760: decode to XVRDPIC using decoder 226
6663 // 13760: }
6664 // 13760: } // switch Inst[2]
6665 // 13760: }
6666 1, 0, // 13765: case 0x1: {
6667 OPC_CheckField, 21, 2, 0, // 13767: check Inst[22:21] == 0x0
6668 OPC_CheckField, 0, 1, 0, // 13771: check Inst[0] == 0x0
6669 OPC_Decode, 229, 22, 228, 1, // 13775: decode to XVTDIVDP using decoder 228
6670 // 13775: }
6671 // 13775: } // switch Inst[6]
6672 // 13775: }
6673 // 13775: } // switch Inst[3]
6674 // 13775: }
6675 8, 45, // 13780: case 0x8: {
6676 OPC_SwitchField, 2, 2, // 13782: switch Inst[3:2] {
6677 1, 25, // 13785: case 0x1: {
6678 OPC_SwitchField, 6, 1, // 13787: switch Inst[6] {
6679 0, 9, // 13790: case 0x0: {
6680 OPC_CheckField, 16, 5, 0, // 13792: check Inst[20:16] == 0x0
6681 OPC_Decode, 211, 20, 224, 1, // 13796: decode to XSCVDPSP using decoder 224
6682 // 13796: }
6683 1, 0, // 13801: case 0x1: {
6684 OPC_CheckField, 16, 5, 0, // 13803: check Inst[20:16] == 0x0
6685 OPC_Decode, 180, 21, 229, 1, // 13807: decode to XSRSP using decoder 229
6686 // 13807: }
6687 // 13807: } // switch Inst[6]
6688 // 13807: }
6689 3, 0, // 13812: case 0x3: {
6690 OPC_CheckField, 16, 5, 0, // 13814: check Inst[20:16] == 0x0
6691 OPC_CheckField, 6, 1, 0, // 13818: check Inst[6] == 0x0
6692 OPC_Decode, 212, 20, 230, 1, // 13822: decode to XSCVDPSPN using decoder 230
6693 // 13822: }
6694 // 13822: } // switch Inst[3:2]
6695 // 13822: }
6696 9, 45, // 13827: case 0x9: {
6697 OPC_SwitchField, 2, 2, // 13829: switch Inst[3:2] {
6698 0, 25, // 13832: case 0x0: {
6699 OPC_SwitchField, 6, 1, // 13834: switch Inst[6] {
6700 0, 9, // 13837: case 0x0: {
6701 OPC_CheckField, 16, 5, 0, // 13839: check Inst[20:16] == 0x0
6702 OPC_Decode, 239, 20, 229, 1, // 13843: decode to XSCVUXDSP using decoder 229
6703 // 13843: }
6704 1, 0, // 13848: case 0x1: {
6705 OPC_CheckField, 16, 5, 0, // 13850: check Inst[20:16] == 0x0
6706 OPC_Decode, 235, 20, 229, 1, // 13854: decode to XSCVSXDSP using decoder 229
6707 // 13854: }
6708 // 13854: } // switch Inst[6]
6709 // 13854: }
6710 2, 0, // 13859: case 0x2: {
6711 OPC_CheckField, 6, 1, 0, // 13861: check Inst[6] == 0x0
6712 OPC_CheckField, 0, 1, 0, // 13865: check Inst[0] == 0x0
6713 OPC_Decode, 195, 21, 231, 1, // 13869: decode to XSTSTDCSP using decoder 231
6714 // 13869: }
6715 // 13869: } // switch Inst[3:2]
6716 // 13869: }
6717 10, 118, // 13874: case 0xa: {
6718 OPC_SwitchField, 16, 5, // 13876: switch Inst[20:16] {
6719 0, 64, // 13879: case 0x0: {
6720 OPC_SwitchField, 2, 2, // 13881: switch Inst[3:2] {
6721 0, 17, // 13884: case 0x0: {
6722 OPC_SwitchField, 6, 1, // 13886: switch Inst[6] {
6723 0, 5, // 13889: case 0x0: {
6724 OPC_Decode, 217, 20, 224, 1, // 13891: decode to XSCVDPUXDS using decoder 224
6725 // 13891: }
6726 1, 0, // 13896: case 0x1: {
6727 OPC_Decode, 213, 20, 224, 1, // 13898: decode to XSCVDPSXDS using decoder 224
6728 // 13898: }
6729 // 13898: } // switch Inst[6]
6730 // 13898: }
6731 1, 17, // 13903: case 0x1: {
6732 OPC_SwitchField, 6, 1, // 13905: switch Inst[6] {
6733 0, 5, // 13908: case 0x0: {
6734 OPC_Decode, 231, 20, 224, 1, // 13910: decode to XSCVSPDP using decoder 224
6735 // 13910: }
6736 1, 0, // 13915: case 0x1: {
6737 OPC_Decode, 185, 20, 224, 1, // 13917: decode to XSABSDP using decoder 224
6738 // 13917: }
6739 // 13917: } // switch Inst[6]
6740 // 13917: }
6741 3, 0, // 13922: case 0x3: {
6742 OPC_SwitchField, 6, 1, // 13924: switch Inst[6] {
6743 0, 5, // 13927: case 0x0: {
6744 OPC_Decode, 232, 20, 232, 1, // 13929: decode to XSCVSPDPN using decoder 232
6745 // 13929: }
6746 1, 0, // 13934: case 0x1: {
6747 OPC_CheckField, 0, 1, 0, // 13936: check Inst[0] == 0x0
6748 OPC_Decode, 196, 21, 233, 1, // 13940: decode to XSXEXPDP using decoder 233
6749 // 13940: }
6750 // 13940: } // switch Inst[6]
6751 // 13940: }
6752 // 13940: } // switch Inst[3:2]
6753 // 13940: }
6754 1, 17, // 13945: case 0x1: {
6755 OPC_CheckField, 6, 1, 1, // 13947: check Inst[6] == 0x1
6756 OPC_CheckField, 2, 2, 3, // 13951: check Inst[3:2] == 0x3
6757 OPC_CheckField, 0, 1, 0, // 13955: check Inst[0] == 0x0
6758 OPC_Decode, 198, 21, 233, 1, // 13959: decode to XSXSIGDP using decoder 233
6759 // 13959: }
6760 16, 13, // 13964: case 0x10: {
6761 OPC_CheckField, 6, 1, 1, // 13966: check Inst[6] == 0x1
6762 OPC_CheckField, 2, 2, 3, // 13970: check Inst[3:2] == 0x3
6763 OPC_Decode, 221, 20, 224, 1, // 13974: decode to XSCVHPDP using decoder 224
6764 // 13974: }
6765 17, 0, // 13979: case 0x11: {
6766 OPC_CheckField, 6, 1, 1, // 13981: check Inst[6] == 0x1
6767 OPC_CheckField, 2, 2, 3, // 13985: check Inst[3:2] == 0x3
6768 OPC_Decode, 209, 20, 224, 1, // 13989: decode to XSCVDPHP using decoder 224
6769 // 13989: }
6770 // 13989: } // switch Inst[20:16]
6771 // 13989: }
6772 11, 72, // 13994: case 0xb: {
6773 OPC_SwitchField, 2, 2, // 13996: switch Inst[3:2] {
6774 0, 25, // 13999: case 0x0: {
6775 OPC_SwitchField, 6, 1, // 14001: switch Inst[6] {
6776 0, 9, // 14004: case 0x0: {
6777 OPC_CheckField, 16, 5, 0, // 14006: check Inst[20:16] == 0x0
6778 OPC_Decode, 238, 20, 224, 1, // 14010: decode to XSCVUXDDP using decoder 224
6779 // 14010: }
6780 1, 0, // 14015: case 0x1: {
6781 OPC_CheckField, 16, 5, 0, // 14017: check Inst[20:16] == 0x0
6782 OPC_Decode, 234, 20, 224, 1, // 14021: decode to XSCVSXDDP using decoder 224
6783 // 14021: }
6784 // 14021: } // switch Inst[6]
6785 // 14021: }
6786 1, 25, // 14026: case 0x1: {
6787 OPC_SwitchField, 6, 1, // 14028: switch Inst[6] {
6788 0, 9, // 14031: case 0x0: {
6789 OPC_CheckField, 16, 5, 0, // 14033: check Inst[20:16] == 0x0
6790 OPC_Decode, 146, 21, 224, 1, // 14037: decode to XSNABSDP using decoder 224
6791 // 14037: }
6792 1, 0, // 14042: case 0x1: {
6793 OPC_CheckField, 16, 5, 0, // 14044: check Inst[20:16] == 0x0
6794 OPC_Decode, 149, 21, 224, 1, // 14048: decode to XSNEGDP using decoder 224
6795 // 14048: }
6796 // 14048: } // switch Inst[6]
6797 // 14048: }
6798 2, 0, // 14053: case 0x2: {
6799 OPC_CheckField, 6, 1, 0, // 14055: check Inst[6] == 0x0
6800 OPC_CheckField, 0, 1, 0, // 14059: check Inst[0] == 0x0
6801 OPC_Decode, 193, 21, 234, 1, // 14063: decode to XSTSTDCDP using decoder 234
6802 // 14063: }
6803 // 14063: } // switch Inst[3:2]
6804 // 14063: }
6805 12, 57, // 14068: case 0xc: {
6806 OPC_SwitchField, 2, 2, // 14070: switch Inst[3:2] {
6807 0, 25, // 14073: case 0x0: {
6808 OPC_SwitchField, 6, 1, // 14075: switch Inst[6] {
6809 0, 9, // 14078: case 0x0: {
6810 OPC_CheckField, 16, 5, 0, // 14080: check Inst[20:16] == 0x0
6811 OPC_Decode, 242, 21, 226, 1, // 14084: decode to XVCVSPUXDS using decoder 226
6812 // 14084: }
6813 1, 0, // 14089: case 0x1: {
6814 OPC_CheckField, 16, 5, 0, // 14091: check Inst[20:16] == 0x0
6815 OPC_Decode, 240, 21, 226, 1, // 14095: decode to XVCVSPSXDS using decoder 226
6816 // 14095: }
6817 // 14095: } // switch Inst[6]
6818 // 14095: }
6819 1, 0, // 14100: case 0x1: {
6820 OPC_SwitchField, 6, 1, // 14102: switch Inst[6] {
6821 0, 9, // 14105: case 0x0: {
6822 OPC_CheckField, 16, 5, 0, // 14107: check Inst[20:16] == 0x0
6823 OPC_Decode, 231, 21, 226, 1, // 14111: decode to XVCVDPSP using decoder 226
6824 // 14111: }
6825 1, 0, // 14116: case 0x1: {
6826 OPC_CheckField, 16, 5, 0, // 14118: check Inst[20:16] == 0x0
6827 OPC_Decode, 201, 21, 226, 1, // 14122: decode to XVABSSP using decoder 226
6828 // 14122: }
6829 // 14122: } // switch Inst[6]
6830 // 14122: }
6831 // 14122: } // switch Inst[3:2]
6832 // 14122: }
6833 13, 69, // 14127: case 0xd: {
6834 OPC_SwitchField, 3, 1, // 14129: switch Inst[3] {
6835 0, 57, // 14132: case 0x0: {
6836 OPC_SwitchField, 2, 1, // 14134: switch Inst[2] {
6837 0, 25, // 14137: case 0x0: {
6838 OPC_SwitchField, 6, 1, // 14139: switch Inst[6] {
6839 0, 9, // 14142: case 0x0: {
6840 OPC_CheckField, 16, 5, 0, // 14144: check Inst[20:16] == 0x0
6841 OPC_Decode, 249, 21, 226, 1, // 14148: decode to XVCVUXDSP using decoder 226
6842 // 14148: }
6843 1, 0, // 14153: case 0x1: {
6844 OPC_CheckField, 16, 5, 0, // 14155: check Inst[20:16] == 0x0
6845 OPC_Decode, 245, 21, 226, 1, // 14159: decode to XVCVSXDSP using decoder 226
6846 // 14159: }
6847 // 14159: } // switch Inst[6]
6848 // 14159: }
6849 1, 0, // 14164: case 0x1: {
6850 OPC_SwitchField, 6, 1, // 14166: switch Inst[6] {
6851 0, 9, // 14169: case 0x0: {
6852 OPC_CheckField, 16, 5, 0, // 14171: check Inst[20:16] == 0x0
6853 OPC_Decode, 197, 22, 226, 1, // 14175: decode to XVNABSSP using decoder 226
6854 // 14175: }
6855 1, 0, // 14180: case 0x1: {
6856 OPC_CheckField, 16, 5, 0, // 14182: check Inst[20:16] == 0x0
6857 OPC_Decode, 199, 22, 226, 1, // 14186: decode to XVNEGSP using decoder 226
6858 // 14186: }
6859 // 14186: } // switch Inst[6]
6860 // 14186: }
6861 // 14186: } // switch Inst[2]
6862 // 14186: }
6863 1, 0, // 14191: case 0x1: {
6864 OPC_Decode, 235, 22, 235, 1, // 14193: decode to XVTSTDCSP using decoder 235
6865 // 14193: }
6866 // 14193: } // switch Inst[3]
6867 // 14193: }
6868 14, 220, 1, // 14198: case 0xe: {
6869 OPC_SwitchField, 2, 2, // 14201: switch Inst[3:2] {
6870 0, 25, // 14204: case 0x0: {
6871 OPC_SwitchField, 6, 1, // 14206: switch Inst[6] {
6872 0, 9, // 14209: case 0x0: {
6873 OPC_CheckField, 16, 5, 0, // 14211: check Inst[20:16] == 0x0
6874 OPC_Decode, 234, 21, 226, 1, // 14215: decode to XVCVDPUXDS using decoder 226
6875 // 14215: }
6876 1, 0, // 14220: case 0x1: {
6877 OPC_CheckField, 16, 5, 0, // 14222: check Inst[20:16] == 0x0
6878 OPC_Decode, 232, 21, 226, 1, // 14226: decode to XVCVDPSXDS using decoder 226
6879 // 14226: }
6880 // 14226: } // switch Inst[6]
6881 // 14226: }
6882 1, 25, // 14231: case 0x1: {
6883 OPC_SwitchField, 6, 1, // 14233: switch Inst[6] {
6884 0, 9, // 14236: case 0x0: {
6885 OPC_CheckField, 16, 5, 0, // 14238: check Inst[20:16] == 0x0
6886 OPC_Decode, 238, 21, 226, 1, // 14242: decode to XVCVSPDP using decoder 226
6887 // 14242: }
6888 1, 0, // 14247: case 0x1: {
6889 OPC_CheckField, 16, 5, 0, // 14249: check Inst[20:16] == 0x0
6890 OPC_Decode, 200, 21, 226, 1, // 14253: decode to XVABSDP using decoder 226
6891 // 14253: }
6892 // 14253: } // switch Inst[6]
6893 // 14253: }
6894 2, 41, // 14258: case 0x2: {
6895 OPC_SwitchField, 1, 1, // 14260: switch Inst[1] {
6896 0, 17, // 14263: case 0x0: {
6897 OPC_SwitchField, 6, 1, // 14265: switch Inst[6] {
6898 0, 5, // 14268: case 0x0: {
6899 OPC_Decode, 253, 22, 236, 1, // 14270: decode to XXGENPCVBM using decoder 236
6900 // 14270: }
6901 1, 0, // 14275: case 0x1: {
6902 OPC_Decode, 128, 23, 236, 1, // 14277: decode to XXGENPCVWM using decoder 236
6903 // 14277: }
6904 // 14277: } // switch Inst[6]
6905 // 14277: }
6906 1, 0, // 14282: case 0x1: {
6907 OPC_SwitchField, 6, 1, // 14284: switch Inst[6] {
6908 0, 5, // 14287: case 0x0: {
6909 OPC_Decode, 255, 22, 236, 1, // 14289: decode to XXGENPCVHM using decoder 236
6910 // 14289: }
6911 1, 0, // 14294: case 0x1: {
6912 OPC_Decode, 254, 22, 236, 1, // 14296: decode to XXGENPCVDM using decoder 236
6913 // 14296: }
6914 // 14296: } // switch Inst[6]
6915 // 14296: }
6916 // 14296: } // switch Inst[1]
6917 // 14296: }
6918 3, 0, // 14301: case 0x3: {
6919 OPC_SwitchField, 6, 1, // 14303: switch Inst[6] {
6920 0, 9, // 14306: case 0x0: {
6921 OPC_CheckField, 1, 1, 0, // 14308: check Inst[1] == 0x0
6922 OPC_Decode, 244, 20, 237, 1, // 14312: decode to XSIEXPDP using decoder 237
6923 // 14312: }
6924 1, 0, // 14317: case 0x1: {
6925 OPC_SwitchField, 16, 5, // 14319: switch Inst[20:16] {
6926 0, 5, // 14322: case 0x0: {
6927 OPC_Decode, 236, 22, 226, 1, // 14324: decode to XVXEXPDP using decoder 226
6928 // 14324: }
6929 1, 5, // 14329: case 0x1: {
6930 OPC_Decode, 238, 22, 226, 1, // 14331: decode to XVXSIGDP using decoder 226
6931 // 14331: }
6932 2, 13, // 14336: case 0x2: {
6933 OPC_CheckField, 21, 2, 0, // 14338: check Inst[22:21] == 0x0
6934 OPC_CheckField, 0, 1, 0, // 14342: check Inst[0] == 0x0
6935 OPC_Decode, 231, 22, 227, 1, // 14346: decode to XVTLSBB using decoder 227
6936 // 14346: }
6937 7, 5, // 14351: case 0x7: {
6938 OPC_Decode, 248, 22, 226, 1, // 14353: decode to XXBRH using decoder 226
6939 // 14353: }
6940 8, 5, // 14358: case 0x8: {
6941 OPC_Decode, 237, 22, 226, 1, // 14360: decode to XVXEXPSP using decoder 226
6942 // 14360: }
6943 9, 5, // 14365: case 0x9: {
6944 OPC_Decode, 239, 22, 226, 1, // 14367: decode to XVXSIGSP using decoder 226
6945 // 14367: }
6946 15, 5, // 14372: case 0xf: {
6947 OPC_Decode, 250, 22, 226, 1, // 14374: decode to XXBRW using decoder 226
6948 // 14374: }
6949 16, 5, // 14379: case 0x10: {
6950 OPC_Decode, 230, 21, 226, 1, // 14381: decode to XVCVBF16SPN using decoder 226
6951 // 14381: }
6952 17, 5, // 14386: case 0x11: {
6953 OPC_Decode, 237, 21, 226, 1, // 14388: decode to XVCVSPBF16 using decoder 226
6954 // 14388: }
6955 23, 5, // 14393: case 0x17: {
6956 OPC_Decode, 247, 22, 226, 1, // 14395: decode to XXBRD using decoder 226
6957 // 14395: }
6958 24, 5, // 14400: case 0x18: {
6959 OPC_Decode, 236, 21, 226, 1, // 14402: decode to XVCVHPSP using decoder 226
6960 // 14402: }
6961 25, 5, // 14407: case 0x19: {
6962 OPC_Decode, 239, 21, 226, 1, // 14409: decode to XVCVSPHP using decoder 226
6963 // 14409: }
6964 31, 0, // 14414: case 0x1f: {
6965 OPC_Decode, 249, 22, 226, 1, // 14416: decode to XXBRQ using decoder 226
6966 // 14416: }
6967 // 14416: } // switch Inst[20:16]
6968 // 14416: }
6969 // 14416: } // switch Inst[6]
6970 // 14416: }
6971 // 14416: } // switch Inst[3:2]
6972 // 14416: }
6973 15, 0, // 14421: case 0xf: {
6974 OPC_SwitchField, 3, 1, // 14423: switch Inst[3] {
6975 0, 57, // 14426: case 0x0: {
6976 OPC_SwitchField, 2, 1, // 14428: switch Inst[2] {
6977 0, 25, // 14431: case 0x0: {
6978 OPC_SwitchField, 6, 1, // 14433: switch Inst[6] {
6979 0, 9, // 14436: case 0x0: {
6980 OPC_CheckField, 16, 5, 0, // 14438: check Inst[20:16] == 0x0
6981 OPC_Decode, 248, 21, 226, 1, // 14442: decode to XVCVUXDDP using decoder 226
6982 // 14442: }
6983 1, 0, // 14447: case 0x1: {
6984 OPC_CheckField, 16, 5, 0, // 14449: check Inst[20:16] == 0x0
6985 OPC_Decode, 244, 21, 226, 1, // 14453: decode to XVCVSXDDP using decoder 226
6986 // 14453: }
6987 // 14453: } // switch Inst[6]
6988 // 14453: }
6989 1, 0, // 14458: case 0x1: {
6990 OPC_SwitchField, 6, 1, // 14460: switch Inst[6] {
6991 0, 9, // 14463: case 0x0: {
6992 OPC_CheckField, 16, 5, 0, // 14465: check Inst[20:16] == 0x0
6993 OPC_Decode, 196, 22, 226, 1, // 14469: decode to XVNABSDP using decoder 226
6994 // 14469: }
6995 1, 0, // 14474: case 0x1: {
6996 OPC_CheckField, 16, 5, 0, // 14476: check Inst[20:16] == 0x0
6997 OPC_Decode, 198, 22, 226, 1, // 14480: decode to XVNEGDP using decoder 226
6998 // 14480: }
6999 // 14480: } // switch Inst[6]
7000 // 14480: }
7001 // 14480: } // switch Inst[2]
7002 // 14480: }
7003 1, 0, // 14485: case 0x1: {
7004 OPC_Decode, 234, 22, 235, 1, // 14487: decode to XVTSTDCDP using decoder 235
7005 // 14487: }
7006 // 14487: } // switch Inst[3]
7007 // 14487: }
7008 // 14487: } // switch Inst[10:7]
7009 // 14487: }
7010 3, 0, // 14492: case 0x3: {
7011 OPC_Decode, 158, 23, 238, 1, // 14494: decode to XXSEL using decoder 238
7012 // 14494: }
7013 // 14494: } // switch Inst[5:4]
7014 // 14494: }
7015 61, 36, // 14499: case 0x3d: {
7016 OPC_SwitchField, 0, 2, // 14501: switch Inst[1:0] {
7017 1, 17, // 14504: case 0x1: {
7018 OPC_SwitchField, 2, 1, // 14506: switch Inst[2] {
7019 0, 5, // 14509: case 0x0: {
7020 OPC_Decode, 191, 11, 239, 1, // 14511: decode to LXV using decoder 239
7021 // 14511: }
7022 1, 0, // 14516: case 0x1: {
7023 OPC_Decode, 160, 16, 239, 1, // 14518: decode to STXV using decoder 239
7024 // 14518: }
7025 // 14518: } // switch Inst[2]
7026 // 14518: }
7027 2, 5, // 14523: case 0x2: {
7028 OPC_Decode, 151, 16, 169, 1, // 14525: decode to STXSD using decoder 169
7029 // 14525: }
7030 3, 0, // 14530: case 0x3: {
7031 OPC_Decode, 158, 16, 169, 1, // 14532: decode to STXSSP using decoder 169
7032 // 14532: }
7033 // 14532: } // switch Inst[1:0]
7034 // 14532: }
7035 62, 24, // 14537: case 0x3e: {
7036 OPC_SwitchField, 0, 2, // 14539: switch Inst[1:0] {
7037 0, 5, // 14542: case 0x0: {
7038 OPC_Decode, 213, 15, 170, 1, // 14544: decode to STD using decoder 170
7039 // 14544: }
7040 1, 5, // 14549: case 0x1: {
7041 OPC_Decode, 218, 15, 240, 1, // 14551: decode to STDU using decoder 240
7042 // 14551: }
7043 2, 0, // 14556: case 0x2: {
7044 OPC_Decode, 254, 15, 241, 1, // 14558: decode to STQ using decoder 241
7045 // 14558: }
7046 // 14558: } // switch Inst[1:0]
7047 // 14558: }
7048 63, 0, // 14563: case 0x3f: {
7049 OPC_SwitchField, 0, 6, // 14565: switch Inst[5:0] {
7050 0, 61, // 14568: case 0x0: {
7051 OPC_SwitchField, 6, 5, // 14570: switch Inst[10:6] {
7052 0, 9, // 14573: case 0x0: {
7053 OPC_CheckField, 21, 2, 0, // 14575: check Inst[22:21] == 0x0
7054 OPC_Decode, 186, 9, 242, 1, // 14579: decode to FCMPUS using decoder 242
7055 // 14579: }
7056 1, 9, // 14584: case 0x1: {
7057 OPC_CheckField, 21, 2, 0, // 14586: check Inst[22:21] == 0x0
7058 OPC_Decode, 184, 9, 242, 1, // 14590: decode to FCMPOS using decoder 242
7059 // 14590: }
7060 2, 12, // 14595: case 0x2: {
7061 OPC_CheckField, 21, 2, 0, // 14597: check Inst[22:21] == 0x0
7062 OPC_CheckField, 11, 7, 0, // 14601: check Inst[17:11] == 0x0
7063 OPC_Decode, 219, 11, 51, // 14605: decode to MCRFS using decoder 51
7064 // 14605: }
7065 4, 9, // 14609: case 0x4: {
7066 OPC_CheckField, 21, 2, 0, // 14611: check Inst[22:21] == 0x0
7067 OPC_Decode, 152, 10, 180, 1, // 14615: decode to FTDIV using decoder 180
7068 // 14615: }
7069 5, 0, // 14620: case 0x5: {
7070 OPC_CheckField, 16, 7, 0, // 14622: check Inst[22:16] == 0x0
7071 OPC_Decode, 153, 10, 243, 1, // 14626: decode to FTSQRT using decoder 243
7072 // 14626: }
7073 // 14626: } // switch Inst[10:6]
7074 // 14626: }
7075 4, 134, 2, // 14631: case 0x4: {
7076 OPC_SwitchField, 6, 4, // 14634: switch Inst[9:6] {
7077 0, 17, // 14637: case 0x0: {
7078 OPC_SwitchField, 10, 1, // 14639: switch Inst[10] {
7079 0, 5, // 14642: case 0x0: {
7080 OPC_Decode, 221, 5, 244, 1, // 14644: decode to DADDQ using decoder 244
7081 // 14644: }
7082 1, 0, // 14649: case 0x1: {
7083 OPC_Decode, 251, 6, 244, 1, // 14651: decode to DSUBQ using decoder 244
7084 // 14651: }
7085 // 14651: } // switch Inst[10]
7086 // 14651: }
7087 1, 17, // 14656: case 0x1: {
7088 OPC_SwitchField, 10, 1, // 14658: switch Inst[10] {
7089 0, 5, // 14661: case 0x0: {
7090 OPC_Decode, 183, 6, 244, 1, // 14663: decode to DMULQ using decoder 244
7091 // 14663: }
7092 1, 0, // 14668: case 0x1: {
7093 OPC_Decode, 135, 6, 244, 1, // 14670: decode to DDIVQ using decoder 244
7094 // 14670: }
7095 // 14670: } // switch Inst[10]
7096 // 14670: }
7097 2, 5, // 14675: case 0x2: {
7098 OPC_Decode, 233, 6, 245, 1, // 14677: decode to DSCLIQ using decoder 245
7099 // 14677: }
7100 3, 5, // 14682: case 0x3: {
7101 OPC_Decode, 237, 6, 245, 1, // 14684: decode to DSCRIQ using decoder 245
7102 // 14684: }
7103 4, 25, // 14689: case 0x4: {
7104 OPC_SwitchField, 10, 1, // 14691: switch Inst[10] {
7105 0, 9, // 14694: case 0x0: {
7106 OPC_CheckField, 21, 2, 0, // 14696: check Inst[22:21] == 0x0
7107 OPC_Decode, 246, 5, 246, 1, // 14700: decode to DCMPOQ using decoder 246
7108 // 14700: }
7109 1, 0, // 14705: case 0x1: {
7110 OPC_CheckField, 21, 2, 0, // 14707: check Inst[22:21] == 0x0
7111 OPC_Decode, 248, 5, 246, 1, // 14711: decode to DCMPUQ using decoder 246
7112 // 14711: }
7113 // 14711: } // switch Inst[10]
7114 // 14711: }
7115 5, 25, // 14716: case 0x5: {
7116 OPC_SwitchField, 10, 1, // 14718: switch Inst[10] {
7117 0, 9, // 14721: case 0x0: {
7118 OPC_CheckField, 21, 2, 0, // 14723: check Inst[22:21] == 0x0
7119 OPC_Decode, 131, 7, 246, 1, // 14727: decode to DTSTEXQ using decoder 246
7120 // 14727: }
7121 1, 0, // 14732: case 0x1: {
7122 OPC_CheckField, 21, 2, 0, // 14734: check Inst[22:21] == 0x0
7123 OPC_Decode, 135, 7, 247, 1, // 14738: decode to DTSTSFQ using decoder 247
7124 // 14738: }
7125 // 14738: } // switch Inst[10]
7126 // 14738: }
7127 6, 9, // 14743: case 0x6: {
7128 OPC_CheckField, 21, 2, 0, // 14745: check Inst[22:21] == 0x0
7129 OPC_Decode, 255, 6, 248, 1, // 14749: decode to DTSTDCQ using decoder 248
7130 // 14749: }
7131 7, 9, // 14754: case 0x7: {
7132 OPC_CheckField, 21, 2, 0, // 14756: check Inst[22:21] == 0x0
7133 OPC_Decode, 129, 7, 248, 1, // 14760: decode to DTSTDGQ using decoder 248
7134 // 14760: }
7135 8, 25, // 14765: case 0x8: {
7136 OPC_SwitchField, 10, 1, // 14767: switch Inst[10] {
7137 0, 9, // 14770: case 0x0: {
7138 OPC_CheckField, 16, 5, 0, // 14772: check Inst[20:16] == 0x0
7139 OPC_Decode, 128, 6, 249, 1, // 14776: decode to DCTQPQ using decoder 249
7140 // 14776: }
7141 1, 0, // 14781: case 0x1: {
7142 OPC_CheckField, 16, 5, 0, // 14783: check Inst[20:16] == 0x0
7143 OPC_Decode, 216, 6, 250, 1, // 14787: decode to DRDPQ using decoder 250
7144 // 14787: }
7145 // 14787: } // switch Inst[10]
7146 // 14787: }
7147 9, 25, // 14792: case 0x9: {
7148 OPC_SwitchField, 10, 1, // 14794: switch Inst[10] {
7149 0, 9, // 14797: case 0x0: {
7150 OPC_CheckField, 16, 5, 0, // 14799: check Inst[20:16] == 0x0
7151 OPC_Decode, 252, 5, 251, 1, // 14803: decode to DCTFIXQ using decoder 251
7152 // 14803: }
7153 1, 0, // 14808: case 0x1: {
7154 OPC_CheckField, 16, 5, 0, // 14810: check Inst[20:16] == 0x0
7155 OPC_Decode, 241, 5, 249, 1, // 14814: decode to DCFFIXQ using decoder 249
7156 // 14814: }
7157 // 14814: } // switch Inst[10]
7158 // 14814: }
7159 10, 25, // 14819: case 0xa: {
7160 OPC_SwitchField, 10, 1, // 14821: switch Inst[10] {
7161 0, 9, // 14824: case 0x0: {
7162 OPC_CheckField, 16, 3, 0, // 14826: check Inst[18:16] == 0x0
7163 OPC_Decode, 131, 6, 252, 1, // 14830: decode to DDEDPDQ using decoder 252
7164 // 14830: }
7165 1, 0, // 14835: case 0x1: {
7166 OPC_CheckField, 16, 4, 0, // 14837: check Inst[19:16] == 0x0
7167 OPC_Decode, 139, 6, 253, 1, // 14841: decode to DENBCDQ using decoder 253
7168 // 14841: }
7169 // 14841: } // switch Inst[10]
7170 // 14841: }
7171 11, 21, // 14846: case 0xb: {
7172 OPC_SwitchField, 10, 1, // 14848: switch Inst[10] {
7173 0, 9, // 14851: case 0x0: {
7174 OPC_CheckField, 16, 5, 0, // 14853: check Inst[20:16] == 0x0
7175 OPC_Decode, 137, 7, 251, 1, // 14857: decode to DXEXQ using decoder 251
7176 // 14857: }
7177 1, 0, // 14862: case 0x1: {
7178 OPC_Decode, 143, 6, 254, 1, // 14864: decode to DIEXQ using decoder 254
7179 // 14864: }
7180 // 14864: } // switch Inst[10]
7181 // 14864: }
7182 15, 0, // 14869: case 0xf: {
7183 OPC_SwitchField, 16, 5, // 14871: switch Inst[20:16] {
7184 0, 9, // 14874: case 0x0: {
7185 OPC_CheckField, 10, 1, 1, // 14876: check Inst[10] == 0x1
7186 OPC_Decode, 242, 5, 255, 1, // 14880: decode to DCFFIXQQ using decoder 255
7187 // 14880: }
7188 1, 0, // 14885: case 0x1: {
7189 OPC_CheckField, 10, 1, 1, // 14887: check Inst[10] == 0x1
7190 OPC_Decode, 253, 5, 128, 2, // 14891: decode to DCTFIXQQ using decoder 256
7191 // 14891: }
7192 // 14891: } // switch Inst[20:16]
7193 // 14891: }
7194 // 14891: } // switch Inst[9:6]
7195 // 14891: }
7196 5, 159, 1, // 14896: case 0x5: {
7197 OPC_SwitchField, 6, 4, // 14899: switch Inst[9:6] {
7198 0, 17, // 14902: case 0x0: {
7199 OPC_SwitchField, 10, 1, // 14904: switch Inst[10] {
7200 0, 5, // 14907: case 0x0: {
7201 OPC_Decode, 222, 5, 244, 1, // 14909: decode to DADDQ_rec using decoder 244
7202 // 14909: }
7203 1, 0, // 14914: case 0x1: {
7204 OPC_Decode, 252, 6, 244, 1, // 14916: decode to DSUBQ_rec using decoder 244
7205 // 14916: }
7206 // 14916: } // switch Inst[10]
7207 // 14916: }
7208 1, 17, // 14921: case 0x1: {
7209 OPC_SwitchField, 10, 1, // 14923: switch Inst[10] {
7210 0, 5, // 14926: case 0x0: {
7211 OPC_Decode, 184, 6, 244, 1, // 14928: decode to DMULQ_rec using decoder 244
7212 // 14928: }
7213 1, 0, // 14933: case 0x1: {
7214 OPC_Decode, 136, 6, 244, 1, // 14935: decode to DDIVQ_rec using decoder 244
7215 // 14935: }
7216 // 14935: } // switch Inst[10]
7217 // 14935: }
7218 2, 5, // 14940: case 0x2: {
7219 OPC_Decode, 234, 6, 245, 1, // 14942: decode to DSCLIQ_rec using decoder 245
7220 // 14942: }
7221 3, 5, // 14947: case 0x3: {
7222 OPC_Decode, 238, 6, 245, 1, // 14949: decode to DSCRIQ_rec using decoder 245
7223 // 14949: }
7224 8, 25, // 14954: case 0x8: {
7225 OPC_SwitchField, 10, 1, // 14956: switch Inst[10] {
7226 0, 9, // 14959: case 0x0: {
7227 OPC_CheckField, 16, 5, 0, // 14961: check Inst[20:16] == 0x0
7228 OPC_Decode, 129, 6, 249, 1, // 14965: decode to DCTQPQ_rec using decoder 249
7229 // 14965: }
7230 1, 0, // 14970: case 0x1: {
7231 OPC_CheckField, 16, 5, 0, // 14972: check Inst[20:16] == 0x0
7232 OPC_Decode, 217, 6, 250, 1, // 14976: decode to DRDPQ_rec using decoder 250
7233 // 14976: }
7234 // 14976: } // switch Inst[10]
7235 // 14976: }
7236 9, 25, // 14981: case 0x9: {
7237 OPC_SwitchField, 10, 1, // 14983: switch Inst[10] {
7238 0, 9, // 14986: case 0x0: {
7239 OPC_CheckField, 16, 5, 0, // 14988: check Inst[20:16] == 0x0
7240 OPC_Decode, 254, 5, 251, 1, // 14992: decode to DCTFIXQ_rec using decoder 251
7241 // 14992: }
7242 1, 0, // 14997: case 0x1: {
7243 OPC_CheckField, 16, 5, 0, // 14999: check Inst[20:16] == 0x0
7244 OPC_Decode, 243, 5, 249, 1, // 15003: decode to DCFFIXQ_rec using decoder 249
7245 // 15003: }
7246 // 15003: } // switch Inst[10]
7247 // 15003: }
7248 10, 25, // 15008: case 0xa: {
7249 OPC_SwitchField, 10, 1, // 15010: switch Inst[10] {
7250 0, 9, // 15013: case 0x0: {
7251 OPC_CheckField, 16, 3, 0, // 15015: check Inst[18:16] == 0x0
7252 OPC_Decode, 132, 6, 252, 1, // 15019: decode to DDEDPDQ_rec using decoder 252
7253 // 15019: }
7254 1, 0, // 15024: case 0x1: {
7255 OPC_CheckField, 16, 4, 0, // 15026: check Inst[19:16] == 0x0
7256 OPC_Decode, 140, 6, 253, 1, // 15030: decode to DENBCDQ_rec using decoder 253
7257 // 15030: }
7258 // 15030: } // switch Inst[10]
7259 // 15030: }
7260 11, 0, // 15035: case 0xb: {
7261 OPC_SwitchField, 10, 1, // 15037: switch Inst[10] {
7262 0, 9, // 15040: case 0x0: {
7263 OPC_CheckField, 16, 5, 0, // 15042: check Inst[20:16] == 0x0
7264 OPC_Decode, 138, 7, 251, 1, // 15046: decode to DXEXQ_rec using decoder 251
7265 // 15046: }
7266 1, 0, // 15051: case 0x1: {
7267 OPC_Decode, 144, 6, 254, 1, // 15053: decode to DIEXQ_rec using decoder 254
7268 // 15053: }
7269 // 15053: } // switch Inst[10]
7270 // 15053: }
7271 // 15053: } // switch Inst[9:6]
7272 // 15053: }
7273 6, 61, // 15058: case 0x6: {
7274 OPC_SwitchField, 6, 3, // 15060: switch Inst[8:6] {
7275 0, 5, // 15063: case 0x0: {
7276 OPC_Decode, 213, 6, 129, 2, // 15065: decode to DQUAQ using decoder 257
7277 // 15065: }
7278 1, 5, // 15070: case 0x1: {
7279 OPC_Decode, 227, 6, 130, 2, // 15072: decode to DRRNDQ using decoder 258
7280 // 15072: }
7281 2, 5, // 15077: case 0x2: {
7282 OPC_Decode, 210, 6, 131, 2, // 15079: decode to DQUAIQ using decoder 259
7283 // 15079: }
7284 3, 9, // 15084: case 0x3: {
7285 OPC_CheckField, 17, 4, 0, // 15086: check Inst[20:17] == 0x0
7286 OPC_Decode, 223, 6, 132, 2, // 15090: decode to DRINTXQ using decoder 260
7287 // 15090: }
7288 5, 13, // 15095: case 0x5: {
7289 OPC_CheckField, 22, 1, 0, // 15097: check Inst[22] == 0x0
7290 OPC_CheckField, 9, 2, 2, // 15101: check Inst[10:9] == 0x2
7291 OPC_Decode, 134, 7, 133, 2, // 15105: decode to DTSTSFIQ using decoder 261
7292 // 15105: }
7293 7, 0, // 15110: case 0x7: {
7294 OPC_CheckField, 17, 4, 0, // 15112: check Inst[20:17] == 0x0
7295 OPC_Decode, 219, 6, 132, 2, // 15116: decode to DRINTNQ using decoder 260
7296 // 15116: }
7297 // 15116: } // switch Inst[8:6]
7298 // 15116: }
7299 7, 46, // 15121: case 0x7: {
7300 OPC_SwitchField, 6, 3, // 15123: switch Inst[8:6] {
7301 0, 5, // 15126: case 0x0: {
7302 OPC_Decode, 214, 6, 129, 2, // 15128: decode to DQUAQ_rec using decoder 257
7303 // 15128: }
7304 1, 5, // 15133: case 0x1: {
7305 OPC_Decode, 228, 6, 130, 2, // 15135: decode to DRRNDQ_rec using decoder 258
7306 // 15135: }
7307 2, 5, // 15140: case 0x2: {
7308 OPC_Decode, 211, 6, 131, 2, // 15142: decode to DQUAIQ_rec using decoder 259
7309 // 15142: }
7310 3, 9, // 15147: case 0x3: {
7311 OPC_CheckField, 17, 4, 0, // 15149: check Inst[20:17] == 0x0
7312 OPC_Decode, 224, 6, 132, 2, // 15153: decode to DRINTXQ_rec using decoder 260
7313 // 15153: }
7314 7, 0, // 15158: case 0x7: {
7315 OPC_CheckField, 17, 4, 0, // 15160: check Inst[20:17] == 0x0
7316 OPC_Decode, 220, 6, 132, 2, // 15164: decode to DRINTNQ_rec using decoder 260
7317 // 15164: }
7318 // 15164: } // switch Inst[8:6]
7319 // 15164: }
7320 8, 129, 2, // 15169: case 0x8: {
7321 OPC_SwitchField, 6, 5, // 15172: switch Inst[10:6] {
7322 0, 4, // 15175: case 0x0: {
7323 OPC_Decode, 190, 20, 3, // 15177: decode to XSADDQP using decoder 3
7324 // 15177: }
7325 1, 4, // 15181: case 0x1: {
7326 OPC_Decode, 143, 21, 3, // 15183: decode to XSMULQP using decoder 3
7327 // 15183: }
7328 2, 4, // 15187: case 0x2: {
7329 OPC_Decode, 196, 20, 3, // 15189: decode to XSCMPEQQP using decoder 3
7330 // 15189: }
7331 3, 4, // 15193: case 0x3: {
7332 OPC_Decode, 208, 20, 3, // 15195: decode to XSCPSGNQP using decoder 3
7333 // 15195: }
7334 4, 8, // 15199: case 0x4: {
7335 OPC_CheckField, 21, 2, 0, // 15201: check Inst[22:21] == 0x0
7336 OPC_Decode, 204, 20, 6, // 15205: decode to XSCMPOQP using decoder 6
7337 // 15205: }
7338 5, 8, // 15209: case 0x5: {
7339 OPC_CheckField, 21, 2, 0, // 15211: check Inst[22:21] == 0x0
7340 OPC_Decode, 198, 20, 6, // 15215: decode to XSCMPEXPQP using decoder 6
7341 // 15215: }
7342 6, 4, // 15219: case 0x6: {
7343 OPC_Decode, 200, 20, 3, // 15221: decode to XSCMPGEQP using decoder 3
7344 // 15221: }
7345 7, 4, // 15225: case 0x7: {
7346 OPC_Decode, 202, 20, 3, // 15227: decode to XSCMPGTQP using decoder 3
7347 // 15227: }
7348 12, 5, // 15231: case 0xc: {
7349 OPC_Decode, 250, 20, 134, 2, // 15233: decode to XSMADDQP using decoder 262
7350 // 15233: }
7351 13, 5, // 15238: case 0xd: {
7352 OPC_Decode, 140, 21, 134, 2, // 15240: decode to XSMSUBQP using decoder 262
7353 // 15240: }
7354 14, 5, // 15245: case 0xe: {
7355 OPC_Decode, 155, 21, 134, 2, // 15247: decode to XSNMADDQP using decoder 262
7356 // 15247: }
7357 15, 5, // 15252: case 0xf: {
7358 OPC_Decode, 161, 21, 134, 2, // 15254: decode to XSNMSUBQP using decoder 262
7359 // 15254: }
7360 16, 4, // 15259: case 0x10: {
7361 OPC_Decode, 188, 21, 3, // 15261: decode to XSSUBQP using decoder 3
7362 // 15261: }
7363 17, 4, // 15265: case 0x11: {
7364 OPC_Decode, 241, 20, 3, // 15267: decode to XSDIVQP using decoder 3
7365 // 15267: }
7366 20, 8, // 15271: case 0x14: {
7367 OPC_CheckField, 21, 2, 0, // 15273: check Inst[22:21] == 0x0
7368 OPC_Decode, 206, 20, 6, // 15277: decode to XSCMPUQP using decoder 6
7369 // 15277: }
7370 21, 4, // 15281: case 0x15: {
7371 OPC_Decode, 253, 20, 3, // 15283: decode to XSMAXCQP using decoder 3
7372 // 15283: }
7373 22, 5, // 15287: case 0x16: {
7374 OPC_Decode, 194, 21, 135, 2, // 15289: decode to XSTSTDCQP using decoder 263
7375 // 15289: }
7376 23, 4, // 15294: case 0x17: {
7377 OPC_Decode, 133, 21, 3, // 15296: decode to XSMINCQP using decoder 3
7378 // 15296: }
7379 25, 39, // 15300: case 0x19: {
7380 OPC_SwitchField, 16, 5, // 15302: switch Inst[20:16] {
7381 0, 4, // 15305: case 0x0: {
7382 OPC_Decode, 186, 20, 7, // 15307: decode to XSABSQP using decoder 7
7383 // 15307: }
7384 2, 4, // 15311: case 0x2: {
7385 OPC_Decode, 197, 21, 7, // 15313: decode to XSXEXPQP using decoder 7
7386 // 15313: }
7387 8, 4, // 15317: case 0x8: {
7388 OPC_Decode, 148, 21, 7, // 15319: decode to XSNABSQP using decoder 7
7389 // 15319: }
7390 16, 4, // 15323: case 0x10: {
7391 OPC_Decode, 150, 21, 7, // 15325: decode to XSNEGQP using decoder 7
7392 // 15325: }
7393 18, 4, // 15329: case 0x12: {
7394 OPC_Decode, 199, 21, 7, // 15331: decode to XSXSIGQP using decoder 7
7395 // 15331: }
7396 27, 0, // 15335: case 0x1b: {
7397 OPC_Decode, 184, 21, 7, // 15337: decode to XSSQRTQP using decoder 7
7398 // 15337: }
7399 // 15337: } // switch Inst[20:16]
7400 // 15337: }
7401 26, 79, // 15341: case 0x1a: {
7402 OPC_SwitchField, 16, 5, // 15343: switch Inst[20:16] {
7403 0, 4, // 15346: case 0x0: {
7404 OPC_Decode, 228, 20, 7, // 15348: decode to XSCVQPUQZ using decoder 7
7405 // 15348: }
7406 1, 4, // 15352: case 0x1: {
7407 OPC_Decode, 229, 20, 7, // 15354: decode to XSCVQPUWZ using decoder 7
7408 // 15354: }
7409 2, 5, // 15358: case 0x2: {
7410 OPC_Decode, 236, 20, 136, 2, // 15360: decode to XSCVUDQP using decoder 264
7411 // 15360: }
7412 3, 4, // 15365: case 0x3: {
7413 OPC_Decode, 237, 20, 7, // 15367: decode to XSCVUQQP using decoder 7
7414 // 15367: }
7415 8, 4, // 15371: case 0x8: {
7416 OPC_Decode, 225, 20, 7, // 15373: decode to XSCVQPSQZ using decoder 7
7417 // 15373: }
7418 9, 4, // 15377: case 0x9: {
7419 OPC_Decode, 226, 20, 7, // 15379: decode to XSCVQPSWZ using decoder 7
7420 // 15379: }
7421 10, 5, // 15383: case 0xa: {
7422 OPC_Decode, 230, 20, 136, 2, // 15385: decode to XSCVSDQP using decoder 264
7423 // 15385: }
7424 11, 4, // 15390: case 0xb: {
7425 OPC_Decode, 233, 20, 7, // 15392: decode to XSCVSQQP using decoder 7
7426 // 15392: }
7427 17, 4, // 15396: case 0x11: {
7428 OPC_Decode, 227, 20, 7, // 15398: decode to XSCVQPUDZ using decoder 7
7429 // 15398: }
7430 20, 5, // 15402: case 0x14: {
7431 OPC_Decode, 222, 20, 137, 2, // 15404: decode to XSCVQPDP using decoder 265
7432 // 15404: }
7433 22, 5, // 15409: case 0x16: {
7434 OPC_Decode, 210, 20, 136, 2, // 15411: decode to XSCVDPQP using decoder 264
7435 // 15411: }
7436 25, 0, // 15416: case 0x19: {
7437 OPC_Decode, 224, 20, 7, // 15418: decode to XSCVQPSDZ using decoder 7
7438 // 15418: }
7439 // 15418: } // switch Inst[20:16]
7440 // 15418: }
7441 27, 0, // 15422: case 0x1b: {
7442 OPC_Decode, 245, 20, 138, 2, // 15424: decode to XSIEXPQP using decoder 266
7443 // 15424: }
7444 // 15424: } // switch Inst[10:6]
7445 // 15424: }
7446 9, 76, // 15429: case 0x9: {
7447 OPC_SwitchField, 6, 5, // 15431: switch Inst[10:6] {
7448 0, 4, // 15434: case 0x0: {
7449 OPC_Decode, 191, 20, 3, // 15436: decode to XSADDQPO using decoder 3
7450 // 15436: }
7451 1, 4, // 15440: case 0x1: {
7452 OPC_Decode, 144, 21, 3, // 15442: decode to XSMULQPO using decoder 3
7453 // 15442: }
7454 12, 5, // 15446: case 0xc: {
7455 OPC_Decode, 251, 20, 134, 2, // 15448: decode to XSMADDQPO using decoder 262
7456 // 15448: }
7457 13, 5, // 15453: case 0xd: {
7458 OPC_Decode, 141, 21, 134, 2, // 15455: decode to XSMSUBQPO using decoder 262
7459 // 15455: }
7460 14, 5, // 15460: case 0xe: {
7461 OPC_Decode, 156, 21, 134, 2, // 15462: decode to XSNMADDQPO using decoder 262
7462 // 15462: }
7463 15, 5, // 15467: case 0xf: {
7464 OPC_Decode, 162, 21, 134, 2, // 15469: decode to XSNMSUBQPO using decoder 262
7465 // 15469: }
7466 16, 4, // 15474: case 0x10: {
7467 OPC_Decode, 189, 21, 3, // 15476: decode to XSSUBQPO using decoder 3
7468 // 15476: }
7469 17, 4, // 15480: case 0x11: {
7470 OPC_Decode, 242, 20, 3, // 15482: decode to XSDIVQPO using decoder 3
7471 // 15482: }
7472 25, 8, // 15486: case 0x19: {
7473 OPC_CheckField, 16, 5, 27, // 15488: check Inst[20:16] == 0x1b
7474 OPC_Decode, 185, 21, 7, // 15492: decode to XSSQRTQPO using decoder 7
7475 // 15492: }
7476 26, 0, // 15496: case 0x1a: {
7477 OPC_CheckField, 16, 5, 20, // 15498: check Inst[20:16] == 0x14
7478 OPC_Decode, 223, 20, 137, 2, // 15502: decode to XSCVQPDPO using decoder 265
7479 // 15502: }
7480 // 15502: } // switch Inst[10:6]
7481 // 15502: }
7482 10, 25, // 15507: case 0xa: {
7483 OPC_SwitchField, 6, 3, // 15509: switch Inst[8:6] {
7484 0, 9, // 15512: case 0x0: {
7485 OPC_CheckField, 17, 4, 0, // 15514: check Inst[20:17] == 0x0
7486 OPC_Decode, 177, 21, 139, 2, // 15518: decode to XSRQPI using decoder 267
7487 // 15518: }
7488 1, 0, // 15523: case 0x1: {
7489 OPC_CheckField, 17, 4, 0, // 15525: check Inst[20:17] == 0x0
7490 OPC_Decode, 179, 21, 139, 2, // 15529: decode to XSRQPXP using decoder 267
7491 // 15529: }
7492 // 15529: } // switch Inst[8:6]
7493 // 15529: }
7494 11, 13, // 15534: case 0xb: {
7495 OPC_CheckField, 17, 4, 0, // 15536: check Inst[20:17] == 0x0
7496 OPC_CheckField, 6, 3, 0, // 15540: check Inst[8:6] == 0x0
7497 OPC_Decode, 178, 21, 139, 2, // 15544: decode to XSRQPIX using decoder 267
7498 // 15544: }
7499 12, 36, // 15549: case 0xc: {
7500 OPC_SwitchField, 6, 6, // 15551: switch Inst[11:6] {
7501 1, 9, // 15554: case 0x1: {
7502 OPC_CheckField, 12, 9, 0, // 15556: check Inst[20:12] == 0x0
7503 OPC_Decode, 142, 12, 149, 1, // 15560: decode to MTFSB1 using decoder 149
7504 // 15560: }
7505 2, 9, // 15565: case 0x2: {
7506 OPC_CheckField, 12, 9, 0, // 15567: check Inst[20:12] == 0x0
7507 OPC_Decode, 141, 12, 149, 1, // 15571: decode to MTFSB0 using decoder 149
7508 // 15571: }
7509 4, 0, // 15576: case 0x4: {
7510 OPC_CheckField, 17, 6, 0, // 15578: check Inst[22:17] == 0x0
7511 OPC_Decode, 144, 12, 140, 2, // 15582: decode to MTFSFI using decoder 268
7512 // 15582: }
7513 // 15582: } // switch Inst[11:6]
7514 // 15582: }
7515 13, 13, // 15587: case 0xd: {
7516 OPC_CheckField, 17, 6, 0, // 15589: check Inst[22:17] == 0x0
7517 OPC_CheckField, 6, 6, 4, // 15593: check Inst[11:6] == 0x4
7518 OPC_Decode, 145, 12, 141, 2, // 15597: decode to MTFSFI_rec using decoder 269
7519 // 15597: }
7520 14, 84, // 15602: case 0xe: {
7521 OPC_SwitchField, 6, 5, // 15604: switch Inst[10:6] {
7522 18, 72, // 15607: case 0x12: {
7523 OPC_SwitchField, 16, 5, // 15609: switch Inst[20:16] {
7524 0, 9, // 15612: case 0x0: {
7525 OPC_CheckField, 11, 5, 0, // 15614: check Inst[15:11] == 0x0
7526 OPC_Decode, 227, 11, 142, 2, // 15618: decode to MFFS using decoder 270
7527 // 15618: }
7528 1, 9, // 15623: case 0x1: {
7529 OPC_CheckField, 11, 5, 0, // 15625: check Inst[15:11] == 0x0
7530 OPC_Decode, 230, 11, 142, 2, // 15629: decode to MFFSCE using decoder 270
7531 // 15629: }
7532 20, 5, // 15634: case 0x14: {
7533 OPC_Decode, 228, 11, 173, 1, // 15636: decode to MFFSCDRN using decoder 173
7534 // 15636: }
7535 21, 9, // 15641: case 0x15: {
7536 OPC_CheckField, 14, 2, 0, // 15643: check Inst[15:14] == 0x0
7537 OPC_Decode, 229, 11, 143, 2, // 15647: decode to MFFSCDRNI using decoder 271
7538 // 15647: }
7539 22, 5, // 15652: case 0x16: {
7540 OPC_Decode, 231, 11, 173, 1, // 15654: decode to MFFSCRN using decoder 173
7541 // 15654: }
7542 23, 9, // 15659: case 0x17: {
7543 OPC_CheckField, 13, 3, 0, // 15661: check Inst[15:13] == 0x0
7544 OPC_Decode, 232, 11, 144, 2, // 15665: decode to MFFSCRNI using decoder 272
7545 // 15665: }
7546 24, 0, // 15670: case 0x18: {
7547 OPC_CheckField, 11, 5, 0, // 15672: check Inst[15:11] == 0x0
7548 OPC_Decode, 233, 11, 142, 2, // 15676: decode to MFFSL using decoder 270
7549 // 15676: }
7550 // 15676: } // switch Inst[20:16]
7551 // 15676: }
7552 22, 0, // 15681: case 0x16: {
7553 OPC_Decode, 143, 12, 145, 2, // 15683: decode to MTFSF using decoder 273
7554 // 15683: }
7555 // 15683: } // switch Inst[10:6]
7556 // 15683: }
7557 15, 21, // 15688: case 0xf: {
7558 OPC_SwitchField, 6, 5, // 15690: switch Inst[10:6] {
7559 18, 9, // 15693: case 0x12: {
7560 OPC_CheckField, 11, 10, 0, // 15695: check Inst[20:11] == 0x0
7561 OPC_Decode, 234, 11, 142, 2, // 15699: decode to MFFS_rec using decoder 270
7562 // 15699: }
7563 22, 0, // 15704: case 0x16: {
7564 OPC_Decode, 147, 12, 145, 2, // 15706: decode to MTFSF_rec using decoder 273
7565 // 15706: }
7566 // 15706: } // switch Inst[10:6]
7567 // 15706: }
7568 16, 98, // 15711: case 0x10: {
7569 OPC_SwitchField, 6, 5, // 15713: switch Inst[10:6] {
7570 0, 5, // 15716: case 0x0: {
7571 OPC_Decode, 189, 9, 195, 1, // 15718: decode to FCPSGNS using decoder 195
7572 // 15718: }
7573 1, 9, // 15723: case 0x1: {
7574 OPC_CheckField, 16, 5, 0, // 15725: check Inst[20:16] == 0x0
7575 OPC_Decode, 232, 9, 196, 1, // 15729: decode to FNEGS using decoder 196
7576 // 15729: }
7577 2, 9, // 15734: case 0x2: {
7578 OPC_CheckField, 16, 5, 0, // 15736: check Inst[20:16] == 0x0
7579 OPC_Decode, 216, 9, 196, 1, // 15740: decode to FMR using decoder 196
7580 // 15740: }
7581 4, 9, // 15745: case 0x4: {
7582 OPC_CheckField, 16, 5, 0, // 15747: check Inst[20:16] == 0x0
7583 OPC_Decode, 228, 9, 196, 1, // 15751: decode to FNABSS using decoder 196
7584 // 15751: }
7585 8, 9, // 15756: case 0x8: {
7586 OPC_CheckField, 16, 5, 0, // 15758: check Inst[20:16] == 0x0
7587 OPC_Decode, 168, 9, 196, 1, // 15762: decode to FABSS using decoder 196
7588 // 15762: }
7589 12, 9, // 15767: case 0xc: {
7590 OPC_CheckField, 16, 5, 0, // 15769: check Inst[20:16] == 0x0
7591 OPC_Decode, 252, 9, 196, 1, // 15773: decode to FRINS using decoder 196
7592 // 15773: }
7593 13, 9, // 15778: case 0xd: {
7594 OPC_CheckField, 16, 5, 0, // 15780: check Inst[20:16] == 0x0
7595 OPC_Decode, 132, 10, 196, 1, // 15784: decode to FRIZS using decoder 196
7596 // 15784: }
7597 14, 9, // 15789: case 0xe: {
7598 OPC_CheckField, 16, 5, 0, // 15791: check Inst[20:16] == 0x0
7599 OPC_Decode, 128, 10, 196, 1, // 15795: decode to FRIPS using decoder 196
7600 // 15795: }
7601 15, 0, // 15800: case 0xf: {
7602 OPC_CheckField, 16, 5, 0, // 15802: check Inst[20:16] == 0x0
7603 OPC_Decode, 248, 9, 196, 1, // 15806: decode to FRIMS using decoder 196
7604 // 15806: }
7605 // 15806: } // switch Inst[10:6]
7606 // 15806: }
7607 17, 98, // 15811: case 0x11: {
7608 OPC_SwitchField, 6, 5, // 15813: switch Inst[10:6] {
7609 0, 5, // 15816: case 0x0: {
7610 OPC_Decode, 190, 9, 195, 1, // 15818: decode to FCPSGNS_rec using decoder 195
7611 // 15818: }
7612 1, 9, // 15823: case 0x1: {
7613 OPC_CheckField, 16, 5, 0, // 15825: check Inst[20:16] == 0x0
7614 OPC_Decode, 233, 9, 196, 1, // 15829: decode to FNEGS_rec using decoder 196
7615 // 15829: }
7616 2, 9, // 15834: case 0x2: {
7617 OPC_CheckField, 16, 5, 0, // 15836: check Inst[20:16] == 0x0
7618 OPC_Decode, 217, 9, 196, 1, // 15840: decode to FMR_rec using decoder 196
7619 // 15840: }
7620 4, 9, // 15845: case 0x4: {
7621 OPC_CheckField, 16, 5, 0, // 15847: check Inst[20:16] == 0x0
7622 OPC_Decode, 229, 9, 196, 1, // 15851: decode to FNABSS_rec using decoder 196
7623 // 15851: }
7624 8, 9, // 15856: case 0x8: {
7625 OPC_CheckField, 16, 5, 0, // 15858: check Inst[20:16] == 0x0
7626 OPC_Decode, 169, 9, 196, 1, // 15862: decode to FABSS_rec using decoder 196
7627 // 15862: }
7628 12, 9, // 15867: case 0xc: {
7629 OPC_CheckField, 16, 5, 0, // 15869: check Inst[20:16] == 0x0
7630 OPC_Decode, 253, 9, 196, 1, // 15873: decode to FRINS_rec using decoder 196
7631 // 15873: }
7632 13, 9, // 15878: case 0xd: {
7633 OPC_CheckField, 16, 5, 0, // 15880: check Inst[20:16] == 0x0
7634 OPC_Decode, 133, 10, 196, 1, // 15884: decode to FRIZS_rec using decoder 196
7635 // 15884: }
7636 14, 9, // 15889: case 0xe: {
7637 OPC_CheckField, 16, 5, 0, // 15891: check Inst[20:16] == 0x0
7638 OPC_Decode, 129, 10, 196, 1, // 15895: decode to FRIPS_rec using decoder 196
7639 // 15895: }
7640 15, 0, // 15900: case 0xf: {
7641 OPC_CheckField, 16, 5, 0, // 15902: check Inst[20:16] == 0x0
7642 OPC_Decode, 249, 9, 196, 1, // 15906: decode to FRIMS_rec using decoder 196
7643 // 15906: }
7644 // 15906: } // switch Inst[10:6]
7645 // 15906: }
7646 24, 13, // 15911: case 0x18: {
7647 OPC_CheckField, 16, 5, 0, // 15913: check Inst[20:16] == 0x0
7648 OPC_CheckField, 6, 5, 0, // 15917: check Inst[10:6] == 0x0
7649 OPC_Decode, 134, 10, 194, 1, // 15921: decode to FRSP using decoder 194
7650 // 15921: }
7651 25, 13, // 15926: case 0x19: {
7652 OPC_CheckField, 16, 5, 0, // 15928: check Inst[20:16] == 0x0
7653 OPC_CheckField, 6, 5, 0, // 15932: check Inst[10:6] == 0x0
7654 OPC_Decode, 135, 10, 194, 1, // 15936: decode to FRSP_rec using decoder 194
7655 // 15936: }
7656 28, 69, // 15941: case 0x1c: {
7657 OPC_SwitchField, 6, 5, // 15943: switch Inst[10:6] {
7658 0, 9, // 15946: case 0x0: {
7659 OPC_CheckField, 16, 5, 0, // 15948: check Inst[20:16] == 0x0
7660 OPC_Decode, 199, 9, 173, 1, // 15952: decode to FCTIW using decoder 173
7661 // 15952: }
7662 4, 9, // 15957: case 0x4: {
7663 OPC_CheckField, 16, 5, 0, // 15959: check Inst[20:16] == 0x0
7664 OPC_Decode, 200, 9, 173, 1, // 15963: decode to FCTIWU using decoder 173
7665 // 15963: }
7666 25, 9, // 15968: case 0x19: {
7667 OPC_CheckField, 16, 5, 0, // 15970: check Inst[20:16] == 0x0
7668 OPC_Decode, 191, 9, 173, 1, // 15974: decode to FCTID using decoder 173
7669 // 15974: }
7670 26, 9, // 15979: case 0x1a: {
7671 OPC_CheckField, 16, 5, 0, // 15981: check Inst[20:16] == 0x0
7672 OPC_Decode, 175, 9, 173, 1, // 15985: decode to FCFID using decoder 173
7673 // 15985: }
7674 29, 9, // 15990: case 0x1d: {
7675 OPC_CheckField, 16, 5, 0, // 15992: check Inst[20:16] == 0x0
7676 OPC_Decode, 192, 9, 173, 1, // 15996: decode to FCTIDU using decoder 173
7677 // 15996: }
7678 30, 0, // 16001: case 0x1e: {
7679 OPC_CheckField, 16, 5, 0, // 16003: check Inst[20:16] == 0x0
7680 OPC_Decode, 178, 9, 173, 1, // 16007: decode to FCFIDU using decoder 173
7681 // 16007: }
7682 // 16007: } // switch Inst[10:6]
7683 // 16007: }
7684 29, 69, // 16012: case 0x1d: {
7685 OPC_SwitchField, 6, 5, // 16014: switch Inst[10:6] {
7686 0, 9, // 16017: case 0x0: {
7687 OPC_CheckField, 16, 5, 0, // 16019: check Inst[20:16] == 0x0
7688 OPC_Decode, 206, 9, 173, 1, // 16023: decode to FCTIW_rec using decoder 173
7689 // 16023: }
7690 4, 9, // 16028: case 0x4: {
7691 OPC_CheckField, 16, 5, 0, // 16030: check Inst[20:16] == 0x0
7692 OPC_Decode, 203, 9, 173, 1, // 16034: decode to FCTIWU_rec using decoder 173
7693 // 16034: }
7694 25, 9, // 16039: case 0x19: {
7695 OPC_CheckField, 16, 5, 0, // 16041: check Inst[20:16] == 0x0
7696 OPC_Decode, 198, 9, 173, 1, // 16045: decode to FCTID_rec using decoder 173
7697 // 16045: }
7698 26, 9, // 16050: case 0x1a: {
7699 OPC_CheckField, 16, 5, 0, // 16052: check Inst[20:16] == 0x0
7700 OPC_Decode, 182, 9, 173, 1, // 16056: decode to FCFID_rec using decoder 173
7701 // 16056: }
7702 29, 9, // 16061: case 0x1d: {
7703 OPC_CheckField, 16, 5, 0, // 16063: check Inst[20:16] == 0x0
7704 OPC_Decode, 195, 9, 173, 1, // 16067: decode to FCTIDU_rec using decoder 173
7705 // 16067: }
7706 30, 0, // 16072: case 0x1e: {
7707 OPC_CheckField, 16, 5, 0, // 16074: check Inst[20:16] == 0x0
7708 OPC_Decode, 181, 9, 173, 1, // 16078: decode to FCFIDU_rec using decoder 173
7709 // 16078: }
7710 // 16078: } // switch Inst[10:6]
7711 // 16078: }
7712 30, 47, // 16083: case 0x1e: {
7713 OPC_SwitchField, 6, 5, // 16085: switch Inst[10:6] {
7714 0, 9, // 16088: case 0x0: {
7715 OPC_CheckField, 16, 5, 0, // 16090: check Inst[20:16] == 0x0
7716 OPC_Decode, 204, 9, 173, 1, // 16094: decode to FCTIWZ using decoder 173
7717 // 16094: }
7718 4, 9, // 16099: case 0x4: {
7719 OPC_CheckField, 16, 5, 0, // 16101: check Inst[20:16] == 0x0
7720 OPC_Decode, 201, 9, 173, 1, // 16105: decode to FCTIWUZ using decoder 173
7721 // 16105: }
7722 25, 9, // 16110: case 0x19: {
7723 OPC_CheckField, 16, 5, 0, // 16112: check Inst[20:16] == 0x0
7724 OPC_Decode, 196, 9, 173, 1, // 16116: decode to FCTIDZ using decoder 173
7725 // 16116: }
7726 29, 0, // 16121: case 0x1d: {
7727 OPC_CheckField, 16, 5, 0, // 16123: check Inst[20:16] == 0x0
7728 OPC_Decode, 193, 9, 173, 1, // 16127: decode to FCTIDUZ using decoder 173
7729 // 16127: }
7730 // 16127: } // switch Inst[10:6]
7731 // 16127: }
7732 31, 47, // 16132: case 0x1f: {
7733 OPC_SwitchField, 6, 5, // 16134: switch Inst[10:6] {
7734 0, 9, // 16137: case 0x0: {
7735 OPC_CheckField, 16, 5, 0, // 16139: check Inst[20:16] == 0x0
7736 OPC_Decode, 205, 9, 173, 1, // 16143: decode to FCTIWZ_rec using decoder 173
7737 // 16143: }
7738 4, 9, // 16148: case 0x4: {
7739 OPC_CheckField, 16, 5, 0, // 16150: check Inst[20:16] == 0x0
7740 OPC_Decode, 202, 9, 173, 1, // 16154: decode to FCTIWUZ_rec using decoder 173
7741 // 16154: }
7742 25, 9, // 16159: case 0x19: {
7743 OPC_CheckField, 16, 5, 0, // 16161: check Inst[20:16] == 0x0
7744 OPC_Decode, 197, 9, 173, 1, // 16165: decode to FCTIDZ_rec using decoder 173
7745 // 16165: }
7746 29, 0, // 16170: case 0x1d: {
7747 OPC_CheckField, 16, 5, 0, // 16172: check Inst[20:16] == 0x0
7748 OPC_Decode, 194, 9, 173, 1, // 16176: decode to FCTIDUZ_rec using decoder 173
7749 // 16176: }
7750 // 16176: } // switch Inst[10:6]
7751 // 16176: }
7752 36, 9, // 16181: case 0x24: {
7753 OPC_CheckField, 6, 5, 0, // 16183: check Inst[10:6] == 0x0
7754 OPC_Decode, 207, 9, 172, 1, // 16187: decode to FDIV using decoder 172
7755 // 16187: }
7756 37, 9, // 16192: case 0x25: {
7757 OPC_CheckField, 6, 5, 0, // 16194: check Inst[10:6] == 0x0
7758 OPC_Decode, 210, 9, 172, 1, // 16198: decode to FDIV_rec using decoder 172
7759 // 16198: }
7760 40, 9, // 16203: case 0x28: {
7761 OPC_CheckField, 6, 5, 0, // 16205: check Inst[10:6] == 0x0
7762 OPC_Decode, 148, 10, 172, 1, // 16209: decode to FSUB using decoder 172
7763 // 16209: }
7764 41, 9, // 16214: case 0x29: {
7765 OPC_CheckField, 6, 5, 0, // 16216: check Inst[10:6] == 0x0
7766 OPC_Decode, 151, 10, 172, 1, // 16220: decode to FSUB_rec using decoder 172
7767 // 16220: }
7768 42, 9, // 16225: case 0x2a: {
7769 OPC_CheckField, 6, 5, 0, // 16227: check Inst[10:6] == 0x0
7770 OPC_Decode, 170, 9, 172, 1, // 16231: decode to FADD using decoder 172
7771 // 16231: }
7772 43, 9, // 16236: case 0x2b: {
7773 OPC_CheckField, 6, 5, 0, // 16238: check Inst[10:6] == 0x0
7774 OPC_Decode, 173, 9, 172, 1, // 16242: decode to FADD_rec using decoder 172
7775 // 16242: }
7776 44, 13, // 16247: case 0x2c: {
7777 OPC_CheckField, 16, 5, 0, // 16249: check Inst[20:16] == 0x0
7778 OPC_CheckField, 6, 5, 0, // 16253: check Inst[10:6] == 0x0
7779 OPC_Decode, 144, 10, 173, 1, // 16257: decode to FSQRT using decoder 173
7780 // 16257: }
7781 45, 13, // 16262: case 0x2d: {
7782 OPC_CheckField, 16, 5, 0, // 16264: check Inst[20:16] == 0x0
7783 OPC_CheckField, 6, 5, 0, // 16268: check Inst[10:6] == 0x0
7784 OPC_Decode, 147, 10, 173, 1, // 16272: decode to FSQRT_rec using decoder 173
7785 // 16272: }
7786 46, 5, // 16277: case 0x2e: {
7787 OPC_Decode, 142, 10, 146, 2, // 16279: decode to FSELS using decoder 274
7788 // 16279: }
7789 47, 5, // 16284: case 0x2f: {
7790 OPC_Decode, 143, 10, 146, 2, // 16286: decode to FSELS_rec using decoder 274
7791 // 16286: }
7792 48, 13, // 16291: case 0x30: {
7793 OPC_CheckField, 16, 5, 0, // 16293: check Inst[20:16] == 0x0
7794 OPC_CheckField, 6, 5, 0, // 16297: check Inst[10:6] == 0x0
7795 OPC_Decode, 242, 9, 173, 1, // 16301: decode to FRE using decoder 173
7796 // 16301: }
7797 49, 13, // 16306: case 0x31: {
7798 OPC_CheckField, 16, 5, 0, // 16308: check Inst[20:16] == 0x0
7799 OPC_CheckField, 6, 5, 0, // 16312: check Inst[10:6] == 0x0
7800 OPC_Decode, 245, 9, 173, 1, // 16316: decode to FRE_rec using decoder 173
7801 // 16316: }
7802 50, 9, // 16321: case 0x32: {
7803 OPC_CheckField, 11, 5, 0, // 16323: check Inst[15:11] == 0x0
7804 OPC_Decode, 222, 9, 147, 2, // 16327: decode to FMUL using decoder 275
7805 // 16327: }
7806 51, 9, // 16332: case 0x33: {
7807 OPC_CheckField, 11, 5, 0, // 16334: check Inst[15:11] == 0x0
7808 OPC_Decode, 225, 9, 147, 2, // 16338: decode to FMUL_rec using decoder 275
7809 // 16338: }
7810 52, 13, // 16343: case 0x34: {
7811 OPC_CheckField, 16, 5, 0, // 16345: check Inst[20:16] == 0x0
7812 OPC_CheckField, 6, 5, 0, // 16349: check Inst[10:6] == 0x0
7813 OPC_Decode, 136, 10, 173, 1, // 16353: decode to FRSQRTE using decoder 173
7814 // 16353: }
7815 53, 13, // 16358: case 0x35: {
7816 OPC_CheckField, 16, 5, 0, // 16360: check Inst[20:16] == 0x0
7817 OPC_CheckField, 6, 5, 0, // 16364: check Inst[10:6] == 0x0
7818 OPC_Decode, 139, 10, 173, 1, // 16368: decode to FRSQRTE_rec using decoder 173
7819 // 16368: }
7820 56, 5, // 16373: case 0x38: {
7821 OPC_Decode, 218, 9, 148, 2, // 16375: decode to FMSUB using decoder 276
7822 // 16375: }
7823 57, 5, // 16380: case 0x39: {
7824 OPC_Decode, 221, 9, 148, 2, // 16382: decode to FMSUB_rec using decoder 276
7825 // 16382: }
7826 58, 5, // 16387: case 0x3a: {
7827 OPC_Decode, 212, 9, 148, 2, // 16389: decode to FMADD using decoder 276
7828 // 16389: }
7829 59, 5, // 16394: case 0x3b: {
7830 OPC_Decode, 215, 9, 148, 2, // 16396: decode to FMADD_rec using decoder 276
7831 // 16396: }
7832 60, 5, // 16401: case 0x3c: {
7833 OPC_Decode, 238, 9, 148, 2, // 16403: decode to FNMSUB using decoder 276
7834 // 16403: }
7835 61, 5, // 16408: case 0x3d: {
7836 OPC_Decode, 241, 9, 148, 2, // 16410: decode to FNMSUB_rec using decoder 276
7837 // 16410: }
7838 62, 5, // 16415: case 0x3e: {
7839 OPC_Decode, 234, 9, 148, 2, // 16417: decode to FNMADD using decoder 276
7840 // 16417: }
7841 63, 0, // 16422: case 0x3f: {
7842 OPC_Decode, 237, 9, 148, 2, // 16424: decode to FNMADD_rec using decoder 276
7843 // 16424: }
7844 // 16424: } // switch Inst[5:0]
7845 // 16424: }
7846 // 16424: } // switch Inst[31:26]
7847};
7848static const uint8_t DecoderTableSPE32[3347] = {
7849 OPC_SwitchField, 3, 8, // 0: switch Inst[10:3] {
7850 64, 47, // 3: case 0x40: {
7851 OPC_SwitchField, 0, 3, // 5: switch Inst[2:0] {
7852 0, 9, // 8: case 0x0: {
7853 OPC_CheckField, 26, 6, 4, // 10: check Inst[31:26] == 0x4
7854 OPC_Decode, 213, 7, 149, 2, // 14: decode to EVADDW using decoder 277
7855 // 14: }
7856 2, 9, // 19: case 0x2: {
7857 OPC_CheckField, 26, 6, 4, // 21: check Inst[31:26] == 0x4
7858 OPC_Decode, 208, 7, 150, 2, // 25: decode to EVADDIW using decoder 278
7859 // 25: }
7860 4, 9, // 30: case 0x4: {
7861 OPC_CheckField, 26, 6, 4, // 32: check Inst[31:26] == 0x4
7862 OPC_Decode, 143, 9, 149, 2, // 36: decode to EVSUBFW using decoder 277
7863 // 36: }
7864 6, 0, // 41: case 0x6: {
7865 OPC_CheckField, 26, 6, 4, // 43: check Inst[31:26] == 0x4
7866 OPC_Decode, 144, 9, 151, 2, // 47: decode to EVSUBIFW using decoder 279
7867 // 47: }
7868 // 47: } // switch Inst[2:0]
7869 // 47: }
7870 65, 118, // 52: case 0x41: {
7871 OPC_SwitchField, 0, 3, // 54: switch Inst[2:0] {
7872 0, 13, // 57: case 0x0: {
7873 OPC_CheckField, 26, 6, 4, // 59: check Inst[31:26] == 0x4
7874 OPC_CheckField, 11, 5, 0, // 63: check Inst[15:11] == 0x0
7875 OPC_Decode, 207, 7, 152, 2, // 67: decode to EVABS using decoder 280
7876 // 67: }
7877 1, 13, // 72: case 0x1: {
7878 OPC_CheckField, 26, 6, 4, // 74: check Inst[31:26] == 0x4
7879 OPC_CheckField, 11, 5, 0, // 78: check Inst[15:11] == 0x0
7880 OPC_Decode, 237, 8, 152, 2, // 82: decode to EVNEG using decoder 280
7881 // 82: }
7882 2, 13, // 87: case 0x2: {
7883 OPC_CheckField, 26, 6, 4, // 89: check Inst[31:26] == 0x4
7884 OPC_CheckField, 11, 5, 0, // 93: check Inst[15:11] == 0x0
7885 OPC_Decode, 226, 7, 152, 2, // 97: decode to EVEXTSB using decoder 280
7886 // 97: }
7887 3, 13, // 102: case 0x3: {
7888 OPC_CheckField, 26, 6, 4, // 104: check Inst[31:26] == 0x4
7889 OPC_CheckField, 11, 5, 0, // 108: check Inst[15:11] == 0x0
7890 OPC_Decode, 227, 7, 152, 2, // 112: decode to EVEXTSH using decoder 280
7891 // 112: }
7892 4, 13, // 117: case 0x4: {
7893 OPC_CheckField, 26, 6, 4, // 119: check Inst[31:26] == 0x4
7894 OPC_CheckField, 11, 5, 0, // 123: check Inst[15:11] == 0x0
7895 OPC_Decode, 243, 8, 152, 2, // 127: decode to EVRNDW using decoder 280
7896 // 127: }
7897 5, 13, // 132: case 0x5: {
7898 OPC_CheckField, 26, 6, 4, // 134: check Inst[31:26] == 0x4
7899 OPC_CheckField, 11, 5, 0, // 138: check Inst[15:11] == 0x0
7900 OPC_Decode, 222, 7, 152, 2, // 142: decode to EVCNTLZW using decoder 280
7901 // 142: }
7902 6, 13, // 147: case 0x6: {
7903 OPC_CheckField, 26, 6, 4, // 149: check Inst[31:26] == 0x4
7904 OPC_CheckField, 11, 5, 0, // 153: check Inst[15:11] == 0x0
7905 OPC_Decode, 221, 7, 152, 2, // 157: decode to EVCNTLSW using decoder 280
7906 // 157: }
7907 7, 0, // 162: case 0x7: {
7908 OPC_CheckField, 26, 6, 4, // 164: check Inst[31:26] == 0x4
7909 OPC_Decode, 165, 5, 81, // 168: decode to BRINC using decoder 81
7910 // 168: }
7911 // 168: } // switch Inst[2:0]
7912 // 168: }
7913 66, 47, // 172: case 0x42: {
7914 OPC_SwitchField, 0, 3, // 174: switch Inst[2:0] {
7915 1, 9, // 177: case 0x1: {
7916 OPC_CheckField, 26, 6, 4, // 179: check Inst[31:26] == 0x4
7917 OPC_Decode, 214, 7, 149, 2, // 183: decode to EVAND using decoder 277
7918 // 183: }
7919 2, 9, // 188: case 0x2: {
7920 OPC_CheckField, 26, 6, 4, // 190: check Inst[31:26] == 0x4
7921 OPC_Decode, 215, 7, 149, 2, // 194: decode to EVANDC using decoder 277
7922 // 194: }
7923 6, 9, // 199: case 0x6: {
7924 OPC_CheckField, 26, 6, 4, // 201: check Inst[31:26] == 0x4
7925 OPC_Decode, 145, 9, 149, 2, // 205: decode to EVXOR using decoder 277
7926 // 205: }
7927 7, 0, // 210: case 0x7: {
7928 OPC_CheckField, 26, 6, 4, // 212: check Inst[31:26] == 0x4
7929 OPC_Decode, 239, 8, 149, 2, // 216: decode to EVOR using decoder 277
7930 // 216: }
7931 // 216: } // switch Inst[2:0]
7932 // 216: }
7933 67, 47, // 221: case 0x43: {
7934 OPC_SwitchField, 0, 3, // 223: switch Inst[2:0] {
7935 0, 9, // 226: case 0x0: {
7936 OPC_CheckField, 26, 6, 4, // 228: check Inst[31:26] == 0x4
7937 OPC_Decode, 238, 8, 149, 2, // 232: decode to EVNOR using decoder 277
7938 // 232: }
7939 1, 9, // 237: case 0x1: {
7940 OPC_CheckField, 26, 6, 4, // 239: check Inst[31:26] == 0x4
7941 OPC_Decode, 225, 7, 149, 2, // 243: decode to EVEQV using decoder 277
7942 // 243: }
7943 3, 9, // 248: case 0x3: {
7944 OPC_CheckField, 26, 6, 4, // 250: check Inst[31:26] == 0x4
7945 OPC_Decode, 240, 8, 149, 2, // 254: decode to EVORC using decoder 277
7946 // 254: }
7947 6, 0, // 259: case 0x6: {
7948 OPC_CheckField, 26, 6, 4, // 261: check Inst[31:26] == 0x4
7949 OPC_Decode, 236, 8, 149, 2, // 265: decode to EVNAND using decoder 277
7950 // 265: }
7951 // 265: } // switch Inst[2:0]
7952 // 265: }
7953 68, 69, // 270: case 0x44: {
7954 OPC_SwitchField, 0, 3, // 272: switch Inst[2:0] {
7955 0, 9, // 275: case 0x0: {
7956 OPC_CheckField, 26, 6, 4, // 277: check Inst[31:26] == 0x4
7957 OPC_Decode, 252, 8, 149, 2, // 281: decode to EVSRWU using decoder 277
7958 // 281: }
7959 1, 9, // 286: case 0x1: {
7960 OPC_CheckField, 26, 6, 4, // 288: check Inst[31:26] == 0x4
7961 OPC_Decode, 251, 8, 149, 2, // 292: decode to EVSRWS using decoder 277
7962 // 292: }
7963 2, 9, // 297: case 0x2: {
7964 OPC_CheckField, 26, 6, 4, // 299: check Inst[31:26] == 0x4
7965 OPC_Decode, 250, 8, 150, 2, // 303: decode to EVSRWIU using decoder 278
7966 // 303: }
7967 3, 9, // 308: case 0x3: {
7968 OPC_CheckField, 26, 6, 4, // 310: check Inst[31:26] == 0x4
7969 OPC_Decode, 249, 8, 150, 2, // 314: decode to EVSRWIS using decoder 278
7970 // 314: }
7971 4, 9, // 319: case 0x4: {
7972 OPC_CheckField, 26, 6, 4, // 321: check Inst[31:26] == 0x4
7973 OPC_Decode, 245, 8, 149, 2, // 325: decode to EVSLW using decoder 277
7974 // 325: }
7975 6, 0, // 330: case 0x6: {
7976 OPC_CheckField, 26, 6, 4, // 332: check Inst[31:26] == 0x4
7977 OPC_Decode, 246, 8, 150, 2, // 336: decode to EVSLWI using decoder 278
7978 // 336: }
7979 // 336: } // switch Inst[2:0]
7980 // 336: }
7981 69, 99, // 341: case 0x45: {
7982 OPC_SwitchField, 0, 3, // 343: switch Inst[2:0] {
7983 0, 9, // 346: case 0x0: {
7984 OPC_CheckField, 26, 6, 4, // 348: check Inst[31:26] == 0x4
7985 OPC_Decode, 241, 8, 149, 2, // 352: decode to EVRLW using decoder 277
7986 // 352: }
7987 1, 13, // 357: case 0x1: {
7988 OPC_CheckField, 26, 6, 4, // 359: check Inst[31:26] == 0x4
7989 OPC_CheckField, 11, 5, 0, // 363: check Inst[15:11] == 0x0
7990 OPC_Decode, 248, 8, 153, 2, // 367: decode to EVSPLATI using decoder 281
7991 // 367: }
7992 2, 9, // 372: case 0x2: {
7993 OPC_CheckField, 26, 6, 4, // 374: check Inst[31:26] == 0x4
7994 OPC_Decode, 242, 8, 150, 2, // 378: decode to EVRLWI using decoder 278
7995 // 378: }
7996 3, 13, // 383: case 0x3: {
7997 OPC_CheckField, 26, 6, 4, // 385: check Inst[31:26] == 0x4
7998 OPC_CheckField, 11, 5, 0, // 389: check Inst[15:11] == 0x0
7999 OPC_Decode, 247, 8, 153, 2, // 393: decode to EVSPLATFI using decoder 281
8000 // 393: }
8001 4, 9, // 398: case 0x4: {
8002 OPC_CheckField, 26, 6, 4, // 400: check Inst[31:26] == 0x4
8003 OPC_Decode, 145, 8, 149, 2, // 404: decode to EVMERGEHI using decoder 277
8004 // 404: }
8005 5, 9, // 409: case 0x5: {
8006 OPC_CheckField, 26, 6, 4, // 411: check Inst[31:26] == 0x4
8007 OPC_Decode, 147, 8, 154, 2, // 415: decode to EVMERGELO using decoder 282
8008 // 415: }
8009 6, 9, // 420: case 0x6: {
8010 OPC_CheckField, 26, 6, 4, // 422: check Inst[31:26] == 0x4
8011 OPC_Decode, 146, 8, 149, 2, // 426: decode to EVMERGEHILO using decoder 277
8012 // 426: }
8013 7, 0, // 431: case 0x7: {
8014 OPC_CheckField, 26, 6, 4, // 433: check Inst[31:26] == 0x4
8015 OPC_Decode, 148, 8, 149, 2, // 437: decode to EVMERGELOHI using decoder 277
8016 // 437: }
8017 // 437: } // switch Inst[2:0]
8018 // 437: }
8019 70, 78, // 442: case 0x46: {
8020 OPC_SwitchField, 0, 3, // 444: switch Inst[2:0] {
8021 0, 13, // 447: case 0x0: {
8022 OPC_CheckField, 26, 6, 4, // 449: check Inst[31:26] == 0x4
8023 OPC_CheckField, 21, 2, 0, // 453: check Inst[22:21] == 0x0
8024 OPC_Decode, 218, 7, 155, 2, // 457: decode to EVCMPGTU using decoder 283
8025 // 457: }
8026 1, 13, // 462: case 0x1: {
8027 OPC_CheckField, 26, 6, 4, // 464: check Inst[31:26] == 0x4
8028 OPC_CheckField, 21, 2, 0, // 468: check Inst[22:21] == 0x0
8029 OPC_Decode, 217, 7, 155, 2, // 472: decode to EVCMPGTS using decoder 283
8030 // 472: }
8031 2, 13, // 477: case 0x2: {
8032 OPC_CheckField, 26, 6, 4, // 479: check Inst[31:26] == 0x4
8033 OPC_CheckField, 21, 2, 0, // 483: check Inst[22:21] == 0x0
8034 OPC_Decode, 220, 7, 155, 2, // 487: decode to EVCMPLTU using decoder 283
8035 // 487: }
8036 3, 13, // 492: case 0x3: {
8037 OPC_CheckField, 26, 6, 4, // 494: check Inst[31:26] == 0x4
8038 OPC_CheckField, 21, 2, 0, // 498: check Inst[22:21] == 0x0
8039 OPC_Decode, 219, 7, 155, 2, // 502: decode to EVCMPLTS using decoder 283
8040 // 502: }
8041 4, 0, // 507: case 0x4: {
8042 OPC_CheckField, 26, 6, 4, // 509: check Inst[31:26] == 0x4
8043 OPC_CheckField, 21, 2, 0, // 513: check Inst[22:21] == 0x0
8044 OPC_Decode, 216, 7, 155, 2, // 517: decode to EVCMPEQ using decoder 283
8045 // 517: }
8046 // 517: } // switch Inst[2:0]
8047 // 517: }
8048 79, 9, // 522: case 0x4f: {
8049 OPC_CheckField, 26, 6, 4, // 524: check Inst[31:26] == 0x4
8050 OPC_Decode, 244, 8, 156, 2, // 528: decode to EVSEL using decoder 284
8051 // 528: }
8052 80, 70, // 533: case 0x50: {
8053 OPC_SwitchField, 0, 3, // 535: switch Inst[2:0] {
8054 0, 9, // 538: case 0x0: {
8055 OPC_CheckField, 26, 6, 4, // 540: check Inst[31:26] == 0x4
8056 OPC_Decode, 229, 7, 149, 2, // 544: decode to EVFSADD using decoder 277
8057 // 544: }
8058 1, 9, // 549: case 0x1: {
8059 OPC_CheckField, 26, 6, 4, // 551: check Inst[31:26] == 0x4
8060 OPC_Decode, 247, 7, 149, 2, // 555: decode to EVFSSUB using decoder 277
8061 // 555: }
8062 4, 13, // 560: case 0x4: {
8063 OPC_CheckField, 26, 6, 4, // 562: check Inst[31:26] == 0x4
8064 OPC_CheckField, 11, 5, 0, // 566: check Inst[15:11] == 0x0
8065 OPC_Decode, 228, 7, 152, 2, // 570: decode to EVFSABS using decoder 280
8066 // 570: }
8067 5, 13, // 575: case 0x5: {
8068 OPC_CheckField, 26, 6, 4, // 577: check Inst[31:26] == 0x4
8069 OPC_CheckField, 11, 5, 0, // 581: check Inst[15:11] == 0x0
8070 OPC_Decode, 245, 7, 152, 2, // 585: decode to EVFSNABS using decoder 280
8071 // 585: }
8072 6, 0, // 590: case 0x6: {
8073 OPC_CheckField, 26, 6, 4, // 592: check Inst[31:26] == 0x4
8074 OPC_CheckField, 11, 5, 0, // 596: check Inst[15:11] == 0x0
8075 OPC_Decode, 246, 7, 152, 2, // 600: decode to EVFSNEG using decoder 280
8076 // 600: }
8077 // 600: } // switch Inst[2:0]
8078 // 600: }
8079 81, 85, // 605: case 0x51: {
8080 OPC_SwitchField, 0, 3, // 607: switch Inst[2:0] {
8081 0, 9, // 610: case 0x0: {
8082 OPC_CheckField, 26, 6, 4, // 612: check Inst[31:26] == 0x4
8083 OPC_Decode, 244, 7, 149, 2, // 616: decode to EVFSMUL using decoder 277
8084 // 616: }
8085 1, 9, // 621: case 0x1: {
8086 OPC_CheckField, 26, 6, 4, // 623: check Inst[31:26] == 0x4
8087 OPC_Decode, 243, 7, 149, 2, // 627: decode to EVFSDIV using decoder 277
8088 // 627: }
8089 2, 13, // 632: case 0x2: {
8090 OPC_CheckField, 26, 6, 4, // 634: check Inst[31:26] == 0x4
8091 OPC_CheckField, 16, 5, 0, // 638: check Inst[20:16] == 0x0
8092 OPC_Decode, 233, 7, 157, 2, // 642: decode to EVFSCFUI using decoder 285
8093 // 642: }
8094 4, 13, // 647: case 0x4: {
8095 OPC_CheckField, 26, 6, 4, // 649: check Inst[31:26] == 0x4
8096 OPC_CheckField, 21, 2, 0, // 653: check Inst[22:21] == 0x0
8097 OPC_Decode, 235, 7, 155, 2, // 657: decode to EVFSCMPGT using decoder 283
8098 // 657: }
8099 5, 13, // 662: case 0x5: {
8100 OPC_CheckField, 26, 6, 4, // 664: check Inst[31:26] == 0x4
8101 OPC_CheckField, 21, 2, 0, // 668: check Inst[22:21] == 0x0
8102 OPC_Decode, 236, 7, 155, 2, // 672: decode to EVFSCMPLT using decoder 283
8103 // 672: }
8104 6, 0, // 677: case 0x6: {
8105 OPC_CheckField, 26, 6, 4, // 679: check Inst[31:26] == 0x4
8106 OPC_CheckField, 21, 2, 0, // 683: check Inst[22:21] == 0x0
8107 OPC_Decode, 234, 7, 155, 2, // 687: decode to EVFSCMPEQ using decoder 283
8108 // 687: }
8109 // 687: } // switch Inst[2:0]
8110 // 687: }
8111 82, 108, // 692: case 0x52: {
8112 OPC_SwitchField, 0, 3, // 694: switch Inst[2:0] {
8113 1, 13, // 697: case 0x1: {
8114 OPC_CheckField, 26, 6, 4, // 699: check Inst[31:26] == 0x4
8115 OPC_CheckField, 16, 5, 0, // 703: check Inst[20:16] == 0x0
8116 OPC_Decode, 231, 7, 157, 2, // 707: decode to EVFSCFSI using decoder 285
8117 // 707: }
8118 2, 13, // 712: case 0x2: {
8119 OPC_CheckField, 26, 6, 4, // 714: check Inst[31:26] == 0x4
8120 OPC_CheckField, 16, 5, 0, // 718: check Inst[20:16] == 0x0
8121 OPC_Decode, 232, 7, 157, 2, // 722: decode to EVFSCFUF using decoder 285
8122 // 722: }
8123 3, 13, // 727: case 0x3: {
8124 OPC_CheckField, 26, 6, 4, // 729: check Inst[31:26] == 0x4
8125 OPC_CheckField, 16, 5, 0, // 733: check Inst[20:16] == 0x0
8126 OPC_Decode, 230, 7, 157, 2, // 737: decode to EVFSCFSF using decoder 285
8127 // 737: }
8128 4, 13, // 742: case 0x4: {
8129 OPC_CheckField, 26, 6, 4, // 744: check Inst[31:26] == 0x4
8130 OPC_CheckField, 16, 5, 0, // 748: check Inst[20:16] == 0x0
8131 OPC_Decode, 241, 7, 157, 2, // 752: decode to EVFSCTUI using decoder 285
8132 // 752: }
8133 5, 13, // 757: case 0x5: {
8134 OPC_CheckField, 26, 6, 4, // 759: check Inst[31:26] == 0x4
8135 OPC_CheckField, 16, 5, 0, // 763: check Inst[20:16] == 0x0
8136 OPC_Decode, 238, 7, 157, 2, // 767: decode to EVFSCTSI using decoder 285
8137 // 767: }
8138 6, 13, // 772: case 0x6: {
8139 OPC_CheckField, 26, 6, 4, // 774: check Inst[31:26] == 0x4
8140 OPC_CheckField, 16, 5, 0, // 778: check Inst[20:16] == 0x0
8141 OPC_Decode, 240, 7, 157, 2, // 782: decode to EVFSCTUF using decoder 285
8142 // 782: }
8143 7, 0, // 787: case 0x7: {
8144 OPC_CheckField, 26, 6, 4, // 789: check Inst[31:26] == 0x4
8145 OPC_CheckField, 16, 5, 0, // 793: check Inst[20:16] == 0x0
8146 OPC_Decode, 237, 7, 157, 2, // 797: decode to EVFSCTSF using decoder 285
8147 // 797: }
8148 // 797: } // switch Inst[2:0]
8149 // 797: }
8150 83, 78, // 802: case 0x53: {
8151 OPC_SwitchField, 0, 3, // 804: switch Inst[2:0] {
8152 0, 13, // 807: case 0x0: {
8153 OPC_CheckField, 26, 6, 4, // 809: check Inst[31:26] == 0x4
8154 OPC_CheckField, 16, 5, 0, // 813: check Inst[20:16] == 0x0
8155 OPC_Decode, 242, 7, 157, 2, // 817: decode to EVFSCTUIZ using decoder 285
8156 // 817: }
8157 2, 13, // 822: case 0x2: {
8158 OPC_CheckField, 26, 6, 4, // 824: check Inst[31:26] == 0x4
8159 OPC_CheckField, 16, 5, 0, // 828: check Inst[20:16] == 0x0
8160 OPC_Decode, 239, 7, 157, 2, // 832: decode to EVFSCTSIZ using decoder 285
8161 // 832: }
8162 4, 13, // 837: case 0x4: {
8163 OPC_CheckField, 26, 6, 4, // 839: check Inst[31:26] == 0x4
8164 OPC_CheckField, 21, 2, 0, // 843: check Inst[22:21] == 0x0
8165 OPC_Decode, 249, 7, 155, 2, // 847: decode to EVFSTSTGT using decoder 283
8166 // 847: }
8167 5, 13, // 852: case 0x5: {
8168 OPC_CheckField, 26, 6, 4, // 854: check Inst[31:26] == 0x4
8169 OPC_CheckField, 21, 2, 0, // 858: check Inst[22:21] == 0x0
8170 OPC_Decode, 250, 7, 155, 2, // 862: decode to EVFSTSTLT using decoder 283
8171 // 862: }
8172 6, 0, // 867: case 0x6: {
8173 OPC_CheckField, 26, 6, 4, // 869: check Inst[31:26] == 0x4
8174 OPC_CheckField, 21, 2, 0, // 873: check Inst[22:21] == 0x0
8175 OPC_Decode, 248, 7, 155, 2, // 877: decode to EVFSTSTEQ using decoder 283
8176 // 877: }
8177 // 877: } // switch Inst[2:0]
8178 // 877: }
8179 88, 65, // 882: case 0x58: {
8180 OPC_SwitchField, 0, 3, // 884: switch Inst[2:0] {
8181 0, 8, // 887: case 0x0: {
8182 OPC_CheckField, 26, 6, 4, // 889: check Inst[31:26] == 0x4
8183 OPC_Decode, 175, 7, 81, // 893: decode to EFSADD using decoder 81
8184 // 893: }
8185 1, 8, // 897: case 0x1: {
8186 OPC_CheckField, 26, 6, 4, // 899: check Inst[31:26] == 0x4
8187 OPC_Decode, 194, 7, 81, // 903: decode to EFSSUB using decoder 81
8188 // 903: }
8189 4, 12, // 907: case 0x4: {
8190 OPC_CheckField, 26, 6, 4, // 909: check Inst[31:26] == 0x4
8191 OPC_CheckField, 11, 5, 0, // 913: check Inst[15:11] == 0x0
8192 OPC_Decode, 174, 7, 84, // 917: decode to EFSABS using decoder 84
8193 // 917: }
8194 5, 12, // 921: case 0x5: {
8195 OPC_CheckField, 26, 6, 4, // 923: check Inst[31:26] == 0x4
8196 OPC_CheckField, 11, 5, 0, // 927: check Inst[15:11] == 0x0
8197 OPC_Decode, 192, 7, 84, // 931: decode to EFSNABS using decoder 84
8198 // 931: }
8199 6, 0, // 935: case 0x6: {
8200 OPC_CheckField, 26, 6, 4, // 937: check Inst[31:26] == 0x4
8201 OPC_CheckField, 11, 5, 0, // 941: check Inst[15:11] == 0x0
8202 OPC_Decode, 193, 7, 84, // 945: decode to EFSNEG using decoder 84
8203 // 945: }
8204 // 945: } // switch Inst[2:0]
8205 // 945: }
8206 89, 80, // 949: case 0x59: {
8207 OPC_SwitchField, 0, 3, // 951: switch Inst[2:0] {
8208 0, 8, // 954: case 0x0: {
8209 OPC_CheckField, 26, 6, 4, // 956: check Inst[31:26] == 0x4
8210 OPC_Decode, 191, 7, 81, // 960: decode to EFSMUL using decoder 81
8211 // 960: }
8212 1, 8, // 964: case 0x1: {
8213 OPC_CheckField, 26, 6, 4, // 966: check Inst[31:26] == 0x4
8214 OPC_Decode, 190, 7, 81, // 970: decode to EFSDIV using decoder 81
8215 // 970: }
8216 4, 12, // 974: case 0x4: {
8217 OPC_CheckField, 26, 6, 4, // 976: check Inst[31:26] == 0x4
8218 OPC_CheckField, 21, 2, 0, // 980: check Inst[22:21] == 0x0
8219 OPC_Decode, 182, 7, 63, // 984: decode to EFSCMPGT using decoder 63
8220 // 984: }
8221 5, 12, // 988: case 0x5: {
8222 OPC_CheckField, 26, 6, 4, // 990: check Inst[31:26] == 0x4
8223 OPC_CheckField, 21, 2, 0, // 994: check Inst[22:21] == 0x0
8224 OPC_Decode, 183, 7, 63, // 998: decode to EFSCMPLT using decoder 63
8225 // 998: }
8226 6, 12, // 1002: case 0x6: {
8227 OPC_CheckField, 26, 6, 4, // 1004: check Inst[31:26] == 0x4
8228 OPC_CheckField, 21, 2, 0, // 1008: check Inst[22:21] == 0x0
8229 OPC_Decode, 181, 7, 63, // 1012: decode to EFSCMPEQ using decoder 63
8230 // 1012: }
8231 7, 0, // 1016: case 0x7: {
8232 OPC_CheckField, 26, 6, 4, // 1018: check Inst[31:26] == 0x4
8233 OPC_CheckField, 16, 5, 0, // 1022: check Inst[20:16] == 0x0
8234 OPC_Decode, 176, 7, 158, 2, // 1026: decode to EFSCFD using decoder 286
8235 // 1026: }
8236 // 1026: } // switch Inst[2:0]
8237 // 1026: }
8238 90, 116, // 1031: case 0x5a: {
8239 OPC_SwitchField, 0, 3, // 1033: switch Inst[2:0] {
8240 0, 12, // 1036: case 0x0: {
8241 OPC_CheckField, 26, 6, 4, // 1038: check Inst[31:26] == 0x4
8242 OPC_CheckField, 16, 5, 0, // 1042: check Inst[20:16] == 0x0
8243 OPC_Decode, 180, 7, 118, // 1046: decode to EFSCFUI using decoder 118
8244 // 1046: }
8245 1, 12, // 1050: case 0x1: {
8246 OPC_CheckField, 26, 6, 4, // 1052: check Inst[31:26] == 0x4
8247 OPC_CheckField, 16, 5, 0, // 1056: check Inst[20:16] == 0x0
8248 OPC_Decode, 178, 7, 118, // 1060: decode to EFSCFSI using decoder 118
8249 // 1060: }
8250 2, 12, // 1064: case 0x2: {
8251 OPC_CheckField, 26, 6, 4, // 1066: check Inst[31:26] == 0x4
8252 OPC_CheckField, 16, 5, 0, // 1070: check Inst[20:16] == 0x0
8253 OPC_Decode, 179, 7, 118, // 1074: decode to EFSCFUF using decoder 118
8254 // 1074: }
8255 3, 12, // 1078: case 0x3: {
8256 OPC_CheckField, 26, 6, 4, // 1080: check Inst[31:26] == 0x4
8257 OPC_CheckField, 16, 5, 0, // 1084: check Inst[20:16] == 0x0
8258 OPC_Decode, 177, 7, 118, // 1088: decode to EFSCFSF using decoder 118
8259 // 1088: }
8260 4, 12, // 1092: case 0x4: {
8261 OPC_CheckField, 26, 6, 4, // 1094: check Inst[31:26] == 0x4
8262 OPC_CheckField, 16, 5, 0, // 1098: check Inst[20:16] == 0x0
8263 OPC_Decode, 188, 7, 118, // 1102: decode to EFSCTUI using decoder 118
8264 // 1102: }
8265 5, 12, // 1106: case 0x5: {
8266 OPC_CheckField, 26, 6, 4, // 1108: check Inst[31:26] == 0x4
8267 OPC_CheckField, 16, 5, 0, // 1112: check Inst[20:16] == 0x0
8268 OPC_Decode, 185, 7, 118, // 1116: decode to EFSCTSI using decoder 118
8269 // 1116: }
8270 6, 13, // 1120: case 0x6: {
8271 OPC_CheckField, 26, 6, 4, // 1122: check Inst[31:26] == 0x4
8272 OPC_CheckField, 16, 5, 0, // 1126: check Inst[20:16] == 0x0
8273 OPC_Decode, 187, 7, 159, 2, // 1130: decode to EFSCTUF using decoder 287
8274 // 1130: }
8275 7, 0, // 1135: case 0x7: {
8276 OPC_CheckField, 26, 6, 4, // 1137: check Inst[31:26] == 0x4
8277 OPC_CheckField, 16, 5, 0, // 1141: check Inst[20:16] == 0x0
8278 OPC_Decode, 184, 7, 118, // 1145: decode to EFSCTSF using decoder 118
8279 // 1145: }
8280 // 1145: } // switch Inst[2:0]
8281 // 1145: }
8282 91, 76, // 1149: case 0x5b: {
8283 OPC_SwitchField, 0, 3, // 1151: switch Inst[2:0] {
8284 0, 12, // 1154: case 0x0: {
8285 OPC_CheckField, 26, 6, 4, // 1156: check Inst[31:26] == 0x4
8286 OPC_CheckField, 16, 5, 0, // 1160: check Inst[20:16] == 0x0
8287 OPC_Decode, 189, 7, 118, // 1164: decode to EFSCTUIZ using decoder 118
8288 // 1164: }
8289 2, 12, // 1168: case 0x2: {
8290 OPC_CheckField, 26, 6, 4, // 1170: check Inst[31:26] == 0x4
8291 OPC_CheckField, 16, 5, 0, // 1174: check Inst[20:16] == 0x0
8292 OPC_Decode, 186, 7, 118, // 1178: decode to EFSCTSIZ using decoder 118
8293 // 1178: }
8294 4, 13, // 1182: case 0x4: {
8295 OPC_CheckField, 26, 6, 4, // 1184: check Inst[31:26] == 0x4
8296 OPC_CheckField, 21, 2, 0, // 1188: check Inst[22:21] == 0x0
8297 OPC_Decode, 196, 7, 155, 2, // 1192: decode to EFSTSTGT using decoder 283
8298 // 1192: }
8299 5, 13, // 1197: case 0x5: {
8300 OPC_CheckField, 26, 6, 4, // 1199: check Inst[31:26] == 0x4
8301 OPC_CheckField, 21, 2, 0, // 1203: check Inst[22:21] == 0x0
8302 OPC_Decode, 197, 7, 155, 2, // 1207: decode to EFSTSTLT using decoder 283
8303 // 1207: }
8304 6, 0, // 1212: case 0x6: {
8305 OPC_CheckField, 26, 6, 4, // 1214: check Inst[31:26] == 0x4
8306 OPC_CheckField, 21, 2, 0, // 1218: check Inst[22:21] == 0x0
8307 OPC_Decode, 195, 7, 155, 2, // 1222: decode to EFSTSTEQ using decoder 283
8308 // 1222: }
8309 // 1222: } // switch Inst[2:0]
8310 // 1222: }
8311 92, 100, // 1227: case 0x5c: {
8312 OPC_SwitchField, 0, 3, // 1229: switch Inst[2:0] {
8313 0, 9, // 1232: case 0x0: {
8314 OPC_CheckField, 26, 6, 4, // 1234: check Inst[31:26] == 0x4
8315 OPC_Decode, 147, 7, 149, 2, // 1238: decode to EFDADD using decoder 277
8316 // 1238: }
8317 1, 9, // 1243: case 0x1: {
8318 OPC_CheckField, 26, 6, 4, // 1245: check Inst[31:26] == 0x4
8319 OPC_Decode, 170, 7, 149, 2, // 1249: decode to EFDSUB using decoder 277
8320 // 1249: }
8321 2, 13, // 1254: case 0x2: {
8322 OPC_CheckField, 26, 6, 4, // 1256: check Inst[31:26] == 0x4
8323 OPC_CheckField, 16, 5, 0, // 1260: check Inst[20:16] == 0x0
8324 OPC_Decode, 154, 7, 159, 2, // 1264: decode to EFDCFUID using decoder 287
8325 // 1264: }
8326 3, 13, // 1269: case 0x3: {
8327 OPC_CheckField, 26, 6, 4, // 1271: check Inst[31:26] == 0x4
8328 OPC_CheckField, 16, 5, 0, // 1275: check Inst[20:16] == 0x0
8329 OPC_Decode, 151, 7, 159, 2, // 1279: decode to EFDCFSID using decoder 287
8330 // 1279: }
8331 4, 13, // 1284: case 0x4: {
8332 OPC_CheckField, 26, 6, 4, // 1286: check Inst[31:26] == 0x4
8333 OPC_CheckField, 11, 5, 0, // 1290: check Inst[15:11] == 0x0
8334 OPC_Decode, 146, 7, 152, 2, // 1294: decode to EFDABS using decoder 280
8335 // 1294: }
8336 5, 13, // 1299: case 0x5: {
8337 OPC_CheckField, 26, 6, 4, // 1301: check Inst[31:26] == 0x4
8338 OPC_CheckField, 11, 5, 0, // 1305: check Inst[15:11] == 0x0
8339 OPC_Decode, 168, 7, 152, 2, // 1309: decode to EFDNABS using decoder 280
8340 // 1309: }
8341 6, 0, // 1314: case 0x6: {
8342 OPC_CheckField, 26, 6, 4, // 1316: check Inst[31:26] == 0x4
8343 OPC_CheckField, 11, 5, 0, // 1320: check Inst[15:11] == 0x0
8344 OPC_Decode, 169, 7, 152, 2, // 1324: decode to EFDNEG using decoder 280
8345 // 1324: }
8346 // 1324: } // switch Inst[2:0]
8347 // 1324: }
8348 93, 115, // 1329: case 0x5d: {
8349 OPC_SwitchField, 0, 3, // 1331: switch Inst[2:0] {
8350 0, 9, // 1334: case 0x0: {
8351 OPC_CheckField, 26, 6, 4, // 1336: check Inst[31:26] == 0x4
8352 OPC_Decode, 167, 7, 149, 2, // 1340: decode to EFDMUL using decoder 277
8353 // 1340: }
8354 1, 9, // 1345: case 0x1: {
8355 OPC_CheckField, 26, 6, 4, // 1347: check Inst[31:26] == 0x4
8356 OPC_Decode, 166, 7, 149, 2, // 1351: decode to EFDDIV using decoder 277
8357 // 1351: }
8358 2, 13, // 1356: case 0x2: {
8359 OPC_CheckField, 26, 6, 4, // 1358: check Inst[31:26] == 0x4
8360 OPC_CheckField, 16, 5, 0, // 1362: check Inst[20:16] == 0x0
8361 OPC_Decode, 164, 7, 158, 2, // 1366: decode to EFDCTUIDZ using decoder 286
8362 // 1366: }
8363 3, 13, // 1371: case 0x3: {
8364 OPC_CheckField, 26, 6, 4, // 1373: check Inst[31:26] == 0x4
8365 OPC_CheckField, 16, 5, 0, // 1377: check Inst[20:16] == 0x0
8366 OPC_Decode, 160, 7, 158, 2, // 1381: decode to EFDCTSIDZ using decoder 286
8367 // 1381: }
8368 4, 13, // 1386: case 0x4: {
8369 OPC_CheckField, 26, 6, 4, // 1388: check Inst[31:26] == 0x4
8370 OPC_CheckField, 21, 2, 0, // 1392: check Inst[22:21] == 0x0
8371 OPC_Decode, 156, 7, 155, 2, // 1396: decode to EFDCMPGT using decoder 283
8372 // 1396: }
8373 5, 13, // 1401: case 0x5: {
8374 OPC_CheckField, 26, 6, 4, // 1403: check Inst[31:26] == 0x4
8375 OPC_CheckField, 21, 2, 0, // 1407: check Inst[22:21] == 0x0
8376 OPC_Decode, 157, 7, 155, 2, // 1411: decode to EFDCMPLT using decoder 283
8377 // 1411: }
8378 6, 13, // 1416: case 0x6: {
8379 OPC_CheckField, 26, 6, 4, // 1418: check Inst[31:26] == 0x4
8380 OPC_CheckField, 21, 2, 0, // 1422: check Inst[22:21] == 0x0
8381 OPC_Decode, 155, 7, 155, 2, // 1426: decode to EFDCMPEQ using decoder 283
8382 // 1426: }
8383 7, 0, // 1431: case 0x7: {
8384 OPC_CheckField, 26, 6, 4, // 1433: check Inst[31:26] == 0x4
8385 OPC_CheckField, 16, 5, 0, // 1437: check Inst[20:16] == 0x0
8386 OPC_Decode, 148, 7, 159, 2, // 1441: decode to EFDCFS using decoder 287
8387 // 1441: }
8388 // 1441: } // switch Inst[2:0]
8389 // 1441: }
8390 94, 123, // 1446: case 0x5e: {
8391 OPC_SwitchField, 0, 3, // 1448: switch Inst[2:0] {
8392 0, 13, // 1451: case 0x0: {
8393 OPC_CheckField, 26, 6, 4, // 1453: check Inst[31:26] == 0x4
8394 OPC_CheckField, 16, 5, 0, // 1457: check Inst[20:16] == 0x0
8395 OPC_Decode, 153, 7, 159, 2, // 1461: decode to EFDCFUI using decoder 287
8396 // 1461: }
8397 1, 13, // 1466: case 0x1: {
8398 OPC_CheckField, 26, 6, 4, // 1468: check Inst[31:26] == 0x4
8399 OPC_CheckField, 16, 5, 0, // 1472: check Inst[20:16] == 0x0
8400 OPC_Decode, 150, 7, 159, 2, // 1476: decode to EFDCFSI using decoder 287
8401 // 1476: }
8402 2, 13, // 1481: case 0x2: {
8403 OPC_CheckField, 26, 6, 4, // 1483: check Inst[31:26] == 0x4
8404 OPC_CheckField, 16, 5, 0, // 1487: check Inst[20:16] == 0x0
8405 OPC_Decode, 152, 7, 159, 2, // 1491: decode to EFDCFUF using decoder 287
8406 // 1491: }
8407 3, 13, // 1496: case 0x3: {
8408 OPC_CheckField, 26, 6, 4, // 1498: check Inst[31:26] == 0x4
8409 OPC_CheckField, 16, 5, 0, // 1502: check Inst[20:16] == 0x0
8410 OPC_Decode, 149, 7, 159, 2, // 1506: decode to EFDCFSF using decoder 287
8411 // 1506: }
8412 4, 13, // 1511: case 0x4: {
8413 OPC_CheckField, 26, 6, 4, // 1513: check Inst[31:26] == 0x4
8414 OPC_CheckField, 16, 5, 0, // 1517: check Inst[20:16] == 0x0
8415 OPC_Decode, 163, 7, 158, 2, // 1521: decode to EFDCTUI using decoder 286
8416 // 1521: }
8417 5, 13, // 1526: case 0x5: {
8418 OPC_CheckField, 26, 6, 4, // 1528: check Inst[31:26] == 0x4
8419 OPC_CheckField, 16, 5, 0, // 1532: check Inst[20:16] == 0x0
8420 OPC_Decode, 159, 7, 158, 2, // 1536: decode to EFDCTSI using decoder 286
8421 // 1536: }
8422 6, 13, // 1541: case 0x6: {
8423 OPC_CheckField, 26, 6, 4, // 1543: check Inst[31:26] == 0x4
8424 OPC_CheckField, 16, 5, 0, // 1547: check Inst[20:16] == 0x0
8425 OPC_Decode, 162, 7, 159, 2, // 1551: decode to EFDCTUF using decoder 287
8426 // 1551: }
8427 7, 0, // 1556: case 0x7: {
8428 OPC_CheckField, 26, 6, 4, // 1558: check Inst[31:26] == 0x4
8429 OPC_CheckField, 16, 5, 0, // 1562: check Inst[20:16] == 0x0
8430 OPC_Decode, 158, 7, 159, 2, // 1566: decode to EFDCTSF using decoder 287
8431 // 1566: }
8432 // 1566: } // switch Inst[2:0]
8433 // 1566: }
8434 95, 78, // 1571: case 0x5f: {
8435 OPC_SwitchField, 0, 3, // 1573: switch Inst[2:0] {
8436 0, 13, // 1576: case 0x0: {
8437 OPC_CheckField, 26, 6, 4, // 1578: check Inst[31:26] == 0x4
8438 OPC_CheckField, 16, 5, 0, // 1582: check Inst[20:16] == 0x0
8439 OPC_Decode, 165, 7, 158, 2, // 1586: decode to EFDCTUIZ using decoder 286
8440 // 1586: }
8441 2, 13, // 1591: case 0x2: {
8442 OPC_CheckField, 26, 6, 4, // 1593: check Inst[31:26] == 0x4
8443 OPC_CheckField, 16, 5, 0, // 1597: check Inst[20:16] == 0x0
8444 OPC_Decode, 161, 7, 158, 2, // 1601: decode to EFDCTSIZ using decoder 286
8445 // 1601: }
8446 4, 13, // 1606: case 0x4: {
8447 OPC_CheckField, 26, 6, 4, // 1608: check Inst[31:26] == 0x4
8448 OPC_CheckField, 21, 2, 0, // 1612: check Inst[22:21] == 0x0
8449 OPC_Decode, 172, 7, 155, 2, // 1616: decode to EFDTSTGT using decoder 283
8450 // 1616: }
8451 5, 13, // 1621: case 0x5: {
8452 OPC_CheckField, 26, 6, 4, // 1623: check Inst[31:26] == 0x4
8453 OPC_CheckField, 21, 2, 0, // 1627: check Inst[22:21] == 0x0
8454 OPC_Decode, 173, 7, 155, 2, // 1631: decode to EFDTSTLT using decoder 283
8455 // 1631: }
8456 6, 0, // 1636: case 0x6: {
8457 OPC_CheckField, 26, 6, 4, // 1638: check Inst[31:26] == 0x4
8458 OPC_CheckField, 21, 2, 0, // 1642: check Inst[22:21] == 0x0
8459 OPC_Decode, 171, 7, 155, 2, // 1646: decode to EFDTSTEQ using decoder 283
8460 // 1646: }
8461 // 1646: } // switch Inst[2:0]
8462 // 1646: }
8463 96, 69, // 1651: case 0x60: {
8464 OPC_SwitchField, 0, 3, // 1653: switch Inst[2:0] {
8465 0, 9, // 1656: case 0x0: {
8466 OPC_CheckField, 26, 6, 4, // 1658: check Inst[31:26] == 0x4
8467 OPC_Decode, 252, 7, 160, 2, // 1662: decode to EVLDDX using decoder 288
8468 // 1662: }
8469 1, 9, // 1667: case 0x1: {
8470 OPC_CheckField, 26, 6, 4, // 1669: check Inst[31:26] == 0x4
8471 OPC_Decode, 251, 7, 161, 2, // 1673: decode to EVLDD using decoder 289
8472 // 1673: }
8473 2, 9, // 1678: case 0x2: {
8474 OPC_CheckField, 26, 6, 4, // 1680: check Inst[31:26] == 0x4
8475 OPC_Decode, 128, 8, 160, 2, // 1684: decode to EVLDWX using decoder 288
8476 // 1684: }
8477 3, 9, // 1689: case 0x3: {
8478 OPC_CheckField, 26, 6, 4, // 1691: check Inst[31:26] == 0x4
8479 OPC_Decode, 255, 7, 161, 2, // 1695: decode to EVLDW using decoder 289
8480 // 1695: }
8481 4, 9, // 1700: case 0x4: {
8482 OPC_CheckField, 26, 6, 4, // 1702: check Inst[31:26] == 0x4
8483 OPC_Decode, 254, 7, 160, 2, // 1706: decode to EVLDHX using decoder 288
8484 // 1706: }
8485 5, 0, // 1711: case 0x5: {
8486 OPC_CheckField, 26, 6, 4, // 1713: check Inst[31:26] == 0x4
8487 OPC_Decode, 253, 7, 161, 2, // 1717: decode to EVLDH using decoder 289
8488 // 1717: }
8489 // 1717: } // switch Inst[2:0]
8490 // 1717: }
8491 97, 69, // 1722: case 0x61: {
8492 OPC_SwitchField, 0, 3, // 1724: switch Inst[2:0] {
8493 0, 9, // 1727: case 0x0: {
8494 OPC_CheckField, 26, 6, 4, // 1729: check Inst[31:26] == 0x4
8495 OPC_Decode, 130, 8, 160, 2, // 1733: decode to EVLHHESPLATX using decoder 288
8496 // 1733: }
8497 1, 9, // 1738: case 0x1: {
8498 OPC_CheckField, 26, 6, 4, // 1740: check Inst[31:26] == 0x4
8499 OPC_Decode, 129, 8, 162, 2, // 1744: decode to EVLHHESPLAT using decoder 290
8500 // 1744: }
8501 4, 9, // 1749: case 0x4: {
8502 OPC_CheckField, 26, 6, 4, // 1751: check Inst[31:26] == 0x4
8503 OPC_Decode, 134, 8, 160, 2, // 1755: decode to EVLHHOUSPLATX using decoder 288
8504 // 1755: }
8505 5, 9, // 1760: case 0x5: {
8506 OPC_CheckField, 26, 6, 4, // 1762: check Inst[31:26] == 0x4
8507 OPC_Decode, 133, 8, 162, 2, // 1766: decode to EVLHHOUSPLAT using decoder 290
8508 // 1766: }
8509 6, 9, // 1771: case 0x6: {
8510 OPC_CheckField, 26, 6, 4, // 1773: check Inst[31:26] == 0x4
8511 OPC_Decode, 132, 8, 160, 2, // 1777: decode to EVLHHOSSPLATX using decoder 288
8512 // 1777: }
8513 7, 0, // 1782: case 0x7: {
8514 OPC_CheckField, 26, 6, 4, // 1784: check Inst[31:26] == 0x4
8515 OPC_Decode, 131, 8, 162, 2, // 1788: decode to EVLHHOSSPLAT using decoder 290
8516 // 1788: }
8517 // 1788: } // switch Inst[2:0]
8518 // 1788: }
8519 98, 69, // 1793: case 0x62: {
8520 OPC_SwitchField, 0, 3, // 1795: switch Inst[2:0] {
8521 0, 9, // 1798: case 0x0: {
8522 OPC_CheckField, 26, 6, 4, // 1800: check Inst[31:26] == 0x4
8523 OPC_Decode, 136, 8, 160, 2, // 1804: decode to EVLWHEX using decoder 288
8524 // 1804: }
8525 1, 9, // 1809: case 0x1: {
8526 OPC_CheckField, 26, 6, 4, // 1811: check Inst[31:26] == 0x4
8527 OPC_Decode, 135, 8, 163, 2, // 1815: decode to EVLWHE using decoder 291
8528 // 1815: }
8529 4, 9, // 1820: case 0x4: {
8530 OPC_CheckField, 26, 6, 4, // 1822: check Inst[31:26] == 0x4
8531 OPC_Decode, 140, 8, 160, 2, // 1826: decode to EVLWHOUX using decoder 288
8532 // 1826: }
8533 5, 9, // 1831: case 0x5: {
8534 OPC_CheckField, 26, 6, 4, // 1833: check Inst[31:26] == 0x4
8535 OPC_Decode, 139, 8, 163, 2, // 1837: decode to EVLWHOU using decoder 291
8536 // 1837: }
8537 6, 9, // 1842: case 0x6: {
8538 OPC_CheckField, 26, 6, 4, // 1844: check Inst[31:26] == 0x4
8539 OPC_Decode, 138, 8, 160, 2, // 1848: decode to EVLWHOSX using decoder 288
8540 // 1848: }
8541 7, 0, // 1853: case 0x7: {
8542 OPC_CheckField, 26, 6, 4, // 1855: check Inst[31:26] == 0x4
8543 OPC_Decode, 137, 8, 163, 2, // 1859: decode to EVLWHOS using decoder 291
8544 // 1859: }
8545 // 1859: } // switch Inst[2:0]
8546 // 1859: }
8547 99, 47, // 1864: case 0x63: {
8548 OPC_SwitchField, 0, 3, // 1866: switch Inst[2:0] {
8549 0, 9, // 1869: case 0x0: {
8550 OPC_CheckField, 26, 6, 4, // 1871: check Inst[31:26] == 0x4
8551 OPC_Decode, 144, 8, 160, 2, // 1875: decode to EVLWWSPLATX using decoder 288
8552 // 1875: }
8553 1, 9, // 1880: case 0x1: {
8554 OPC_CheckField, 26, 6, 4, // 1882: check Inst[31:26] == 0x4
8555 OPC_Decode, 143, 8, 163, 2, // 1886: decode to EVLWWSPLAT using decoder 291
8556 // 1886: }
8557 4, 9, // 1891: case 0x4: {
8558 OPC_CheckField, 26, 6, 4, // 1893: check Inst[31:26] == 0x4
8559 OPC_Decode, 142, 8, 160, 2, // 1897: decode to EVLWHSPLATX using decoder 288
8560 // 1897: }
8561 5, 0, // 1902: case 0x5: {
8562 OPC_CheckField, 26, 6, 4, // 1904: check Inst[31:26] == 0x4
8563 OPC_Decode, 141, 8, 163, 2, // 1908: decode to EVLWHSPLAT using decoder 291
8564 // 1908: }
8565 // 1908: } // switch Inst[2:0]
8566 // 1908: }
8567 100, 69, // 1913: case 0x64: {
8568 OPC_SwitchField, 0, 3, // 1915: switch Inst[2:0] {
8569 0, 9, // 1918: case 0x0: {
8570 OPC_CheckField, 26, 6, 4, // 1920: check Inst[31:26] == 0x4
8571 OPC_Decode, 254, 8, 160, 2, // 1924: decode to EVSTDDX using decoder 288
8572 // 1924: }
8573 1, 9, // 1929: case 0x1: {
8574 OPC_CheckField, 26, 6, 4, // 1931: check Inst[31:26] == 0x4
8575 OPC_Decode, 253, 8, 161, 2, // 1935: decode to EVSTDD using decoder 289
8576 // 1935: }
8577 2, 9, // 1940: case 0x2: {
8578 OPC_CheckField, 26, 6, 4, // 1942: check Inst[31:26] == 0x4
8579 OPC_Decode, 130, 9, 160, 2, // 1946: decode to EVSTDWX using decoder 288
8580 // 1946: }
8581 3, 9, // 1951: case 0x3: {
8582 OPC_CheckField, 26, 6, 4, // 1953: check Inst[31:26] == 0x4
8583 OPC_Decode, 129, 9, 161, 2, // 1957: decode to EVSTDW using decoder 289
8584 // 1957: }
8585 4, 9, // 1962: case 0x4: {
8586 OPC_CheckField, 26, 6, 4, // 1964: check Inst[31:26] == 0x4
8587 OPC_Decode, 128, 9, 160, 2, // 1968: decode to EVSTDHX using decoder 288
8588 // 1968: }
8589 5, 0, // 1973: case 0x5: {
8590 OPC_CheckField, 26, 6, 4, // 1975: check Inst[31:26] == 0x4
8591 OPC_Decode, 255, 8, 161, 2, // 1979: decode to EVSTDH using decoder 289
8592 // 1979: }
8593 // 1979: } // switch Inst[2:0]
8594 // 1979: }
8595 102, 47, // 1984: case 0x66: {
8596 OPC_SwitchField, 0, 3, // 1986: switch Inst[2:0] {
8597 0, 9, // 1989: case 0x0: {
8598 OPC_CheckField, 26, 6, 4, // 1991: check Inst[31:26] == 0x4
8599 OPC_Decode, 132, 9, 160, 2, // 1995: decode to EVSTWHEX using decoder 288
8600 // 1995: }
8601 1, 9, // 2000: case 0x1: {
8602 OPC_CheckField, 26, 6, 4, // 2002: check Inst[31:26] == 0x4
8603 OPC_Decode, 131, 9, 163, 2, // 2006: decode to EVSTWHE using decoder 291
8604 // 2006: }
8605 4, 9, // 2011: case 0x4: {
8606 OPC_CheckField, 26, 6, 4, // 2013: check Inst[31:26] == 0x4
8607 OPC_Decode, 134, 9, 160, 2, // 2017: decode to EVSTWHOX using decoder 288
8608 // 2017: }
8609 5, 0, // 2022: case 0x5: {
8610 OPC_CheckField, 26, 6, 4, // 2024: check Inst[31:26] == 0x4
8611 OPC_Decode, 133, 9, 163, 2, // 2028: decode to EVSTWHO using decoder 291
8612 // 2028: }
8613 // 2028: } // switch Inst[2:0]
8614 // 2028: }
8615 103, 47, // 2033: case 0x67: {
8616 OPC_SwitchField, 0, 3, // 2035: switch Inst[2:0] {
8617 0, 9, // 2038: case 0x0: {
8618 OPC_CheckField, 26, 6, 4, // 2040: check Inst[31:26] == 0x4
8619 OPC_Decode, 136, 9, 160, 2, // 2044: decode to EVSTWWEX using decoder 288
8620 // 2044: }
8621 1, 9, // 2049: case 0x1: {
8622 OPC_CheckField, 26, 6, 4, // 2051: check Inst[31:26] == 0x4
8623 OPC_Decode, 135, 9, 163, 2, // 2055: decode to EVSTWWE using decoder 291
8624 // 2055: }
8625 4, 9, // 2060: case 0x4: {
8626 OPC_CheckField, 26, 6, 4, // 2062: check Inst[31:26] == 0x4
8627 OPC_Decode, 138, 9, 160, 2, // 2066: decode to EVSTWWOX using decoder 288
8628 // 2066: }
8629 5, 0, // 2071: case 0x5: {
8630 OPC_CheckField, 26, 6, 4, // 2073: check Inst[31:26] == 0x4
8631 OPC_Decode, 137, 9, 163, 2, // 2077: decode to EVSTWWO using decoder 291
8632 // 2077: }
8633 // 2077: } // switch Inst[2:0]
8634 // 2077: }
8635 128, 1, 25, // 2082: case 0x80: {
8636 OPC_SwitchField, 0, 3, // 2085: switch Inst[2:0] {
8637 3, 9, // 2088: case 0x3: {
8638 OPC_CheckField, 26, 6, 4, // 2090: check Inst[31:26] == 0x4
8639 OPC_Decode, 163, 8, 149, 2, // 2094: decode to EVMHESSF using decoder 277
8640 // 2094: }
8641 7, 0, // 2099: case 0x7: {
8642 OPC_CheckField, 26, 6, 4, // 2101: check Inst[31:26] == 0x4
8643 OPC_Decode, 189, 8, 149, 2, // 2105: decode to EVMHOSSF using decoder 277
8644 // 2105: }
8645 // 2105: } // switch Inst[2:0]
8646 // 2105: }
8647 129, 1, 69, // 2110: case 0x81: {
8648 OPC_SwitchField, 0, 3, // 2113: switch Inst[2:0] {
8649 0, 9, // 2116: case 0x0: {
8650 OPC_CheckField, 26, 6, 4, // 2118: check Inst[31:26] == 0x4
8651 OPC_Decode, 169, 8, 149, 2, // 2122: decode to EVMHEUMI using decoder 277
8652 // 2122: }
8653 1, 9, // 2127: case 0x1: {
8654 OPC_CheckField, 26, 6, 4, // 2129: check Inst[31:26] == 0x4
8655 OPC_Decode, 159, 8, 149, 2, // 2133: decode to EVMHESMI using decoder 277
8656 // 2133: }
8657 3, 9, // 2138: case 0x3: {
8658 OPC_CheckField, 26, 6, 4, // 2140: check Inst[31:26] == 0x4
8659 OPC_Decode, 155, 8, 149, 2, // 2144: decode to EVMHESMF using decoder 277
8660 // 2144: }
8661 4, 9, // 2149: case 0x4: {
8662 OPC_CheckField, 26, 6, 4, // 2151: check Inst[31:26] == 0x4
8663 OPC_Decode, 195, 8, 149, 2, // 2155: decode to EVMHOUMI using decoder 277
8664 // 2155: }
8665 5, 9, // 2160: case 0x5: {
8666 OPC_CheckField, 26, 6, 4, // 2162: check Inst[31:26] == 0x4
8667 OPC_Decode, 185, 8, 149, 2, // 2166: decode to EVMHOSMI using decoder 277
8668 // 2166: }
8669 7, 0, // 2171: case 0x7: {
8670 OPC_CheckField, 26, 6, 4, // 2173: check Inst[31:26] == 0x4
8671 OPC_Decode, 181, 8, 149, 2, // 2177: decode to EVMHOSMF using decoder 277
8672 // 2177: }
8673 // 2177: } // switch Inst[2:0]
8674 // 2177: }
8675 132, 1, 25, // 2182: case 0x84: {
8676 OPC_SwitchField, 0, 3, // 2185: switch Inst[2:0] {
8677 3, 9, // 2188: case 0x3: {
8678 OPC_CheckField, 26, 6, 4, // 2190: check Inst[31:26] == 0x4
8679 OPC_Decode, 164, 8, 149, 2, // 2194: decode to EVMHESSFA using decoder 277
8680 // 2194: }
8681 7, 0, // 2199: case 0x7: {
8682 OPC_CheckField, 26, 6, 4, // 2201: check Inst[31:26] == 0x4
8683 OPC_Decode, 190, 8, 149, 2, // 2205: decode to EVMHOSSFA using decoder 277
8684 // 2205: }
8685 // 2205: } // switch Inst[2:0]
8686 // 2205: }
8687 133, 1, 69, // 2210: case 0x85: {
8688 OPC_SwitchField, 0, 3, // 2213: switch Inst[2:0] {
8689 0, 9, // 2216: case 0x0: {
8690 OPC_CheckField, 26, 6, 4, // 2218: check Inst[31:26] == 0x4
8691 OPC_Decode, 170, 8, 149, 2, // 2222: decode to EVMHEUMIA using decoder 277
8692 // 2222: }
8693 1, 9, // 2227: case 0x1: {
8694 OPC_CheckField, 26, 6, 4, // 2229: check Inst[31:26] == 0x4
8695 OPC_Decode, 160, 8, 149, 2, // 2233: decode to EVMHESMIA using decoder 277
8696 // 2233: }
8697 3, 9, // 2238: case 0x3: {
8698 OPC_CheckField, 26, 6, 4, // 2240: check Inst[31:26] == 0x4
8699 OPC_Decode, 156, 8, 149, 2, // 2244: decode to EVMHESMFA using decoder 277
8700 // 2244: }
8701 4, 9, // 2249: case 0x4: {
8702 OPC_CheckField, 26, 6, 4, // 2251: check Inst[31:26] == 0x4
8703 OPC_Decode, 196, 8, 149, 2, // 2255: decode to EVMHOUMIA using decoder 277
8704 // 2255: }
8705 5, 9, // 2260: case 0x5: {
8706 OPC_CheckField, 26, 6, 4, // 2262: check Inst[31:26] == 0x4
8707 OPC_Decode, 186, 8, 149, 2, // 2266: decode to EVMHOSMIA using decoder 277
8708 // 2266: }
8709 7, 0, // 2271: case 0x7: {
8710 OPC_CheckField, 26, 6, 4, // 2273: check Inst[31:26] == 0x4
8711 OPC_Decode, 182, 8, 149, 2, // 2277: decode to EVMHOSMFA using decoder 277
8712 // 2277: }
8713 // 2277: } // switch Inst[2:0]
8714 // 2277: }
8715 136, 1, 13, // 2282: case 0x88: {
8716 OPC_CheckField, 26, 6, 4, // 2285: check Inst[31:26] == 0x4
8717 OPC_CheckField, 0, 3, 7, // 2289: check Inst[2:0] == 0x7
8718 OPC_Decode, 206, 8, 149, 2, // 2293: decode to EVMWHSSF using decoder 277
8719 // 2293: }
8720 137, 1, 47, // 2298: case 0x89: {
8721 OPC_SwitchField, 0, 3, // 2301: switch Inst[2:0] {
8722 0, 9, // 2304: case 0x0: {
8723 OPC_CheckField, 26, 6, 4, // 2306: check Inst[31:26] == 0x4
8724 OPC_Decode, 214, 8, 149, 2, // 2310: decode to EVMWLUMI using decoder 277
8725 // 2310: }
8726 4, 9, // 2315: case 0x4: {
8727 OPC_CheckField, 26, 6, 4, // 2317: check Inst[31:26] == 0x4
8728 OPC_Decode, 208, 8, 149, 2, // 2321: decode to EVMWHUMI using decoder 277
8729 // 2321: }
8730 5, 9, // 2326: case 0x5: {
8731 OPC_CheckField, 26, 6, 4, // 2328: check Inst[31:26] == 0x4
8732 OPC_Decode, 204, 8, 149, 2, // 2332: decode to EVMWHSMI using decoder 277
8733 // 2332: }
8734 7, 0, // 2337: case 0x7: {
8735 OPC_CheckField, 26, 6, 4, // 2339: check Inst[31:26] == 0x4
8736 OPC_Decode, 202, 8, 149, 2, // 2343: decode to EVMWHSMF using decoder 277
8737 // 2343: }
8738 // 2343: } // switch Inst[2:0]
8739 // 2343: }
8740 138, 1, 13, // 2348: case 0x8a: {
8741 OPC_CheckField, 26, 6, 4, // 2351: check Inst[31:26] == 0x4
8742 OPC_CheckField, 0, 3, 3, // 2355: check Inst[2:0] == 0x3
8743 OPC_Decode, 228, 8, 149, 2, // 2359: decode to EVMWSSF using decoder 277
8744 // 2359: }
8745 139, 1, 36, // 2364: case 0x8b: {
8746 OPC_SwitchField, 0, 3, // 2367: switch Inst[2:0] {
8747 0, 9, // 2370: case 0x0: {
8748 OPC_CheckField, 26, 6, 4, // 2372: check Inst[31:26] == 0x4
8749 OPC_Decode, 232, 8, 149, 2, // 2376: decode to EVMWUMI using decoder 277
8750 // 2376: }
8751 1, 9, // 2381: case 0x1: {
8752 OPC_CheckField, 26, 6, 4, // 2383: check Inst[31:26] == 0x4
8753 OPC_Decode, 224, 8, 149, 2, // 2387: decode to EVMWSMI using decoder 277
8754 // 2387: }
8755 3, 0, // 2392: case 0x3: {
8756 OPC_CheckField, 26, 6, 4, // 2394: check Inst[31:26] == 0x4
8757 OPC_Decode, 220, 8, 149, 2, // 2398: decode to EVMWSMF using decoder 277
8758 // 2398: }
8759 // 2398: } // switch Inst[2:0]
8760 // 2398: }
8761 140, 1, 13, // 2403: case 0x8c: {
8762 OPC_CheckField, 26, 6, 4, // 2406: check Inst[31:26] == 0x4
8763 OPC_CheckField, 0, 3, 7, // 2410: check Inst[2:0] == 0x7
8764 OPC_Decode, 207, 8, 149, 2, // 2414: decode to EVMWHSSFA using decoder 277
8765 // 2414: }
8766 141, 1, 47, // 2419: case 0x8d: {
8767 OPC_SwitchField, 0, 3, // 2422: switch Inst[2:0] {
8768 0, 9, // 2425: case 0x0: {
8769 OPC_CheckField, 26, 6, 4, // 2427: check Inst[31:26] == 0x4
8770 OPC_Decode, 215, 8, 149, 2, // 2431: decode to EVMWLUMIA using decoder 277
8771 // 2431: }
8772 4, 9, // 2436: case 0x4: {
8773 OPC_CheckField, 26, 6, 4, // 2438: check Inst[31:26] == 0x4
8774 OPC_Decode, 209, 8, 149, 2, // 2442: decode to EVMWHUMIA using decoder 277
8775 // 2442: }
8776 5, 9, // 2447: case 0x5: {
8777 OPC_CheckField, 26, 6, 4, // 2449: check Inst[31:26] == 0x4
8778 OPC_Decode, 205, 8, 149, 2, // 2453: decode to EVMWHSMIA using decoder 277
8779 // 2453: }
8780 7, 0, // 2458: case 0x7: {
8781 OPC_CheckField, 26, 6, 4, // 2460: check Inst[31:26] == 0x4
8782 OPC_Decode, 203, 8, 149, 2, // 2464: decode to EVMWHSMFA using decoder 277
8783 // 2464: }
8784 // 2464: } // switch Inst[2:0]
8785 // 2464: }
8786 142, 1, 13, // 2469: case 0x8e: {
8787 OPC_CheckField, 26, 6, 4, // 2472: check Inst[31:26] == 0x4
8788 OPC_CheckField, 0, 3, 3, // 2476: check Inst[2:0] == 0x3
8789 OPC_Decode, 229, 8, 149, 2, // 2480: decode to EVMWSSFA using decoder 277
8790 // 2480: }
8791 143, 1, 36, // 2485: case 0x8f: {
8792 OPC_SwitchField, 0, 3, // 2488: switch Inst[2:0] {
8793 0, 9, // 2491: case 0x0: {
8794 OPC_CheckField, 26, 6, 4, // 2493: check Inst[31:26] == 0x4
8795 OPC_Decode, 233, 8, 149, 2, // 2497: decode to EVMWUMIA using decoder 277
8796 // 2497: }
8797 1, 9, // 2502: case 0x1: {
8798 OPC_CheckField, 26, 6, 4, // 2504: check Inst[31:26] == 0x4
8799 OPC_Decode, 225, 8, 149, 2, // 2508: decode to EVMWSMIA using decoder 277
8800 // 2508: }
8801 3, 0, // 2513: case 0x3: {
8802 OPC_CheckField, 26, 6, 4, // 2515: check Inst[31:26] == 0x4
8803 OPC_Decode, 221, 8, 149, 2, // 2519: decode to EVMWSMFA using decoder 277
8804 // 2519: }
8805 // 2519: } // switch Inst[2:0]
8806 // 2519: }
8807 152, 1, 100, // 2524: case 0x98: {
8808 OPC_SwitchField, 0, 3, // 2527: switch Inst[2:0] {
8809 0, 13, // 2530: case 0x0: {
8810 OPC_CheckField, 26, 6, 4, // 2532: check Inst[31:26] == 0x4
8811 OPC_CheckField, 11, 5, 0, // 2536: check Inst[15:11] == 0x0
8812 OPC_Decode, 212, 7, 152, 2, // 2540: decode to EVADDUSIAAW using decoder 280
8813 // 2540: }
8814 1, 13, // 2545: case 0x1: {
8815 OPC_CheckField, 26, 6, 4, // 2547: check Inst[31:26] == 0x4
8816 OPC_CheckField, 11, 5, 0, // 2551: check Inst[15:11] == 0x0
8817 OPC_Decode, 210, 7, 152, 2, // 2555: decode to EVADDSSIAAW using decoder 280
8818 // 2555: }
8819 2, 13, // 2560: case 0x2: {
8820 OPC_CheckField, 26, 6, 4, // 2562: check Inst[31:26] == 0x4
8821 OPC_CheckField, 11, 5, 0, // 2566: check Inst[15:11] == 0x0
8822 OPC_Decode, 142, 9, 152, 2, // 2570: decode to EVSUBFUSIAAW using decoder 280
8823 // 2570: }
8824 3, 13, // 2575: case 0x3: {
8825 OPC_CheckField, 26, 6, 4, // 2577: check Inst[31:26] == 0x4
8826 OPC_CheckField, 11, 5, 0, // 2581: check Inst[15:11] == 0x0
8827 OPC_Decode, 140, 9, 152, 2, // 2585: decode to EVSUBFSSIAAW using decoder 280
8828 // 2585: }
8829 4, 13, // 2590: case 0x4: {
8830 OPC_CheckField, 26, 6, 4, // 2592: check Inst[31:26] == 0x4
8831 OPC_CheckField, 11, 5, 0, // 2596: check Inst[15:11] == 0x0
8832 OPC_Decode, 201, 8, 152, 2, // 2600: decode to EVMRA using decoder 280
8833 // 2600: }
8834 6, 9, // 2605: case 0x6: {
8835 OPC_CheckField, 26, 6, 4, // 2607: check Inst[31:26] == 0x4
8836 OPC_Decode, 223, 7, 149, 2, // 2611: decode to EVDIVWS using decoder 277
8837 // 2611: }
8838 7, 0, // 2616: case 0x7: {
8839 OPC_CheckField, 26, 6, 4, // 2618: check Inst[31:26] == 0x4
8840 OPC_Decode, 224, 7, 149, 2, // 2622: decode to EVDIVWU using decoder 277
8841 // 2622: }
8842 // 2622: } // switch Inst[2:0]
8843 // 2622: }
8844 153, 1, 63, // 2627: case 0x99: {
8845 OPC_SwitchField, 0, 3, // 2630: switch Inst[2:0] {
8846 0, 13, // 2633: case 0x0: {
8847 OPC_CheckField, 26, 6, 4, // 2635: check Inst[31:26] == 0x4
8848 OPC_CheckField, 11, 5, 0, // 2639: check Inst[15:11] == 0x0
8849 OPC_Decode, 211, 7, 152, 2, // 2643: decode to EVADDUMIAAW using decoder 280
8850 // 2643: }
8851 1, 13, // 2648: case 0x1: {
8852 OPC_CheckField, 26, 6, 4, // 2650: check Inst[31:26] == 0x4
8853 OPC_CheckField, 11, 5, 0, // 2654: check Inst[15:11] == 0x0
8854 OPC_Decode, 209, 7, 152, 2, // 2658: decode to EVADDSMIAAW using decoder 280
8855 // 2658: }
8856 2, 13, // 2663: case 0x2: {
8857 OPC_CheckField, 26, 6, 4, // 2665: check Inst[31:26] == 0x4
8858 OPC_CheckField, 11, 5, 0, // 2669: check Inst[15:11] == 0x0
8859 OPC_Decode, 141, 9, 152, 2, // 2673: decode to EVSUBFUMIAAW using decoder 280
8860 // 2673: }
8861 3, 0, // 2678: case 0x3: {
8862 OPC_CheckField, 26, 6, 4, // 2680: check Inst[31:26] == 0x4
8863 OPC_CheckField, 11, 5, 0, // 2684: check Inst[15:11] == 0x0
8864 OPC_Decode, 139, 9, 152, 2, // 2688: decode to EVSUBFSMIAAW using decoder 280
8865 // 2688: }
8866 // 2688: } // switch Inst[2:0]
8867 // 2688: }
8868 160, 1, 69, // 2693: case 0xa0: {
8869 OPC_SwitchField, 0, 3, // 2696: switch Inst[2:0] {
8870 0, 9, // 2699: case 0x0: {
8871 OPC_CheckField, 26, 6, 4, // 2701: check Inst[31:26] == 0x4
8872 OPC_Decode, 173, 8, 149, 2, // 2705: decode to EVMHEUSIAAW using decoder 277
8873 // 2705: }
8874 1, 9, // 2710: case 0x1: {
8875 OPC_CheckField, 26, 6, 4, // 2712: check Inst[31:26] == 0x4
8876 OPC_Decode, 167, 8, 149, 2, // 2716: decode to EVMHESSIAAW using decoder 277
8877 // 2716: }
8878 3, 9, // 2721: case 0x3: {
8879 OPC_CheckField, 26, 6, 4, // 2723: check Inst[31:26] == 0x4
8880 OPC_Decode, 165, 8, 149, 2, // 2727: decode to EVMHESSFAAW using decoder 277
8881 // 2727: }
8882 4, 9, // 2732: case 0x4: {
8883 OPC_CheckField, 26, 6, 4, // 2734: check Inst[31:26] == 0x4
8884 OPC_Decode, 199, 8, 149, 2, // 2738: decode to EVMHOUSIAAW using decoder 277
8885 // 2738: }
8886 5, 9, // 2743: case 0x5: {
8887 OPC_CheckField, 26, 6, 4, // 2745: check Inst[31:26] == 0x4
8888 OPC_Decode, 193, 8, 149, 2, // 2749: decode to EVMHOSSIAAW using decoder 277
8889 // 2749: }
8890 7, 0, // 2754: case 0x7: {
8891 OPC_CheckField, 26, 6, 4, // 2756: check Inst[31:26] == 0x4
8892 OPC_Decode, 191, 8, 149, 2, // 2760: decode to EVMHOSSFAAW using decoder 277
8893 // 2760: }
8894 // 2760: } // switch Inst[2:0]
8895 // 2760: }
8896 161, 1, 69, // 2765: case 0xa1: {
8897 OPC_SwitchField, 0, 3, // 2768: switch Inst[2:0] {
8898 0, 9, // 2771: case 0x0: {
8899 OPC_CheckField, 26, 6, 4, // 2773: check Inst[31:26] == 0x4
8900 OPC_Decode, 171, 8, 149, 2, // 2777: decode to EVMHEUMIAAW using decoder 277
8901 // 2777: }
8902 1, 9, // 2782: case 0x1: {
8903 OPC_CheckField, 26, 6, 4, // 2784: check Inst[31:26] == 0x4
8904 OPC_Decode, 161, 8, 149, 2, // 2788: decode to EVMHESMIAAW using decoder 277
8905 // 2788: }
8906 3, 9, // 2793: case 0x3: {
8907 OPC_CheckField, 26, 6, 4, // 2795: check Inst[31:26] == 0x4
8908 OPC_Decode, 157, 8, 149, 2, // 2799: decode to EVMHESMFAAW using decoder 277
8909 // 2799: }
8910 4, 9, // 2804: case 0x4: {
8911 OPC_CheckField, 26, 6, 4, // 2806: check Inst[31:26] == 0x4
8912 OPC_Decode, 197, 8, 149, 2, // 2810: decode to EVMHOUMIAAW using decoder 277
8913 // 2810: }
8914 5, 9, // 2815: case 0x5: {
8915 OPC_CheckField, 26, 6, 4, // 2817: check Inst[31:26] == 0x4
8916 OPC_Decode, 187, 8, 149, 2, // 2821: decode to EVMHOSMIAAW using decoder 277
8917 // 2821: }
8918 7, 0, // 2826: case 0x7: {
8919 OPC_CheckField, 26, 6, 4, // 2828: check Inst[31:26] == 0x4
8920 OPC_Decode, 183, 8, 149, 2, // 2832: decode to EVMHOSMFAAW using decoder 277
8921 // 2832: }
8922 // 2832: } // switch Inst[2:0]
8923 // 2832: }
8924 165, 1, 69, // 2837: case 0xa5: {
8925 OPC_SwitchField, 0, 3, // 2840: switch Inst[2:0] {
8926 0, 9, // 2843: case 0x0: {
8927 OPC_CheckField, 26, 6, 4, // 2845: check Inst[31:26] == 0x4
8928 OPC_Decode, 153, 8, 149, 2, // 2849: decode to EVMHEGUMIAA using decoder 277
8929 // 2849: }
8930 1, 9, // 2854: case 0x1: {
8931 OPC_CheckField, 26, 6, 4, // 2856: check Inst[31:26] == 0x4
8932 OPC_Decode, 151, 8, 149, 2, // 2860: decode to EVMHEGSMIAA using decoder 277
8933 // 2860: }
8934 3, 9, // 2865: case 0x3: {
8935 OPC_CheckField, 26, 6, 4, // 2867: check Inst[31:26] == 0x4
8936 OPC_Decode, 149, 8, 149, 2, // 2871: decode to EVMHEGSMFAA using decoder 277
8937 // 2871: }
8938 4, 9, // 2876: case 0x4: {
8939 OPC_CheckField, 26, 6, 4, // 2878: check Inst[31:26] == 0x4
8940 OPC_Decode, 179, 8, 149, 2, // 2882: decode to EVMHOGUMIAA using decoder 277
8941 // 2882: }
8942 5, 9, // 2887: case 0x5: {
8943 OPC_CheckField, 26, 6, 4, // 2889: check Inst[31:26] == 0x4
8944 OPC_Decode, 177, 8, 149, 2, // 2893: decode to EVMHOGSMIAA using decoder 277
8945 // 2893: }
8946 7, 0, // 2898: case 0x7: {
8947 OPC_CheckField, 26, 6, 4, // 2900: check Inst[31:26] == 0x4
8948 OPC_Decode, 175, 8, 149, 2, // 2904: decode to EVMHOGSMFAA using decoder 277
8949 // 2904: }
8950 // 2904: } // switch Inst[2:0]
8951 // 2904: }
8952 168, 1, 25, // 2909: case 0xa8: {
8953 OPC_SwitchField, 0, 3, // 2912: switch Inst[2:0] {
8954 0, 9, // 2915: case 0x0: {
8955 OPC_CheckField, 26, 6, 4, // 2917: check Inst[31:26] == 0x4
8956 OPC_Decode, 218, 8, 149, 2, // 2921: decode to EVMWLUSIAAW using decoder 277
8957 // 2921: }
8958 1, 0, // 2926: case 0x1: {
8959 OPC_CheckField, 26, 6, 4, // 2928: check Inst[31:26] == 0x4
8960 OPC_Decode, 212, 8, 149, 2, // 2932: decode to EVMWLSSIAAW using decoder 277
8961 // 2932: }
8962 // 2932: } // switch Inst[2:0]
8963 // 2932: }
8964 169, 1, 25, // 2937: case 0xa9: {
8965 OPC_SwitchField, 0, 3, // 2940: switch Inst[2:0] {
8966 0, 9, // 2943: case 0x0: {
8967 OPC_CheckField, 26, 6, 4, // 2945: check Inst[31:26] == 0x4
8968 OPC_Decode, 216, 8, 149, 2, // 2949: decode to EVMWLUMIAAW using decoder 277
8969 // 2949: }
8970 1, 0, // 2954: case 0x1: {
8971 OPC_CheckField, 26, 6, 4, // 2956: check Inst[31:26] == 0x4
8972 OPC_Decode, 210, 8, 149, 2, // 2960: decode to EVMWLSMIAAW using decoder 277
8973 // 2960: }
8974 // 2960: } // switch Inst[2:0]
8975 // 2960: }
8976 170, 1, 13, // 2965: case 0xaa: {
8977 OPC_CheckField, 26, 6, 4, // 2968: check Inst[31:26] == 0x4
8978 OPC_CheckField, 0, 3, 3, // 2972: check Inst[2:0] == 0x3
8979 OPC_Decode, 230, 8, 149, 2, // 2976: decode to EVMWSSFAA using decoder 277
8980 // 2976: }
8981 171, 1, 36, // 2981: case 0xab: {
8982 OPC_SwitchField, 0, 3, // 2984: switch Inst[2:0] {
8983 0, 9, // 2987: case 0x0: {
8984 OPC_CheckField, 26, 6, 4, // 2989: check Inst[31:26] == 0x4
8985 OPC_Decode, 234, 8, 149, 2, // 2993: decode to EVMWUMIAA using decoder 277
8986 // 2993: }
8987 1, 9, // 2998: case 0x1: {
8988 OPC_CheckField, 26, 6, 4, // 3000: check Inst[31:26] == 0x4
8989 OPC_Decode, 226, 8, 149, 2, // 3004: decode to EVMWSMIAA using decoder 277
8990 // 3004: }
8991 3, 0, // 3009: case 0x3: {
8992 OPC_CheckField, 26, 6, 4, // 3011: check Inst[31:26] == 0x4
8993 OPC_Decode, 222, 8, 149, 2, // 3015: decode to EVMWSMFAA using decoder 277
8994 // 3015: }
8995 // 3015: } // switch Inst[2:0]
8996 // 3015: }
8997 176, 1, 69, // 3020: case 0xb0: {
8998 OPC_SwitchField, 0, 3, // 3023: switch Inst[2:0] {
8999 0, 9, // 3026: case 0x0: {
9000 OPC_CheckField, 26, 6, 4, // 3028: check Inst[31:26] == 0x4
9001 OPC_Decode, 174, 8, 149, 2, // 3032: decode to EVMHEUSIANW using decoder 277
9002 // 3032: }
9003 1, 9, // 3037: case 0x1: {
9004 OPC_CheckField, 26, 6, 4, // 3039: check Inst[31:26] == 0x4
9005 OPC_Decode, 168, 8, 149, 2, // 3043: decode to EVMHESSIANW using decoder 277
9006 // 3043: }
9007 3, 9, // 3048: case 0x3: {
9008 OPC_CheckField, 26, 6, 4, // 3050: check Inst[31:26] == 0x4
9009 OPC_Decode, 166, 8, 149, 2, // 3054: decode to EVMHESSFANW using decoder 277
9010 // 3054: }
9011 4, 9, // 3059: case 0x4: {
9012 OPC_CheckField, 26, 6, 4, // 3061: check Inst[31:26] == 0x4
9013 OPC_Decode, 200, 8, 149, 2, // 3065: decode to EVMHOUSIANW using decoder 277
9014 // 3065: }
9015 5, 9, // 3070: case 0x5: {
9016 OPC_CheckField, 26, 6, 4, // 3072: check Inst[31:26] == 0x4
9017 OPC_Decode, 194, 8, 149, 2, // 3076: decode to EVMHOSSIANW using decoder 277
9018 // 3076: }
9019 7, 0, // 3081: case 0x7: {
9020 OPC_CheckField, 26, 6, 4, // 3083: check Inst[31:26] == 0x4
9021 OPC_Decode, 192, 8, 149, 2, // 3087: decode to EVMHOSSFANW using decoder 277
9022 // 3087: }
9023 // 3087: } // switch Inst[2:0]
9024 // 3087: }
9025 177, 1, 69, // 3092: case 0xb1: {
9026 OPC_SwitchField, 0, 3, // 3095: switch Inst[2:0] {
9027 0, 9, // 3098: case 0x0: {
9028 OPC_CheckField, 26, 6, 4, // 3100: check Inst[31:26] == 0x4
9029 OPC_Decode, 172, 8, 149, 2, // 3104: decode to EVMHEUMIANW using decoder 277
9030 // 3104: }
9031 1, 9, // 3109: case 0x1: {
9032 OPC_CheckField, 26, 6, 4, // 3111: check Inst[31:26] == 0x4
9033 OPC_Decode, 162, 8, 149, 2, // 3115: decode to EVMHESMIANW using decoder 277
9034 // 3115: }
9035 3, 9, // 3120: case 0x3: {
9036 OPC_CheckField, 26, 6, 4, // 3122: check Inst[31:26] == 0x4
9037 OPC_Decode, 158, 8, 149, 2, // 3126: decode to EVMHESMFANW using decoder 277
9038 // 3126: }
9039 4, 9, // 3131: case 0x4: {
9040 OPC_CheckField, 26, 6, 4, // 3133: check Inst[31:26] == 0x4
9041 OPC_Decode, 198, 8, 149, 2, // 3137: decode to EVMHOUMIANW using decoder 277
9042 // 3137: }
9043 5, 9, // 3142: case 0x5: {
9044 OPC_CheckField, 26, 6, 4, // 3144: check Inst[31:26] == 0x4
9045 OPC_Decode, 188, 8, 149, 2, // 3148: decode to EVMHOSMIANW using decoder 277
9046 // 3148: }
9047 7, 0, // 3153: case 0x7: {
9048 OPC_CheckField, 26, 6, 4, // 3155: check Inst[31:26] == 0x4
9049 OPC_Decode, 184, 8, 149, 2, // 3159: decode to EVMHOSMFANW using decoder 277
9050 // 3159: }
9051 // 3159: } // switch Inst[2:0]
9052 // 3159: }
9053 181, 1, 69, // 3164: case 0xb5: {
9054 OPC_SwitchField, 0, 3, // 3167: switch Inst[2:0] {
9055 0, 9, // 3170: case 0x0: {
9056 OPC_CheckField, 26, 6, 4, // 3172: check Inst[31:26] == 0x4
9057 OPC_Decode, 154, 8, 149, 2, // 3176: decode to EVMHEGUMIAN using decoder 277
9058 // 3176: }
9059 1, 9, // 3181: case 0x1: {
9060 OPC_CheckField, 26, 6, 4, // 3183: check Inst[31:26] == 0x4
9061 OPC_Decode, 152, 8, 149, 2, // 3187: decode to EVMHEGSMIAN using decoder 277
9062 // 3187: }
9063 3, 9, // 3192: case 0x3: {
9064 OPC_CheckField, 26, 6, 4, // 3194: check Inst[31:26] == 0x4
9065 OPC_Decode, 150, 8, 149, 2, // 3198: decode to EVMHEGSMFAN using decoder 277
9066 // 3198: }
9067 4, 9, // 3203: case 0x4: {
9068 OPC_CheckField, 26, 6, 4, // 3205: check Inst[31:26] == 0x4
9069 OPC_Decode, 180, 8, 149, 2, // 3209: decode to EVMHOGUMIAN using decoder 277
9070 // 3209: }
9071 5, 9, // 3214: case 0x5: {
9072 OPC_CheckField, 26, 6, 4, // 3216: check Inst[31:26] == 0x4
9073 OPC_Decode, 178, 8, 149, 2, // 3220: decode to EVMHOGSMIAN using decoder 277
9074 // 3220: }
9075 7, 0, // 3225: case 0x7: {
9076 OPC_CheckField, 26, 6, 4, // 3227: check Inst[31:26] == 0x4
9077 OPC_Decode, 176, 8, 149, 2, // 3231: decode to EVMHOGSMFAN using decoder 277
9078 // 3231: }
9079 // 3231: } // switch Inst[2:0]
9080 // 3231: }
9081 184, 1, 25, // 3236: case 0xb8: {
9082 OPC_SwitchField, 0, 3, // 3239: switch Inst[2:0] {
9083 0, 9, // 3242: case 0x0: {
9084 OPC_CheckField, 26, 6, 4, // 3244: check Inst[31:26] == 0x4
9085 OPC_Decode, 219, 8, 149, 2, // 3248: decode to EVMWLUSIANW using decoder 277
9086 // 3248: }
9087 1, 0, // 3253: case 0x1: {
9088 OPC_CheckField, 26, 6, 4, // 3255: check Inst[31:26] == 0x4
9089 OPC_Decode, 213, 8, 149, 2, // 3259: decode to EVMWLSSIANW using decoder 277
9090 // 3259: }
9091 // 3259: } // switch Inst[2:0]
9092 // 3259: }
9093 185, 1, 25, // 3264: case 0xb9: {
9094 OPC_SwitchField, 0, 3, // 3267: switch Inst[2:0] {
9095 0, 9, // 3270: case 0x0: {
9096 OPC_CheckField, 26, 6, 4, // 3272: check Inst[31:26] == 0x4
9097 OPC_Decode, 217, 8, 149, 2, // 3276: decode to EVMWLUMIANW using decoder 277
9098 // 3276: }
9099 1, 0, // 3281: case 0x1: {
9100 OPC_CheckField, 26, 6, 4, // 3283: check Inst[31:26] == 0x4
9101 OPC_Decode, 211, 8, 149, 2, // 3287: decode to EVMWLSMIANW using decoder 277
9102 // 3287: }
9103 // 3287: } // switch Inst[2:0]
9104 // 3287: }
9105 186, 1, 13, // 3292: case 0xba: {
9106 OPC_CheckField, 26, 6, 4, // 3295: check Inst[31:26] == 0x4
9107 OPC_CheckField, 0, 3, 3, // 3299: check Inst[2:0] == 0x3
9108 OPC_Decode, 231, 8, 149, 2, // 3303: decode to EVMWSSFAN using decoder 277
9109 // 3303: }
9110 187, 1, 0, // 3308: case 0xbb: {
9111 OPC_SwitchField, 0, 3, // 3311: switch Inst[2:0] {
9112 0, 9, // 3314: case 0x0: {
9113 OPC_CheckField, 26, 6, 4, // 3316: check Inst[31:26] == 0x4
9114 OPC_Decode, 235, 8, 149, 2, // 3320: decode to EVMWUMIAN using decoder 277
9115 // 3320: }
9116 1, 9, // 3325: case 0x1: {
9117 OPC_CheckField, 26, 6, 4, // 3327: check Inst[31:26] == 0x4
9118 OPC_Decode, 227, 8, 149, 2, // 3331: decode to EVMWSMIAN using decoder 277
9119 // 3331: }
9120 3, 0, // 3336: case 0x3: {
9121 OPC_CheckField, 26, 6, 4, // 3338: check Inst[31:26] == 0x4
9122 OPC_Decode, 223, 8, 149, 2, // 3342: decode to EVMWSMFAN using decoder 277
9123 // 3342: }
9124 // 3342: } // switch Inst[2:0]
9125 // 3342: }
9126 // 3342: } // switch Inst[10:3]
9127};
9128static const uint8_t DecoderTable64[1965] = {
9129 OPC_SwitchField, 27, 5, // 0: switch Inst[31:27] {
9130 7, 62, // 3: case 0x7: {
9131 OPC_SwitchField, 26, 1, // 5: switch Inst[26] {
9132 0, 30, // 8: case 0x0: {
9133 OPC_SwitchField, 50, 14, // 10: switch Inst[63:50] {
9134 128, 3, 16, // 13: case 0x180: {
9135 OPC_Scope, 9, // 16: try {
9136 OPC_CheckField, 16, 5, 0, // 18: check Inst[20:16] == 0x0
9137 OPC_Decode, 156, 13, 164, 2, // 22: decode to PLI using decoder 292
9138 // 22: } else try {
9139 OPC_Decode, 233, 12, 165, 2, // 27: decode to PADDI using decoder 293
9140 // 27: }
9141 // 27: }
9142 132, 3, 0, // 32: case 0x184: {
9143 OPC_Decode, 241, 12, 166, 2, // 35: decode to PADDIpc using decoder 294
9144 // 35: }
9145 // 35: } // switch Inst[63:50]
9146 // 35: }
9147 1, 0, // 40: case 0x1: {
9148 OPC_SwitchField, 52, 1, // 42: switch Inst[52] {
9149 0, 9, // 45: case 0x0: {
9150 OPC_CheckField, 55, 9, 12, // 47: check Inst[63:55] == 0xc
9151 OPC_Decode, 236, 12, 167, 2, // 51: decode to PADDIS using decoder 295
9152 // 51: }
9153 1, 0, // 56: case 0x1: {
9154 OPC_CheckField, 55, 9, 12, // 58: check Inst[63:55] == 0xc
9155 OPC_Decode, 239, 12, 168, 2, // 62: decode to PADDISpc using decoder 296
9156 // 62: }
9157 // 62: } // switch Inst[52]
9158 // 62: }
9159 // 62: } // switch Inst[26]
9160 // 62: }
9161 16, 125, // 67: case 0x10: {
9162 OPC_SwitchField, 50, 14, // 69: switch Inst[63:50] {
9163 192, 2, 95, // 72: case 0x140: {
9164 OPC_SwitchField, 26, 1, // 75: switch Inst[26] {
9165 0, 41, // 78: case 0x0: {
9166 OPC_SwitchField, 18, 3, // 80: switch Inst[20:18] {
9167 0, 9, // 83: case 0x0: {
9168 OPC_CheckField, 48, 2, 0, // 85: check Inst[49:48] == 0x0
9169 OPC_Decode, 162, 23, 169, 2, // 89: decode to XXSPLTI32DX using decoder 297
9170 // 89: }
9171 1, 0, // 94: case 0x1: {
9172 OPC_SwitchField, 17, 1, // 96: switch Inst[17] {
9173 0, 9, // 99: case 0x0: {
9174 OPC_CheckField, 48, 2, 0, // 101: check Inst[49:48] == 0x0
9175 OPC_Decode, 164, 23, 170, 2, // 105: decode to XXSPLTIDP using decoder 298
9176 // 105: }
9177 1, 0, // 110: case 0x1: {
9178 OPC_CheckField, 48, 2, 0, // 112: check Inst[49:48] == 0x0
9179 OPC_Decode, 165, 23, 170, 2, // 116: decode to XXSPLTIW using decoder 298
9180 // 116: }
9181 // 116: } // switch Inst[17]
9182 // 116: }
9183 // 116: } // switch Inst[20:18]
9184 // 116: }
9185 1, 0, // 121: case 0x1: {
9186 OPC_SwitchField, 4, 2, // 123: switch Inst[5:4] {
9187 0, 9, // 126: case 0x0: {
9188 OPC_CheckField, 32, 18, 0, // 128: check Inst[49:32] == 0x0
9189 OPC_Decode, 243, 22, 238, 1, // 132: decode to XXBLENDVB using decoder 238
9190 // 132: }
9191 1, 9, // 137: case 0x1: {
9192 OPC_CheckField, 32, 18, 0, // 139: check Inst[49:32] == 0x0
9193 OPC_Decode, 245, 22, 238, 1, // 143: decode to XXBLENDVH using decoder 238
9194 // 143: }
9195 2, 9, // 148: case 0x2: {
9196 OPC_CheckField, 32, 18, 0, // 150: check Inst[49:32] == 0x0
9197 OPC_Decode, 246, 22, 238, 1, // 154: decode to XXBLENDVW using decoder 238
9198 // 154: }
9199 3, 0, // 159: case 0x3: {
9200 OPC_CheckField, 32, 18, 0, // 161: check Inst[49:32] == 0x0
9201 OPC_Decode, 244, 22, 238, 1, // 165: decode to XXBLENDVD using decoder 238
9202 // 165: }
9203 // 165: } // switch Inst[5:4]
9204 // 165: }
9205 // 165: } // switch Inst[26]
9206 // 165: }
9207 128, 3, 9, // 170: case 0x180: {
9208 OPC_CheckField, 26, 1, 0, // 173: check Inst[26] == 0x0
9209 OPC_Decode, 166, 13, 171, 2, // 177: decode to PLWZ using decoder 299
9210 // 177: }
9211 132, 3, 0, // 182: case 0x184: {
9212 OPC_CheckField, 26, 1, 0, // 185: check Inst[26] == 0x0
9213 OPC_Decode, 173, 13, 172, 2, // 189: decode to PLWZpc using decoder 300
9214 // 189: }
9215 // 189: } // switch Inst[63:50]
9216 // 189: }
9217 17, 84, // 194: case 0x11: {
9218 OPC_SwitchField, 52, 12, // 196: switch Inst[63:52] {
9219 80, 49, // 199: case 0x50: {
9220 OPC_SwitchField, 5, 1, // 201: switch Inst[5] {
9221 0, 33, // 204: case 0x0: {
9222 OPC_SwitchField, 4, 1, // 206: switch Inst[4] {
9223 0, 13, // 209: case 0x0: {
9224 OPC_CheckField, 35, 17, 0, // 211: check Inst[51:35] == 0x0
9225 OPC_CheckField, 26, 1, 0, // 215: check Inst[26] == 0x0
9226 OPC_Decode, 157, 23, 173, 2, // 219: decode to XXPERMX using decoder 301
9227 // 219: }
9228 1, 0, // 224: case 0x1: {
9229 OPC_CheckField, 40, 12, 0, // 226: check Inst[51:40] == 0x0
9230 OPC_CheckField, 26, 1, 0, // 230: check Inst[26] == 0x0
9231 OPC_Decode, 251, 22, 174, 2, // 234: decode to XXEVAL using decoder 302
9232 // 234: }
9233 // 234: } // switch Inst[4]
9234 // 234: }
9235 1, 0, // 239: case 0x1: {
9236 OPC_CheckField, 26, 1, 0, // 241: check Inst[26] == 0x0
9237 OPC_Decode, 170, 23, 175, 2, // 245: decode to XXSSUMUDMCEXT using decoder 303
9238 // 245: }
9239 // 245: } // switch Inst[5]
9240 // 245: }
9241 96, 13, // 250: case 0x60: {
9242 OPC_CheckField, 50, 2, 0, // 252: check Inst[51:50] == 0x0
9243 OPC_CheckField, 26, 1, 0, // 256: check Inst[26] == 0x0
9244 OPC_Decode, 248, 12, 171, 2, // 260: decode to PLBZ using decoder 299
9245 // 260: }
9246 97, 0, // 265: case 0x61: {
9247 OPC_CheckField, 50, 2, 0, // 267: check Inst[51:50] == 0x0
9248 OPC_CheckField, 26, 1, 0, // 271: check Inst[26] == 0x0
9249 OPC_Decode, 255, 12, 172, 2, // 275: decode to PLBZpc using decoder 300
9250 // 275: }
9251 // 275: } // switch Inst[63:52]
9252 // 275: }
9253 18, 27, // 280: case 0x12: {
9254 OPC_SwitchField, 50, 14, // 282: switch Inst[63:50] {
9255 128, 3, 9, // 285: case 0x180: {
9256 OPC_CheckField, 26, 1, 0, // 288: check Inst[26] == 0x0
9257 OPC_Decode, 175, 14, 171, 2, // 292: decode to PSTW using decoder 299
9258 // 292: }
9259 132, 3, 0, // 297: case 0x184: {
9260 OPC_CheckField, 26, 1, 0, // 300: check Inst[26] == 0x0
9261 OPC_Decode, 182, 14, 172, 2, // 304: decode to PSTWpc using decoder 300
9262 // 304: }
9263 // 304: } // switch Inst[63:50]
9264 // 304: }
9265 19, 27, // 309: case 0x13: {
9266 OPC_SwitchField, 50, 14, // 311: switch Inst[63:50] {
9267 128, 3, 9, // 314: case 0x180: {
9268 OPC_CheckField, 26, 1, 0, // 317: check Inst[26] == 0x0
9269 OPC_Decode, 147, 14, 171, 2, // 321: decode to PSTB using decoder 299
9270 // 321: }
9271 132, 3, 0, // 326: case 0x184: {
9272 OPC_CheckField, 26, 1, 0, // 329: check Inst[26] == 0x0
9273 OPC_Decode, 154, 14, 172, 2, // 333: decode to PSTBpc using decoder 300
9274 // 333: }
9275 // 333: } // switch Inst[63:50]
9276 // 333: }
9277 20, 51, // 338: case 0x14: {
9278 OPC_SwitchField, 50, 14, // 340: switch Inst[63:50] {
9279 128, 2, 9, // 343: case 0x100: {
9280 OPC_CheckField, 26, 1, 1, // 346: check Inst[26] == 0x1
9281 OPC_Decode, 158, 13, 171, 2, // 350: decode to PLWA using decoder 299
9282 // 350: }
9283 132, 2, 9, // 355: case 0x104: {
9284 OPC_CheckField, 26, 1, 1, // 358: check Inst[26] == 0x1
9285 OPC_Decode, 165, 13, 172, 2, // 362: decode to PLWApc using decoder 300
9286 // 362: }
9287 128, 3, 9, // 367: case 0x180: {
9288 OPC_CheckField, 26, 1, 0, // 370: check Inst[26] == 0x0
9289 OPC_Decode, 148, 13, 171, 2, // 374: decode to PLHZ using decoder 299
9290 // 374: }
9291 132, 3, 0, // 379: case 0x184: {
9292 OPC_CheckField, 26, 1, 0, // 382: check Inst[26] == 0x0
9293 OPC_Decode, 155, 13, 172, 2, // 386: decode to PLHZpc using decoder 300
9294 // 386: }
9295 // 386: } // switch Inst[63:50]
9296 // 386: }
9297 21, 67, // 391: case 0x15: {
9298 OPC_SwitchField, 50, 14, // 393: switch Inst[63:50] {
9299 128, 2, 17, // 396: case 0x100: {
9300 OPC_SwitchField, 26, 1, // 399: switch Inst[26] {
9301 0, 5, // 402: case 0x0: {
9302 OPC_Decode, 174, 13, 176, 2, // 404: decode to PLXSD using decoder 304
9303 // 404: }
9304 1, 0, // 409: case 0x1: {
9305 OPC_Decode, 178, 13, 176, 2, // 411: decode to PLXSSP using decoder 304
9306 // 411: }
9307 // 411: } // switch Inst[26]
9308 // 411: }
9309 132, 2, 17, // 416: case 0x104: {
9310 OPC_SwitchField, 26, 1, // 419: switch Inst[26] {
9311 0, 5, // 422: case 0x0: {
9312 OPC_Decode, 177, 13, 177, 2, // 424: decode to PLXSDpc using decoder 305
9313 // 424: }
9314 1, 0, // 429: case 0x1: {
9315 OPC_Decode, 181, 13, 177, 2, // 431: decode to PLXSSPpc using decoder 305
9316 // 431: }
9317 // 431: } // switch Inst[26]
9318 // 431: }
9319 128, 3, 9, // 436: case 0x180: {
9320 OPC_CheckField, 26, 1, 0, // 439: check Inst[26] == 0x0
9321 OPC_Decode, 140, 13, 171, 2, // 443: decode to PLHA using decoder 299
9322 // 443: }
9323 132, 3, 0, // 448: case 0x184: {
9324 OPC_CheckField, 26, 1, 0, // 451: check Inst[26] == 0x0
9325 OPC_Decode, 147, 13, 172, 2, // 455: decode to PLHApc using decoder 300
9326 // 455: }
9327 // 455: } // switch Inst[63:50]
9328 // 455: }
9329 22, 27, // 460: case 0x16: {
9330 OPC_SwitchField, 50, 14, // 462: switch Inst[63:50] {
9331 128, 3, 9, // 465: case 0x180: {
9332 OPC_CheckField, 26, 1, 0, // 468: check Inst[26] == 0x0
9333 OPC_Decode, 167, 14, 171, 2, // 472: decode to PSTH using decoder 299
9334 // 472: }
9335 132, 3, 0, // 477: case 0x184: {
9336 OPC_CheckField, 26, 1, 0, // 480: check Inst[26] == 0x0
9337 OPC_Decode, 174, 14, 172, 2, // 484: decode to PSTHpc using decoder 300
9338 // 484: }
9339 // 484: } // switch Inst[63:50]
9340 // 484: }
9341 23, 45, // 489: case 0x17: {
9342 OPC_SwitchField, 26, 1, // 491: switch Inst[26] {
9343 0, 19, // 494: case 0x0: {
9344 OPC_SwitchField, 50, 14, // 496: switch Inst[63:50] {
9345 128, 2, 5, // 499: case 0x100: {
9346 OPC_Decode, 183, 14, 176, 2, // 502: decode to PSTXSD using decoder 304
9347 // 502: }
9348 132, 2, 0, // 507: case 0x104: {
9349 OPC_Decode, 186, 14, 177, 2, // 510: decode to PSTXSDpc using decoder 305
9350 // 510: }
9351 // 510: } // switch Inst[63:50]
9352 // 510: }
9353 1, 0, // 515: case 0x1: {
9354 OPC_SwitchField, 50, 14, // 517: switch Inst[63:50] {
9355 128, 2, 5, // 520: case 0x100: {
9356 OPC_Decode, 187, 14, 176, 2, // 523: decode to PSTXSSP using decoder 304
9357 // 523: }
9358 132, 2, 0, // 528: case 0x104: {
9359 OPC_Decode, 190, 14, 177, 2, // 531: decode to PSTXSSPpc using decoder 305
9360 // 531: }
9361 // 531: } // switch Inst[63:50]
9362 // 531: }
9363 // 531: } // switch Inst[26]
9364 // 531: }
9365 24, 27, // 536: case 0x18: {
9366 OPC_SwitchField, 50, 14, // 538: switch Inst[63:50] {
9367 128, 3, 9, // 541: case 0x180: {
9368 OPC_CheckField, 26, 1, 0, // 544: check Inst[26] == 0x0
9369 OPC_Decode, 136, 13, 178, 2, // 548: decode to PLFS using decoder 306
9370 // 548: }
9371 132, 3, 0, // 553: case 0x184: {
9372 OPC_CheckField, 26, 1, 0, // 556: check Inst[26] == 0x0
9373 OPC_Decode, 139, 13, 179, 2, // 560: decode to PLFSpc using decoder 307
9374 // 560: }
9375 // 560: } // switch Inst[63:50]
9376 // 560: }
9377 25, 43, // 565: case 0x19: {
9378 OPC_SwitchField, 50, 14, // 567: switch Inst[63:50] {
9379 128, 2, 5, // 570: case 0x100: {
9380 OPC_Decode, 182, 13, 180, 2, // 573: decode to PLXV using decoder 308
9381 // 573: }
9382 132, 2, 5, // 578: case 0x104: {
9383 OPC_Decode, 189, 13, 181, 2, // 581: decode to PLXVpc using decoder 309
9384 // 581: }
9385 128, 3, 9, // 586: case 0x180: {
9386 OPC_CheckField, 26, 1, 0, // 589: check Inst[26] == 0x0
9387 OPC_Decode, 132, 13, 182, 2, // 593: decode to PLFD using decoder 310
9388 // 593: }
9389 132, 3, 0, // 598: case 0x184: {
9390 OPC_CheckField, 26, 1, 0, // 601: check Inst[26] == 0x0
9391 OPC_Decode, 135, 13, 183, 2, // 605: decode to PLFDpc using decoder 311
9392 // 605: }
9393 // 605: } // switch Inst[63:50]
9394 // 605: }
9395 26, 27, // 610: case 0x1a: {
9396 OPC_SwitchField, 50, 14, // 612: switch Inst[63:50] {
9397 128, 3, 9, // 615: case 0x180: {
9398 OPC_CheckField, 26, 1, 0, // 618: check Inst[26] == 0x0
9399 OPC_Decode, 163, 14, 178, 2, // 622: decode to PSTFS using decoder 306
9400 // 622: }
9401 132, 3, 0, // 627: case 0x184: {
9402 OPC_CheckField, 26, 1, 0, // 630: check Inst[26] == 0x0
9403 OPC_Decode, 166, 14, 179, 2, // 634: decode to PSTFSpc using decoder 307
9404 // 634: }
9405 // 634: } // switch Inst[63:50]
9406 // 634: }
9407 27, 43, // 639: case 0x1b: {
9408 OPC_SwitchField, 50, 14, // 641: switch Inst[63:50] {
9409 128, 2, 5, // 644: case 0x100: {
9410 OPC_Decode, 191, 14, 180, 2, // 647: decode to PSTXV using decoder 308
9411 // 647: }
9412 132, 2, 5, // 652: case 0x104: {
9413 OPC_Decode, 198, 14, 181, 2, // 655: decode to PSTXVpc using decoder 309
9414 // 655: }
9415 128, 3, 9, // 660: case 0x180: {
9416 OPC_CheckField, 26, 1, 0, // 663: check Inst[26] == 0x0
9417 OPC_Decode, 159, 14, 182, 2, // 667: decode to PSTFD using decoder 310
9418 // 667: }
9419 132, 3, 0, // 672: case 0x184: {
9420 OPC_CheckField, 26, 1, 0, // 675: check Inst[26] == 0x0
9421 OPC_Decode, 162, 14, 183, 2, // 679: decode to PSTFDpc using decoder 311
9422 // 679: }
9423 // 679: } // switch Inst[63:50]
9424 // 679: }
9425 28, 27, // 684: case 0x1c: {
9426 OPC_SwitchField, 50, 14, // 686: switch Inst[63:50] {
9427 128, 2, 9, // 689: case 0x100: {
9428 OPC_CheckField, 26, 1, 1, // 692: check Inst[26] == 0x1
9429 OPC_Decode, 128, 13, 184, 2, // 696: decode to PLD using decoder 312
9430 // 696: }
9431 132, 2, 0, // 701: case 0x104: {
9432 OPC_CheckField, 26, 1, 1, // 704: check Inst[26] == 0x1
9433 OPC_Decode, 131, 13, 185, 2, // 708: decode to PLDpc using decoder 313
9434 // 708: }
9435 // 708: } // switch Inst[63:50]
9436 // 708: }
9437 29, 167, 9, // 713: case 0x1d: {
9438 OPC_SwitchField, 50, 14, // 716: switch Inst[63:50] {
9439 128, 2, 9, // 719: case 0x100: {
9440 OPC_CheckField, 26, 1, 0, // 722: check Inst[26] == 0x0
9441 OPC_Decode, 183, 13, 186, 2, // 726: decode to PLXVP using decoder 314
9442 // 726: }
9443 132, 2, 9, // 731: case 0x104: {
9444 OPC_CheckField, 26, 1, 0, // 734: check Inst[26] == 0x0
9445 OPC_Decode, 186, 13, 187, 2, // 738: decode to PLXVPpc using decoder 315
9446 // 738: }
9447 228, 3, 0, // 743: case 0x1e4: {
9448 OPC_SwitchField, 3, 8, // 746: switch Inst[10:3] {
9449 2, 25, // 749: case 0x2: {
9450 OPC_CheckField, 48, 2, 0, // 751: check Inst[49:48] == 0x0
9451 OPC_CheckField, 40, 4, 0, // 755: check Inst[43:40] == 0x0
9452 OPC_CheckField, 26, 1, 1, // 759: check Inst[26] == 0x1
9453 OPC_CheckField, 21, 2, 0, // 763: check Inst[22:21] == 0x0
9454 OPC_CheckField, 0, 1, 0, // 767: check Inst[0] == 0x0
9455 OPC_Decode, 128, 14, 188, 2, // 771: decode to PMXVI8GER4PP using decoder 316
9456 // 771: }
9457 3, 25, // 776: case 0x3: {
9458 OPC_CheckField, 48, 2, 0, // 778: check Inst[49:48] == 0x0
9459 OPC_CheckField, 40, 4, 0, // 782: check Inst[43:40] == 0x0
9460 OPC_CheckField, 26, 1, 1, // 786: check Inst[26] == 0x1
9461 OPC_CheckField, 21, 2, 0, // 790: check Inst[22:21] == 0x0
9462 OPC_CheckField, 0, 1, 0, // 794: check Inst[0] == 0x0
9463 OPC_Decode, 255, 13, 189, 2, // 798: decode to PMXVI8GER4 using decoder 317
9464 // 798: }
9465 10, 25, // 803: case 0xa: {
9466 OPC_CheckField, 48, 2, 0, // 805: check Inst[49:48] == 0x0
9467 OPC_CheckField, 26, 1, 1, // 809: check Inst[26] == 0x1
9468 OPC_CheckField, 21, 2, 0, // 813: check Inst[22:21] == 0x0
9469 OPC_CheckField, 16, 1, 0, // 817: check Inst[16] == 0x0
9470 OPC_CheckField, 0, 1, 0, // 821: check Inst[0] == 0x0
9471 OPC_Decode, 201, 13, 190, 2, // 825: decode to PMDMXVI8GERX4PP using decoder 318
9472 // 825: }
9473 11, 25, // 830: case 0xb: {
9474 OPC_CheckField, 48, 2, 0, // 832: check Inst[49:48] == 0x0
9475 OPC_CheckField, 26, 1, 1, // 836: check Inst[26] == 0x1
9476 OPC_CheckField, 21, 2, 0, // 840: check Inst[22:21] == 0x0
9477 OPC_CheckField, 16, 1, 0, // 844: check Inst[16] == 0x0
9478 OPC_CheckField, 0, 1, 0, // 848: check Inst[0] == 0x0
9479 OPC_Decode, 200, 13, 191, 2, // 852: decode to PMDMXVI8GERX4 using decoder 319
9480 // 852: }
9481 18, 25, // 857: case 0x12: {
9482 OPC_CheckField, 48, 2, 0, // 859: check Inst[49:48] == 0x0
9483 OPC_CheckField, 40, 6, 0, // 863: check Inst[45:40] == 0x0
9484 OPC_CheckField, 26, 1, 1, // 867: check Inst[26] == 0x1
9485 OPC_CheckField, 21, 2, 0, // 871: check Inst[22:21] == 0x0
9486 OPC_CheckField, 0, 1, 0, // 875: check Inst[0] == 0x0
9487 OPC_Decode, 217, 13, 192, 2, // 879: decode to PMXVF16GER2PP using decoder 320
9488 // 879: }
9489 19, 25, // 884: case 0x13: {
9490 OPC_CheckField, 48, 2, 0, // 886: check Inst[49:48] == 0x0
9491 OPC_CheckField, 40, 6, 0, // 890: check Inst[45:40] == 0x0
9492 OPC_CheckField, 26, 1, 1, // 894: check Inst[26] == 0x1
9493 OPC_CheckField, 21, 2, 0, // 898: check Inst[22:21] == 0x0
9494 OPC_CheckField, 0, 1, 0, // 902: check Inst[0] == 0x0
9495 OPC_Decode, 213, 13, 193, 2, // 906: decode to PMXVF16GER2 using decoder 321
9496 // 906: }
9497 26, 21, // 911: case 0x1a: {
9498 OPC_CheckField, 40, 10, 0, // 913: check Inst[49:40] == 0x0
9499 OPC_CheckField, 26, 1, 1, // 917: check Inst[26] == 0x1
9500 OPC_CheckField, 21, 2, 0, // 921: check Inst[22:21] == 0x0
9501 OPC_CheckField, 0, 1, 0, // 925: check Inst[0] == 0x0
9502 OPC_Decode, 227, 13, 194, 2, // 929: decode to PMXVF32GERPP using decoder 322
9503 // 929: }
9504 27, 21, // 934: case 0x1b: {
9505 OPC_CheckField, 40, 10, 0, // 936: check Inst[49:40] == 0x0
9506 OPC_CheckField, 26, 1, 1, // 940: check Inst[26] == 0x1
9507 OPC_CheckField, 21, 2, 0, // 944: check Inst[22:21] == 0x0
9508 OPC_CheckField, 0, 1, 0, // 948: check Inst[0] == 0x0
9509 OPC_Decode, 223, 13, 195, 2, // 952: decode to PMXVF32GER using decoder 323
9510 // 952: }
9511 34, 21, // 957: case 0x22: {
9512 OPC_CheckField, 48, 2, 0, // 959: check Inst[49:48] == 0x0
9513 OPC_CheckField, 26, 1, 1, // 963: check Inst[26] == 0x1
9514 OPC_CheckField, 21, 2, 0, // 967: check Inst[22:21] == 0x0
9515 OPC_CheckField, 0, 1, 0, // 971: check Inst[0] == 0x0
9516 OPC_Decode, 252, 13, 196, 2, // 975: decode to PMXVI4GER8PP using decoder 324
9517 // 975: }
9518 35, 21, // 980: case 0x23: {
9519 OPC_CheckField, 48, 2, 0, // 982: check Inst[49:48] == 0x0
9520 OPC_CheckField, 26, 1, 1, // 986: check Inst[26] == 0x1
9521 OPC_CheckField, 21, 2, 0, // 990: check Inst[22:21] == 0x0
9522 OPC_CheckField, 0, 1, 0, // 994: check Inst[0] == 0x0
9523 OPC_Decode, 251, 13, 197, 2, // 998: decode to PMXVI4GER8 using decoder 325
9524 // 998: }
9525 42, 25, // 1003: case 0x2a: {
9526 OPC_CheckField, 48, 2, 0, // 1005: check Inst[49:48] == 0x0
9527 OPC_CheckField, 40, 6, 0, // 1009: check Inst[45:40] == 0x0
9528 OPC_CheckField, 26, 1, 1, // 1013: check Inst[26] == 0x1
9529 OPC_CheckField, 21, 2, 0, // 1017: check Inst[22:21] == 0x0
9530 OPC_CheckField, 0, 1, 0, // 1021: check Inst[0] == 0x0
9531 OPC_Decode, 246, 13, 192, 2, // 1025: decode to PMXVI16GER2SPP using decoder 320
9532 // 1025: }
9533 43, 25, // 1030: case 0x2b: {
9534 OPC_CheckField, 48, 2, 0, // 1032: check Inst[49:48] == 0x0
9535 OPC_CheckField, 40, 6, 0, // 1036: check Inst[45:40] == 0x0
9536 OPC_CheckField, 26, 1, 1, // 1040: check Inst[26] == 0x1
9537 OPC_CheckField, 21, 2, 0, // 1044: check Inst[22:21] == 0x0
9538 OPC_CheckField, 0, 1, 0, // 1048: check Inst[0] == 0x0
9539 OPC_Decode, 245, 13, 193, 2, // 1052: decode to PMXVI16GER2S using decoder 321
9540 // 1052: }
9541 50, 25, // 1057: case 0x32: {
9542 OPC_CheckField, 48, 2, 0, // 1059: check Inst[49:48] == 0x0
9543 OPC_CheckField, 40, 6, 0, // 1063: check Inst[45:40] == 0x0
9544 OPC_CheckField, 26, 1, 1, // 1067: check Inst[26] == 0x1
9545 OPC_CheckField, 21, 2, 0, // 1071: check Inst[22:21] == 0x0
9546 OPC_CheckField, 0, 1, 0, // 1075: check Inst[0] == 0x0
9547 OPC_Decode, 207, 13, 192, 2, // 1079: decode to PMXVBF16GER2PP using decoder 320
9548 // 1079: }
9549 51, 25, // 1084: case 0x33: {
9550 OPC_CheckField, 48, 2, 0, // 1086: check Inst[49:48] == 0x0
9551 OPC_CheckField, 40, 6, 0, // 1090: check Inst[45:40] == 0x0
9552 OPC_CheckField, 26, 1, 1, // 1094: check Inst[26] == 0x1
9553 OPC_CheckField, 21, 2, 0, // 1098: check Inst[22:21] == 0x0
9554 OPC_CheckField, 0, 1, 0, // 1102: check Inst[0] == 0x0
9555 OPC_Decode, 203, 13, 193, 2, // 1106: decode to PMXVBF16GER2 using decoder 321
9556 // 1106: }
9557 58, 25, // 1111: case 0x3a: {
9558 OPC_CheckField, 40, 10, 0, // 1113: check Inst[49:40] == 0x0
9559 OPC_CheckField, 32, 2, 0, // 1117: check Inst[33:32] == 0x0
9560 OPC_CheckField, 26, 1, 1, // 1121: check Inst[26] == 0x1
9561 OPC_CheckField, 21, 2, 0, // 1125: check Inst[22:21] == 0x0
9562 OPC_CheckField, 0, 1, 0, // 1129: check Inst[0] == 0x0
9563 OPC_Decode, 237, 13, 198, 2, // 1133: decode to PMXVF64GERPP using decoder 326
9564 // 1133: }
9565 59, 25, // 1138: case 0x3b: {
9566 OPC_CheckField, 40, 10, 0, // 1140: check Inst[49:40] == 0x0
9567 OPC_CheckField, 32, 2, 0, // 1144: check Inst[33:32] == 0x0
9568 OPC_CheckField, 26, 1, 1, // 1148: check Inst[26] == 0x1
9569 OPC_CheckField, 21, 2, 0, // 1152: check Inst[22:21] == 0x0
9570 OPC_CheckField, 0, 1, 0, // 1156: check Inst[0] == 0x0
9571 OPC_Decode, 233, 13, 199, 2, // 1160: decode to PMXVF64GER using decoder 327
9572 // 1160: }
9573 66, 29, // 1165: case 0x42: {
9574 OPC_CheckField, 48, 2, 0, // 1167: check Inst[49:48] == 0x0
9575 OPC_CheckField, 44, 2, 0, // 1171: check Inst[45:44] == 0x0
9576 OPC_CheckField, 26, 1, 1, // 1175: check Inst[26] == 0x1
9577 OPC_CheckField, 21, 2, 0, // 1179: check Inst[22:21] == 0x0
9578 OPC_CheckField, 16, 1, 0, // 1183: check Inst[16] == 0x0
9579 OPC_CheckField, 0, 1, 0, // 1187: check Inst[0] == 0x0
9580 OPC_Decode, 199, 13, 200, 2, // 1191: decode to PMDMXVF16GERX2PP using decoder 328
9581 // 1191: }
9582 67, 29, // 1196: case 0x43: {
9583 OPC_CheckField, 48, 2, 0, // 1198: check Inst[49:48] == 0x0
9584 OPC_CheckField, 44, 2, 0, // 1202: check Inst[45:44] == 0x0
9585 OPC_CheckField, 26, 1, 1, // 1206: check Inst[26] == 0x1
9586 OPC_CheckField, 21, 2, 0, // 1210: check Inst[22:21] == 0x0
9587 OPC_CheckField, 16, 1, 0, // 1214: check Inst[16] == 0x0
9588 OPC_CheckField, 0, 1, 0, // 1218: check Inst[0] == 0x0
9589 OPC_Decode, 195, 13, 201, 2, // 1222: decode to PMDMXVF16GERX2 using decoder 329
9590 // 1222: }
9591 74, 29, // 1227: case 0x4a: {
9592 OPC_CheckField, 48, 2, 0, // 1229: check Inst[49:48] == 0x0
9593 OPC_CheckField, 44, 2, 0, // 1233: check Inst[45:44] == 0x0
9594 OPC_CheckField, 26, 1, 1, // 1237: check Inst[26] == 0x1
9595 OPC_CheckField, 21, 2, 0, // 1241: check Inst[22:21] == 0x0
9596 OPC_CheckField, 16, 1, 0, // 1245: check Inst[16] == 0x0
9597 OPC_CheckField, 0, 1, 0, // 1249: check Inst[0] == 0x0
9598 OPC_Decode, 194, 13, 200, 2, // 1253: decode to PMDMXVBF16GERX2PP using decoder 328
9599 // 1253: }
9600 75, 25, // 1258: case 0x4b: {
9601 OPC_CheckField, 48, 2, 0, // 1260: check Inst[49:48] == 0x0
9602 OPC_CheckField, 40, 6, 0, // 1264: check Inst[45:40] == 0x0
9603 OPC_CheckField, 26, 1, 1, // 1268: check Inst[26] == 0x1
9604 OPC_CheckField, 21, 2, 0, // 1272: check Inst[22:21] == 0x0
9605 OPC_CheckField, 0, 1, 0, // 1276: check Inst[0] == 0x0
9606 OPC_Decode, 243, 13, 193, 2, // 1280: decode to PMXVI16GER2 using decoder 321
9607 // 1280: }
9608 82, 25, // 1285: case 0x52: {
9609 OPC_CheckField, 48, 2, 0, // 1287: check Inst[49:48] == 0x0
9610 OPC_CheckField, 40, 6, 0, // 1291: check Inst[45:40] == 0x0
9611 OPC_CheckField, 26, 1, 1, // 1295: check Inst[26] == 0x1
9612 OPC_CheckField, 21, 2, 0, // 1299: check Inst[22:21] == 0x0
9613 OPC_CheckField, 0, 1, 0, // 1303: check Inst[0] == 0x0
9614 OPC_Decode, 215, 13, 192, 2, // 1307: decode to PMXVF16GER2NP using decoder 320
9615 // 1307: }
9616 83, 29, // 1312: case 0x53: {
9617 OPC_CheckField, 48, 2, 0, // 1314: check Inst[49:48] == 0x0
9618 OPC_CheckField, 44, 2, 0, // 1318: check Inst[45:44] == 0x0
9619 OPC_CheckField, 26, 1, 1, // 1322: check Inst[26] == 0x1
9620 OPC_CheckField, 21, 2, 0, // 1326: check Inst[22:21] == 0x0
9621 OPC_CheckField, 16, 1, 0, // 1330: check Inst[16] == 0x0
9622 OPC_CheckField, 0, 1, 0, // 1334: check Inst[0] == 0x0
9623 OPC_Decode, 197, 13, 200, 2, // 1338: decode to PMDMXVF16GERX2NP using decoder 328
9624 // 1338: }
9625 90, 21, // 1343: case 0x5a: {
9626 OPC_CheckField, 40, 10, 0, // 1345: check Inst[49:40] == 0x0
9627 OPC_CheckField, 26, 1, 1, // 1349: check Inst[26] == 0x1
9628 OPC_CheckField, 21, 2, 0, // 1353: check Inst[22:21] == 0x0
9629 OPC_CheckField, 0, 1, 0, // 1357: check Inst[0] == 0x0
9630 OPC_Decode, 225, 13, 194, 2, // 1361: decode to PMXVF32GERNP using decoder 322
9631 // 1361: }
9632 91, 29, // 1366: case 0x5b: {
9633 OPC_CheckField, 48, 2, 0, // 1368: check Inst[49:48] == 0x0
9634 OPC_CheckField, 44, 2, 0, // 1372: check Inst[45:44] == 0x0
9635 OPC_CheckField, 26, 1, 1, // 1376: check Inst[26] == 0x1
9636 OPC_CheckField, 21, 2, 0, // 1380: check Inst[22:21] == 0x0
9637 OPC_CheckField, 16, 1, 0, // 1384: check Inst[16] == 0x0
9638 OPC_CheckField, 0, 1, 0, // 1388: check Inst[0] == 0x0
9639 OPC_Decode, 190, 13, 201, 2, // 1392: decode to PMDMXVBF16GERX2 using decoder 329
9640 // 1392: }
9641 98, 25, // 1397: case 0x62: {
9642 OPC_CheckField, 48, 2, 0, // 1399: check Inst[49:48] == 0x0
9643 OPC_CheckField, 26, 1, 1, // 1403: check Inst[26] == 0x1
9644 OPC_CheckField, 21, 2, 0, // 1407: check Inst[22:21] == 0x0
9645 OPC_CheckField, 16, 1, 0, // 1411: check Inst[16] == 0x0
9646 OPC_CheckField, 0, 1, 0, // 1415: check Inst[0] == 0x0
9647 OPC_Decode, 202, 13, 190, 2, // 1419: decode to PMDMXVI8GERX4SPP using decoder 318
9648 // 1419: }
9649 99, 25, // 1424: case 0x63: {
9650 OPC_CheckField, 48, 2, 0, // 1426: check Inst[49:48] == 0x0
9651 OPC_CheckField, 40, 4, 0, // 1430: check Inst[43:40] == 0x0
9652 OPC_CheckField, 26, 1, 1, // 1434: check Inst[26] == 0x1
9653 OPC_CheckField, 21, 2, 0, // 1438: check Inst[22:21] == 0x0
9654 OPC_CheckField, 0, 1, 0, // 1442: check Inst[0] == 0x0
9655 OPC_Decode, 129, 14, 188, 2, // 1446: decode to PMXVI8GER4SPP using decoder 316
9656 // 1446: }
9657 107, 25, // 1451: case 0x6b: {
9658 OPC_CheckField, 48, 2, 0, // 1453: check Inst[49:48] == 0x0
9659 OPC_CheckField, 40, 6, 0, // 1457: check Inst[45:40] == 0x0
9660 OPC_CheckField, 26, 1, 1, // 1461: check Inst[26] == 0x1
9661 OPC_CheckField, 21, 2, 0, // 1465: check Inst[22:21] == 0x0
9662 OPC_CheckField, 0, 1, 0, // 1469: check Inst[0] == 0x0
9663 OPC_Decode, 244, 13, 192, 2, // 1473: decode to PMXVI16GER2PP using decoder 320
9664 // 1473: }
9665 114, 25, // 1478: case 0x72: {
9666 OPC_CheckField, 48, 2, 0, // 1480: check Inst[49:48] == 0x0
9667 OPC_CheckField, 40, 6, 0, // 1484: check Inst[45:40] == 0x0
9668 OPC_CheckField, 26, 1, 1, // 1488: check Inst[26] == 0x1
9669 OPC_CheckField, 21, 2, 0, // 1492: check Inst[22:21] == 0x0
9670 OPC_CheckField, 0, 1, 0, // 1496: check Inst[0] == 0x0
9671 OPC_Decode, 205, 13, 192, 2, // 1500: decode to PMXVBF16GER2NP using decoder 320
9672 // 1500: }
9673 115, 29, // 1505: case 0x73: {
9674 OPC_CheckField, 48, 2, 0, // 1507: check Inst[49:48] == 0x0
9675 OPC_CheckField, 44, 2, 0, // 1511: check Inst[45:44] == 0x0
9676 OPC_CheckField, 26, 1, 1, // 1515: check Inst[26] == 0x1
9677 OPC_CheckField, 21, 2, 0, // 1519: check Inst[22:21] == 0x0
9678 OPC_CheckField, 16, 1, 0, // 1523: check Inst[16] == 0x0
9679 OPC_CheckField, 0, 1, 0, // 1527: check Inst[0] == 0x0
9680 OPC_Decode, 192, 13, 200, 2, // 1531: decode to PMDMXVBF16GERX2NP using decoder 328
9681 // 1531: }
9682 122, 25, // 1536: case 0x7a: {
9683 OPC_CheckField, 40, 10, 0, // 1538: check Inst[49:40] == 0x0
9684 OPC_CheckField, 32, 2, 0, // 1542: check Inst[33:32] == 0x0
9685 OPC_CheckField, 26, 1, 1, // 1546: check Inst[26] == 0x1
9686 OPC_CheckField, 21, 2, 0, // 1550: check Inst[22:21] == 0x0
9687 OPC_CheckField, 0, 1, 0, // 1554: check Inst[0] == 0x0
9688 OPC_Decode, 235, 13, 198, 2, // 1558: decode to PMXVF64GERNP using decoder 326
9689 // 1558: }
9690 146, 1, 25, // 1563: case 0x92: {
9691 OPC_CheckField, 48, 2, 0, // 1566: check Inst[49:48] == 0x0
9692 OPC_CheckField, 40, 6, 0, // 1570: check Inst[45:40] == 0x0
9693 OPC_CheckField, 26, 1, 1, // 1574: check Inst[26] == 0x1
9694 OPC_CheckField, 21, 2, 0, // 1578: check Inst[22:21] == 0x0
9695 OPC_CheckField, 0, 1, 0, // 1582: check Inst[0] == 0x0
9696 OPC_Decode, 216, 13, 192, 2, // 1586: decode to PMXVF16GER2PN using decoder 320
9697 // 1586: }
9698 147, 1, 29, // 1591: case 0x93: {
9699 OPC_CheckField, 48, 2, 0, // 1594: check Inst[49:48] == 0x0
9700 OPC_CheckField, 44, 2, 0, // 1598: check Inst[45:44] == 0x0
9701 OPC_CheckField, 26, 1, 1, // 1602: check Inst[26] == 0x1
9702 OPC_CheckField, 21, 2, 0, // 1606: check Inst[22:21] == 0x0
9703 OPC_CheckField, 16, 1, 0, // 1610: check Inst[16] == 0x0
9704 OPC_CheckField, 0, 1, 0, // 1614: check Inst[0] == 0x0
9705 OPC_Decode, 198, 13, 200, 2, // 1618: decode to PMDMXVF16GERX2PN using decoder 328
9706 // 1618: }
9707 154, 1, 21, // 1623: case 0x9a: {
9708 OPC_CheckField, 40, 10, 0, // 1626: check Inst[49:40] == 0x0
9709 OPC_CheckField, 26, 1, 1, // 1630: check Inst[26] == 0x1
9710 OPC_CheckField, 21, 2, 0, // 1634: check Inst[22:21] == 0x0
9711 OPC_CheckField, 0, 1, 0, // 1638: check Inst[0] == 0x0
9712 OPC_Decode, 226, 13, 194, 2, // 1642: decode to PMXVF32GERPN using decoder 322
9713 // 1642: }
9714 178, 1, 25, // 1647: case 0xb2: {
9715 OPC_CheckField, 48, 2, 0, // 1650: check Inst[49:48] == 0x0
9716 OPC_CheckField, 40, 6, 0, // 1654: check Inst[45:40] == 0x0
9717 OPC_CheckField, 26, 1, 1, // 1658: check Inst[26] == 0x1
9718 OPC_CheckField, 21, 2, 0, // 1662: check Inst[22:21] == 0x0
9719 OPC_CheckField, 0, 1, 0, // 1666: check Inst[0] == 0x0
9720 OPC_Decode, 206, 13, 192, 2, // 1670: decode to PMXVBF16GER2PN using decoder 320
9721 // 1670: }
9722 179, 1, 29, // 1675: case 0xb3: {
9723 OPC_CheckField, 48, 2, 0, // 1678: check Inst[49:48] == 0x0
9724 OPC_CheckField, 44, 2, 0, // 1682: check Inst[45:44] == 0x0
9725 OPC_CheckField, 26, 1, 1, // 1686: check Inst[26] == 0x1
9726 OPC_CheckField, 21, 2, 0, // 1690: check Inst[22:21] == 0x0
9727 OPC_CheckField, 16, 1, 0, // 1694: check Inst[16] == 0x0
9728 OPC_CheckField, 0, 1, 0, // 1698: check Inst[0] == 0x0
9729 OPC_Decode, 193, 13, 200, 2, // 1702: decode to PMDMXVBF16GERX2PN using decoder 328
9730 // 1702: }
9731 186, 1, 25, // 1707: case 0xba: {
9732 OPC_CheckField, 40, 10, 0, // 1710: check Inst[49:40] == 0x0
9733 OPC_CheckField, 32, 2, 0, // 1714: check Inst[33:32] == 0x0
9734 OPC_CheckField, 26, 1, 1, // 1718: check Inst[26] == 0x1
9735 OPC_CheckField, 21, 2, 0, // 1722: check Inst[22:21] == 0x0
9736 OPC_CheckField, 0, 1, 0, // 1726: check Inst[0] == 0x0
9737 OPC_Decode, 236, 13, 198, 2, // 1730: decode to PMXVF64GERPN using decoder 326
9738 // 1730: }
9739 202, 1, 29, // 1735: case 0xca: {
9740 OPC_CheckField, 48, 2, 0, // 1738: check Inst[49:48] == 0x0
9741 OPC_CheckField, 44, 2, 0, // 1742: check Inst[45:44] == 0x0
9742 OPC_CheckField, 26, 1, 1, // 1746: check Inst[26] == 0x1
9743 OPC_CheckField, 21, 2, 0, // 1750: check Inst[22:21] == 0x0
9744 OPC_CheckField, 16, 1, 0, // 1754: check Inst[16] == 0x0
9745 OPC_CheckField, 0, 1, 0, // 1758: check Inst[0] == 0x0
9746 OPC_Decode, 196, 13, 200, 2, // 1762: decode to PMDMXVF16GERX2NN using decoder 328
9747 // 1762: }
9748 210, 1, 25, // 1767: case 0xd2: {
9749 OPC_CheckField, 48, 2, 0, // 1770: check Inst[49:48] == 0x0
9750 OPC_CheckField, 40, 6, 0, // 1774: check Inst[45:40] == 0x0
9751 OPC_CheckField, 26, 1, 1, // 1778: check Inst[26] == 0x1
9752 OPC_CheckField, 21, 2, 0, // 1782: check Inst[22:21] == 0x0
9753 OPC_CheckField, 0, 1, 0, // 1786: check Inst[0] == 0x0
9754 OPC_Decode, 214, 13, 192, 2, // 1790: decode to PMXVF16GER2NN using decoder 320
9755 // 1790: }
9756 218, 1, 21, // 1795: case 0xda: {
9757 OPC_CheckField, 40, 10, 0, // 1798: check Inst[49:40] == 0x0
9758 OPC_CheckField, 26, 1, 1, // 1802: check Inst[26] == 0x1
9759 OPC_CheckField, 21, 2, 0, // 1806: check Inst[22:21] == 0x0
9760 OPC_CheckField, 0, 1, 0, // 1810: check Inst[0] == 0x0
9761 OPC_Decode, 224, 13, 194, 2, // 1814: decode to PMXVF32GERNN using decoder 322
9762 // 1814: }
9763 234, 1, 29, // 1819: case 0xea: {
9764 OPC_CheckField, 48, 2, 0, // 1822: check Inst[49:48] == 0x0
9765 OPC_CheckField, 44, 2, 0, // 1826: check Inst[45:44] == 0x0
9766 OPC_CheckField, 26, 1, 1, // 1830: check Inst[26] == 0x1
9767 OPC_CheckField, 21, 2, 0, // 1834: check Inst[22:21] == 0x0
9768 OPC_CheckField, 16, 1, 0, // 1838: check Inst[16] == 0x0
9769 OPC_CheckField, 0, 1, 0, // 1842: check Inst[0] == 0x0
9770 OPC_Decode, 191, 13, 200, 2, // 1846: decode to PMDMXVBF16GERX2NN using decoder 328
9771 // 1846: }
9772 242, 1, 25, // 1851: case 0xf2: {
9773 OPC_CheckField, 48, 2, 0, // 1854: check Inst[49:48] == 0x0
9774 OPC_CheckField, 40, 6, 0, // 1858: check Inst[45:40] == 0x0
9775 OPC_CheckField, 26, 1, 1, // 1862: check Inst[26] == 0x1
9776 OPC_CheckField, 21, 2, 0, // 1866: check Inst[22:21] == 0x0
9777 OPC_CheckField, 0, 1, 0, // 1870: check Inst[0] == 0x0
9778 OPC_Decode, 204, 13, 192, 2, // 1874: decode to PMXVBF16GER2NN using decoder 320
9779 // 1874: }
9780 250, 1, 0, // 1879: case 0xfa: {
9781 OPC_CheckField, 40, 10, 0, // 1882: check Inst[49:40] == 0x0
9782 OPC_CheckField, 32, 2, 0, // 1886: check Inst[33:32] == 0x0
9783 OPC_CheckField, 26, 1, 1, // 1890: check Inst[26] == 0x1
9784 OPC_CheckField, 21, 2, 0, // 1894: check Inst[22:21] == 0x0
9785 OPC_CheckField, 0, 1, 0, // 1898: check Inst[0] == 0x0
9786 OPC_Decode, 234, 13, 198, 2, // 1902: decode to PMXVF64GERNN using decoder 326
9787 // 1902: }
9788 // 1902: } // switch Inst[10:3]
9789 // 1902: }
9790 // 1902: } // switch Inst[63:50]
9791 // 1902: }
9792 30, 27, // 1907: case 0x1e: {
9793 OPC_SwitchField, 50, 14, // 1909: switch Inst[63:50] {
9794 128, 2, 9, // 1912: case 0x100: {
9795 OPC_CheckField, 26, 1, 1, // 1915: check Inst[26] == 0x1
9796 OPC_Decode, 155, 14, 184, 2, // 1919: decode to PSTD using decoder 312
9797 // 1919: }
9798 132, 2, 0, // 1924: case 0x104: {
9799 OPC_CheckField, 26, 1, 1, // 1927: check Inst[26] == 0x1
9800 OPC_Decode, 158, 14, 185, 2, // 1931: decode to PSTDpc using decoder 313
9801 // 1931: }
9802 // 1931: } // switch Inst[63:50]
9803 // 1931: }
9804 31, 0, // 1936: case 0x1f: {
9805 OPC_SwitchField, 50, 14, // 1938: switch Inst[63:50] {
9806 128, 2, 9, // 1941: case 0x100: {
9807 OPC_CheckField, 26, 1, 0, // 1944: check Inst[26] == 0x0
9808 OPC_Decode, 192, 14, 186, 2, // 1948: decode to PSTXVP using decoder 314
9809 // 1948: }
9810 132, 2, 0, // 1953: case 0x104: {
9811 OPC_CheckField, 26, 1, 0, // 1956: check Inst[26] == 0x0
9812 OPC_Decode, 195, 14, 187, 2, // 1960: decode to PSTXVPpc using decoder 315
9813 // 1960: }
9814 // 1960: } // switch Inst[63:50]
9815 // 1960: }
9816 // 1960: } // switch Inst[31:27]
9817};
9818// Handling 330 cases.
9819template <typename InsnType>
9820static DecodeStatus decodeToMCInst(unsigned Idx, DecodeStatus S, InsnType insn, MCInst &MI, uint64_t Address, const MCDisassembler *Decoder, bool &DecodeComplete) {
9821 DecodeComplete = true;
9822 using TmpType = std::conditional_t<std::is_integral<InsnType>::value, InsnType, uint64_t>;
9823 TmpType tmp;
9824 switch (Idx) {
9825 default: llvm_unreachable("Invalid decoder index!");
9826 case 0:
9827 return S;
9828 case 1:
9829 tmp = fieldFromInstruction(insn, 21, 5);
9830 if (!Check(S, decodeUImmOperand<5>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
9831 tmp = fieldFromInstruction(insn, 16, 5);
9832 if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
9833 tmp = fieldFromInstruction(insn, 0, 16);
9834 if (!Check(S, decodeSImmOperand<16>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
9835 return S;
9836 case 2:
9837 tmp = fieldFromInstruction(insn, 21, 5);
9838 if (!Check(S, decodeUImmOperand<5>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
9839 tmp = fieldFromInstruction(insn, 16, 5);
9840 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
9841 tmp = fieldFromInstruction(insn, 0, 16);
9842 if (!Check(S, decodeSImmOperand<16>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
9843 return S;
9844 case 3:
9845 tmp = fieldFromInstruction(insn, 21, 5);
9846 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
9847 tmp = fieldFromInstruction(insn, 16, 5);
9848 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
9849 tmp = fieldFromInstruction(insn, 11, 5);
9850 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
9851 return S;
9852 case 4:
9853 tmp = fieldFromInstruction(insn, 21, 5);
9854 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
9855 tmp = fieldFromInstruction(insn, 16, 5);
9856 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
9857 return S;
9858 case 5:
9859 tmp = fieldFromInstruction(insn, 21, 5);
9860 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
9861 tmp = fieldFromInstruction(insn, 16, 5);
9862 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
9863 tmp = fieldFromInstruction(insn, 11, 5);
9864 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
9865 tmp = fieldFromInstruction(insn, 9, 1);
9866 if (!Check(S, decodeUImmOperand<1>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
9867 return S;
9868 case 6:
9869 tmp = fieldFromInstruction(insn, 23, 3);
9870 if (!Check(S, DecodeCRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
9871 tmp = fieldFromInstruction(insn, 16, 5);
9872 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
9873 tmp = fieldFromInstruction(insn, 11, 5);
9874 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
9875 return S;
9876 case 7:
9877 tmp = fieldFromInstruction(insn, 21, 5);
9878 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
9879 tmp = fieldFromInstruction(insn, 11, 5);
9880 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
9881 return S;
9882 case 8:
9883 tmp = fieldFromInstruction(insn, 21, 5);
9884 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
9885 tmp = fieldFromInstruction(insn, 11, 5);
9886 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
9887 tmp = fieldFromInstruction(insn, 9, 1);
9888 if (!Check(S, decodeUImmOperand<1>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
9889 return S;
9890 case 9:
9891 tmp = fieldFromInstruction(insn, 21, 5);
9892 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
9893 tmp = fieldFromInstruction(insn, 11, 5);
9894 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
9895 tmp = fieldFromInstruction(insn, 16, 1);
9896 if (!Check(S, decodeUImmOperand<1>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
9897 return S;
9898 case 10:
9899 tmp = fieldFromInstruction(insn, 21, 5);
9900 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
9901 tmp = fieldFromInstruction(insn, 11, 5);
9902 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
9903 tmp = fieldFromInstruction(insn, 16, 2);
9904 if (!Check(S, decodeUImmOperand<2>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
9905 return S;
9906 case 11:
9907 tmp = fieldFromInstruction(insn, 21, 5);
9908 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
9909 tmp = fieldFromInstruction(insn, 11, 5);
9910 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
9911 tmp = fieldFromInstruction(insn, 16, 3);
9912 if (!Check(S, decodeUImmOperand<3>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
9913 return S;
9914 case 12:
9915 tmp = fieldFromInstruction(insn, 21, 5);
9916 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
9917 tmp = fieldFromInstruction(insn, 11, 5);
9918 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
9919 return S;
9920 case 13:
9921 tmp = fieldFromInstruction(insn, 21, 5);
9922 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
9923 tmp = fieldFromInstruction(insn, 11, 5);
9924 if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
9925 return S;
9926 case 14:
9927 tmp = fieldFromInstruction(insn, 21, 5);
9928 if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
9929 tmp = fieldFromInstruction(insn, 11, 5);
9930 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
9931 tmp = fieldFromInstruction(insn, 16, 1);
9932 if (!Check(S, decodeUImmOperand<1>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
9933 return S;
9934 case 15:
9935 tmp = fieldFromInstruction(insn, 21, 5);
9936 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
9937 tmp = fieldFromInstruction(insn, 16, 5);
9938 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
9939 tmp = fieldFromInstruction(insn, 15, 1);
9940 if (!Check(S, decodeUImmOperand<1>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
9941 tmp = fieldFromInstruction(insn, 11, 4);
9942 if (!Check(S, decodeUImmOperand<4>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
9943 return S;
9944 case 16:
9945 tmp = fieldFromInstruction(insn, 21, 5);
9946 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
9947 tmp = fieldFromInstruction(insn, 16, 5);
9948 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
9949 tmp = fieldFromInstruction(insn, 11, 5);
9950 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
9951 tmp = fieldFromInstruction(insn, 21, 5);
9952 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
9953 return S;
9954 case 17:
9955 tmp = fieldFromInstruction(insn, 21, 5);
9956 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
9957 return S;
9958 case 18:
9959 tmp = fieldFromInstruction(insn, 11, 5);
9960 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
9961 return S;
9962 case 19:
9963 tmp = fieldFromInstruction(insn, 21, 5);
9964 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
9965 tmp = fieldFromInstruction(insn, 16, 5);
9966 if (!Check(S, decodeUImmOperand<5>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
9967 tmp = fieldFromInstruction(insn, 11, 5);
9968 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
9969 return S;
9970 case 20:
9971 tmp = fieldFromInstruction(insn, 21, 5);
9972 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
9973 tmp = fieldFromInstruction(insn, 16, 5);
9974 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
9975 tmp = fieldFromInstruction(insn, 11, 5);
9976 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
9977 return S;
9978 case 21:
9979 tmp = fieldFromInstruction(insn, 21, 5);
9980 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
9981 tmp = fieldFromInstruction(insn, 16, 5);
9982 if (!Check(S, decodeUImmOperand<4>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
9983 tmp = fieldFromInstruction(insn, 11, 5);
9984 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
9985 return S;
9986 case 22:
9987 tmp = fieldFromInstruction(insn, 21, 5);
9988 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
9989 tmp = fieldFromInstruction(insn, 16, 5);
9990 if (!Check(S, decodeSImmOperand<5>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
9991 return S;
9992 case 23:
9993 tmp = fieldFromInstruction(insn, 21, 5);
9994 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
9995 tmp = fieldFromInstruction(insn, 21, 5);
9996 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
9997 tmp = fieldFromInstruction(insn, 16, 5);
9998 if (!Check(S, decodeUImmOperand<4>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
9999 tmp = fieldFromInstruction(insn, 11, 5);
10000 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10001 return S;
10002 case 24:
10003 tmp = fieldFromInstruction(insn, 21, 5);
10004 if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10005 tmp = fieldFromInstruction(insn, 11, 5);
10006 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10007 tmp = fieldFromInstruction(insn, 16, 3);
10008 if (!Check(S, decodeUImmOperand<3>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10009 return S;
10010 case 25:
10011 tmp = fieldFromInstruction(insn, 21, 5);
10012 if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10013 tmp = fieldFromInstruction(insn, 16, 5);
10014 if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10015 tmp = fieldFromInstruction(insn, 11, 5);
10016 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10017 return S;
10018 case 26:
10019 tmp = fieldFromInstruction(insn, 21, 5);
10020 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10021 tmp = fieldFromInstruction(insn, 21, 5);
10022 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10023 tmp = fieldFromInstruction(insn, 16, 5);
10024 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10025 tmp = fieldFromInstruction(insn, 11, 5);
10026 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10027 return S;
10028 case 27:
10029 tmp = fieldFromInstruction(insn, 21, 5);
10030 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10031 tmp = fieldFromInstruction(insn, 21, 5);
10032 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10033 tmp = fieldFromInstruction(insn, 16, 5);
10034 if (!Check(S, decodeUImmOperand<4>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10035 tmp = fieldFromInstruction(insn, 11, 5);
10036 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10037 return S;
10038 case 28:
10039 tmp = fieldFromInstruction(insn, 21, 5);
10040 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10041 tmp = fieldFromInstruction(insn, 21, 5);
10042 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10043 tmp = fieldFromInstruction(insn, 16, 5);
10044 if (!Check(S, decodeUImmOperand<4>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10045 tmp = fieldFromInstruction(insn, 11, 5);
10046 if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10047 return S;
10048 case 29:
10049 tmp = fieldFromInstruction(insn, 21, 5);
10050 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10051 tmp = fieldFromInstruction(insn, 21, 5);
10052 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10053 tmp = fieldFromInstruction(insn, 16, 5);
10054 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10055 tmp = fieldFromInstruction(insn, 11, 5);
10056 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10057 return S;
10058 case 30:
10059 tmp = fieldFromInstruction(insn, 21, 5);
10060 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10061 tmp = fieldFromInstruction(insn, 21, 5);
10062 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10063 tmp = fieldFromInstruction(insn, 16, 5);
10064 if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10065 tmp = fieldFromInstruction(insn, 11, 5);
10066 if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10067 return S;
10068 case 31:
10069 tmp = fieldFromInstruction(insn, 21, 5);
10070 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10071 tmp = 0x0;
10072 tmp |= fieldFromInstruction(insn, 0, 1);
10073 tmp |= fieldFromInstruction(insn, 6, 10) << 6;
10074 tmp |= fieldFromInstruction(insn, 16, 5) << 1;
10075 if (!Check(S, decodeUImmOperand<16>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10076 return S;
10077 case 32:
10078 tmp = fieldFromInstruction(insn, 21, 5);
10079 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10080 tmp = fieldFromInstruction(insn, 16, 5);
10081 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10082 tmp = fieldFromInstruction(insn, 11, 5);
10083 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10084 tmp = fieldFromInstruction(insn, 6, 3);
10085 if (!Check(S, decodeUImmOperand<3>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10086 return S;
10087 case 33:
10088 tmp = fieldFromInstruction(insn, 21, 5);
10089 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10090 tmp = fieldFromInstruction(insn, 16, 5);
10091 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10092 tmp = fieldFromInstruction(insn, 11, 5);
10093 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10094 tmp = fieldFromInstruction(insn, 6, 5);
10095 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10096 return S;
10097 case 34:
10098 tmp = fieldFromInstruction(insn, 21, 5);
10099 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10100 tmp = fieldFromInstruction(insn, 16, 5);
10101 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10102 tmp = fieldFromInstruction(insn, 11, 5);
10103 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10104 tmp = fieldFromInstruction(insn, 6, 5);
10105 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10106 return S;
10107 case 35:
10108 tmp = fieldFromInstruction(insn, 21, 5);
10109 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10110 tmp = fieldFromInstruction(insn, 16, 5);
10111 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10112 tmp = fieldFromInstruction(insn, 11, 5);
10113 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10114 tmp = fieldFromInstruction(insn, 6, 4);
10115 if (!Check(S, decodeUImmOperand<4>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10116 return S;
10117 case 36:
10118 tmp = fieldFromInstruction(insn, 21, 5);
10119 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10120 tmp = fieldFromInstruction(insn, 16, 5);
10121 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10122 tmp = fieldFromInstruction(insn, 6, 5);
10123 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10124 tmp = fieldFromInstruction(insn, 11, 5);
10125 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10126 return S;
10127 case 37:
10128 tmp = fieldFromInstruction(insn, 21, 5);
10129 if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10130 tmp = fieldFromInstruction(insn, 16, 5);
10131 if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10132 tmp = fieldFromInstruction(insn, 11, 5);
10133 if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10134 tmp = fieldFromInstruction(insn, 6, 5);
10135 if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10136 return S;
10137 case 38:
10138 tmp = fieldFromInstruction(insn, 21, 5);
10139 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10140 tmp = fieldFromInstruction(insn, 16, 5);
10141 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10142 tmp = fieldFromInstruction(insn, 11, 5);
10143 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10144 tmp = fieldFromInstruction(insn, 6, 5);
10145 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10146 return S;
10147 case 39:
10148 tmp = 0x0;
10149 tmp |= fieldFromInstruction(insn, 21, 1) << 4;
10150 tmp |= fieldFromInstruction(insn, 22, 4);
10151 if (!Check(S, DecodeVSRpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10152 tmp = fieldFromInstruction(insn, 4, 12);
10153 if (!Check(S, decodeDispRIX16Operand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10154 tmp = fieldFromInstruction(insn, 16, 5);
10155 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10156 return S;
10157 case 40:
10158 tmp = fieldFromInstruction(insn, 21, 5);
10159 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10160 tmp = fieldFromInstruction(insn, 16, 5);
10161 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10162 tmp = fieldFromInstruction(insn, 0, 16);
10163 if (!Check(S, decodeSImmOperand<16>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10164 return S;
10165 case 41:
10166 tmp = fieldFromInstruction(insn, 23, 3);
10167 if (!Check(S, DecodeCRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10168 tmp = fieldFromInstruction(insn, 16, 5);
10169 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10170 tmp = fieldFromInstruction(insn, 0, 16);
10171 if (!Check(S, decodeUImmOperand<16>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10172 return S;
10173 case 42:
10174 tmp = fieldFromInstruction(insn, 23, 3);
10175 if (!Check(S, DecodeCRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10176 tmp = fieldFromInstruction(insn, 16, 5);
10177 if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10178 tmp = fieldFromInstruction(insn, 0, 16);
10179 if (!Check(S, decodeUImmOperand<16>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10180 return S;
10181 case 43:
10182 tmp = fieldFromInstruction(insn, 23, 3);
10183 if (!Check(S, DecodeCRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10184 tmp = fieldFromInstruction(insn, 16, 5);
10185 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10186 tmp = fieldFromInstruction(insn, 0, 16);
10187 if (!Check(S, decodeSImmOperand<16>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10188 return S;
10189 case 44:
10190 tmp = fieldFromInstruction(insn, 23, 3);
10191 if (!Check(S, DecodeCRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10192 tmp = fieldFromInstruction(insn, 16, 5);
10193 if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10194 tmp = fieldFromInstruction(insn, 0, 16);
10195 if (!Check(S, decodeSImmOperand<16>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10196 return S;
10197 case 45:
10198 tmp = fieldFromInstruction(insn, 21, 5);
10199 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10200 tmp = fieldFromInstruction(insn, 0, 16);
10201 if (!Check(S, decodeSImmOperand<16>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10202 return S;
10203 case 46:
10204 tmp = fieldFromInstruction(insn, 21, 5);
10205 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10206 tmp = fieldFromInstruction(insn, 16, 5);
10207 if (!Check(S, DecodeGPRC_NOR0RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10208 tmp = fieldFromInstruction(insn, 0, 16);
10209 if (!Check(S, decodeSImmOperand<16>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10210 return S;
10211 case 47:
10212 tmp = fieldFromInstruction(insn, 2, 14);
10213 if (!Check(S, decodeCondBrTarget(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10214 return S;
10215 case 48:
10216 tmp = fieldFromInstruction(insn, 21, 5);
10217 if (!Check(S, decodeUImmOperand<5>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10218 tmp = fieldFromInstruction(insn, 16, 5);
10219 if (!Check(S, DecodeCRBITRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10220 tmp = fieldFromInstruction(insn, 2, 14);
10221 if (!Check(S, decodeCondBrTarget(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10222 return S;
10223 case 49:
10224 tmp = fieldFromInstruction(insn, 5, 7);
10225 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
10226 return S;
10227 case 50:
10228 tmp = fieldFromInstruction(insn, 2, 24);
10229 if (!Check(S, decodeDirectBrTarget(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10230 return S;
10231 case 51:
10232 tmp = fieldFromInstruction(insn, 23, 3);
10233 if (!Check(S, DecodeCRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10234 tmp = fieldFromInstruction(insn, 18, 3);
10235 if (!Check(S, DecodeCRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10236 return S;
10237 case 52:
10238 tmp = fieldFromInstruction(insn, 21, 5);
10239 if (!Check(S, DecodeCRBITRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10240 tmp = fieldFromInstruction(insn, 16, 5);
10241 if (!Check(S, DecodeCRBITRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10242 tmp = fieldFromInstruction(insn, 11, 5);
10243 if (!Check(S, DecodeCRBITRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10244 return S;
10245 case 53:
10246 tmp = fieldFromInstruction(insn, 21, 5);
10247 if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10248 tmp = 0x0;
10249 tmp |= fieldFromInstruction(insn, 0, 1);
10250 tmp |= fieldFromInstruction(insn, 6, 10) << 6;
10251 tmp |= fieldFromInstruction(insn, 16, 5) << 1;
10252 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
10253 return S;
10254 case 54:
10255 tmp = fieldFromInstruction(insn, 21, 5);
10256 if (!Check(S, decodeUImmOperand<5>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10257 tmp = fieldFromInstruction(insn, 16, 5);
10258 if (!Check(S, DecodeCRBITRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10259 tmp = fieldFromInstruction(insn, 11, 2);
10260 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
10261 return S;
10262 case 55:
10263 tmp = fieldFromInstruction(insn, 11, 1);
10264 if (!Check(S, decodeUImmOperand<1>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10265 return S;
10266 case 56:
10267 tmp = fieldFromInstruction(insn, 16, 5);
10268 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10269 tmp = fieldFromInstruction(insn, 16, 5);
10270 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10271 tmp = fieldFromInstruction(insn, 21, 5);
10272 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10273 tmp = fieldFromInstruction(insn, 11, 5);
10274 if (!Check(S, decodeUImmOperand<5>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10275 tmp = fieldFromInstruction(insn, 6, 5);
10276 if (!Check(S, decodeUImmOperand<5>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10277 tmp = fieldFromInstruction(insn, 1, 5);
10278 if (!Check(S, decodeUImmOperand<5>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10279 return S;
10280 case 57:
10281 tmp = fieldFromInstruction(insn, 16, 5);
10282 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10283 tmp = fieldFromInstruction(insn, 21, 5);
10284 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10285 tmp = fieldFromInstruction(insn, 11, 5);
10286 if (!Check(S, decodeUImmOperand<5>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10287 tmp = fieldFromInstruction(insn, 6, 5);
10288 if (!Check(S, decodeUImmOperand<5>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10289 tmp = fieldFromInstruction(insn, 1, 5);
10290 if (!Check(S, decodeUImmOperand<5>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10291 return S;
10292 case 58:
10293 tmp = fieldFromInstruction(insn, 16, 5);
10294 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10295 tmp = fieldFromInstruction(insn, 21, 5);
10296 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10297 tmp = fieldFromInstruction(insn, 11, 5);
10298 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10299 tmp = fieldFromInstruction(insn, 6, 5);
10300 if (!Check(S, decodeUImmOperand<5>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10301 tmp = fieldFromInstruction(insn, 1, 5);
10302 if (!Check(S, decodeUImmOperand<5>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10303 return S;
10304 case 59:
10305 tmp = fieldFromInstruction(insn, 16, 5);
10306 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10307 tmp = fieldFromInstruction(insn, 21, 5);
10308 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10309 tmp = fieldFromInstruction(insn, 0, 16);
10310 if (!Check(S, decodeUImmOperand<16>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10311 return S;
10312 case 60:
10313 tmp = fieldFromInstruction(insn, 16, 5);
10314 if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10315 tmp = fieldFromInstruction(insn, 21, 5);
10316 if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10317 tmp = 0x0;
10318 tmp |= fieldFromInstruction(insn, 1, 1) << 5;
10319 tmp |= fieldFromInstruction(insn, 11, 5);
10320 if (!Check(S, decodeUImmOperand<6>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10321 tmp = 0x0;
10322 tmp |= fieldFromInstruction(insn, 5, 1) << 5;
10323 tmp |= fieldFromInstruction(insn, 6, 5);
10324 if (!Check(S, decodeUImmOperand<6>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10325 return S;
10326 case 61:
10327 tmp = fieldFromInstruction(insn, 16, 5);
10328 if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10329 tmp = fieldFromInstruction(insn, 16, 5);
10330 if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10331 tmp = fieldFromInstruction(insn, 21, 5);
10332 if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10333 tmp = 0x0;
10334 tmp |= fieldFromInstruction(insn, 1, 1) << 5;
10335 tmp |= fieldFromInstruction(insn, 11, 5);
10336 if (!Check(S, decodeUImmOperand<6>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10337 tmp = 0x0;
10338 tmp |= fieldFromInstruction(insn, 5, 1) << 5;
10339 tmp |= fieldFromInstruction(insn, 6, 5);
10340 if (!Check(S, decodeUImmOperand<6>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10341 return S;
10342 case 62:
10343 tmp = fieldFromInstruction(insn, 16, 5);
10344 if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10345 tmp = fieldFromInstruction(insn, 21, 5);
10346 if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10347 tmp = fieldFromInstruction(insn, 11, 5);
10348 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10349 tmp = 0x0;
10350 tmp |= fieldFromInstruction(insn, 5, 1) << 5;
10351 tmp |= fieldFromInstruction(insn, 6, 5);
10352 if (!Check(S, decodeUImmOperand<6>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10353 return S;
10354 case 63:
10355 tmp = fieldFromInstruction(insn, 23, 3);
10356 if (!Check(S, DecodeCRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10357 tmp = fieldFromInstruction(insn, 16, 5);
10358 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10359 tmp = fieldFromInstruction(insn, 11, 5);
10360 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10361 return S;
10362 case 64:
10363 tmp = fieldFromInstruction(insn, 23, 3);
10364 if (!Check(S, DecodeCRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10365 tmp = fieldFromInstruction(insn, 16, 5);
10366 if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10367 tmp = fieldFromInstruction(insn, 11, 5);
10368 if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10369 return S;
10370 case 65:
10371 tmp = fieldFromInstruction(insn, 21, 5);
10372 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10373 tmp = fieldFromInstruction(insn, 18, 3);
10374 if (!Check(S, DecodeCRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10375 return S;
10376 case 66:
10377 tmp = fieldFromInstruction(insn, 23, 3);
10378 if (!Check(S, DecodeCRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10379 tmp = fieldFromInstruction(insn, 21, 1);
10380 if (!Check(S, decodeUImmOperand<1>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10381 tmp = fieldFromInstruction(insn, 16, 5);
10382 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10383 tmp = fieldFromInstruction(insn, 11, 5);
10384 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10385 return S;
10386 case 67:
10387 tmp = fieldFromInstruction(insn, 21, 5);
10388 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10389 tmp = fieldFromInstruction(insn, 16, 5);
10390 if (!Check(S, DecodeCRBITRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10391 return S;
10392 case 68:
10393 tmp = fieldFromInstruction(insn, 23, 3);
10394 if (!Check(S, DecodeCRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10395 return S;
10396 case 69:
10397 tmp = fieldFromInstruction(insn, 21, 5);
10398 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10399 return S;
10400 case 70:
10401 tmp = fieldFromInstruction(insn, 15, 1);
10402 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
10403 return S;
10404 case 71:
10405 tmp = fieldFromInstruction(insn, 21, 5);
10406 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10407 tmp = 0x0;
10408 tmp |= fieldFromInstruction(insn, 11, 5) << 5;
10409 tmp |= fieldFromInstruction(insn, 16, 5);
10410 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
10411 return S;
10412 case 72:
10413 tmp = fieldFromInstruction(insn, 21, 5);
10414 if (!Check(S, decodeUImmOperand<5>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10415 tmp = fieldFromInstruction(insn, 16, 5);
10416 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10417 tmp = fieldFromInstruction(insn, 11, 5);
10418 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10419 return S;
10420 case 73:
10421 tmp = fieldFromInstruction(insn, 21, 5);
10422 if (!Check(S, decodeUImmOperand<5>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10423 tmp = fieldFromInstruction(insn, 16, 5);
10424 if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10425 tmp = fieldFromInstruction(insn, 11, 5);
10426 if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10427 return S;
10428 case 74:
10429 tmp = fieldFromInstruction(insn, 21, 5);
10430 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10431 tmp = fieldFromInstruction(insn, 16, 5);
10432 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10433 tmp = fieldFromInstruction(insn, 11, 5);
10434 if (!Check(S, Decodeptr_rc_idx_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10435 return S;
10436 case 75:
10437 tmp = fieldFromInstruction(insn, 21, 4);
10438 if (!Check(S, decodeUImmOperand<4>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10439 tmp = fieldFromInstruction(insn, 16, 5);
10440 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10441 tmp = fieldFromInstruction(insn, 11, 5);
10442 if (!Check(S, Decodeptr_rc_idx_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10443 return S;
10444 case 76:
10445 tmp = fieldFromInstruction(insn, 16, 5);
10446 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10447 tmp = fieldFromInstruction(insn, 11, 5);
10448 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10449 return S;
10450 case 77:
10451 tmp = fieldFromInstruction(insn, 21, 5);
10452 if (!Check(S, DecodeG8pRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10453 tmp = fieldFromInstruction(insn, 21, 5);
10454 if (!Check(S, DecodeG8pRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10455 tmp = fieldFromInstruction(insn, 16, 5);
10456 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10457 tmp = fieldFromInstruction(insn, 11, 5);
10458 if (!Check(S, decodeUImmOperand<5>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10459 return S;
10460 case 78:
10461 tmp = fieldFromInstruction(insn, 21, 5);
10462 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10463 tmp = fieldFromInstruction(insn, 16, 5);
10464 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10465 tmp = fieldFromInstruction(insn, 11, 5);
10466 if (!Check(S, decodeUImmOperand<5>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10467 return S;
10468 case 79:
10469 tmp = fieldFromInstruction(insn, 21, 5);
10470 if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10471 tmp = fieldFromInstruction(insn, 16, 5);
10472 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10473 tmp = fieldFromInstruction(insn, 11, 5);
10474 if (!Check(S, decodeUImmOperand<5>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10475 return S;
10476 case 80:
10477 tmp = fieldFromInstruction(insn, 16, 5);
10478 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10479 tmp = fieldFromInstruction(insn, 11, 5);
10480 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10481 tmp = fieldFromInstruction(insn, 21, 1);
10482 if (!Check(S, decodeUImmOperand<1>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10483 return S;
10484 case 81:
10485 tmp = fieldFromInstruction(insn, 21, 5);
10486 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10487 tmp = fieldFromInstruction(insn, 16, 5);
10488 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10489 tmp = fieldFromInstruction(insn, 11, 5);
10490 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10491 return S;
10492 case 82:
10493 tmp = fieldFromInstruction(insn, 21, 5);
10494 if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10495 tmp = fieldFromInstruction(insn, 16, 5);
10496 if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10497 tmp = fieldFromInstruction(insn, 11, 5);
10498 if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10499 return S;
10500 case 83:
10501 tmp = fieldFromInstruction(insn, 21, 5);
10502 if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10503 tmp = fieldFromInstruction(insn, 16, 5);
10504 if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10505 tmp = fieldFromInstruction(insn, 11, 5);
10506 if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10507 tmp = fieldFromInstruction(insn, 10, 1);
10508 if (!Check(S, decodeUImmOperand<1>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10509 return S;
10510 case 84:
10511 tmp = fieldFromInstruction(insn, 21, 5);
10512 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10513 tmp = fieldFromInstruction(insn, 16, 5);
10514 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10515 return S;
10516 case 85:
10517 tmp = fieldFromInstruction(insn, 21, 5);
10518 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10519 tmp = fieldFromInstruction(insn, 16, 5);
10520 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10521 tmp = fieldFromInstruction(insn, 11, 5);
10522 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10523 tmp = fieldFromInstruction(insn, 9, 2);
10524 if (!Check(S, decodeUImmOperand<2>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10525 return S;
10526 case 86:
10527 tmp = 0x0;
10528 tmp |= fieldFromInstruction(insn, 0, 1) << 5;
10529 tmp |= fieldFromInstruction(insn, 21, 5);
10530 if (!Check(S, DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10531 tmp = fieldFromInstruction(insn, 16, 5);
10532 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10533 tmp = fieldFromInstruction(insn, 11, 5);
10534 if (!Check(S, Decodeptr_rc_idx_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10535 return S;
10536 case 87:
10537 tmp = 0x0;
10538 tmp |= fieldFromInstruction(insn, 0, 1) << 5;
10539 tmp |= fieldFromInstruction(insn, 21, 5);
10540 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10541 tmp = fieldFromInstruction(insn, 16, 5);
10542 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10543 tmp = fieldFromInstruction(insn, 11, 5);
10544 if (!Check(S, Decodeptr_rc_idx_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10545 return S;
10546 case 88:
10547 tmp = 0x0;
10548 tmp |= fieldFromInstruction(insn, 0, 1) << 5;
10549 tmp |= fieldFromInstruction(insn, 21, 5);
10550 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10551 tmp = fieldFromInstruction(insn, 16, 5);
10552 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10553 tmp = fieldFromInstruction(insn, 11, 5);
10554 if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10555 return S;
10556 case 89:
10557 tmp = 0x0;
10558 tmp |= fieldFromInstruction(insn, 21, 1) << 4;
10559 tmp |= fieldFromInstruction(insn, 22, 4);
10560 if (!Check(S, DecodeVSRpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10561 tmp = fieldFromInstruction(insn, 16, 5);
10562 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10563 tmp = fieldFromInstruction(insn, 11, 5);
10564 if (!Check(S, Decodeptr_rc_idx_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10565 return S;
10566 case 90:
10567 tmp = 0x0;
10568 tmp |= fieldFromInstruction(insn, 0, 1) << 5;
10569 tmp |= fieldFromInstruction(insn, 21, 5);
10570 if (!Check(S, DecodeVSSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10571 tmp = fieldFromInstruction(insn, 16, 5);
10572 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10573 tmp = fieldFromInstruction(insn, 11, 5);
10574 if (!Check(S, Decodeptr_rc_idx_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10575 return S;
10576 case 91:
10577 tmp = 0x0;
10578 tmp |= fieldFromInstruction(insn, 21, 1) << 4;
10579 tmp |= fieldFromInstruction(insn, 22, 4);
10580 if (!Check(S, DecodeVSRpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10581 tmp = fieldFromInstruction(insn, 16, 5);
10582 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10583 tmp = fieldFromInstruction(insn, 11, 5);
10584 if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10585 return S;
10586 case 92:
10587 tmp = fieldFromInstruction(insn, 21, 5);
10588 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10589 tmp = fieldFromInstruction(insn, 11, 10);
10590 if (!Check(S, decodeUImmOperand<10>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10591 return S;
10592 case 93:
10593 tmp = 0x0;
10594 tmp |= fieldFromInstruction(insn, 11, 5) << 5;
10595 tmp |= fieldFromInstruction(insn, 16, 5);
10596 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
10597 tmp = fieldFromInstruction(insn, 21, 5);
10598 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10599 return S;
10600 case 94:
10601 tmp = fieldFromInstruction(insn, 21, 1);
10602 if (!Check(S, decodeUImmOperand<1>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10603 return S;
10604 case 95:
10605 tmp = fieldFromInstruction(insn, 25, 1);
10606 if (!Check(S, decodeUImmOperand<1>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10607 return S;
10608 case 96:
10609 tmp = fieldFromInstruction(insn, 21, 5);
10610 if (!Check(S, decodeUImmOperand<5>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10611 tmp = fieldFromInstruction(insn, 16, 5);
10612 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10613 tmp = fieldFromInstruction(insn, 11, 5);
10614 if (!Check(S, decodeUImmOperand<5>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10615 return S;
10616 case 97:
10617 tmp = fieldFromInstruction(insn, 16, 5);
10618 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10619 return S;
10620 case 98:
10621 tmp = fieldFromInstruction(insn, 21, 5);
10622 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10623 tmp = fieldFromInstruction(insn, 16, 5);
10624 if (!Check(S, DecodeGPRC_NOR0RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10625 tmp = fieldFromInstruction(insn, 11, 5);
10626 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10627 tmp = fieldFromInstruction(insn, 6, 5);
10628 if (!Check(S, DecodeCRBITRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10629 return S;
10630 case 99:
10631 tmp = fieldFromInstruction(insn, 12, 8);
10632 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
10633 tmp = fieldFromInstruction(insn, 21, 5);
10634 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10635 return S;
10636 case 100:
10637 tmp = fieldFromInstruction(insn, 12, 8);
10638 if (!Check(S, decodeCRBitMOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10639 tmp = fieldFromInstruction(insn, 21, 5);
10640 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10641 return S;
10642 case 101:
10643 tmp = fieldFromInstruction(insn, 23, 3);
10644 if (!Check(S, DecodeACCRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10645 tmp = fieldFromInstruction(insn, 23, 3);
10646 if (!Check(S, DecodeACCRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10647 return S;
10648 case 102:
10649 tmp = fieldFromInstruction(insn, 23, 3);
10650 if (!Check(S, DecodeDMRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10651 return S;
10652 case 103:
10653 tmp = fieldFromInstruction(insn, 23, 3);
10654 if (!Check(S, DecodeACCRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10655 return S;
10656 case 104:
10657 tmp = fieldFromInstruction(insn, 23, 3);
10658 if (!Check(S, DecodeDMRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10659 tmp = fieldFromInstruction(insn, 13, 3);
10660 if (!Check(S, DecodeDMRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10661 return S;
10662 case 105:
10663 tmp = fieldFromInstruction(insn, 23, 3);
10664 if (!Check(S, DecodeDMRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10665 tmp = fieldFromInstruction(insn, 23, 3);
10666 if (!Check(S, DecodeDMRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10667 tmp = fieldFromInstruction(insn, 13, 3);
10668 if (!Check(S, DecodeDMRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10669 return S;
10670 case 106:
10671 tmp = fieldFromInstruction(insn, 23, 3);
10672 if (!Check(S, DecodeDMRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10673 tmp = fieldFromInstruction(insn, 23, 3);
10674 if (!Check(S, DecodeDMRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10675 tmp = fieldFromInstruction(insn, 13, 3);
10676 if (!Check(S, DecodeDMRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10677 tmp = fieldFromInstruction(insn, 21, 1);
10678 if (!Check(S, decodeUImmOperand<1>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10679 return S;
10680 case 107:
10681 tmp = fieldFromInstruction(insn, 24, 2);
10682 if (!Check(S, DecodeDMRpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10683 tmp = fieldFromInstruction(insn, 24, 2);
10684 if (!Check(S, DecodeDMRpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10685 tmp = fieldFromInstruction(insn, 11, 5);
10686 if (!Check(S, decodeUImmOperand<5>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10687 return S;
10688 case 108:
10689 tmp = fieldFromInstruction(insn, 11, 5);
10690 if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10691 tmp = fieldFromInstruction(insn, 21, 5);
10692 if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10693 tmp = fieldFromInstruction(insn, 18, 2);
10694 if (!Check(S, decodeUImmOperand<2>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10695 return S;
10696 case 109:
10697 tmp = fieldFromInstruction(insn, 21, 5);
10698 if (!Check(S, decodeUImmOperand<2>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10699 tmp = fieldFromInstruction(insn, 16, 5);
10700 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10701 tmp = fieldFromInstruction(insn, 11, 5);
10702 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10703 return S;
10704 case 110:
10705 tmp = fieldFromInstruction(insn, 21, 5);
10706 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10707 tmp = fieldFromInstruction(insn, 12, 8);
10708 if (!Check(S, decodeCRBitMOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10709 return S;
10710 case 111:
10711 tmp = fieldFromInstruction(insn, 11, 5);
10712 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10713 tmp = fieldFromInstruction(insn, 21, 5);
10714 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10715 tmp = fieldFromInstruction(insn, 18, 2);
10716 if (!Check(S, decodeUImmOperand<2>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10717 tmp = fieldFromInstruction(insn, 17, 1);
10718 if (!Check(S, decodeUImmOperand<1>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10719 tmp = fieldFromInstruction(insn, 16, 1);
10720 if (!Check(S, decodeUImmOperand<1>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10721 return S;
10722 case 112:
10723 tmp = fieldFromInstruction(insn, 16, 5);
10724 if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10725 tmp = 0x0;
10726 tmp |= fieldFromInstruction(insn, 0, 1) << 5;
10727 tmp |= fieldFromInstruction(insn, 21, 5);
10728 if (!Check(S, DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10729 return S;
10730 case 113:
10731 tmp = fieldFromInstruction(insn, 16, 5);
10732 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10733 tmp = 0x0;
10734 tmp |= fieldFromInstruction(insn, 0, 1) << 5;
10735 tmp |= fieldFromInstruction(insn, 21, 5);
10736 if (!Check(S, DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10737 return S;
10738 case 114:
10739 tmp = fieldFromInstruction(insn, 21, 5);
10740 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10741 tmp = fieldFromInstruction(insn, 16, 1);
10742 if (!Check(S, decodeUImmOperand<1>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10743 return S;
10744 case 115:
10745 tmp = 0x0;
10746 tmp |= fieldFromInstruction(insn, 0, 1) << 5;
10747 tmp |= fieldFromInstruction(insn, 21, 5);
10748 if (!Check(S, DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10749 tmp = fieldFromInstruction(insn, 16, 5);
10750 if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10751 return S;
10752 case 116:
10753 tmp = fieldFromInstruction(insn, 21, 5);
10754 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10755 tmp = fieldFromInstruction(insn, 16, 4);
10756 if (!Check(S, decodeUImmOperand<4>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10757 return S;
10758 case 117:
10759 tmp = 0x0;
10760 tmp |= fieldFromInstruction(insn, 0, 1) << 5;
10761 tmp |= fieldFromInstruction(insn, 21, 5);
10762 if (!Check(S, DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10763 tmp = fieldFromInstruction(insn, 16, 5);
10764 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10765 return S;
10766 case 118:
10767 tmp = fieldFromInstruction(insn, 21, 5);
10768 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10769 tmp = fieldFromInstruction(insn, 11, 5);
10770 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10771 return S;
10772 case 119:
10773 tmp = fieldFromInstruction(insn, 11, 5);
10774 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10775 return S;
10776 case 120:
10777 tmp = fieldFromInstruction(insn, 11, 5);
10778 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10779 tmp = fieldFromInstruction(insn, 21, 5);
10780 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10781 return S;
10782 case 121:
10783 tmp = fieldFromInstruction(insn, 16, 5);
10784 if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10785 tmp = 0x0;
10786 tmp |= fieldFromInstruction(insn, 0, 1) << 5;
10787 tmp |= fieldFromInstruction(insn, 21, 5);
10788 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10789 return S;
10790 case 122:
10791 tmp = 0x0;
10792 tmp |= fieldFromInstruction(insn, 0, 1) << 5;
10793 tmp |= fieldFromInstruction(insn, 21, 5);
10794 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10795 tmp = fieldFromInstruction(insn, 16, 5);
10796 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10797 return S;
10798 case 123:
10799 tmp = 0x0;
10800 tmp |= fieldFromInstruction(insn, 0, 1) << 5;
10801 tmp |= fieldFromInstruction(insn, 21, 5);
10802 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10803 tmp = fieldFromInstruction(insn, 16, 5);
10804 if (!Check(S, DecodeG8RC_NOX0RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10805 tmp = fieldFromInstruction(insn, 11, 5);
10806 if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10807 return S;
10808 case 124:
10809 tmp = fieldFromInstruction(insn, 11, 5);
10810 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10811 tmp = 0x0;
10812 tmp |= fieldFromInstruction(insn, 0, 1) << 5;
10813 tmp |= fieldFromInstruction(insn, 21, 5);
10814 if (!Check(S, decodeDispRIHashOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10815 tmp = fieldFromInstruction(insn, 16, 5);
10816 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10817 return S;
10818 case 125:
10819 tmp = fieldFromInstruction(insn, 21, 5);
10820 if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10821 tmp = fieldFromInstruction(insn, 16, 2);
10822 if (!Check(S, decodeUImmOperand<2>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10823 return S;
10824 case 126:
10825 tmp = fieldFromInstruction(insn, 21, 5);
10826 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10827 tmp = fieldFromInstruction(insn, 16, 5);
10828 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10829 tmp = fieldFromInstruction(insn, 11, 1);
10830 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
10831 return S;
10832 case 127:
10833 tmp = fieldFromInstruction(insn, 21, 5);
10834 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10835 tmp = fieldFromInstruction(insn, 16, 5);
10836 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10837 tmp = fieldFromInstruction(insn, 11, 5);
10838 if (!Check(S, Decodeptr_rc_idx_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10839 return S;
10840 case 128:
10841 tmp = fieldFromInstruction(insn, 21, 5);
10842 if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10843 tmp = fieldFromInstruction(insn, 16, 5);
10844 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10845 tmp = fieldFromInstruction(insn, 11, 5);
10846 if (!Check(S, Decodeptr_rc_idx_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10847 return S;
10848 case 129:
10849 tmp = fieldFromInstruction(insn, 21, 5);
10850 if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10851 tmp = fieldFromInstruction(insn, 16, 5);
10852 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10853 tmp = fieldFromInstruction(insn, 16, 5);
10854 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10855 tmp = fieldFromInstruction(insn, 11, 5);
10856 if (!Check(S, Decodeptr_rc_idx_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10857 return S;
10858 case 130:
10859 tmp = fieldFromInstruction(insn, 16, 5);
10860 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10861 tmp = fieldFromInstruction(insn, 21, 5);
10862 if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10863 tmp = fieldFromInstruction(insn, 16, 5);
10864 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10865 tmp = fieldFromInstruction(insn, 11, 5);
10866 if (!Check(S, Decodeptr_rc_idx_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10867 return S;
10868 case 131:
10869 tmp = fieldFromInstruction(insn, 21, 5);
10870 if (!Check(S, DecodeG8pRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10871 tmp = fieldFromInstruction(insn, 16, 5);
10872 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10873 tmp = fieldFromInstruction(insn, 11, 5);
10874 if (!Check(S, Decodeptr_rc_idx_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10875 return S;
10876 case 132:
10877 tmp = fieldFromInstruction(insn, 21, 5);
10878 if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10879 return S;
10880 case 133:
10881 tmp = fieldFromInstruction(insn, 21, 5);
10882 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10883 tmp = fieldFromInstruction(insn, 16, 5);
10884 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10885 tmp = fieldFromInstruction(insn, 11, 5);
10886 if (!Check(S, decodeUImmOperand<5>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10887 return S;
10888 case 134:
10889 tmp = fieldFromInstruction(insn, 16, 5);
10890 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10891 tmp = fieldFromInstruction(insn, 11, 5);
10892 if (!Check(S, Decodeptr_rc_idx_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10893 return S;
10894 case 135:
10895 tmp = fieldFromInstruction(insn, 21, 5);
10896 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10897 tmp = fieldFromInstruction(insn, 16, 5);
10898 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10899 tmp = fieldFromInstruction(insn, 16, 5);
10900 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10901 tmp = fieldFromInstruction(insn, 11, 5);
10902 if (!Check(S, Decodeptr_rc_idx_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10903 return S;
10904 case 136:
10905 tmp = fieldFromInstruction(insn, 21, 5);
10906 if (!Check(S, decodeUImmOperand<3>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10907 tmp = fieldFromInstruction(insn, 16, 5);
10908 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10909 tmp = fieldFromInstruction(insn, 11, 5);
10910 if (!Check(S, Decodeptr_rc_idx_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10911 return S;
10912 case 137:
10913 tmp = fieldFromInstruction(insn, 16, 5);
10914 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10915 tmp = fieldFromInstruction(insn, 21, 5);
10916 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10917 tmp = fieldFromInstruction(insn, 16, 5);
10918 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10919 tmp = fieldFromInstruction(insn, 11, 5);
10920 if (!Check(S, Decodeptr_rc_idx_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10921 return S;
10922 case 138:
10923 tmp = fieldFromInstruction(insn, 21, 5);
10924 if (!Check(S, decodeUImmOperand<5>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10925 tmp = fieldFromInstruction(insn, 16, 5);
10926 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10927 tmp = fieldFromInstruction(insn, 11, 5);
10928 if (!Check(S, Decodeptr_rc_idx_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10929 return S;
10930 case 139:
10931 tmp = fieldFromInstruction(insn, 21, 2);
10932 if (!Check(S, decodeUImmOperand<5>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10933 tmp = fieldFromInstruction(insn, 16, 5);
10934 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10935 tmp = fieldFromInstruction(insn, 11, 5);
10936 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10937 return S;
10938 case 140:
10939 tmp = fieldFromInstruction(insn, 21, 5);
10940 if (!Check(S, DecodeF4RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10941 tmp = fieldFromInstruction(insn, 16, 5);
10942 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10943 tmp = fieldFromInstruction(insn, 11, 5);
10944 if (!Check(S, Decodeptr_rc_idx_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10945 return S;
10946 case 141:
10947 tmp = fieldFromInstruction(insn, 21, 5);
10948 if (!Check(S, DecodeF4RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10949 tmp = fieldFromInstruction(insn, 16, 5);
10950 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10951 tmp = fieldFromInstruction(insn, 16, 5);
10952 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10953 tmp = fieldFromInstruction(insn, 11, 5);
10954 if (!Check(S, Decodeptr_rc_idx_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10955 return S;
10956 case 142:
10957 tmp = fieldFromInstruction(insn, 21, 2);
10958 if (!Check(S, decodeUImmOperand<2>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10959 return S;
10960 case 143:
10961 tmp = fieldFromInstruction(insn, 21, 3);
10962 if (!Check(S, decodeUImmOperand<3>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10963 tmp = fieldFromInstruction(insn, 16, 2);
10964 if (!Check(S, decodeUImmOperand<2>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10965 return S;
10966 case 144:
10967 tmp = fieldFromInstruction(insn, 21, 5);
10968 if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10969 tmp = fieldFromInstruction(insn, 16, 5);
10970 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10971 tmp = fieldFromInstruction(insn, 11, 5);
10972 if (!Check(S, Decodeptr_rc_idx_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10973 return S;
10974 case 145:
10975 tmp = fieldFromInstruction(insn, 21, 5);
10976 if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10977 tmp = fieldFromInstruction(insn, 16, 5);
10978 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10979 tmp = fieldFromInstruction(insn, 16, 5);
10980 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10981 tmp = fieldFromInstruction(insn, 11, 5);
10982 if (!Check(S, Decodeptr_rc_idx_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10983 return S;
10984 case 146:
10985 tmp = fieldFromInstruction(insn, 16, 5);
10986 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10987 tmp = fieldFromInstruction(insn, 21, 5);
10988 if (!Check(S, DecodeF4RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10989 tmp = fieldFromInstruction(insn, 16, 5);
10990 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10991 tmp = fieldFromInstruction(insn, 11, 5);
10992 if (!Check(S, Decodeptr_rc_idx_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10993 return S;
10994 case 147:
10995 tmp = fieldFromInstruction(insn, 16, 5);
10996 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10997 tmp = fieldFromInstruction(insn, 21, 5);
10998 if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
10999 tmp = fieldFromInstruction(insn, 16, 5);
11000 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11001 tmp = fieldFromInstruction(insn, 11, 5);
11002 if (!Check(S, Decodeptr_rc_idx_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11003 return S;
11004 case 148:
11005 tmp = fieldFromInstruction(insn, 21, 2);
11006 if (!Check(S, decodeUImmOperand<5>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11007 return S;
11008 case 149:
11009 tmp = fieldFromInstruction(insn, 21, 5);
11010 if (!Check(S, decodeUImmOperand<5>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11011 return S;
11012 case 150:
11013 tmp = fieldFromInstruction(insn, 16, 5);
11014 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11015 tmp = fieldFromInstruction(insn, 21, 5);
11016 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11017 tmp = fieldFromInstruction(insn, 11, 5);
11018 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11019 return S;
11020 case 151:
11021 tmp = fieldFromInstruction(insn, 16, 5);
11022 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11023 tmp = fieldFromInstruction(insn, 21, 5);
11024 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11025 tmp = fieldFromInstruction(insn, 11, 5);
11026 if (!Check(S, decodeUImmOperand<5>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11027 return S;
11028 case 152:
11029 tmp = fieldFromInstruction(insn, 16, 5);
11030 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11031 tmp = fieldFromInstruction(insn, 21, 5);
11032 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11033 return S;
11034 case 153:
11035 tmp = fieldFromInstruction(insn, 16, 5);
11036 if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11037 tmp = fieldFromInstruction(insn, 21, 5);
11038 if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11039 tmp = fieldFromInstruction(insn, 11, 5);
11040 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11041 return S;
11042 case 154:
11043 tmp = fieldFromInstruction(insn, 16, 5);
11044 if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11045 tmp = fieldFromInstruction(insn, 21, 5);
11046 if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11047 return S;
11048 case 155:
11049 tmp = fieldFromInstruction(insn, 16, 5);
11050 if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11051 tmp = fieldFromInstruction(insn, 21, 5);
11052 if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11053 tmp = fieldFromInstruction(insn, 11, 5);
11054 if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11055 return S;
11056 case 156:
11057 tmp = fieldFromInstruction(insn, 16, 5);
11058 if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11059 tmp = fieldFromInstruction(insn, 21, 5);
11060 if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11061 tmp = 0x0;
11062 tmp |= fieldFromInstruction(insn, 1, 1) << 5;
11063 tmp |= fieldFromInstruction(insn, 11, 5);
11064 if (!Check(S, decodeUImmOperand<6>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11065 return S;
11066 case 157:
11067 tmp = fieldFromInstruction(insn, 21, 2);
11068 if (!Check(S, decodeUImmOperand<2>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11069 tmp = fieldFromInstruction(insn, 16, 2);
11070 if (!Check(S, decodeUImmOperand<2>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11071 return S;
11072 case 158:
11073 tmp = fieldFromInstruction(insn, 16, 5);
11074 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11075 tmp = fieldFromInstruction(insn, 11, 5);
11076 if (!Check(S, Decodeptr_rc_idx_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11077 tmp = fieldFromInstruction(insn, 21, 5);
11078 if (!Check(S, decodeUImmOperand<5>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11079 return S;
11080 case 159:
11081 tmp = fieldFromInstruction(insn, 21, 5);
11082 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11083 tmp = fieldFromInstruction(insn, 0, 16);
11084 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
11085 tmp = fieldFromInstruction(insn, 16, 5);
11086 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11087 return S;
11088 case 160:
11089 tmp = fieldFromInstruction(insn, 21, 5);
11090 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11091 tmp = fieldFromInstruction(insn, 16, 5);
11092 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11093 tmp = fieldFromInstruction(insn, 0, 16);
11094 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
11095 tmp = fieldFromInstruction(insn, 16, 5);
11096 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11097 return S;
11098 case 161:
11099 tmp = fieldFromInstruction(insn, 16, 5);
11100 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11101 tmp = fieldFromInstruction(insn, 21, 5);
11102 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11103 tmp = fieldFromInstruction(insn, 0, 16);
11104 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
11105 tmp = fieldFromInstruction(insn, 16, 5);
11106 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11107 return S;
11108 case 162:
11109 tmp = fieldFromInstruction(insn, 21, 5);
11110 if (!Check(S, DecodeF4RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11111 tmp = fieldFromInstruction(insn, 0, 16);
11112 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
11113 tmp = fieldFromInstruction(insn, 16, 5);
11114 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11115 return S;
11116 case 163:
11117 tmp = fieldFromInstruction(insn, 21, 5);
11118 if (!Check(S, DecodeF4RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11119 tmp = fieldFromInstruction(insn, 16, 5);
11120 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11121 tmp = fieldFromInstruction(insn, 0, 16);
11122 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
11123 tmp = fieldFromInstruction(insn, 16, 5);
11124 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11125 return S;
11126 case 164:
11127 tmp = fieldFromInstruction(insn, 21, 5);
11128 if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11129 tmp = fieldFromInstruction(insn, 0, 16);
11130 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
11131 tmp = fieldFromInstruction(insn, 16, 5);
11132 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11133 return S;
11134 case 165:
11135 tmp = fieldFromInstruction(insn, 21, 5);
11136 if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11137 tmp = fieldFromInstruction(insn, 16, 5);
11138 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11139 tmp = fieldFromInstruction(insn, 0, 16);
11140 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
11141 tmp = fieldFromInstruction(insn, 16, 5);
11142 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11143 return S;
11144 case 166:
11145 tmp = fieldFromInstruction(insn, 16, 5);
11146 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11147 tmp = fieldFromInstruction(insn, 21, 5);
11148 if (!Check(S, DecodeF4RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11149 tmp = fieldFromInstruction(insn, 0, 16);
11150 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
11151 tmp = fieldFromInstruction(insn, 16, 5);
11152 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11153 return S;
11154 case 167:
11155 tmp = fieldFromInstruction(insn, 16, 5);
11156 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11157 tmp = fieldFromInstruction(insn, 21, 5);
11158 if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11159 tmp = fieldFromInstruction(insn, 0, 16);
11160 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
11161 tmp = fieldFromInstruction(insn, 16, 5);
11162 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11163 return S;
11164 case 168:
11165 tmp = fieldFromInstruction(insn, 21, 5);
11166 if (!Check(S, DecodeG8pRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11167 tmp = fieldFromInstruction(insn, 4, 12);
11168 if (!Check(S, decodeDispRIX16Operand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11169 tmp = fieldFromInstruction(insn, 16, 5);
11170 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11171 return S;
11172 case 169:
11173 tmp = fieldFromInstruction(insn, 21, 5);
11174 if (!Check(S, DecodeVFRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11175 tmp = fieldFromInstruction(insn, 2, 14);
11176 if (!Check(S, decodeDispRIXOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11177 tmp = fieldFromInstruction(insn, 16, 5);
11178 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11179 return S;
11180 case 170:
11181 tmp = fieldFromInstruction(insn, 21, 5);
11182 if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11183 tmp = fieldFromInstruction(insn, 2, 14);
11184 if (!Check(S, decodeDispRIXOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11185 tmp = fieldFromInstruction(insn, 16, 5);
11186 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11187 return S;
11188 case 171:
11189 tmp = fieldFromInstruction(insn, 21, 5);
11190 if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11191 tmp = fieldFromInstruction(insn, 16, 5);
11192 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11193 tmp = fieldFromInstruction(insn, 2, 14);
11194 if (!Check(S, decodeDispRIXOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11195 tmp = fieldFromInstruction(insn, 16, 5);
11196 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11197 return S;
11198 case 172:
11199 tmp = fieldFromInstruction(insn, 21, 5);
11200 if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11201 tmp = fieldFromInstruction(insn, 16, 5);
11202 if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11203 tmp = fieldFromInstruction(insn, 11, 5);
11204 if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11205 return S;
11206 case 173:
11207 tmp = fieldFromInstruction(insn, 21, 5);
11208 if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11209 tmp = fieldFromInstruction(insn, 11, 5);
11210 if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11211 return S;
11212 case 174:
11213 tmp = fieldFromInstruction(insn, 21, 5);
11214 if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11215 tmp = fieldFromInstruction(insn, 16, 5);
11216 if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11217 tmp = fieldFromInstruction(insn, 11, 5);
11218 if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11219 tmp = fieldFromInstruction(insn, 9, 2);
11220 if (!Check(S, decodeUImmOperand<2>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11221 return S;
11222 case 175:
11223 tmp = fieldFromInstruction(insn, 21, 5);
11224 if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11225 tmp = fieldFromInstruction(insn, 16, 5);
11226 if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11227 tmp = fieldFromInstruction(insn, 10, 6);
11228 if (!Check(S, decodeUImmOperand<6>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11229 return S;
11230 case 176:
11231 tmp = fieldFromInstruction(insn, 21, 5);
11232 if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11233 tmp = fieldFromInstruction(insn, 19, 2);
11234 if (!Check(S, decodeUImmOperand<2>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11235 tmp = fieldFromInstruction(insn, 11, 5);
11236 if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11237 return S;
11238 case 177:
11239 tmp = fieldFromInstruction(insn, 21, 5);
11240 if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11241 tmp = fieldFromInstruction(insn, 20, 1);
11242 if (!Check(S, decodeUImmOperand<1>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11243 tmp = fieldFromInstruction(insn, 11, 5);
11244 if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11245 return S;
11246 case 178:
11247 tmp = fieldFromInstruction(insn, 21, 5);
11248 if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11249 tmp = fieldFromInstruction(insn, 16, 5);
11250 if (!Check(S, decodeSImmOperand<5>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11251 tmp = fieldFromInstruction(insn, 11, 5);
11252 if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11253 tmp = fieldFromInstruction(insn, 9, 2);
11254 if (!Check(S, decodeUImmOperand<2>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11255 return S;
11256 case 179:
11257 tmp = fieldFromInstruction(insn, 21, 5);
11258 if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11259 tmp = fieldFromInstruction(insn, 16, 1);
11260 if (!Check(S, decodeUImmOperand<1>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11261 tmp = fieldFromInstruction(insn, 11, 5);
11262 if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11263 tmp = fieldFromInstruction(insn, 9, 2);
11264 if (!Check(S, decodeUImmOperand<2>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11265 return S;
11266 case 180:
11267 tmp = fieldFromInstruction(insn, 23, 3);
11268 if (!Check(S, DecodeCRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11269 tmp = fieldFromInstruction(insn, 16, 5);
11270 if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11271 tmp = fieldFromInstruction(insn, 11, 5);
11272 if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11273 return S;
11274 case 181:
11275 tmp = 0x0;
11276 tmp |= fieldFromInstruction(insn, 0, 1) << 5;
11277 tmp |= fieldFromInstruction(insn, 21, 5);
11278 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11279 tmp = 0x0;
11280 tmp |= fieldFromInstruction(insn, 2, 1) << 5;
11281 tmp |= fieldFromInstruction(insn, 16, 5);
11282 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11283 tmp = 0x0;
11284 tmp |= fieldFromInstruction(insn, 1, 1) << 5;
11285 tmp |= fieldFromInstruction(insn, 11, 5);
11286 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11287 return S;
11288 case 182:
11289 tmp = fieldFromInstruction(insn, 23, 3);
11290 if (!Check(S, DecodeCRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11291 tmp = fieldFromInstruction(insn, 16, 6);
11292 if (!Check(S, decodeUImmOperand<6>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11293 tmp = fieldFromInstruction(insn, 11, 5);
11294 if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11295 return S;
11296 case 183:
11297 tmp = fieldFromInstruction(insn, 23, 3);
11298 if (!Check(S, DecodeCRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11299 tmp = fieldFromInstruction(insn, 16, 5);
11300 if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11301 tmp = fieldFromInstruction(insn, 10, 6);
11302 if (!Check(S, decodeUImmOperand<6>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11303 return S;
11304 case 184:
11305 tmp = 0x0;
11306 tmp |= fieldFromInstruction(insn, 0, 1) << 5;
11307 tmp |= fieldFromInstruction(insn, 21, 5);
11308 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11309 tmp = 0x0;
11310 tmp |= fieldFromInstruction(insn, 2, 1) << 5;
11311 tmp |= fieldFromInstruction(insn, 16, 5);
11312 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11313 tmp = 0x0;
11314 tmp |= fieldFromInstruction(insn, 1, 1) << 5;
11315 tmp |= fieldFromInstruction(insn, 11, 5);
11316 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11317 tmp = fieldFromInstruction(insn, 8, 3);
11318 if (!Check(S, decodeUImmOperand<3>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11319 return S;
11320 case 185:
11321 tmp = 0x0;
11322 tmp |= fieldFromInstruction(insn, 0, 1) << 5;
11323 tmp |= fieldFromInstruction(insn, 21, 5);
11324 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11325 tmp = 0x0;
11326 tmp |= fieldFromInstruction(insn, 2, 1) << 5;
11327 tmp |= fieldFromInstruction(insn, 16, 5);
11328 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11329 tmp = 0x0;
11330 tmp |= fieldFromInstruction(insn, 1, 1) << 5;
11331 tmp |= fieldFromInstruction(insn, 11, 5);
11332 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11333 tmp = fieldFromInstruction(insn, 10, 1);
11334 if (!Check(S, decodeUImmOperand<1>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11335 tmp = fieldFromInstruction(insn, 9, 1);
11336 if (!Check(S, decodeUImmOperand<1>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11337 tmp = fieldFromInstruction(insn, 8, 1);
11338 if (!Check(S, decodeUImmOperand<1>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11339 return S;
11340 case 186:
11341 tmp = 0x0;
11342 tmp |= fieldFromInstruction(insn, 0, 1) << 5;
11343 tmp |= fieldFromInstruction(insn, 21, 5);
11344 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11345 tmp = 0x0;
11346 tmp |= fieldFromInstruction(insn, 2, 1) << 5;
11347 tmp |= fieldFromInstruction(insn, 16, 5);
11348 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11349 tmp = 0x0;
11350 tmp |= fieldFromInstruction(insn, 1, 1) << 5;
11351 tmp |= fieldFromInstruction(insn, 11, 5);
11352 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11353 tmp = fieldFromInstruction(insn, 9, 1);
11354 if (!Check(S, decodeUImmOperand<1>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11355 tmp = fieldFromInstruction(insn, 8, 1);
11356 if (!Check(S, decodeUImmOperand<1>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11357 return S;
11358 case 187:
11359 tmp = 0x0;
11360 tmp |= fieldFromInstruction(insn, 0, 1) << 5;
11361 tmp |= fieldFromInstruction(insn, 21, 5);
11362 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11363 tmp = 0x0;
11364 tmp |= fieldFromInstruction(insn, 2, 1) << 5;
11365 tmp |= fieldFromInstruction(insn, 16, 5);
11366 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11367 tmp = 0x0;
11368 tmp |= fieldFromInstruction(insn, 1, 1) << 5;
11369 tmp |= fieldFromInstruction(insn, 11, 5);
11370 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11371 tmp = fieldFromInstruction(insn, 10, 1);
11372 if (!Check(S, decodeUImmOperand<1>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11373 return S;
11374 case 188:
11375 tmp = fieldFromInstruction(insn, 23, 3);
11376 if (!Check(S, DecodeACCRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11377 tmp = fieldFromInstruction(insn, 23, 3);
11378 if (!Check(S, DecodeACCRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11379 tmp = 0x0;
11380 tmp |= fieldFromInstruction(insn, 2, 1) << 5;
11381 tmp |= fieldFromInstruction(insn, 16, 5);
11382 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11383 tmp = 0x0;
11384 tmp |= fieldFromInstruction(insn, 1, 1) << 5;
11385 tmp |= fieldFromInstruction(insn, 11, 5);
11386 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11387 return S;
11388 case 189:
11389 tmp = fieldFromInstruction(insn, 23, 3);
11390 if (!Check(S, DecodeDMRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11391 tmp = fieldFromInstruction(insn, 23, 3);
11392 if (!Check(S, DecodeDMRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11393 tmp = 0x0;
11394 tmp |= fieldFromInstruction(insn, 2, 1) << 4;
11395 tmp |= fieldFromInstruction(insn, 17, 4);
11396 if (!Check(S, DecodeVSRpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11397 tmp = 0x0;
11398 tmp |= fieldFromInstruction(insn, 1, 1) << 5;
11399 tmp |= fieldFromInstruction(insn, 11, 5);
11400 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11401 return S;
11402 case 190:
11403 tmp = fieldFromInstruction(insn, 23, 3);
11404 if (!Check(S, DecodeACCRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11405 tmp = fieldFromInstruction(insn, 23, 3);
11406 if (!Check(S, DecodeACCRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11407 tmp = 0x0;
11408 tmp |= fieldFromInstruction(insn, 2, 1) << 5;
11409 tmp |= fieldFromInstruction(insn, 16, 5);
11410 if (!Check(S, decodeVSRpEvenOperands(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11411 tmp = 0x0;
11412 tmp |= fieldFromInstruction(insn, 1, 1) << 5;
11413 tmp |= fieldFromInstruction(insn, 11, 5);
11414 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11415 return S;
11416 case 191:
11417 tmp = fieldFromInstruction(insn, 23, 3);
11418 if (!Check(S, DecodeACCRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11419 tmp = 0x0;
11420 tmp |= fieldFromInstruction(insn, 2, 1) << 5;
11421 tmp |= fieldFromInstruction(insn, 16, 5);
11422 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11423 tmp = 0x0;
11424 tmp |= fieldFromInstruction(insn, 1, 1) << 5;
11425 tmp |= fieldFromInstruction(insn, 11, 5);
11426 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11427 return S;
11428 case 192:
11429 tmp = fieldFromInstruction(insn, 23, 3);
11430 if (!Check(S, DecodeDMRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11431 tmp = 0x0;
11432 tmp |= fieldFromInstruction(insn, 2, 1) << 4;
11433 tmp |= fieldFromInstruction(insn, 17, 4);
11434 if (!Check(S, DecodeVSRpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11435 tmp = 0x0;
11436 tmp |= fieldFromInstruction(insn, 1, 1) << 5;
11437 tmp |= fieldFromInstruction(insn, 11, 5);
11438 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11439 return S;
11440 case 193:
11441 tmp = fieldFromInstruction(insn, 23, 3);
11442 if (!Check(S, DecodeACCRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11443 tmp = 0x0;
11444 tmp |= fieldFromInstruction(insn, 2, 1) << 5;
11445 tmp |= fieldFromInstruction(insn, 16, 5);
11446 if (!Check(S, decodeVSRpEvenOperands(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11447 tmp = 0x0;
11448 tmp |= fieldFromInstruction(insn, 1, 1) << 5;
11449 tmp |= fieldFromInstruction(insn, 11, 5);
11450 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11451 return S;
11452 case 194:
11453 tmp = fieldFromInstruction(insn, 21, 5);
11454 if (!Check(S, DecodeF4RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11455 tmp = fieldFromInstruction(insn, 11, 5);
11456 if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11457 return S;
11458 case 195:
11459 tmp = fieldFromInstruction(insn, 21, 5);
11460 if (!Check(S, DecodeF4RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11461 tmp = fieldFromInstruction(insn, 16, 5);
11462 if (!Check(S, DecodeF4RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11463 tmp = fieldFromInstruction(insn, 11, 5);
11464 if (!Check(S, DecodeF4RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11465 return S;
11466 case 196:
11467 tmp = fieldFromInstruction(insn, 21, 5);
11468 if (!Check(S, DecodeF4RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11469 tmp = fieldFromInstruction(insn, 11, 5);
11470 if (!Check(S, DecodeF4RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11471 return S;
11472 case 197:
11473 tmp = fieldFromInstruction(insn, 21, 5);
11474 if (!Check(S, DecodeF4RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11475 tmp = fieldFromInstruction(insn, 16, 5);
11476 if (!Check(S, DecodeF4RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11477 tmp = fieldFromInstruction(insn, 6, 5);
11478 if (!Check(S, DecodeF4RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11479 return S;
11480 case 198:
11481 tmp = fieldFromInstruction(insn, 21, 5);
11482 if (!Check(S, DecodeF4RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11483 tmp = fieldFromInstruction(insn, 16, 5);
11484 if (!Check(S, DecodeF4RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11485 tmp = fieldFromInstruction(insn, 6, 5);
11486 if (!Check(S, DecodeF4RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11487 tmp = fieldFromInstruction(insn, 11, 5);
11488 if (!Check(S, DecodeF4RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11489 return S;
11490 case 199:
11491 tmp = 0x0;
11492 tmp |= fieldFromInstruction(insn, 0, 1) << 5;
11493 tmp |= fieldFromInstruction(insn, 21, 5);
11494 if (!Check(S, DecodeVSSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11495 tmp = 0x0;
11496 tmp |= fieldFromInstruction(insn, 2, 1) << 5;
11497 tmp |= fieldFromInstruction(insn, 16, 5);
11498 if (!Check(S, DecodeVSSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11499 tmp = 0x0;
11500 tmp |= fieldFromInstruction(insn, 1, 1) << 5;
11501 tmp |= fieldFromInstruction(insn, 11, 5);
11502 if (!Check(S, DecodeVSSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11503 return S;
11504 case 200:
11505 tmp = 0x0;
11506 tmp |= fieldFromInstruction(insn, 0, 1) << 5;
11507 tmp |= fieldFromInstruction(insn, 21, 5);
11508 if (!Check(S, DecodeVSSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11509 tmp = 0x0;
11510 tmp |= fieldFromInstruction(insn, 0, 1) << 5;
11511 tmp |= fieldFromInstruction(insn, 21, 5);
11512 if (!Check(S, DecodeVSSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11513 tmp = 0x0;
11514 tmp |= fieldFromInstruction(insn, 2, 1) << 5;
11515 tmp |= fieldFromInstruction(insn, 16, 5);
11516 if (!Check(S, DecodeVSSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11517 tmp = 0x0;
11518 tmp |= fieldFromInstruction(insn, 1, 1) << 5;
11519 tmp |= fieldFromInstruction(insn, 11, 5);
11520 if (!Check(S, DecodeVSSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11521 return S;
11522 case 201:
11523 tmp = 0x0;
11524 tmp |= fieldFromInstruction(insn, 0, 1) << 5;
11525 tmp |= fieldFromInstruction(insn, 21, 5);
11526 if (!Check(S, DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11527 tmp = 0x0;
11528 tmp |= fieldFromInstruction(insn, 2, 1) << 5;
11529 tmp |= fieldFromInstruction(insn, 16, 5);
11530 if (!Check(S, DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11531 tmp = 0x0;
11532 tmp |= fieldFromInstruction(insn, 1, 1) << 5;
11533 tmp |= fieldFromInstruction(insn, 11, 5);
11534 if (!Check(S, DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11535 return S;
11536 case 202:
11537 tmp = 0x0;
11538 tmp |= fieldFromInstruction(insn, 0, 1) << 5;
11539 tmp |= fieldFromInstruction(insn, 21, 5);
11540 if (!Check(S, DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11541 tmp = 0x0;
11542 tmp |= fieldFromInstruction(insn, 0, 1) << 5;
11543 tmp |= fieldFromInstruction(insn, 21, 5);
11544 if (!Check(S, DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11545 tmp = 0x0;
11546 tmp |= fieldFromInstruction(insn, 2, 1) << 5;
11547 tmp |= fieldFromInstruction(insn, 16, 5);
11548 if (!Check(S, DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11549 tmp = 0x0;
11550 tmp |= fieldFromInstruction(insn, 1, 1) << 5;
11551 tmp |= fieldFromInstruction(insn, 11, 5);
11552 if (!Check(S, DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11553 return S;
11554 case 203:
11555 tmp = 0x0;
11556 tmp |= fieldFromInstruction(insn, 0, 1) << 5;
11557 tmp |= fieldFromInstruction(insn, 21, 5);
11558 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11559 tmp = 0x0;
11560 tmp |= fieldFromInstruction(insn, 0, 1) << 5;
11561 tmp |= fieldFromInstruction(insn, 21, 5);
11562 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11563 tmp = 0x0;
11564 tmp |= fieldFromInstruction(insn, 2, 1) << 5;
11565 tmp |= fieldFromInstruction(insn, 16, 5);
11566 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11567 tmp = 0x0;
11568 tmp |= fieldFromInstruction(insn, 1, 1) << 5;
11569 tmp |= fieldFromInstruction(insn, 11, 5);
11570 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11571 return S;
11572 case 204:
11573 tmp = 0x0;
11574 tmp |= fieldFromInstruction(insn, 0, 1) << 5;
11575 tmp |= fieldFromInstruction(insn, 21, 5);
11576 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11577 tmp = 0x0;
11578 tmp |= fieldFromInstruction(insn, 2, 1) << 5;
11579 tmp |= fieldFromInstruction(insn, 16, 5);
11580 if (!Check(S, DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11581 tmp = 0x0;
11582 tmp |= fieldFromInstruction(insn, 1, 1) << 5;
11583 tmp |= fieldFromInstruction(insn, 11, 5);
11584 if (!Check(S, DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11585 return S;
11586 case 205:
11587 tmp = 0x0;
11588 tmp |= fieldFromInstruction(insn, 0, 1) << 5;
11589 tmp |= fieldFromInstruction(insn, 21, 5);
11590 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11591 tmp = 0x0;
11592 tmp |= fieldFromInstruction(insn, 2, 1) << 5;
11593 tmp |= fieldFromInstruction(insn, 16, 5);
11594 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11595 tmp = 0x0;
11596 tmp |= fieldFromInstruction(insn, 1, 1) << 5;
11597 tmp |= fieldFromInstruction(insn, 11, 5);
11598 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11599 tmp = fieldFromInstruction(insn, 8, 2);
11600 if (!Check(S, decodeUImmOperand<2>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11601 return S;
11602 case 206:
11603 tmp = 0x0;
11604 tmp |= fieldFromInstruction(insn, 21, 1) << 4;
11605 tmp |= fieldFromInstruction(insn, 22, 4);
11606 if (!Check(S, DecodeVSRpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11607 tmp = 0x0;
11608 tmp |= fieldFromInstruction(insn, 2, 1) << 4;
11609 tmp |= fieldFromInstruction(insn, 17, 4);
11610 if (!Check(S, DecodeVSRpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11611 tmp = 0x0;
11612 tmp |= fieldFromInstruction(insn, 1, 1) << 4;
11613 tmp |= fieldFromInstruction(insn, 12, 4);
11614 if (!Check(S, DecodeVSRpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11615 tmp = 0x0;
11616 tmp |= fieldFromInstruction(insn, 11, 1) << 1;
11617 tmp |= fieldFromInstruction(insn, 16, 1);
11618 if (!Check(S, decodeUImmOperand<2>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11619 return S;
11620 case 207:
11621 tmp = 0x0;
11622 tmp |= fieldFromInstruction(insn, 2, 1) << 4;
11623 tmp |= fieldFromInstruction(insn, 17, 4);
11624 if (!Check(S, DecodeVSRpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11625 tmp = 0x0;
11626 tmp |= fieldFromInstruction(insn, 1, 1) << 4;
11627 tmp |= fieldFromInstruction(insn, 12, 4);
11628 if (!Check(S, DecodeVSRpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11629 tmp = fieldFromInstruction(insn, 23, 3);
11630 if (!Check(S, DecodeWACCRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11631 return S;
11632 case 208:
11633 tmp = 0x0;
11634 tmp |= fieldFromInstruction(insn, 2, 1) << 4;
11635 tmp |= fieldFromInstruction(insn, 17, 4);
11636 if (!Check(S, DecodeVSRpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11637 tmp = 0x0;
11638 tmp |= fieldFromInstruction(insn, 1, 1) << 4;
11639 tmp |= fieldFromInstruction(insn, 12, 4);
11640 if (!Check(S, DecodeVSRpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11641 tmp = fieldFromInstruction(insn, 23, 3);
11642 if (!Check(S, DecodeWACC_HIRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11643 return S;
11644 case 209:
11645 tmp = fieldFromInstruction(insn, 23, 3);
11646 if (!Check(S, DecodeCRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11647 tmp = 0x0;
11648 tmp |= fieldFromInstruction(insn, 2, 1) << 5;
11649 tmp |= fieldFromInstruction(insn, 16, 5);
11650 if (!Check(S, DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11651 tmp = 0x0;
11652 tmp |= fieldFromInstruction(insn, 1, 1) << 5;
11653 tmp |= fieldFromInstruction(insn, 11, 5);
11654 if (!Check(S, DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11655 return S;
11656 case 210:
11657 tmp = fieldFromInstruction(insn, 23, 3);
11658 if (!Check(S, DecodeWACCRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11659 tmp = 0x0;
11660 tmp |= fieldFromInstruction(insn, 2, 1) << 4;
11661 tmp |= fieldFromInstruction(insn, 17, 4);
11662 if (!Check(S, DecodeVSRpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11663 tmp = 0x0;
11664 tmp |= fieldFromInstruction(insn, 1, 1) << 4;
11665 tmp |= fieldFromInstruction(insn, 12, 4);
11666 if (!Check(S, DecodeVSRpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11667 return S;
11668 case 211:
11669 tmp = fieldFromInstruction(insn, 23, 3);
11670 if (!Check(S, DecodeWACC_HIRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11671 tmp = 0x0;
11672 tmp |= fieldFromInstruction(insn, 2, 1) << 4;
11673 tmp |= fieldFromInstruction(insn, 17, 4);
11674 if (!Check(S, DecodeVSRpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11675 tmp = 0x0;
11676 tmp |= fieldFromInstruction(insn, 1, 1) << 4;
11677 tmp |= fieldFromInstruction(insn, 12, 4);
11678 if (!Check(S, DecodeVSRpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11679 return S;
11680 case 212:
11681 tmp = 0x0;
11682 tmp |= fieldFromInstruction(insn, 0, 1) << 5;
11683 tmp |= fieldFromInstruction(insn, 21, 5);
11684 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11685 tmp = 0x0;
11686 tmp |= fieldFromInstruction(insn, 1, 1) << 5;
11687 tmp |= fieldFromInstruction(insn, 11, 5);
11688 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11689 tmp = fieldFromInstruction(insn, 16, 2);
11690 if (!Check(S, decodeUImmOperand<2>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11691 return S;
11692 case 213:
11693 tmp = 0x0;
11694 tmp |= fieldFromInstruction(insn, 0, 1) << 5;
11695 tmp |= fieldFromInstruction(insn, 21, 5);
11696 if (!Check(S, DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11697 tmp = 0x0;
11698 tmp |= fieldFromInstruction(insn, 1, 1) << 5;
11699 tmp |= fieldFromInstruction(insn, 11, 5);
11700 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11701 tmp = fieldFromInstruction(insn, 16, 5);
11702 if (!Check(S, decodeUImmOperand<4>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11703 return S;
11704 case 214:
11705 tmp = 0x0;
11706 tmp |= fieldFromInstruction(insn, 21, 1) << 4;
11707 tmp |= fieldFromInstruction(insn, 22, 4);
11708 if (!Check(S, DecodeVSRpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11709 tmp = 0x0;
11710 tmp |= fieldFromInstruction(insn, 1, 1) << 4;
11711 tmp |= fieldFromInstruction(insn, 12, 4);
11712 if (!Check(S, DecodeVSRpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11713 tmp = 0x0;
11714 tmp |= fieldFromInstruction(insn, 11, 1) << 1;
11715 tmp |= fieldFromInstruction(insn, 16, 1);
11716 if (!Check(S, decodeUImmOperand<2>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11717 return S;
11718 case 215:
11719 tmp = fieldFromInstruction(insn, 23, 3);
11720 if (!Check(S, DecodeDMRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11721 tmp = fieldFromInstruction(insn, 23, 3);
11722 if (!Check(S, DecodeDMRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11723 tmp = 0x0;
11724 tmp |= fieldFromInstruction(insn, 1, 1) << 5;
11725 tmp |= fieldFromInstruction(insn, 11, 5);
11726 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11727 tmp = fieldFromInstruction(insn, 19, 2);
11728 if (!Check(S, decodeUImmOperand<2>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11729 tmp = fieldFromInstruction(insn, 18, 1);
11730 if (!Check(S, decodeUImmOperand<1>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11731 tmp = fieldFromInstruction(insn, 16, 2);
11732 if (!Check(S, decodeUImmOperand<2>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11733 return S;
11734 case 216:
11735 tmp = 0x0;
11736 tmp |= fieldFromInstruction(insn, 1, 1) << 4;
11737 tmp |= fieldFromInstruction(insn, 12, 4);
11738 if (!Check(S, DecodeVSRpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11739 tmp = fieldFromInstruction(insn, 23, 3);
11740 if (!Check(S, DecodeDMRROWpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11741 tmp = 0x0;
11742 tmp |= fieldFromInstruction(insn, 11, 1) << 1;
11743 tmp |= fieldFromInstruction(insn, 16, 1);
11744 if (!Check(S, decodeUImmOperand<2>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11745 return S;
11746 case 217:
11747 tmp = fieldFromInstruction(insn, 23, 3);
11748 if (!Check(S, DecodeDMRROWpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11749 tmp = 0x0;
11750 tmp |= fieldFromInstruction(insn, 1, 1) << 4;
11751 tmp |= fieldFromInstruction(insn, 12, 4);
11752 if (!Check(S, DecodeVSRpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11753 tmp = 0x0;
11754 tmp |= fieldFromInstruction(insn, 11, 1) << 1;
11755 tmp |= fieldFromInstruction(insn, 16, 1);
11756 if (!Check(S, decodeUImmOperand<2>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11757 return S;
11758 case 218:
11759 tmp = 0x0;
11760 tmp |= fieldFromInstruction(insn, 0, 1) << 5;
11761 tmp |= fieldFromInstruction(insn, 21, 5);
11762 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11763 tmp = 0x0;
11764 tmp |= fieldFromInstruction(insn, 2, 1) << 5;
11765 tmp |= fieldFromInstruction(insn, 16, 5);
11766 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11767 tmp = 0x0;
11768 tmp |= fieldFromInstruction(insn, 0, 1) << 5;
11769 tmp |= fieldFromInstruction(insn, 21, 5);
11770 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11771 tmp = 0x0;
11772 tmp |= fieldFromInstruction(insn, 1, 1) << 5;
11773 tmp |= fieldFromInstruction(insn, 11, 5);
11774 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11775 return S;
11776 case 219:
11777 tmp = 0x0;
11778 tmp |= fieldFromInstruction(insn, 0, 1) << 5;
11779 tmp |= fieldFromInstruction(insn, 21, 5);
11780 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11781 tmp = fieldFromInstruction(insn, 11, 8);
11782 if (!Check(S, decodeUImmOperand<8>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11783 return S;
11784 case 220:
11785 tmp = 0x0;
11786 tmp |= fieldFromInstruction(insn, 0, 1) << 5;
11787 tmp |= fieldFromInstruction(insn, 21, 5);
11788 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11789 tmp = fieldFromInstruction(insn, 11, 5);
11790 if (!Check(S, decodeUImmOperand<5>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11791 return S;
11792 case 221:
11793 tmp = 0x0;
11794 tmp |= fieldFromInstruction(insn, 0, 1) << 5;
11795 tmp |= fieldFromInstruction(insn, 21, 5);
11796 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11797 tmp = 0x0;
11798 tmp |= fieldFromInstruction(insn, 0, 1) << 5;
11799 tmp |= fieldFromInstruction(insn, 21, 5);
11800 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11801 tmp = 0x0;
11802 tmp |= fieldFromInstruction(insn, 1, 1) << 5;
11803 tmp |= fieldFromInstruction(insn, 11, 5);
11804 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11805 tmp = fieldFromInstruction(insn, 16, 5);
11806 if (!Check(S, decodeUImmOperand<4>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11807 return S;
11808 case 222:
11809 tmp = 0x0;
11810 tmp |= fieldFromInstruction(insn, 0, 1) << 5;
11811 tmp |= fieldFromInstruction(insn, 21, 5);
11812 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11813 tmp = 0x0;
11814 tmp |= fieldFromInstruction(insn, 2, 1) << 5;
11815 tmp |= fieldFromInstruction(insn, 16, 5);
11816 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11817 tmp = 0x0;
11818 tmp |= fieldFromInstruction(insn, 1, 1) << 5;
11819 tmp |= fieldFromInstruction(insn, 11, 5);
11820 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11821 tmp = fieldFromInstruction(insn, 8, 1);
11822 if (!Check(S, decodeUImmOperand<1>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11823 return S;
11824 case 223:
11825 tmp = 0x0;
11826 tmp |= fieldFromInstruction(insn, 0, 1) << 5;
11827 tmp |= fieldFromInstruction(insn, 21, 5);
11828 if (!Check(S, DecodeVSSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11829 tmp = 0x0;
11830 tmp |= fieldFromInstruction(insn, 1, 1) << 5;
11831 tmp |= fieldFromInstruction(insn, 11, 5);
11832 if (!Check(S, DecodeVSSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11833 return S;
11834 case 224:
11835 tmp = 0x0;
11836 tmp |= fieldFromInstruction(insn, 0, 1) << 5;
11837 tmp |= fieldFromInstruction(insn, 21, 5);
11838 if (!Check(S, DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11839 tmp = 0x0;
11840 tmp |= fieldFromInstruction(insn, 1, 1) << 5;
11841 tmp |= fieldFromInstruction(insn, 11, 5);
11842 if (!Check(S, DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11843 return S;
11844 case 225:
11845 tmp = fieldFromInstruction(insn, 23, 3);
11846 if (!Check(S, DecodeCRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11847 tmp = 0x0;
11848 tmp |= fieldFromInstruction(insn, 1, 1) << 5;
11849 tmp |= fieldFromInstruction(insn, 11, 5);
11850 if (!Check(S, DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11851 return S;
11852 case 226:
11853 tmp = 0x0;
11854 tmp |= fieldFromInstruction(insn, 0, 1) << 5;
11855 tmp |= fieldFromInstruction(insn, 21, 5);
11856 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11857 tmp = 0x0;
11858 tmp |= fieldFromInstruction(insn, 1, 1) << 5;
11859 tmp |= fieldFromInstruction(insn, 11, 5);
11860 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11861 return S;
11862 case 227:
11863 tmp = fieldFromInstruction(insn, 23, 3);
11864 if (!Check(S, DecodeCRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11865 tmp = 0x0;
11866 tmp |= fieldFromInstruction(insn, 1, 1) << 5;
11867 tmp |= fieldFromInstruction(insn, 11, 5);
11868 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11869 return S;
11870 case 228:
11871 tmp = fieldFromInstruction(insn, 23, 3);
11872 if (!Check(S, DecodeCRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11873 tmp = 0x0;
11874 tmp |= fieldFromInstruction(insn, 2, 1) << 5;
11875 tmp |= fieldFromInstruction(insn, 16, 5);
11876 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11877 tmp = 0x0;
11878 tmp |= fieldFromInstruction(insn, 1, 1) << 5;
11879 tmp |= fieldFromInstruction(insn, 11, 5);
11880 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11881 return S;
11882 case 229:
11883 tmp = 0x0;
11884 tmp |= fieldFromInstruction(insn, 0, 1) << 5;
11885 tmp |= fieldFromInstruction(insn, 21, 5);
11886 if (!Check(S, DecodeVSSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11887 tmp = 0x0;
11888 tmp |= fieldFromInstruction(insn, 1, 1) << 5;
11889 tmp |= fieldFromInstruction(insn, 11, 5);
11890 if (!Check(S, DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11891 return S;
11892 case 230:
11893 tmp = 0x0;
11894 tmp |= fieldFromInstruction(insn, 0, 1) << 5;
11895 tmp |= fieldFromInstruction(insn, 21, 5);
11896 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11897 tmp = 0x0;
11898 tmp |= fieldFromInstruction(insn, 1, 1) << 5;
11899 tmp |= fieldFromInstruction(insn, 11, 5);
11900 if (!Check(S, DecodeVSSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11901 return S;
11902 case 231:
11903 tmp = fieldFromInstruction(insn, 23, 3);
11904 if (!Check(S, DecodeCRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11905 tmp = fieldFromInstruction(insn, 16, 7);
11906 if (!Check(S, decodeUImmOperand<7>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11907 tmp = 0x0;
11908 tmp |= fieldFromInstruction(insn, 1, 1) << 5;
11909 tmp |= fieldFromInstruction(insn, 11, 5);
11910 if (!Check(S, DecodeVSSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11911 return S;
11912 case 232:
11913 tmp = 0x0;
11914 tmp |= fieldFromInstruction(insn, 0, 1) << 5;
11915 tmp |= fieldFromInstruction(insn, 21, 5);
11916 if (!Check(S, DecodeVSSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11917 tmp = 0x0;
11918 tmp |= fieldFromInstruction(insn, 1, 1) << 5;
11919 tmp |= fieldFromInstruction(insn, 11, 5);
11920 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11921 return S;
11922 case 233:
11923 tmp = fieldFromInstruction(insn, 21, 5);
11924 if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11925 tmp = 0x0;
11926 tmp |= fieldFromInstruction(insn, 1, 1) << 5;
11927 tmp |= fieldFromInstruction(insn, 11, 5);
11928 if (!Check(S, DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11929 return S;
11930 case 234:
11931 tmp = fieldFromInstruction(insn, 23, 3);
11932 if (!Check(S, DecodeCRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11933 tmp = fieldFromInstruction(insn, 16, 7);
11934 if (!Check(S, decodeUImmOperand<7>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11935 tmp = 0x0;
11936 tmp |= fieldFromInstruction(insn, 1, 1) << 5;
11937 tmp |= fieldFromInstruction(insn, 11, 5);
11938 if (!Check(S, DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11939 return S;
11940 case 235:
11941 tmp = 0x0;
11942 tmp |= fieldFromInstruction(insn, 0, 1) << 5;
11943 tmp |= fieldFromInstruction(insn, 21, 5);
11944 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11945 tmp = 0x0;
11946 tmp |= fieldFromInstruction(insn, 2, 1) << 5;
11947 tmp |= fieldFromInstruction(insn, 6, 1) << 6;
11948 tmp |= fieldFromInstruction(insn, 16, 5);
11949 if (!Check(S, decodeUImmOperand<7>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11950 tmp = 0x0;
11951 tmp |= fieldFromInstruction(insn, 1, 1) << 5;
11952 tmp |= fieldFromInstruction(insn, 11, 5);
11953 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11954 return S;
11955 case 236:
11956 tmp = 0x0;
11957 tmp |= fieldFromInstruction(insn, 0, 1) << 5;
11958 tmp |= fieldFromInstruction(insn, 21, 5);
11959 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11960 tmp = fieldFromInstruction(insn, 11, 5);
11961 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11962 tmp = fieldFromInstruction(insn, 16, 5);
11963 if (!Check(S, decodeSImmOperand<5>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11964 return S;
11965 case 237:
11966 tmp = 0x0;
11967 tmp |= fieldFromInstruction(insn, 0, 1) << 5;
11968 tmp |= fieldFromInstruction(insn, 21, 5);
11969 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11970 tmp = fieldFromInstruction(insn, 16, 5);
11971 if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11972 tmp = fieldFromInstruction(insn, 11, 5);
11973 if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11974 return S;
11975 case 238:
11976 tmp = 0x0;
11977 tmp |= fieldFromInstruction(insn, 0, 1) << 5;
11978 tmp |= fieldFromInstruction(insn, 21, 5);
11979 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11980 tmp = 0x0;
11981 tmp |= fieldFromInstruction(insn, 2, 1) << 5;
11982 tmp |= fieldFromInstruction(insn, 16, 5);
11983 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11984 tmp = 0x0;
11985 tmp |= fieldFromInstruction(insn, 1, 1) << 5;
11986 tmp |= fieldFromInstruction(insn, 11, 5);
11987 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11988 tmp = 0x0;
11989 tmp |= fieldFromInstruction(insn, 3, 1) << 5;
11990 tmp |= fieldFromInstruction(insn, 6, 5);
11991 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11992 return S;
11993 case 239:
11994 tmp = 0x0;
11995 tmp |= fieldFromInstruction(insn, 3, 1) << 5;
11996 tmp |= fieldFromInstruction(insn, 21, 5);
11997 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
11998 tmp = fieldFromInstruction(insn, 4, 12);
11999 if (!Check(S, decodeDispRIX16Operand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12000 tmp = fieldFromInstruction(insn, 16, 5);
12001 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12002 return S;
12003 case 240:
12004 tmp = fieldFromInstruction(insn, 16, 5);
12005 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12006 tmp = fieldFromInstruction(insn, 21, 5);
12007 if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12008 tmp = fieldFromInstruction(insn, 2, 14);
12009 if (!Check(S, decodeDispRIXOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12010 tmp = fieldFromInstruction(insn, 16, 5);
12011 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12012 return S;
12013 case 241:
12014 tmp = fieldFromInstruction(insn, 21, 5);
12015 if (!Check(S, DecodeG8pRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12016 tmp = fieldFromInstruction(insn, 2, 14);
12017 if (!Check(S, decodeDispRIXOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12018 tmp = fieldFromInstruction(insn, 16, 5);
12019 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12020 return S;
12021 case 242:
12022 tmp = fieldFromInstruction(insn, 23, 3);
12023 if (!Check(S, DecodeCRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12024 tmp = fieldFromInstruction(insn, 16, 5);
12025 if (!Check(S, DecodeF4RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12026 tmp = fieldFromInstruction(insn, 11, 5);
12027 if (!Check(S, DecodeF4RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12028 return S;
12029 case 243:
12030 tmp = fieldFromInstruction(insn, 23, 3);
12031 if (!Check(S, DecodeCRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12032 tmp = fieldFromInstruction(insn, 11, 5);
12033 if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12034 return S;
12035 case 244:
12036 tmp = fieldFromInstruction(insn, 21, 5);
12037 if (!Check(S, DecodeFpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12038 tmp = fieldFromInstruction(insn, 16, 5);
12039 if (!Check(S, DecodeFpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12040 tmp = fieldFromInstruction(insn, 11, 5);
12041 if (!Check(S, DecodeFpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12042 return S;
12043 case 245:
12044 tmp = fieldFromInstruction(insn, 21, 5);
12045 if (!Check(S, DecodeFpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12046 tmp = fieldFromInstruction(insn, 16, 5);
12047 if (!Check(S, DecodeFpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12048 tmp = fieldFromInstruction(insn, 10, 6);
12049 if (!Check(S, decodeUImmOperand<6>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12050 return S;
12051 case 246:
12052 tmp = fieldFromInstruction(insn, 23, 3);
12053 if (!Check(S, DecodeCRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12054 tmp = fieldFromInstruction(insn, 16, 5);
12055 if (!Check(S, DecodeFpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12056 tmp = fieldFromInstruction(insn, 11, 5);
12057 if (!Check(S, DecodeFpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12058 return S;
12059 case 247:
12060 tmp = fieldFromInstruction(insn, 23, 3);
12061 if (!Check(S, DecodeCRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12062 tmp = fieldFromInstruction(insn, 16, 5);
12063 if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12064 tmp = fieldFromInstruction(insn, 11, 5);
12065 if (!Check(S, DecodeFpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12066 return S;
12067 case 248:
12068 tmp = fieldFromInstruction(insn, 23, 3);
12069 if (!Check(S, DecodeCRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12070 tmp = fieldFromInstruction(insn, 16, 5);
12071 if (!Check(S, DecodeFpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12072 tmp = fieldFromInstruction(insn, 10, 6);
12073 if (!Check(S, decodeUImmOperand<6>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12074 return S;
12075 case 249:
12076 tmp = fieldFromInstruction(insn, 21, 5);
12077 if (!Check(S, DecodeFpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12078 tmp = fieldFromInstruction(insn, 11, 5);
12079 if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12080 return S;
12081 case 250:
12082 tmp = fieldFromInstruction(insn, 21, 5);
12083 if (!Check(S, DecodeFpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12084 tmp = fieldFromInstruction(insn, 11, 5);
12085 if (!Check(S, DecodeFpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12086 return S;
12087 case 251:
12088 tmp = fieldFromInstruction(insn, 21, 5);
12089 if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12090 tmp = fieldFromInstruction(insn, 11, 5);
12091 if (!Check(S, DecodeFpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12092 return S;
12093 case 252:
12094 tmp = fieldFromInstruction(insn, 21, 5);
12095 if (!Check(S, DecodeFpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12096 tmp = fieldFromInstruction(insn, 19, 2);
12097 if (!Check(S, decodeUImmOperand<2>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12098 tmp = fieldFromInstruction(insn, 11, 5);
12099 if (!Check(S, DecodeFpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12100 return S;
12101 case 253:
12102 tmp = fieldFromInstruction(insn, 21, 5);
12103 if (!Check(S, DecodeFpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12104 tmp = fieldFromInstruction(insn, 20, 1);
12105 if (!Check(S, decodeUImmOperand<1>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12106 tmp = fieldFromInstruction(insn, 11, 5);
12107 if (!Check(S, DecodeFpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12108 return S;
12109 case 254:
12110 tmp = fieldFromInstruction(insn, 21, 5);
12111 if (!Check(S, DecodeFpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12112 tmp = fieldFromInstruction(insn, 16, 5);
12113 if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12114 tmp = fieldFromInstruction(insn, 11, 5);
12115 if (!Check(S, DecodeFpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12116 return S;
12117 case 255:
12118 tmp = fieldFromInstruction(insn, 21, 5);
12119 if (!Check(S, DecodeFpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12120 tmp = fieldFromInstruction(insn, 11, 5);
12121 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12122 return S;
12123 case 256:
12124 tmp = fieldFromInstruction(insn, 21, 5);
12125 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12126 tmp = fieldFromInstruction(insn, 11, 5);
12127 if (!Check(S, DecodeFpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12128 return S;
12129 case 257:
12130 tmp = fieldFromInstruction(insn, 21, 5);
12131 if (!Check(S, DecodeFpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12132 tmp = fieldFromInstruction(insn, 16, 5);
12133 if (!Check(S, DecodeFpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12134 tmp = fieldFromInstruction(insn, 11, 5);
12135 if (!Check(S, DecodeFpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12136 tmp = fieldFromInstruction(insn, 9, 2);
12137 if (!Check(S, decodeUImmOperand<2>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12138 return S;
12139 case 258:
12140 tmp = fieldFromInstruction(insn, 21, 5);
12141 if (!Check(S, DecodeFpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12142 tmp = fieldFromInstruction(insn, 16, 5);
12143 if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12144 tmp = fieldFromInstruction(insn, 11, 5);
12145 if (!Check(S, DecodeFpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12146 tmp = fieldFromInstruction(insn, 9, 2);
12147 if (!Check(S, decodeUImmOperand<2>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12148 return S;
12149 case 259:
12150 tmp = fieldFromInstruction(insn, 21, 5);
12151 if (!Check(S, DecodeFpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12152 tmp = fieldFromInstruction(insn, 16, 5);
12153 if (!Check(S, decodeSImmOperand<5>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12154 tmp = fieldFromInstruction(insn, 11, 5);
12155 if (!Check(S, DecodeFpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12156 tmp = fieldFromInstruction(insn, 9, 2);
12157 if (!Check(S, decodeUImmOperand<2>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12158 return S;
12159 case 260:
12160 tmp = fieldFromInstruction(insn, 21, 5);
12161 if (!Check(S, DecodeFpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12162 tmp = fieldFromInstruction(insn, 16, 1);
12163 if (!Check(S, decodeUImmOperand<1>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12164 tmp = fieldFromInstruction(insn, 11, 5);
12165 if (!Check(S, DecodeFpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12166 tmp = fieldFromInstruction(insn, 9, 2);
12167 if (!Check(S, decodeUImmOperand<2>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12168 return S;
12169 case 261:
12170 tmp = fieldFromInstruction(insn, 23, 3);
12171 if (!Check(S, DecodeCRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12172 tmp = fieldFromInstruction(insn, 16, 6);
12173 if (!Check(S, decodeUImmOperand<6>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12174 tmp = fieldFromInstruction(insn, 11, 5);
12175 if (!Check(S, DecodeFpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12176 return S;
12177 case 262:
12178 tmp = fieldFromInstruction(insn, 21, 5);
12179 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12180 tmp = fieldFromInstruction(insn, 21, 5);
12181 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12182 tmp = fieldFromInstruction(insn, 16, 5);
12183 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12184 tmp = fieldFromInstruction(insn, 11, 5);
12185 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12186 return S;
12187 case 263:
12188 tmp = fieldFromInstruction(insn, 23, 3);
12189 if (!Check(S, DecodeCRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12190 tmp = fieldFromInstruction(insn, 16, 7);
12191 if (!Check(S, decodeUImmOperand<7>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12192 tmp = fieldFromInstruction(insn, 11, 5);
12193 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12194 return S;
12195 case 264:
12196 tmp = fieldFromInstruction(insn, 21, 5);
12197 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12198 tmp = fieldFromInstruction(insn, 11, 5);
12199 if (!Check(S, DecodeVFRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12200 return S;
12201 case 265:
12202 tmp = fieldFromInstruction(insn, 21, 5);
12203 if (!Check(S, DecodeVFRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12204 tmp = fieldFromInstruction(insn, 11, 5);
12205 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12206 return S;
12207 case 266:
12208 tmp = fieldFromInstruction(insn, 21, 5);
12209 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12210 tmp = fieldFromInstruction(insn, 16, 5);
12211 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12212 tmp = fieldFromInstruction(insn, 11, 5);
12213 if (!Check(S, DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12214 return S;
12215 case 267:
12216 tmp = fieldFromInstruction(insn, 21, 5);
12217 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12218 tmp = fieldFromInstruction(insn, 16, 1);
12219 if (!Check(S, decodeUImmOperand<1>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12220 tmp = fieldFromInstruction(insn, 11, 5);
12221 if (!Check(S, DecodeVRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12222 tmp = fieldFromInstruction(insn, 9, 2);
12223 if (!Check(S, decodeUImmOperand<2>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12224 return S;
12225 case 268:
12226 tmp = fieldFromInstruction(insn, 23, 3);
12227 if (!Check(S, decodeUImmOperand<3>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12228 tmp = fieldFromInstruction(insn, 12, 4);
12229 if (!Check(S, decodeUImmOperand<4>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12230 tmp = fieldFromInstruction(insn, 16, 1);
12231 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
12232 return S;
12233 case 269:
12234 tmp = fieldFromInstruction(insn, 23, 3);
12235 if (!Check(S, decodeUImmOperand<3>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12236 tmp = fieldFromInstruction(insn, 12, 4);
12237 if (!Check(S, decodeUImmOperand<4>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12238 tmp = fieldFromInstruction(insn, 16, 1);
12239 if (!Check(S, decodeUImmOperand<1>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12240 return S;
12241 case 270:
12242 tmp = fieldFromInstruction(insn, 21, 5);
12243 if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12244 return S;
12245 case 271:
12246 tmp = fieldFromInstruction(insn, 21, 5);
12247 if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12248 tmp = fieldFromInstruction(insn, 11, 3);
12249 if (!Check(S, decodeUImmOperand<3>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12250 return S;
12251 case 272:
12252 tmp = fieldFromInstruction(insn, 21, 5);
12253 if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12254 tmp = fieldFromInstruction(insn, 11, 2);
12255 if (!Check(S, decodeUImmOperand<2>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12256 return S;
12257 case 273:
12258 tmp = fieldFromInstruction(insn, 17, 8);
12259 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
12260 tmp = fieldFromInstruction(insn, 11, 5);
12261 if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12262 tmp = fieldFromInstruction(insn, 25, 1);
12263 if (!Check(S, decodeUImmOperand<1>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12264 tmp = fieldFromInstruction(insn, 16, 1);
12265 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
12266 return S;
12267 case 274:
12268 tmp = fieldFromInstruction(insn, 21, 5);
12269 if (!Check(S, DecodeF4RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12270 tmp = fieldFromInstruction(insn, 16, 5);
12271 if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12272 tmp = fieldFromInstruction(insn, 6, 5);
12273 if (!Check(S, DecodeF4RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12274 tmp = fieldFromInstruction(insn, 11, 5);
12275 if (!Check(S, DecodeF4RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12276 return S;
12277 case 275:
12278 tmp = fieldFromInstruction(insn, 21, 5);
12279 if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12280 tmp = fieldFromInstruction(insn, 16, 5);
12281 if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12282 tmp = fieldFromInstruction(insn, 6, 5);
12283 if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12284 return S;
12285 case 276:
12286 tmp = fieldFromInstruction(insn, 21, 5);
12287 if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12288 tmp = fieldFromInstruction(insn, 16, 5);
12289 if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12290 tmp = fieldFromInstruction(insn, 6, 5);
12291 if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12292 tmp = fieldFromInstruction(insn, 11, 5);
12293 if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12294 return S;
12295 case 277:
12296 tmp = fieldFromInstruction(insn, 21, 5);
12297 if (!Check(S, DecodeSPERCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12298 tmp = fieldFromInstruction(insn, 16, 5);
12299 if (!Check(S, DecodeSPERCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12300 tmp = fieldFromInstruction(insn, 11, 5);
12301 if (!Check(S, DecodeSPERCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12302 return S;
12303 case 278:
12304 tmp = fieldFromInstruction(insn, 21, 5);
12305 if (!Check(S, DecodeSPERCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12306 tmp = fieldFromInstruction(insn, 16, 5);
12307 if (!Check(S, DecodeSPERCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12308 tmp = fieldFromInstruction(insn, 11, 5);
12309 if (!Check(S, decodeUImmOperand<5>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12310 return S;
12311 case 279:
12312 tmp = fieldFromInstruction(insn, 21, 5);
12313 if (!Check(S, DecodeSPERCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12314 tmp = fieldFromInstruction(insn, 16, 5);
12315 if (!Check(S, decodeUImmOperand<5>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12316 tmp = fieldFromInstruction(insn, 11, 5);
12317 if (!Check(S, DecodeSPERCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12318 return S;
12319 case 280:
12320 tmp = fieldFromInstruction(insn, 21, 5);
12321 if (!Check(S, DecodeSPERCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12322 tmp = fieldFromInstruction(insn, 16, 5);
12323 if (!Check(S, DecodeSPERCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12324 return S;
12325 case 281:
12326 tmp = fieldFromInstruction(insn, 21, 5);
12327 if (!Check(S, DecodeSPERCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12328 tmp = fieldFromInstruction(insn, 16, 5);
12329 if (!Check(S, decodeSImmOperand<5>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12330 return S;
12331 case 282:
12332 tmp = fieldFromInstruction(insn, 21, 5);
12333 if (!Check(S, DecodeSPERCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12334 tmp = fieldFromInstruction(insn, 16, 5);
12335 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12336 tmp = fieldFromInstruction(insn, 11, 5);
12337 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12338 return S;
12339 case 283:
12340 tmp = fieldFromInstruction(insn, 23, 3);
12341 if (!Check(S, DecodeCRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12342 tmp = fieldFromInstruction(insn, 16, 5);
12343 if (!Check(S, DecodeSPERCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12344 tmp = fieldFromInstruction(insn, 11, 5);
12345 if (!Check(S, DecodeSPERCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12346 return S;
12347 case 284:
12348 tmp = fieldFromInstruction(insn, 21, 5);
12349 if (!Check(S, DecodeSPERCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12350 tmp = fieldFromInstruction(insn, 16, 5);
12351 if (!Check(S, DecodeSPERCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12352 tmp = fieldFromInstruction(insn, 11, 5);
12353 if (!Check(S, DecodeSPERCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12354 tmp = fieldFromInstruction(insn, 0, 3);
12355 if (!Check(S, DecodeCRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12356 return S;
12357 case 285:
12358 tmp = fieldFromInstruction(insn, 21, 5);
12359 if (!Check(S, DecodeSPERCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12360 tmp = fieldFromInstruction(insn, 11, 5);
12361 if (!Check(S, DecodeSPERCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12362 return S;
12363 case 286:
12364 tmp = fieldFromInstruction(insn, 21, 5);
12365 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12366 tmp = fieldFromInstruction(insn, 11, 5);
12367 if (!Check(S, DecodeSPERCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12368 return S;
12369 case 287:
12370 tmp = fieldFromInstruction(insn, 21, 5);
12371 if (!Check(S, DecodeSPERCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12372 tmp = fieldFromInstruction(insn, 11, 5);
12373 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12374 return S;
12375 case 288:
12376 tmp = fieldFromInstruction(insn, 21, 5);
12377 if (!Check(S, DecodeSPERCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12378 tmp = fieldFromInstruction(insn, 16, 5);
12379 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12380 tmp = fieldFromInstruction(insn, 11, 5);
12381 if (!Check(S, Decodeptr_rc_idx_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12382 return S;
12383 case 289:
12384 tmp = fieldFromInstruction(insn, 21, 5);
12385 if (!Check(S, DecodeSPERCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12386 tmp = fieldFromInstruction(insn, 11, 5);
12387 if (!Check(S, decodeDispSPE8Operand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12388 tmp = fieldFromInstruction(insn, 16, 5);
12389 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12390 return S;
12391 case 290:
12392 tmp = fieldFromInstruction(insn, 21, 5);
12393 if (!Check(S, DecodeSPERCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12394 tmp = fieldFromInstruction(insn, 11, 5);
12395 if (!Check(S, decodeDispSPE2Operand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12396 tmp = fieldFromInstruction(insn, 16, 5);
12397 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12398 return S;
12399 case 291:
12400 tmp = fieldFromInstruction(insn, 21, 5);
12401 if (!Check(S, DecodeSPERCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12402 tmp = fieldFromInstruction(insn, 11, 5);
12403 if (!Check(S, decodeDispSPE4Operand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12404 tmp = fieldFromInstruction(insn, 16, 5);
12405 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12406 return S;
12407 case 292:
12408 tmp = fieldFromInstruction(insn, 21, 5);
12409 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12410 tmp = 0x0;
12411 tmp |= fieldFromInstruction(insn, 0, 16);
12412 tmp |= fieldFromInstruction(insn, 32, 18) << 16;
12413 if (!Check(S, decodeSImmOperand<34>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12414 return S;
12415 case 293:
12416 tmp = fieldFromInstruction(insn, 21, 5);
12417 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12418 tmp = fieldFromInstruction(insn, 16, 5);
12419 if (!Check(S, DecodeGPRC_NOR0RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12420 tmp = 0x0;
12421 tmp |= fieldFromInstruction(insn, 0, 16);
12422 tmp |= fieldFromInstruction(insn, 32, 18) << 16;
12423 if (!Check(S, decodeSImmOperand<34>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12424 return S;
12425 case 294:
12426 tmp = fieldFromInstruction(insn, 21, 5);
12427 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12428 tmp = fieldFromInstruction(insn, 16, 5);
12429 if (!Check(S, decodeImmZeroOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12430 tmp = 0x0;
12431 tmp |= fieldFromInstruction(insn, 0, 16);
12432 tmp |= fieldFromInstruction(insn, 32, 18) << 16;
12433 if (!Check(S, decodeSImmOperand<34>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12434 return S;
12435 case 295:
12436 tmp = fieldFromInstruction(insn, 21, 5);
12437 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12438 tmp = fieldFromInstruction(insn, 16, 5);
12439 if (!Check(S, DecodeGPRC_NOR0RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12440 tmp = 0x0;
12441 tmp |= fieldFromInstruction(insn, 0, 16);
12442 tmp |= fieldFromInstruction(insn, 32, 16) << 16;
12443 if (!Check(S, decodeSImmOperand<32>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12444 return S;
12445 case 296:
12446 tmp = fieldFromInstruction(insn, 21, 5);
12447 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12448 tmp = fieldFromInstruction(insn, 16, 5);
12449 if (!Check(S, decodeImmZeroOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12450 tmp = 0x0;
12451 tmp |= fieldFromInstruction(insn, 0, 16);
12452 tmp |= fieldFromInstruction(insn, 32, 16) << 16;
12453 if (!Check(S, decodeSImmOperand<32>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12454 return S;
12455 case 297:
12456 tmp = 0x0;
12457 tmp |= fieldFromInstruction(insn, 16, 1) << 5;
12458 tmp |= fieldFromInstruction(insn, 21, 5);
12459 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12460 tmp = 0x0;
12461 tmp |= fieldFromInstruction(insn, 16, 1) << 5;
12462 tmp |= fieldFromInstruction(insn, 21, 5);
12463 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12464 tmp = fieldFromInstruction(insn, 17, 1);
12465 if (!Check(S, decodeUImmOperand<1>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12466 tmp = 0x0;
12467 tmp |= fieldFromInstruction(insn, 0, 16);
12468 tmp |= fieldFromInstruction(insn, 32, 16) << 16;
12469 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
12470 return S;
12471 case 298:
12472 tmp = 0x0;
12473 tmp |= fieldFromInstruction(insn, 16, 1) << 5;
12474 tmp |= fieldFromInstruction(insn, 21, 5);
12475 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12476 tmp = 0x0;
12477 tmp |= fieldFromInstruction(insn, 0, 16);
12478 tmp |= fieldFromInstruction(insn, 32, 16) << 16;
12479 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
12480 return S;
12481 case 299:
12482 tmp = fieldFromInstruction(insn, 21, 5);
12483 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12484 tmp = 0x0;
12485 tmp |= fieldFromInstruction(insn, 0, 16);
12486 tmp |= fieldFromInstruction(insn, 32, 18) << 16;
12487 if (!Check(S, decodeSImmOperand<34>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12488 tmp = fieldFromInstruction(insn, 16, 5);
12489 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12490 return S;
12491 case 300:
12492 tmp = fieldFromInstruction(insn, 21, 5);
12493 if (!Check(S, DecodeGPRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12494 tmp = 0x0;
12495 tmp |= fieldFromInstruction(insn, 0, 16);
12496 tmp |= fieldFromInstruction(insn, 32, 18) << 16;
12497 if (!Check(S, decodeSImmOperand<34>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12498 tmp = fieldFromInstruction(insn, 16, 5);
12499 if (!Check(S, decodeImmZeroOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12500 return S;
12501 case 301:
12502 tmp = 0x0;
12503 tmp |= fieldFromInstruction(insn, 0, 1) << 5;
12504 tmp |= fieldFromInstruction(insn, 21, 5);
12505 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12506 tmp = 0x0;
12507 tmp |= fieldFromInstruction(insn, 2, 1) << 5;
12508 tmp |= fieldFromInstruction(insn, 16, 5);
12509 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12510 tmp = 0x0;
12511 tmp |= fieldFromInstruction(insn, 1, 1) << 5;
12512 tmp |= fieldFromInstruction(insn, 11, 5);
12513 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12514 tmp = 0x0;
12515 tmp |= fieldFromInstruction(insn, 3, 1) << 5;
12516 tmp |= fieldFromInstruction(insn, 6, 5);
12517 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12518 tmp = fieldFromInstruction(insn, 32, 3);
12519 if (!Check(S, decodeUImmOperand<3>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12520 return S;
12521 case 302:
12522 tmp = 0x0;
12523 tmp |= fieldFromInstruction(insn, 0, 1) << 5;
12524 tmp |= fieldFromInstruction(insn, 21, 5);
12525 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12526 tmp = 0x0;
12527 tmp |= fieldFromInstruction(insn, 2, 1) << 5;
12528 tmp |= fieldFromInstruction(insn, 16, 5);
12529 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12530 tmp = 0x0;
12531 tmp |= fieldFromInstruction(insn, 1, 1) << 5;
12532 tmp |= fieldFromInstruction(insn, 11, 5);
12533 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12534 tmp = 0x0;
12535 tmp |= fieldFromInstruction(insn, 3, 1) << 5;
12536 tmp |= fieldFromInstruction(insn, 6, 5);
12537 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12538 tmp = fieldFromInstruction(insn, 32, 8);
12539 if (!Check(S, decodeUImmOperand<8>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12540 return S;
12541 case 303:
12542 tmp = 0x0;
12543 tmp |= fieldFromInstruction(insn, 0, 1) << 5;
12544 tmp |= fieldFromInstruction(insn, 21, 5);
12545 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12546 tmp = 0x0;
12547 tmp |= fieldFromInstruction(insn, 2, 1) << 5;
12548 tmp |= fieldFromInstruction(insn, 16, 5);
12549 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12550 tmp = 0x0;
12551 tmp |= fieldFromInstruction(insn, 1, 1) << 5;
12552 tmp |= fieldFromInstruction(insn, 11, 5);
12553 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12554 tmp = 0x0;
12555 tmp |= fieldFromInstruction(insn, 3, 1) << 5;
12556 tmp |= fieldFromInstruction(insn, 6, 5);
12557 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12558 tmp = fieldFromInstruction(insn, 4, 1);
12559 if (!Check(S, decodeUImmOperand<1>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12560 return S;
12561 case 304:
12562 tmp = fieldFromInstruction(insn, 21, 5);
12563 if (!Check(S, DecodeVFRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12564 tmp = 0x0;
12565 tmp |= fieldFromInstruction(insn, 0, 16);
12566 tmp |= fieldFromInstruction(insn, 32, 18) << 16;
12567 if (!Check(S, decodeSImmOperand<34>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12568 tmp = fieldFromInstruction(insn, 16, 5);
12569 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12570 return S;
12571 case 305:
12572 tmp = fieldFromInstruction(insn, 21, 5);
12573 if (!Check(S, DecodeVFRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12574 tmp = 0x0;
12575 tmp |= fieldFromInstruction(insn, 0, 16);
12576 tmp |= fieldFromInstruction(insn, 32, 18) << 16;
12577 if (!Check(S, decodeSImmOperand<34>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12578 tmp = fieldFromInstruction(insn, 16, 5);
12579 if (!Check(S, decodeImmZeroOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12580 return S;
12581 case 306:
12582 tmp = fieldFromInstruction(insn, 21, 5);
12583 if (!Check(S, DecodeF4RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12584 tmp = 0x0;
12585 tmp |= fieldFromInstruction(insn, 0, 16);
12586 tmp |= fieldFromInstruction(insn, 32, 18) << 16;
12587 if (!Check(S, decodeSImmOperand<34>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12588 tmp = fieldFromInstruction(insn, 16, 5);
12589 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12590 return S;
12591 case 307:
12592 tmp = fieldFromInstruction(insn, 21, 5);
12593 if (!Check(S, DecodeF4RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12594 tmp = 0x0;
12595 tmp |= fieldFromInstruction(insn, 0, 16);
12596 tmp |= fieldFromInstruction(insn, 32, 18) << 16;
12597 if (!Check(S, decodeSImmOperand<34>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12598 tmp = fieldFromInstruction(insn, 16, 5);
12599 if (!Check(S, decodeImmZeroOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12600 return S;
12601 case 308:
12602 tmp = fieldFromInstruction(insn, 21, 6);
12603 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12604 tmp = 0x0;
12605 tmp |= fieldFromInstruction(insn, 0, 16);
12606 tmp |= fieldFromInstruction(insn, 32, 18) << 16;
12607 if (!Check(S, decodeSImmOperand<34>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12608 tmp = fieldFromInstruction(insn, 16, 5);
12609 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12610 return S;
12611 case 309:
12612 tmp = fieldFromInstruction(insn, 21, 6);
12613 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12614 tmp = 0x0;
12615 tmp |= fieldFromInstruction(insn, 0, 16);
12616 tmp |= fieldFromInstruction(insn, 32, 18) << 16;
12617 if (!Check(S, decodeSImmOperand<34>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12618 tmp = fieldFromInstruction(insn, 16, 5);
12619 if (!Check(S, decodeImmZeroOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12620 return S;
12621 case 310:
12622 tmp = fieldFromInstruction(insn, 21, 5);
12623 if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12624 tmp = 0x0;
12625 tmp |= fieldFromInstruction(insn, 0, 16);
12626 tmp |= fieldFromInstruction(insn, 32, 18) << 16;
12627 if (!Check(S, decodeSImmOperand<34>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12628 tmp = fieldFromInstruction(insn, 16, 5);
12629 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12630 return S;
12631 case 311:
12632 tmp = fieldFromInstruction(insn, 21, 5);
12633 if (!Check(S, DecodeF8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12634 tmp = 0x0;
12635 tmp |= fieldFromInstruction(insn, 0, 16);
12636 tmp |= fieldFromInstruction(insn, 32, 18) << 16;
12637 if (!Check(S, decodeSImmOperand<34>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12638 tmp = fieldFromInstruction(insn, 16, 5);
12639 if (!Check(S, decodeImmZeroOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12640 return S;
12641 case 312:
12642 tmp = fieldFromInstruction(insn, 21, 5);
12643 if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12644 tmp = 0x0;
12645 tmp |= fieldFromInstruction(insn, 0, 16);
12646 tmp |= fieldFromInstruction(insn, 32, 18) << 16;
12647 if (!Check(S, decodeSImmOperand<34>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12648 tmp = fieldFromInstruction(insn, 16, 5);
12649 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12650 return S;
12651 case 313:
12652 tmp = fieldFromInstruction(insn, 21, 5);
12653 if (!Check(S, DecodeG8RCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12654 tmp = 0x0;
12655 tmp |= fieldFromInstruction(insn, 0, 16);
12656 tmp |= fieldFromInstruction(insn, 32, 18) << 16;
12657 if (!Check(S, decodeSImmOperand<34>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12658 tmp = fieldFromInstruction(insn, 16, 5);
12659 if (!Check(S, decodeImmZeroOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12660 return S;
12661 case 314:
12662 tmp = 0x0;
12663 tmp |= fieldFromInstruction(insn, 21, 1) << 4;
12664 tmp |= fieldFromInstruction(insn, 22, 4);
12665 if (!Check(S, DecodeVSRpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12666 tmp = 0x0;
12667 tmp |= fieldFromInstruction(insn, 0, 16);
12668 tmp |= fieldFromInstruction(insn, 32, 18) << 16;
12669 if (!Check(S, decodeSImmOperand<34>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12670 tmp = fieldFromInstruction(insn, 16, 5);
12671 if (!Check(S, Decodeptr_rc_nor0_by_hwmodeRegClassByHwMode(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12672 return S;
12673 case 315:
12674 tmp = 0x0;
12675 tmp |= fieldFromInstruction(insn, 21, 1) << 4;
12676 tmp |= fieldFromInstruction(insn, 22, 4);
12677 if (!Check(S, DecodeVSRpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12678 tmp = 0x0;
12679 tmp |= fieldFromInstruction(insn, 0, 16);
12680 tmp |= fieldFromInstruction(insn, 32, 18) << 16;
12681 if (!Check(S, decodeSImmOperand<34>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12682 tmp = fieldFromInstruction(insn, 16, 5);
12683 if (!Check(S, decodeImmZeroOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12684 return S;
12685 case 316:
12686 tmp = fieldFromInstruction(insn, 23, 3);
12687 if (!Check(S, DecodeACCRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12688 tmp = fieldFromInstruction(insn, 23, 3);
12689 if (!Check(S, DecodeACCRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12690 tmp = 0x0;
12691 tmp |= fieldFromInstruction(insn, 2, 1) << 5;
12692 tmp |= fieldFromInstruction(insn, 16, 5);
12693 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12694 tmp = 0x0;
12695 tmp |= fieldFromInstruction(insn, 1, 1) << 5;
12696 tmp |= fieldFromInstruction(insn, 11, 5);
12697 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12698 tmp = fieldFromInstruction(insn, 36, 4);
12699 if (!Check(S, decodeUImmOperand<4>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12700 tmp = fieldFromInstruction(insn, 32, 4);
12701 if (!Check(S, decodeUImmOperand<4>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12702 tmp = fieldFromInstruction(insn, 44, 4);
12703 if (!Check(S, decodeUImmOperand<4>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12704 return S;
12705 case 317:
12706 tmp = fieldFromInstruction(insn, 23, 3);
12707 if (!Check(S, DecodeACCRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12708 tmp = 0x0;
12709 tmp |= fieldFromInstruction(insn, 2, 1) << 5;
12710 tmp |= fieldFromInstruction(insn, 16, 5);
12711 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12712 tmp = 0x0;
12713 tmp |= fieldFromInstruction(insn, 1, 1) << 5;
12714 tmp |= fieldFromInstruction(insn, 11, 5);
12715 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12716 tmp = fieldFromInstruction(insn, 36, 4);
12717 if (!Check(S, decodeUImmOperand<4>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12718 tmp = fieldFromInstruction(insn, 32, 4);
12719 if (!Check(S, decodeUImmOperand<4>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12720 tmp = fieldFromInstruction(insn, 44, 4);
12721 if (!Check(S, decodeUImmOperand<4>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12722 return S;
12723 case 318:
12724 tmp = fieldFromInstruction(insn, 23, 3);
12725 if (!Check(S, DecodeDMRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12726 tmp = fieldFromInstruction(insn, 23, 3);
12727 if (!Check(S, DecodeDMRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12728 tmp = 0x0;
12729 tmp |= fieldFromInstruction(insn, 2, 1) << 4;
12730 tmp |= fieldFromInstruction(insn, 17, 4);
12731 if (!Check(S, DecodeVSRpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12732 tmp = 0x0;
12733 tmp |= fieldFromInstruction(insn, 1, 1) << 5;
12734 tmp |= fieldFromInstruction(insn, 11, 5);
12735 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12736 tmp = fieldFromInstruction(insn, 36, 8);
12737 if (!Check(S, decodeUImmOperand<8>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12738 tmp = fieldFromInstruction(insn, 32, 4);
12739 if (!Check(S, decodeUImmOperand<4>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12740 tmp = fieldFromInstruction(insn, 44, 4);
12741 if (!Check(S, decodeUImmOperand<4>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12742 return S;
12743 case 319:
12744 tmp = fieldFromInstruction(insn, 23, 3);
12745 if (!Check(S, DecodeDMRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12746 tmp = 0x0;
12747 tmp |= fieldFromInstruction(insn, 2, 1) << 4;
12748 tmp |= fieldFromInstruction(insn, 17, 4);
12749 if (!Check(S, DecodeVSRpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12750 tmp = 0x0;
12751 tmp |= fieldFromInstruction(insn, 1, 1) << 5;
12752 tmp |= fieldFromInstruction(insn, 11, 5);
12753 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12754 tmp = fieldFromInstruction(insn, 36, 8);
12755 if (!Check(S, decodeUImmOperand<8>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12756 tmp = fieldFromInstruction(insn, 32, 4);
12757 if (!Check(S, decodeUImmOperand<4>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12758 tmp = fieldFromInstruction(insn, 44, 4);
12759 if (!Check(S, decodeUImmOperand<4>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12760 return S;
12761 case 320:
12762 tmp = fieldFromInstruction(insn, 23, 3);
12763 if (!Check(S, DecodeACCRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12764 tmp = fieldFromInstruction(insn, 23, 3);
12765 if (!Check(S, DecodeACCRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12766 tmp = 0x0;
12767 tmp |= fieldFromInstruction(insn, 2, 1) << 5;
12768 tmp |= fieldFromInstruction(insn, 16, 5);
12769 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12770 tmp = 0x0;
12771 tmp |= fieldFromInstruction(insn, 1, 1) << 5;
12772 tmp |= fieldFromInstruction(insn, 11, 5);
12773 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12774 tmp = fieldFromInstruction(insn, 36, 4);
12775 if (!Check(S, decodeUImmOperand<4>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12776 tmp = fieldFromInstruction(insn, 32, 4);
12777 if (!Check(S, decodeUImmOperand<4>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12778 tmp = fieldFromInstruction(insn, 46, 2);
12779 if (!Check(S, decodeUImmOperand<2>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12780 return S;
12781 case 321:
12782 tmp = fieldFromInstruction(insn, 23, 3);
12783 if (!Check(S, DecodeACCRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12784 tmp = 0x0;
12785 tmp |= fieldFromInstruction(insn, 2, 1) << 5;
12786 tmp |= fieldFromInstruction(insn, 16, 5);
12787 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12788 tmp = 0x0;
12789 tmp |= fieldFromInstruction(insn, 1, 1) << 5;
12790 tmp |= fieldFromInstruction(insn, 11, 5);
12791 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12792 tmp = fieldFromInstruction(insn, 36, 4);
12793 if (!Check(S, decodeUImmOperand<4>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12794 tmp = fieldFromInstruction(insn, 32, 4);
12795 if (!Check(S, decodeUImmOperand<4>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12796 tmp = fieldFromInstruction(insn, 46, 2);
12797 if (!Check(S, decodeUImmOperand<2>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12798 return S;
12799 case 322:
12800 tmp = fieldFromInstruction(insn, 23, 3);
12801 if (!Check(S, DecodeACCRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12802 tmp = fieldFromInstruction(insn, 23, 3);
12803 if (!Check(S, DecodeACCRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12804 tmp = 0x0;
12805 tmp |= fieldFromInstruction(insn, 2, 1) << 5;
12806 tmp |= fieldFromInstruction(insn, 16, 5);
12807 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12808 tmp = 0x0;
12809 tmp |= fieldFromInstruction(insn, 1, 1) << 5;
12810 tmp |= fieldFromInstruction(insn, 11, 5);
12811 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12812 tmp = fieldFromInstruction(insn, 36, 4);
12813 if (!Check(S, decodeUImmOperand<4>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12814 tmp = fieldFromInstruction(insn, 32, 4);
12815 if (!Check(S, decodeUImmOperand<4>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12816 return S;
12817 case 323:
12818 tmp = fieldFromInstruction(insn, 23, 3);
12819 if (!Check(S, DecodeACCRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12820 tmp = 0x0;
12821 tmp |= fieldFromInstruction(insn, 2, 1) << 5;
12822 tmp |= fieldFromInstruction(insn, 16, 5);
12823 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12824 tmp = 0x0;
12825 tmp |= fieldFromInstruction(insn, 1, 1) << 5;
12826 tmp |= fieldFromInstruction(insn, 11, 5);
12827 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12828 tmp = fieldFromInstruction(insn, 36, 4);
12829 if (!Check(S, decodeUImmOperand<4>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12830 tmp = fieldFromInstruction(insn, 32, 4);
12831 if (!Check(S, decodeUImmOperand<4>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12832 return S;
12833 case 324:
12834 tmp = fieldFromInstruction(insn, 23, 3);
12835 if (!Check(S, DecodeACCRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12836 tmp = fieldFromInstruction(insn, 23, 3);
12837 if (!Check(S, DecodeACCRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12838 tmp = 0x0;
12839 tmp |= fieldFromInstruction(insn, 2, 1) << 5;
12840 tmp |= fieldFromInstruction(insn, 16, 5);
12841 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12842 tmp = 0x0;
12843 tmp |= fieldFromInstruction(insn, 1, 1) << 5;
12844 tmp |= fieldFromInstruction(insn, 11, 5);
12845 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12846 tmp = fieldFromInstruction(insn, 36, 4);
12847 if (!Check(S, decodeUImmOperand<4>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12848 tmp = fieldFromInstruction(insn, 32, 4);
12849 if (!Check(S, decodeUImmOperand<4>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12850 tmp = fieldFromInstruction(insn, 40, 8);
12851 if (!Check(S, decodeUImmOperand<8>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12852 return S;
12853 case 325:
12854 tmp = fieldFromInstruction(insn, 23, 3);
12855 if (!Check(S, DecodeACCRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12856 tmp = 0x0;
12857 tmp |= fieldFromInstruction(insn, 2, 1) << 5;
12858 tmp |= fieldFromInstruction(insn, 16, 5);
12859 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12860 tmp = 0x0;
12861 tmp |= fieldFromInstruction(insn, 1, 1) << 5;
12862 tmp |= fieldFromInstruction(insn, 11, 5);
12863 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12864 tmp = fieldFromInstruction(insn, 36, 4);
12865 if (!Check(S, decodeUImmOperand<4>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12866 tmp = fieldFromInstruction(insn, 32, 4);
12867 if (!Check(S, decodeUImmOperand<4>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12868 tmp = fieldFromInstruction(insn, 40, 8);
12869 if (!Check(S, decodeUImmOperand<8>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12870 return S;
12871 case 326:
12872 tmp = fieldFromInstruction(insn, 23, 3);
12873 if (!Check(S, DecodeACCRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12874 tmp = fieldFromInstruction(insn, 23, 3);
12875 if (!Check(S, DecodeACCRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12876 tmp = 0x0;
12877 tmp |= fieldFromInstruction(insn, 2, 1) << 5;
12878 tmp |= fieldFromInstruction(insn, 16, 5);
12879 if (!Check(S, decodeVSRpEvenOperands(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12880 tmp = 0x0;
12881 tmp |= fieldFromInstruction(insn, 1, 1) << 5;
12882 tmp |= fieldFromInstruction(insn, 11, 5);
12883 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12884 tmp = fieldFromInstruction(insn, 36, 4);
12885 if (!Check(S, decodeUImmOperand<4>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12886 tmp = fieldFromInstruction(insn, 34, 2);
12887 if (!Check(S, decodeUImmOperand<2>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12888 return S;
12889 case 327:
12890 tmp = fieldFromInstruction(insn, 23, 3);
12891 if (!Check(S, DecodeACCRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12892 tmp = 0x0;
12893 tmp |= fieldFromInstruction(insn, 2, 1) << 5;
12894 tmp |= fieldFromInstruction(insn, 16, 5);
12895 if (!Check(S, decodeVSRpEvenOperands(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12896 tmp = 0x0;
12897 tmp |= fieldFromInstruction(insn, 1, 1) << 5;
12898 tmp |= fieldFromInstruction(insn, 11, 5);
12899 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12900 tmp = fieldFromInstruction(insn, 36, 4);
12901 if (!Check(S, decodeUImmOperand<4>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12902 tmp = fieldFromInstruction(insn, 34, 2);
12903 if (!Check(S, decodeUImmOperand<2>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12904 return S;
12905 case 328:
12906 tmp = fieldFromInstruction(insn, 23, 3);
12907 if (!Check(S, DecodeDMRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12908 tmp = fieldFromInstruction(insn, 23, 3);
12909 if (!Check(S, DecodeDMRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12910 tmp = 0x0;
12911 tmp |= fieldFromInstruction(insn, 2, 1) << 4;
12912 tmp |= fieldFromInstruction(insn, 17, 4);
12913 if (!Check(S, DecodeVSRpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12914 tmp = 0x0;
12915 tmp |= fieldFromInstruction(insn, 1, 1) << 5;
12916 tmp |= fieldFromInstruction(insn, 11, 5);
12917 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12918 tmp = fieldFromInstruction(insn, 36, 8);
12919 if (!Check(S, decodeUImmOperand<8>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12920 tmp = fieldFromInstruction(insn, 32, 4);
12921 if (!Check(S, decodeUImmOperand<4>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12922 tmp = fieldFromInstruction(insn, 46, 2);
12923 if (!Check(S, decodeUImmOperand<2>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12924 return S;
12925 case 329:
12926 tmp = fieldFromInstruction(insn, 23, 3);
12927 if (!Check(S, DecodeDMRRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12928 tmp = 0x0;
12929 tmp |= fieldFromInstruction(insn, 2, 1) << 4;
12930 tmp |= fieldFromInstruction(insn, 17, 4);
12931 if (!Check(S, DecodeVSRpRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12932 tmp = 0x0;
12933 tmp |= fieldFromInstruction(insn, 1, 1) << 5;
12934 tmp |= fieldFromInstruction(insn, 11, 5);
12935 if (!Check(S, DecodeVSRCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12936 tmp = fieldFromInstruction(insn, 36, 8);
12937 if (!Check(S, decodeUImmOperand<8>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12938 tmp = fieldFromInstruction(insn, 32, 4);
12939 if (!Check(S, decodeUImmOperand<4>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12940 tmp = fieldFromInstruction(insn, 46, 2);
12941 if (!Check(S, decodeUImmOperand<2>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
12942 return S;
12943 }
12944}
12945
12946template <typename InsnType>
12947static DecodeStatus decodeInstruction(const uint8_t DecodeTable[], MCInst &MI,
12948 InsnType insn, uint64_t Address,
12949 const MCDisassembler *DisAsm,
12950 const MCSubtargetInfo &STI) {
12951 const uint8_t *Ptr = DecodeTable;
12952
12953 SmallVector<const uint8_t *, 8> ScopeStack;
12954 DecodeStatus S = MCDisassembler::Success;
12955 while (true) {
12956 ptrdiff_t Loc = Ptr - DecodeTable;
12957 const uint8_t DecoderOp = *Ptr++;
12958 switch (DecoderOp) {
12959 default:
12960 errs() << Loc << ": Unexpected decode table opcode: "
12961 << (int)DecoderOp << '\n';
12962 return MCDisassembler::Fail;
12963 case OPC_Scope: {
12964 unsigned NumToSkip = decodeULEB128AndIncUnsafe(p&: Ptr);
12965 const uint8_t *SkipTo = Ptr + NumToSkip;
12966 ScopeStack.push_back(Elt: SkipTo);
12967 LLVM_DEBUG(dbgs() << Loc << ": OPC_Scope(" << SkipTo - DecodeTable
12968 << ")\n");
12969 continue;
12970 }
12971 case OPC_SwitchField: {
12972 // Decode the start value.
12973 unsigned Start = decodeULEB128AndIncUnsafe(p&: Ptr);
12974 unsigned Len = *Ptr++;
12975 uint64_t FieldValue = fieldFromInstruction(insn, Start, Len);
12976 uint64_t CaseValue;
12977 unsigned CaseSize;
12978 while (true) {
12979 CaseValue = decodeULEB128AndIncUnsafe(p&: Ptr);
12980 CaseSize = decodeULEB128AndIncUnsafe(p&: Ptr);
12981 if (FieldValue == CaseValue || !CaseSize)
12982 break;
12983 Ptr += CaseSize;
12984 }
12985 if (FieldValue == CaseValue) {
12986 LLVM_DEBUG(dbgs() << Loc << ": OPC_SwitchField(" << Start << ", " << Len
12987 << "): " << FieldValue << '\n');
12988 continue;
12989 }
12990 break;
12991 }
12992 case OPC_CheckField: {
12993 // Decode the start value.
12994 unsigned Start = decodeULEB128AndIncUnsafe(p&: Ptr);
12995 unsigned Len = *Ptr;
12996 uint64_t FieldValue = fieldFromInstruction(insn, Start, Len);
12997 // Decode the field value.
12998 unsigned PtrLen = 0;
12999 uint64_t ExpectedValue = decodeULEB128(p: ++Ptr, n: &PtrLen);
13000 Ptr += PtrLen;
13001 bool Failed = ExpectedValue != FieldValue;
13002
13003 LLVM_DEBUG(dbgs() << Loc << ": OPC_CheckField(" << Start << ", " << Len
13004 << ", " << ExpectedValue << "): FieldValue = "
13005 << FieldValue << ", ExpectedValue = " << ExpectedValue
13006 << ": " << (Failed ? "FAIL, " : "PASS\n"););
13007 if (!Failed)
13008 continue;
13009 break;
13010 }
13011 case OPC_Decode: {
13012 // Decode the Opcode value.
13013 unsigned Opc = decodeULEB128AndIncUnsafe(p&: Ptr);
13014 unsigned DecodeIdx = decodeULEB128AndIncUnsafe(p&: Ptr);
13015
13016 MI.clear();
13017 MI.setOpcode(Opc);
13018 bool DecodeComplete;
13019 S = decodeToMCInst(DecodeIdx, S, insn, MI, Address, DisAsm,
13020 DecodeComplete);
13021 LLVM_DEBUG(dbgs() << Loc << ": OPC_Decode: opcode " << Opc
13022 << ", using decoder " << DecodeIdx << ": "
13023 << (S ? "PASS, " : "FAIL, "));
13024
13025 if (DecodeComplete) {
13026 LLVM_DEBUG(dbgs() << "decoding complete\n");
13027 return S;
13028 }
13029 assert(S == MCDisassembler::Fail);
13030 // Reset decode status. This also drops a SoftFail status that could be
13031 // set before the decode attempt.
13032 S = MCDisassembler::Success;
13033 break;
13034 }
13035 }
13036 if (ScopeStack.empty()) {
13037 LLVM_DEBUG(dbgs() << "returning Fail\n");
13038 return MCDisassembler::Fail;
13039 }
13040 Ptr = ScopeStack.pop_back_val();
13041 LLVM_DEBUG(dbgs() << "continuing at " << Ptr - DecodeTable << '\n');
13042 }
13043 llvm_unreachable("bogosity detected in disassembler state machine!");
13044}
13045
13046
13047} // namespace
13048