1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Register Bank Source Fragments *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_REGBANK_DECLARATIONS
10#undef GET_REGBANK_DECLARATIONS
11
12namespace llvm::PPC {
13
14enum : unsigned {
15 InvalidRegBankID = ~0u,
16 CRRegBankID = 0,
17 FPRRegBankID = 1,
18 GPRRegBankID = 2,
19 VECRegBankID = 3,
20 NumRegisterBanks,
21};
22
23} // namespace llvm::PPC
24
25#endif // GET_REGBANK_DECLARATIONS
26
27#ifdef GET_TARGET_REGBANK_CLASS
28#undef GET_TARGET_REGBANK_CLASS
29
30private:
31 static const RegisterBank *RegBanks[];
32 static const unsigned Sizes[];
33
34public:
35 const RegisterBank &getRegBankFromRegClass(const TargetRegisterClass &RC, LLT Ty) const override;
36protected:
37 PPCGenRegisterBankInfo(unsigned HwMode = 0);
38
39
40#endif // GET_TARGET_REGBANK_CLASS
41
42#ifdef GET_TARGET_REGBANK_IMPL
43#undef GET_TARGET_REGBANK_IMPL
44
45namespace llvm {
46
47namespace PPC {
48
49const uint32_t CRRegBankCoverageData[] = {
50 // 0-31
51 (1u << (PPC::CRRCRegClassID - 0)) |
52 (1u << (PPC::CRBITRCRegClassID - 0)) |
53 0,
54 // 32-63
55 0,
56};
57const uint32_t FPRRegBankCoverageData[] = {
58 // 0-31
59 (1u << (PPC::VSSRCRegClassID - 0)) |
60 (1u << (PPC::F4RCRegClassID - 0)) |
61 (1u << (PPC::F8RCRegClassID - 0)) |
62 (1u << (PPC::SPILLTOVSRRC_and_F4RCRegClassID - 0)) |
63 (1u << (PPC::VSFRCRegClassID - 0)) |
64 (1u << (PPC::SPILLTOVSRRC_and_VSFRCRegClassID - 0)) |
65 (1u << (PPC::SPILLTOVSRRC_and_VFRCRegClassID - 0)) |
66 (1u << (PPC::VFRCRegClassID - 0)) |
67 0,
68 // 32-63
69 0,
70};
71const uint32_t GPRRegBankCoverageData[] = {
72 // 0-31
73 (1u << (PPC::G8RCRegClassID - 0)) |
74 (1u << (PPC::GPRCRegClassID - 0)) |
75 (1u << (PPC::G8RC_and_G8RC_NOX0RegClassID - 0)) |
76 (1u << (PPC::GPRC_NOR0RegClassID - 0)) |
77 (1u << (PPC::GPRC_and_GPRC_NOR0RegClassID - 0)) |
78 (1u << (PPC::G8RC_NOX0RegClassID - 0)) |
79 0,
80 // 32-63
81 0,
82};
83const uint32_t VECRegBankCoverageData[] = {
84 // 0-31
85 (1u << (PPC::VSRCRegClassID - 0)) |
86 (1u << (PPC::VSSRCRegClassID - 0)) |
87 (1u << (PPC::VSFRCRegClassID - 0)) |
88 (1u << (PPC::VSRC_with_sub_64_in_SPILLTOVSRRCRegClassID - 0)) |
89 (1u << (PPC::SPILLTOVSRRCRegClassID - 0)) |
90 (1u << (PPC::SPILLTOVSRRC_and_VSFRCRegClassID - 0)) |
91 (1u << (PPC::VFRCRegClassID - 0)) |
92 (1u << (PPC::SPILLTOVSRRC_and_VFRCRegClassID - 0)) |
93 (1u << (PPC::F4RCRegClassID - 0)) |
94 (1u << (PPC::F8RCRegClassID - 0)) |
95 (1u << (PPC::SPILLTOVSRRC_and_F4RCRegClassID - 0)) |
96 (1u << (PPC::VRRCRegClassID - 0)) |
97 0,
98 // 32-63
99 (1u << (PPC::VRRC_with_sub_64_in_SPILLTOVSRRCRegClassID - 32)) |
100 (1u << (PPC::VSLRC_with_sub_64_in_SPILLTOVSRRCRegClassID - 32)) |
101 (1u << (PPC::VSLRCRegClassID - 32)) |
102 0,
103};
104
105constexpr RegisterBank CRRegBank(/* ID */ PPC::CRRegBankID, /* Name */ "CR", /* CoveredRegClasses */ CRRegBankCoverageData, /* NumRegClasses */ 56);
106constexpr RegisterBank FPRRegBank(/* ID */ PPC::FPRRegBankID, /* Name */ "FPR", /* CoveredRegClasses */ FPRRegBankCoverageData, /* NumRegClasses */ 56);
107constexpr RegisterBank GPRRegBank(/* ID */ PPC::GPRRegBankID, /* Name */ "GPR", /* CoveredRegClasses */ GPRRegBankCoverageData, /* NumRegClasses */ 56);
108constexpr RegisterBank VECRegBank(/* ID */ PPC::VECRegBankID, /* Name */ "VEC", /* CoveredRegClasses */ VECRegBankCoverageData, /* NumRegClasses */ 56);
109
110} // namespace PPC
111
112const RegisterBank *PPCGenRegisterBankInfo::RegBanks[] = {
113 &PPC::CRRegBank,
114 &PPC::FPRRegBank,
115 &PPC::GPRRegBank,
116 &PPC::VECRegBank,
117};
118
119const unsigned PPCGenRegisterBankInfo::Sizes[] = {
120 // Mode = 0 (Default)
121 32,
122 64,
123 64,
124 128,
125 // Mode = 1 (PPC64)
126 32,
127 64,
128 64,
129 128,
130};
131
132PPCGenRegisterBankInfo::PPCGenRegisterBankInfo(unsigned HwMode)
133 : RegisterBankInfo(RegBanks, PPC::NumRegisterBanks, Sizes, HwMode) {
134 // Assert that RegBank indices match their ID's
135#ifndef NDEBUG
136 for (auto RB : enumerate(RegBanks))
137 assert(RB.index() == RB.value()->getID() && "Index != ID");
138#endif // NDEBUG
139}
140
141const RegisterBank &
142PPCGenRegisterBankInfo::getRegBankFromRegClass(const TargetRegisterClass &RC, LLT) const {
143 constexpr uint32_t InvalidRegBankID = uint32_t(PPC::InvalidRegBankID) & 15;
144 static const uint32_t RegClass2RegBank[5] = {
145 (uint32_t(InvalidRegBankID) << 0) | // VSSRCRegClassID
146 (uint32_t(PPC::GPRRegBankID) << 4) | // GPRCRegClassID
147 (uint32_t(PPC::GPRRegBankID) << 8) | // GPRC_NOR0RegClassID
148 (uint32_t(PPC::GPRRegBankID) << 12) | // GPRC_and_GPRC_NOR0RegClassID
149 (uint32_t(PPC::CRRegBankID) << 16) | // CRBITRCRegClassID
150 (uint32_t(InvalidRegBankID) << 20) | // F4RCRegClassID
151 (uint32_t(InvalidRegBankID) << 24) |
152 (uint32_t(PPC::CRRegBankID) << 28), // CRRCRegClassID
153 (uint32_t(InvalidRegBankID) << 0) |
154 (uint32_t(InvalidRegBankID) << 4) |
155 (uint32_t(InvalidRegBankID) << 8) |
156 (uint32_t(InvalidRegBankID) << 12) |
157 (uint32_t(PPC::VECRegBankID) << 16) | // SPILLTOVSRRCRegClassID
158 (uint32_t(InvalidRegBankID) << 20) | // VSFRCRegClassID
159 (uint32_t(PPC::GPRRegBankID) << 24) | // G8RCRegClassID
160 (uint32_t(PPC::GPRRegBankID) << 28), // G8RC_NOX0RegClassID
161 (uint32_t(InvalidRegBankID) << 0) | // SPILLTOVSRRC_and_VSFRCRegClassID
162 (uint32_t(PPC::GPRRegBankID) << 4) | // G8RC_and_G8RC_NOX0RegClassID
163 (uint32_t(InvalidRegBankID) << 8) | // F8RCRegClassID
164 (uint32_t(InvalidRegBankID) << 12) |
165 (uint32_t(InvalidRegBankID) << 16) |
166 (uint32_t(InvalidRegBankID) << 20) |
167 (uint32_t(InvalidRegBankID) << 24) | // VFRCRegClassID
168 (uint32_t(InvalidRegBankID) << 28),
169 (uint32_t(InvalidRegBankID) << 0) | // SPILLTOVSRRC_and_VFRCRegClassID
170 (uint32_t(InvalidRegBankID) << 4) | // SPILLTOVSRRC_and_F4RCRegClassID
171 (uint32_t(InvalidRegBankID) << 8) |
172 (uint32_t(InvalidRegBankID) << 12) |
173 (uint32_t(InvalidRegBankID) << 16) |
174 (uint32_t(PPC::VECRegBankID) << 20) | // VSRCRegClassID
175 (uint32_t(PPC::VECRegBankID) << 24) | // VSRC_with_sub_64_in_SPILLTOVSRRCRegClassID
176 (uint32_t(PPC::VECRegBankID) << 28), // VRRCRegClassID
177 (uint32_t(PPC::VECRegBankID) << 0) | // VSLRCRegClassID
178 (uint32_t(PPC::VECRegBankID) << 4) | // VRRC_with_sub_64_in_SPILLTOVSRRCRegClassID
179 (uint32_t(InvalidRegBankID) << 8) |
180 (uint32_t(InvalidRegBankID) << 12) |
181 (uint32_t(InvalidRegBankID) << 16) |
182 (uint32_t(PPC::VECRegBankID) << 20) // VSLRC_with_sub_64_in_SPILLTOVSRRCRegClassID
183 };
184 const unsigned RegClassID = RC.getID();
185 if (LLVM_LIKELY(RegClassID < 38)) {
186 unsigned RegBankID = (RegClass2RegBank[RegClassID / 8] >> ((RegClassID % 8) * 4)) & 15;
187 if (RegBankID != InvalidRegBankID)
188 return getRegBank(RegBankID);
189 }
190 llvm_unreachable(llvm::Twine("Target needs to handle register class ID 0x").concat(llvm::Twine::utohexstr(RegClassID)).str().c_str());
191}
192
193} // namespace llvm
194
195#endif // GET_TARGET_REGBANK_IMPL
196
197